Adding RISC-V Core to ODIN

[remi-boivin]

Summary

Integrate a RISC-V core into the ODIN neuromorphic processor to enhance its computational capabilities and provide a versatile control mechanism for handling tasks that are not efficiently managed by the neuromorphic components alone.

Motivation

The inclusion of a RISC-V core within the ODIN architecture offers several benefits:

• Versatile Control and Computation: A RISC-V core can handle general-purpose computation and control tasks, enabling more complex and varied workloads.
• Standardized Instruction Set: Utilizing the RISC-V ISA ensures compatibility with a wide range of existing software tools and libraries, facilitating easier development and integration.
• Enhanced Flexibility: The RISC-V core can manage tasks such as data preprocessing, control flow, and interfacing with external components, complementing the neuromorphic processing capabilities of ODIN.

Implementation Steps

• Add RISC-V Core: Integrate an open-source RISC-V core (such as the Rocket core or PicoRV32) into the ODIN hardware design.
• Interface Design: Implement the memory-mapped or custom interface for communication between the RISC-V core and neuromorphic components.
• Testing and Validation: Simulate the integrated system to verify functionality, followed by FPGA prototyping for hardware validation.
• Software Support: Develop or adapt existing software tools to support the new hardware configuration, ensuring seamless operation and programming.

Detailed Design

Integration Approach

To be able to communicate between the RISC-V and the neuromorphic processor we need to implement a communication mechanism.

• Memory-Mapped Interface: Establish a memory-mapped I/O interface between the RISC-V core and the neuromorphic processor components. This allows the RISC-V core to read from and write to neuromorphic components using standard load and store instructions.

• Custom Interface: Optionally, design a custom interface for high-speed communication and specific control signals tailored to the needs of the neuromorphic processor.

The first solution seams simpler but the second solution may give better performance. The subject may need more research.

Example Interface Design

Memory-Mapped Interface

Define specific memory addresses for communication between the RISC-V core and the neuromorphic processor:

• Control Register (Write): Address 0x80000000
• Data Register (Read): Address 0x80000004

Custom Interface Design

The custom interface will use a set of dedicated control and data signals for communication between the RISC-V core and the neuromorphic processor. These signals will include:

• Control signals for starting, stopping, and configuring neuromorphic computations.
• Data buses for transferring input data to the neuromorphic processor and reading output data.
• Status signals to monitor the state of the neuromorphic processor.

Example Custom Interface Signals

• Control Signals

  • start: Initiates neuromorphic processing.
  • stop: Halts neuromorphic processing.
  • config: Configuration data bus for setting parameters.

• Data Signals

  • input_data: Data bus for input data.
  • output_data: Data bus for output data.

• Status Signals

  • ready: Indicates when the neuromorphic processor is ready for new data.
  • done: Indicates completion of processing.

Alternatives Considered

• Custom ISA Core: Designing a custom core specifically tailored for the neuromorphic processor. However, this approach lacks the extensive toolchain and software ecosystem support available for RISC-V.
• ARM Cortex-M Core: Integrating an ARM core. While feasible, this approach could involve licensing costs and complexity not present with RISC-V.

Additional Context

Integrating a RISC-V core aligns with the trend towards open-source hardware and leverages a growing ecosystem of tools and libraries, ensuring long-term support and flexibility for future developments in the ODIN architecture.

References:

RISC-V Foundation
Rocket Chip Generator
PicoRV32