From c8904b67b498b43c14d6cf001193861f7873f14e Mon Sep 17 00:00:00 2001
From: Andrey Filippov <andrey@elphel.com>
Date: Thu, 22 May 2014 02:13:04 -0600
Subject: [PATCH] added modules, simulating

---
 .editor_defines                               |    3 +-
 .gitignore                                    |    1 +
 .project                                      |   16 +-
 .settings/com.elphel.vdt.FPGA_project.prefs   |    6 +-
 .../com.elphel.vdt.VivadoSynthesis.prefs      |    5 +-
 axi/axibram.v                                 |    8 +-
 axi/axibram_read.v                            |    2 +-
 axi/axibram_write.v                           |   21 +-
 axi/macros393.v                               |  107 +-
 ddrc_control.v                                |  166 +-
 ddrc_status.v                                 |   36 +-
 ddrc_test01.v                                 |  217 ++-
 ddrc_test01.xdc                               |  207 +++
 ddrc_test01_testbench.sav                     | 1413 +++++++++++++++++
 ddrc_test01_testbench.tf                      |  731 +++++++++
 phy/phy_top.v                                 |    6 +-
 simulation_modules/simul_axi_fifo_out.v       |   65 +
 simulation_modules/simul_axi_master_rdaddr.v  |   92 ++
 simulation_modules/simul_axi_master_wdata.v   |   77 +
 simulation_modules/simul_axi_master_wraddr.v  |   90 ++
 simulation_modules/simul_axi_read.v           |   86 +
 simulation_modules/simul_axi_slow_ready.v     |   40 +
 simulation_modules/simul_fifo.v               |   65 +
 util_modules/fifo_cross_clocks.v              |   95 ++
 util_modules/fifo_same_clock.v                |   88 +
 wrap/mmcm_phase_cntr.v                        |    2 +-
 wrap/oserdes_mem.v                            |    4 +-
 27 files changed, 3409 insertions(+), 240 deletions(-)
 create mode 100644 ddrc_test01.xdc
 create mode 100644 ddrc_test01_testbench.sav
 create mode 100644 ddrc_test01_testbench.tf
 create mode 100644 simulation_modules/simul_axi_fifo_out.v
 create mode 100644 simulation_modules/simul_axi_master_rdaddr.v
 create mode 100644 simulation_modules/simul_axi_master_wdata.v
 create mode 100644 simulation_modules/simul_axi_master_wraddr.v
 create mode 100644 simulation_modules/simul_axi_read.v
 create mode 100644 simulation_modules/simul_axi_slow_ready.v
 create mode 100644 simulation_modules/simul_fifo.v
 create mode 100644 util_modules/fifo_cross_clocks.v
 create mode 100644 util_modules/fifo_same_clock.v

diff --git a/.editor_defines b/.editor_defines
index 7fc8bed..071a363 100644
--- a/.editor_defines
+++ b/.editor_defines
@@ -1,3 +1,4 @@
   // This file may be used to define same pre-processor macros to be included into each parsed file
   // It can be used to check different `ifdef branches
-  `define XIL_TIMING //Simprim 
+  //`define XIL_TIMING //Simprim 
+  `define IVERILOG
\ No newline at end of file
diff --git a/.gitignore b/.gitignore
index af7384a..aa1ba16 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,3 +2,4 @@ unisims
 glbl.v
 vivado_*
 syntax_*
+simulation/*
diff --git a/.project b/.project
index 1b7f111..23e3e63 100644
--- a/.project
+++ b/.project
@@ -51,7 +51,7 @@
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140515155524262.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140520232524498.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
@@ -61,12 +61,12 @@
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140515155524262.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140520232524498.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140515155524262.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140520232524498.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
@@ -76,7 +76,7 @@
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140515155524262.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140520232242973.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
@@ -86,7 +86,7 @@
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140515155524262.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140520232524498.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
@@ -96,7 +96,7 @@
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140515155524262.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140520232524498.log</location>
 		</link>
 		<link>
 			<name>vivado_state/eddr3-opt-phys.dcp</name>
@@ -106,7 +106,7 @@
 		<link>
 			<name>vivado_state/eddr3-place.dcp</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140515155524262.dcp</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140520232524498.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/eddr3-route.dcp</name>
@@ -116,7 +116,7 @@
 		<link>
 			<name>vivado_state/eddr3-synth.dcp</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140515155524262.dcp</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140520204515091.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>
diff --git a/.settings/com.elphel.vdt.FPGA_project.prefs b/.settings/com.elphel.vdt.FPGA_project.prefs
index 2329b07..cf951ee 100644
--- a/.settings/com.elphel.vdt.FPGA_project.prefs
+++ b/.settings/com.elphel.vdt.FPGA_project.prefs
@@ -1,4 +1,6 @@
-FPGA_project_2_ImplementationTopFile=phy/test_phy_top_01.v
+FPGA_project_0_SimulationTopFile=ddrc_test01_testbench.tf
+FPGA_project_1_SimulationTopModule=ddrc_test01_testbench
+FPGA_project_2_ImplementationTopFile=ddrc_test01.v
 FPGA_project_4_part=xc7z030fbg484-2
-com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->
+com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->
 eclipse.preferences.version=1
diff --git a/.settings/com.elphel.vdt.VivadoSynthesis.prefs b/.settings/com.elphel.vdt.VivadoSynthesis.prefs
index fc0b76f..066c634 100644
--- a/.settings/com.elphel.vdt.VivadoSynthesis.prefs
+++ b/.settings/com.elphel.vdt.VivadoSynthesis.prefs
@@ -1,3 +1,4 @@
-VivadoSynthesis_102_ConstraintsFiles=phy/test_phy_top_01.xdc<-@\#\#@->
-com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->
+VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->
+VivadoSynthesis_95_ShowInfo=false
+com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->
 eclipse.preferences.version=1
diff --git a/axi/axibram.v b/axi/axibram.v
index 48527f9..5f4d645 100644
--- a/axi/axibram.v
+++ b/axi/axibram.v
@@ -308,7 +308,7 @@ ram_1kx32_1kx32
       .data_in(wdata_out[31:0])     // data out
     );
     
-fifo_reg_W_D   #( .DATA_WIDTH(30),.DATA_DEPTH(4))    
+fifo_same_clock   #( .DATA_WIDTH(30),.DATA_DEPTH(4))    
     raddr_i (
         .rst(rst),
         .clk(aclk),
@@ -320,7 +320,7 @@ fifo_reg_W_D   #( .DATA_WIDTH(30),.DATA_DEPTH(4))
         .full(),
         .half_full(ar_half_full)
     );
-fifo_reg_W_D   #( .DATA_WIDTH(30),.DATA_DEPTH(4))    
+fifo_same_clock   #( .DATA_WIDTH(30),.DATA_DEPTH(4))    
     waddr_i (
         .rst(rst),
         .clk(aclk),
@@ -332,7 +332,7 @@ fifo_reg_W_D   #( .DATA_WIDTH(30),.DATA_DEPTH(4))
         .full(),
         .half_full(aw_half_full)
     );
-fifo_reg_W_D   #( .DATA_WIDTH(49),.DATA_DEPTH(4))    
+fifo_same_clock   #( .DATA_WIDTH(49),.DATA_DEPTH(4))    
     wdata_i (
         .rst(rst),
         .clk(aclk),
@@ -344,7 +344,7 @@ fifo_reg_W_D   #( .DATA_WIDTH(49),.DATA_DEPTH(4))
         .full(),
         .half_full(w_half_full)
     );
-fifo_reg_W_D  #( .DATA_WIDTH(14),.DATA_DEPTH(4))    
+fifo_same_clock  #( .DATA_WIDTH(14),.DATA_DEPTH(4))    
     wresp_i (
         .rst(rst),
         .clk(aclk),
diff --git a/axi/axibram_read.v b/axi/axibram_read.v
index df59c64..6104653 100644
--- a/axi/axibram_read.v
+++ b/axi/axibram_read.v
@@ -223,7 +223,7 @@ module  axibram_read #(
 */    
 //    assign start_read_burst_w=  ar_nempty && (rready?start_read_burst_1:start_read_burst_0);
 
-fifo_reg_W_D   #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))    
+fifo_same_clock   #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))    
     raddr_i (
         .rst(rst),
         .clk(aclk),
diff --git a/axi/axibram_write.v b/axi/axibram_write.v
index b74c855..988fb42 100644
--- a/axi/axibram_write.v
+++ b/axi/axibram_write.v
@@ -92,16 +92,25 @@ module  axibram_write #(
     wire        bram_we_w; //,bram_we_nonmasked;   // write BRAM memory non-masked - should be combined with  
     wire        start_write_burst_w;
     wire        write_in_progress_w;
+    
+    wire        aw_nempty_ready; // aw_nempty and device ready
+    wire        w_nempty_ready; // w_nempty and device ready
+    assign aw_nempty_ready=aw_nempty && dev_ready_r; // should it be dev_ready?
+    assign w_nempty_ready=w_nempty && dev_ready_r; // should it be dev_ready?
+    
     reg         dev_ready_r;        // device, selected at start burst
     assign      next_wr_address_w=
       wburst[1]?
         (wburst[0]? {ADDRESS_BITS{1'b0}}:((write_address[ADDRESS_BITS-1:0]+1) & {{(ADDRESS_BITS-4){1'b1}}, ~wlen[3:0]})):
         (wburst[0]? (write_address[ADDRESS_BITS-1:0]+1):(write_address[ADDRESS_BITS-1:0]));
         
-    assign      bram_we_w=         w_nempty &&  write_in_progress && dev_ready_r;
+    assign      bram_we_w=         w_nempty_ready &&  write_in_progress;
 //    assign      bram_we_nonmasked= w_nempty &&  write_in_progress;
-    assign start_write_burst_w=aw_nempty && (!write_in_progress || (w_nempty && (write_left[3:0]==4'b0)));
-    assign write_in_progress_w=aw_nempty || (write_in_progress && !(w_nempty && (write_left[3:0]==4'b0))); 
+//    assign start_write_burst_w=aw_nempty && (!write_in_progress || (w_nempty && (write_left[3:0]==4'b0)));
+//    assign start_write_burst_w=aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));
+    assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));
+//    assign write_in_progress_w=aw_nempty || (write_in_progress && !(w_nempty && (write_left[3:0]==4'b0))); 
+    assign write_in_progress_w=aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0))); 
     
     always @ (posedge  aclk or posedge  rst) begin
       if   (rst)                    wburst[1:0] <= 0;
@@ -152,7 +161,7 @@ module  axibram_write #(
    assign  bram_wstb   = wstb_out[3:0]; 
    assign  bram_wdata = wdata_out[31:0];
     
-fifo_reg_W_D   #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))    
+fifo_same_clock   #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))    
     waddr_i (
         .rst(rst),
         .clk(aclk),
@@ -164,7 +173,7 @@ fifo_reg_W_D   #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
         .full(),
         .half_full(aw_half_full)
     );
-fifo_reg_W_D   #( .DATA_WIDTH(49),.DATA_DEPTH(4))    
+fifo_same_clock   #( .DATA_WIDTH(49),.DATA_DEPTH(4))    
     wdata_i (
         .rst(rst),
         .clk(aclk),
@@ -176,7 +185,7 @@ fifo_reg_W_D   #( .DATA_WIDTH(49),.DATA_DEPTH(4))
         .full(),
         .half_full(w_half_full)
     );
-fifo_reg_W_D  #( .DATA_WIDTH(14),.DATA_DEPTH(4))    
+fifo_same_clock  #( .DATA_WIDTH(14),.DATA_DEPTH(4))    
     wresp_i (
         .rst(rst),
         .clk(aclk),
diff --git a/axi/macros393.v b/axi/macros393.v
index 81654f3..309d1e2 100644
--- a/axi/macros393.v
+++ b/axi/macros393.v
@@ -2,7 +2,7 @@
 ** -----------------------------------------------------------------------------**
 ** macros353.v
 **
-** I/O pads related circuitry
+** temporary, modules to be moved
 **
 ** Copyright (C) 2002 Elphel, Inc
 **
@@ -25,42 +25,8 @@
 ** -----------------------------------------------------------------------------**
 **
 */
-// just make more convenient A[3:0] instead of 4 one-bit inputs
-// TODO: Replace direct instances of SRL16 to imporve portability
-/*
-module MSRL16 (Q, A, CLK, D);
-    output Q;
-    input  [3:0] A;
-    input  CLK, D;
-    SRL16 i_q(.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
-endmodule
-
 
-module MSRL16_1 (Q, A, CLK, D);
-    output Q;
-    input  [3:0] A;
-    input  CLK, D;
-    SRL16_1 i_q(.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
-endmodule
-*/
 
-/*
-module myRAM_WxD_D(D,WE,clk,AW,AR,QW,QR);
-parameter DATA_WIDTH=16;
-parameter DATA_DEPTH=4;
-parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
-    input	 [DATA_WIDTH-1:0]	D;
-    input				WE,clk;
-    input	 [DATA_DEPTH-1:0]	AW;
-    input	 [DATA_DEPTH-1:0]	AR;
-    output [DATA_WIDTH-1:0]	QW;
-    output [DATA_WIDTH-1:0]	QR;
-    reg	 [DATA_WIDTH-1:0]	ram [0:DATA_2DEPTH];
-    always @ (posedge clk) if (WE) ram[AW] <= D; 
-    assign	QW= ram[AW];
-    assign	QR= ram[AR];
-endmodule
-*/
 module ram_WxD
 #(
   parameter integer DATA_WIDTH=16,
@@ -82,75 +48,4 @@ module ram_WxD
     assign	QR= ram[AR];
 endmodule
 
-/*
-FIFO with minimal latency 1, uses 1 register slice on the data input, output - 1 mux after register
-*/
 
-module fifo_reg_W_D
-#(
-  parameter integer DATA_WIDTH=16,
-  parameter integer DATA_DEPTH=4,
-  parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
-)
-    (
-  input                   rst,      // reset, active high
-  input                   clk,      // clock - positive edge
-  input                   we,       // write enable
-  input                   re,       // read enable
-  input  [DATA_WIDTH-1:0] data_in,  // input data
-  output [DATA_WIDTH-1:0] data_out, // output data
-  output reg              nempty,   // FIFO has some data
-  output reg              full,     // FIFO full
-  output reg              half_full // FIFO half full
-  );
-    reg  [DATA_DEPTH  :0] fill=0;
-    reg                   just_one=0;
-    reg  [DATA_WIDTH-1:0] inreg;
-    reg  [DATA_WIDTH-1:0] outreg;
-    reg  [DATA_DEPTH-1:0] ra;
-    reg  [DATA_DEPTH-1:0] wa;
-    wire [DATA_DEPTH  :0] next_fill;
-    reg  wem;
-    wire rem;
-    reg  [DATA_WIDTH-1:0]   ram [0:DATA_2DEPTH];
-//    wire  [DATA_DEPTH  :0] pre_next_fill= ((we && ~re)?1:((~we && re)?-1:0));
-    assign next_fill = fill[4:0]+((we && ~re)?1:((~we && re)?5'b11111:5'b00000));
-//    assign next_fill = fill+((we && ~re)?1:((~we && re)?-1:0));
-//    assign next_fill[DATA_DEPTH  :0] = fill[DATA_DEPTH  :0]+pre_next_fill[DATA_DEPTH  :0];
-//    assign next_fill[DATA_DEPTH  :0] = fill[DATA_DEPTH  :0]+1;
-//    assign next_fill[DATA_DEPTH  :0] = fill[DATA_DEPTH  :0]+((we && ~re)?5'b1:0);
-//    assign next_fill[4  :0] = fill[4  :0]+((we && ~re)?5'b1:0);
-    assign data_out  = just_one?inreg:outreg;
-    assign rem = just_one? wem : re; 
-    always @ (posedge  clk or posedge  rst) begin
-      if   (rst) fill <= 0;
-//      else       fill <= next_fill;
-//      else       fill <= fill+1;
-//      else       fill <= fill[4  :0]+((we && ~re)?1:((~we && re)?-1:0));
-//      else       fill <= fill[4  :0]+((we && ~re)?5'b00001:((~we && re)?5'b11111:5'b00000));
-      else if (we && ~re) fill <= fill+1;
-      else if (~we && re) fill <= fill-1;
-      if (rst)      wa <= 0;
-      else if (wem) wa <= wa+1;
-      if (rst)      ra <= 1; // 0;
-//      else if (re)  ra <= ra+1; //wrong?
-//      else if (rem)  ra <= ra+1; //may be still wrong
-      else if (re)  ra <= ra+1; //now ra is 1 ahead
-      else if (!nempty) ra <= wa+1; // Just recover from bit errors TODO: fix
-      
-      if (rst)      nempty <= 0;
-      else          nempty <= (next_fill != 0);
-      
-    end
-    always @ (posedge  clk) begin
-      if (wem) ram[wa] <= inreg;
-      just_one <= (next_fill == 1);
-//      nempty   <= (next_fill != 0);
-      half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
-      full <=     (fill & (1<< DATA_DEPTH   ))!=0;
-      if (we)  inreg  <= data_in;
-      if (rem) outreg <= just_one?inreg:ram[ra];
-      wem <= we;
-    end
-endmodule
-//    tri0 GSR = glbl.GSR;
diff --git a/ddrc_control.v b/ddrc_control.v
index 3db240d..ad80b09 100644
--- a/ddrc_control.v
+++ b/ddrc_control.v
@@ -21,11 +21,48 @@
 `timescale 1ns/1ps
 
 module  ddrc_control #(
-    parameter AXI_WR_ADDR_BITS=   12,
-    parameter SELECT_ADDR =      'h800, // address to select this module
-    parameter SELECT_ADDR_MASK = 'h800, // address mask to select this  module
-    parameter BUSY_ADDR =        'hc00, // address to generate busy
-    parameter BUSY_ADDR_MASK =   'hc00  // address mask to generate busy
+    parameter AXI_WR_ADDR_BITS=    12,
+//    parameter SELECT_ADDR =        'h800, // address to select this module
+//    parameter SELECT_ADDR_MASK =   'h800, // address mask to select this  module
+//    parameter BUSY_ADDR =          'hc00, // address to generate busy
+//    parameter BUSY_ADDR_MASK =     'hc00,  // address mask to generate busy
+
+    parameter CONTROL_ADDR =        'h1000, // AXI write address of control write registers
+    parameter CONTROL_ADDR_MASK =   'h1400, // AXI write address of control registers
+//    parameter STATUS_ADDR =         'h1400, // AXI write address of status read registers
+//    parameter STATUS_ADDR_MASK =    'h1400, // AXI write address of status registers
+    parameter BUSY_WR_ADDR =        'h1800, // AXI write address to generate busy
+    parameter BUSY_WR_ADDR_MASK =   'h1c00, // AXI write address mask to generate busy
+    
+//    parameter DLY_LD_ADDR =        'h880,  // address to generate delay load
+//    parameter DLY_LD_ADDR_MASK =   'hb80,  // address mask to generate delay load
+//    parameter DLY_SET_ADDR =       'h870,  // address to generate delay set
+//    parameter DLY_SET_ADDR_MASK =  'hbff,  // address mask to generate delay set
+//    parameter RUN_CHN_ADDR =       'h800,  // address to set sequnecer channel and  run (4 LSB-s - channel)
+//    parameter RUN_CHN_ADDR_MASK =  'hbf0,  // address mask to generate sequencer channel/run
+//    parameter PATTERNS_ADDR =      'h820,  // address to set DQM and DQS patterns (16'h0055)
+//    parameter PATTERNS_ADDR_MASK = 'hbff,  // address mask to set DQM and DQS patterns
+//    parameter PAGES_ADDR =         'h821,  // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
+//    parameter PAGES_ADDR_MASK =    'hbff,  // address mask to set DQM and DQS patterns
+//    parameter CMDA_EN_ADDR =       'h822,  // address to enable('h823)/disable('h822) command/address outputs  
+//    parameter CMDA_EN_ADDR_MASK =  'hbfe,  // address mask for command/address outputs
+//    parameter EXTRA_ADDR =         'h824,  // address to set extra parameters (currently just inv_clk_div)
+//    parameter EXTRA_ADDR_MASK =    'hbff   // address mask for extra parameters
+
+    parameter DLY_LD_REL =        'h080,  // address to generate delay load
+    parameter DLY_LD_REL_MASK =   'h380,  // address mask to generate delay load
+    parameter DLY_SET_REL =       'h070,  // address to generate delay set
+    parameter DLY_SET_REL_MASK =  'h3ff,  // address mask to generate delay set
+    parameter RUN_CHN_REL =       'h000,  // address to set sequnecer channel and  run (4 LSB-s - channel)
+    parameter RUN_CHN_REL_MASK =  'h3f0,  // address mask to generate sequencer channel/run
+    parameter PATTERNS_REL =      'h020,  // address to set DQM and DQS patterns (16'h0055)
+    parameter PATTERNS_REL_MASK = 'h3ff,  // address mask to set DQM and DQS patterns
+    parameter PAGES_REL =         'h021,  // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
+    parameter PAGES_REL_MASK =    'h3ff,  // address mask to set DQM and DQS patterns
+    parameter CMDA_EN_REL =       'h022,  // address to enable('h823)/disable('h822) command/address outputs  
+    parameter CMDA_EN_REL_MASK =  'h3fe,  // address mask for command/address outputs
+    parameter EXTRA_REL =         'h024,  // address to set extra parameters (currently just inv_clk_div)
+    parameter EXTRA_REL_MASK =    'h3ff   // address mask for extra parameters
 )(
     input                         clk,
     input                         mclk,
@@ -46,7 +83,7 @@ module  ddrc_control #(
     output                 [ 7:0] dly_data, // 8-bit IDELAY/ODELAY (fine) and MMCM phase shift
     output                 [ 6:0] dly_addr, // address to select delay register
     output                        ld_delay, // write dly_data to dly_address, one mclk active pulse
-    output                        set,      // transfer (activate) all delays simultaneosly, 1 mclk pulse 
+    output                        dly_set,      // transfer (activate) all delays simultaneosly, 1 mclk pulse 
 // control: additional signals
     output                        cmda_tri,    // tri-state all command and address lines to DDR chip
     output                        inv_clk_div, // invert clk_div to ISERDES
@@ -59,11 +96,122 @@ module  ddrc_control #(
     output                 [ 1:0] port1_int_page  // port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0) 
 
 );
+    localparam DLY_LD_ADDR =        CONTROL_ADDR |      DLY_LD_REL;       // address to generate delay load
+    localparam DLY_LD_ADDR_MASK =   CONTROL_ADDR_MASK | DLY_LD_REL_MASK;  // address mask to generate delay load
+    localparam DLY_SET_ADDR =       CONTROL_ADDR |      DLY_SET_REL;      // address to generate delay set
+    localparam DLY_SET_ADDR_MASK =  CONTROL_ADDR_MASK | DLY_SET_REL_MASK; // address mask to generate delay set
+    localparam RUN_CHN_ADDR =       CONTROL_ADDR |      RUN_CHN_REL;      // address to set sequnecer channel and  run (4 LSB-s - channel)
+    localparam RUN_CHN_ADDR_MASK =  CONTROL_ADDR_MASK | RUN_CHN_REL_MASK; // address mask to generate sequencer channel/run
+    localparam PATTERNS_ADDR =      CONTROL_ADDR |      PATTERNS_REL;     // address to set DQM and DQS patterns (16'h0055)
+    localparam PATTERNS_ADDR_MASK = CONTROL_ADDR_MASK | PATTERNS_REL_MASK;// address mask to set DQM and DQS patterns
+    localparam PAGES_ADDR =         CONTROL_ADDR |      PAGES_REL;        // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
+    localparam PAGES_ADDR_MASK =    CONTROL_ADDR_MASK | PAGES_REL_MASK;   // address mask to set DQM and DQS patterns
+    localparam CMDA_EN_ADDR =       CONTROL_ADDR |      CMDA_EN_REL;      // address to enable('h823)/disable('h822) command/address outputs  
+    localparam CMDA_EN_ADDR_MASK =  CONTROL_ADDR_MASK | CMDA_EN_REL_MASK; // address mask for command/address outputs
+    localparam EXTRA_ADDR =         CONTROL_ADDR |      EXTRA_REL;        // address to set extra parameters (currently just inv_clk_div)
+    localparam EXTRA_ADDR_MASK =    CONTROL_ADDR_MASK | EXTRA_REL_MASK;   // address mask for extra parameters
+
     reg busy_r=0;
-    reg selected_r=0;
+    reg selected=0;
+    reg selected_busy=0;
+(* keep = "true" *)    wire fifo_half_empty; // just debugging with (* keep = "true" *)
+    wire [AXI_WR_ADDR_BITS-1:0] waddr_fifo_out;
+    wire                 [31:0] wdata_fifo_out;
+//    reg                         fifo_re; // wrong, need to have (fifo!=1) || !re 
+    wire                        fifo_nempty;
+    wire                        fifo_re=fifo_nempty; // try simpler
+    reg  [AXI_WR_ADDR_BITS-1:0] waddr_fifo_out_r;
+    reg                  [31:0] wdata_fifo_out_r;
+    reg                         dly_ld_r=0;
+    reg                         dly_set_r=0;
+    reg                         run_seq_r=0;
+    reg                  [ 7:0] dqs_pattern_r;    // DQS pattern during write (normally 8'h55)
+    reg                  [ 7:0] dqm_pattern_r;    // DQM pattern (just for testing, should be 8'h0)
+    reg                  [ 1:0] port0_page_r;     // port 0 buffer read page (to be controlled by arbiter later, set to 2'b0)
+    reg                  [ 1:0] port0_int_page_r; // port 0 PHY-side write to buffer page (to be controlled by arbiter later, set to 2'b0)
+    reg                  [ 1:0] port1_page_r;     // port 1 buffer write page (to be controlled by arbiter later, set to 2'b0)
+    reg                  [ 1:0] port1_int_page_r; // port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0) 
+    reg                         cmda_en_r;        // enable (tri-state off) all command and address lines to DDR chip
+    reg                         inv_clk_div_r;    // invert clk_div to ISERDES
+
+    assign ld_delay = dly_ld_r;
+    assign dly_set =  dly_set_r;
+    assign dly_data = wdata_fifo_out_r[ 7:0]; // WARNING: [Synth 8-3936] Found unconnected internal register 'wdata_fifo_out_r_reg' and it is trimmed from '32' to '11' bits. [ddrc_control.v:100]
+    assign dly_addr = waddr_fifo_out_r[ 6:0]; //WARNING: [Synth 8-3936] Found unconnected internal register 'waddr_fifo_out_r_reg' and it is trimmed from '12' to '7' bits. [ddrc_control.v:101]
+    assign run_addr = wdata_fifo_out_r[10:0];
+    assign run_chn =  waddr_fifo_out_r[3:0];
+    assign run_seq =  run_seq_r;
+
+    assign busy=busy_r && (start_wburst?(((pre_waddr ^ BUSY_WR_ADDR) & BUSY_WR_ADDR_MASK)==0): selected_busy);
+
+    assign dqs_pattern =    dqs_pattern_r[7:0];
+    assign dqm_pattern =    dqm_pattern_r[7:0];
+    assign port0_page =     port0_page_r[1:0];
+    assign port0_int_page = port0_int_page_r[1:0];
+    assign port1_page =     port1_page_r[1:0];
+    assign port1_int_page = port1_int_page_r[1:0];
+    assign cmda_tri =       ~cmda_en_r;
+    assign inv_clk_div =    inv_clk_div_r;
+
+    always @ (posedge clk or posedge rst) begin
+        if (rst)               selected <= 1'b0;
+        else if (start_wburst) selected <= ((pre_waddr ^ CONTROL_ADDR) & CONTROL_ADDR_MASK)==0;
+        if (rst)               selected_busy <= 1'b0;
+        else if (start_wburst) selected_busy <= ((pre_waddr ^ BUSY_WR_ADDR) & BUSY_WR_ADDR_MASK)==0;
+        if (rst)               busy_r <= 1'b0;
+//        else if (start_wburst) busy_r <= !fifo_half_empty;
+        else                   busy_r <= !fifo_half_empty;
+        
+    end
+
+    /* FIFO to cross clock boundary */
+    fifo_cross_clocks #(
+        .DATA_WIDTH  (AXI_WR_ADDR_BITS+32),
+        .DATA_DEPTH  (4)
+    ) fifo_cross_clocks_i (
+        .rst         (rst), // input
+        .rclk        (mclk), // input
+        .wclk        (clk), // input
+        .we          (wr_en && selected), // input
+        .re          (fifo_re), // input
+        .data_in     ({waddr[AXI_WR_ADDR_BITS-1:0],wdata[31:0]}), // input[15:0] 
+        .data_out    ({waddr_fifo_out[AXI_WR_ADDR_BITS-1:0],wdata_fifo_out[31:0]}), // output[15:0] 
+        .nempty      (fifo_nempty), // output
+        .half_empty  (fifo_half_empty) // output
+    );
+    always @ (posedge rst or posedge mclk) begin
+  //      if (rst) fifo_re <= 1'b0;
+  //      else     fifo_re <= fifo_nempty;
+        if (rst) dly_ld_r <= 1'b0;
+        else     dly_ld_r <= fifo_re && (((waddr_fifo_out ^ DLY_LD_ADDR) & DLY_LD_ADDR_MASK)==0);
+        if (rst) dly_set_r <= 1'b0;
+        else     dly_set_r <= fifo_re && (((waddr_fifo_out ^ DLY_SET_ADDR) & DLY_SET_ADDR_MASK)==0);
+        if (rst) run_seq_r <= 1'b0;
+        else     run_seq_r <= fifo_re && (((waddr_fifo_out ^ RUN_CHN_ADDR) & RUN_CHN_ADDR_MASK)==0);
+
+        if (rst) {dqm_pattern_r,dqs_pattern_r} <= 16'h0055;
+        else if (fifo_re && (((waddr_fifo_out ^ PATTERNS_ADDR) & PATTERNS_ADDR_MASK)==0))
+                 {dqm_pattern_r,dqs_pattern_r} <= wdata_fifo_out[15:0];
+
+        if (rst) {port1_page_r[1:0],port1_int_page_r[1:0],port0_page_r[1:0],port0_int_page_r[1:0]} <= 8'h00;
+        else if (fifo_re && (((waddr_fifo_out ^ PAGES_ADDR) & PAGES_ADDR_MASK)==0))
+                 {port1_page_r[1:0],port1_int_page_r[1:0],port0_page_r[1:0],port0_int_page_r[1:0]} <= wdata_fifo_out[7:0];
+        
+        if (rst) cmda_en_r <= 1'b0;
+        else if (fifo_re && (((waddr_fifo_out ^ CMDA_EN_ADDR) & CMDA_EN_ADDR_MASK)==0))
+                 cmda_en_r <= waddr_fifo_out[0];
+
+        if (rst) inv_clk_div_r <= 1'b0;
+        else if (fifo_re && (((waddr_fifo_out ^ EXTRA_ADDR) & EXTRA_ADDR_MASK)==0))
+                 inv_clk_div_r <= wdata_fifo_out[0];
+
+    end
+    always @ (posedge mclk) begin
+        waddr_fifo_out_r <= waddr_fifo_out;
+        wdata_fifo_out_r <= wdata_fifo_out;
+    end
     
-//    assign busy=busy_r && start_wburst?(((pre_addr ^ SELECT_ADDR) & SELECT_ADDR_MASK)==0): selected_r;
-    assign busy=busy_r && start_wburst?(((pre_waddr ^ BUSY_ADDR) & BUSY_ADDR_MASK)==0): selected_r;
+
 
 endmodule
 
diff --git a/ddrc_status.v b/ddrc_status.v
index a6d8fde..9d4b029 100644
--- a/ddrc_status.v
+++ b/ddrc_status.v
@@ -20,31 +20,35 @@
  *******************************************************************************/
 `timescale 1ns/1ps
 
-module  ddrc_status#(
-    parameter AXI_RD_ADDR_BITS=   12,
-    parameter SELECT_ADDR =      'h800, // address to select this module
-    parameter SELECT_ADDR_MASK = 'h800, // address mask to select this  module
-    parameter BUSY_ADDR =        'hc00, // address to generate busy
-    parameter BUSY_ADDR_MASK =   'hc00  // address mask to generate busy
-)(
-    input                         clk,
-    input                         mclk,
-    input                         rst,
-    input  [AXI_RD_ADDR_BITS-1:0] pre_raddr,     // AXI reade address, before actual reads (to generate busy), valid@start_burst
-    input                         start_rburst,  // burst start - should generate ~ready (should be AND-ed with !busy internally) 
-    input  [AXI_RD_ADDR_BITS-1:0] raddr,         // read address, valid with rd_en
-    input                         rd_en,         // read enable
+module  ddrc_status
+//#(
+//    parameter AXI_RD_ADDR_BITS=   12
+//    parameter SELECT_ADDR =      'h800, // address to select this module
+//    parameter SELECT_ADDR_MASK = 'h800, // address mask to select this  module
+//    parameter BUSY_ADDR =        'hc00, // address to generate busy
+//    parameter BUSY_ADDR_MASK =   'hc00  // address mask to generate busy
+//)
+ (
+//    input                         clk,
+//    input                         mclk,
+//    input                         rst,
+//    input  [AXI_RD_ADDR_BITS-1:0] pre_raddr,     // AXI reade address, before actual reads (to generate busy), valid@start_burst
+//    input                         start_rburst,  // burst start - should generate ~ready (should be AND-ed with !busy internally) 
+//    input  [AXI_RD_ADDR_BITS-1:0] raddr,         // read address, valid with rd_en
+//    input                         rd_en,         // read enable
     output                 [31:0] rdata,         // read data, should valid with raddr and rd_en
     output                        busy,          // interface busy (combinatorial delay from start_wburst and pre_addr
 // status/readback signals
-    input                         run_done,      // sequencer done (add busy?)
+//    input                         run_done,      // sequencer done (add busy?)
     input                         run_busy,      // sequencer busy
 
     input                         locked,        // MMCM and PLL locked
     input                         ps_rdy,        // MMCM phase shift control ready
     input                  [ 7:0] ps_out         // MMCM phase shift value (in 1/56 of the Fvco period)
 );
-
+    assign busy=0;
+    assign rdata={21'b0,run_busy,locked,ps_rdy,ps_out[7:0]};
+    
 
 endmodule
 
diff --git a/ddrc_test01.v b/ddrc_test01.v
index 44e9369..0aff595 100644
--- a/ddrc_test01.v
+++ b/ddrc_test01.v
@@ -25,7 +25,7 @@ module  ddrc_test01 #(
     parameter SLEW_DQ =         "SLOW",
     parameter SLEW_DQS =        "SLOW",
     parameter SLEW_CMDA =       "SLOW",
-    parameter SLEW_CLK =       "SLOW",
+    parameter SLEW_CLK =        "SLOW",
     parameter IBUF_LOW_PWR =    "TRUE",
     parameter real REFCLK_FREQUENCY = 300.0,
     parameter HIGH_PERFORMANCE_MODE = "FALSE",
@@ -45,16 +45,36 @@ module  ddrc_test01 #(
     parameter SS_MOD_PERIOD =       10000,
     parameter CMD_PAUSE_BITS=       6,
     parameter CMD_DONE_BIT=         6,
-    parameter AXI_WR_ADDR_BITS =   12,
-    parameter AXI_RD_ADDR_BITS =   12,
-    parameter SELECT_WR_ADDR =      'h800, // AXI write address to select this module
-    parameter SELECT_WR_ADDR_MASK = 'h800, // AXI write address mask to select this  module
-    parameter BUSY_WR_ADDR =        'hc00, // AXI write address to generate busy
-    parameter BUSY_WR_ADDR_MASK =   'hc00, // AXI write address mask to generate busy
-    parameter SELECT_RD_ADDR =      'h800, // AXI read address to select this module
-    parameter SELECT_RD_ADDR_MASK = 'h800, // AXI read address mask to select this  module
-    parameter BUSY_RD_ADDR =        'hc00, // AXI read address to generate busy
-    parameter BUSY_RD_ADDR_MASK =   'hc00  // AXI read address mask to generate busy
+    parameter AXI_WR_ADDR_BITS =   13,
+    parameter AXI_RD_ADDR_BITS =   13,
+    parameter CONTROL_ADDR =        'h1000, // AXI write address of control write registers
+    parameter CONTROL_ADDR_MASK =   'h1400, // AXI write address of control registers
+    parameter STATUS_ADDR =         'h1400, // AXI write address of status read registers
+    parameter STATUS_ADDR_MASK =    'h1400, // AXI write address of status registers
+    parameter BUSY_WR_ADDR =        'h1800, // AXI write address to generate busy
+    parameter BUSY_WR_ADDR_MASK =   'h1c00, // AXI write address mask to generate busy
+    parameter CMD0_ADDR =           'h0800, // AXI write to command sequence memory
+    parameter CMD0_ADDR_MASK =      'h1800, // AXI read address mask for the command sequence memory
+    parameter PORT0_RD_ADDR =       'h0000, // AXI read address to generate busy
+    parameter PORT0_RD_ADDR_MASK =  'h1c00, // AXI read address mask to generate busy
+    parameter PORT1_WR_ADDR =       'h0400, // AXI read address to generate busy
+    parameter PORT1_WR_ADDR_MASK =  'h1c00,  // AXI read address mask to generate busy
+    // parameters below to be ORed with CONTROL_ADDR and CONTROL_ADDR_MASK respectively
+    parameter DLY_LD_REL =          'h080,  // address to generate delay load
+    parameter DLY_LD_REL_MASK =     'h380,  // address mask to generate delay load
+    parameter DLY_SET_REL =         'h070,  // address to generate delay set
+    parameter DLY_SET_REL_MASK =    'h3ff,  // address mask to generate delay set
+    parameter RUN_CHN_REL =         'h000,  // address to set sequnecer channel and  run (4 LSB-s - channel)
+    parameter RUN_CHN_REL_MASK =    'h3f0,  // address mask to generate sequencer channel/run
+    parameter PATTERNS_REL =        'h020,  // address to set DQM and DQS patterns (16'h0055)
+    parameter PATTERNS_REL_MASK =   'h3ff,  // address mask to set DQM and DQS patterns
+    parameter PAGES_REL =           'h021,  // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
+    parameter PAGES_REL_MASK =      'h3ff,  // address mask to set DQM and DQS patterns
+    parameter CMDA_EN_REL =         'h022,  // address to enable('h823)/disable('h822) command/address outputs  
+    parameter CMDA_EN_REL_MASK =    'h3fe,  // address mask for command/address outputs
+    parameter EXTRA_REL =           'h024,  // address to set extra parameters (currently just inv_clk_div)
+    parameter EXTRA_REL_MASK =      'h3ff   // address mask for extra parameters
+    
     
 )(
     // DDR3 interface
@@ -155,6 +175,67 @@ module  ddrc_test01 #(
    wire           axird_bram_ren;   //      .ren(bram_reg_re_w) ,      // read port enable
    wire           axird_bram_regen; //   .regen(bram_reg_re_w),        // output register enable
    wire  [31:0]   axird_bram_rdata;  //      .data_out(rdata[31:0]),       // data out
+   wire  [31:0]   port0_rdata;  //
+   wire  [31:0]   status_rdata;  //
+
+   wire        mclk;
+   wire        en_cmd0_wr;
+   wire [10:0] run_addr; // input[10:0] 
+   wire [ 3:0] run_chn;  // input[3:0] 
+   wire        run_seq;  // input
+//   wire        run_done; // output
+   wire        run_busy; // TODO: add to ddrc_sequencer 
+   wire [ 7:0] dly_data; // input[7:0] 
+   wire [ 6:0] dly_addr; // input[6:0] 
+   wire        ld_delay; // input
+   wire        set; // input
+
+   wire        locked; // output
+   wire        ps_rdy; // output
+   wire [ 7:0] ps_out; // output[7:0] 
+
+   wire        en_port0_rd;
+   wire        en_port0_regen;
+   wire        en_port1_wr;
+
+   wire [ 1:0] port0_page; // input[1:0] 
+   wire [ 1:0] port0_int_page; // input[1:0] 
+
+   wire [ 1:0] port1_page; // input[1:0] 
+   wire [ 1:0] port1_int_page;// input[1:0] 
+
+// additional control signals
+   wire        cmda_tri; // input
+   wire        inv_clk_div; // input
+   wire [ 7:0] dqs_pattern; // input[7:0] 8'h55 
+   wire [ 7:0] dqm_pattern; // input[7:0] 8'h00
+
+   reg    select_port0;
+   reg    select_status;
+   wire axiwr_dev_busy;
+   wire axird_dev_busy;
+
+//   assign en_cmd0_wr=     axiwr_bram_wen   && (axiwr_bram_waddr[11:10]==2'h1);
+//   assign en_port0_rd=    axird_bram_ren   && (axird_bram_raddr[11:10]==2'h0);
+//   assign en_port0_regen= axird_bram_regen && (axird_bram_raddr[11:10]==2'h0);
+//   assign en_port1_wr=    axiwr_bram_wen   && (axiwr_bram_waddr[11:10]==2'h0);
+
+   assign en_cmd0_wr=     axiwr_bram_wen   && (((axiwr_bram_waddr ^ CMD0_ADDR) & CMD0_ADDR_MASK)==0);
+   assign en_port0_rd=    axird_bram_ren   && (((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
+   assign en_port0_regen= axird_bram_regen && (((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
+   assign en_port1_wr=    axiwr_bram_wen   && (((axiwr_bram_waddr ^ PORT1_WR_ADDR) & PORT1_WR_ADDR_MASK)==0);
+   
+   
+   assign axiwr_dev_ready = ~axiwr_dev_busy; //may combine (AND) multiple sources if needed
+   assign axird_bram_rdata= select_port0? port0_rdata[31:0]:(select_status?status_rdata[31:0]:32'bx);
+   assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed
+
+always @ (posedge axi_rst or posedge axi_aclk) begin
+    if (axi_rst) select_port0 <= 1'b0;
+    else if (axird_start_burst) select_port0 <= (((axird_pre_araddr[11:10]^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
+    if (axi_rst) select_status <= 1'b0;
+    else if (axird_start_burst) select_status <= (((axird_pre_araddr[11:10]^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
+end
    
 // Clock and reset from PS
 BUFG axi_rst_i  (.O(axi_rst),.I(~frst[0]));
@@ -219,58 +300,31 @@ BUFG axi_aclk_i (.O(axi_aclk),.I(~fclk[0]));
         .bram_regen  (axird_bram_regen), // output
         .bram_rdata  (axird_bram_rdata) // input[31:0] 
     );
-
-wire        mclk;
-wire        en_cmd0_wr;
-wire [10:0] run_addr; // input[10:0] 
-wire [ 3:0] run_chn;  // input[3:0] 
-wire        run_seq;  // input
-wire        run_done; // output
-wire        run_busy; // TODO: add to ddrc_sequencer 
-wire [ 7:0] dly_data; // input[7:0] 
-wire [ 6:0] dly_addr; // input[6:0] 
-wire        ld_delay; // input
-wire        set; // input
-
-wire        locked; // output
-wire        ps_rdy; // output
-wire [ 7:0] ps_out; // output[7:0] 
-
-wire        en_port0_rd;
-wire        en_port0_regen;
-wire        en_port1_wr;
-
-wire [ 1:0] port0_page; // input[1:0] 
-wire [ 1:0] port0_int_page; // input[1:0] 
-
-wire [ 1:0] port1_page; // input[1:0] 
-wire [ 1:0] port1_int_page;// input[1:0] 
-
-// additional control signals
-wire        cmda_tri; // input
-wire        inv_clk_div; // input
-wire [ 7:0] dqs_pattern; // input[7:0] 8'h55 
-wire [ 7:0] dqm_pattern; // input[7:0] 8'h00
-
-
-assign en_cmd0_wr=     axiwr_bram_wen   && (axiwr_bram_waddr[11:10]==2'h1);
-assign en_port0_rd=    axird_bram_ren   && (axird_bram_raddr[11:10]==2'h0);
-assign en_port0_regen= axird_bram_regen && (axird_bram_raddr[11:10]==2'h0);
-assign en_port1_wr=    axiwr_bram_wen   && (axiwr_bram_waddr[11:10]==2'h0);
-wire axiwr_dev_busy;
-assign axiwr_dev_ready = ~axiwr_dev_busy; //may combine (AND) multiple sources if needed
-
-wire axird_dev_busy;
-assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed
     ddrc_control #(
-        .AXI_WR_ADDR_BITS (AXI_WR_ADDR_BITS),
-        .SELECT_ADDR      (SELECT_WR_ADDR),
-        .SELECT_ADDR_MASK (SELECT_WR_ADDR_MASK),
-        .BUSY_ADDR        (BUSY_WR_ADDR),
-        .BUSY_ADDR_MASK   (BUSY_WR_ADDR_MASK)
+        .AXI_WR_ADDR_BITS  (AXI_WR_ADDR_BITS),
+        .CONTROL_ADDR      (CONTROL_ADDR),
+        .CONTROL_ADDR_MASK (CONTROL_ADDR_MASK),
+//        .STATUS_ADDR       (STATUS_ADDR),
+//        .STATUS_ADDR_MASK  (STATUS_ADDR_MASK),
+        .BUSY_WR_ADDR      (BUSY_WR_ADDR),
+        .BUSY_WR_ADDR_MASK (BUSY_WR_ADDR_MASK),
+        .DLY_LD_REL        (DLY_LD_REL),
+        .DLY_LD_REL_MASK   (DLY_LD_REL_MASK),
+        .DLY_SET_REL       (DLY_SET_REL),
+        .DLY_SET_REL_MASK  (DLY_SET_REL_MASK),
+        .RUN_CHN_REL       (RUN_CHN_REL),
+        .RUN_CHN_REL_MASK  (RUN_CHN_REL_MASK),
+        .PATTERNS_REL      (PATTERNS_REL),
+        .PATTERNS_REL_MASK (PATTERNS_REL_MASK),
+        .PAGES_REL         (PAGES_REL),
+        .PAGES_REL_MASK    (PAGES_REL_MASK),
+        .CMDA_EN_REL       (CMDA_EN_REL),
+        .CMDA_EN_REL_MASK  (CMDA_EN_REL_MASK),
+        .EXTRA_REL         (EXTRA_REL),
+        .EXTRA_REL_MASK    (EXTRA_REL_MASK)
     ) ddrc_control_i (
-        .clk              (axi_aclk),               // input
-        .mclk             (axiwr_bram_wclk),        // input
+        .clk              (axiwr_bram_wclk),        // same as axi_aclk
+        .mclk             (mclk),                   // input
         .rst              (axi_rst),                // input
         .pre_waddr        (axiwr_pre_awaddr[AXI_WR_ADDR_BITS-1:0]), // input[11:0] 
         .start_wburst     (axiwr_start_burst),      // input
@@ -284,7 +338,7 @@ assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources i
         .dly_data         (dly_data[7:0]),          // output[7:0] 
         .dly_addr         (dly_addr[6:0]),          // output[6:0] 
         .ld_delay         (ld_delay),               // output
-        .set              (set),                    // output
+        .dly_set          (set),                    // output
         .cmda_tri         (cmda_tri),               // output
         .inv_clk_div      (inv_clk_div),            // output
         .dqs_pattern      (dqs_pattern[7:0]),       // output[7:0] 
@@ -295,23 +349,25 @@ assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources i
         .port1_int_page   (port1_int_page[1:0])     // output[1:0] 
     );
     
-    ddrc_status #(
-        .AXI_RD_ADDR_BITS (AXI_RD_ADDR_BITS),
-        .SELECT_ADDR      (SELECT_RD_ADDR),
-        .SELECT_ADDR_MASK (SELECT_RD_ADDR_MASK),
-        .BUSY_ADDR        (BUSY_RD_ADDR),
-        .BUSY_ADDR_MASK   (BUSY_RD_ADDR_MASK)
-    ) ddrc_status_i (
-        .clk              (axi_aclk), // input
-        .mclk             (mclk), // input
-        .rst              (axi_rst), // input
-        .pre_raddr        (axird_pre_araddr[AXI_RD_ADDR_BITS-1:0]), // input[11:0] 
-        .start_rburst     (axird_start_burst), // input
-        .raddr            (axird_bram_raddr[AXI_RD_ADDR_BITS-1:0]), // input[11:0] 
-        .rd_en            (axird_bram_regen), // input
-        .rdata            (axird_bram_rdata[31:0]), // output[31:0] 
+    ddrc_status
+//     #(
+//        .AXI_RD_ADDR_BITS (AXI_RD_ADDR_BITS),
+//        .SELECT_ADDR      (SELECT_RD_ADDR),
+//        .SELECT_ADDR_MASK (SELECT_RD_ADDR_MASK),
+//        .BUSY_ADDR        (BUSY_RD_ADDR),
+//        .BUSY_ADDR_MASK   (BUSY_RD_ADDR_MASK)
+//    )
+     ddrc_status_i (
+//        .clk              (axi_aclk), // input
+//        .mclk             (mclk), // input
+//        .rst              (axi_rst), // input
+//        .pre_raddr        (axird_pre_araddr[AXI_RD_ADDR_BITS-1:0]), // input[11:0] 
+//        .start_rburst     (axird_start_burst), // input
+//        .raddr            (axird_bram_raddr[AXI_RD_ADDR_BITS-1:0]), // input[11:0] 
+//        .rd_en            (axird_bram_regen), // input
+        .rdata            (status_rdata[31:0]), // output[31:0] 
         .busy             (axird_dev_busy), // output
-        .run_done         (run_done), // input
+//        .run_done         (run_done), // input
         .run_busy         (run_busy), // input
         .locked           (locked), // input
         .ps_rdy           (ps_rdy), // input
@@ -377,7 +433,8 @@ assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources i
         .run_addr       (run_addr[10:0]), // input[10:0] 
         .run_chn        (run_chn[3:0]), // input[3:0] 
         .run_seq        (run_seq), // input
-        .run_done       (run_done), // output
+//        .run_done       (run_done), // output
+        .run_done       (), // output
         .run_busy       (run_busy), // output
         .dly_data       (dly_data[7:0]), // input[7:0] 
         .dly_addr       (dly_addr[6:0]), // input[6:0] 
@@ -393,7 +450,7 @@ assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources i
         .port0_page     (port0_page[1:0]), // input[1:0] 
         .port0_int_page (port0_int_page[1:0]), // input[1:0] 
         .port0_addr     (axird_bram_raddr[7:0]), // input[7:0] 
-        .port0_data     (axird_bram_rdata[31:0]), // output[31:0] 
+        .port0_data     (port0_rdata[31:0]), // output[31:0] 
         .port1_clk      (axi_aclk), // input
         .port1_we       (en_port1_wr), // input
         .port1_page     (port1_page[1:0]), // input[1:0] 
diff --git a/ddrc_test01.xdc b/ddrc_test01.xdc
new file mode 100644
index 0000000..b45aef9
--- /dev/null
+++ b/ddrc_test01.xdc
@@ -0,0 +1,207 @@
+#################################################################################
+# Filename: ddrc_test01.xdc
+# Date:2014-05-20  
+# Author: Andrey Filippov
+# Description: DDR3 controller test with axi constraints
+#
+# Copyright (c) 2014 Elphel, Inc.
+# ddrc_test01.xdc is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+#  ddrc_test01.xdc is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#################################################################################
+
+#    output                       SDCLK, // DDR3 clock differential output, positive
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDCLK}]
+set_property PACKAGE_PIN K3 [get_ports {SDCLK}]
+
+#    output                       SDNCLK,// DDR3 clock differential output, negative
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDNCLK}]
+set_property PACKAGE_PIN K2 [get_ports {SDNCLK}]
+
+#    output  [ADDRESS_NUMBER-1:0] SDA,   // output address ports (14:0) for 4Gb device
+set_property IOSTANDARD SSTL15 [get_ports {SDA[0]}]
+set_property PACKAGE_PIN N3 [get_ports {SDA[0]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[1]}]
+set_property PACKAGE_PIN H2 [get_ports {SDA[1]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[2]}]
+set_property PACKAGE_PIN M2 [get_ports {SDA[2]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[3]}]
+set_property PACKAGE_PIN P5 [get_ports {SDA[3]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[4]}]
+set_property PACKAGE_PIN H1 [get_ports {SDA[4]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[5]}]
+set_property PACKAGE_PIN M3 [get_ports {SDA[5]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[6]}]
+set_property PACKAGE_PIN J1 [get_ports {SDA[6]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[7]}]
+set_property PACKAGE_PIN P4 [get_ports {SDA[7]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[8]}]
+set_property PACKAGE_PIN K1 [get_ports {SDA[8]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[9]}]
+set_property PACKAGE_PIN P3 [get_ports {SDA[9]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[10]}]
+set_property PACKAGE_PIN F2 [get_ports {SDA[10]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[11]}]
+set_property PACKAGE_PIN H3 [get_ports {SDA[11]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[12]}]
+set_property PACKAGE_PIN G3 [get_ports {SDA[12]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[13]}]
+set_property PACKAGE_PIN N2 [get_ports {SDA[13]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDA[14]}]
+set_property PACKAGE_PIN J3 [get_ports {SDA[14]}]
+
+
+#    output                 [2:0] SDBA,  // output bank address ports
+set_property IOSTANDARD SSTL15 [get_ports {SDBA[0]}]
+set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDBA[1]}]
+set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}]
+
+set_property IOSTANDARD SSTL15 [get_ports {SDBA[2]}]
+set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}]
+
+#    output                       SDWE,  // output WE port
+set_property IOSTANDARD SSTL15 [get_ports {SDWE}]
+set_property PACKAGE_PIN G4 [get_ports {SDWE}]
+
+#    output                       SDRAS, // output RAS port
+set_property IOSTANDARD SSTL15 [get_ports {SDRAS}]
+set_property PACKAGE_PIN L2 [get_ports {SDRAS}]
+
+#    output                       SDCAS, // output CAS port
+set_property IOSTANDARD SSTL15 [get_ports {SDCAS}]
+set_property PACKAGE_PIN L1 [get_ports {SDCAS}]
+
+#    output                       SDCKE, // output Clock Enable port
+set_property IOSTANDARD SSTL15 [get_ports {SDCKE}]
+set_property PACKAGE_PIN E1 [get_ports {SDCKE}]
+
+#    output                       SDODT, // output ODT port
+set_property IOSTANDARD SSTL15 [get_ports {SDODT}]
+set_property PACKAGE_PIN M7 [get_ports {SDODT}]
+#
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[0]}]
+set_property PACKAGE_PIN K6 [get_ports {SDD[0]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[1]}]
+set_property PACKAGE_PIN L4 [get_ports {SDD[1]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[2]}]
+set_property PACKAGE_PIN K7 [get_ports {SDD[2]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[3]}]
+set_property PACKAGE_PIN K4 [get_ports {SDD[3]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[4]}]
+set_property PACKAGE_PIN L6 [get_ports {SDD[4]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[5]}]
+set_property PACKAGE_PIN M4 [get_ports {SDD[5]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[6]}]
+set_property PACKAGE_PIN L7 [get_ports {SDD[6]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[7]}]
+set_property PACKAGE_PIN N5 [get_ports {SDD[7]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[8]}]
+set_property PACKAGE_PIN H5 [get_ports {SDD[8]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[9]}]
+set_property PACKAGE_PIN J6 [get_ports {SDD[9]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[10]}]
+set_property PACKAGE_PIN G5 [get_ports {SDD[10]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[11]}]
+set_property PACKAGE_PIN H6 [get_ports {SDD[11]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[12]}]
+set_property PACKAGE_PIN F5 [get_ports {SDD[12]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[13]}]
+set_property PACKAGE_PIN F7 [get_ports {SDD[13]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[14]}]
+set_property PACKAGE_PIN F4 [get_ports {SDD[14]}]
+
+#    inout                 [15:0] SDD,       // DQ  I/O pads
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[15]}]
+set_property PACKAGE_PIN F6 [get_ports {SDD[15]}]
+
+#    inout                        DQSL,     // LDQS I/O pad
+set_property PACKAGE_PIN N7 [get_ports {DQSL}]
+set_property SLEW FAST [get_ports {DQSL}]
+set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSL}]
+
+#    inout                        NDQSL,    // ~LDQS I/O pad
+set_property PACKAGE_PIN N6 [get_ports {NDQSL}]
+set_property SLEW FAST [get_ports {NDQSL}]
+set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSL}]
+
+#    inout                        DQSU,     // UDQS I/O pad
+set_property PACKAGE_PIN H7 [get_ports {DQSU}]
+#set_property SLEW FAST [get_ports {DQSU}]
+set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSU}]
+
+#    inout                        NDQSU,    // ~UDQS I/O pad
+set_property PACKAGE_PIN G7 [get_ports {NDQSU}]
+#set_property SLEW FAST [get_ports {NDQSU}]
+set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSU}]
+
+#    inout                        SDDML,      // LDM  I/O pad (actually only output)
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDML}]
+set_property PACKAGE_PIN L5 [get_ports {SDDML}]
+
+#    inout                        SDDMU,      // UDM  I/O pad (actually only output)
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDMU}]
+set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
+
+
+# Global constraints
+
+set_property INTERNAL_VREF  0.750 [get_iobanks 34]
+set_property DCI_CASCADE 34 [get_iobanks 35]
+set_property INTERNAL_VREF  0.750 [get_iobanks 35]
+set_property CFGBVS GND [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
diff --git a/ddrc_test01_testbench.sav b/ddrc_test01_testbench.sav
new file mode 100644
index 0000000..ea6431c
--- /dev/null
+++ b/ddrc_test01_testbench.sav
@@ -0,0 +1,1413 @@
+[*]
+[*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI
+[*] Thu May 22 07:54:47 2014
+[*]
+[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140522015055672.lxt"
+[dumpfile_mtime] "Thu May 22 07:51:58 2014"
+[dumpfile_size] 63157569
+[savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav"
+[timestart] 98147000
+[size] 1920 1180
+[pos] -1921 -1
+*-20.053656 101463750 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] ddrc_test01_testbench.
+[treeopen] ddrc_test01_testbench.ddrc_test01_i.
+[treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.
+[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.
+[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.
+[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.
+[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.
+[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_ctrl_i.
+[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.
+[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.
+[treeopen] ddrc_test01_testbench.simul_axi_master_wdata_i.
+[sst_width] 305
+[signals_width] 348
+[sst_expanded] 1
+[sst_vpaned_height] 646
+@28
+ddrc_test01_testbench.RST[0]
+ddrc_test01_testbench.CLK[0]
+@c00200
+-pll_base_i
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.clkfbin[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.clkfbout[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.clkin[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.clkout0[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.clkout1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.clkout2[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.clkout3[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.clkout4[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.clkout5[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.locked[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.pwrdwn[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.rst[0]
+@1401200
+-pll_base_i
+@c00200
+-PLLE2_BASE_i
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.CLKFBIN[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.CLKFBOUT[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.CLKIN1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.CLKOUT0[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.CLKOUT1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.CLKOUT2[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.CLKOUT3[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.CLKOUT4[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.CLKOUT5[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.LOCKED[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.OPEN_DO[15:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.OPEN_DRDY[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.PWRDWN[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.RST[0]
+@1401200
+-PLLE2_BASE_i
+@c00200
+-plle2_adv_1
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKFBIN[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKFBOUTB[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKFBOUT[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKFBSTOPPED[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKIN1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKIN2[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKINSEL[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKINSTOPPED[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKOUT0B[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKOUT0[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKOUT1B[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKOUT1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKOUT2B[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKOUT2[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKOUT3B[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKOUT3[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKOUT4[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.CLKOUT5[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.DADDR[6:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.DCLK[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.DEN[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.DI[15:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.DO[15:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.DRDY[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.DWE[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.GSR[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.IS_CLKINSEL_INVERTED_REG[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.IS_PWRDWN_INVERTED_REG[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.IS_RST_INVERTED_REG[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.LOCKED[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.PSCLK[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.PSDONE[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.PSEN[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.PSINCDEC[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.PWRDWN[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.REF_CLK_JITTER_MAX_tmp[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.RST[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.chk_ok[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_cnt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_div1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_div[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_div_fint[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_div_fint_odd[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_div_frac
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_div_frac_int[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_dly_cnt[5:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_edge[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_fps_en[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_frac_en[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_frac_ht[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_frac_lt[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_frac_out[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_ht1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_ht[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_lt[6:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_nf_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_nocnt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0_out[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0f_product[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0pm_sel1[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0pm_sel[2:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0pm_sel_int[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk0ps_en[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_cnt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_div1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_div[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_dly_cnt[5:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_edge[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_fps_en[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_ht1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_ht[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_lt[6:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_nocnt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1pm_sel[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk1ps_en[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_cnt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_div1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_div[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_dly_cnt[5:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_edge[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_fps_en[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_ht1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_ht[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_lt[6:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_nocnt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2pm_sel[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk2ps_en[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_cnt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_div1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_div[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_dly_cnt[5:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_edge[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_fps_en[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_ht1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_ht[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_lt[6:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_nocnt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3pm_sel[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk3ps_en[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_cnt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_div1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_div[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_dly_cnt[5:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_edge[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_fps_en[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_ht1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_ht[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_lt[6:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_nocnt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4pm_sel[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk4ps_en[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_cnt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_div1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_div[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_dly_cnt[5:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_edge[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_fps_en[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_ht1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_ht[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_lt[6:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_nocnt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5pm_sel1[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5pm_sel[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk5ps_en[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_cnt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_div1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_div[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_dly_cnt[5:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_edge[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_fps_en[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_ht1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_ht[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_lt[6:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_nocnt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6pm_sel1[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6pm_sel[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk6ps_en[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clk_osc[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_div_fint[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_div_fint_odd[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_div_frac
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_div_frac_int[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_dly_t[63:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_fps_en[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_frac_en[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_frac_ht[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_frac_lt[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_in[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_lost_cnt[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_lost_val[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_p[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_stop_max[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_stop_tmp[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfb_tst[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_cnt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_div1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_div[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_div_t
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_div_t_int[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_dly[5:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_dly_cnt[5:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_edge[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_f_div
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_frac_out[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_ht1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_ht[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_lt[6:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_nf_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_nocnt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1pm_rl
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1pm_sel1[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1pm_sel[2:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1pm_sel_int[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm1ps_en[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm2_cnt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm2_div1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm2_div[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm2_edge[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm2_ht1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm2_ht[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm2_lt[6:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm2_nocnt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm2_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbm2_out_tmp[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbstopped_out1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbstopped_out[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbtmp_divi[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbtmp_hti[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbtmp_lti[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkfbtmp_nocnti[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin1_in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin2_in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_chk_t1
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_chk_t1_i[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_chk_t1_r
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_chk_t2
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_chk_t2_i[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_chk_t2_r
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_dly_t[63:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_edge[63:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_hold_f[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_jit[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_lock_cnt[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_lost_cnt[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_lost_val[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_lost_val_lk[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_p[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_period_tmp_t[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_stop_f[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_stop_max[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkin_stop_tmp[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_cnt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_div1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_div[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_divi[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_edge[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_edgei[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_ht1[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_ht[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_hti[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_lt[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_lti[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_nocnt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_nocnti[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkind_out_tmp[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkinsel_in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkinsel_tmp[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkinstopped_hold[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkinstopped_out1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkinstopped_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkinstopped_out_dly2[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkinstopped_out_dly[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkinstopped_vco_f[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkout0_dly[5:0]
+@28
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+@22
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+@28
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+@22
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+@28
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+@22
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+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkout3_out[0]
+@22
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+@28
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+@22
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+@28
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+@22
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+@28
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+@22
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkout_en_val[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkout_mux[7:0]
+@28
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+@22
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+@28
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+@22
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+@28
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkvco[0]
+@22
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+@28
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkvco_lk[0]
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkvco_lk_en[0]
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkvco_lk_tmp[0]
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkvco_ps_tmp1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkvco_ps_tmp2[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.clkvco_ps_tmp2_en[0]
+@22
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+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.cmpvco
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.daddr_in[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.daddr_lat[6:0]
+@28
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+@22
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+@28
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.den_r1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.den_r2[0]
+@22
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.dly_tmp1[63:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.dly_tmp[63:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.dly_tmp_int[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.do_out1[15:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.do_out[15:0]
+@28
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.drdy_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.drp_lock[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.drp_lock_cnt[9:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.drp_lock_fb_dly[4:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.drp_lock_lat[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.drp_lock_lat_cnt[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.drp_lock_ref_dly[4:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.drp_lock_sat_high[9:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.drp_unlock_cnt[9:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.dwe_in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.dwe_r1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.dwe_r2[0]
+@22
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+@28
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.fb_delay_found_tmp[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.fb_delay_max
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.fbclk_tmp[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.fbm1_comp_delay[63:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.fps_en[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.glock[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.i[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.ib[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.ik0[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.ik1[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.ik2[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.ik3[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.ik4[31:0]
+@28
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.init_trig[0]
+@22
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.lock_cnt_max[31:0]
+@28
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+@22
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.locked_en_time[31:0]
+@28
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.locked_out[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.locked_out_tmp[0]
+@22
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.md_product[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.mf_product[31:0]
+@28
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.pchk_clr[0]
+@22
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+@28
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+@22
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+@28
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+@22
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+@28
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+@22
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+@28
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+@28
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+@22
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+@28
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+@22
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+@28
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+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.tmp_ps_val1[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.tmp_ps_val2[63:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.tmp_string[160:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.unlock_recover[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.val_tmp[63:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.valid_daddr[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.vco_stp_f[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.vcoflag[0]
+@1401200
+-plle2_adv_1
+@c00200
+-phy_top_i
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk_div[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk_div_pre[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk_fb[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk_in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk_pre[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk_ref[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk_ref_pre[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clkfb_ref[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dci_disable_dq[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dci_disable_dqs[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ddr3_a[14:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ddr3_ba[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ddr3_cas[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ddr3_cke[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ddr3_clk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ddr3_nclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ddr3_odt[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ddr3_ras[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ddr3_we[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.din[63:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.din_dm[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dly_addr[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dly_data[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dly_ready[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dml[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dmu[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dout[63:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dq[15:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dqsl[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dqsu[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.iclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.iclk_pre[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.in_a[29:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.in_ba[5:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.in_cas[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.in_cke[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.in_odt[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.in_ras[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.in_tri[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.in_we[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.inv_clk_div[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ld_cmda[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ld_data_h[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ld_data_l[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ld_delay[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ld_mmcm[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.locked[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.locked_mmcm[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.locked_pll[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mclk_pre[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ndqsl[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ndqsu[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ps_out[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ps_rdy[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst_in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.set[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.tin_dq[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.tin_dqs[7:0]
+@1401200
+-phy_top_i
+@800200
+-mmcm_phase_cntr
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfbin[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfbout[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfboutb[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkin[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0b[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout1[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout1b[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout2[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout2b[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout3[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout3b[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout4[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout5[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout6[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.diff[8:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.locked[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_busy[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_din[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_dout[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_dout_r[7:0]
+@29
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_ready[0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start0[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_target[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_we[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.psclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.psdone[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.psen[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.psincdec[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.pwrdwn[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.rst[0]
+@1000200
+-mmcm_phase_cntr
+@c00200
+-idelay_ctrl_i
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_ctrl_i.rdy[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_ctrl_i.refclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_ctrl_i.rst[0]
+@1401200
+-idelay_ctrl_i
+@c00200
+-ddrc_control_i
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.busy[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.busy_r[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.clk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.cmda_en_r[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.cmda_tri[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dly_addr[6:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dly_data[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dly_ld_r[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dly_set[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dly_set_r[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dqm_pattern[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dqm_pattern_r[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dqs_pattern[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dqs_pattern_r[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_half_empty[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_nempty[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_re[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.inv_clk_div[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.inv_clk_div_r[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.ld_delay[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.mclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.port0_int_page[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.port0_int_page_r[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.port0_page[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.port0_page_r[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.port1_int_page[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.port1_int_page_r[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.port1_page[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.port1_page_r[1:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.pre_waddr[12:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.rst[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.run_addr[10:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.run_chn[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.run_seq[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.run_seq_r[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.selected[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.selected_busy[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.start_wburst[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.waddr[12:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.waddr_fifo_out[12:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.waddr_fifo_out_r[12:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wdata[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wdata_fifo_out[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wdata_fifo_out_r[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wr_en[0]
+@1401200
+-ddrc_control_i
+@c00200
+-fifo_cross_clocks
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.addr_diff[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.data_in[44:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.data_out[44:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.half_empty[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.nempty[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.raddr[3:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.raddr_gray[3:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.raddr_gray_top3[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.raddr_gray_top3_wclk[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.raddr_plus1[3:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.raddr_plus1_gray_top3[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.raddr_top3_wclk[2:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.rclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.re[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.rst[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.waddr[3:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.waddr_gray[3:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.waddr_gray_rclk[3:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.waddr_plus1[3:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.waddr_plus1_gray[3:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.waddr_top3[2:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.wclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.we[0]
+@1401200
+-fifo_cross_clocks
+@c00200
+-phy_cmd_i
+@28
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.DQSU[0]
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+@22
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+@28
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+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDCLK[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDDML[0]
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+@22
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+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDNCLK[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDODT[0]
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+@22
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+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.buf_wr[0]
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+@22
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+@28
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+@28
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+ddrc_test01_testbench.ddrc_test01_i.axi_rresp[1:0]
+ddrc_test01_testbench.ddrc_test01_i.axi_rst[0]
+ddrc_test01_testbench.ddrc_test01_i.axi_rvalid[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axi_wdata[31:0]
+ddrc_test01_testbench.ddrc_test01_i.axi_wid[11:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axi_wlast[0]
+ddrc_test01_testbench.ddrc_test01_i.axi_wready[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axi_wstb[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axi_wvalid[0]
+ddrc_test01_testbench.ddrc_test01_i.axird_bram_rclk[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axird_bram_rdata[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axird_bram_regen[0]
+ddrc_test01_testbench.ddrc_test01_i.axird_bram_ren[0]
+ddrc_test01_testbench.ddrc_test01_i.axird_dev_busy[0]
+ddrc_test01_testbench.ddrc_test01_i.axird_dev_ready[0]
+ddrc_test01_testbench.ddrc_test01_i.axird_start_burst[0]
+ddrc_test01_testbench.ddrc_test01_i.axiwr_bram_wclk[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axiwr_bram_wdata[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axiwr_bram_wen[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axiwr_bram_wstb[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axiwr_dev_busy[0]
+ddrc_test01_testbench.ddrc_test01_i.axiwr_dev_ready[0]
+ddrc_test01_testbench.ddrc_test01_i.axiwr_start_burst[0]
+ddrc_test01_testbench.ddrc_test01_i.cmda_tri[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.dly_addr[6:0]
+ddrc_test01_testbench.ddrc_test01_i.dly_data[7:0]
+ddrc_test01_testbench.ddrc_test01_i.dqm_pattern[7:0]
+ddrc_test01_testbench.ddrc_test01_i.dqs_pattern[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.en_cmd0_wr[0]
+ddrc_test01_testbench.ddrc_test01_i.en_port0_rd[0]
+ddrc_test01_testbench.ddrc_test01_i.en_port0_regen[0]
+ddrc_test01_testbench.ddrc_test01_i.en_port1_wr[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.fclk[3:0]
+ddrc_test01_testbench.ddrc_test01_i.frst[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.inv_clk_div[0]
+ddrc_test01_testbench.ddrc_test01_i.ld_delay[0]
+ddrc_test01_testbench.ddrc_test01_i.locked[0]
+ddrc_test01_testbench.ddrc_test01_i.mclk[0]
+ddrc_test01_testbench.ddrc_test01_i.port0_int_page[1:0]
+ddrc_test01_testbench.ddrc_test01_i.port0_page[1:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.port0_rdata[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.port1_int_page[1:0]
+ddrc_test01_testbench.ddrc_test01_i.port1_page[1:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps_out[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps_rdy[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.run_addr[10:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.run_busy[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.run_chn[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.run_seq[0]
+ddrc_test01_testbench.ddrc_test01_i.select_port0[0]
+ddrc_test01_testbench.ddrc_test01_i.select_status[0]
+ddrc_test01_testbench.ddrc_test01_i.set[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.status_rdata[31:0]
+@1401200
+-ddrc_test01
+@c00200
+-axibram_write_i
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aclk[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_half_full[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty_ready[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awaddr[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awburst[1:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awburst_out[1:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awid[11:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awid_out[11:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awlen[3:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awlen_out[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awready[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awsize[1:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awsize_out[1:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awvalid[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bid[11:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_waddr[12:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_wclk[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_wdata[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_we_w[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_wen[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_wstb[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bready[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bresp[1:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bresp_in[1:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bvalid[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.dev_ready[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.dev_ready_r[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.rst[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.start_burst[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.start_write_burst_w[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.w_half_full[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.w_nempty[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.w_nempty_ready[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wburst[1:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata[31:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_out[31:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wid[11:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wid_out[11:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wlast[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wlast_out[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wlen[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wready[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.write_in_progress[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.write_in_progress_w[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.write_left[3:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb[3:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb_out[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wvalid[0]
+@1401200
+-axibram_write_i
+@c00200
+-wresp_i
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.clk[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.we[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.wem[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.wa[3:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.data_in[13:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.inreg[13:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.fill[4:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.next_fill[4:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.full[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.half_full[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.just_one[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.nempty[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.re[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.rem[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.out_full[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.ra[3:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.outreg[13:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.data_out[13:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.rst[0]
+@1401200
+-wresp_i
+@800200
+-waddr_i
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.clk[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.fill[4:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.full[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.half_full[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.just_one[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.nempty[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.next_fill[4:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.out_full[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.ra[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.re[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.rem[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.rst[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wa[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.we[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wem[0]
+@1000200
+-waddr_i
+@c00200
+-wdata_i
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.clk[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_in[48:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_out[48:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.fill[4:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.full[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.half_full[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.inreg[48:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.just_one[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.nempty[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.next_fill[4:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.out_full[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.outreg[48:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.ra[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.re[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.rem[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.rst[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wa[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.we[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wem[0]
+@1401200
+-wdata_i
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/ddrc_test01_testbench.tf b/ddrc_test01_testbench.tf
new file mode 100644
index 0000000..e6f5036
--- /dev/null
+++ b/ddrc_test01_testbench.tf
@@ -0,0 +1,731 @@
+/*******************************************************************************
+ * Module: ddrc_test01_testbench
+ * Date:2014-05-20  
+ * Author: Andrey Filippov
+ * Description: testbench for ddrc_test01
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * ddrc_test01_testbench.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  ddrc_test01_testbench.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  ddrc_test01_testbench #(
+    parameter PHASE_WIDTH =     8,
+    parameter SLEW_DQ =         "SLOW",
+    parameter SLEW_DQS =        "SLOW",
+    parameter SLEW_CMDA =       "SLOW",
+    parameter SLEW_CLK =       "SLOW",
+    parameter IBUF_LOW_PWR =    "TRUE",
+    parameter real REFCLK_FREQUENCY = 300.0,
+    parameter HIGH_PERFORMANCE_MODE = "FALSE",
+    parameter CLKIN_PERIOD          = 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to             | 6.667
+    parameter CLKFBOUT_MULT =       8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE  | 16
+    parameter CLKFBOUT_MULT_REF =   9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE  | 6
+    parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
+    parameter DIVCLK_DIVIDE=        1, //                                                                      | 3
+    parameter CLKFBOUT_PHASE =      0.000,
+    parameter ICLK_PHASE =          0.000,
+    parameter CLK_PHASE =           0.000,
+    parameter CLK_DIV_PHASE =       0.000,
+    parameter MCLK_PHASE =          90.000,
+    parameter REF_JITTER1 =         0.010,
+    parameter SS_EN =              "FALSE",
+    parameter SS_MODE =      "CENTER_HIGH",
+    parameter SS_MOD_PERIOD =       10000,
+    parameter CMD_PAUSE_BITS=       6,
+    parameter CMD_DONE_BIT=         6,
+    parameter AXI_WR_ADDR_BITS =   13,
+    parameter AXI_RD_ADDR_BITS =   13,
+    parameter CONTROL_ADDR =        'h1000, // AXI write address of control write registers
+    parameter CONTROL_ADDR_MASK =   'h1400, // AXI write address of control registers
+    parameter STATUS_ADDR =         'h1400, // AXI write address of status read registers
+    parameter STATUS_ADDR_MASK =    'h1400, // AXI write address of status registers
+    parameter BUSY_WR_ADDR =        'h1800, // AXI write address to generate busy
+    parameter BUSY_WR_ADDR_MASK =   'h1c00, // AXI write address mask to generate busy
+    parameter CMD0_ADDR =           'h0800, // AXI write to command sequence memory
+    parameter CMD0_ADDR_MASK =      'h1800, // AXI read address mask for the command sequence memory
+    parameter PORT0_RD_ADDR =       'h0000, // AXI read address to generate busy
+    parameter PORT0_RD_ADDR_MASK =  'h1c00, // AXI read address mask to generate busy
+    parameter PORT1_WR_ADDR =       'h0400, // AXI read address to generate busy
+    parameter PORT1_WR_ADDR_MASK =  'h1c00,  // AXI read address mask to generate busy
+    // relative address parameters below to be ORed with CONTROL_ADDR and CONTROL_ADDR_MASK respectively
+    parameter DLY_LD_REL =          'h080,  // address to generate delay load
+    parameter DLY_LD_REL_MASK =     'h380,  // address mask to generate delay load
+    parameter DLY_SET_REL =         'h070,  // address to generate delay set
+    parameter DLY_SET_REL_MASK =    'h3ff,  // address mask to generate delay set
+    parameter RUN_CHN_REL =         'h000,  // address to set sequnecer channel and  run (4 LSB-s - channel)
+    parameter RUN_CHN_REL_MASK =    'h3f0,  // address mask to generate sequencer channel/run
+    parameter PATTERNS_REL =        'h020,  // address to set DQM and DQS patterns (16'h0055)
+    parameter PATTERNS_REL_MASK =   'h3ff,  // address mask to set DQM and DQS patterns
+    parameter PAGES_REL =           'h021,  // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
+    parameter PAGES_REL_MASK =      'h3ff,  // address mask to set DQM and DQS patterns
+    parameter CMDA_EN_REL =         'h022,  // address to enable('h823)/disable('h822) command/address outputs  
+    parameter CMDA_EN_REL_MASK =    'h3fe,  // address mask for command/address outputs
+    parameter EXTRA_REL =           'h024,  // address to set extra parameters (currently just inv_clk_div)
+    parameter EXTRA_REL_MASK =      'h3ff,   // address mask for extra parameters
+    
+    // simulation-specific parameters
+    parameter integer AXI_RDADDR_LATENCY=2,
+    parameter integer AXI_WRADDR_LATENCY=4,
+    parameter integer AXI_WRDATA_LATENCY=1,
+    parameter integer AXI_TASK_HOLD=1.0 
+)();
+`ifdef IVERILOG              
+//    $display("IVERILOG is defined");
+    `include "IVERILOG_INCLUDE.v"
+`else
+//    $display("IVERILOG is not defined");
+    parameter lxtname = "x393.lxt";
+`endif
+`define DEBUG_WR_SINGLE 1  
+  // DDR3 signals
+  wire        SDCLK;  // output
+  wire        SDNCLK; // output
+  wire [14:0] SDA;    // output[14:0] 
+  wire [ 2:0] SDBA;   // output[2:0] 
+  wire        SDWE;   // output
+  wire        SDRAS;  // output
+  wire        SDCAS;  // output
+  wire        SDCKE;  // output
+  wire        SDODT;  // output
+  wire [15:0] SDD;    // inout[15:0] 
+  wire        SDDML;  // inout
+  wire        DQSL;   // inout
+  wire        NDQSL;  // inout
+  wire        SDDMU;  // inout
+  wire        DQSU;   // inout
+  wire        NDQSU;  // inout
+  
+  
+  // Simulation signals
+  reg [11:0] ARID_IN_r;
+  reg [31:0] ARADDR_IN_r;
+  reg  [3:0] ARLEN_IN_r;
+  reg  [2:0] ARSIZE_IN_r;
+  reg  [1:0] ARBURST_IN_r;
+  reg [11:0] AWID_IN_r;
+  reg [31:0] AWADDR_IN_r;
+  reg  [3:0] AWLEN_IN_r;
+  reg  [2:0] AWSIZE_IN_r;
+  reg  [1:0] AWBURST_IN_r;
+
+  reg [11:0] WID_IN_r;
+  reg [31:0] WDATA_IN_r;
+  reg [ 3:0] WSTRB_IN_r;
+  reg        WLAST_IN_r;
+
+  wire [ 9:0] SIMUL_AXI_ADDR_W; 
+  // SuppressWarnings VEditor : assigned in $readmem() system task
+  wire        SIMUL_AXI_MISMATCH;
+  reg  [31:0] SIMUL_AXI_READ;
+  reg  [ 9:0] SIMUL_AXI_ADDR;
+  reg         SIMUL_AXI_FULL; // some data available
+
+
+
+  reg        CLK;
+  reg        RST;
+  reg        AR_SET_CMD_r;
+  wire       AR_READY;
+
+  reg        AW_SET_CMD_r;
+  wire       AW_READY;
+
+  reg        W_SET_CMD_r;
+  wire       W_READY;
+
+  wire [11:0]  #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r;
+  wire [31:0]  #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r;
+  wire  [3:0]  #(AXI_TASK_HOLD) ARLEN_IN = ARLEN_IN_r;
+  wire  [2:0]  #(AXI_TASK_HOLD) ARSIZE_IN = ARSIZE_IN_r;
+  wire  [1:0]  #(AXI_TASK_HOLD) ARBURST_IN = ARBURST_IN_r;
+  wire [11:0]  #(AXI_TASK_HOLD) AWID_IN = AWID_IN_r;
+  wire [31:0]  #(AXI_TASK_HOLD) AWADDR_IN = AWADDR_IN_r;
+  wire  [3:0]  #(AXI_TASK_HOLD) AWLEN_IN = AWLEN_IN_r;
+  wire  [2:0]  #(AXI_TASK_HOLD) AWSIZE_IN = AWSIZE_IN_r;
+  wire  [1:0]  #(AXI_TASK_HOLD) AWBURST_IN = AWBURST_IN_r;
+  wire [11:0]  #(AXI_TASK_HOLD) WID_IN = WID_IN_r;
+  wire [31:0]  #(AXI_TASK_HOLD) WDATA_IN = WDATA_IN_r;
+  wire [ 3:0]  #(AXI_TASK_HOLD) WSTRB_IN = WSTRB_IN_r;
+  wire         #(AXI_TASK_HOLD) WLAST_IN = WLAST_IN_r;
+  wire         #(AXI_TASK_HOLD) AR_SET_CMD = AR_SET_CMD_r;
+  wire         #(AXI_TASK_HOLD) AW_SET_CMD = AW_SET_CMD_r;
+  wire         #(AXI_TASK_HOLD) W_SET_CMD =  W_SET_CMD_r;
+
+  reg  [3:0] RD_LAG;  // ready signal lag in axi read channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)   
+  reg  [3:0] B_LAG;   // ready signal lag in axi arete response channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)   
+
+// Simulation modules interconnection
+  wire [11:0] arid;
+  wire [31:0] araddr;
+  wire [3:0]  arlen;
+  wire [2:0]  arsize;
+  wire [1:0]  arburst;
+  // SuppressWarnings VEditor : assigned in $readmem() system task
+  wire [3:0]  arcache;
+  // SuppressWarnings VEditor : assigned in $readmem() system task
+  wire [2:0]  arprot;
+  wire        arvalid;
+  wire        arready;
+
+  wire [11:0] awid;
+  wire [31:0] awaddr;
+  wire [3:0]  awlen;
+  wire [2:0]  awsize;
+  wire [1:0]  awburst;
+  // SuppressWarnings VEditor : assigned in $readmem() system task
+  wire [3:0]  awcache;
+  // SuppressWarnings VEditor : assigned in $readmem() system task
+  wire [2:0]  awprot;
+  wire        awvalid;
+  wire        awready;
+
+  wire [11:0] wid;
+  wire [31:0] wdata;
+  wire [3:0]  wstrb;
+  wire        wlast;
+  wire        wvalid;
+  wire        wready;
+  
+  wire [31:0] rdata;
+  // SuppressWarnings VEditor : assigned in $readmem() system task
+  wire [11:0] rid;
+  wire        rlast;
+  // SuppressWarnings VEditor : assigned in $readmem() system task
+  wire  [1:0] rresp;
+  wire        rvalid;
+  wire        rready;
+  wire        rstb=rvalid && rready;
+
+  // SuppressWarnings VEditor : assigned in $readmem() system task
+  wire  [1:0] bresp;
+  // SuppressWarnings VEditor : assigned in $readmem() system task
+  wire [11:0] bid;
+  wire        bvalid;
+  wire        bready;
+  
+always #(CLKIN_PERIOD/2) CLK <= ~CLK;
+
+  initial begin
+`ifdef IVERILOG              
+    $display("IVERILOG is defined");
+`else
+    $display("IVERILOG is not defined");
+`endif
+
+`ifdef ICARUS              
+    $display("ICARUS is defined");
+`else
+    $display("ICARUS is not defined");
+`endif
+  
+    $dumpfile(lxtname);
+  // SuppressWarnings VEditor : assigned in $readmem() system task
+    $dumpvars(0,ddrc_test01_testbench);
+    CLK <=1'b0;
+    RST <= 1'b1;
+    AR_SET_CMD_r <= 1'b0;
+    AW_SET_CMD_r <= 1'b0;
+    W_SET_CMD_r <= 1'b0;
+    #100000; // same as glbl
+    repeat (20) @(posedge CLK) ;
+    RST <=1'b0;
+    axi_set_b_lag(0); //(1);
+    axi_set_rd_lag(0);
+    axi_set_delays;
+    // write memory
+//    test_axi_1;
+    // read memory
+//    test_axi_2;
+    repeat (512) @(posedge CLK) ;
+    
+#100;
+    #10000;
+    $display("finish testbench 1");
+    $finish;
+  end
+
+// protect from never end
+  initial begin
+//  #10000000;
+  #110000;
+    $display("finish testbench 2");
+  $finish;
+  end
+
+
+
+assign ddrc_test01_i.ps7_i.FCLKCLK=        {4{CLK}};
+assign ddrc_test01_i.ps7_i.FCLKRESETN=     {4{~RST}};
+// Read address
+assign ddrc_test01_i.ps7_i.MAXIGP0ARADDR=  araddr;
+assign ddrc_test01_i.ps7_i.MAXIGP0ARVALID= arvalid;
+assign arready=                            ddrc_test01_i.ps7_i.MAXIGP0ARREADY;
+assign ddrc_test01_i.ps7_i.MAXIGP0ARID=    arid; 
+assign ddrc_test01_i.ps7_i.MAXIGP0ARLEN=   arlen;
+assign ddrc_test01_i.ps7_i.MAXIGP0ARSIZE=  arsize[1:0]; // arsize[2] is not used
+assign ddrc_test01_i.ps7_i.MAXIGP0ARBURST= arburst;
+// Read data
+assign rdata=                              ddrc_test01_i.ps7_i.MAXIGP0RDATA; 
+assign rvalid=                             ddrc_test01_i.ps7_i.MAXIGP0RVALID;
+assign ddrc_test01_i.ps7_i.MAXIGP0RREADY=  rready;
+assign rid=                                ddrc_test01_i.ps7_i.MAXIGP0RID;
+assign rlast=                              ddrc_test01_i.ps7_i.MAXIGP0RLAST;
+assign rresp=                              ddrc_test01_i.ps7_i.MAXIGP0RRESP;
+// Write address
+assign ddrc_test01_i.ps7_i.MAXIGP0AWADDR=  awaddr;
+assign ddrc_test01_i.ps7_i.MAXIGP0AWVALID= awvalid;
+
+assign awready=                            ddrc_test01_i.ps7_i.MAXIGP0AWREADY;
+
+//assign awready= AWREADY_AAAA;
+assign ddrc_test01_i.ps7_i.MAXIGP0AWID=awid;
+
+      // SuppressWarnings VEditor all
+//  wire [ 1:0] AWLOCK;
+      // SuppressWarnings VEditor all
+//  wire [ 3:0] AWCACHE;
+      // SuppressWarnings VEditor all
+//  wire [ 2:0] AWPROT;
+assign ddrc_test01_i.ps7_i.MAXIGP0AWLEN=   awlen;
+assign ddrc_test01_i.ps7_i.MAXIGP0AWSIZE=  awsize[1:0]; // awsize[2] is not used
+assign ddrc_test01_i.ps7_i.MAXIGP0AWBURST= awburst;
+      // SuppressWarnings VEditor all
+//  wire [ 3:0] AWQOS;
+// Write data
+assign ddrc_test01_i.ps7_i.MAXIGP0WDATA=   wdata;
+assign ddrc_test01_i.ps7_i.MAXIGP0WVALID=  wvalid;
+assign wready=                             ddrc_test01_i.ps7_i.MAXIGP0WREADY;
+assign ddrc_test01_i.ps7_i.MAXIGP0WID=     wid;
+assign ddrc_test01_i.ps7_i.MAXIGP0WLAST=   wlast;
+assign ddrc_test01_i.ps7_i.MAXIGP0WSTRB=   wstrb;
+// Write responce
+assign bvalid=                             ddrc_test01_i.ps7_i.MAXIGP0BVALID;
+assign ddrc_test01_i.ps7_i.MAXIGP0BREADY=  bready;
+assign bid=                                ddrc_test01_i.ps7_i.MAXIGP0BID;
+assign bresp=                              ddrc_test01_i.ps7_i.MAXIGP0BRESP;
+  
+// Top module under test
+    ddrc_test01 #(
+        .PHASE_WIDTH           (PHASE_WIDTH),
+        .SLEW_DQ               (SLEW_DQ),
+        .SLEW_DQS              (SLEW_DQS),
+        .SLEW_CMDA             (SLEW_CMDA),
+        .SLEW_CLK              (SLEW_CLK),
+        .IBUF_LOW_PWR          (IBUF_LOW_PWR),
+        .REFCLK_FREQUENCY      (REFCLK_FREQUENCY),
+        .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
+        .CLKIN_PERIOD          (CLKIN_PERIOD),
+        .CLKFBOUT_MULT         (CLKFBOUT_MULT),
+        .CLKFBOUT_MULT_REF     (CLKFBOUT_MULT_REF),
+        .CLKFBOUT_DIV_REF      (CLKFBOUT_DIV_REF),
+        .DIVCLK_DIVIDE         (DIVCLK_DIVIDE),
+        .CLKFBOUT_PHASE        (CLKFBOUT_PHASE),
+        .ICLK_PHASE            (ICLK_PHASE),
+        .CLK_PHASE             (CLK_PHASE),
+        .CLK_DIV_PHASE         (CLK_DIV_PHASE),
+        .MCLK_PHASE            (MCLK_PHASE),
+        .REF_JITTER1           (REF_JITTER1),
+        .SS_EN                 (SS_EN),
+        .SS_MODE               (SS_MODE),
+        .SS_MOD_PERIOD         (SS_MOD_PERIOD),
+        .CMD_PAUSE_BITS        (CMD_PAUSE_BITS),
+        .CMD_DONE_BIT          (CMD_DONE_BIT),
+        .AXI_WR_ADDR_BITS      (AXI_WR_ADDR_BITS),
+        .AXI_RD_ADDR_BITS      (AXI_RD_ADDR_BITS),
+        .CONTROL_ADDR          (CONTROL_ADDR),
+        .CONTROL_ADDR_MASK     (CONTROL_ADDR_MASK),
+        .STATUS_ADDR           (STATUS_ADDR),
+        .STATUS_ADDR_MASK      (STATUS_ADDR_MASK),
+        .BUSY_WR_ADDR          (BUSY_WR_ADDR),
+        .BUSY_WR_ADDR_MASK     (BUSY_WR_ADDR_MASK),
+        .CMD0_ADDR             (CMD0_ADDR),
+        .CMD0_ADDR_MASK        (CMD0_ADDR_MASK),
+        .PORT0_RD_ADDR         (PORT0_RD_ADDR),
+        .PORT0_RD_ADDR_MASK    (PORT0_RD_ADDR_MASK),
+        .PORT1_WR_ADDR         (PORT1_WR_ADDR),
+        .PORT1_WR_ADDR_MASK    (PORT1_WR_ADDR_MASK),
+        .DLY_LD_REL            (DLY_LD_REL),
+        .DLY_LD_REL_MASK       (DLY_LD_REL_MASK),
+        .DLY_SET_REL           (DLY_SET_REL),
+        .DLY_SET_REL_MASK      (DLY_SET_REL_MASK),
+        .RUN_CHN_REL           (RUN_CHN_REL),
+        .RUN_CHN_REL_MASK      (RUN_CHN_REL_MASK),
+        .PATTERNS_REL          (PATTERNS_REL),
+        .PATTERNS_REL_MASK     (PATTERNS_REL_MASK),
+        .PAGES_REL             (PAGES_REL),
+        .PAGES_REL_MASK        (PAGES_REL_MASK),
+        .CMDA_EN_REL           (CMDA_EN_REL),
+        .CMDA_EN_REL_MASK      (CMDA_EN_REL_MASK),
+        .EXTRA_REL             (EXTRA_REL),
+        .EXTRA_REL_MASK        (EXTRA_REL_MASK)
+        
+    ) ddrc_test01_i (
+        .SDCLK   (SDCLK), // output
+        .SDNCLK  (SDNCLK), // output
+        .SDA     (SDA[14:0]), // output[14:0] 
+        .SDBA    (SDBA[2:0]), // output[2:0] 
+        .SDWE    (SDWE), // output
+        .SDRAS   (SDRAS), // output
+        .SDCAS   (SDCAS), // output
+        .SDCKE   (SDCKE), // output
+        .SDODT   (SDODT), // output
+        .SDD     (SDD[15:0]), // inout[15:0] 
+        .SDDML   (SDDML), // inout
+        .DQSL    (DQSL), // inout
+        .NDQSL   (NDQSL), // inout
+        .SDDMU   (SDDMU), // inout
+        .DQSU    (DQSU), // inout
+        .NDQSU   (NDQSU) // inout
+    );
+    
+    
+// Simulation modules    
+simul_axi_master_rdaddr
+#(
+  .ID_WIDTH(12),
+  .ADDRESS_WIDTH(32),
+  .LATENCY(AXI_RDADDR_LATENCY),          // minimal delay between inout and output ( 0 - next cycle)
+  .DEPTH(8),            // maximal number of commands in FIFO
+  .DATA_DELAY(3.5),
+  .VALID_DELAY(4.0)
+) simul_axi_master_rdaddr_i (
+    .clk(CLK),
+    .reset(RST),
+    .arid_in(ARID_IN[11:0]),
+    .araddr_in(ARADDR_IN[31:0]),
+    .arlen_in(ARLEN_IN[3:0]),
+    .arsize_in(ARSIZE_IN[2:0]),
+    .arburst_in(ARBURST_IN[1:0]),
+    .arcache_in(4'b0),
+    .arprot_in(3'b0), //     .arprot_in(2'b0),
+    .arid(arid[11:0]),
+    .araddr(araddr[31:0]),
+    .arlen(arlen[3:0]),
+    .arsize(arsize[2:0]),
+    .arburst(arburst[1:0]),
+    .arcache(arcache[3:0]),
+    .arprot(arprot[2:0]),
+    .arvalid(arvalid),
+    .arready(arready),
+    .set_cmd(AR_SET_CMD),  // latch all other input data at posedge of clock
+    .ready(AR_READY)     // command/data FIFO can accept command
+);
+
+simul_axi_master_wraddr
+#(
+  .ID_WIDTH(12),
+  .ADDRESS_WIDTH(32),
+  .LATENCY(AXI_WRADDR_LATENCY),          // minimal delay between inout and output ( 0 - next cycle)
+  .DEPTH(8),            // maximal number of commands in FIFO
+  .DATA_DELAY(3.5),
+  .VALID_DELAY(4.0)
+) simul_axi_master_wraddr_i (
+    .clk(CLK),
+    .reset(RST),
+    .awid_in(AWID_IN[11:0]),
+    .awaddr_in(AWADDR_IN[31:0]),
+    .awlen_in(AWLEN_IN[3:0]),
+    .awsize_in(AWSIZE_IN[2:0]),
+    .awburst_in(AWBURST_IN[1:0]),
+    .awcache_in(4'b0),
+    .awprot_in(3'b0), //.awprot_in(2'b0),
+    .awid(awid[11:0]),
+    .awaddr(awaddr[31:0]),
+    .awlen(awlen[3:0]),
+    .awsize(awsize[2:0]),
+    .awburst(awburst[1:0]),
+    .awcache(awcache[3:0]),
+    .awprot(awprot[2:0]),
+    .awvalid(awvalid),
+    .awready(awready),
+    .set_cmd(AW_SET_CMD),  // latch all other input data at posedge of clock
+    .ready(AW_READY)     // command/data FIFO can accept command
+);
+
+simul_axi_master_wdata
+#(
+  .ID_WIDTH(12),
+  .DATA_WIDTH(32),
+  .WSTB_WIDTH(4),
+  .LATENCY(AXI_WRDATA_LATENCY),          // minimal delay between inout and output ( 0 - next cycle)
+  .DEPTH(8),            // maximal number of commands in FIFO
+  .DATA_DELAY(3.2),
+  .VALID_DELAY(3.6)
+) simul_axi_master_wdata_i (
+    .clk(CLK),
+    .reset(RST),
+    .wid_in(WID_IN[11:0]),
+    .wdata_in(WDATA_IN[31:0]),
+    .wstrb_in(WSTRB_IN[3:0]),
+    .wlast_in(WLAST_IN),
+    .wid(wid[11:0]),
+    .wdata(wdata[31:0]),
+    .wstrb(wstrb[3:0]),
+    .wlast(wlast),
+    .wvalid(wvalid),
+    .wready(wready),
+    .set_cmd(W_SET_CMD),  // latch all other input data at posedge of clock
+    .ready(W_READY)        // command/data FIFO can accept command
+);
+
+simul_axi_slow_ready simul_axi_slow_ready_read_i(
+    .clk(CLK),
+    .reset(RST), //input         reset,
+    .delay(RD_LAG), //input  [3:0]  delay,
+    .valid(rvalid), // input         valid,
+    .ready(rready)  //output        ready
+    );
+
+simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(
+    .clk(CLK),
+    .reset(RST), //input         reset,
+    .delay(B_LAG), //input  [3:0]  delay,
+    .valid(bvalid), // input         valid,
+    .ready(bready)  //output        ready
+    );
+
+simul_axi_read simul_axi_read_i(
+  .clk(CLK),
+  .reset(RST),
+  .last(rlast),
+  .data_stb(rstb),
+  .raddr(ARADDR_IN[11:2]), 
+  .rlen(ARLEN_IN),
+  .rcmd(AR_SET_CMD),
+  .addr_out(SIMUL_AXI_ADDR_W),
+  .burst(),     // burst in progress - just debug
+  .err_out());  // data last does not match predicted or FIFO over/under run - just debug
+    
+    
+    
+// SuppressWarnings VEditor all - these variables are just for viewing, not used anywhere else
+  reg DEBUG1, DEBUG2, DEBUG3;
+  
+//  Tasks
+// top simulation tasks
+// base addresses  
+    localparam BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2; // 'h0000  << 2
+    localparam BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2; // 'h0000 << 2 = 'h000
+    localparam BASEADDR_CMD0 =     CMD0_ADDR << 2;     // 'h0800 << 2 = 'h2000
+//    localparam BASEADDR_CTRL =     CONTROL_ADDR << 2;
+    localparam BASEADDR_CTRL =     (CONTROL_ADDR | BUSY_WR_ADDR) << 2; // with busy
+    localparam BASEADDR_STATUS =   STATUS_ADDR << 2;   // 'h0800 << 2 = 'h2000
+    localparam BASEADDR_DLY_LD =  BASEADDR_CTRL | (DLY_LD_REL <<2);  // 'h080, address to generate delay load
+    localparam BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2);  // 'h070, address to generate delay set
+    localparam BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2);  // 'h000, address to set sequnecer channel and  run (4 LSB-s - channel)
+    localparam BASEADDR_PATTERNS =BASEADDR_CTRL | (PATTERNS_REL<<2); // 'h020, address to set DQM and DQS patterns (16'h0055)
+    localparam BASEADDR_PAGES =   BASEADDR_CTRL | (PAGES_REL<<2);    // 'h021, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
+    localparam BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2);  // 'h022, address to enable('h823)/disable('h822) command/address outputs  
+    localparam BASEADDR_EXTRA =   BASEADDR_CTRL | (EXTRA_REL<<2);    // 'h024, address to set extra parameters (currently just inv_clk_div)
+    localparam BASEADDRESS_LANE0 = BASEADDR_DLY_LD;  
+    localparam BASEADDRESS_LANE1 = BASEADDR_DLY_LD+('h20<<2);  
+    localparam BASEADDRESS_CMDA  = BASEADDR_DLY_LD+('h40<<2);
+    localparam BASEADDRESS_PHASE = BASEADDR_DLY_LD+('h60<<2);
+      
+
+    localparam DLY_LANE0= 152'h74737271706f6e6d6c7574737271706f6e6d6c; // idelay dqs, idelay dq[7:0, odelay dqm, odelay ddqs, odelay dq[7:0]
+    localparam DLY_LANE1= 152'h74737271706f6e6d6c7574737271706f6e6d6c; // idelay dqs, idelay dq[7:0, odelay dqm, odelay ddqs, odelay dq[7:0]
+    localparam DLY_CMDA=  256'h5f5e5d5c5b5a59585756555453525150004e4b4c4b4a49484746454443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
+//    localparam DLY_PHASE= 8'h25; // mmcm fine phase shift
+    localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
+    
+
+// initialize delays
+    task axi_set_delays;
+     integer i;
+     begin
+        for (i=0;i<19;i=i+1) begin
+            axi_write_single(BASEADDRESS_LANE0 + (i<<2), (DLY_LANE0 >> (i<<3)) & 32'hff);
+        end
+        for (i=0;i<19;i=i+1) begin
+            axi_write_single(BASEADDRESS_LANE1 + (i<<2), (DLY_LANE1 >> (i<<3)) & 32'hff);
+        end
+        for (i=0;i<32;i=i+1) begin
+            axi_write_single(BASEADDRESS_CMDA + (i<<2), (DLY_CMDA >> (i<<3)) & 32'hff);
+        end
+        axi_write_single(BASEADDR_DLY_SET, 0); // set all dealys - remove after fixed axi_set_phase
+        axi_set_phase(DLY_PHASE);
+        axi_write_single(BASEADDR_DLY_SET, 0); // set all dealys
+     end
+    endtask
+
+    task axi_set_phase;
+        input [PHASE_WIDTH-1:0] phase;
+        begin
+            axi_write_single(BASEADDRESS_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase});
+        end
+    endtask
+
+
+// Low-level tasks     
+    task axi_set_rd_lag;
+        input [3:0] lag;
+        begin
+            @(posedge CLK);
+            RD_LAG <= lag;
+        end
+    endtask
+
+    task axi_set_b_lag;
+        input [3:0] lag;
+        begin
+            @(posedge CLK);
+            B_LAG <= lag;
+        end
+    endtask
+   
+    reg [11:0] GLOBAL_WRITE_ID=0;
+    
+    task axi_write_single; // address in bytes, not words
+        input [31:0] address;
+        input [31:0] data;
+        begin
+`ifdef DEBUG_WR_SINGLE
+          $display("axi_write_single %h:%h @ %t",address,data,$time);
+`endif                
+          axi_write_addr_data(
+                    GLOBAL_WRITE_ID,    // id
+//                    address << 2, // addr
+                    address & 32'hfffffffc, // addr
+                    data,
+                    4'h0, // len - single
+                    1,    // burst type - increment
+                    1'b1, // data_en
+                    4'hf, // wstrb
+                    1'b1 // last
+                );
+          GLOBAL_WRITE_ID <= GLOBAL_WRITE_ID+1;
+        end
+    endtask
+   
+    task axi_write_addr_data;
+        input [11:0] id;
+        input [31:0] addr;
+        input [31:0] data;
+        input [ 3:0] len;
+        input [ 1:0] burst;
+        input        data_en; // if 0 - do not send data, only address
+        input [ 3:0] wstrb;
+        input        last;
+        reg          data_sent;
+//        wire         data_sent_d;
+//        assign #(.1) data_sent_d= data_sent;
+        begin
+            wait (!CLK && AW_READY);
+            AWID_IN_r    <= id;
+            AWADDR_IN_r  <= addr;
+            AWLEN_IN_r   <= len;
+            AWSIZE_IN_r  <= 3'b010;
+            AWBURST_IN_r <= burst;
+            AW_SET_CMD_r <= 1'b1;
+            if (data_en && W_READY) begin
+                WID_IN_r <= id;
+                WDATA_IN_r <= data;
+                WSTRB_IN_r <= wstrb;
+                WLAST_IN_r <= last;
+                W_SET_CMD_r <= 1'b1; 
+                data_sent <= 1'b1;
+            end else begin
+                data_sent <= 1'b0;
+            end
+            DEBUG1 <=1'b1;
+            wait (CLK);
+            DEBUG1 <=1'b0;
+            AWID_IN_r    <= 'hz;
+            AWADDR_IN_r  <= 'hz;
+            AWLEN_IN_r   <= 'hz;
+            AWSIZE_IN_r  <= 'hz;
+            AWBURST_IN_r <= 'hz;
+            AW_SET_CMD_r <= 1'b0;
+            DEBUG2 <=1'b1;
+            if (data_sent) begin
+                WID_IN_r    <= 'hz;
+                WDATA_IN_r  <= 'hz;
+                WSTRB_IN_r  <= 'hz;
+                WLAST_IN_r  <= 'hz;
+                W_SET_CMD_r <= 1'b0; 
+            end
+// Now sent data if it was not sent simultaneously with the address
+            if (data_en && !data_sent) begin
+                DEBUG3 <=1'b1;
+                wait (!CLK && W_READY);
+                DEBUG3 <=1'b0;
+                WID_IN_r    <= id;
+                WDATA_IN_r  <= data;
+                WSTRB_IN_r  <= wstrb;
+                WLAST_IN_r  <= last;
+                W_SET_CMD_r <= 1'b1; 
+                wait (CLK);
+                DEBUG3 <=1'bx;
+                WID_IN_r    <= 'hz;
+                WDATA_IN_r  <= 'hz;
+                WSTRB_IN_r  <= 'hz;
+                WLAST_IN_r  <= 'hz;
+                W_SET_CMD_r <= 1'b0; 
+            end
+            DEBUG2 <=1'b0;
+            #0.1;
+            data_sent <= 1'b0;
+            #0.1;
+        end
+    endtask
+
+    task axi_write_data;
+        input [11:0] id;
+        input [31:0] data;
+        input [ 3:0] wstrb;
+        input        last;
+        begin
+            wait (!CLK && W_READY);
+            WID_IN_r    <= id;
+            WDATA_IN_r  <= data;
+            WSTRB_IN_r  <= wstrb;
+            WLAST_IN_r  <= last;
+            W_SET_CMD_r <= 1'b1; 
+            wait (CLK);
+            WID_IN_r    <= 12'hz;
+            WDATA_IN_r  <= 'hz;
+            WSTRB_IN_r  <= 4'hz;
+            WLAST_IN_r  <= 1'bz;
+            W_SET_CMD_r <= 1'b0;
+            #0.1;
+        end
+    endtask
+
+    task axi_read_addr;
+        input [11:0] id;
+        input [31:0] addr;
+        input [ 3:0] len;
+        input [ 1:0] burst;
+        begin
+            wait (!CLK && AR_READY);
+            ARID_IN_r    <= id;
+            ARADDR_IN_r  <= addr;
+            ARLEN_IN_r   <= len;
+            ARSIZE_IN_r  <= 3'b010;
+            ARBURST_IN_r <= burst;
+            AR_SET_CMD_r <= 1'b1;
+            wait (CLK);
+            ARID_IN_r    <= 12'hz;
+            ARADDR_IN_r  <= 'hz;
+            ARLEN_IN_r   <= 4'hz;
+            ARSIZE_IN_r  <= 3'hz;
+            ARBURST_IN_r <= 2'hz;
+            AR_SET_CMD_r <= 1'b0;
+        end
+    endtask
+
+endmodule
+
diff --git a/phy/phy_top.v b/phy/phy_top.v
index 3a18dd7..60331cd 100644
--- a/phy/phy_top.v
+++ b/phy/phy_top.v
@@ -284,7 +284,8 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
     ) mmcm_phase_cntr_i (
         .clkin               (clk_in), // input
         .clkfbin             (clk_fb), // input
-        .rst                 (rst), // input
+//        .rst                 (rst), // input
+        .rst                 (rst_in), // input
         .pwrdwn                 (1'b0), // input
         .psclk               (clk_div), // input
         .ps_we               (ld_mmcm), // input
@@ -318,7 +319,8 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
     ) pll_base_i (
         .clkin(clk_in), // input
         .clkfbin(clkfb_ref), // input
-        .rst(rst), // input
+//        .rst(rst), // input
+        .rst(rst_in), // input
         .pwrdwn(1'b0), // input
         .clkout0(clk_ref_pre), // output
         .clkout1(), // output
diff --git a/simulation_modules/simul_axi_fifo_out.v b/simulation_modules/simul_axi_fifo_out.v
new file mode 100644
index 0000000..9629bc8
--- /dev/null
+++ b/simulation_modules/simul_axi_fifo_out.v
@@ -0,0 +1,65 @@
+/**************************************
+* Module: simul_axi_fifo
+* Date:2014-03-23  
+* Author: andrey     
+*
+* Description: 
+***************************************/
+`timescale 1ns/1ps
+
+module simul_axi_fifo
+#(
+  parameter integer WIDTH=  64,         // total number of output bits
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+//  parameter OUT_DELAY = 3.5,
+  parameter integer FIFO_DEPTH=LATENCY+DEPTH+1
+//  parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
+)(
+  input              clk,
+  input              reset,
+  input  [WIDTH-1:0] data_in,
+  input              load,
+  output             input_ready,
+  output [WIDTH-1:0] data_out,
+  output             valid,
+  input              ready);
+  
+  reg  [WIDTH-1:0]   fifo [0:FIFO_DEPTH-1];
+  integer            in_address;
+  integer            out_address;
+  integer            in_count;
+  integer            out_count;
+  reg    [LATENCY:0] latency_delay_r;
+  
+  wire [LATENCY+1:0] latency_delay={latency_delay_r,load};             
+  wire               out_inc=latency_delay[LATENCY];
+  
+  assign data_out=    fifo[out_address];
+  assign valid=       out_count!=0;
+  assign input_ready= in_count<DEPTH;
+//  assign out_inc={
+
+  always @ (posedge clk or posedge reset) begin
+    if (reset) latency_delay_r <= 0;
+    else       latency_delay_r <= latency_delay[LATENCY:0];
+
+    if    (reset)  in_address <= 0;
+    else if (load) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1;
+
+    if    (reset)            out_address <= 0;
+    else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1;
+    
+    if    (reset)                       in_count <= 0;
+    else if (!(valid && ready) && load) in_count <= in_count+1;
+    else if (valid && ready && !load)   in_count <= in_count-1;
+
+    if    (reset)                          out_count <= 0;
+    else if (!(valid && ready) && out_inc) out_count <= out_count+1;
+    else if (valid && ready && !out_inc)   out_count <= out_count-1;
+  end
+  always @ (posedge clk) begin
+    if (load) fifo[in_address] <= data_in;
+  end
+  
+endmodule
\ No newline at end of file
diff --git a/simulation_modules/simul_axi_master_rdaddr.v b/simulation_modules/simul_axi_master_rdaddr.v
new file mode 100644
index 0000000..1bb0490
--- /dev/null
+++ b/simulation_modules/simul_axi_master_rdaddr.v
@@ -0,0 +1,92 @@
+/*******************************************************************************
+ * Module: simul_axi_master_rdaddr
+ * Date:2014-03-23  
+ * Author: andrey     
+ * Description: Simulation model for AXI read address channel
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * simul_axi_master_rdaddr.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_master_rdaddr.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+
+`timescale 1ns/1ps
+
+module simul_axi_master_rdaddr
+#(
+  parameter integer ID_WIDTH=12,
+  parameter integer ADDRESS_WIDTH=32,
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+  parameter DATA_DELAY = 3.5,
+  parameter VALID_DELAY = 4.0
+  
+//  parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
+)(
+    input                      clk,
+    input                      reset,
+    input  [ID_WIDTH-1:0]      arid_in,
+    input  [ADDRESS_WIDTH-1:0] araddr_in,
+    input  [3:0]               arlen_in,
+    input  [2:0]               arsize_in,
+    input  [1:0]               arburst_in,
+    input  [3:0]               arcache_in,
+    input  [2:0]               arprot_in,
+
+    output [ID_WIDTH-1:0]      arid,
+    output [ADDRESS_WIDTH-1:0] araddr,
+    output [3:0]               arlen,
+    output [2:0]               arsize,
+    output [1:0]               arburst,
+    output [3:0]               arcache,
+    output [2:0]               arprot,
+    output                     arvalid,
+    input                      arready,
+
+    input                      set_cmd,  // latch all other input data at posedge of clock
+    output                     ready     // command/data FIFO can accept command
+);
+    wire [ID_WIDTH-1:0]      arid_out;
+    wire [ADDRESS_WIDTH-1:0] araddr_out;
+    wire [3:0]               arlen_out;
+    wire [2:0]               arsize_out;
+    wire [1:0]               arburst_out;
+    wire [3:0]               arcache_out;
+    wire [2:0]               arprot_out;
+    wire                     arvalid_out;
+    
+    assign #(DATA_DELAY) arid=    arid_out;
+    assign #(DATA_DELAY) araddr=  araddr_out;
+    assign #(DATA_DELAY) arlen=   arlen_out;
+    assign #(DATA_DELAY) arsize=  arsize_out;
+    assign #(DATA_DELAY) arburst= arburst_out;
+    assign #(DATA_DELAY) arcache= arcache_out;
+    assign #(DATA_DELAY) arprot=  arprot_out;
+    assign #(VALID_DELAY) arvalid=arvalid_out;
+
+simul_axi_fifo
+    #(
+      .WIDTH(ID_WIDTH+ADDRESS_WIDTH+16),     // total number of output bits
+      .LATENCY(LATENCY),                     // minimal delay between inout and output ( 0 - next cycle)
+      .DEPTH(DEPTH)                          // maximal number of commands in FIFO
+//  parameter OUT_DELAY = 3.5,
+    ) simul_axi_fifo_i (
+    .clk(clk),         // input              clk,
+    .reset(reset),       // input              reset,
+    .data_in({arid_in,araddr_in,arlen_in,arsize_in,arburst_in,arcache_in,arprot_in}),     // input  [WIDTH-1:0] data_in,
+    .load(set_cmd),        // input              load,
+    .input_ready(ready), // output             input_ready,
+    .data_out({arid_out,araddr_out,arlen_out,arsize_out,arburst_out,arcache_out,arprot_out}),    // output [WIDTH-1:0] data_out,
+    .valid(arvalid_out),       // output             valid,
+    .ready(arready));      //  input              ready);
+
+endmodule
diff --git a/simulation_modules/simul_axi_master_wdata.v b/simulation_modules/simul_axi_master_wdata.v
new file mode 100644
index 0000000..a3d8314
--- /dev/null
+++ b/simulation_modules/simul_axi_master_wdata.v
@@ -0,0 +1,77 @@
+/*******************************************************************************
+ * Module: simul_axi_master_wdata
+ * Date:2014-03-24  
+ * Author: Andrey Filippov    
+ * Description: Simulation model for AXI write data channel
+ *
+ * Copyright (c) 2014 Elphel, Inc..
+ * simul_axi_master_wdata.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_master_wdata.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_master_wdata#(
+  parameter integer ID_WIDTH=12,
+  parameter integer DATA_WIDTH=32,
+  parameter integer WSTB_WIDTH= 4,
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+  parameter DATA_DELAY = 3.5,
+  parameter VALID_DELAY = 4.0
+)(
+    input                      clk,
+    input                      reset,
+    input  [ID_WIDTH-1:0]      wid_in,
+    input  [DATA_WIDTH-1:0]    wdata_in,
+    input  [WSTB_WIDTH-1:0]    wstrb_in,
+    input                      wlast_in,
+    output [ID_WIDTH-1:0]      wid,
+    output [DATA_WIDTH-1:0]    wdata,
+    output [WSTB_WIDTH-1:0]    wstrb,
+    output                     wlast,
+    output                     wvalid,
+    input                      wready,
+
+    input                      set_cmd,  // latch all other input data at posedge of clock
+    output                     ready     // command/data FIFO can accept command
+);
+
+    wire  [ID_WIDTH-1:0]      wid_out;
+    wire  [DATA_WIDTH-1:0]    wdata_out;
+    wire  [WSTB_WIDTH-1:0]    wstrb_out;
+    wire                      wlast_out;
+    wire                      wvalid_out;
+    
+    assign #(DATA_DELAY)  wid=    wid_out;
+    assign #(DATA_DELAY)  wdata=  wdata_out;
+    assign #(DATA_DELAY)  wstrb=  wstrb_out;
+    assign #(DATA_DELAY)  wlast=  wlast_out;
+    assign #(VALID_DELAY) wvalid= wvalid_out;
+
+simul_axi_fifo
+    #(
+      .WIDTH(ID_WIDTH+DATA_WIDTH+WSTB_WIDTH+1),  // total number of output bits
+      .LATENCY(LATENCY),                         // minimal delay between inout and output ( 0 - next cycle)
+      .DEPTH(DEPTH)                              // maximal number of commands in FIFO
+    ) simul_axi_fifo_i (
+    .clk(clk),         // input              clk,
+    .reset(reset),       // input              reset,
+    .data_in({wid_in, wdata_in, wstrb_in, wlast_in}),     // input  [WIDTH-1:0] data_in,
+    .load(set_cmd),        // input              load,
+    .input_ready(ready), // output             input_ready,
+    .data_out({wid_out, wdata_out, wstrb_out, wlast_out}),    // output [WIDTH-1:0] data_out,
+    .valid(wvalid_out),       // output             valid,
+    .ready(wready));          //  input              ready);
+
+endmodule
+
diff --git a/simulation_modules/simul_axi_master_wraddr.v b/simulation_modules/simul_axi_master_wraddr.v
new file mode 100644
index 0000000..64fedb8
--- /dev/null
+++ b/simulation_modules/simul_axi_master_wraddr.v
@@ -0,0 +1,90 @@
+/*******************************************************************************
+ * Module: simul_axi_master_wraddr
+ * Date:2014-03-24  
+ * Author: Andrey Filippov    
+ * Description: Simulation model for AXI write address channel
+ *
+ * Copyright (c) 2014 Elphel, Inc..
+ * simul_axi_master_wraddr.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_master_wraddr.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_master_wraddr
+#(
+  parameter integer ID_WIDTH=12,
+  parameter integer ADDRESS_WIDTH=32,
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+  parameter DATA_DELAY = 3.5,
+  parameter VALID_DELAY = 4.0
+)(
+    input                      clk,
+    input                      reset,
+    input  [ID_WIDTH-1:0]      awid_in,
+    input  [ADDRESS_WIDTH-1:0] awaddr_in,
+    input  [3:0]               awlen_in,
+    input  [2:0]               awsize_in,
+    input  [1:0]               awburst_in,
+    input  [3:0]               awcache_in,
+    input  [2:0]               awprot_in,
+
+    output [ID_WIDTH-1:0]      awid,
+    output [ADDRESS_WIDTH-1:0] awaddr,
+    output [3:0]               awlen,
+    output [2:0]               awsize,
+    output [1:0]               awburst,
+    output [3:0]               awcache,
+    output [2:0]               awprot,
+    output                     awvalid,
+    input                      awready,
+
+    input                      set_cmd,  // latch all other input data at posedge of clock
+    output                     ready     // command/data FIFO can accept command
+);
+    wire [ID_WIDTH-1:0]      awid_out;
+    wire [ADDRESS_WIDTH-1:0] awaddr_out;
+    wire [3:0]               awlen_out;
+    wire [2:0]               awsize_out;
+    wire [1:0]               awburst_out;
+    wire [3:0]               awcache_out;
+    wire [2:0]               awprot_out;
+    wire                     awvalid_out;
+    
+    assign #(DATA_DELAY) awid=    awid_out;
+    assign #(DATA_DELAY) awaddr=  awaddr_out;
+    assign #(DATA_DELAY) awlen=   awlen_out;
+    assign #(DATA_DELAY) awsize=  awsize_out;
+    assign #(DATA_DELAY) awburst= awburst_out;
+    assign #(DATA_DELAY) awcache= awcache_out;
+    assign #(DATA_DELAY) awprot=  awprot_out;
+    assign #(VALID_DELAY) awvalid= awvalid_out;
+
+simul_axi_fifo
+    #(
+      .WIDTH(ID_WIDTH+ADDRESS_WIDTH+16),     // total number of output bits
+      .LATENCY(LATENCY),                     // minimal delay between inout and output ( 0 - next cycle)
+      .DEPTH(DEPTH)                          // maximal number of commands in FIFO
+//  parameter OUT_DELAY = 3.5,
+    ) simul_axi_fifo_i (
+    .clk(clk),         // input              clk,
+    .reset(reset),       // input              reset,
+    .data_in({awid_in,awaddr_in,awlen_in,awsize_in,awburst_in,awcache_in,awprot_in}),     // input  [WIDTH-1:0] data_in,
+    .load(set_cmd),        // input              load,
+    .input_ready(ready), // output             input_ready,
+    .data_out({awid_out,awaddr_out,awlen_out,awsize_out,awburst_out,awcache_out,awprot_out}),    // output [WIDTH-1:0] data_out,
+    .valid(awvalid_out),       // output             valid,
+    .ready(awready));      //  input              ready);
+
+endmodule
+
diff --git a/simulation_modules/simul_axi_read.v b/simulation_modules/simul_axi_read.v
new file mode 100644
index 0000000..6236ee0
--- /dev/null
+++ b/simulation_modules/simul_axi_read.v
@@ -0,0 +1,86 @@
+/*******************************************************************************
+ * Module: simul_axi_read
+ * Date:2014-04-06  
+ * Author: Andrey Filippov
+ * Description: simulation of read data through maxi channel
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * simul_axi_read.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_read.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_read(
+  input         clk,
+  input         reset,
+  input         last,      // last data word in burst
+  input         data_stb,  // data strobe (RVALID & RREADY) genearted externally
+  input  [ 9:0] raddr,     // read burst address as written by axi master, 10 significant bits [11:2], valid at rcmd 
+  input  [ 3:0] rlen,      // burst length  as written by axi master, valid at rcmd
+  input         rcmd,      // read command (address+length) strobe
+  output [ 9:0] addr_out,  // output address
+  output        burst,     // burst in progress
+  output reg    err_out);  // data last does not match predicted or FIFO over/under run
+
+  wire   [ 9:0] raddr_fifo; // raddr after fifo
+  wire   [ 3:0] rlen_fifo;  // rlen after fifo
+  wire          fifo_valid; // fifo out valid
+//  wire          fifo_re;    // fifo read strobe
+  reg           burst_r=0;
+  reg    [ 3:0] left_plus_1;
+//  wire          start_burst=fifo_valid && (!burst_r || (last && data_stb));
+//  wire          start_burst=fifo_valid && data_stb && (!burst_r || last );
+  wire          start_burst=fifo_valid && data_stb && !burst_r;
+  wire          generated_last= burst?(left_plus_1==1): ( fifo_valid && (rlen_fifo==0)) ;
+  wire          fifo_in_rdy;
+  wire          error_w= (data_stb && (last != generated_last)) || (rcmd && !fifo_in_rdy) || (start_burst && !fifo_valid);
+  reg    [ 9:0] adr_out_r;
+//  reg           was_last;
+
+  assign  burst=burst_r || start_burst;
+  assign  addr_out=start_burst?raddr_fifo:adr_out_r;
+  always @ (posedge reset or posedge clk) begin
+      if (reset)                 burst_r <= 0;
+      else if (start_burst)      burst_r <= rlen_fifo!=0;
+//      else if (last && data_stb) burst_r <= 0;
+      else if (generated_last && data_stb) burst_r <= 0;
+      if (reset)                 left_plus_1 <= 0;
+      else if (start_burst)      left_plus_1 <= rlen_fifo;
+      else if (data_stb)         left_plus_1 <= left_plus_1-1;
+      if (reset)                 err_out <= 0;
+      else                       err_out <= error_w;
+//      if (reset)                 was_last <= 0;
+//      else if (data_stb)         was_last <= last;
+
+  end
+  always @ (posedge clk) begin
+      if   (start_burst) adr_out_r <= raddr_fifo+1; // simulating only address incremental mode
+      else if (data_stb) adr_out_r <= adr_out_r + 1;
+  
+  end
+simul_fifo
+#(
+  .WIDTH(14),
+  .DEPTH(64)
+)simmul_fifo_i(
+     .clk(clk),
+     .reset(reset),
+//     .data_in({rlen[3:0],raddr[11:2]}), // did not detect raddr[11:2] for  input  [ 9:0] raddr 
+     .data_in({rlen[3:0],raddr}),
+     .load(rcmd),
+     .input_ready(fifo_in_rdy),
+     .data_out({rlen_fifo, raddr_fifo}),
+     .valid(fifo_valid),
+     .ready(start_burst));
+endmodule
+
diff --git a/simulation_modules/simul_axi_slow_ready.v b/simulation_modules/simul_axi_slow_ready.v
new file mode 100644
index 0000000..bf4a5ff
--- /dev/null
+++ b/simulation_modules/simul_axi_slow_ready.v
@@ -0,0 +1,40 @@
+/*******************************************************************************
+ * Module: simul_axi_slow_ready
+ * Date:2014-03-24  
+ * Author: Andrey Filippov    
+ * Description: Simulation model for AXI: slow ready generation
+ *
+ * Copyright (c) 2014 Elphel, Inc..
+ * simul_axi_slow_ready.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_slow_ready.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_slow_ready(
+    input         clk,
+    input         reset,
+    input  [3:0]  delay,
+    input         valid,
+    output        ready
+    );
+    reg   [14:0]  rdy_reg;
+    assign ready=(delay==0)?1'b1: ((((rdy_reg[14:0] >> (delay-1)) & 1'b1) != 0)?1'b1:1'b0);
+    always @ (posedge clk or posedge reset) begin
+        if (reset)                rdy_reg <=0;
+        else if (!valid || ready) rdy_reg <=0;
+        else rdy_reg <={rdy_reg[13:0],valid};
+    end
+    
+
+endmodule
+
diff --git a/simulation_modules/simul_fifo.v b/simulation_modules/simul_fifo.v
new file mode 100644
index 0000000..761b3f9
--- /dev/null
+++ b/simulation_modules/simul_fifo.v
@@ -0,0 +1,65 @@
+/*******************************************************************************
+ * Module: simul_fifo
+ * Date:2014-04-06  
+ * Author: Andrey Filippov     
+ * Description: simple fifo for simulation
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * simul_fifo.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_fifo.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module simul_fifo
+#(
+  parameter integer WIDTH=  32,         // total number of output bits
+  parameter integer DEPTH=  64,         // maximal number of words in FIFO
+//  parameter OUT_DELAY = 3.5,
+  parameter integer FIFO_DEPTH=DEPTH+1
+//  parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
+)(
+  input              clk,
+  input              reset,
+  input  [WIDTH-1:0] data_in,
+  input              load,
+  output             input_ready,
+  output [WIDTH-1:0] data_out,
+  output             valid,
+  input              ready);
+  
+  reg  [WIDTH-1:0]   fifo [0:FIFO_DEPTH-1];
+  integer            in_address;
+  integer            out_address;
+  integer            count;
+  
+  assign data_out=    fifo[out_address];
+  assign valid=       count!=0;
+  assign input_ready= count<DEPTH;
+
+  always @ (posedge clk or posedge reset) begin
+    if    (reset)  in_address <= 0;
+    else if (load) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1;
+
+    if    (reset)            out_address <= 0;
+    else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1;
+
+    
+    if    (reset)                       count <= 0;
+    else if (!(valid && ready) && load) count <= count+1;
+    else if (valid && ready && !load)   count <= count-1;
+  end
+
+  always @ (posedge clk) begin
+    if (load) fifo[in_address] <= data_in;
+  end
+endmodule
\ No newline at end of file
diff --git a/util_modules/fifo_cross_clocks.v b/util_modules/fifo_cross_clocks.v
new file mode 100644
index 0000000..930ae74
--- /dev/null
+++ b/util_modules/fifo_cross_clocks.v
@@ -0,0 +1,95 @@
+/*******************************************************************************
+ * Module: fifo_cross_clocks
+ * Date:2014-05-20  
+ * Author: Andrey Filippov
+ * Description: Configurable FIFO with separate read and write clocks
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * fifo_cross_clocks.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  fifo_cross_clocks.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module fifo_cross_clocks
+#(
+  parameter integer DATA_WIDTH=16,
+  parameter integer DATA_DEPTH=4 // >=3
+) (
+    input                   rst,      // reset, active high
+    input                   rclk,     // read clock - positive edge
+    input                   wclk,     // write clock - positive edge
+    input                   we,       // write enable
+    input                   re,       // read enable
+    input  [DATA_WIDTH-1:0] data_in,  // input data
+    output [DATA_WIDTH-1:0] data_out, // output data
+    output                  nempty,   // FIFO has some data (sync to rclk)
+    output                  half_empty // FIFO half full (wclk) -(not more than 5/8 full)
+  );
+    localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
+    reg  [DATA_WIDTH-1:0]   ram [0:DATA_2DEPTH];
+    reg  [DATA_DEPTH-1:0] raddr;
+    reg  [DATA_DEPTH-1:0] waddr;
+    reg  [DATA_DEPTH-1:0] waddr_gray;
+    reg  [DATA_DEPTH-1:0] waddr_gray_rclk;
+    wire [DATA_DEPTH-1:0] waddr_plus1 = waddr +1;   
+    wire [DATA_DEPTH-1:0] waddr_plus1_gray = waddr_plus1 ^ {1'b0,waddr_plus1[DATA_DEPTH-1:1]};
+       
+    wire [DATA_DEPTH-1:0] raddr_gray = raddr ^ {1'b0,raddr[DATA_DEPTH-1:1]};
+    wire [DATA_DEPTH-1:0] raddr_plus1 = raddr +1;   
+    wire [2:0] raddr_plus1_gray_top3 = raddr_plus1[DATA_DEPTH-1:DATA_DEPTH-3] ^ {1'b0,raddr_plus1[DATA_DEPTH-1:DATA_DEPTH-2]};
+    reg  [2:0] raddr_gray_top3;
+    reg  [2:0] raddr_gray_top3_wclk;
+       wire [2:0] raddr_top3_wclk = {
+        raddr_gray_top3_wclk[2],
+        raddr_gray_top3_wclk[2]^raddr_gray_top3_wclk[1],
+        raddr_gray_top3_wclk[2]^raddr_gray_top3_wclk[1]^raddr_gray_top3_wclk[0]};
+//(* keep = "true" *)   wire [2:0] addr_diff=waddr[DATA_DEPTH-1-:3]-raddr_top3_wclk; // just debugging 8-3332
+   wire [2:0] waddr_top3=waddr[DATA_DEPTH-1:DATA_DEPTH-3];
+//(* keep = "true" *)   wire [2:0] addr_diff=waddr[DATA_DEPTH-1:DATA_DEPTH-4]-raddr_top3_wclk; // just debugging 8-3332
+   wire [2:0] addr_diff=waddr_top3[2:0]-raddr_top3_wclk[2:0];
+    // half-empty does not need to be precise, it uses 3 MSBs of the write address
+    // converting to Gray code (easy) and then back (can not be done parallel easily).
+    // Comparing to 1/8'th of the depth with one-bit Gray code error results in uncertainty
+    // of +/-1/8, so half_empty means "no more than 5/8 full"
+    assign half_empty=~addr_diff[2];
+    // False positive in nempty can only happen if
+    // a) it is transitioning from empty to non-empty due to we pulse
+    // b) it is transitioning to overrun - too bad already
+    // false negative - OK, just wait fro the next rclk 
+    assign nempty=waddr_gray_rclk != raddr_gray;
+    assign data_out=ram[raddr];
+    always @ (posedge  wclk or posedge rst) begin
+        if (rst)     waddr <= 0;
+        else if (we) waddr <= waddr_plus1;
+        if (rst)     waddr_gray <= 0;
+        else if (we) waddr_gray <= waddr_plus1_gray;
+    end
+    
+    always @ (posedge  rclk or posedge rst) begin
+        if (rst)     raddr <= 0;
+        else if (re) raddr <= raddr_plus1;
+        if (rst)     raddr_gray_top3 <= 0;
+        else if (re) raddr_gray_top3 <= raddr_plus1_gray_top3;
+    end
+    
+    always @ (posedge  rclk) begin
+        waddr_gray_rclk <= waddr_gray;
+    end
+
+    always @ (posedge  wclk) begin
+          raddr_gray_top3_wclk <= raddr_gray_top3;
+          if (we) ram[waddr] <= data_in;
+    end
+    
+endmodule
+
diff --git a/util_modules/fifo_same_clock.v b/util_modules/fifo_same_clock.v
new file mode 100644
index 0000000..a15461c
--- /dev/null
+++ b/util_modules/fifo_same_clock.v
@@ -0,0 +1,88 @@
+/*******************************************************************************
+ * Module: fifo_same_clock
+ * Date:2014-05-20  
+ * Author: Andrey Filippov
+ * Description: Configurable synchronous FIFO using the same clock for read and write
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * fifo_same_clock.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  fifo_same_clock.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module fifo_same_clock
+#(
+  parameter integer DATA_WIDTH=16,
+  parameter integer DATA_DEPTH=4
+)
+    (
+  input                   rst,      // reset, active high
+  input                   clk,      // clock - positive edge
+  input                   we,       // write enable
+  input                   re,       // read enable
+  input  [DATA_WIDTH-1:0] data_in,  // input data
+  output [DATA_WIDTH-1:0] data_out, // output data
+  output reg              nempty,   // FIFO has some data
+  output reg              full,     // FIFO full
+  output reg              half_full // FIFO half full
+  );
+    localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
+    reg  [DATA_DEPTH  :0] fill=0;
+    reg                   just_one=0;
+    reg  [DATA_WIDTH-1:0] inreg;
+    reg  [DATA_WIDTH-1:0] outreg;
+    reg  [DATA_DEPTH-1:0] ra;
+    reg  [DATA_DEPTH-1:0] wa;
+    wire [DATA_DEPTH  :0] next_fill;
+    reg  wem;
+    wire rem;
+    reg  out_full=0; //output register full
+    reg  [DATA_WIDTH-1:0]   ram [0:DATA_2DEPTH];
+//    assign next_fill = fill[4:0]+((we && ~re)?1:((~we && re)?5'b11111:5'b00000));
+//    assign data_out  = just_one?inreg:outreg;
+    assign data_out  = out_full?outreg:inreg;
+    assign rem = (!out_full || re)&& (just_one? wem : re); 
+
+ //   assign next_fill = fill[4:0]+((we && ~rem)?1:((~we && rem)?5'b11111:5'b00000));
+ // TODO: verify rem is not needed instead of re
+    assign next_fill = fill[4:0]+((we && ~re)?1:((~we && re)?5'b11111:5'b00000));
+
+
+    always @ (posedge  clk or posedge  rst) begin
+      if   (rst) fill <= 0;
+      else if (we && ~re) fill <= fill+1;
+      else if (~we && re) fill <= fill-1;
+      if (rst)      wa <= 0;
+      else if (wem) wa <= wa+1;
+      if (rst)      ra <= 1; // 0;
+      else if (re)  ra <= ra+1; //now ra is 1 ahead
+      else if (!nempty) ra <= wa+1; // Just recover from bit errors TODO: fix
+      
+      if (rst)      nempty <= 0;
+      else          nempty <= (next_fill != 0);
+
+      if (rst)             out_full <= 0;
+      else if (rem && ~re) out_full <= 1;
+      else if (re && ~rem) out_full <= 0;
+      
+    end
+    always @ (posedge  clk) begin
+      if (wem) ram[wa] <= inreg;
+      just_one <= (next_fill == 1);
+      half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
+      full <=     (fill & (1<< DATA_DEPTH   ))!=0;
+      if (we)  inreg  <= data_in;
+      if (rem) outreg <= just_one?inreg:ram[ra];
+      wem <= we;
+    end
+endmodule
diff --git a/wrap/mmcm_phase_cntr.v b/wrap/mmcm_phase_cntr.v
index c477552..da57396 100644
--- a/wrap/mmcm_phase_cntr.v
+++ b/wrap/mmcm_phase_cntr.v
@@ -105,7 +105,7 @@ module  mmcm_phase_cntr#(
     reg ps_busy=0;
 // TODO: find out why it was optimized out!    
     (* keep = "true" *) reg ps_start0, ps_start; // debugging
-    assign ps_ready=!ps_busy && locked && ps_start0 && ps_start;
+    assign ps_ready=!ps_busy && locked && !ps_start0 && !ps_start;
     assign psen=ps_start && (diff != 0);
 //    wire [PHASE_WIDTH:0] diff= ps_target-ps_dout_r;
 // made a difference, so it doesn't seem Vivado extends bits of operands "+", "-"
diff --git a/wrap/oserdes_mem.v b/wrap/oserdes_mem.v
index 81349d5..e427fc5 100644
--- a/wrap/oserdes_mem.v
+++ b/wrap/oserdes_mem.v
@@ -93,7 +93,7 @@ localparam integer DATA_WIDTH_TRI=  (MODE_DDR=="TRUE")?4:1;
                .DATA_RATE_OQ         (DATA_RATE),
                .DATA_RATE_TQ         (DATA_RATE),
                .DATA_WIDTH           (DATA_WIDTH),
-               .DDR3_DATA            (DDR3_DATA), //For DDR3 DQ, DQS: 1, Address, ctrl, clock - 0
+//               .DDR3_DATA            (DDR3_DATA), //For DDR3 DQ, DQS: 1, Address, ctrl, clock - 0
                .INIT_OQ              (1'b0),
                .INIT_TQ              (1'b0),
                .INTERFACE_TYPE       ("DEFAULT"), //"DEFAULT", "MEMORY_DDR3" 
@@ -101,7 +101,7 @@ localparam integer DATA_WIDTH_TRI=  (MODE_DDR=="TRUE")?4:1;
                .SERDES_MODE          ("MASTER"),
                .SRVAL_OQ             (1'b0),
                .SRVAL_TQ             (1'b0),
-               .TRISTATE_WIDTH       (DATA_WIDTH)
+               .TRISTATE_WIDTH       (DATA_WIDTH_TRI)
             ) oserdes_i (
                .OFB                 (dout_dly),
                .OQ                  (dout_iob),