From 983cc0af3299476013e50c5dcc4a9595d8b4ae2c Mon Sep 17 00:00:00 2001 From: Leon Anavi Date: Wed, 26 Jun 2024 17:20:23 +0300 Subject: [PATCH 1/3] u-boot-imx_%.bbappend: Olimex iMX8MP-SOM-EVB-IND Add U-Boot defconfig for Olimex iMX8MP-SOM-EVB-IND based on the existing configuration for imx8mp-evk. Signed-off-by: Leon Anavi --- .../0001-Add-Olimex-iMX8MP-SOM-EVB-IND.patch | 235 ++++++++++++++++++ recipes-bsp/u-boot/u-boot-imx_%.bbappend | 3 + 2 files changed, 238 insertions(+) create mode 100644 recipes-bsp/u-boot/u-boot-imx/0001-Add-Olimex-iMX8MP-SOM-EVB-IND.patch create mode 100644 recipes-bsp/u-boot/u-boot-imx_%.bbappend diff --git a/recipes-bsp/u-boot/u-boot-imx/0001-Add-Olimex-iMX8MP-SOM-EVB-IND.patch b/recipes-bsp/u-boot/u-boot-imx/0001-Add-Olimex-iMX8MP-SOM-EVB-IND.patch new file mode 100644 index 00000000..c82031eb --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-imx/0001-Add-Olimex-iMX8MP-SOM-EVB-IND.patch @@ -0,0 +1,235 @@ +From fe883ebe672d5d35b174ef8e2864e735c8e4c094 Mon Sep 17 00:00:00 2001 +From: Leon Anavi +Date: Wed, 26 Jun 2024 14:12:44 +0000 +Subject: [PATCH] Add Olimex iMX8MP-SOM-EVB-IND + +Add support for Olimex iMX8MP-SOM-EVB-IND. + +Upstream-Status: Pending + +Signed-off-by: Leon Anavi +--- + configs/imx8mp_olimex_defconfig | 211 ++++++++++++++++++++++++++++++++ + 1 file changed, 211 insertions(+) + create mode 100644 configs/imx8mp_olimex_defconfig + +diff --git a/configs/imx8mp_olimex_defconfig b/configs/imx8mp_olimex_defconfig +new file mode 100644 +index 00000000000..da0e64c79eb +--- /dev/null ++++ b/configs/imx8mp_olimex_defconfig +@@ -0,0 +1,211 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_IMX8M=y ++CONFIG_TEXT_BASE=0x40200000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 ++CONFIG_SPL_GPIO=y ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_IMX_BOOTAUX=y ++CONFIG_NR_DRAM_BANKS=3 ++CONFIG_SYS_MEMTEST_START=0x60000000 ++CONFIG_SYS_MEMTEST_END=0xC0000000 ++CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_OFFSET=0x700000 ++CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_DM_GPIO=y ++CONFIG_SPL_TEXT_BASE=0x920000 ++CONFIG_USB_TCPC=y ++CONFIG_TARGET_IMX8MP_EVK=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_DRIVERS_MISC=y ++CONFIG_SPL_STACK=0x96dff0 ++CONFIG_SPL=y ++CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 ++CONFIG_SYS_LOAD_ADDR=0x40400000 ++CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_MONITOR_LEN=524288 ++CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" ++CONFIG_BOOTCOMMAND="run sr_ir_v2_cmd;run distro_bootcmd;run bsp_bootcmd" ++CONFIG_FIT=y ++CONFIG_FIT_EXTERNAL_OFFSET=0x3000 ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_REMAKE_ELF=y ++CONFIG_OF_BOARD_FIXUP=y ++CONFIG_OF_BOARD_SETUP=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="imx8mp-olimex.dtb" ++CONFIG_ARCH_MISC_INIT=y ++CONFIG_BOARD_EARLY_INIT_F=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_SPL_MAX_SIZE=0x26000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x96e000 ++CONFIG_SPL_BSS_MAX_SIZE=0x2000 ++CONFIG_SPL_BOARD_INIT=y ++CONFIG_SPL_BOOTROM_SUPPORT=y ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SYS_SPL_MALLOC=y ++CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y ++CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 ++CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 ++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y ++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 ++CONFIG_SPL_I2C=y ++CONFIG_SPL_POWER=y ++CONFIG_SPL_WATCHDOG=y ++CONFIG_SYS_MAXARGS=64 ++CONFIG_SYS_CBSIZE=2048 ++CONFIG_SYS_PBSIZE=2074 ++CONFIG_SYS_BOOTM_LEN=0x2000000 ++CONFIG_SYS_PROMPT="u-boot=> " ++# CONFIG_BOOTM_NETBSD is not set ++# CONFIG_CMD_EXPORTENV is not set ++# CONFIG_CMD_IMPORTENV is not set ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_NVEDIT_EFI=y ++CONFIG_CMD_CRC32=y ++CONFIG_CRC32_VERIFY=y ++CONFIG_CMD_MEMTEST=y ++CONFIG_CMD_CLK=y ++CONFIG_CMD_DFU=y ++CONFIG_CMD_FUSE=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_BMP=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_EFIDEBUG=y ++CONFIG_CMD_RTC=y ++CONFIG_CMD_TIME=y ++CONFIG_CMD_GETTIME=y ++CONFIG_CMD_TIMER=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_CMD_EXT4_WRITE=y ++CONFIG_CMD_LED=y ++CONFIG_OF_CONTROL=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_NOWHERE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_IS_IN_SPI_FLASH=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_USE_ETHPRIME=y ++CONFIG_ETHPRIME="eth1" ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SPL_DM=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_CLK_COMPOSITE_CCF=y ++CONFIG_CLK_COMPOSITE_CCF=y ++CONFIG_SPL_CLK_IMX8MP=y ++CONFIG_CLK_IMX8MP=y ++CONFIG_DFU_TFTP=y ++CONFIG_DFU_MMC=y ++CONFIG_DFU_RAM=y ++CONFIG_USB_FUNCTION_FASTBOOT=y ++CONFIG_UDP_FUNCTION_FASTBOOT=y ++CONFIG_FASTBOOT_BUF_ADDR=0x42800000 ++CONFIG_FASTBOOT_BUF_SIZE=0x40000000 ++CONFIG_FASTBOOT_FLASH=y ++CONFIG_MXC_GPIO=y ++CONFIG_DM_PCA953X=y ++CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_DM_MMC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_IO_VOLTAGE=y ++CONFIG_MMC_UHS_SUPPORT=y ++CONFIG_MMC_HS400_ES_SUPPORT=y ++CONFIG_MMC_HS400_SUPPORT=y ++CONFIG_FSL_USDHC=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SF_DEFAULT_MODE=0 ++CONFIG_SF_DEFAULT_SPEED=40000000 ++CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_PHY_GIGE=y ++CONFIG_PHY=y ++CONFIG_PHY_IMX8MQ_USB=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_IMX=y ++CONFIG_FEC_MXC=y ++CONFIG_MII=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_PINCTRL_IMX8M=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_IMX8M_POWER_DOMAIN=y ++CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_SPL_DM_PMIC_PCA9450=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_SERIAL=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_EMULATION=y ++CONFIG_MXC_UART=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_NXP_FSPI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_DM_THERMAL=y ++CONFIG_IMX_TMU=y ++CONFIG_USB=y ++CONFIG_DM_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_MANUFACTURER="FSL" ++CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 ++CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 ++CONFIG_VIDEO=y ++CONFIG_BMP_16BPP=y ++CONFIG_BMP_24BPP=y ++CONFIG_BMP_32BPP=y ++CONFIG_IMX8M_BLK_CTRL=y ++CONFIG_VIDEO_LOGO=y ++CONFIG_SYS_WHITE_ON_BLACK=y ++CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y ++CONFIG_VIDEO_IMX_SEC_DSI=y ++CONFIG_VIDEO_IMX_LCDIFV3=y ++CONFIG_SPLASH_SCREEN=y ++CONFIG_SPLASH_SCREEN_ALIGN=y ++CONFIG_VIDEO_ADV7535=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_LZO=y ++CONFIG_BZIP2=y ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_EFI_SET_TIME=y ++CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y ++CONFIG_EFI_CAPSULE_ON_DISK=y ++CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y ++CONFIG_EFI_SECURE_BOOT=y ++CONFIG_SPL_RSA=y ++CONFIG_SHA384=y ++CONFIG_EFI_VAR_BUF_SIZE=139264 ++CONFIG_EFI_IGNORE_OSINDICATIONS=y ++CONFIG_EFI_CAPSULE_AUTHENTICATE=y ++CONFIG_OPTEE=y ++CONFIG_CMD_OPTEE_RPMB=y ++CONFIG_EFI_MM_COMM_TEE=y ++CONFIG_TEE=y ++CONFIG_EFI_ESRT=y ++CONFIG_EFI_HAVE_CAPSULE_UPDATE=y ++CONFIG_FIT_SIGNATURE=y +-- +2.44.1 + diff --git a/recipes-bsp/u-boot/u-boot-imx_%.bbappend b/recipes-bsp/u-boot/u-boot-imx_%.bbappend new file mode 100644 index 00000000..1a1d5fe3 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-imx_%.bbappend @@ -0,0 +1,3 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" + +SRC_URI:append:olimex-imx8mp-evb = " file://0001-Add-Olimex-iMX8MP-SOM-EVB-IND.patch" From aa7d5d2c3b94d8fbb8768092695acdfd249e6532 Mon Sep 17 00:00:00 2001 From: Leon Anavi Date: Wed, 26 Jun 2024 17:23:01 +0300 Subject: [PATCH 2/3] linux-fslc-imx_%.bbappend: Olimex iMX8MP-SOM-EVB-IND Add Linux device tree for Olimex iMX8MP-SOM-EVB-IND. Signed-off-by: Leon Anavi --- ...olimex.dts-Olimex-iMX8MP-SOM-EVB-IND.patch | 1188 +++++++++++++++++ .../linux/linux-fslc-imx_%.bbappend | 3 + 2 files changed, 1191 insertions(+) create mode 100644 recipes-kernel/linux/linux-fslc-imx/0001-imx8mp-olimex.dts-Olimex-iMX8MP-SOM-EVB-IND.patch create mode 100644 recipes-kernel/linux/linux-fslc-imx_%.bbappend diff --git a/recipes-kernel/linux/linux-fslc-imx/0001-imx8mp-olimex.dts-Olimex-iMX8MP-SOM-EVB-IND.patch b/recipes-kernel/linux/linux-fslc-imx/0001-imx8mp-olimex.dts-Olimex-iMX8MP-SOM-EVB-IND.patch new file mode 100644 index 00000000..543387bd --- /dev/null +++ b/recipes-kernel/linux/linux-fslc-imx/0001-imx8mp-olimex.dts-Olimex-iMX8MP-SOM-EVB-IND.patch @@ -0,0 +1,1188 @@ +From 325ac8254da21b4327f9b7e8fe35305298a17aab Mon Sep 17 00:00:00 2001 +From: Leon Anavi +Date: Wed, 26 Jun 2024 15:08:47 +0000 +Subject: [PATCH] imx8mp-olimex.dts: Olimex iMX8MP-SOM-EVB-IND + +Upstream-Status: Pending + +Signed-off-by: Leon Anavi +--- + .../boot/dts/freescale/imx8mp-olimex.dts | 1166 +++++++++++++++++ + 1 file changed, 1166 insertions(+) + create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-olimex.dts + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-olimex.dts b/arch/arm64/boot/dts/freescale/imx8mp-olimex.dts +new file mode 100644 +index 000000000000..f8c7ebdeee4e +--- /dev/null ++++ b/arch/arm64/boot/dts/freescale/imx8mp-olimex.dts +@@ -0,0 +1,1166 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright 2019 NXP ++ */ ++ ++/dts-v1/; ++ ++#include ++#include "imx8mp.dtsi" ++ ++/ { ++ model = "Olimex i.MX8MPlus"; ++ compatible = "fsl,imx8mp-evk", "fsl,imx8mp", "olimex,imx8mp"; ++ ++ chosen { ++ stdout-path = &uart2; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpio_led>; ++ ++ status { ++ label = "yellow:status"; ++ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x0 0x40000000 0 0xc0000000>, ++ <0x1 0x00000000 0 0xc0000000>; ++ }; ++ reg_usdhc2_vmmc: regulator-usdhc2 { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; ++ regulator-name = "VSD_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ reg_audio_pwr: regulator-audio-pwr { ++ compatible = "regulator-fixed"; ++ regulator-name = "audio-pwr"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ sound { ++ compatible = "fsl,imx-audio-es8328"; ++ model = "imx-audio-es8328"; ++ audio-codec = <&codec>; ++ audio-routing = ++ "Speaker", "LOUT2", ++ "Speaker", "ROUT2", ++ "Speaker", "audio-amp", ++ "Headphone", "ROUT1", ++ "Headphone", "LOUT1", ++ "LINPUT1", "Mic Jack", ++ "RINPUT1", "Mic Jack", ++ "Mic Jack", "Mic Bias"; ++ mux-int-port = <0x1>; ++ mux-ext-port = <0x3>; ++ }; ++ ++ ++ sound-hdmi { ++ compatible = "fsl,imx-audio-cdnhdmi"; ++ model = "audio-hdmi"; ++ audio-cpu = <&aud2htx>; ++ hdmi-out; ++ constraint-rate = <44100>, ++ <88200>, ++ <176400>, ++ <32000>, ++ <48000>, ++ <96000>, ++ <192000>; ++ status = "okay"; ++ }; ++ ++}; ++ ++&A53_0 { ++ cpu-supply = <&buck2>; ++}; ++ ++&A53_1 { ++ cpu-supply = <&buck2>; ++}; ++ ++&A53_2 { ++ cpu-supply = <&buck2>; ++}; ++ ++&A53_3 { ++ cpu-supply = <&buck2>; ++}; ++ ++&dsp { ++ status = "okay"; ++}; ++ ++&pwm1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm1>; ++ status = "okay"; ++}; ++ ++&pwm2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm2>; ++ status = "okay"; ++}; ++ ++&pwm4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm4>; ++ status = "okay"; ++}; ++ ++&aud2htx { ++ status = "okay"; ++}; ++/* ++&ecspi2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ fsl,spi-num-chipselects = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; ++ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++ ++ spidev1: spi@0 { ++ reg = <0>; ++ compatible = "rohm,dh2228fv"; ++ spi-max-frequency = <500000>; ++ }; ++}; ++*/ ++ ++&eqos { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_eqos>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <ðphy0>; ++ phy-reset-gpios = <&gpio4 02 GPIO_ACTIVE_LOW>; ++ phy-reset-post-delay = <150>; ++ phy-reset-duration = <10>; ++ fsl,magic-packet; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ethphy0: ethernet-phy@3 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ eee-broken-100tx; ++ eee-broken-1000t; ++ ++ reg = <3>; ++ }; ++ }; ++}; ++ ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_fec>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <ðphy1>; ++ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; ++ phy-reset-post-delay = <150>; ++ phy-reset-duration = <10>; ++ fsl,magic-packet; ++ status = "okay"; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ethphy1: ethernet-phy@7 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++ }; ++}; ++ ++ ++&flexspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexspi0>; ++ status = "okay"; ++ ++ flash0: w25q128@0 { ++ compatible = "jedec,spi-nor", "winbond,w25q128"; ++ reg = <0>; ++ spi-rx-bus-width = <4>; ++ spi-max-frequency = <108000000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ ++}; ++ ++&flexcan1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan1>; ++// xceiver-supply = <®_can1_stby>; ++ status = "okay"; ++}; ++ ++&flexcan2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan2>; ++ //xceiver-supply = <®_can2_stby>; ++ //pinctrl-assert-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <400000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1>; ++ status = "okay"; ++ ++ pmic: pca9450@25 { ++ reg = <0x25>; ++ compatible = "nxp,pca9450c"; ++ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ ++ pinctrl-0 = <&pinctrl_pmic>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <3 GPIO_ACTIVE_LOW>; ++ ++ regulators { ++ buck1: BUCK1 { ++ regulator-name = "BUCK1"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <2187500>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-ramp-delay = <3125>; ++ }; ++ ++ buck2: BUCK2 { ++ regulator-name = "BUCK2"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <2187500>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-ramp-delay = <3125>; ++ nxp,dvs-run-voltage = <950000>; ++ nxp,dvs-standby-voltage = <850000>; ++ }; ++ ++ buck4: BUCK4{ ++ regulator-name = "BUCK4"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ buck5: BUCK5{ ++ regulator-name = "BUCK5"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ buck6: BUCK6 { ++ regulator-name = "BUCK6"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo1: LDO1 { ++ regulator-name = "LDO1"; ++ regulator-min-microvolt = <1600000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo2: LDO2 { ++ regulator-name = "LDO2"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo3: LDO3 { ++ regulator-name = "LDO3"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo4: LDO4 { ++ regulator-name = "LDO4"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo5: LDO5 { ++ regulator-name = "LDO5"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++/* ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++ ++ adv_bridge: adv7535@3d { ++ compatible = "adi,adv7533"; ++ reg = <0x3d>; ++ adi,addr-cec = <0x3b>; ++ adi,dsi-lanes = <4>; ++ status = "okay"; ++ ++ port { ++ adv7535_from_dsim: endpoint { ++ remote-endpoint = <&dsim_to_adv7535>; ++ }; ++ }; ++ }; ++ ++ lvds_bridge: lvds-to-hdmi-bridge@4c { ++ compatible = "ite,it6263"; ++ reg = <0x4c>; ++ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; ++ ++ port { ++ it6263_in: endpoint { ++ remote-endpoint = <&lvds_out>; ++ }; ++ }; ++ }; ++/* ++ ov5640_0: ov5640_mipi@3c { ++ compatible = "ovti,ov5640"; ++ reg = <0x3c>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; ++ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; ++ clock-names = "xclk"; ++ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; ++ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; ++ assigned-clock-rates = <24000000>; ++ csi_id = <0>; ++ powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; ++ mclk = <24000000>; ++ mclk_source = <0>; ++ mipi_csi; ++ status = "okay"; ++ ++ port { ++ ov5640_mipi_0_ep: endpoint { ++ remote-endpoint = <&mipi_csi0_ep>; ++ data-lanes = <1 2>; ++ clock-lanes = <0>; ++ }; ++ }; ++ }; ++ ++ ptn5110: tcpc@50 { ++ compatible = "nxp,ptn5110"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_typec>; ++ reg = <0x50>; ++ interrupt-parent = <&gpio4>; ++ interrupts = <19 8>; ++ ++ port { ++ typec_dr_sw: endpoint { ++ remote-endpoint = <&usb3_drd_sw>; ++ }; ++ }; ++ ++ usb_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ power-role = "dual"; ++ data-role = "dual"; ++ try-power-role = "sink"; ++ source-pdos = ; ++ sink-pdos = ; ++ op-sink-microwatt = <15000000>; ++ self-powered; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ typec_con_ss: endpoint { ++ remote-endpoint = <&usb3_data_ss>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++*/ ++ ++&i2c3 { ++ clock-frequency = <400000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ status = "okay"; ++ ++ codec: es8328@11 { ++ compatible = "everest,es8328"; ++ reg = <0x11>; ++ /* DVDD-supply = <®_audio_codec>; ++ AVDD-supply = <®_audio_codec>; ++ PVDD-supply = <®_audio_codec>; ++ HPVDD-supply = <®_audio_codec>;*/ ++ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; ++ }; ++ ++}; ++ ++&irqsteer_hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_blk_ctrl { ++ status = "okay"; ++}; ++ ++&hdmi_pavi { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmiphy { ++ status = "okay"; ++}; ++ ++&lcdif1 { ++ status = "okay"; ++}; ++ ++&lcdif2 { ++ status = "okay"; ++}; ++ ++&lcdif3 { ++ status = "okay"; ++ ++ thres-low = <1 2>; ++ thres-high = <3 4>; ++}; ++ ++/* ++&ldb { ++ status = "okay"; ++ ++ lvds-channel@0 { ++ fsl,data-mapping = "jeida"; ++ fsl,data-width = <24>; ++ status = "okay"; ++ ++ port@1 { ++ reg = <1>; ++ ++ lvds_out: endpoint { ++ remote-endpoint = <&it6263_in>; ++ }; ++ }; ++ }; ++}; ++ ++&ldb_phy { ++ status = "okay"; ++}; ++ ++&mipi_dsi { ++ status = "okay"; ++ ++ port@1 { ++ dsim_to_adv7535: endpoint { ++ remote-endpoint = <&adv7535_from_dsim>; ++ attach-bridge; ++ }; ++ }; ++}; ++*/ ++&snvs_pwrkey { ++ status = "okay"; ++}; ++ ++&easrc { ++ fsl,asrc-rate = <48000>; ++ status = "okay"; ++}; ++/* ++&micfil { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pdm>; ++ assigned-clocks = <&clk IMX8MP_CLK_PDM>; ++ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; ++ assigned-clock-rates = <196608000>; ++ status = "okay"; ++}; ++*/ ++&pcie{ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie>; ++ disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; ++ reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; ++ ext_osc = <1>; ++ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, ++ <&clk IMX8MP_CLK_PCIE_AUX>, ++ <&clk IMX8MP_CLK_HSIO_AXI>, ++ <&clk IMX8MP_CLK_PCIE_ROOT>; ++ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; ++ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, ++ <&clk IMX8MP_CLK_PCIE_AUX>; ++ assigned-clock-rates = <500000000>, <10000000>; ++ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, ++ <&clk IMX8MP_SYS_PLL2_50M>; ++ status = "okay"; ++}; ++ ++&pcie_ep{ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie>; ++ ext_osc = <1>; ++ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, ++ <&clk IMX8MP_CLK_PCIE_AUX>, ++ <&clk IMX8MP_CLK_HSIO_AXI>, ++ <&clk IMX8MP_CLK_PCIE_ROOT>; ++ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; ++ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, ++ <&clk IMX8MP_CLK_PCIE_AUX>; ++ assigned-clock-rates = <500000000>, <10000000>; ++ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, ++ <&clk IMX8MP_SYS_PLL2_50M>; ++ status = "disabled"; ++}; ++ ++&pcie_phy{ ++ ext_osc = <1>; ++ status = "okay"; ++}; ++/* ++&sai2 { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_sai2>; ++ assigned-clocks = <&clk IMX8MP_CLK_SAI2>; ++ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; ++ assigned-clock-rates = <12288000>; ++ status = "okay"; ++}; ++*/ ++&sai3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_sai3>; ++ assigned-clocks = <&clk IMX8MP_CLK_SAI3>; ++ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; ++ assigned-clock-rates = <12288000>; ++ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, ++ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, ++ <&clk IMX8MP_CLK_DUMMY>; ++ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; ++ fsl,sai-mclk-direction-output; ++ status = "okay"; ++}; ++/* ++&xcvr { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++*/ ++&sdma2 { ++ status = "okay"; ++}; ++ ++&uart1 { /* BT */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1>; ++ assigned-clocks = <&clk IMX8MP_CLK_UART1>; ++ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; ++ fsl,uart-has-rtscts; ++ status = "okay"; ++}; ++ ++&uart2 { ++ /* console */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2>; ++ status = "okay"; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart3>; ++ assigned-clocks = <&clk IMX8MP_CLK_UART3>; ++ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; ++ fsl,uart-has-rtscts; ++ status = "okay"; ++}; ++ ++&usb3_phy0 { ++// vbus-power-supply = <&ptn5110>; ++ fsl,phy-tx-vref-tune = <0xb>; ++ fsl,phy-tx-preemp-amp-tune = <3>; ++ status = "okay"; ++}; ++ ++&usb3_0 { ++ status = "okay"; ++}; ++ ++&usb_dwc3_0 { ++ //pinctrl-names = "default"; ++ //pinctrl-0 = <&pinctrl_usb2_vbus>; ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb3_phy1 { ++ fsl,phy-tx-preemp-amp-tune = <3>; ++ fsl,phy-tx-vref-tune = <0xb>; ++ status = "okay"; ++}; ++ ++&usb3_1 { ++ status = "okay"; ++}; ++ ++&usb_dwc3_1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usb1_vbus>; ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usdhc2 { ++ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; ++ assigned-clock-rates = <400000000>; ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; ++ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; ++ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; ++ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <®_usdhc2_vmmc>; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&usdhc3 { ++ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; ++ assigned-clock-rates = <400000000>; ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc3>; ++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; ++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&wdog1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_wdog>; ++ fsl,ext-reset-output; ++ status = "okay"; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 ++ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 ++ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 ++ MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 ++ >; ++ }; ++ ++ pinctrl_pwm1: pwm1grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 ++ >; ++ }; ++ ++ pinctrl_pwm2: pwm2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 ++ >; ++ }; ++ ++ pinctrl_pwm4: pwm4grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 ++ >; ++ }; ++ ++ pinctrl_ecspi2: ecspi2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 ++ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 ++ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 ++ >; ++ }; ++ ++ pinctrl_ecspi2_cs: ecspi2cs { ++ fsl,pins = < ++ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 ++ >; ++ }; ++ ++ pinctrl_eqos: eqosgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 ++ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 ++ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 ++ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 ++ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 ++ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 ++ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 ++ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 ++ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f ++ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f ++ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f ++ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f ++ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f ++ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f ++ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 ++ >; ++ }; ++ ++ pinctrl_fec: fecgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 ++ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 ++ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 ++ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 ++ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 ++ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 ++ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 ++ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 ++ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f ++ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f ++ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f ++ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f ++ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f ++ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f ++ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 ++ >; ++ }; ++ ++ pinctrl_flexcan1: flexcan1grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 ++ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 ++ >; ++ }; ++ ++ pinctrl_flexcan2: flexcan2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 ++ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 ++ >; ++ }; ++ ++ pinctrl_flexcan1_reg: flexcan1reggrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ ++ >; ++ }; ++ ++ pinctrl_flexcan2_reg: flexcan2reggrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ ++ >; ++ }; ++ ++ pinctrl_flexspi0: flexspi0grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 ++ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 ++ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 ++ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 ++ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 ++ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 ++ >; ++ }; ++ ++ pinctrl_gpio_led: gpioledgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 ++ >; ++ }; ++ ++ pinctrl_i2c1: i2c1grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 ++ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 ++ >; ++ }; ++ ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 ++ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 ++ >; ++ }; ++ ++ pinctrl_i2c3: i2c3grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 ++ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 ++ >; ++ }; ++ ++ pinctrl_mipi_dsi_en: mipi_dsi_en { ++ fsl,pins = < ++ MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 ++ >; ++ }; ++ ++ pinctrl_pcie: pciegrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ ++ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 ++ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 ++ >; ++ }; ++ ++ pinctrl_pmic: pmicirq { ++ fsl,pins = < ++ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 ++ >; ++ }; ++ ++ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 ++ >; ++ }; ++ ++ pinctrl_pdm: pdmgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 ++ MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 ++ MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 ++ MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 ++ MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 ++ >; ++ }; ++ ++ pinctrl_sai2: sai2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 ++ MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 ++ MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 ++ MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 ++ >; ++ }; ++ ++ pinctrl_sai3: sai3grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 ++ MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 ++ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 ++ MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 ++ MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 ++ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 ++ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 ++ >; ++ }; ++ ++ pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x16 ++ >; ++ }; ++ ++ pinctrl_uart1: uart1grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 ++ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 ++ MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 ++ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 ++ >; ++ }; ++ ++ pinctrl_typec: typec1grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 ++ >; ++ }; ++ ++ pinctrl_typec_mux: typec1muxgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 ++ >; ++ }; ++ ++ pinctrl_uart2: uart2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 ++ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 ++ >; ++ }; ++ ++ pinctrl_uart3: uart3grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 ++ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 ++ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 ++ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 ++ >; ++ }; ++ ++ pinctrl_usb1_vbus: usb1grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x19 ++ >; ++ }; ++/* ++ pinctrl_usb2_vbus: usb2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x106 ++ >; ++ }; ++*/ ++ pinctrl_usdhc2: usdhc2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 ++ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 ++ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 ++ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 ++ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 ++ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 ++ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 ++ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 ++ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 ++ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 ++ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 ++ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 ++ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 ++ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 ++ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 ++ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc2_gpio: usdhc2gpiogrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 ++ >; ++ }; ++ ++ pinctrl_usdhc3: usdhc3grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 ++ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 ++ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 ++ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 ++ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 ++ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 ++ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 ++ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 ++ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 ++ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 ++ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 ++ >; ++ }; ++ ++ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 ++ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 ++ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 ++ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 ++ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 ++ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 ++ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 ++ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 ++ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 ++ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 ++ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 ++ >; ++ }; ++ ++ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 ++ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 ++ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 ++ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 ++ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 ++ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 ++ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 ++ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 ++ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 ++ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 ++ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 ++ >; ++ }; ++ ++ pinctrl_wdog: wdoggrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 ++ >; ++ }; ++ ++ pinctrl_csi0_pwn: csi0_pwn_grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19 ++ >; ++ }; ++ ++ pinctrl_csi0_rst: csi0_rst_grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 ++ >; ++ }; ++ ++ pinctrl_csi_mclk: csi_mclk_grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x59 ++ >; ++ }; ++}; ++ ++&vpu_g1 { ++ status = "okay"; ++}; ++ ++&vpu_g2 { ++ status = "okay"; ++}; ++ ++&vpu_vc8000e { ++ status = "okay"; ++}; ++ ++&gpu_3d { ++ status = "okay"; ++}; ++ ++&gpu_2d { ++ status = "okay"; ++}; ++ ++&ml_vipsi { ++ status = "okay"; ++}; ++ ++&mix_gpu_ml { ++ status = "okay"; ++}; ++/* ++&mipi_csi_0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ port@0 { ++ reg = <0>; ++ mipi_csi0_ep: endpoint { ++ remote-endpoint = <&ov5640_mipi_0_ep>; ++ data-lanes = <2>; ++ csis-hs-settle = <13>; ++ csis-clk-settle = <2>; ++ csis-wclk; ++ }; ++ }; ++}; ++ ++&mipi_csi_1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ port@1 { ++ reg = <1>; ++ mipi_csi1_ep: endpoint { ++ remote-endpoint = <&ov5640_mipi_1_ep>; ++ data-lanes = <2>; ++ csis-hs-settle = <13>; ++ csis-clk-settle = <2>; ++ csis-wclk; ++ }; ++ }; ++}; ++ ++&cameradev { ++ status = "okay"; ++}; ++*/ ++&isi_0 { ++ status = "okay"; ++ ++ cap_device { ++ status = "okay"; ++ }; ++ ++ m2m_device { ++ status = "okay"; ++ }; ++}; ++ ++&isi_1 { ++ status = "disabled"; ++ ++ cap_device { ++ status = "okay"; ++ }; ++}; +-- +2.45.2 + diff --git a/recipes-kernel/linux/linux-fslc-imx_%.bbappend b/recipes-kernel/linux/linux-fslc-imx_%.bbappend new file mode 100644 index 00000000..2d721191 --- /dev/null +++ b/recipes-kernel/linux/linux-fslc-imx_%.bbappend @@ -0,0 +1,3 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" + +SRC_URI:append:olimex-imx8mp-evb = " file://0001-imx8mp-olimex.dts-Olimex-iMX8MP-SOM-EVB-IND.patch" From 9c95d8b19cf180356472db0c4a41dfc37d9ed7e4 Mon Sep 17 00:00:00 2001 From: Leon Anavi Date: Wed, 26 Jun 2024 17:24:49 +0300 Subject: [PATCH 3/3] conf/machine/olimex-imx8mp-evb.conf: Add machine Add machine configuration for Olimex iMX8MP-SOM-EVB-IND. Signed-off-by: Leon Anavi --- conf/machine/olimex-imx8mp-evb.conf | 71 +++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 conf/machine/olimex-imx8mp-evb.conf diff --git a/conf/machine/olimex-imx8mp-evb.conf b/conf/machine/olimex-imx8mp-evb.conf new file mode 100644 index 00000000..1b427696 --- /dev/null +++ b/conf/machine/olimex-imx8mp-evb.conf @@ -0,0 +1,71 @@ +#@TYPE: Machine +#@NAME: Olimex iMX8MP-SOM evaluation board +#@SOC: i.MX8MP +#@DESCRIPTION: Machine configuration for Olimex iMX8MP-SOM evaluation board with LPDDR4 +#@MAINTAINER: Leon Anavi + +require conf/machine/include/imx8mp-evk.inc + +KERNEL_DEVICETREE_BASENAME = "imx8mp-olimex" + +# NXP kernel has additional DTB files for various board configuration and +# derivates. Include them here for NXP BSP only +KERNEL_DEVICETREE:append:use-nxp-bsp = " \ + freescale/imx8mp-ab2.dtb \ + freescale/imx8mp-evk-basler.dtb \ + freescale/imx8mp-evk-basler-ov2775.dtb \ + freescale/imx8mp-evk-basler-ov5640.dtb \ + freescale/imx8mp-evk-dpdk.dtb \ + freescale/imx8mp-evk-dsp.dtb \ + freescale/imx8mp-evk-dual-basler.dtb \ + freescale/imx8mp-evk-dual-os08a20.dtb \ + freescale/imx8mp-evk-dual-ov2775.dtb \ + freescale/imx8mp-evk-ecspi-slave.dtb \ + freescale/imx8mp-evk-flexcan2.dtb \ + freescale/imx8mp-evk-hifiberry-dacplus.dtb \ + freescale/imx8mp-evk-inmate.dtb \ + freescale/imx8mp-evk-iqaudio-dacplus.dtb \ + freescale/imx8mp-evk-iqaudio-dacpro.dtb \ + freescale/imx8mp-evk-it6263-lvds-dual-channel.dtb \ + freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dtb \ + freescale/imx8mp-evk-ndm.dtb \ + freescale/imx8mp-evk-os08a20.dtb \ + freescale/imx8mp-evk-os08a20-ov5640.dtb \ + freescale/imx8mp-evk-ov2775.dtb \ + freescale/imx8mp-evk-ov2775-ov5640.dtb \ + freescale/imx8mp-evk-pcie-ep.dtb \ + freescale/imx8mp-evk-revA3-8mic-revE.dtb \ + freescale/imx8mp-evk-rm67191.dtb \ + freescale/imx8mp-evk-rm67199.dtb \ + freescale/imx8mp-evk-root.dtb \ + freescale/imx8mp-evk-rpmsg.dtb \ + freescale/imx8mp-evk-rpmsg-lpv.dtb \ + freescale/imx8mp-evk-sof-wm8960.dtb \ + freescale/imx8mp-evk-spdif-lb.dtb \ + freescale/imx8mp-evk-usdhc1-m2.dtb \ + freescale/imx8mp-evk-8mic-swpdm.dtb \ + freescale/imx8mp-olimex.dtb \ +" + +IMX_DEFAULT_BOOTLOADER = "u-boot-imx" +IMX_DEFAULT_KERNEL = "linux-imx" + +UBOOT_CONFIG_BASENAME = "imx8mp_olimex" +UBOOT_CONFIG[fspi] = "${UBOOT_CONFIG_BASENAME}_defconfig" +UBOOT_CONFIG[ndm] = "${UBOOT_CONFIG_BASENAME}_ndm_defconfig" + +# Set DDR FIRMWARE +DDR_FIRMWARE_VERSION = "202006" +DDR_FIRMWARE_NAME = " \ + lpddr4_pmu_train_1d_dmem_${DDR_FIRMWARE_VERSION}.bin \ + lpddr4_pmu_train_1d_imem_${DDR_FIRMWARE_VERSION}.bin \ + lpddr4_pmu_train_2d_dmem_${DDR_FIRMWARE_VERSION}.bin \ + lpddr4_pmu_train_2d_imem_${DDR_FIRMWARE_VERSION}.bin \ +" + +IMXBOOT_TARGETS_BASENAME = "flash_evk" + +# Mainline BSP doesn't support LPDDR4 so it must be set to nxp. +# Also this machine isn't supported by u-boot-fslc but imx8mn-evk.inc already +# set the bootloader to u-boot-imx instead when NXP BSP is used. +IMX_DEFAULT_BSP = "nxp"