diff --git a/common/dev_c1700.c b/common/dev_c1700.c index a582268ae..d6bf1ecc5 100644 --- a/common/dev_c1700.c +++ b/common/dev_c1700.c @@ -497,7 +497,7 @@ static int c1700_init_platform(c1700_t *router) vm->boot_cpu = gen; /* Set processor ID */ - ppc32_set_pvr(cpu,0x00500202); + ppc32_set_pvr(cpu,PPC32_PVR_MPC860); /* Mark the Network IO interrupt as high priority */ vm->irq_idle_preempt[C1700_NETIO_IRQ] = TRUE; diff --git a/common/dev_c2600.c b/common/dev_c2600.c index 6158e2a43..5cd4ded20 100644 --- a/common/dev_c2600.c +++ b/common/dev_c2600.c @@ -560,7 +560,7 @@ static int c2600_init_platform(c2600_t *router) vm->boot_cpu = gen; /* Set processor ID */ - ppc32_set_pvr(cpu,0x00500202); + ppc32_set_pvr(cpu,PPC32_PVR_MPC860); /* Mark the Network IO interrupt as high priority */ vm->irq_idle_preempt[C2600_NETIO_IRQ] = TRUE; diff --git a/common/dev_c7200.c b/common/dev_c7200.c index e9f1965d8..c401707cc 100644 --- a/common/dev_c7200.c +++ b/common/dev_c7200.c @@ -1303,7 +1303,7 @@ int c7200_init_npeg2(c7200_t *router) int i; /* Set the processor type: PowerPC G4 */ - ppc32_set_pvr(CPU_PPC32(vm->boot_cpu),0x80040201); + ppc32_set_pvr(CPU_PPC32(vm->boot_cpu),PPC32_PVR_7448_v21); /* Initialize the PA PCI busses */ if (c7200_pa_create_pci_busses(router) == -1) diff --git a/stable/ppc32.h b/stable/ppc32.h index 50dd3d8a6..efab9e854 100644 --- a/stable/ppc32.h +++ b/stable/ppc32.h @@ -12,7 +12,10 @@ #include "rbtree.h" /* CPU identifiers */ -#define PPC32_PVR_405 0x40110000 +#define PPC32_PVR_405 0x40110000 /* PowerPC 405GPa */ +#define PPC32_PVR_MPC8xx 0x00500000 /* PowerPC MPC 8xx cores (aka PowerQUICC) */ +#define PPC32_PVR_MPC860 (PPC32_PVR_MPC8xx | 0x0202) /* assumed, because dev_mpc860 is being used */ +#define PPC32_PVR_7448_v21 0x80040201 /* PowerPC 74xx cores (aka G4) */ /* Number of GPR (general purpose registers) */ #define PPC32_GPR_NR 32 diff --git a/unstable/ppc32.h b/unstable/ppc32.h index 48d4d78cf..5fde3b250 100644 --- a/unstable/ppc32.h +++ b/unstable/ppc32.h @@ -12,7 +12,10 @@ #include "rbtree.h" /* CPU identifiers */ -#define PPC32_PVR_405 0x40110000 +#define PPC32_PVR_405 0x40110000 /* PowerPC 405GPa */ +#define PPC32_PVR_MPC8xx 0x00500000 /* PowerPC MPC 8xx cores (aka PowerQUICC) */ +#define PPC32_PVR_MPC860 (PPC32_PVR_MPC8xx | 0x0202) /* assumed, because dev_mpc860 is being used */ +#define PPC32_PVR_7448_v21 0x80040201 /* PowerPC 74xx cores (aka G4) */ /* Number of GPR (general purpose registers) */ #define PPC32_GPR_NR 32