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Frequently asked questions
If your question is not answered below please raise an enhancement issue with your question in the body of the issue. To do this, click the Issues tab above and click on 'New Issue' to get started.
Currently, the only way to get one is to obtain and build a bare printed circuit board. The cost for a PCB is only £3 (about $4.50 US) including post and packing in the UK. For the moment, we must currently ask for an additional amount to cover increased postage charges for all destinations outside the UK. However, for bare PCB’s this should not be a big deal. We'll let you know the mailing costs before you commit your order. To obtain a PCB, please contact us by leaving a comment against issue #1 in this repository. For construction notes and a bill of materials please see the documentation section of this repository. We will review the methods for obtaining GuzuntyPI hardware frequently as the community and demand develops. If you would prefer a kit of parts for example, please indicate this by leaving a comment against issue #2. We estimate a full kit will cost about £10 ($15 US) including postage and packing in the UK.
Aside from the basic pin protection and I/O expansion, there are a great many things a GuzuntyPI can do. You can think of it like a swiss army knife peripheral or a 'glue' chip that can bring all the parts of your project together. Check out the Gallery pages to see some examples.
Very easy indeed. The GuzuntyPI has been designed with 'through hole' components only. That is, there are no fiddly surface mount components to deal with at all. Just follow the advice in our construction notes and this great guide to soldering and you will be successful. Assembly time varies by soldering experience but unless you really want to savour the experience, you'll need less than an hour.
The XC9500XL CPLD is programmed using a file in the Xilinx Serial Vector Format. Cores you can download and cores that you make yourself are stored in this format. To program the CPLD with a particular core you use a utility that decodes the XSVF file and sets up the device using four special programming and test pins called collectively the JTAG interface. The CPLD retains its program during power down, so you only need to program it once (or until you move on to another project). The programming process takes at most a couple of minutes.
It does this by implementing an SPI (Serial Peripheral Interface) interface that the RPi can send commands across. To do this, four pins are needed on the Guzunty CPLD chip and the corresponding dedicated SPI pins on the Raspberry Pi GPIO array are also needed. This leaves an additional 30 I/O pins available for expansion.
That's easy. First of all, decide how many inputs and outputs your project requires. Most XSVF files on this site have a coded filename, such as gz_16o8i.xsvf. The letters tell you what numbers of pins do what. In this example, the core provides 16 outputs and 8 inputs via the RPi's SPI interface. Besides 'o' and 'i', 'p' denotes a pulse width modulation output. As we get more requests for cores, this list may grow. Additionally, if the letter is upper case it means that the function is provided directly to a Raspberry Pi GPIO pin, rather than via the SPI interface. Cores which provide specialised functionality do not follow this name encoding convention. Examples are gz_test.xsvf (which can be used to test your completed board) and gz_led_driver.xsvf (which drives a 4 digit 7 segment display).
A companion file for each core tells which Guzunty IO pins map to which functions of the core. For example, outputs<0> FB2_MC2 means that the lowest output bit is mapped to the pin labeled 'FB2 2' on the board.
Not at all. All you need is the loader available in the repository and a core that does what you need for your project. Once you have the right one, you may never need to replace the core with another. It really depends on whether you like to have many projects at once or one longer term project.
The chances are you won't have to, but there is a free toolchain you can use to create CPLD cores. If you are used to creating hardware schematics, you can use those to specify the required behavior of your core. Alternatively, if you prefer, you can use the VHDL and Verilog hardware definition languages. These languages have some similarities to the computer programming language Ada and so are often preferred by people with a programming background.
Unfortunately not. The VHDL flow is supported by the Xilinx integrated development environment, ISE. For the foreseeable future, ISE runs only on Windows and a very limited subset of x86 Linux distributions.
Create an enhancement issue in this repository and tag it with the ‘new core request’ label. If the function is general purpose, either myself or another community member will see if it can be fitted into an XC9572XL’s resources. If the function is very specific, you may have to download the toolchain and create your own core, perhaps starting with building blocks which can be found on the open hardware sites mentioned below. We are here to help you get started with the toolchain, but be aware that you will need to sign up with Xilinx to obtain a free copy of the development tools.
Yes, there are websites that provide generic open source cores in several of the standard Hardware Definition Languages. One example of this is opencores.org. The difference in this website is that here we have cores that have been adapted as required to the XC9572XL CPLD and configured for use with a Raspberry Pi.
No. A Complex Programmable Logic Device is strictly digital only. You can of course use the CPLD to control analog signals using devices such as a CD4067.
The rated maximum clock speed speed of the CPLD is 178 million cycles per second (MHz). In practice the Raspberry Pi can provide a maximum hardware clock speed of 125MHz. The actual speed you might actually want to use depends to some extent on your design. For example, a simple clock divider core has been shown to work fine up the RPi's maximum external clock speed. By contrast, it was found that the LED driver design is best clocked much more slowly; at 4MHz or less.
In theory, the SPI, or Serial Peripheral Interface can be clocked at the maximum rate provided by the Raspberry Pi, which provides a range between 3.814 kHz to 125 MHz. However, it has been found that data transfer at 125MHz is very unreliable. Since data transfer at 124MHz appears to be perfectly reliable, it is suspected that the 125MHz setting is unreliable for a reason unrelated to the GuzuntyPI board.
The Guzunty board is highly configurable. Its default configuration is designed to provide maximum protection for your Raspberry Pi. It is possible to reconfigure the board to your exact needs by cutting links between these pads and joining others with a blob of solder. You can explore the possibilities by studying the schematic. The default configuration will be useful to most people without modification. If you do modify the configuration, we'd love to hear what you did and why.
17 on P1 and 8 on P2, making a total of 25 IO pins.
The maximum number of 25 pins is less than the 30 free pins mentioned above in the interests of ensuring that the Raspberry Pi pin gets as much protection as possible. If you know what you are doing, you can modify the default configuration to make more IO available.
Yes, the Guzunty provides Ground, 3.3v and 5v outputs. These are taken from the power pins on the RPi GPIO header and so you must be sure to adhere to the overall power drain limits specified for the Pi itself. Also, take care not to jumper or otherwise short pins on the power header or you may damage your Pi (the silk screen shows a warning beside a large exclamation mark to help remind you of this). The Guzunty itself does not draw much power unless it is sinking current for another device it is controlling.
Yes, the CPLD itself operates at 3.3v, but the IO pins are '5 volt tolerant'. This means that it will operate with 5 volt inputs without damage. On the output side, 3.3 volts is reliably sensed as a logic '1' in almost all 5 volt technology logic.
You bet. The schematic is found here. The design was created in Kicad and the design source files are in the repository. Source code for all cores and executables are also available in the repository.