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vivado_15812.backup.jou
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vivado_15812.backup.jou
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#-----------------------------------------------------------
# Vivado v2022.2 (64-bit)
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
# Start of session at: Tue Jul 11 15:04:40 2023
# Process ID: 15812
# Current directory: D:/lab2_miniRV
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent13860 D:\lab2_miniRV\proj_single_cycle.xpr
# Log file: D:/lab2_miniRV/vivado.log
# Journal file: D:/lab2_miniRV\vivado.jou
# Running On: Mech-Win-Tera, OS: Windows, CPU Frequency: 2688 MHz, CPU Physical cores: 10, Host memory: 16898 MB
#-----------------------------------------------------------
start_gui
open_project D:/lab2_miniRV/proj_single_cycle.xpr
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
set_property -dict [list \
CONFIG.coefficient_file {D:/lab2_miniRV/data_ram_0.coe} \
CONFIG.data_width {8} \
] [get_ips DRAM]
generate_target all [get_files D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM/DRAM.xci]
catch { config_ip_cache -export [get_ips -all DRAM] }
export_ip_user_files -of_objects [get_files D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM/DRAM.xci] -no_script -sync -force -quiet
reset_run DRAM_synth_1
launch_runs DRAM_synth_1 -jobs 16
wait_on_run DRAM_synth_1
export_simulation -of_objects [get_files D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM/DRAM.xci] -directory D:/lab2_miniRV/proj_single_cycle.ip_user_files/sim_scripts -ip_user_files_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files -ipstatic_source_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/modelsim} {questa=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/questa} {riviera=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/riviera} {activehdl=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
set_property CONFIG.coefficient_file {D:/lab2_miniRV/data_ram_1.coe} [get_ips DRAM]
generate_target all [get_files D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM/DRAM.xci]
catch { config_ip_cache -export [get_ips -all DRAM] }
export_ip_user_files -of_objects [get_files D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM/DRAM.xci] -no_script -sync -force -quiet
reset_run DRAM_synth_1
launch_runs DRAM_synth_1 -jobs 16
wait_on_run DRAM_synth_1
export_simulation -of_objects [get_files D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM/DRAM.xci] -directory D:/lab2_miniRV/proj_single_cycle.ip_user_files/sim_scripts -ip_user_files_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files -ipstatic_source_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/modelsim} {questa=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/questa} {riviera=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/riviera} {activehdl=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
create_ip -name dist_mem_gen -vendor xilinx.com -library ip -version 8.0 -module_name dist_mem_gen_0
set_property -dict [list \
CONFIG.coefficient_file {D:/lab2_miniRV/data_ram_0.coe} \
CONFIG.data_width {8} \
CONFIG.depth {16384} \
] [get_ips dist_mem_gen_0]
generate_target {instantiation_template} [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci]
generate_target all [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci]
catch { config_ip_cache -export [get_ips -all dist_mem_gen_0] }
export_ip_user_files -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci]
export_simulation -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci] -directory D:/lab2_miniRV/proj_single_cycle.ip_user_files/sim_scripts -ip_user_files_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files -ipstatic_source_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/modelsim} {questa=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/questa} {riviera=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/riviera} {activehdl=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
update_compile_order -fileset sources_1
export_ip_user_files -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci] -no_script -reset -force -quiet
remove_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci
export_ip_user_files -of_objects [get_files D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM/DRAM.xci] -no_script -reset -force -quiet
remove_files -fileset DRAM D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM/DRAM.xci
create_ip -name dist_mem_gen -vendor xilinx.com -library ip -version 8.0 -module_name DRAM0
set_property -dict [list \
CONFIG.Component_Name {DRAM0} \
CONFIG.coefficient_file {D:/lab2_miniRV/data_ram_0.coe} \
CONFIG.data_width {8} \
CONFIG.depth {16384} \
] [get_ips DRAM0]
generate_target {instantiation_template} [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM0/DRAM0.xci]
generate_target all [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM0/DRAM0.xci]
catch { config_ip_cache -export [get_ips -all DRAM0] }
export_ip_user_files -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM0/DRAM0.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM0/DRAM0.xci]
export_simulation -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM0/DRAM0.xci] -directory D:/lab2_miniRV/proj_single_cycle.ip_user_files/sim_scripts -ip_user_files_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files -ipstatic_source_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/modelsim} {questa=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/questa} {riviera=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/riviera} {activehdl=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
create_ip -name dist_mem_gen -vendor xilinx.com -library ip -version 8.0 -module_name DRAM1
set_property -dict [list \
CONFIG.Component_Name {DRAM1} \
CONFIG.coefficient_file {D:/lab2_miniRV/data_ram_1.coe} \
CONFIG.data_width {8} \
CONFIG.depth {16384} \
] [get_ips DRAM1]
generate_target {instantiation_template} [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM1/DRAM1.xci]
generate_target all [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM1/DRAM1.xci]
catch { config_ip_cache -export [get_ips -all DRAM1] }
export_ip_user_files -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM1/DRAM1.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM1/DRAM1.xci]
export_simulation -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM1/DRAM1.xci] -directory D:/lab2_miniRV/proj_single_cycle.ip_user_files/sim_scripts -ip_user_files_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files -ipstatic_source_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/modelsim} {questa=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/questa} {riviera=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/riviera} {activehdl=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
update_compile_order -fileset sources_1
create_ip -name dist_mem_gen -vendor xilinx.com -library ip -version 8.0 -module_name DRAM2
set_property -dict [list \
CONFIG.Component_Name {DRAM2} \
CONFIG.coefficient_file {D:/lab2_miniRV/data_ram_2.coe} \
CONFIG.data_width {8} \
CONFIG.depth {16384} \
] [get_ips DRAM2]
generate_target {instantiation_template} [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM2/DRAM2.xci]
generate_target all [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM2/DRAM2.xci]
catch { config_ip_cache -export [get_ips -all DRAM2] }
export_ip_user_files -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM2/DRAM2.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM2/DRAM2.xci]
launch_runs DRAM2_synth_1 -jobs 16
wait_on_run DRAM2_synth_1
export_simulation -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM2/DRAM2.xci] -directory D:/lab2_miniRV/proj_single_cycle.ip_user_files/sim_scripts -ip_user_files_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files -ipstatic_source_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/modelsim} {questa=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/questa} {riviera=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/riviera} {activehdl=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
create_ip -name dist_mem_gen -vendor xilinx.com -library ip -version 8.0 -module_name DRAM3
set_property -dict [list \
CONFIG.Component_Name {DRAM3} \
CONFIG.coefficient_file {D:/lab2_miniRV/data_ram_3.coe} \
CONFIG.data_width {8} \
CONFIG.depth {16384} \
] [get_ips DRAM3]
generate_target {instantiation_template} [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM3/DRAM3.xci]
generate_target all [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM3/DRAM3.xci]
catch { config_ip_cache -export [get_ips -all DRAM3] }
export_ip_user_files -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM3/DRAM3.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM3/DRAM3.xci]
launch_runs DRAM3_synth_1 -jobs 16
wait_on_run DRAM3_synth_1
export_simulation -of_objects [get_files d:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/DRAM3/DRAM3.xci] -directory D:/lab2_miniRV/proj_single_cycle.ip_user_files/sim_scripts -ip_user_files_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files -ipstatic_source_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/modelsim} {questa=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/questa} {riviera=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/riviera} {activehdl=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 16
wait_on_run impl_1
open_hw_manager
connect_hw_server -allow_non_jtag
open_hw_target
set_property PROGRAM.FILE {D:/lab2_miniRV/proj_single_cycle.runs/impl_1/miniRV_SoC.bit} [get_hw_devices xc7a100t_0]
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {D:/lab2_miniRV/proj_single_cycle.runs/impl_1/miniRV_SoC.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
add_files -norecurse {D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/new/Buttons.v D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/new/Switches.v D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/new/LED.v}
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 16
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 16
wait_on_run impl_1
reset_run synth_1
set_property CONFIG.coefficient_file {D:/lab2_miniRV/controller.coe} [get_ips IROM]
generate_target all [get_files D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/IROM/IROM.xci]
catch { config_ip_cache -export [get_ips -all IROM] }
export_ip_user_files -of_objects [get_files D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/IROM/IROM.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/IROM/IROM.xci]
launch_runs IROM_synth_1 -jobs 16
wait_on_run IROM_synth_1
export_simulation -of_objects [get_files D:/lab2_miniRV/proj_single_cycle.srcs/sources_1/ip/IROM/IROM.xci] -directory D:/lab2_miniRV/proj_single_cycle.ip_user_files/sim_scripts -ip_user_files_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files -ipstatic_source_dir D:/lab2_miniRV/proj_single_cycle.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/modelsim} {questa=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/questa} {riviera=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/riviera} {activehdl=D:/lab2_miniRV/proj_single_cycle.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
launch_runs impl_1 -to_step write_bitstream -jobs 16
wait_on_run impl_1
reset_run impl_1
launch_runs impl_1 -jobs 16
wait_on_run impl_1