ps2.v

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// PS2髞ｮ逶俶沖謠乗｣?豬区ｨ｡蝮暦ｼ係縲、縲ヾ縲．蛻�悪謗ｧ蛻ｶ蟆剰寐逧�ｸ翫∝ｷｦ縲∽ｸ九∝承
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module PS2(
    input clk     ,    //50MHz
    input rst_n   ,    //Low Active
    input ps2_clk ,    //PS2譌ｶ髓滉ｿ｡蜿ｷ
    input ps2_data,    //PS2謨ｰ謐ｮ菫｡蜿ｷ
    
    output reg left,   //蟾ｦ髞ｮ謖我ｸ狗噪菫｡蜿?
    output reg right,  //蜿ｳ髞ｮ謖我ｸ狗噪菫｡蜿?
    output reg up,     //荳企醗謖我ｸ狗噪菫｡蜿?
    output reg down    //荳矩醗謖我ｸ狗噪菫｡蜿?
    );

    reg ps2_state;
//-----------------ps2_clk荳矩剄豐ｿ謐戊?--------------------
    
    //clk逶ｸ蠖謎ｺ惹ｸｭ髣ｴ驥�ｷ轤ｹ逧�ｽ懃畑�檎ｬｬ荳荳ｪ荳矩剄豐ｿ蛻ｰ譚･隸ｴ譏手ｵｷ蟋倶ｽ榊ｼ蟋?
    
    reg ps2_clk0, ps2_clk1, ps2_clk2;//郛灘�蟇�ｭ伜?
    wire ps2_clk_neg;  //1陦ｨ遉ｺ譽?豬句芦荳矩剄豐?
    
    always @ (posedge clk or negedge rst_n)
        if (!rst_n) 
            {ps2_clk0, ps2_clk1, ps2_clk2} <= 3'd0;
        else 
            begin
                ps2_clk0 <= ps2_clk;
                ps2_clk1 <= ps2_clk0;
                ps2_clk2 <= ps2_clk1;
            end
    
    assign ps2_clk_neg = ~ps2_clk1 & ps2_clk2;

    
//----------------------謨ｰ謐ｮ謗･謾ｶ----------------------------

    reg [3:0]num;      //遘ｻ菴肴而蛻ｶ
    reg [7:0]data_temp;//蠖灘燕謗･謾ｶ逧�焚謐?

    always @ (posedge clk or negedge rst_n)
        if (!rst_n)
            begin
                num <= 4'd0;
                data_temp <= 8'd0;
            end

        else if (ps2_clk_neg)
            begin
                if (num == 0) num <= num + 1'b1;//霍ｳ霑�ｵｷ蟋倶ｽ?
                else if (num <= 8)              //謨ｰ謐ｮ菴崎ｵ句?
                    begin
                        num <= num + 1'b1;
                        data_temp[num-1] <= ps2_data;
                    end
                else if (num == 9) num <= num + 1'b1;//霍ｳ霑�｡鬪御ｽ?
                else  num <= 4'd0;              //貂?0  
            end


//--------------------謖蛾醗謖我ｸ/譚ｾ蠑譽?豬?-------------------------
    
    reg ps2_loosen;//1陦ｨ遉ｺ謖蛾醗譚ｾ蠑
    reg [7:0]ps2_byte;//ps2荳?荳ｪ蟄苓鰍謨ｰ謐?

    always @ (posedge clk or negedge rst_n)
        if (!rst_n)
            begin 
                ps2_state <= 1'b0;
                ps2_loosen<= 1'b0;
            end
        //豈乗磁謾ｶ螳御ｸ?荳ｪ謨ｰ謐ｮ蟆ｱ霑幄｡梧潔髞ｮ譽?豬?
        else if (num == 4'd10)
            if (data_temp == 8'hf0) ps2_loosen <= 1'b1;//譁ｭ遐∵�ｯ�ｬ?
            else
                begin
                    if (ps2_loosen) //1陦ｨ遉ｺ謖蛾醗譚ｾ蠑�御ｸ倶ｸ?谺｡謗･謾ｶ謨ｰ謐ｮ蜷取ｸ?0
                        begin 
                            ps2_state <= 1'b0;
                            ps2_loosen<= 1'b0;
                        end
                    else            //loosen蜿?0蜷守噪荳倶ｸ荳ｪ謨ｰ謐ｮ陦ｨ遉ｺ謖蛾醗陲ｫ謖我ｸ
                        begin
                            ps2_state <= 1'b1;
                            ps2_byte <= data_temp; //謚願ｯｻ蜿門芦逧�?ｼ襍狗ｻ冪s2_out
                        end
                end

reg ps2state_reg;
wire flag;
always @ (posedge clk)
    ps2state_reg <= ps2_state;
assign flag = (ps2state_reg) & (~ps2_state);    
    
//---------------------譬ｹ謐ｮ髞ｮ逶俶沖謠冗∬ｾ灘�謖蛾醗譛画譜菫｡蜿?--------------------------         

    always @ (posedge clk or negedge rst_n) 
    if (!rst_n)
        begin left <= 0; right <= 0; up <= 0; down <= 0; end
    else if (flag)    //豈丞ｽ捺收蠑謖蛾醗譌ｶ謇崎ｿ幄｡瑚ｾ灘�
        case (ps2_byte)       
            8'h1C: begin left  <= 1;  end //a
            8'h23: begin right <= 1;  end //d
            8'h1D: begin up    <= 1;  end //w
            8'h1B: begin down  <= 1;  end //s
          default: begin left <= 0; right <= 0; up <= 0; down <= 0; end  
        endcase
    else if (left) left <= 0;       //謇?譛画潔髞ｮ譛画譜菫｡蜿ｷ霎灘�荳荳ｪ閼牙�蜷朱ｩｬ荳頑ｸ�峺
    else if (right) right <= 0;
    else if (up) up <= 0;
    else if (down) down <= 0;
   
endmodule