You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Hi, we were following the switch tutorial for compiling P4 to NetFPGA. And we noticed that it takes around a couple of hours to generate the bit file. Is there a way to reduce this time? Since we'd have to recompile for any small change in the P4 program.
The text was updated successfully, but these errors were encountered:
Hi,
You can try to reduce the time using incremental design. Check this AR https://www.xilinx.com/support/answers/57853.html out. You need the dcp from the original project. I'm not sure how much time you can reduce.
Hi, we were following the switch tutorial for compiling P4 to NetFPGA. And we noticed that it takes around a couple of hours to generate the bit file. Is there a way to reduce this time? Since we'd have to recompile for any small change in the P4 program.
The text was updated successfully, but these errors were encountered: