No bitstream generated

[mdumitru]

Doing "Assignment 1: Switch Calculator" of the tutorials, step 10 completes successfully, but no .bit files are actually generated. The folder bitfiles only contains program_switch.sh and README. A find for *bit files reveals that they were not created anywhere else.

I'm working on branch "vivado-2018.2", using both Vivado version 2018.2.

Here is the vivado.log.

[sibanez12]

It looks like the compilation never finished. How long did the build run for? For some reason the job was killed prematurely.

[mdumitru]

The build runs for a little more than 2 hours.

I'm using lmgrd to serve a "Xilinx.lic" floating license. The lmgrd outputs these two errors several times (each line repeated 8 times):

UNSUPPORTED: "xc7vx690t" (PORT_AT_HOST_PLUS ) mdumitru@omicron (No such feature exists. (-5,346))
...
UNSUPPORTED: "Internal_bitstream" (PORT_AT_HOST_PLUS ) mdumitru@omicron (No such feature exists. (-5,346))

Unfortunately, I have no prior experience with Vivado; is this simply an issue of not having the correct correct licenses?

[gsankara]

I am facing same issue during bitstream generation step where the make script getting stuck looking for impl_1. Even when I launch_runs impl_1, it never finishes.

This is for "int" example.

Any known issues ?

regs
Ganesh

Opening simple_sume_switch Implementation design

open_run impl_1

ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
Vivado%

[samersh23]

im getting an error at the same step, im getting this error:
ERROR: [DRC NSTD-1] Unspecified I/O Standard: 16 out of 62 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pcie_7x_mgt_txn[7:0], and pcie_7x_mgt_txp[7:0].
any known issues about this error?

[wangmengsail]

You should use the updated new version of P4-FPGA issued two years ago ,which is for vivado 2018.2 .All errors will be disappeared and bit files also be created