How to select the Commercial vs the Industrial speed grade of Gowin LV9QN88PC6/I5?

[zapta]

We have a project that is built using the three commands below and it works well. The Gowin FPGA device it uses is GW1NR-LV9QN88PC6/I5 and it has two speed grades, 6 for commercial temperature range and 5 for industrial temperature range. How can we specify in the command which of the two speed grades we want to target with our design?

yosys -p "synth_gowin -top blinky -json _build/hardware.json" -q blinky.v
nextpnr-himbaechel --device GW1NR-LV9QN88PC6/I5 --json _build/hardware.json --write _build/hardware.pnr.json --report _build/hardware.pnr --vopt family=GW1N-9C --vopt cst=blinky.cst -q
gowin_pack -d GW1N-9C -o _build/hardware.fs _build/hardware.pnr.json

[yrabbit]

I can assume you're not picking one or the other - you're picking a couple because fast commercial is simultaneously slow industrial.

[zapta]

nextpnr-himbaechel prints in its log the line below. Is this max speed for grade 5 (industrial temp range) or grade 6 (commercial temp range)?

Max frequency for clock 'sys_clk_IBUF_I_O': 153.47 MHz (PASS at 12.00 MHz)

[yrabbit]

Both at the same time - what is slow for Industrial is fast for Commercial.
They are indicated on the chip at the same time because they are just different names for the same speed.

[zapta]

... nextpnr-ecp5 allows to specify the speed grade via --speed and reports timing according to that speed grade.

E.g.

yosys -p "synth_ecp5 -top Test -json _build/hardware.json" -q Blinky.v
nextpnr-ecp5 --25k --package CABGA256 --speed 6 --json _build/hardware.json --textcfg _build/hardware.config --report _build/hardware.pnr --lpf pinout.lpf -q --timing-allow-fail --force
ecppack --compress --db /Users/user/.apio/packages/oss-cad-suite/share/trellis/database _build/hardware.config _build/hardware.bit

[yrabbit]

You specify speed grade when you say which chip to compile for. - LV9QN88PC6/I5
Or I don't understand how you want to separate the chip speeds if they are listed on it at the same time since they are the same thing.

[zapta]

"C6/I5" means that if you intend to use the FPGA in commercial temperature range (0C to 85C) you should use the timing constrains of speed grade 6 (faster) and if you intend to use the FPGA in industrial temperature range (-40C to 100C) you should use the timing constraints of speed grade 5 (slower).

The board designer that uses the FPGA needs to let nextpnr know which temperature range that board is designed for (or what speed grade constraints nexpnr should use), for example, for the purpose reporting the max speed.

The picture below is from the Gowin Design Timing Constraints User Guide and it shows how the user sets the intended temperature range (and thus the speed grade) in their system.

EDIT: This is the design constraints file. Is the user supposed to specify the speed grade in the .cst file? https://www.gowinsemi.com/upload/database_doc/2/document/5bfcfd099cf5f.pdf?_file=database_doc%2F2%2Fdocument%2F5bfcfd099cf5f.pdf

EDIT: ChatGPT suggests set_operating_conditions -grade c in the .cst file what it gives the warning Warning: Invalid constraint: set_operating_conditions -grade c.

[yrabbit]

I almost understand what you want to do - you want to specify for delay calculations not the categories specified on the chip, but arbitrary ones, and even separately.

Using gowin .sdc file to specify 'Set_operation_condition -grade c' command with nextpnr will not work because this file is not supported at the moment.

Maybe someone will add support for .SDC files in the future.

But you can still get different reports for different grades just by specifying a different chip (within a family) to compile.

And I will say that internally Gowin IDE keeps one latency table for the whole family regardless of chip brand (PARTNO) and it is organized like this:

'C5/I4': delays,
'C6/I5': delays,
'C7/I6': delays

That is delays do not change in each pair. Perhaps the calculation model changes, but that's beyond me.

[zapta]

1 I want to specify the speed grade for nextpnr to use for calculations. Either directly using 4, 5, 6, or indirectly by specifying I or c. 2. I want to know what speed grade nextpnr uses now for part number that has the c6/i5 suffix. Is it 6 or is it 5?

…

On Thu, Jan 16, 2025 at 1:33 PM YRabbit ***@***.***> wrote: I almost understand what you want to do - you want to specify for delay calculations not the categories specified on the chip, but arbitrary ones, and even separately. Using gowin .sdc file to specify 'Set_operation_condition -grade c' command with nextpnr will not work because this file is not supported at the moment. Maybe someone will add support for .SDC files in the future. But you can still get different reports for different grades just by specifying a different chip (within a family) to compile. And I will say that internally Gowin IDE keeps one latency table for the whole family regardless of chip brand (PARTNO) and it is organized like this: 'C5/I4': delays, 'C6/I5': delays, 'C7/I6': delays That is delays do not change in each pair. Perhaps the calculation model changes, but that's beyond me. — Reply to this email directly, view it on GitHub <#1424 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAQVMQOBTM6F2IVSFXRGXQT2LAQTVAVCNFSM6AAAAABVI3ZXY6VHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTCOBVHE4DENI> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[whitequark]

Isn't this just a misunderstanding? Let's consider that at some speed grade X, a counter can reach the speed of 150 MHz over commercial range and 140 MHz over industrial, and at speed grade Y, it is 160 MHz over commercial and 150 MHz over industrial. In this case we could call grade X "C5/I4" and grade Y "C6/I5". The delay model is probably computed for some arbitrary point (room temperature?) so the delays are the same, and so is the grading of the devices (surely nobody is using climatic chambers to do that), but the derating factors differ for commercial/industrial ranges.

[yrabbit]

The delays in the C/I pair are same. There's no point in choosing C6 or I5 - internally, Gowin keeps the temp stuff in the same place.

I think more experienced people can help further.

[zapta]

ecp5 has speed grades such as 6, 7, 8 that the user can specify to the pnr and this is clear and school will give different max clock speed. For Gowin my interpretation of c6/i5 is: if you intend to operate the fpga in the commercial temperature range, compute as speed grade 6, and if in the industrial temperature range, downgrade to speed grade 5.

…

On Thu, Jan 16, 2025 at 2:07 PM YRabbit ***@***.***> wrote: The delays in the C/I pair are same. There's no point in choosing C6 or I5 - internally, Gowin keeps the temp stuff in the same place. delays.png (view on web) <https://github.com/user-attachments/assets/463ab1e3-a679-44f7-b0e7-bca10c1ab7ec> I think more experienced people can help further. — Reply to this email directly, view it on GitHub <#1424 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAQVMQKASX3FD25HD3UUOTL2LAUR5AVCNFSM6AAAAABVI3ZXY6VHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTCOBWGAYDSNI> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[zapta]

Typo. school -> each

…

On Thu, Jan 16, 2025 at 2:18 PM Tal Dayan ***@***.***> wrote: ecp5 has speed grades such as 6, 7, 8 that the user can specify to the pnr and this is clear and school will give different max clock speed. For Gowin my interpretation of c6/i5 is: if you intend to operate the fpga in the commercial temperature range, compute as speed grade 6, and if in the industrial temperature range, downgrade to speed grade 5. On Thu, Jan 16, 2025 at 2:07 PM YRabbit ***@***.***> wrote: > The delays in the C/I pair are same. There's no point in choosing C6 or > I5 - internally, Gowin keeps the temp stuff in the same place. > > delays.png (view on web) > <https://github.com/user-attachments/assets/463ab1e3-a679-44f7-b0e7-bca10c1ab7ec> > > I think more experienced people can help further. > > — > Reply to this email directly, view it on GitHub > <#1424 (reply in thread)>, > or unsubscribe > <https://github.com/notifications/unsubscribe-auth/AAQVMQKASX3FD25HD3UUOTL2LAUR5AVCNFSM6AAAAABVI3ZXY6VHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTCOBWGAYDSNI> > . > You are receiving this because you authored the thread.Message ID: > ***@***.***> >

[zapta]

> The delays in the C/I pair are same.

I will try setting I and setting C in the gowin IDE and seep if it affects the reported timing analysis. Will post an update here. Currently waiting for the license, hope it will go through. @catherine, for your question, I would expect the reported max frequency to apply to the worst case situation in the relevant temperature range. That's the common practice in IC's datasheets.

…

On Thu, Jan 16, 2025 at 2:07 PM YRabbit ***@***.***> wrote: The delays in the C/I pair are same. There's no point in choosing C6 or I5 - internally, Gowin keeps the temp stuff in the same place. delays.png (view on web) <https://github.com/user-attachments/assets/463ab1e3-a679-44f7-b0e7-bca10c1ab7ec> I think more experienced people can help further. — Reply to this email directly, view it on GitHub <#1424 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAQVMQKASX3FD25HD3UUOTL2LAUR5AVCNFSM6AAAAABVI3ZXY6VHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTCOBWGAYDSNI> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[zapta]

After testing with the Gowin IDE it seems that the people here that said that C6 and I5 represent the same timing information are right.

I tried an example with the following time constraints

.csd

create_clock -name sys_clk -period 2 -waveform {0 1} [get_nets {sys_clk}]

// Select one of these 4 conbinations:
set_operating_conditions -grade c -model slow -speed 5
set_operating_conditions -grade c -model slow -speed 6
set_operating_conditions -grade i -model slow -speed 5
set_operating_conditions -grade i -model slow -speed 6

And i5 and c6 gave the same max clock speed

Example

module parity (
    input      sys_clk,
    output reg led  // Active low
);

  // Placement fails around 269.
  reg [260:0] counter = 0;

  always @(posedge sys_clk) begin
    counter <= counter + 1;
    led <= ^counter;
  end

endmodule