From 2dfa06c0eef9b64a901ba2c357475d29d515e896 Mon Sep 17 00:00:00 2001 From: SamulKyull Date: Thu, 14 Nov 2024 00:18:23 +0800 Subject: [PATCH] [driver] smhc update for new driver --- board/avaota-a1/board.c | 30 ++++++++++++++++++++++++++---- board/avaota-cam/board.c | 21 ++++++++++++--------- board/longanpi-4b/board.c | 30 ++++++++++++++++++++++++++---- board/lt527x/board.c | 30 ++++++++++++++++++++++++++---- include/drivers/mmc/sys-sdhci.h | 2 ++ 5 files changed, 92 insertions(+), 21 deletions(-) diff --git a/board/avaota-a1/board.c b/board/avaota-a1/board.c index 0243e066..60dfa5d6 100644 --- a/board/avaota-a1/board.c +++ b/board/avaota-a1/board.c @@ -106,8 +106,6 @@ sunxi_sdhci_t sdhci0 = { .name = "sdhci0", .id = MMC_CONTROLLER_0, .reg_base = SUNXI_SMHC0_BASE, - .clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG, - .clk_base = CCU_BASE + CCU_SMHC0_CLK_REG, .sdhci_mmc_type = MMC_TYPE_SD, .max_clk = 50000000, .width = SMHC_WIDTH_4BIT, @@ -122,14 +120,25 @@ sunxi_sdhci_t sdhci0 = { .gpio_cd = {GPIO_PIN(GPIO_PORTF, 6), GPIO_INPUT}, .cd_level = GPIO_LEVEL_LOW, }, + .clk_ctrl = { + .gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(0), + .rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(0), + }, + .sdhci_clk = { + .reg_base = CCU_BASE + CCU_SMHC0_CLK_REG, + .reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET, + .reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET, + .clk_sel = 0x1, + .parent_clk = 300000000, + }, }; sunxi_sdhci_t sdhci2 = { .name = "sdhci2", .id = MMC_CONTROLLER_2, .reg_base = SUNXI_SMHC2_BASE, - .clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG, - .clk_base = CCU_BASE + CCU_SMHC2_CLK_REG, .sdhci_mmc_type = MMC_TYPE_EMMC, .max_clk = 25000000, .width = SMHC_WIDTH_8BIT, @@ -148,6 +157,19 @@ sunxi_sdhci_t sdhci2 = { .gpio_ds = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX3}, .gpio_rst = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX3}, }, + .clk_ctrl = { + .gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(2), + .rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(2), + }, + .sdhci_clk = { + .reg_base = CCU_BASE + CCU_SMHC2_CLK_REG, + .reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET, + .reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET, + .clk_sel = 0x1, + .parent_clk = 600000000, + }, }; sunxi_i2c_t i2c_pmu = { diff --git a/board/avaota-cam/board.c b/board/avaota-cam/board.c index 781f2109..6ecf5dc7 100644 --- a/board/avaota-cam/board.c +++ b/board/avaota-cam/board.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include @@ -136,14 +136,14 @@ sunxi_sdhci_t sdhci1 = { .sdhci_mmc_type = MMC_TYPE_SD, .max_clk = 50000000, .width = SMHC_WIDTH_4BIT, - .dma_des_addr = SDRAM_BASE + 0x20080000, + .dma_des_addr = SDRAM_BASE + 0x10080000, .pinctrl = { - .gpio_clk = {GPIO_PIN(GPIO_PORTD, 3), GPIO_PERIPH_MUX6}, - .gpio_cmd = {GPIO_PIN(GPIO_PORTD, 4), GPIO_PERIPH_MUX6}, - .gpio_d0 = {GPIO_PIN(GPIO_PORTD, 2), GPIO_PERIPH_MUX6}, - .gpio_d1 = {GPIO_PIN(GPIO_PORTD, 1), GPIO_PERIPH_MUX6}, - .gpio_d2 = {GPIO_PIN(GPIO_PORTD, 5), GPIO_PERIPH_MUX6}, - .gpio_d3 = {GPIO_PIN(GPIO_PORTD, 6), GPIO_PERIPH_MUX6}, + .gpio_clk = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX2}, + .gpio_cmd = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX2}, + .gpio_d0 = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX2}, + .gpio_d1 = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX2}, + .gpio_d2 = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX2}, + .gpio_d3 = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX2}, }, .clk_ctrl = { .gate_reg_base = SUNXI_CCU_APP_BASE + BUS_CLK_GATING1_REG, @@ -153,7 +153,10 @@ sunxi_sdhci_t sdhci1 = { }, .sdhci_clk = { .reg_base = SUNXI_CCU_APP_BASE + SMHC_CTRL1_CLK_REG, - .clk_sel = SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_PERI_219M, + .reg_factor_n_offset = SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_DIV2_OFFSET, + .reg_factor_m_offset = SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_DIV1_OFFSET, + .clk_sel = SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_PERI_192M, + .parent_clk = 192000000, }, }; diff --git a/board/longanpi-4b/board.c b/board/longanpi-4b/board.c index 2cc30e37..8694f16e 100644 --- a/board/longanpi-4b/board.c +++ b/board/longanpi-4b/board.c @@ -106,8 +106,6 @@ sunxi_sdhci_t sdhci0 = { .name = "sdhci0", .id = MMC_CONTROLLER_0, .reg_base = SUNXI_SMHC0_BASE, - .clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG, - .clk_base = CCU_BASE + CCU_SMHC0_CLK_REG, .sdhci_mmc_type = MMC_TYPE_SD, .max_clk = 50000000, .width = SMHC_WIDTH_4BIT, @@ -122,14 +120,25 @@ sunxi_sdhci_t sdhci0 = { .gpio_cd = {GPIO_PIN(GPIO_PORTF, 6), GPIO_INPUT}, .cd_level = GPIO_LEVEL_LOW, }, + .clk_ctrl = { + .gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(0), + .rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(0), + }, + .sdhci_clk = { + .reg_base = CCU_BASE + CCU_SMHC0_CLK_REG, + .reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET, + .reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET, + .clk_sel = 0x1, + .parent_clk = 300000000, + }, }; sunxi_sdhci_t sdhci2 = { .name = "sdhci2", .id = MMC_CONTROLLER_2, .reg_base = SUNXI_SMHC2_BASE, - .clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG, - .clk_base = CCU_BASE + CCU_SMHC2_CLK_REG, .sdhci_mmc_type = MMC_TYPE_EMMC, .max_clk = 25000000, .width = SMHC_WIDTH_8BIT, @@ -148,6 +157,19 @@ sunxi_sdhci_t sdhci2 = { .gpio_ds = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX3}, .gpio_rst = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX3}, }, + .clk_ctrl = { + .gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(2), + .rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(2), + }, + .sdhci_clk = { + .reg_base = CCU_BASE + CCU_SMHC2_CLK_REG, + .reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET, + .reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET, + .clk_sel = 0x1, + .parent_clk = 600000000, + }, }; sunxi_i2c_t i2c_pmu = { diff --git a/board/lt527x/board.c b/board/lt527x/board.c index 23cafda4..6451c2be 100644 --- a/board/lt527x/board.c +++ b/board/lt527x/board.c @@ -105,8 +105,6 @@ sunxi_sdhci_t sdhci0 = { .name = "sdhci0", .id = MMC_CONTROLLER_0, .reg_base = SUNXI_SMHC0_BASE, - .clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG, - .clk_base = CCU_BASE + CCU_SMHC0_CLK_REG, .sdhci_mmc_type = MMC_TYPE_SD, .max_clk = 50000000, .width = SMHC_WIDTH_4BIT, @@ -121,14 +119,25 @@ sunxi_sdhci_t sdhci0 = { .gpio_cd = {GPIO_PIN(GPIO_PORTF, 6), GPIO_INPUT}, .cd_level = GPIO_LEVEL_LOW, }, + .clk_ctrl = { + .gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(0), + .rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(0), + }, + .sdhci_clk = { + .reg_base = CCU_BASE + CCU_SMHC0_CLK_REG, + .reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET, + .reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET, + .clk_sel = 0x1, + .parent_clk = 300000000, + }, }; sunxi_sdhci_t sdhci2 = { .name = "sdhci2", .id = MMC_CONTROLLER_2, .reg_base = SUNXI_SMHC2_BASE, - .clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG, - .clk_base = CCU_BASE + CCU_SMHC2_CLK_REG, .sdhci_mmc_type = MMC_TYPE_EMMC, .max_clk = 25000000, .width = SMHC_WIDTH_8BIT, @@ -147,6 +156,19 @@ sunxi_sdhci_t sdhci2 = { .gpio_ds = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX3}, .gpio_rst = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX3}, }, + .clk_ctrl = { + .gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(2), + .rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG, + .rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(2), + }, + .sdhci_clk = { + .reg_base = CCU_BASE + CCU_SMHC2_CLK_REG, + .reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET, + .reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET, + .clk_sel = 0x1, + .parent_clk = 600000000, + }, }; sunxi_i2c_t i2c_pmu = { diff --git a/include/drivers/mmc/sys-sdhci.h b/include/drivers/mmc/sys-sdhci.h index 2d660f71..5b10c8d0 100644 --- a/include/drivers/mmc/sys-sdhci.h +++ b/include/drivers/mmc/sys-sdhci.h @@ -125,6 +125,8 @@ typedef struct sunxi_sdhci { #define SDHCI_DEFAULT_CLK_RST_OFFSET(x) (16 + x) #define SDHCI_DEFAULT_CLK_GATE_OFFSET(x) (x) +#define SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET (0) +#define SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET (8) /** * @brief Initialize the SDHC controller.