Conformal not finding modules that are being used in experiment unless module is included in top file.

[jonath48]

This is a conformal log of a comparison of the ooc EX_stage before and after going through yosys synthesis. The log shows that the top file EX_stage.v is instancing the alu module which conformal can't find for some reason. The module in mips_16_defs.v is included in the EX_stage.v with an include statement. This may be what was causing the redefinition errors that were occurring before when I was running yosys synths because when I include the alu.v file in the EX_stage.v I receive a redefinition error once again. If I comment out the include_all_verilog_files: yes line in the design.yaml file for this experiment then It goes away.