From 28e9b215bb19f4247e39ba0e3b2ad983e507d688 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Thu, 7 Dec 2023 14:48:14 -0700 Subject: [PATCH 01/25] Adding IP encryption --- .gitmodules | 3 ++ Makefile | 2 +- bfasst/flows/encrypted_ip.py | 33 +++++++++++++++++++ bfasst/flows/flow.py | 3 ++ bfasst/flows/flow_descriptions.yaml | 10 +++++- bfasst/tools/ip/ipencrypter.py | 31 +++++++++++++++++ .../tools/ip/ipencrypter_build.ninja.mustache | 6 ++++ bfasst/tools/ip/ipencrypter_rules.ninja | 4 +++ bfasst/tools/synth/synth_tool.py | 3 +- bfasst/tools/synth/vivado_synth.py | 6 ++-- bfasst/tools/tool.py | 9 +++++ bfasst/yaml_parser.py | 4 +++ designs/base/pid/design.yaml | 2 ++ third_party/encrypted_ip | 1 + 14 files changed, 111 insertions(+), 6 deletions(-) create mode 100644 bfasst/flows/encrypted_ip.py create mode 100644 bfasst/tools/ip/ipencrypter.py create mode 100644 bfasst/tools/ip/ipencrypter_build.ninja.mustache create mode 100644 bfasst/tools/ip/ipencrypter_rules.ninja create mode 160000 third_party/encrypted_ip diff --git a/.gitmodules b/.gitmodules index 0d964ac5a..0e42907e9 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,3 +13,6 @@ [submodule "third_party/gmt_tools"] path = third_party/gmt_tools url = git@github.com:byuccl/gmt_tools.git +[submodule "third_party/encrypted_ip"] + path = third_party/encrypted_ip + url = git@github.com:byuccl/encrypted_ip.git diff --git a/Makefile b/Makefile index 6892925dc..c9de4c949 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -VIVADO_PATH := "/tools/Xilinx/Vivado/2022.2/bin/vivado" +VIVADO_PATH := "/tools/Xilinx/Vivado/2021.1/bin/vivado" IN_ENV = if [ -e .venv/bin/activate ]; then . .venv/bin/activate; fi; CAPNPJ := $(shell which capnpc-java) PYTHON311 := $(shell which python3.11) diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py new file mode 100644 index 000000000..3e3cc91cf --- /dev/null +++ b/bfasst/flows/encrypted_ip.py @@ -0,0 +1,33 @@ +"""Flow to create Vivado synthesis and implementation ninja snippets.""" +import pathlib +from bfasst.flows.flow import Flow + +from bfasst.tools.ip.ipencrypter import IpEncrypter +from bfasst.tools.synth.vivado_synth import VivadoSynth + + +class EncryptedIP(Flow): + def __init__(self, design): + super().__init__(design) + + for ip in self.design_props.encrypted_ip: + print(f"Encrypted IP: {ip}") + synth_tool = VivadoSynth( + self, + design, + ooc=True, + top=ip, + synth_options="-mode out_of_context -flatten_hierarchy full", + ) + synth_tool.override_build_path( + synth_tool.build_path.parent / f"{synth_tool.build_path.name}_{ip}" + ) + synth_tool._init_outputs() + + ip_encrypter_tool = IpEncrypter(self, design, synth_tool.outputs["synth_dcp"]) + ip_encrypter_tool.override_build_path( + ip_encrypter_tool.build_path.parent / f"{ip_encrypter_tool.build_path.name}_{ip}" + ) + + def get_top_level_flow_path(self): + return pathlib.Path(__file__) diff --git a/bfasst/flows/flow.py b/bfasst/flows/flow.py index 2446646e1..ff4a86426 100644 --- a/bfasst/flows/flow.py +++ b/bfasst/flows/flow.py @@ -2,6 +2,7 @@ import abc from bfasst.paths import BUILD_PATH, DESIGNS_PATH +from bfasst.yaml_parser import DesignParser class FlowBase(abc.ABC): @@ -40,6 +41,7 @@ def get_top_level_flow_path(self) -> str: def create_tool_build_dirs(self): """Create the build directories for all tools used by this flow""" for tool in self.tools: + assert tool.build_path is not None, f"Tool build path must be set for tool {tool}" tool.build_path.mkdir(parents=True, exist_ok=True) def post_execute(self): @@ -53,6 +55,7 @@ class Flow(FlowBase): def __init__(self, design_path): super().__init__() self.design_path = design_path + self.design_props = DesignParser(design_path / "design.yaml") self.design_build_path = BUILD_PATH / design_path.relative_to(DESIGNS_PATH) diff --git a/bfasst/flows/flow_descriptions.yaml b/bfasst/flows/flow_descriptions.yaml index b4cfff2f2..62d9ff195 100644 --- a/bfasst/flows/flow_descriptions.yaml +++ b/bfasst/flows/flow_descriptions.yaml @@ -74,4 +74,12 @@ flows: class: RandSoc external_tools: - vivado - - gmt_tools \ No newline at end of file + - gmt_tools + +- name: EncryptedIP + description: Encrypt IP in Vivado + module: encrypted_ip + class: EncryptedIP + external_tools: + - vivado + - encrypted_ip \ No newline at end of file diff --git a/bfasst/tools/ip/ipencrypter.py b/bfasst/tools/ip/ipencrypter.py new file mode 100644 index 000000000..2ec65b770 --- /dev/null +++ b/bfasst/tools/ip/ipencrypter.py @@ -0,0 +1,31 @@ +from bfasst.tools.tool import Tool + + +class IpEncrypter(Tool): + def __init__(self, flow, design_path, ip_dcp_path) -> None: + super().__init__(flow, design_path) + self.build_path = self.design_build_path / "ip_encrypter" + self.ip_dcp_path = ip_dcp_path + self._init_outputs() + + def create_rule_snippets(self): + self._append_rule_snippets_default(__file__) + + def create_build_snippets(self): + self._append_build_snippets_default( + __file__, + { + "dcp_unencrypted": self.ip_dcp_path, + "dcp_encrypted": self.outputs["encrypted_ip_dcp"], + "lut_ciphertext": self.outputs["lut_ciphertext"], + "log_file": self.outputs["log"], + }, + ) + + def add_ninja_deps(self, deps): + self._add_ninja_deps_default(deps, __file__) + + def _init_outputs(self): + self.outputs["encrypted_ip_dcp"] = self.build_path / "encrypted_ip.dcp" + self.outputs["lut_ciphertext"] = self.build_path / "lut_ciphertext.txt" + self.outputs["log"] = self.build_path / "log.txt" diff --git a/bfasst/tools/ip/ipencrypter_build.ninja.mustache b/bfasst/tools/ip/ipencrypter_build.ninja.mustache new file mode 100644 index 000000000..24f40e9a5 --- /dev/null +++ b/bfasst/tools/ip/ipencrypter_build.ninja.mustache @@ -0,0 +1,6 @@ +build {{ log_file }} {{ dcp_encrypted }}: encrypt_ip + dcp_unencrypted = {{ dcp_unencrypted }} + key = 00112233445566778899AABBCCDDEEFF + dcp_encrypted = {{ dcp_encrypted }} + lut_ciphertext = {{ lut_ciphertext }} + log_file = {{ log_file }} diff --git a/bfasst/tools/ip/ipencrypter_rules.ninja b/bfasst/tools/ip/ipencrypter_rules.ninja new file mode 100644 index 000000000..ce7bb57ac --- /dev/null +++ b/bfasst/tools/ip/ipencrypter_rules.ninja @@ -0,0 +1,4 @@ +rule encrypt_ip + command = python third_party/encrypted_ip/Project/python_scripts/encryptDesign.py $dcp_unencrypted $key $dcp_encrypted $lut_ciphertext > $log_file + description = encrypt ip $dcp_unencrypted + diff --git a/bfasst/tools/synth/synth_tool.py b/bfasst/tools/synth/synth_tool.py index 3f2b6a60e..ec6c90e3f 100644 --- a/bfasst/tools/synth/synth_tool.py +++ b/bfasst/tools/synth/synth_tool.py @@ -8,8 +8,9 @@ class SynthTool(Tool): """Base class for synthesis tools""" - def __init__(self, flow, design_path, ooc=False) -> None: + def __init__(self, flow, design_path, top=None, ooc=False) -> None: super().__init__(flow, design_path) + self.top = top if ooc: self.build_path = self.design_build_path / "synth_ooc" else: diff --git a/bfasst/tools/synth/vivado_synth.py b/bfasst/tools/synth/vivado_synth.py index 072e72c74..7c267e0c8 100644 --- a/bfasst/tools/synth/vivado_synth.py +++ b/bfasst/tools/synth/vivado_synth.py @@ -10,8 +10,8 @@ class VivadoSynth(SynthTool): """Tool to create vivado synthesis ninja snippets.""" - def __init__(self, flow, design_path, ooc=False, synth_options=""): - super().__init__(flow, design_path, ooc=ooc) + def __init__(self, flow, design_path, ooc=False, synth_options="", top=None): + super().__init__(flow, design_path, top=top, ooc=ooc) self.synth_options = synth_options self._my_dir_path = pathlib.Path(__file__).parent @@ -36,7 +36,7 @@ def create_build_snippets(self): # Chevron will use this file to fill in the tcl template. synth = { "part": config.PART, - "top": self.design_props.top, + "top": self.design_props.top if not self.top else self.top, "vhdl": self.vhdl, "vhdl_libs": list(self.vhdl_file_lib_map.items()), "verilog": self.verilog, diff --git a/bfasst/tools/tool.py b/bfasst/tools/tool.py index c350d38be..e7d2d096f 100644 --- a/bfasst/tools/tool.py +++ b/bfasst/tools/tool.py @@ -110,3 +110,12 @@ def __init__(self, flow, design_path) -> None: self.design_props = None if design_yaml.is_file(): self.design_props = DesignParser(design_yaml) + + @abc.abstractmethod + def _init_outputs(self): + """Initialize the outputs for this tool""" + + def override_build_path(self, build_path): + """Override the build path""" + self.build_path = build_path + self._init_outputs() diff --git a/bfasst/yaml_parser.py b/bfasst/yaml_parser.py index 8ec55b188..0b37bc2f5 100644 --- a/bfasst/yaml_parser.py +++ b/bfasst/yaml_parser.py @@ -109,6 +109,10 @@ def __init__(self, yaml_path): if "vhdl_libs" in self.props: self.vhdl_libs = self.props["vhdl_libs"] + self.encrypted_ip = None + if "encrypted_ip" in self.props: + self.encrypted_ip = self.props["encrypted_ip"] + class FlowDescriptionParser(YamlParser): """Parse the flow description yaml file""" diff --git a/designs/base/pid/design.yaml b/designs/base/pid/design.yaml index 4b93c1339..c3fadc866 100644 --- a/designs/base/pid/design.yaml +++ b/designs/base/pid/design.yaml @@ -2,3 +2,5 @@ top: top include_all_verilog_files: True +encrypted_ip: ["divider_dshift"] + diff --git a/third_party/encrypted_ip b/third_party/encrypted_ip new file mode 160000 index 000000000..c6e09baa7 --- /dev/null +++ b/third_party/encrypted_ip @@ -0,0 +1 @@ +Subproject commit c6e09baa757f5a5f031f787a25229c72ece7c3e1 From 0b93e386aa50201cef99759e2a7c90d38d32ce8d Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Thu, 7 Dec 2023 19:37:24 -0700 Subject: [PATCH 02/25] IP encryption done --- bfasst/tools/common/dcp_to_v.tcl.mustache | 3 +++ bfasst/tools/common/vivado_rules.ninja.mustache | 4 +--- bfasst/tools/ip/ipencrypter.py | 17 +++++++++++++++++ .../tools/ip/ipencrypter_build.ninja.mustache | 8 ++++++++ bfasst/tools/tool.py | 3 +-- 5 files changed, 30 insertions(+), 5 deletions(-) create mode 100644 bfasst/tools/common/dcp_to_v.tcl.mustache diff --git a/bfasst/tools/common/dcp_to_v.tcl.mustache b/bfasst/tools/common/dcp_to_v.tcl.mustache new file mode 100644 index 000000000..0918d5f4f --- /dev/null +++ b/bfasst/tools/common/dcp_to_v.tcl.mustache @@ -0,0 +1,3 @@ +open_checkpoint {{ dcp }} +write_verilog {{ verilog }} -force +close_project \ No newline at end of file diff --git a/bfasst/tools/common/vivado_rules.ninja.mustache b/bfasst/tools/common/vivado_rules.ninja.mustache index 231755145..109fd7450 100644 --- a/bfasst/tools/common/vivado_rules.ninja.mustache +++ b/bfasst/tools/common/vivado_rules.ninja.mustache @@ -2,9 +2,7 @@ rule vivado command = export tempjou=$$(mktemp); export templog=$$(mktemp); cd $cwd && {{ utils_path }}/retry.sh {{ vivado_path }} -mode batch -journal $$tempjou -log $$templog -source $in >&- && mv $$tempjou $journal && mv $$templog $log description = vivado $in -{{#in_context}} rule vivado_ioparse command = python3 bfasst/utils/vivado_ioparse.py <$in >$out description = vivado_ioparse <$in >$out - -{{/in_context}} + diff --git a/bfasst/tools/ip/ipencrypter.py b/bfasst/tools/ip/ipencrypter.py index 2ec65b770..c9605d45e 100644 --- a/bfasst/tools/ip/ipencrypter.py +++ b/bfasst/tools/ip/ipencrypter.py @@ -1,4 +1,7 @@ +import json +from bfasst.paths import COMMON_TOOLS_PATH from bfasst.tools.tool import Tool +from bfasst.utils.general import json_write_if_changed class IpEncrypter(Tool): @@ -10,15 +13,28 @@ def __init__(self, flow, design_path, ip_dcp_path) -> None: def create_rule_snippets(self): self._append_rule_snippets_default(__file__) + self._append_rule_snippets_default( + None, {}, COMMON_TOOLS_PATH / "vivado_rules.ninja.mustache" + ) def create_build_snippets(self): + dcp_to_v = { + "dcp": str(self.outputs["encrypted_ip_dcp"]), + "verilog": str(self.outputs["encrypted_verilog"]), + } + dcp_to_v_json = json.dumps(dcp_to_v, indent=4) + json_write_if_changed(self.build_path / "dcp_to_v.json", dcp_to_v_json) + self._append_build_snippets_default( __file__, { "dcp_unencrypted": self.ip_dcp_path, "dcp_encrypted": self.outputs["encrypted_ip_dcp"], + "verilog_encrypted": self.outputs["encrypted_verilog"], "lut_ciphertext": self.outputs["lut_ciphertext"], "log_file": self.outputs["log"], + "cwd": self.build_path, + "gen_encrypted_verilog_template": COMMON_TOOLS_PATH / "dcp_to_v.tcl.mustache", }, ) @@ -27,5 +43,6 @@ def add_ninja_deps(self, deps): def _init_outputs(self): self.outputs["encrypted_ip_dcp"] = self.build_path / "encrypted_ip.dcp" + self.outputs["encrypted_verilog"] = self.build_path / "encrypted_ip.v" self.outputs["lut_ciphertext"] = self.build_path / "lut_ciphertext.txt" self.outputs["log"] = self.build_path / "log.txt" diff --git a/bfasst/tools/ip/ipencrypter_build.ninja.mustache b/bfasst/tools/ip/ipencrypter_build.ninja.mustache index 24f40e9a5..26ec3d7b3 100644 --- a/bfasst/tools/ip/ipencrypter_build.ninja.mustache +++ b/bfasst/tools/ip/ipencrypter_build.ninja.mustache @@ -4,3 +4,11 @@ build {{ log_file }} {{ dcp_encrypted }}: encrypt_ip dcp_encrypted = {{ dcp_encrypted }} lut_ciphertext = {{ lut_ciphertext }} log_file = {{ log_file }} + +build {{ cwd }}/dcp_to_v.tcl: template {{ cwd }}/dcp_to_v.json {{ gen_encrypted_verilog_template }} + cwd = {{ cwd }} + +build {{ verilog_encrypted }}: vivado {{ cwd }}/dcp_to_v.tcl + cwd = {{ cwd }} + journal = {{ cwd }}/vivado.jou + log = {{ cwd }}/vivado.log diff --git a/bfasst/tools/tool.py b/bfasst/tools/tool.py index e7d2d096f..1767f889e 100644 --- a/bfasst/tools/tool.py +++ b/bfasst/tools/tool.py @@ -40,9 +40,8 @@ def _append_rule_snippets_default(self, py_tool_path, render_dict=None, rules_pa assuming default filenames are used """ - py_tool_path = pathlib.Path(py_tool_path) - if rules_path is None: + py_tool_path = pathlib.Path(py_tool_path) if render_dict: rules_path = py_tool_path.parent / (py_tool_path.stem + "_rules.ninja.mustache") else: From 6fc46df194f57ac979c561368d96f9c3d159c666 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Thu, 7 Dec 2023 22:12:36 -0700 Subject: [PATCH 03/25] working on loader --- bfasst/config.py | 2 +- bfasst/flows/encrypted_ip.py | 9 +++- bfasst/paths.py | 1 + bfasst/tools/ip/ipencrypter.py | 10 ++++- bfasst/tools/ip/loader.py | 47 +++++++++++++++++++++ bfasst/tools/ip/loader_build.ninja.mustache | 6 +++ bfasst/tools/ip/loader_vivado.tcl.mustache | 46 ++++++++++++++++++++ bfasst/tools/synth/vivado_synth.py | 1 - 8 files changed, 117 insertions(+), 5 deletions(-) create mode 100644 bfasst/tools/ip/loader.py create mode 100644 bfasst/tools/ip/loader_build.ninja.mustache create mode 100644 bfasst/tools/ip/loader_vivado.tcl.mustache diff --git a/bfasst/config.py b/bfasst/config.py index a40996282..065d1bb30 100644 --- a/bfasst/config.py +++ b/bfasst/config.py @@ -24,4 +24,4 @@ BUILD = "build" PART_FAMILY = "artix7" -PART = "xc7a200tsbg484-1" +PART = "xc7a100t-csg324-3" diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py index 3e3cc91cf..8ed6e48c2 100644 --- a/bfasst/flows/encrypted_ip.py +++ b/bfasst/flows/encrypted_ip.py @@ -3,6 +3,7 @@ from bfasst.flows.flow import Flow from bfasst.tools.ip.ipencrypter import IpEncrypter +from bfasst.tools.ip.loader import EncryptedIpLoader from bfasst.tools.synth.vivado_synth import VivadoSynth @@ -10,8 +11,8 @@ class EncryptedIP(Flow): def __init__(self, design): super().__init__(design) + # Synthesize and encrypt each encrypte IP for ip in self.design_props.encrypted_ip: - print(f"Encrypted IP: {ip}") synth_tool = VivadoSynth( self, design, @@ -29,5 +30,11 @@ def __init__(self, design): ip_encrypter_tool.build_path.parent / f"{ip_encrypter_tool.build_path.name}_{ip}" ) + # Synthesize the top module + synth_tool = VivadoSynth(self, design, ooc=True, synth_options="-flatten_hierarchy rebuilt") + + # Encrypted IP Shell + EncryptedIpLoader(self, design) + def get_top_level_flow_path(self): return pathlib.Path(__file__) diff --git a/bfasst/paths.py b/bfasst/paths.py index 8035ea704..1cb9b1926 100644 --- a/bfasst/paths.py +++ b/bfasst/paths.py @@ -36,6 +36,7 @@ ONESPIN_RESOURCES = RESOURCES_PATH / "onespin" YOSYS_INSTALL_DIR = THIRD_PARTY_PATH / "yosys" GMT_TOOLS_PATH = THIRD_PARTY_PATH / "gmt_tools" +ENCRYPTED_IP_PATH = THIRD_PARTY_PATH / "encrypted_ip" BFASST_UTILS_PATH = BFASST_PATH / "utils" diff --git a/bfasst/tools/ip/ipencrypter.py b/bfasst/tools/ip/ipencrypter.py index c9605d45e..a022c51b4 100644 --- a/bfasst/tools/ip/ipencrypter.py +++ b/bfasst/tools/ip/ipencrypter.py @@ -1,5 +1,6 @@ import json -from bfasst.paths import COMMON_TOOLS_PATH +from bfasst import config +from bfasst.paths import BFASST_UTILS_PATH, COMMON_TOOLS_PATH from bfasst.tools.tool import Tool from bfasst.utils.general import json_write_if_changed @@ -14,7 +15,12 @@ def __init__(self, flow, design_path, ip_dcp_path) -> None: def create_rule_snippets(self): self._append_rule_snippets_default(__file__) self._append_rule_snippets_default( - None, {}, COMMON_TOOLS_PATH / "vivado_rules.ninja.mustache" + None, + { + "vivado_path": config.VIVADO_BIN_PATH, + "utils_path": BFASST_UTILS_PATH, + }, + COMMON_TOOLS_PATH / "vivado_rules.ninja.mustache", ) def create_build_snippets(self): diff --git a/bfasst/tools/ip/loader.py b/bfasst/tools/ip/loader.py new file mode 100644 index 000000000..9748a7e99 --- /dev/null +++ b/bfasst/tools/ip/loader.py @@ -0,0 +1,47 @@ +import json +import pathlib +from bfasst import config +from bfasst.paths import BFASST_UTILS_PATH, COMMON_TOOLS_PATH, ENCRYPTED_IP_PATH +from bfasst.tools.tool import Tool +from bfasst.utils.general import json_write_if_changed + + +class EncryptedIpLoader(Tool): + def __init__(self, flow, design_path) -> None: + super().__init__(flow, design_path) + self.build_path = self.design_build_path / "loader" + self._my_dir_path = pathlib.Path(__file__).parent + self._init_outputs() + + def create_rule_snippets(self): + self._append_rule_snippets_default( + None, + { + "vivado_path": config.VIVADO_BIN_PATH, + "utils_path": BFASST_UTILS_PATH, + }, + COMMON_TOOLS_PATH / "vivado_rules.ninja.mustache", + ) + + def create_build_snippets(self): + vivado_tcl_dict = { + "loader_impl_dcp": str( + ENCRYPTED_IP_PATH / "Project" / "loader_imp_design" / "implemented_loader.dcp" + ) + } + vivado_tcl_json = json.dumps(vivado_tcl_dict, indent=4) + json_write_if_changed(self.build_path / "vivado.json", vivado_tcl_json) + + self._append_build_snippets_default( + __file__, + { + "cwd": self.build_path, + "loader_tcl_template": self._my_dir_path / "loader_vivado.tcl.mustache", + }, + ) + + def add_ninja_deps(self, deps): + self._add_ninja_deps_default(deps, __file__) + + def _init_outputs(self): + pass diff --git a/bfasst/tools/ip/loader_build.ninja.mustache b/bfasst/tools/ip/loader_build.ninja.mustache new file mode 100644 index 000000000..1aff8fb55 --- /dev/null +++ b/bfasst/tools/ip/loader_build.ninja.mustache @@ -0,0 +1,6 @@ +build {{ cwd }}/vivado.tcl: template {{ cwd }}/vivado.json {{ loader_tcl_template }} + +build abc: vivado {{ cwd }}/vivado.tcl + cwd = {{ cwd }} + journal = {{ cwd }}/vivado.jou + log = {{ cwd }}/vivado.log diff --git a/bfasst/tools/ip/loader_vivado.tcl.mustache b/bfasst/tools/ip/loader_vivado.tcl.mustache new file mode 100644 index 000000000..1ca7342f5 --- /dev/null +++ b/bfasst/tools/ip/loader_vivado.tcl.mustache @@ -0,0 +1,46 @@ + +open_checkpoint {{ loader_impl_dcp }} + +exit + +#set_property dont_touch true [get_cells $env(USER_SPACE_BLOCK_NAME)] +read_checkpoint -cell $env(USER_SPACE_BLOCK_NAME) ./checkpoints/$env(NAME_SYNTHED).dcp + +# Step 4: Place and route +puts "Time starting implementing partition DTIMING" +set a [exec date] +puts $a +place_design +route_design +puts "Time ending implementing partition DTIMING" +set a [exec date] +puts $a + +# Step 4: Write out implemented checkpoints +write_checkpoint ./checkpoints/$env(BITSTREAM_NAME_FULL).dcp -force +write_edif ./checkpoints/$env(BITSTREAM_NAME_FULL).edif -force + +puts "Time starting writing bitstream DTIMING" +set a [exec date] +puts $a + + +# Step 5.1: Bitstream for timing purposes +write_bitstream -bin_file -cell $env(USER_SPACE_BLOCK_NAME) partialpartialtiming.bit -force + + +puts "Time starting writing bitstreams not applicable for timing DTIMING" +set a [exec date] +puts $a +# Step 5.2: Write out full bitstream +write_bitstream -bin_file ./bitstreams/unencrypted/$env(BITSTREAM_NAME_FULL).bit -force + +#Step 6: Write out encrypted bitstream +set_property BITSTREAM.ENCRYPTION.ENCRYPT YES [get_designs checkpoint_$env(LOADER_DESIGN_NAME_IMPLEMENTED)] +set_property BITSTREAM.ENCRYPTION.ENCRYPTKEYSELECT EFUSE [get_designs checkpoint_$env(LOADER_DESIGN_NAME_IMPLEMENTED)] +set_property BITSTREAM.ENCRYPTION.KEYFILE ./key_files/design_1_wrapper.nky [get_designs checkpoint_$env(LOADER_DESIGN_NAME_IMPLEMENTED)] +#set_property BITSTREAM.GENERAL.CRC DISABLE [get_designs checkpoint_$env(LOADER_DESIGN_NAME_IMPLEMENTED)] +write_bitstream -bin_file ./bitstreams/encrypted/$env(BITSTREAM_NAME_FULL)_encrypted.bit -force +puts "Time ending writing bitstream not applicable for timing DTIMING" +set a [exec date] +puts $a \ No newline at end of file diff --git a/bfasst/tools/synth/vivado_synth.py b/bfasst/tools/synth/vivado_synth.py index 7c267e0c8..c173b8333 100644 --- a/bfasst/tools/synth/vivado_synth.py +++ b/bfasst/tools/synth/vivado_synth.py @@ -23,7 +23,6 @@ def create_rule_snippets(self): __file__, { "vivado_path": config.VIVADO_BIN_PATH, - "in_context": not self.ooc, "utils_path": BFASST_UTILS_PATH, }, COMMON_TOOLS_PATH / "vivado_rules.ninja.mustache", From 8087dd442a9441a51eed93c589961f0ac94e9b0e Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Fri, 8 Dec 2023 08:31:04 -0700 Subject: [PATCH 04/25] working on loader --- bfasst/flows/encrypted_ip.py | 2 +- bfasst/tools/ip/loader.py | 6 ++++-- bfasst/tools/ip/loader_vivado.tcl.mustache | 10 ++++------ 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py index 8ed6e48c2..aa76e6c82 100644 --- a/bfasst/flows/encrypted_ip.py +++ b/bfasst/flows/encrypted_ip.py @@ -34,7 +34,7 @@ def __init__(self, design): synth_tool = VivadoSynth(self, design, ooc=True, synth_options="-flatten_hierarchy rebuilt") # Encrypted IP Shell - EncryptedIpLoader(self, design) + EncryptedIpLoader(self, design, user_synth_dcp_path=synth_tool.outputs["synth_dcp"]) def get_top_level_flow_path(self): return pathlib.Path(__file__) diff --git a/bfasst/tools/ip/loader.py b/bfasst/tools/ip/loader.py index 9748a7e99..6765bdc23 100644 --- a/bfasst/tools/ip/loader.py +++ b/bfasst/tools/ip/loader.py @@ -7,10 +7,11 @@ class EncryptedIpLoader(Tool): - def __init__(self, flow, design_path) -> None: + def __init__(self, flow, design_path, user_synth_dcp_path) -> None: super().__init__(flow, design_path) self.build_path = self.design_build_path / "loader" self._my_dir_path = pathlib.Path(__file__).parent + self.user_synth_dcp_path = user_synth_dcp_path self._init_outputs() def create_rule_snippets(self): @@ -27,7 +28,8 @@ def create_build_snippets(self): vivado_tcl_dict = { "loader_impl_dcp": str( ENCRYPTED_IP_PATH / "Project" / "loader_imp_design" / "implemented_loader.dcp" - ) + ), + "user_synth_dcp": str(self.user_synth_dcp_path), } vivado_tcl_json = json.dumps(vivado_tcl_dict, indent=4) json_write_if_changed(self.build_path / "vivado.json", vivado_tcl_json) diff --git a/bfasst/tools/ip/loader_vivado.tcl.mustache b/bfasst/tools/ip/loader_vivado.tcl.mustache index 1ca7342f5..4fb1ac906 100644 --- a/bfasst/tools/ip/loader_vivado.tcl.mustache +++ b/bfasst/tools/ip/loader_vivado.tcl.mustache @@ -1,20 +1,18 @@ open_checkpoint {{ loader_impl_dcp }} -exit #set_property dont_touch true [get_cells $env(USER_SPACE_BLOCK_NAME)] -read_checkpoint -cell $env(USER_SPACE_BLOCK_NAME) ./checkpoints/$env(NAME_SYNTHED).dcp +read_checkpoint -cell "static_top_i/top_0" {{ user_synth_dcp }} +exit # Step 4: Place and route puts "Time starting implementing partition DTIMING" -set a [exec date] -puts $a +puts [exec date] place_design route_design puts "Time ending implementing partition DTIMING" -set a [exec date] -puts $a +puts [exec date] # Step 4: Write out implemented checkpoints write_checkpoint ./checkpoints/$env(BITSTREAM_NAME_FULL).dcp -force From 111c02111fbd7771857c64c2840a021abc94c4d7 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Fri, 8 Dec 2023 10:10:11 -0700 Subject: [PATCH 05/25] fix dependencies --- .../tools/ip/ipencrypter_build.ninja.mustache | 6 +- bfasst/tools/ip/ipencrypter_rules.ninja | 2 +- bfasst/tools/ip/loader.py | 1 + bfasst/tools/ip/loader_build.ninja.mustache | 2 +- bfasst/yaml_parser.py | 2 + .../pid_test/16x16bit_multiplier_pipelined.v | 1413 +++++++++++++++++ designs/encrypted_ip/pid_test/CLA_fixed.v | 259 +++ designs/encrypted_ip/pid_test/PID.v | 434 +++++ designs/encrypted_ip/pid_test/PID_defines.v | 8 + designs/encrypted_ip/pid_test/booth.v | 37 + designs/encrypted_ip/pid_test/design.yaml | 3 + .../encrypted_ip/pid_test/divider_dshift.v | 273 ++++ designs/encrypted_ip/pid_test/shifter.v | 319 ++++ designs/encrypted_ip/pid_test/top.v | 115 ++ 14 files changed, 2869 insertions(+), 5 deletions(-) create mode 100644 designs/encrypted_ip/pid_test/16x16bit_multiplier_pipelined.v create mode 100644 designs/encrypted_ip/pid_test/CLA_fixed.v create mode 100644 designs/encrypted_ip/pid_test/PID.v create mode 100644 designs/encrypted_ip/pid_test/PID_defines.v create mode 100644 designs/encrypted_ip/pid_test/booth.v create mode 100644 designs/encrypted_ip/pid_test/design.yaml create mode 100644 designs/encrypted_ip/pid_test/divider_dshift.v create mode 100644 designs/encrypted_ip/pid_test/shifter.v create mode 100644 designs/encrypted_ip/pid_test/top.v diff --git a/bfasst/tools/ip/ipencrypter_build.ninja.mustache b/bfasst/tools/ip/ipencrypter_build.ninja.mustache index 26ec3d7b3..03911efbf 100644 --- a/bfasst/tools/ip/ipencrypter_build.ninja.mustache +++ b/bfasst/tools/ip/ipencrypter_build.ninja.mustache @@ -1,5 +1,4 @@ -build {{ log_file }} {{ dcp_encrypted }}: encrypt_ip - dcp_unencrypted = {{ dcp_unencrypted }} +build {{ log_file }} {{ dcp_encrypted }}: encrypt_ip {{ dcp_unencrypted }} key = 00112233445566778899AABBCCDDEEFF dcp_encrypted = {{ dcp_encrypted }} lut_ciphertext = {{ lut_ciphertext }} @@ -8,7 +7,8 @@ build {{ log_file }} {{ dcp_encrypted }}: encrypt_ip build {{ cwd }}/dcp_to_v.tcl: template {{ cwd }}/dcp_to_v.json {{ gen_encrypted_verilog_template }} cwd = {{ cwd }} -build {{ verilog_encrypted }}: vivado {{ cwd }}/dcp_to_v.tcl +build {{ verilog_encrypted }}: vivado {{ cwd }}/dcp_to_v.tcl {{ dcp_encrypted }} cwd = {{ cwd }} journal = {{ cwd }}/vivado.jou log = {{ cwd }}/vivado.log + diff --git a/bfasst/tools/ip/ipencrypter_rules.ninja b/bfasst/tools/ip/ipencrypter_rules.ninja index ce7bb57ac..1d8227473 100644 --- a/bfasst/tools/ip/ipencrypter_rules.ninja +++ b/bfasst/tools/ip/ipencrypter_rules.ninja @@ -1,4 +1,4 @@ rule encrypt_ip - command = python third_party/encrypted_ip/Project/python_scripts/encryptDesign.py $dcp_unencrypted $key $dcp_encrypted $lut_ciphertext > $log_file + command = python third_party/encrypted_ip/Project/python_scripts/encryptDesign.py $in $key $dcp_encrypted $lut_ciphertext > $log_file description = encrypt ip $dcp_unencrypted diff --git a/bfasst/tools/ip/loader.py b/bfasst/tools/ip/loader.py index 6765bdc23..181e74cbb 100644 --- a/bfasst/tools/ip/loader.py +++ b/bfasst/tools/ip/loader.py @@ -39,6 +39,7 @@ def create_build_snippets(self): { "cwd": self.build_path, "loader_tcl_template": self._my_dir_path / "loader_vivado.tcl.mustache", + "top_dcp": str(self.user_synth_dcp_path), }, ) diff --git a/bfasst/tools/ip/loader_build.ninja.mustache b/bfasst/tools/ip/loader_build.ninja.mustache index 1aff8fb55..b273a475d 100644 --- a/bfasst/tools/ip/loader_build.ninja.mustache +++ b/bfasst/tools/ip/loader_build.ninja.mustache @@ -1,6 +1,6 @@ build {{ cwd }}/vivado.tcl: template {{ cwd }}/vivado.json {{ loader_tcl_template }} -build abc: vivado {{ cwd }}/vivado.tcl +build abc: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} cwd = {{ cwd }} journal = {{ cwd }}/vivado.jou log = {{ cwd }}/vivado.log diff --git a/bfasst/yaml_parser.py b/bfasst/yaml_parser.py index 0b37bc2f5..f6d701398 100644 --- a/bfasst/yaml_parser.py +++ b/bfasst/yaml_parser.py @@ -99,6 +99,8 @@ class DesignParser(YamlParser): def __init__(self, yaml_path): super().__init__(yaml_path) + assert self.props, f"Design {self.yaml_path} is empty" + # Get top module name if "top" not in self.props: error(f"Design {self.yaml_path} does not specify a top module") diff --git a/designs/encrypted_ip/pid_test/16x16bit_multiplier_pipelined.v b/designs/encrypted_ip/pid_test/16x16bit_multiplier_pipelined.v new file mode 100644 index 000000000..7e9f45680 --- /dev/null +++ b/designs/encrypted_ip/pid_test/16x16bit_multiplier_pipelined.v @@ -0,0 +1,1413 @@ +/*16x16-bit multiplier +Author: Zhu Xu +Email: m99a1@yahoo.cn +*/ + +//Booth Encoder Array +module booth_array( +input [15:0]multiplier, +output [7:0]zero, +output [7:0]double, +output [7:0]negation +); + +booth_radix4 booth_radix4_0( +{multiplier[1:0],1'b0}, +zero[0], +double[0], +negation[0] +); + +booth_radix4 booth_radix4_1( +multiplier[3:1], +zero[1], +double[1], +negation[1] +); + +booth_radix4 booth_radix4_2( +multiplier[5:3], +zero[2], +double[2], +negation[2] +); +booth_radix4 booth_radix4_3( +multiplier[7:5], +zero[3], +double[3], +negation[3] +); + +booth_radix4 booth_radix4_4( +multiplier[9:7], +zero[4], +double[4], +negation[4] +); + +booth_radix4 booth_radix4_5( +multiplier[11:9], +zero[5], +double[5], +negation[5] +); +booth_radix4 booth_radix4_6( +multiplier[13:11], +zero[6], +double[6], +negation[6] +); + +booth_radix4 booth_radix4_7( +multiplier[15:13], +zero[7], +double[7], +negation[7] +); + +endmodule + +/*partial product generator unit +generate one 17-bit partial with inversed MSB without correction bit for negation +*/ +module partial_product_gen( +input [15:0]md, //multiplicand +input zero, +input double, +input negation, +output [16:0]pp +); + +wire [15:0]nmd; +assign nmd=negation?~md:md; + +wire [15:0]zmd; +assign zmd=zero?0:nmd; + +assign pp=double?{~zmd[15],zmd[14:0],negation}:{~zmd[15],zmd[15:0]}; + +endmodule + +module half_adder( +input A, +input B, +output S, +output carry +); +assign S=A^B; +assign carry=A&B; +endmodule + +module full_adder( +input A, +input B, +input cin, +output S, +output cout +); +wire AB; +assign AB=A&B; +wire AxorB; +assign AxorB=A^B; +assign S=AxorB^cin; +assign cout=AB|(AxorB&cin); +endmodule + +module compressor42( +input A, +input B, +input C, +input D, +input cin, +output S, +output carry, +output cout +); +wire AB; +assign AB=A&B; +wire AxorB; +assign AxorB=A^B; +wire CD; +assign CD=C&D; +wire CxorD; +assign CxorD=C^D; + +wire AxBxCxD=AxorB^CxorD; + +assign cout=AB|CD; +assign carry=(AB&CD)|(AxorB&CxorD)|((AxBxCxD)&cin); + +assign S=AxBxCxD^cin; + +endmodule + + +module multiplier_16x16bit_pipelined( +input i_clk, +input i_rst, +input i_start, +input [15:0]i_md, +input [15:0]i_mr, +output [31:0]o_product, +output o_ready +); +/////////////////////////////////////////////////////////////stage 0/////////////////////////////////////////////////// + +reg [15:0]md; +reg [15:0]mr; +reg stage_0_ready; + +always @(posedge i_clk or negedge i_rst)begin + if(!i_rst)begin + md<=0; + mr<=0; + stage_0_ready<=0; + end + else begin + if(i_start)begin + md<=i_md; + mr<=i_mr; + end + stage_0_ready<=i_start; + end + +end + +wire [7:0]zero; +wire [7:0]double; +wire [7:0]negation; + +booth_array booth_array_0( +mr, +zero, +double, +negation +); + + +//layer 0 +wire layer_0_w0[1:0]; +wire layer_0_w1; +wire layer_0_w2[2:0]; +wire layer_0_w3[1:0]; +wire layer_0_w4[3:0]; +wire layer_0_w5[2:0]; +wire layer_0_w6[4:0]; +wire layer_0_w7[3:0]; +wire layer_0_w8[5:0]; +wire layer_0_w9[4:0]; +wire layer_0_w10[6:0]; +wire layer_0_w11[5:0]; +wire layer_0_w12[7:0]; +wire layer_0_w13[6:0]; +wire layer_0_w14[8:0]; +wire layer_0_w15[7:0]; +wire layer_0_w16[8:0]; +wire layer_0_w17[7:0]; +wire layer_0_w18[6:0]; +wire layer_0_w19[6:0]; +wire layer_0_w20[5:0]; +wire layer_0_w21[5:0]; +wire layer_0_w22[4:0]; +wire layer_0_w23[4:0]; +wire layer_0_w24[3:0]; +wire layer_0_w25[3:0]; +wire layer_0_w26[2:0]; +wire layer_0_w27[2:0]; +wire layer_0_w28[1:0]; +wire layer_0_w29[1:0]; +wire layer_0_w30; +wire layer_0_w31; +partial_product_gen partial_product_gen_0( +md, +zero[0], +double[0], +negation[0], +{layer_0_w16[0],layer_0_w15[0],layer_0_w14[0],layer_0_w13[0],layer_0_w12[0],layer_0_w11[0],layer_0_w10[0],layer_0_w9[0],layer_0_w8[0],layer_0_w7[0],layer_0_w6[0],layer_0_w5[0],layer_0_w4[0],layer_0_w3[0],layer_0_w2[0],layer_0_w1,layer_0_w0[0]} +); +partial_product_gen partial_product_gen_1( +md, +zero[1], +double[1], +negation[1], +{layer_0_w18[0],layer_0_w17[0],layer_0_w16[1],layer_0_w15[1],layer_0_w14[1],layer_0_w13[1],layer_0_w12[1],layer_0_w11[1],layer_0_w10[1],layer_0_w9[1],layer_0_w8[1],layer_0_w7[1],layer_0_w6[1],layer_0_w5[1],layer_0_w4[1],layer_0_w3[1],layer_0_w2[1]} +); +partial_product_gen partial_product_gen_2( +md, +zero[2], +double[2], +negation[2], +{layer_0_w20[0],layer_0_w19[0],layer_0_w18[1],layer_0_w17[1],layer_0_w16[2],layer_0_w15[2],layer_0_w14[2],layer_0_w13[2],layer_0_w12[2],layer_0_w11[2],layer_0_w10[2],layer_0_w9[2],layer_0_w8[2],layer_0_w7[2],layer_0_w6[2],layer_0_w5[2],layer_0_w4[2]} +); +partial_product_gen partial_product_gen_3( +md, +zero[3], +double[3], +negation[3], +{layer_0_w22[0],layer_0_w21[0],layer_0_w20[1],layer_0_w19[1],layer_0_w18[2],layer_0_w17[2],layer_0_w16[3],layer_0_w15[3],layer_0_w14[3],layer_0_w13[3],layer_0_w12[3],layer_0_w11[3],layer_0_w10[3],layer_0_w9[3],layer_0_w8[3],layer_0_w7[3],layer_0_w6[3]} +); +partial_product_gen partial_product_gen_4( +md, +zero[4], +double[4], +negation[4], +{layer_0_w24[0],layer_0_w23[0],layer_0_w22[1],layer_0_w21[1],layer_0_w20[2],layer_0_w19[2],layer_0_w18[3],layer_0_w17[3],layer_0_w16[4],layer_0_w15[4],layer_0_w14[4],layer_0_w13[4],layer_0_w12[4],layer_0_w11[4],layer_0_w10[4],layer_0_w9[4],layer_0_w8[4]} +); +partial_product_gen partial_product_gen_5( +md, +zero[5], +double[5], +negation[5], +{layer_0_w26[0],layer_0_w25[0],layer_0_w24[1],layer_0_w23[1],layer_0_w22[2],layer_0_w21[2],layer_0_w20[3],layer_0_w19[3],layer_0_w18[4],layer_0_w17[4],layer_0_w16[5],layer_0_w15[5],layer_0_w14[5],layer_0_w13[5],layer_0_w12[5],layer_0_w11[5],layer_0_w10[5]} +); +partial_product_gen partial_product_gen_6( +md, +zero[6], +double[6], +negation[6], +{layer_0_w28[0],layer_0_w27[0],layer_0_w26[1],layer_0_w25[1],layer_0_w24[2],layer_0_w23[2],layer_0_w22[3],layer_0_w21[3],layer_0_w20[4],layer_0_w19[4],layer_0_w18[5],layer_0_w17[5],layer_0_w16[6],layer_0_w15[6],layer_0_w14[6],layer_0_w13[6],layer_0_w12[6]} +); +partial_product_gen partial_product_gen_7( +md, +zero[7], +double[7], +negation[7], +{layer_0_w30,layer_0_w29[0],layer_0_w28[1],layer_0_w27[1],layer_0_w26[2],layer_0_w25[2],layer_0_w24[3],layer_0_w23[3],layer_0_w22[4],layer_0_w21[4],layer_0_w20[5],layer_0_w19[5],layer_0_w18[6],layer_0_w17[6],layer_0_w16[7],layer_0_w15[7],layer_0_w14[7]} +); +//correction for negation +assign layer_0_w0[1]=negation[0]; +//sign extension +assign layer_0_w16[8]=1; +assign layer_0_w17[7]=1; +//correction for negation +assign layer_0_w2[2]=negation[1]; +//sign extension +assign layer_0_w19[6]=1; +//correction for negation +assign layer_0_w4[3]=negation[2]; +//sign extension +assign layer_0_w21[5]=1; +//correction for negation +assign layer_0_w6[4]=negation[3]; +//sign extension +assign layer_0_w23[4]=1; +//correction for negation +assign layer_0_w8[5]=negation[4]; +//sign extension +assign layer_0_w25[3]=1; +//correction for negation +assign layer_0_w10[6]=negation[5]; +//sign extension +assign layer_0_w27[2]=1; +//correction for negation +assign layer_0_w12[7]=negation[6]; +//sign extension +assign layer_0_w29[1]=1; +//correction for negation +assign layer_0_w14[8]=negation[7]; +//sign extension +assign layer_0_w31=1; + +//layer 1 +wire layer_1_w0[1:0]; +wire layer_1_w1; +wire layer_1_w2[2:0]; +wire layer_1_w3[1:0]; +wire layer_1_w4[1:0]; +wire layer_1_w5[1:0]; +wire layer_1_w6[1:0]; +wire layer_1_w7[3:0]; +wire layer_1_w8[2:0]; +wire layer_1_w9[2:0]; +wire layer_1_w10[4:0]; +wire layer_1_w11[3:0]; +wire layer_1_w12[3:0]; +wire layer_1_w13[5:0]; +wire layer_1_w14[4:0]; +wire layer_1_w15[4:0]; +wire layer_1_w16[5:0]; +wire layer_1_w17[4:0]; +wire layer_1_w18[5:0]; +wire layer_1_w19[4:0]; +wire layer_1_w20[3:0]; +wire layer_1_w21[3:0]; +wire layer_1_w22[2:0]; +wire layer_1_w23[2:0]; +wire layer_1_w24[3:0]; +wire layer_1_w25[2:0]; +wire layer_1_w26[1:0]; +wire layer_1_w27[1:0]; +wire layer_1_w28[2:0]; +wire layer_1_w29[1:0]; +wire layer_1_w30; +wire layer_1_w31; +assign layer_1_w0[0]=layer_0_w0[0]; +assign layer_1_w0[1]=layer_0_w0[1]; +assign layer_1_w1=layer_0_w1; +assign layer_1_w2[0]=layer_0_w2[0]; +assign layer_1_w2[1]=layer_0_w2[1]; +assign layer_1_w2[2]=layer_0_w2[2]; +assign layer_1_w3[0]=layer_0_w3[0]; +assign layer_1_w3[1]=layer_0_w3[1]; +full_adder layer_1_full_adder_0( +layer_0_w4[0], +layer_0_w4[1], +layer_0_w4[2], +layer_1_w4[0], +layer_1_w5[0] +); +assign layer_1_w4[1]=layer_0_w4[3]; +full_adder layer_1_full_adder_1( +layer_0_w5[0], +layer_0_w5[1], +layer_0_w5[2], +layer_1_w5[1], +layer_1_w6[0] +); +compressor42 layer_1_compressor42_0( +layer_0_w6[0], +layer_0_w6[1], +layer_0_w6[2], +layer_0_w6[3], +layer_0_w6[4], +layer_1_w6[1], +layer_1_w7[0], +layer_1_w7[1] +); +full_adder layer_1_full_adder_2( +layer_0_w7[0], +layer_0_w7[1], +layer_0_w7[2], +layer_1_w7[2], +layer_1_w8[0] +); +assign layer_1_w7[3]=layer_0_w7[3]; +compressor42 layer_1_compressor42_1( +layer_0_w8[0], +layer_0_w8[1], +layer_0_w8[2], +layer_0_w8[3], +layer_0_w8[4], +layer_1_w8[1], +layer_1_w9[0], +layer_1_w9[1] +); +assign layer_1_w8[2]=layer_0_w8[5]; +compressor42 layer_1_compressor42_2( +layer_0_w9[0], +layer_0_w9[1], +layer_0_w9[2], +layer_0_w9[3], +layer_0_w9[4], +layer_1_w9[2], +layer_1_w10[0], +layer_1_w10[1] +); +compressor42 layer_1_compressor42_3( +layer_0_w10[0], +layer_0_w10[1], +layer_0_w10[2], +layer_0_w10[3], +layer_0_w10[4], +layer_1_w10[2], +layer_1_w11[0], +layer_1_w11[1] +); +assign layer_1_w10[3]=layer_0_w10[5]; +assign layer_1_w10[4]=layer_0_w10[6]; +compressor42 layer_1_compressor42_4( +layer_0_w11[0], +layer_0_w11[1], +layer_0_w11[2], +layer_0_w11[3], +layer_0_w11[4], +layer_1_w11[2], +layer_1_w12[0], +layer_1_w12[1] +); +assign layer_1_w11[3]=layer_0_w11[5]; +compressor42 layer_1_compressor42_5( +layer_0_w12[0], +layer_0_w12[1], +layer_0_w12[2], +layer_0_w12[3], +layer_0_w12[4], +layer_1_w12[2], +layer_1_w13[0], +layer_1_w13[1] +); +full_adder layer_1_full_adder_3( +layer_0_w12[5], +layer_0_w12[6], +layer_0_w12[7], +layer_1_w12[3], +layer_1_w13[2] +); +compressor42 layer_1_compressor42_6( +layer_0_w13[0], +layer_0_w13[1], +layer_0_w13[2], +layer_0_w13[3], +layer_0_w13[4], +layer_1_w13[3], +layer_1_w14[0], +layer_1_w14[1] +); +assign layer_1_w13[4]=layer_0_w13[5]; +assign layer_1_w13[5]=layer_0_w13[6]; +compressor42 layer_1_compressor42_7( +layer_0_w14[0], +layer_0_w14[1], +layer_0_w14[2], +layer_0_w14[3], +layer_0_w14[4], +layer_1_w14[2], +layer_1_w15[0], +layer_1_w15[1] +); +full_adder layer_1_full_adder_4( +layer_0_w14[5], +layer_0_w14[6], +layer_0_w14[7], +layer_1_w14[3], +layer_1_w15[2] +); +assign layer_1_w14[4]=layer_0_w14[8]; +compressor42 layer_1_compressor42_8( +layer_0_w15[0], +layer_0_w15[1], +layer_0_w15[2], +layer_0_w15[3], +layer_0_w15[4], +layer_1_w15[3], +layer_1_w16[0], +layer_1_w16[1] +); +full_adder layer_1_full_adder_5( +layer_0_w15[5], +layer_0_w15[6], +layer_0_w15[7], +layer_1_w15[4], +layer_1_w16[2] +); +compressor42 layer_1_compressor42_9( +layer_0_w16[0], +layer_0_w16[1], +layer_0_w16[2], +layer_0_w16[3], +layer_0_w16[4], +layer_1_w16[3], +layer_1_w17[0], +layer_1_w17[1] +); +full_adder layer_1_full_adder_6( +layer_0_w16[5], +layer_0_w16[6], +layer_0_w16[7], +layer_1_w16[4], +layer_1_w17[2] +); +assign layer_1_w16[5]=layer_0_w16[8]; +compressor42 layer_1_compressor42_10( +layer_0_w17[0], +layer_0_w17[1], +layer_0_w17[2], +layer_0_w17[3], +layer_0_w17[4], +layer_1_w17[3], +layer_1_w18[0], +layer_1_w18[1] +); +full_adder layer_1_full_adder_7( +layer_0_w17[5], +layer_0_w17[6], +layer_0_w17[7], +layer_1_w17[4], +layer_1_w18[2] +); +compressor42 layer_1_compressor42_11( +layer_0_w18[0], +layer_0_w18[1], +layer_0_w18[2], +layer_0_w18[3], +layer_0_w18[4], +layer_1_w18[3], +layer_1_w19[0], +layer_1_w19[1] +); +assign layer_1_w18[4]=layer_0_w18[5]; +assign layer_1_w18[5]=layer_0_w18[6]; +compressor42 layer_1_compressor42_12( +layer_0_w19[0], +layer_0_w19[1], +layer_0_w19[2], +layer_0_w19[3], +layer_0_w19[4], +layer_1_w19[2], +layer_1_w20[0], +layer_1_w20[1] +); +assign layer_1_w19[3]=layer_0_w19[5]; +assign layer_1_w19[4]=layer_0_w19[6]; +compressor42 layer_1_compressor42_13( +layer_0_w20[0], +layer_0_w20[1], +layer_0_w20[2], +layer_0_w20[3], +layer_0_w20[4], +layer_1_w20[2], +layer_1_w21[0], +layer_1_w21[1] +); +assign layer_1_w20[3]=layer_0_w20[5]; +compressor42 layer_1_compressor42_14( +layer_0_w21[0], +layer_0_w21[1], +layer_0_w21[2], +layer_0_w21[3], +layer_0_w21[4], +layer_1_w21[2], +layer_1_w22[0], +layer_1_w22[1] +); +assign layer_1_w21[3]=layer_0_w21[5]; +compressor42 layer_1_compressor42_15( +layer_0_w22[0], +layer_0_w22[1], +layer_0_w22[2], +layer_0_w22[3], +layer_0_w22[4], +layer_1_w22[2], +layer_1_w23[0], +layer_1_w23[1] +); +compressor42 layer_1_compressor42_16( +layer_0_w23[0], +layer_0_w23[1], +layer_0_w23[2], +layer_0_w23[3], +layer_0_w23[4], +layer_1_w23[2], +layer_1_w24[0], +layer_1_w24[1] +); +full_adder layer_1_full_adder_8( +layer_0_w24[0], +layer_0_w24[1], +layer_0_w24[2], +layer_1_w24[2], +layer_1_w25[0] +); +assign layer_1_w24[3]=layer_0_w24[3]; +full_adder layer_1_full_adder_9( +layer_0_w25[0], +layer_0_w25[1], +layer_0_w25[2], +layer_1_w25[1], +layer_1_w26[0] +); +assign layer_1_w25[2]=layer_0_w25[3]; +full_adder layer_1_full_adder_10( +layer_0_w26[0], +layer_0_w26[1], +layer_0_w26[2], +layer_1_w26[1], +layer_1_w27[0] +); +full_adder layer_1_full_adder_11( +layer_0_w27[0], +layer_0_w27[1], +layer_0_w27[2], +layer_1_w27[1], +layer_1_w28[0] +); +assign layer_1_w28[1]=layer_0_w28[0]; +assign layer_1_w28[2]=layer_0_w28[1]; +assign layer_1_w29[0]=layer_0_w29[0]; +assign layer_1_w29[1]=layer_0_w29[1]; +assign layer_1_w30=layer_0_w30; +assign layer_1_w31=layer_0_w31; + +//layer 2 +wire [1:0]layer_2_w0; +wire layer_2_w1; +wire [2:0]layer_2_w2; +wire [1:0]layer_2_w3; +wire [1:0]layer_2_w4; +wire [1:0]layer_2_w5; +wire [1:0]layer_2_w6; +wire [1:0]layer_2_w7; +wire [1:0]layer_2_w8; +wire [1:0]layer_2_w9; +wire [1:0]layer_2_w10; +wire [3:0]layer_2_w11; +wire [2:0]layer_2_w12; +wire [2:0]layer_2_w13; +wire [2:0]layer_2_w14; +wire [2:0]layer_2_w15; +wire [3:0]layer_2_w16; +wire [2:0]layer_2_w17; +wire [3:0]layer_2_w18; +wire [2:0]layer_2_w19; +wire [3:0]layer_2_w20; +wire [2:0]layer_2_w21; +wire [1:0]layer_2_w22; +wire [1:0]layer_2_w23; +wire [2:0]layer_2_w24; +wire [1:0]layer_2_w25; +wire [2:0]layer_2_w26; +wire [1:0]layer_2_w27; +wire layer_2_w28; +wire [2:0]layer_2_w29; +wire layer_2_w30; +wire layer_2_w31; +assign layer_2_w0[0]=layer_1_w0[0]; +assign layer_2_w0[1]=layer_1_w0[1]; +assign layer_2_w1=layer_1_w1; +assign layer_2_w2[0]=layer_1_w2[0]; +assign layer_2_w2[1]=layer_1_w2[1]; +assign layer_2_w2[2]=layer_1_w2[2]; +assign layer_2_w3[0]=layer_1_w3[0]; +assign layer_2_w3[1]=layer_1_w3[1]; +assign layer_2_w4[0]=layer_1_w4[0]; +assign layer_2_w4[1]=layer_1_w4[1]; +assign layer_2_w5[0]=layer_1_w5[0]; +assign layer_2_w5[1]=layer_1_w5[1]; +assign layer_2_w6[0]=layer_1_w6[0]; +assign layer_2_w6[1]=layer_1_w6[1]; +full_adder layer_2_full_adder_0( +layer_1_w7[0], +layer_1_w7[1], +layer_1_w7[2], +layer_2_w7[0], +layer_2_w8[0] +); +assign layer_2_w7[1]=layer_1_w7[3]; +full_adder layer_2_full_adder_1( +layer_1_w8[0], +layer_1_w8[1], +layer_1_w8[2], +layer_2_w8[1], +layer_2_w9[0] +); +full_adder layer_2_full_adder_2( +layer_1_w9[0], +layer_1_w9[1], +layer_1_w9[2], +layer_2_w9[1], +layer_2_w10[0] +); +compressor42 layer_2_compressor42_0( +layer_1_w10[0], +layer_1_w10[1], +layer_1_w10[2], +layer_1_w10[3], +layer_1_w10[4], +layer_2_w10[1], +layer_2_w11[0], +layer_2_w11[1] +); +full_adder layer_2_full_adder_3( +layer_1_w11[0], +layer_1_w11[1], +layer_1_w11[2], +layer_2_w11[2], +layer_2_w12[0] +); +assign layer_2_w11[3]=layer_1_w11[3]; +full_adder layer_2_full_adder_4( +layer_1_w12[0], +layer_1_w12[1], +layer_1_w12[2], +layer_2_w12[1], +layer_2_w13[0] +); +assign layer_2_w12[2]=layer_1_w12[3]; +compressor42 layer_2_compressor42_1( +layer_1_w13[0], +layer_1_w13[1], +layer_1_w13[2], +layer_1_w13[3], +layer_1_w13[4], +layer_2_w13[1], +layer_2_w14[0], +layer_2_w14[1] +); +assign layer_2_w13[2]=layer_1_w13[5]; +compressor42 layer_2_compressor42_2( +layer_1_w14[0], +layer_1_w14[1], +layer_1_w14[2], +layer_1_w14[3], +layer_1_w14[4], +layer_2_w14[2], +layer_2_w15[0], +layer_2_w15[1] +); +compressor42 layer_2_compressor42_3( +layer_1_w15[0], +layer_1_w15[1], +layer_1_w15[2], +layer_1_w15[3], +layer_1_w15[4], +layer_2_w15[2], +layer_2_w16[0], +layer_2_w16[1] +); +compressor42 layer_2_compressor42_4( +layer_1_w16[0], +layer_1_w16[1], +layer_1_w16[2], +layer_1_w16[3], +layer_1_w16[4], +layer_2_w16[2], +layer_2_w17[0], +layer_2_w17[1] +); +assign layer_2_w16[3]=layer_1_w16[5]; +compressor42 layer_2_compressor42_5( +layer_1_w17[0], +layer_1_w17[1], +layer_1_w17[2], +layer_1_w17[3], +layer_1_w17[4], +layer_2_w17[2], +layer_2_w18[0], +layer_2_w18[1] +); +compressor42 layer_2_compressor42_6( +layer_1_w18[0], +layer_1_w18[1], +layer_1_w18[2], +layer_1_w18[3], +layer_1_w18[4], +layer_2_w18[2], +layer_2_w19[0], +layer_2_w19[1] +); +assign layer_2_w18[3]=layer_1_w18[5]; +compressor42 layer_2_compressor42_7( +layer_1_w19[0], +layer_1_w19[1], +layer_1_w19[2], +layer_1_w19[3], +layer_1_w19[4], +layer_2_w19[2], +layer_2_w20[0], +layer_2_w20[1] +); +full_adder layer_2_full_adder_5( +layer_1_w20[0], +layer_1_w20[1], +layer_1_w20[2], +layer_2_w20[2], +layer_2_w21[0] +); +assign layer_2_w20[3]=layer_1_w20[3]; +full_adder layer_2_full_adder_6( +layer_1_w21[0], +layer_1_w21[1], +layer_1_w21[2], +layer_2_w21[1], +layer_2_w22[0] +); +assign layer_2_w21[2]=layer_1_w21[3]; +full_adder layer_2_full_adder_7( +layer_1_w22[0], +layer_1_w22[1], +layer_1_w22[2], +layer_2_w22[1], +layer_2_w23[0] +); +full_adder layer_2_full_adder_8( +layer_1_w23[0], +layer_1_w23[1], +layer_1_w23[2], +layer_2_w23[1], +layer_2_w24[0] +); +full_adder layer_2_full_adder_9( +layer_1_w24[0], +layer_1_w24[1], +layer_1_w24[2], +layer_2_w24[1], +layer_2_w25[0] +); +assign layer_2_w24[2]=layer_1_w24[3]; +full_adder layer_2_full_adder_10( +layer_1_w25[0], +layer_1_w25[1], +layer_1_w25[2], +layer_2_w25[1], +layer_2_w26[0] +); +assign layer_2_w26[1]=layer_1_w26[0]; +assign layer_2_w26[2]=layer_1_w26[1]; +assign layer_2_w27[0]=layer_1_w27[0]; +assign layer_2_w27[1]=layer_1_w27[1]; +full_adder layer_2_full_adder_11( +layer_1_w28[0], +layer_1_w28[1], +layer_1_w28[2], +layer_2_w28, +layer_2_w29[0] +); +assign layer_2_w29[1]=layer_1_w29[0]; +assign layer_2_w29[2]=layer_1_w29[1]; +assign layer_2_w30=layer_1_w30; +assign layer_2_w31=layer_1_w31; + + +///////////////////////////////////////////////////////stage 1/////////////////////////////////////////////////////// +reg [1:0]reg_layer_2_w0; +reg reg_layer_2_w1; +reg [2:0]reg_layer_2_w2; +reg [1:0]reg_layer_2_w3; +reg [1:0]reg_layer_2_w4; +reg [1:0]reg_layer_2_w5; +reg [1:0]reg_layer_2_w6; +reg [1:0]reg_layer_2_w7; +reg [1:0]reg_layer_2_w8; +reg [1:0]reg_layer_2_w9; +reg [1:0]reg_layer_2_w10; +reg [3:0]reg_layer_2_w11; +reg [2:0]reg_layer_2_w12; +reg [2:0]reg_layer_2_w13; +reg [2:0]reg_layer_2_w14; +reg [2:0]reg_layer_2_w15; +reg [3:0]reg_layer_2_w16; +reg [2:0]reg_layer_2_w17; +reg [3:0]reg_layer_2_w18; +reg [2:0]reg_layer_2_w19; +reg [3:0]reg_layer_2_w20; +reg [2:0]reg_layer_2_w21; +reg [1:0]reg_layer_2_w22; +reg [1:0]reg_layer_2_w23; +reg [2:0]reg_layer_2_w24; +reg [1:0]reg_layer_2_w25; +reg [2:0]reg_layer_2_w26; +reg [1:0]reg_layer_2_w27; +reg reg_layer_2_w28; +reg [2:0]reg_layer_2_w29; +reg reg_layer_2_w30; +reg reg_layer_2_w31; +reg stage_1_ready; +assign o_ready=stage_1_ready; + +always @(posedge i_clk or negedge i_rst)begin + if(!i_rst)begin + stage_1_ready<=0; + reg_layer_2_w0<=0; + reg_layer_2_w1<=0; + reg_layer_2_w2<=0; + reg_layer_2_w3<=0; + reg_layer_2_w4<=0; + reg_layer_2_w5<=0; + reg_layer_2_w6<=0; + reg_layer_2_w7<=0; + reg_layer_2_w8<=0; + reg_layer_2_w9<=0; + reg_layer_2_w10<=0; + reg_layer_2_w11<=0; + reg_layer_2_w12<=0; + reg_layer_2_w13<=0; + reg_layer_2_w14<=0; + reg_layer_2_w15<=0; + reg_layer_2_w16<=0; + reg_layer_2_w17<=0; + reg_layer_2_w18<=0; + reg_layer_2_w19<=0; + reg_layer_2_w20<=0; + reg_layer_2_w21<=0; + reg_layer_2_w22<=0; + reg_layer_2_w23<=0; + reg_layer_2_w24<=0; + reg_layer_2_w25<=0; + reg_layer_2_w26<=0; + reg_layer_2_w27<=0; + reg_layer_2_w28<=0; + reg_layer_2_w29<=0; + reg_layer_2_w30<=0; + reg_layer_2_w31<=0; + end + else begin + if(stage_0_ready)begin + reg_layer_2_w0<=layer_2_w0; + reg_layer_2_w1<=layer_2_w1; + reg_layer_2_w2<=layer_2_w2; + reg_layer_2_w3<=layer_2_w3; + reg_layer_2_w4<=layer_2_w4; + reg_layer_2_w5<=layer_2_w5; + reg_layer_2_w6<=layer_2_w6; + reg_layer_2_w7<=layer_2_w7; + reg_layer_2_w8<=layer_2_w8; + reg_layer_2_w9<=layer_2_w9; + reg_layer_2_w10<=layer_2_w10; + reg_layer_2_w11<=layer_2_w11; + reg_layer_2_w12<=layer_2_w12; + reg_layer_2_w13<=layer_2_w13; + reg_layer_2_w14<=layer_2_w14; + reg_layer_2_w15<=layer_2_w15; + reg_layer_2_w16<=layer_2_w16; + reg_layer_2_w17<=layer_2_w17; + reg_layer_2_w18<=layer_2_w18; + reg_layer_2_w19<=layer_2_w19; + reg_layer_2_w20<=layer_2_w20; + reg_layer_2_w21<=layer_2_w21; + reg_layer_2_w22<=layer_2_w22; + reg_layer_2_w23<=layer_2_w23; + reg_layer_2_w24<=layer_2_w24; + reg_layer_2_w25<=layer_2_w25; + reg_layer_2_w26<=layer_2_w26; + reg_layer_2_w27<=layer_2_w27; + reg_layer_2_w28<=layer_2_w28; + reg_layer_2_w29<=layer_2_w29; + reg_layer_2_w30<=layer_2_w30; + reg_layer_2_w31<=layer_2_w31; + end + stage_1_ready<=stage_0_ready; + end +end + +//layer 3 +wire layer_3_w0[1:0]; +wire layer_3_w1; +wire layer_3_w2[2:0]; +wire layer_3_w3[1:0]; +wire layer_3_w4[1:0]; +wire layer_3_w5[1:0]; +wire layer_3_w6[1:0]; +wire layer_3_w7[1:0]; +wire layer_3_w8[1:0]; +wire layer_3_w9[1:0]; +wire layer_3_w10[1:0]; +wire layer_3_w11[1:0]; +wire layer_3_w12[1:0]; +wire layer_3_w13[1:0]; +wire layer_3_w14[1:0]; +wire layer_3_w15[1:0]; +wire layer_3_w16[2:0]; +wire layer_3_w17[1:0]; +wire layer_3_w18[2:0]; +wire layer_3_w19[1:0]; +wire layer_3_w20[2:0]; +wire layer_3_w21[1:0]; +wire layer_3_w22[2:0]; +wire layer_3_w23[1:0]; +wire layer_3_w24; +wire layer_3_w25[2:0]; +wire layer_3_w26; +wire layer_3_w27[2:0]; +wire layer_3_w28; +wire layer_3_w29; +wire layer_3_w30[1:0]; +wire layer_3_w31; +assign layer_3_w0[0]=reg_layer_2_w0[0]; +assign layer_3_w0[1]=reg_layer_2_w0[1]; +assign layer_3_w1=reg_layer_2_w1; +assign layer_3_w2[0]=reg_layer_2_w2[0]; +assign layer_3_w2[1]=reg_layer_2_w2[1]; +assign layer_3_w2[2]=reg_layer_2_w2[2]; +assign layer_3_w3[0]=reg_layer_2_w3[0]; +assign layer_3_w3[1]=reg_layer_2_w3[1]; +assign layer_3_w4[0]=reg_layer_2_w4[0]; +assign layer_3_w4[1]=reg_layer_2_w4[1]; +assign layer_3_w5[0]=reg_layer_2_w5[0]; +assign layer_3_w5[1]=reg_layer_2_w5[1]; +assign layer_3_w6[0]=reg_layer_2_w6[0]; +assign layer_3_w6[1]=reg_layer_2_w6[1]; +assign layer_3_w7[0]=reg_layer_2_w7[0]; +assign layer_3_w7[1]=reg_layer_2_w7[1]; +assign layer_3_w8[0]=reg_layer_2_w8[0]; +assign layer_3_w8[1]=reg_layer_2_w8[1]; +assign layer_3_w9[0]=reg_layer_2_w9[0]; +assign layer_3_w9[1]=reg_layer_2_w9[1]; +assign layer_3_w10[0]=reg_layer_2_w10[0]; +assign layer_3_w10[1]=reg_layer_2_w10[1]; +full_adder layer_3_full_adder_0( +reg_layer_2_w11[0], +reg_layer_2_w11[1], +reg_layer_2_w11[2], +layer_3_w11[0], +layer_3_w12[0] +); +assign layer_3_w11[1]=reg_layer_2_w11[3]; +full_adder layer_3_full_adder_1( +reg_layer_2_w12[0], +reg_layer_2_w12[1], +reg_layer_2_w12[2], +layer_3_w12[1], +layer_3_w13[0] +); +full_adder layer_3_full_adder_2( +reg_layer_2_w13[0], +reg_layer_2_w13[1], +reg_layer_2_w13[2], +layer_3_w13[1], +layer_3_w14[0] +); +full_adder layer_3_full_adder_3( +reg_layer_2_w14[0], +reg_layer_2_w14[1], +reg_layer_2_w14[2], +layer_3_w14[1], +layer_3_w15[0] +); +full_adder layer_3_full_adder_4( +reg_layer_2_w15[0], +reg_layer_2_w15[1], +reg_layer_2_w15[2], +layer_3_w15[1], +layer_3_w16[0] +); +full_adder layer_3_full_adder_5( +reg_layer_2_w16[0], +reg_layer_2_w16[1], +reg_layer_2_w16[2], +layer_3_w16[1], +layer_3_w17[0] +); +assign layer_3_w16[2]=reg_layer_2_w16[3]; +full_adder layer_3_full_adder_6( +reg_layer_2_w17[0], +reg_layer_2_w17[1], +reg_layer_2_w17[2], +layer_3_w17[1], +layer_3_w18[0] +); +full_adder layer_3_full_adder_7( +reg_layer_2_w18[0], +reg_layer_2_w18[1], +reg_layer_2_w18[2], +layer_3_w18[1], +layer_3_w19[0] +); +assign layer_3_w18[2]=reg_layer_2_w18[3]; +full_adder layer_3_full_adder_8( +reg_layer_2_w19[0], +reg_layer_2_w19[1], +reg_layer_2_w19[2], +layer_3_w19[1], +layer_3_w20[0] +); +full_adder layer_3_full_adder_9( +reg_layer_2_w20[0], +reg_layer_2_w20[1], +reg_layer_2_w20[2], +layer_3_w20[1], +layer_3_w21[0] +); +assign layer_3_w20[2]=reg_layer_2_w20[3]; +full_adder layer_3_full_adder_10( +reg_layer_2_w21[0], +reg_layer_2_w21[1], +reg_layer_2_w21[2], +layer_3_w21[1], +layer_3_w22[0] +); +assign layer_3_w22[1]=reg_layer_2_w22[0]; +assign layer_3_w22[2]=reg_layer_2_w22[1]; +assign layer_3_w23[0]=reg_layer_2_w23[0]; +assign layer_3_w23[1]=reg_layer_2_w23[1]; +full_adder layer_3_full_adder_11( +reg_layer_2_w24[0], +reg_layer_2_w24[1], +reg_layer_2_w24[2], +layer_3_w24, +layer_3_w25[0] +); +assign layer_3_w25[1]=reg_layer_2_w25[0]; +assign layer_3_w25[2]=reg_layer_2_w25[1]; +full_adder layer_3_full_adder_12( +reg_layer_2_w26[0], +reg_layer_2_w26[1], +reg_layer_2_w26[2], +layer_3_w26, +layer_3_w27[0] +); +assign layer_3_w27[1]=reg_layer_2_w27[0]; +assign layer_3_w27[2]=reg_layer_2_w27[1]; +assign layer_3_w28=reg_layer_2_w28; +full_adder layer_3_full_adder_13( +reg_layer_2_w29[0], +reg_layer_2_w29[1], +reg_layer_2_w29[2], +layer_3_w29, +layer_3_w30[0] +); +assign layer_3_w30[1]=reg_layer_2_w30; +assign layer_3_w31=reg_layer_2_w31; + +//layer 4 +wire layer_4_w0[1:0]; +wire layer_4_w1; +wire layer_4_w2; +wire layer_4_w3[1:0]; +wire layer_4_w4[1:0]; +wire layer_4_w5[1:0]; +wire layer_4_w6[1:0]; +wire layer_4_w7[1:0]; +wire layer_4_w8[1:0]; +wire layer_4_w9[1:0]; +wire layer_4_w10[1:0]; +wire layer_4_w11[1:0]; +wire layer_4_w12[1:0]; +wire layer_4_w13[1:0]; +wire layer_4_w14[1:0]; +wire layer_4_w15[1:0]; +wire layer_4_w16[1:0]; +wire layer_4_w17[1:0]; +wire layer_4_w18[1:0]; +wire layer_4_w19[1:0]; +wire layer_4_w20[1:0]; +wire layer_4_w21[1:0]; +wire layer_4_w22[1:0]; +wire layer_4_w23[1:0]; +wire layer_4_w24[1:0]; +wire layer_4_w25; +wire layer_4_w26[1:0]; +wire layer_4_w27; +wire layer_4_w28[1:0]; +wire layer_4_w29; +wire layer_4_w30[1:0]; +wire layer_4_w31; +assign layer_4_w0[0]=layer_3_w0[0]; +assign layer_4_w0[1]=layer_3_w0[1]; +assign layer_4_w1=layer_3_w1; +full_adder layer_4_full_adder_0( +layer_3_w2[0], +layer_3_w2[1], +layer_3_w2[2], +layer_4_w2, +layer_4_w3[0] +); +half_adder layer_4_half_adder_0( +layer_3_w3[0], +layer_3_w3[1], +layer_4_w3[1], +layer_4_w4[0] +); +half_adder layer_4_half_adder_1( +layer_3_w4[0], +layer_3_w4[1], +layer_4_w4[1], +layer_4_w5[0] +); +half_adder layer_4_half_adder_2( +layer_3_w5[0], +layer_3_w5[1], +layer_4_w5[1], +layer_4_w6[0] +); +half_adder layer_4_half_adder_3( +layer_3_w6[0], +layer_3_w6[1], +layer_4_w6[1], +layer_4_w7[0] +); +half_adder layer_4_half_adder_4( +layer_3_w7[0], +layer_3_w7[1], +layer_4_w7[1], +layer_4_w8[0] +); +half_adder layer_4_half_adder_5( +layer_3_w8[0], +layer_3_w8[1], +layer_4_w8[1], +layer_4_w9[0] +); +half_adder layer_4_half_adder_6( +layer_3_w9[0], +layer_3_w9[1], +layer_4_w9[1], +layer_4_w10[0] +); +half_adder layer_4_half_adder_7( +layer_3_w10[0], +layer_3_w10[1], +layer_4_w10[1], +layer_4_w11[0] +); +half_adder layer_4_half_adder_8( +layer_3_w11[0], +layer_3_w11[1], +layer_4_w11[1], +layer_4_w12[0] +); +half_adder layer_4_half_adder_9( +layer_3_w12[0], +layer_3_w12[1], +layer_4_w12[1], +layer_4_w13[0] +); +half_adder layer_4_half_adder_10( +layer_3_w13[0], +layer_3_w13[1], +layer_4_w13[1], +layer_4_w14[0] +); +half_adder layer_4_half_adder_11( +layer_3_w14[0], +layer_3_w14[1], +layer_4_w14[1], +layer_4_w15[0] +); +half_adder layer_4_half_adder_12( +layer_3_w15[0], +layer_3_w15[1], +layer_4_w15[1], +layer_4_w16[0] +); +full_adder layer_4_full_adder_1( +layer_3_w16[0], +layer_3_w16[1], +layer_3_w16[2], +layer_4_w16[1], +layer_4_w17[0] +); +half_adder layer_4_half_adder_13( +layer_3_w17[0], +layer_3_w17[1], +layer_4_w17[1], +layer_4_w18[0] +); +full_adder layer_4_full_adder_2( +layer_3_w18[0], +layer_3_w18[1], +layer_3_w18[2], +layer_4_w18[1], +layer_4_w19[0] +); +half_adder layer_4_half_adder_14( +layer_3_w19[0], +layer_3_w19[1], +layer_4_w19[1], +layer_4_w20[0] +); +full_adder layer_4_full_adder_3( +layer_3_w20[0], +layer_3_w20[1], +layer_3_w20[2], +layer_4_w20[1], +layer_4_w21[0] +); +half_adder layer_4_half_adder_15( +layer_3_w21[0], +layer_3_w21[1], +layer_4_w21[1], +layer_4_w22[0] +); +full_adder layer_4_full_adder_4( +layer_3_w22[0], +layer_3_w22[1], +layer_3_w22[2], +layer_4_w22[1], +layer_4_w23[0] +); +half_adder layer_4_half_adder_16( +layer_3_w23[0], +layer_3_w23[1], +layer_4_w23[1], +layer_4_w24[0] +); +assign layer_4_w24[1]=layer_3_w24; +full_adder layer_4_full_adder_5( +layer_3_w25[0], +layer_3_w25[1], +layer_3_w25[2], +layer_4_w25, +layer_4_w26[0] +); +assign layer_4_w26[1]=layer_3_w26; +full_adder layer_4_full_adder_6( +layer_3_w27[0], +layer_3_w27[1], +layer_3_w27[2], +layer_4_w27, +layer_4_w28[0] +); +assign layer_4_w28[1]=layer_3_w28; +assign layer_4_w29=layer_3_w29; +assign layer_4_w30[0]=layer_3_w30[0]; +assign layer_4_w30[1]=layer_3_w30[1]; +assign layer_4_w31=layer_3_w31; + +//group reduction results into 2 numbers +wire [31:0]A,B; +assign A[0]=layer_4_w0[0]; +assign B[0]=layer_4_w0[1]; +assign A[1]=layer_4_w1; +assign B[1]=0; +assign A[2]=layer_4_w2; +assign B[2]=0; +assign A[3]=layer_4_w3[0]; +assign B[3]=layer_4_w3[1]; +assign A[4]=layer_4_w4[0]; +assign B[4]=layer_4_w4[1]; +assign A[5]=layer_4_w5[0]; +assign B[5]=layer_4_w5[1]; +assign A[6]=layer_4_w6[0]; +assign B[6]=layer_4_w6[1]; +assign A[7]=layer_4_w7[0]; +assign B[7]=layer_4_w7[1]; +assign A[8]=layer_4_w8[0]; +assign B[8]=layer_4_w8[1]; +assign A[9]=layer_4_w9[0]; +assign B[9]=layer_4_w9[1]; +assign A[10]=layer_4_w10[0]; +assign B[10]=layer_4_w10[1]; +assign A[11]=layer_4_w11[0]; +assign B[11]=layer_4_w11[1]; +assign A[12]=layer_4_w12[0]; +assign B[12]=layer_4_w12[1]; +assign A[13]=layer_4_w13[0]; +assign B[13]=layer_4_w13[1]; +assign A[14]=layer_4_w14[0]; +assign B[14]=layer_4_w14[1]; +assign A[15]=layer_4_w15[0]; +assign B[15]=layer_4_w15[1]; +assign A[16]=layer_4_w16[0]; +assign B[16]=layer_4_w16[1]; +assign A[17]=layer_4_w17[0]; +assign B[17]=layer_4_w17[1]; +assign A[18]=layer_4_w18[0]; +assign B[18]=layer_4_w18[1]; +assign A[19]=layer_4_w19[0]; +assign B[19]=layer_4_w19[1]; +assign A[20]=layer_4_w20[0]; +assign B[20]=layer_4_w20[1]; +assign A[21]=layer_4_w21[0]; +assign B[21]=layer_4_w21[1]; +assign A[22]=layer_4_w22[0]; +assign B[22]=layer_4_w22[1]; +assign A[23]=layer_4_w23[0]; +assign B[23]=layer_4_w23[1]; +assign A[24]=layer_4_w24[0]; +assign B[24]=layer_4_w24[1]; +assign A[25]=layer_4_w25; +assign B[25]=0; +assign A[26]=layer_4_w26[0]; +assign B[26]=layer_4_w26[1]; +assign A[27]=layer_4_w27; +assign B[27]=0; +assign A[28]=layer_4_w28[0]; +assign B[28]=layer_4_w28[1]; +assign A[29]=layer_4_w29; +assign B[29]=0; +assign A[30]=layer_4_w30[0]; +assign B[30]=layer_4_w30[1]; +assign A[31]=layer_4_w31; +assign B[31]=0; + +wire carry; +adder_32bit adder_32bit( +A, +B, +1'b0, +o_product, +carry +); + + +endmodule diff --git a/designs/encrypted_ip/pid_test/CLA_fixed.v b/designs/encrypted_ip/pid_test/CLA_fixed.v new file mode 100644 index 000000000..bd68e0204 --- /dev/null +++ b/designs/encrypted_ip/pid_test/CLA_fixed.v @@ -0,0 +1,259 @@ +/*Carry look-ahead adder +Author: Zhu Xu +Email: m99a1@yahoo.cn +*/ + +module operator_A( +input A, +input B, +output P, +output G +); + +assign P=A^B; +assign G=A&B; + +endmodule + +module operator_B( +input P,G,P1,G1, +output Po,Go +); + +assign Po=P&P1; +assign Go=G|(P&G1); + +endmodule + +module operator_C( +input P,G,G1, +output Go +); + +assign Go=G|(P&G1); + +endmodule + + +/* 32-bit prefix-2 Han-Carlson adder +stage 0: Number of Generation=32, NP=32, NOA=32, NOB=0, NOC=0. +stage 1: NG=16, NP=15, NOA=0, NOB=15, NOC=1. +stage 2: NG=16, NP=14, NOA=0, NOB=14, NOC=1. +stage 3: NG=16, NP=12, NOA=0, NOB=12, NOC=2. +stage 4: NG=16, NP=8, NOA=0, NOB=8, NOC=4. +stage 5: NG=16, NP=0, NOA=0, NOB=0, NOC=8. +stage 6; NG=32, NP=0, NOA=0, NOB=0, NOC=15. +*/ +module adder_32bit( +input [31:0]i_a,i_b, +input i_c, +output [31:0]o_s, +output o_c +); + +//stage 0 +wire [31:0]P0,G0; +operator_A operator_A_0(i_a[0],i_b[0],P0[0],G0[0]); +operator_A operator_A_1(i_a[1],i_b[1],P0[1],G0[1]); +operator_A operator_A_2(i_a[2],i_b[2],P0[2],G0[2]); +operator_A operator_A_3(i_a[3],i_b[3],P0[3],G0[3]); +operator_A operator_A_4(i_a[4],i_b[4],P0[4],G0[4]); +operator_A operator_A_5(i_a[5],i_b[5],P0[5],G0[5]); +operator_A operator_A_6(i_a[6],i_b[6],P0[6],G0[6]); +operator_A operator_A_7(i_a[7],i_b[7],P0[7],G0[7]); +operator_A operator_A_8(i_a[8],i_b[8],P0[8],G0[8]); +operator_A operator_A_9(i_a[9],i_b[9],P0[9],G0[9]); +operator_A operator_A_10(i_a[10],i_b[10],P0[10],G0[10]); +operator_A operator_A_11(i_a[11],i_b[11],P0[11],G0[11]); +operator_A operator_A_12(i_a[12],i_b[12],P0[12],G0[12]); +operator_A operator_A_13(i_a[13],i_b[13],P0[13],G0[13]); +operator_A operator_A_14(i_a[14],i_b[14],P0[14],G0[14]); +operator_A operator_A_15(i_a[15],i_b[15],P0[15],G0[15]); +operator_A operator_A_16(i_a[16],i_b[16],P0[16],G0[16]); +operator_A operator_A_17(i_a[17],i_b[17],P0[17],G0[17]); +operator_A operator_A_18(i_a[18],i_b[18],P0[18],G0[18]); +operator_A operator_A_19(i_a[19],i_b[19],P0[19],G0[19]); +operator_A operator_A_20(i_a[20],i_b[20],P0[20],G0[20]); +operator_A operator_A_21(i_a[21],i_b[21],P0[21],G0[21]); +operator_A operator_A_22(i_a[22],i_b[22],P0[22],G0[22]); +operator_A operator_A_23(i_a[23],i_b[23],P0[23],G0[23]); +operator_A operator_A_24(i_a[24],i_b[24],P0[24],G0[24]); +operator_A operator_A_25(i_a[25],i_b[25],P0[25],G0[25]); +operator_A operator_A_26(i_a[26],i_b[26],P0[26],G0[26]); +operator_A operator_A_27(i_a[27],i_b[27],P0[27],G0[27]); +operator_A operator_A_28(i_a[28],i_b[28],P0[28],G0[28]); +operator_A operator_A_29(i_a[29],i_b[29],P0[29],G0[29]); +operator_A operator_A_30(i_a[30],i_b[30],P0[30],G0[30]); +operator_A operator_A_31(i_a[31],i_b[31],P0[31],G0[31]); + +//stage 1 +wire [15:0]G1; +wire [15:1]P1; +operator_C operator_C_stage_1_0(P0[0],G0[0],i_c,G1[0]); +operator_B operator_B_stage_1_1(P0[2],G0[2],P0[1],G0[1],P1[1],G1[1]); +operator_B operator_B_stage_1_2(P0[4],G0[4],P0[3],G0[3],P1[2],G1[2]); +operator_B operator_B_stage_1_3(P0[6],G0[6],P0[5],G0[5],P1[3],G1[3]); +operator_B operator_B_stage_1_4(P0[8],G0[8],P0[7],G0[7],P1[4],G1[4]); +operator_B operator_B_stage_1_5(P0[10],G0[10],P0[9],G0[9],P1[5],G1[5]); +operator_B operator_B_stage_1_6(P0[12],G0[12],P0[11],G0[11],P1[6],G1[6]); +operator_B operator_B_stage_1_7(P0[14],G0[14],P0[13],G0[13],P1[7],G1[7]); +operator_B operator_B_stage_1_8(P0[16],G0[16],P0[15],G0[15],P1[8],G1[8]); +operator_B operator_B_stage_1_9(P0[18],G0[18],P0[17],G0[17],P1[9],G1[9]); +operator_B operator_B_stage_1_10(P0[20],G0[20],P0[19],G0[19],P1[10],G1[10]); +operator_B operator_B_stage_1_11(P0[22],G0[22],P0[21],G0[21],P1[11],G1[11]); +operator_B operator_B_stage_1_12(P0[24],G0[24],P0[23],G0[23],P1[12],G1[12]); +operator_B operator_B_stage_1_13(P0[26],G0[26],P0[25],G0[25],P1[13],G1[13]); +operator_B operator_B_stage_1_14(P0[28],G0[28],P0[27],G0[27],P1[14],G1[14]); +operator_B operator_B_stage_1_15(P0[30],G0[30],P0[29],G0[29],P1[15],G1[15]); + + + +//stage 2 +wire [15:0]G2; +wire [15:2]P2; +assign G2[0]=G1[0]; +operator_C operator_C_stage_2_1(P1[1],G1[1],G1[0],G2[1]); +operator_B operator_B_stage_2_2(P1[2], G1[2],P1[1],G1[1],P2[2],G2[2]); +operator_B operator_B_stage_2_3(P1[3], G1[3],P1[2],G1[2],P2[3],G2[3]); +operator_B operator_B_stage_2_4(P1[4], G1[4],P1[3],G1[3],P2[4],G2[4]); +operator_B operator_B_stage_2_5(P1[5], G1[5],P1[4],G1[4],P2[5],G2[5]); +operator_B operator_B_stage_2_6(P1[6], G1[6],P1[5],G1[5],P2[6],G2[6]); +operator_B operator_B_stage_2_7(P1[7], G1[7],P1[6],G1[6],P2[7],G2[7]); +operator_B operator_B_stage_2_8(P1[8], G1[8],P1[7],G1[7],P2[8],G2[8]); +operator_B operator_B_stage_2_9(P1[9], G1[9],P1[8],G1[8],P2[9],G2[9]); +operator_B operator_B_stage_2_10(P1[10], G1[10],P1[9],G1[9],P2[10],G2[10]); +operator_B operator_B_stage_2_11(P1[11], G1[11],P1[10],G1[10],P2[11],G2[11]); +operator_B operator_B_stage_2_12(P1[12], G1[12],P1[11],G1[11],P2[12],G2[12]); +operator_B operator_B_stage_2_13(P1[13], G1[13],P1[12],G1[12],P2[13],G2[13]); +operator_B operator_B_stage_2_14(P1[14], G1[14],P1[13],G1[13],P2[14],G2[14]); +operator_B operator_B_stage_2_15(P1[15], G1[15],P1[14],G1[14],P2[15],G2[15]); + +//stage 3 +wire [15:0]G3; +wire [15:4]P3; +assign G3[0]=G2[0]; +assign G3[1]=G2[1]; +operator_C operator_C_stage_3_2(P2[2],G2[2],G2[0],G3[2]); +operator_C operator_C_stage_3_3(P2[3],G2[3],G2[1],G3[3]); +operator_B operator_B_stage_3_4(P2[4], G2[4],P2[2],G2[2],P3[4],G3[4]); +operator_B operator_B_stage_3_5(P2[5], G2[5],P2[3],G2[3],P3[5],G3[5]); +operator_B operator_B_stage_3_6(P2[6], G2[6],P2[4],G2[4],P3[6],G3[6]); +operator_B operator_B_stage_3_7(P2[7], G2[7],P2[5],G2[5],P3[7],G3[7]); +operator_B operator_B_stage_3_8(P2[8], G2[8],P2[6],G2[6],P3[8],G3[8]); +operator_B operator_B_stage_3_9(P2[9], G2[9],P2[7],G2[7],P3[9],G3[9]); +operator_B operator_B_stage_3_10(P2[10], G2[10],P2[8],G2[8],P3[10],G3[10]); +operator_B operator_B_stage_3_11(P2[11], G2[11],P2[9],G2[9],P3[11],G3[11]); +operator_B operator_B_stage_3_12(P2[12], G2[12],P2[10],G2[10],P3[12],G3[12]); +operator_B operator_B_stage_3_13(P2[13], G2[13],P2[11],G2[11],P3[13],G3[13]); +operator_B operator_B_stage_3_14(P2[14], G2[14],P2[12],G2[12],P3[14],G3[14]); +operator_B operator_B_stage_3_15(P2[15], G2[15],P2[13],G2[13],P3[15],G3[15]); + +//stage 4 +wire [15:0]G4; +wire [15:8]P4; +assign G4[0]=G3[0]; +assign G4[1]=G3[1]; +assign G4[2]=G3[2]; +assign G4[3]=G3[3]; +operator_C operator_C_stage_4_4(P3[4],G3[4],G3[0],G4[4]); +operator_C operator_C_stage_4_5(P3[5],G3[5],G3[1],G4[5]); +operator_C operator_C_stage_4_6(P3[6],G3[6],G3[2],G4[6]); +operator_C operator_C_stage_4_7(P3[7],G3[7],G3[3],G4[7]); +operator_B operator_B_stage_4_8(P3[8], G3[8],P3[4],G3[4],P4[8],G4[8]); +operator_B operator_B_stage_4_9(P3[9], G3[9],P3[5],G3[5],P4[9],G4[9]); +operator_B operator_B_stage_4_10(P3[10], G3[10],P3[6],G3[6],P4[10],G4[10]); +operator_B operator_B_stage_4_11(P3[11], G3[11],P3[7],G3[7],P4[11],G4[11]); +operator_B operator_B_stage_4_12(P3[12], G3[12],P3[8],G3[8],P4[12],G4[12]); +operator_B operator_B_stage_4_13(P3[13], G3[13],P3[9],G3[9],P4[13],G4[13]); +operator_B operator_B_stage_4_14(P3[14], G3[14],P3[10],G3[10],P4[14],G4[14]); +operator_B operator_B_stage_4_15(P3[15], G3[15],P3[11],G3[11],P4[15],G4[15]); + +//stage 5 +wire [15:0]G5; +assign G5[0]=G4[0]; +assign G5[1]=G4[1]; +assign G5[2]=G4[2]; +assign G5[3]=G4[3]; +assign G5[4]=G4[4]; +assign G5[5]=G4[5]; +assign G5[6]=G4[6]; +assign G5[7]=G4[7]; +operator_C operator_C_stage_5_8(P4[8],G4[8],G4[0],G5[8]); +operator_C operator_C_stage_5_9(P4[9],G4[9],G4[1],G5[9]); +operator_C operator_C_stage_5_10(P4[10],G4[10],G4[2],G5[10]); +operator_C operator_C_stage_5_11(P4[11],G4[11],G4[3],G5[11]); +operator_C operator_C_stage_5_12(P4[12],G4[12],G4[4],G5[12]); +operator_C operator_C_stage_5_13(P4[13],G4[13],G4[5],G5[13]); +operator_C operator_C_stage_5_14(P4[14],G4[14],G4[6],G5[14]); +operator_C operator_C_stage_5_15(P4[15],G4[15],G4[7],G5[15]); + +//stage 6 +wire [31:0]G6; +assign G6[0]=G5[0]; +assign G6[2]=G5[1]; +assign G6[4]=G5[2]; +assign G6[6]=G5[3]; +assign G6[8]=G5[4]; +assign G6[10]=G5[5]; +assign G6[12]=G5[6]; +assign G6[14]=G5[7]; +assign G6[16]=G5[8]; +assign G6[18]=G5[9]; +assign G6[20]=G5[10]; +assign G6[22]=G5[11]; +assign G6[24]=G5[12]; +assign G6[26]=G5[13]; +assign G6[28]=G5[14]; +assign G6[30]=G5[15]; +operator_C operator_C_stage_6_0(P0[1],G0[1],G5[0],G6[1]); +operator_C operator_C_stage_6_1(P0[3],G0[3],G5[1],G6[3]); +operator_C operator_C_stage_6_2(P0[5],G0[5],G5[2],G6[5]); +operator_C operator_C_stage_6_3(P0[7],G0[7],G5[3],G6[7]); +operator_C operator_C_stage_6_4(P0[9],G0[9],G5[4],G6[9]); +operator_C operator_C_stage_6_5(P0[11],G0[11],G5[5],G6[11]); +operator_C operator_C_stage_6_6(P0[13],G0[13],G5[6],G6[13]); +operator_C operator_C_stage_6_7(P0[15],G0[15],G5[7],G6[15]); +operator_C operator_C_stage_6_8(P0[17],G0[17],G5[8],G6[17]); +operator_C operator_C_stage_6_9(P0[19],G0[19],G5[9],G6[19]); +operator_C operator_C_stage_6_10(P0[21],G0[21],G5[10],G6[21]); +operator_C operator_C_stage_6_11(P0[23],G0[23],G5[11],G6[23]); +operator_C operator_C_stage_6_12(P0[25],G0[25],G5[12],G6[25]); +operator_C operator_C_stage_6_13(P0[27],G0[27],G5[13],G6[27]); +operator_C operator_C_stage_6_14(P0[29],G0[29],G5[14],G6[29]); +operator_C operator_C_stage_6_15(P0[31],G0[31],G5[15],G6[31]); + +assign o_s[0]=P0[0]^i_c; +assign o_s[1]=P0[1]^G6[0]; +assign o_s[2]=P0[2]^G6[1]; +assign o_s[3]=P0[3]^G6[2]; +assign o_s[4]=P0[4]^G6[3]; +assign o_s[5]=P0[5]^G6[4]; +assign o_s[6]=P0[6]^G6[5]; +assign o_s[7]=P0[7]^G6[6]; +assign o_s[8]=P0[8]^G6[7]; +assign o_s[9]=P0[9]^G6[8]; +assign o_s[10]=P0[10]^G6[9]; +assign o_s[11]=P0[11]^G6[10]; +assign o_s[12]=P0[12]^G6[11]; +assign o_s[13]=P0[13]^G6[12]; +assign o_s[14]=P0[14]^G6[13]; +assign o_s[15]=P0[15]^G6[14]; +assign o_s[16]=P0[16]^G6[15]; +assign o_s[17]=P0[17]^G6[16]; +assign o_s[18]=P0[18]^G6[17]; +assign o_s[19]=P0[19]^G6[18]; +assign o_s[20]=P0[20]^G6[19]; +assign o_s[21]=P0[21]^G6[20]; +assign o_s[22]=P0[22]^G6[21]; +assign o_s[23]=P0[23]^G6[22]; +assign o_s[24]=P0[24]^G6[23]; +assign o_s[25]=P0[25]^G6[24]; +assign o_s[26]=P0[26]^G6[25]; +assign o_s[27]=P0[27]^G6[26]; +assign o_s[28]=P0[28]^G6[27]; +assign o_s[29]=P0[29]^G6[28]; +assign o_s[30]=P0[30]^G6[29]; +assign o_s[31]=P0[31]^G6[30]; +assign o_c=G6[31]; + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pid_test/PID.v b/designs/encrypted_ip/pid_test/PID.v new file mode 100644 index 000000000..9133b1c64 --- /dev/null +++ b/designs/encrypted_ip/pid_test/PID.v @@ -0,0 +1,434 @@ +/* PID controller + +sigma=Ki*e(n)+sigma +u(n)=(Kp+Kd)*e(n)+sigma+Kd*(-e(n-1)) + +Data width of Wishbone slave port can be can be toggled between 64-bit, 32-bit and 16-bit. +Address width of Wishbone slave port can be can be modified by changing parameter adr_wb_nb. + +Wishbone compliant +Work as Wishbone slave, support Classic standard SINGLE/BLOCK READ/WRITE Cycle + +registers or wires +[15:0]kp,ki,kd,sp,pv; can be both read and written +[15:0]kpd; read only +[15:0]err[0:1]; read only +[15:0]mr,md; not accessable +[31:0]p,b; not accessable +[31:0]un,sigma; read only +RS write 0 to RS will reset err[0], OF, un and sigma + + + +[4:0]of; overflow register, read only through Wishbone interface, address: 0x40 +of[0]==1 : kpd overflow +of[1]==1 : err[0] overflow +of[2]==1 : err[1] overflow +of[3]==1 : un overflow +of[4]==1 : sigma overflow +[0:15]rl; read lock, when asserted corelated reagister can not be read through Wishbone interface +[0:7]wl; write lock, when asserted corelated reagister can not be written through Wishbone interface + + + +*/ + +`include "PID_defines.v" + +module pid #( +`ifdef wb_16bit +parameter wb_nb=16, +`endif +`ifdef wb_32bit +parameter wb_nb=32, +`endif +`ifdef wb_64bit +parameter wb_nb=64, +`endif + adr_wb_nb=16, + kp_adr = 0, + ki_adr = 1, + kd_adr = 2, + sp_adr = 3, + pv_adr = 4, + kpd_adr = 5, + err_0_adr = 6, + err_1_adr = 7, + un_adr = 8, + sigma_adr = 9, + of_adr = 10, + RS_adr = 11 +)( +input i_clk, +input i_rst, //reset when high +//Wishbone Slave port +input i_wb_cyc, +input i_wb_stb, +input i_wb_we, +input [adr_wb_nb-1:0]i_wb_adr, +input [wb_nb-1:0]i_wb_data, +output o_wb_ack, +output [wb_nb-1:0]o_wb_data, + +//u(n) output +output [31:0]o_un, +output o_valid +); + + + +reg [15:0]kp,ki,kd,sp,pv; +reg wla,wlb; // write locks +wire wlRS; +assign wlRS=wla|wlb; +wire [0:7]wl={{3{wla}},{2{wlb}},3'h0}; + +reg wack; //write acknowledged + +wire [2:0]adr; // address for write +`ifdef wb_16bit +assign adr=i_wb_adr[3:1]; +`endif +`ifdef wb_32bit +assign adr=i_wb_adr[4:2]; +`endif +`ifdef wb_64bit +assign adr=i_wb_adr[5:3]; +`endif + +wire [3:0]adr_1; // address for read +`ifdef wb_32bit +assign adr_1=i_wb_adr[5:2]; +`endif +`ifdef wb_16bit +assign adr_1=i_wb_adr[4:1]; +`endif +`ifdef wb_64bit +assign adr_1=i_wb_adr[6:3]; +`endif + + +wire we; // write enable +assign we=i_wb_cyc&i_wb_we&i_wb_stb; +wire re; //read enable +assign re=i_wb_cyc&(~i_wb_we)&i_wb_stb; + +reg state_0; //state machine No.1's state register + +wire adr_check_1; // A '1' means address is within the range of adr_1 +`ifdef wb_32bit +assign adr_check_1=i_wb_adr[adr_wb_nb-1:6]==0; +`endif +`ifdef wb_16bit +assign adr_check_1=i_wb_adr[adr_wb_nb-1:5]==0; +`endif +`ifdef wb_64bit +assign adr_check_1=i_wb_adr[adr_wb_nb-1:7]==0; +`endif + +wire adr_check; // A '1' means address is within the range of adr +`ifdef wb_16bit +assign adr_check=i_wb_adr[4]==0&&adr_check_1; +`endif +`ifdef wb_32bit +assign adr_check=i_wb_adr[5]==0&&adr_check_1; +`endif +`ifdef wb_64bit +assign adr_check=i_wb_adr[6]==0&&adr_check_1; +`endif + + //state machine No.1 +reg RS; +always@(posedge i_clk or posedge i_rst) + if(i_rst)begin + state_0<=0; + wack<=0; + kp<=0; + ki<=0; + kd<=0; + sp<=0; + pv<=0; + RS<=0; + end + else begin + if(wack&&(!i_wb_stb)) wack<=0; + if(RS)RS<=0; + case(state_0) + 0: begin + if(we&&(!wack)) state_0<=1; + end + 1: begin + if(adr_check)begin + if(!wl[adr])begin + wack<=1; + state_0<=0; + case(adr) + 0: begin + kp<=i_wb_data[15:0]; + end + 1: begin + ki<=i_wb_data[15:0]; + end + 2: begin + kd<=i_wb_data[15:0]; + end + 3: begin + sp<=i_wb_data[15:0]; + end + 4: begin + pv<=i_wb_data[15:0]; + end + endcase + + end + end + else if((adr_1==RS_adr)&&(!wlRS)&&(i_wb_data==0))begin + wack<=1; + state_0<=0; + RS<=1; + end + else begin + wack<=1; + state_0<=0; + end + end + endcase + end + + + //state machine No.2 +reg [9:0]state_1; + +wire update_kpd; +assign update_kpd=wack&&(~adr[2])&&(~adr[0])&&adr_check; //adr==0||adr==2 + +wire update_esu; //update e(n), sigma and u(n) +assign update_esu=wack&&(adr==4)&&adr_check; + +reg rla; // read locks +reg rlb; + + +reg [4:0]of; +reg [15:0]kpd; +reg [15:0]err[0:1]; + +wire [15:0]mr,md; + +reg [31:0]p; +reg [31:0]a,sigma,un; + +reg cout; +wire cin; +wire [31:0]sum; +wire [31:0]product; + +reg start; //start signal for multiplier + +reg [1:0]mr_index; +reg [1:0]md_index; +assign mr= mr_index==1?kpd: + mr_index==2?kd:ki; +assign md= md_index==2?err[1]: + md_index==1?err[0]:sum[15:0]; + + +wire of_addition[0:1]; +assign of_addition[0]=(p[15]&&a[15]&&(!sum[15]))||((!p[15])&&(!a[15])&&sum[15]); +assign of_addition[1]=(p[31]&&a[31]&&(!sum[31]))||((!p[31])&&(!a[31])&&sum[31]); + +always@(posedge i_clk or posedge i_rst) + if(i_rst)begin + state_1<=12'b000000000001; + wla<=0; + wlb<=0; + rla<=0; + rlb<=0; + of<=0; + kpd<=0; + err[0]<=0; + err[1]<=0; + p<=0; + a<=0; + sigma<=0; + un<=0; + start<=0; + mr_index<=0; + md_index<=0; + cout<=0; + end + else begin + case(state_1) + 10'b0000000001: begin + if(update_kpd)begin + state_1<=10'b0000000010; + wla<=1; + rla<=1; + end + else if(update_esu)begin + state_1<=10'b0000001000; + wla<=1; + wlb<=1; + rlb<=1; + end + else if(RS)begin //start a new sequance of U(n) + un<=0; + sigma<=0; + of<=0; + err[0]<=0; + end + end + 10'b0000000010: begin + p<={{16{kp[15]}},kp}; + a<={{16{kd[15]}},kd}; + state_1<=10'b0000000100; + end + 10'b0000000100: begin + kpd<=sum[15:0]; + wla<=0; + rla<=0; + of[0]<=of_addition[0]; + state_1<=10'b0000000001; + end + 10'b0000001000: begin + p<={{16{sp[15]}},sp}; + a<={{16{~pv[15]}},~pv}; + cout<=1; + start<=1; // start calculate err0 * ki + state_1<=10'b0000010000; + end + 10'b0000010000: begin + err[0]<=sum[15:0]; + of[1]<=of_addition[0]; + of[2]<=of[1]; + p<={{16{~err[0][15]}},~err[0]}; + a<={31'b0,1'b1}; + cout<=0; + mr_index<=1; // start calculate err0 * kpd + md_index<=1; + state_1<=10'b0000100000; + end + 10'b0000100000: begin + err[1]<=sum[15:0]; + mr_index<=2; // start calculate err1 * kd + md_index<=2; + state_1<=10'b0001000000; + end + 10'b0001000000: begin + mr_index<=0; + md_index<=0; + start<=0; + p<=product; // start calculate err0*ki + sigma_last + a<=sigma; + state_1<=10'b0010000000; + end + 10'b0010000000: begin + a<=sum; // start calculate err0*kpd + sigma_recent + sigma<=sum; + of[3]<=of[4]|of_addition[1]; + of[4]<=of[4]|of_addition[1]; + p<=product; + state_1<=10'b0100000000; + end + 10'b0100000000: begin + a<=sum; // start calculate err0*kpd + sigma_recent+err1*kd + of[3]<=of[3]|of_addition[1]; + p<=product; + state_1<=10'b1000000000; + end + 10'b1000000000: begin + un<=sum; + of[3]<=of[3]|of_addition[1]; + state_1<=10'b0000000001; + wla<=0; + wlb<=0; + rlb<=0; + end + endcase + end + + +wire ready; +multiplier_16x16bit_pipelined multiplier_16x16bit_pipelined( +i_clk, +~i_rst, +start, +md, +mr, +product, +ready +); + +adder_32bit adder_32bit_0( +a, +p, +cout, +sum, +cin +); + + +wire [wb_nb-1:0]rdata[0:15]; //wishbone read data array +`ifdef wb_16bit +assign rdata[0]=kp; +assign rdata[1]=ki; +assign rdata[2]=kd; +assign rdata[3]=sp; +assign rdata[4]=pv; +assign rdata[5]=kpd; +assign rdata[6]=err[0]; +assign rdata[7]=err[1]; +assign rdata[8]=un[15:0]; +assign rdata[9]=sigma[15:0]; +assign rdata[10]={11'b0,of}; +`endif + +`ifdef wb_32bit +assign rdata[0]={{16{kp[15]}},kp}; +assign rdata[1]={{16{ki[15]}},ki}; +assign rdata[2]={{16{kd[15]}},kd}; +assign rdata[3]={{16{sp[15]}},sp}; +assign rdata[4]={{16{pv[15]}},pv}; +assign rdata[5]={{16{kpd[15]}},kpd}; +assign rdata[6]={{16{err[0][15]}},err[0]}; +assign rdata[7]={{16{err[1][15]}},err[1]}; +assign rdata[8]=un; +assign rdata[9]=sigma; +assign rdata[10]={27'b0,of}; +`endif + +`ifdef wb_64bit +assign rdata[0]={{48{kp[15]}},kp}; +assign rdata[1]={{48{ki[15]}},ki}; +assign rdata[2]={{48{kd[15]}},kd}; +assign rdata[3]={{48{sp[15]}},sp}; +assign rdata[4]={{48{pv[15]}},pv}; +assign rdata[5]={{48{kpd[15]}},kpd}; +assign rdata[6]={{48{err[0][15]}},err[0]}; +assign rdata[7]={{48{err[1][15]}},err[1]}; +assign rdata[8]={{32{un[31]}},un}; +assign rdata[9]={{32{sigma[31]}},sigma}; +assign rdata[10]={59'b0,of}; +`endif + +assign rdata[11]=0; +assign rdata[12]=0; +assign rdata[13]=0; +assign rdata[14]=0; +assign rdata[15]=0; + + +wire [0:15]rl; +assign rl={5'b0,rla,{4{rlb}},rla|rlb,5'b0}; + +wire rack; // wishbone read acknowledged +assign rack=(re&adr_check_1&(~rl[adr_1]))|(re&(~adr_check_1)); + +assign o_wb_ack=(wack|rack)&i_wb_stb; + +assign o_wb_data=adr_check_1?rdata[adr_1]:0; +assign o_un=un; +assign o_valid=~rlb; + + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pid_test/PID_defines.v b/designs/encrypted_ip/pid_test/PID_defines.v new file mode 100644 index 000000000..a43f6b38d --- /dev/null +++ b/designs/encrypted_ip/pid_test/PID_defines.v @@ -0,0 +1,8 @@ +//`define wb_16bit +`define wb_32bit +//`define wb_64bit + + +//`define PID_test + +//`define PID_direct_test \ No newline at end of file diff --git a/designs/encrypted_ip/pid_test/booth.v b/designs/encrypted_ip/pid_test/booth.v new file mode 100644 index 000000000..f33b3d80e --- /dev/null +++ b/designs/encrypted_ip/pid_test/booth.v @@ -0,0 +1,37 @@ +/*Booth Encoder +Author: Zhu Xu +Email: m99a1@yahoo.cn +*/ +module booth_radix4( +input [2:0]codes, +output zero, +output double, +output negation +); + +wire A; +assign A=codes[2]; +wire B; +assign B=codes[1]; +wire C; +assign C=codes[0]; +wire nB,nC,nA; +assign nB=~B; +assign nC=~C; +assign nA=~A; + +wire BC; +assign BC=B&C; +wire nBnC; +assign nBnC=nB&nC; +wire nBanC; +assign nBanC=nB|nC; + +assign double=(nBnC&A)|(BC&nA); +assign negation=A&nBanC; +assign zero=(A&BC)|(nA&nBnC); + + + + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pid_test/design.yaml b/designs/encrypted_ip/pid_test/design.yaml new file mode 100644 index 000000000..dd64f661d --- /dev/null +++ b/designs/encrypted_ip/pid_test/design.yaml @@ -0,0 +1,3 @@ +top: top + +encrypted_ip: ["pid", "divider_dshift"] \ No newline at end of file diff --git a/designs/encrypted_ip/pid_test/divider_dshift.v b/designs/encrypted_ip/pid_test/divider_dshift.v new file mode 100644 index 000000000..93898825a --- /dev/null +++ b/designs/encrypted_ip/pid_test/divider_dshift.v @@ -0,0 +1,273 @@ +module divider_dshift( +input i_clk, +input i_rst, +input [31:0]i_dividend, +input [31:0]i_divisor, +input i_start, +output o_ready, +output reg [31:0]o_quotient, +output reg [31:0]o_remainder +); + +parameter + state_1=1, + state_2=2, + state_3=4, + state_4=8, + state_5=16, + state_6=32; + + +reg [31:0]PR; //partial remainder +reg signed[31:0]PR_1; +reg [31:0]DR; //divisor +reg [5:0]ct,ct_1; // ct: index for quotient bit under calculation ct_1: shift value for last PR +reg ct_1_en,ct_1_en_1; // enable calculating of ct_1 +reg DD_sign; //sign of dividend +reg [5:0]state; +reg ready; +assign o_ready=ready?i_start:0; +reg [30:0]nq; //negative quotient +reg [30:0]q; //positive quotient +wire [30:0]nqp1; // nq+1 +wire [30:0]qp1; // q+1 +assign nqp1=nq+1; +assign qp1=q+1; + +wire [31:0]nDR; +assign nDR=~DR; +wire nsub; // not sub '1' means PR=PR+DR; + // '0' means PR=PR-DR; +assign nsub=PR[31]^DR[31]; + + +/// over subtract detection during final results adjustment +wire over_sub; +//assign over_sub=(state==state_4)||(state==state_3)?DD_sign^PR[62]&(PR[62:31]!=0):0; +assign over_sub=(DD_sign^PR[31])&(PR[31:0]!=0); +//reg over_sub; +wire addback_nDR; +wire addback_DR; +assign addback_nDR=over_sub&(~nsub); +assign addback_DR=over_sub⊄ +/// +/// results adjustment +wire [30:0]final_nq,final_q; +assign final_nq=addback_DR?nqp1:nq; +assign final_q=addback_nDR?qp1:q; +wire [31:0]remainder_addback; +assign remainder_addback= addback_DR?i_divisor: + addback_nDR?~i_divisor:0; +/// + +/// main subtractor +wire [31:0]a,b; +wire [31:0]sum; +wire carry_in; +wire carry_out; + +reg [31:0]reg_a,reg_b; +reg reg_carry; +reg [1:0]state_reg; + +///////////// Dynamic Shift ///////////// +reg [4:0]shifted,shifted_1; +reg [31:0]sdata; +wire [31:0]sdata_o; +wire [4:0]shifted_o; +shifter shifter_0( +sdata, +sdata_o, +shifted_o +); + +/* +assign a= + state==state_4?{1'b1,~final_nq}: + state==state_5?remainder_addback: + nsub?DR:nDR; +*/ +assign a= ct_1_en?{27'd0,shifted_1}: + state==state_4?{1'b1,~final_nq}: + state==state_5?remainder_addback: + nsub?DR:nDR; +assign b= ct_1_en?{26'd0,ct_1}: + state==state_4?{1'b0,final_q}: + state==state_5?PR_1:PR; + +assign carry_in= ct_1_en?0: + state==state_4?1: + state==state_5? addback_nDR?1:0: + nsub?0:1; + +adder_32bit adder_0( +reg_a, +reg_b, +reg_carry, +sum, +carry_out +); + + + + +// ct calculation +//reg UDR; // update Divisor +wire [5:0]sum_ct; +wire [25:0]sum_ct_h; +wire carry_ct; +adder_32bit adder_1( +{26'd0,ct}, +state[5]?{27'd0,shifted}:~{27'd0,shifted}, +state[5]?1'b0:1'b1, +{sum_ct_h,sum_ct}, +carry_ct +); + + + + + + +/////////////////////////////////////////// + +always@(posedge i_clk or negedge i_rst) + if(!i_rst)begin + sdata<=0; + shifted<=0; + shifted_1<=0; + PR<=0; + PR_1<=0; + DR<=0; + //UDR<=0; + ready<=0; + ct<=0; + ct_1<=0; + ct_1_en<=0; + ct_1_en_1<=0; + state<=state_1; + DD_sign<=0; + o_quotient<=0; + o_remainder<=0; + nq<=0; + q<=0; + //over_sub<=0; + reg_a<=0; + reg_b<=0; + reg_carry<=0; + state_reg<=0; + end + else begin + if(ready&&(!i_start))ready<=0; + case(state_reg) + 0: + case(state) + state_1:if((!ready)&&i_start)begin + sdata<=i_divisor; + state<=state_6; + q<=0; + nq<=0; + shifted<=0; + //UDR<=1; + end + state_2:begin + sdata<=i_dividend; + PR_1<=i_dividend; + DD_sign<=i_dividend[31]; + state<=state_3; + state_reg<=1; + end + state_3:begin + if(ct[5])begin + state<=state_4; + ct<=0; + state_reg<=2; + end + else begin + ct_1_en<=1; + shifted_1<=shifted; + nq[ct]<=nsub; + q[ct]<=~nsub; + sdata<=sum; + state_reg<=1; + end + end + state_4:begin + state<=state_5; + o_quotient<=sum; + PR_1<=PR_1>>>ct_1; + state_reg<=2; + end + state_5:begin + o_remainder<=sum; + ct_1<=0; + state<=state_1; + ready<=1; + end + + state_6:begin + sdata<=sdata_o; + shifted<=shifted_o; + ct<=sum_ct; + if(sdata[31]!=sdata[30])begin + state<=state_2; + DR<=sdata; + end + end +/* + state_6:begin + //if(!over_sub)o_remainder<=sum>>>ct_1; + o_remainder<=sum; + ct_1<=0; + state<=state_1; + ready<=1; + end + +*/ + endcase + 1:begin + PR<=sdata_o; + PR_1<=sdata; +/* + if(UDR)begin + UDR<=0; + ct<=shifted; + + if(shifted==0)begin + ct<=0; + end + else begin + ct<=shifted-1; + DR<={DR[31],DR[31:1]}; + end + + end +*/ + shifted<=shifted_o; + state_reg<=2; + reg_a<=a; //calculate ct_1 + reg_b<=b; + reg_carry<=carry_in; + ct_1_en<=0; + ct_1_en_1<=ct_1_en; + end + 2:begin + if(state==state_3)begin + ct<=sum_ct; + end + state_reg<=0; + if(ct_1_en_1)begin + ct_1<=sum[5:0]; + end + ct_1_en_1<=0; + reg_a<=a; // calculate PR + reg_b<=b; + reg_carry<=carry_in; + end + endcase + end + + + + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pid_test/shifter.v b/designs/encrypted_ip/pid_test/shifter.v new file mode 100644 index 000000000..42c60b389 --- /dev/null +++ b/designs/encrypted_ip/pid_test/shifter.v @@ -0,0 +1,319 @@ +module shift_1b( +input i_shift, +input [31:0]i_data, +output [31:0]o_data +); +assign o_data=i_shift?{i_data[30:0],1'b0}:i_data; + +endmodule + +module shift_3b( +input [2:0]i_shift, +input [31:0]i_data, +output [31:0]o_data +); +wire [31:0]data1; +assign data1=i_shift[1]?{i_data[29:0],2'b0}:i_data; +wire shift1; +assign shift1=(i_shift[0]&i_shift[1])|(i_shift[2]^i_shift[1]); +shift_1b shift_1b_0( +shift1, +data1, +o_data +); +endmodule + +module shift_7b( +input [6:0]i_shift, +input [31:0]i_data, +output [31:0]o_data +); +wire [31:0]data1; +assign data1=i_shift[3]?{i_data[27:0],4'b0}:i_data; +wire [2:0]shift1; +assign shift1=(i_shift[2:0]&{3{i_shift[3]}})|(i_shift[6:4]^{3{i_shift[3]}}); + +shift_3b shift_3b_0( +shift1, +data1, +o_data +); + +endmodule + +module shift_15b( +input [14:0]i_shift, +input [31:0]i_data, +output [31:0]o_data +); +wire [31:0]data1; +assign data1=i_shift[7]?{i_data[23:0],8'b0}:i_data; +wire [6:0]shift1; +assign shift1=(i_shift[6:0]&{7{i_shift[7]}})|(i_shift[14:8]^{7{i_shift[7]}}); + +shift_7b shift_7b_0( +shift1, +data1, +o_data +); + +endmodule + + + + + + + + + + + +module shifter( +input [31:0]i_data, +output [31:0]o_data, +output [4:0]o_shifted +); + +wire [31:0]node_0; +assign node_0=i_data[31]?i_data:~i_data; + +// odd nodes tree +///////////////////////// layer 1 //////////////////////////// +wire [15:0]onode_1; +assign onode_1[0]=node_0[0]&node_0[1]; +assign onode_1[1]=node_0[2]&node_0[3]; +assign onode_1[2]=node_0[4]&node_0[5]; +assign onode_1[3]=node_0[6]&node_0[7]; +assign onode_1[4]=node_0[8]&node_0[9]; +assign onode_1[5]=node_0[10]&node_0[11]; +assign onode_1[6]=node_0[12]&node_0[13]; +assign onode_1[7]=node_0[14]&node_0[15]; +assign onode_1[8]=node_0[16]&node_0[17]; +assign onode_1[9]=node_0[18]&node_0[19]; +assign onode_1[10]=node_0[20]&node_0[21]; +assign onode_1[11]=node_0[22]&node_0[23]; +assign onode_1[12]=node_0[24]&node_0[25]; +assign onode_1[13]=node_0[26]&node_0[27]; +assign onode_1[14]=node_0[28]&node_0[29]; +assign onode_1[15]=node_0[30]&node_0[31]; +///////////////////////// layer 2 //////////////////////////// +wire [15:0]onode_2; +assign onode_2[0]=onode_1[0]&onode_1[1]; +assign onode_2[1]=onode_1[1]&onode_1[2]; +assign onode_2[2]=onode_1[2]&onode_1[3]; +assign onode_2[3]=onode_1[3]&onode_1[4]; +assign onode_2[4]=onode_1[4]&onode_1[5]; +assign onode_2[5]=onode_1[5]&onode_1[6]; +assign onode_2[6]=onode_1[6]&onode_1[7]; +assign onode_2[7]=onode_1[7]&onode_1[8]; +assign onode_2[8]=onode_1[8]&onode_1[9]; +assign onode_2[9]=onode_1[9]&onode_1[10]; +assign onode_2[10]=onode_1[10]&onode_1[11]; +assign onode_2[11]=onode_1[11]&onode_1[12]; +assign onode_2[12]=onode_1[12]&onode_1[13]; +assign onode_2[13]=onode_1[13]&onode_1[14]; +assign onode_2[14]=onode_1[14]&onode_1[15]; +assign onode_2[15]=onode_1[15]; +///////////////////////// layer 3 //////////////////////////// +wire [15:0]onode_3; +assign onode_3[0]=onode_2[0]&onode_2[2]; +assign onode_3[1]=onode_2[1]&onode_2[3]; +assign onode_3[2]=onode_2[2]&onode_2[4]; +assign onode_3[3]=onode_2[3]&onode_2[5]; +assign onode_3[4]=onode_2[4]&onode_2[6]; +assign onode_3[5]=onode_2[5]&onode_2[7]; +assign onode_3[6]=onode_2[6]&onode_2[8]; +assign onode_3[7]=onode_2[7]&onode_2[9]; +assign onode_3[8]=onode_2[8]&onode_2[10]; +assign onode_3[9]=onode_2[9]&onode_2[11]; +assign onode_3[10]=onode_2[10]&onode_2[12]; +assign onode_3[11]=onode_2[11]&onode_2[13]; +assign onode_3[12]=onode_2[12]&onode_2[14]; +assign onode_3[13]=onode_2[13]&onode_2[15]; +assign onode_3[14]=onode_2[14]; +assign onode_3[15]=onode_2[15]; +///////////////////////// layer 4 //////////////////////////// +wire [15:0]onode_4; +assign onode_4[0]=onode_3[0]&onode_3[4]; +assign onode_4[1]=onode_3[1]&onode_3[5]; +assign onode_4[2]=onode_3[2]&onode_3[6]; +assign onode_4[3]=onode_3[3]&onode_3[7]; +assign onode_4[4]=onode_3[4]&onode_3[8]; +assign onode_4[5]=onode_3[5]&onode_3[9]; +assign onode_4[6]=onode_3[6]&onode_3[10]; +assign onode_4[7]=onode_3[7]&onode_3[11]; +assign onode_4[8]=onode_3[8]&onode_3[12]; +assign onode_4[9]=onode_3[9]&onode_3[13]; +assign onode_4[10]=onode_3[10]&onode_3[14]; +assign onode_4[11]=onode_3[11]&onode_3[15]; +assign onode_4[12]=onode_3[12]; +assign onode_4[13]=onode_3[13]; +assign onode_4[14]=onode_3[14]; +assign onode_4[15]=onode_3[15]; +///////////////////////// layer 5 //////////////////////////// +wire [15:0]onode_5; +assign onode_5[0]=onode_4[0]&onode_4[8]; +assign onode_5[1]=onode_4[1]&onode_4[9]; +assign onode_5[2]=onode_4[2]&onode_4[10]; +assign onode_5[3]=onode_4[3]&onode_4[11]; +assign onode_5[4]=onode_4[4]&onode_4[12]; +assign onode_5[5]=onode_4[5]&onode_4[13]; +assign onode_5[6]=onode_4[6]&onode_4[14]; +assign onode_5[7]=onode_4[7]&onode_4[15]; +assign onode_5[8]=onode_4[8]; +assign onode_5[9]=onode_4[9]; +assign onode_5[10]=onode_4[10]; +assign onode_5[11]=onode_4[11]; +assign onode_5[12]=onode_4[12]; +assign onode_5[13]=onode_4[13]; +assign onode_5[14]=onode_4[14]; +assign onode_5[15]=onode_4[15]; + + +// even nodes +wire [14:0]enode; +assign enode[14]=onode_5[15]&node_0[29]; +assign enode[13]=onode_5[14]&node_0[27]; +assign enode[12]=onode_5[13]&node_0[25]; +assign enode[11]=onode_5[12]&node_0[23]; +assign enode[10]=onode_5[11]&node_0[21]; +assign enode[9]=onode_5[10]&node_0[19]; +assign enode[8]=onode_5[9]&node_0[17]; +assign enode[7]=onode_5[8]&node_0[15]; +assign enode[6]=onode_5[7]&node_0[13]; +assign enode[5]=onode_5[6]&node_0[11]; +assign enode[4]=onode_5[5]&node_0[9]; +assign enode[3]=onode_5[4]&node_0[7]; +assign enode[2]=onode_5[3]&node_0[5]; +assign enode[1]=onode_5[2]&node_0[3]; +assign enode[0]=onode_5[1]&node_0[1]; + +// shift amount genration +wire shift_1; +assign shift_1=onode_5[15]; +wire [1:0]shift_2; +assign shift_2[0]=onode_5[14]; +assign shift_2[1]=enode[14]; +wire [1:0]shift_3; +assign shift_3[0]=onode_5[13]; +assign shift_3[1]=enode[13]; +wire [3:0]shift_4; +assign shift_4[0]=onode_5[11]; +assign shift_4[1]=enode[11]; +assign shift_4[2]=onode_5[12]; +assign shift_4[3]=enode[12]; +wire [7:0]shift_5; +assign shift_5[0]=onode_5[7]; +assign shift_5[1]=enode[7]; +assign shift_5[2]=onode_5[8]; +assign shift_5[3]=enode[8]; +assign shift_5[4]=onode_5[9]; +assign shift_5[5]=enode[9]; +assign shift_5[6]=onode_5[10]; +assign shift_5[7]=enode[10]; +wire [13:0]shift_6; +assign shift_6[0]=onode_5[0]; +assign shift_6[1]=enode[0]; +assign shift_6[2]=onode_5[1]; +assign shift_6[3]=enode[1]; +assign shift_6[4]=onode_5[2]; +assign shift_6[5]=enode[2]; +assign shift_6[6]=onode_5[3]; +assign shift_6[7]=enode[3]; +assign shift_6[8]=onode_5[4]; +assign shift_6[9]=enode[4]; +assign shift_6[10]=onode_5[5]; +assign shift_6[11]=enode[5]; +assign shift_6[12]=onode_5[6]; +assign shift_6[13]=enode[6]; + +// shift tree + +wire [31:0]data_1,data_2,data_3,data_4,data_5; +shift_1b shift_1b_0( +shift_1, +i_data, +data_1 +); + +shift_3b shift_3b_0( +{shift_2,1'b0}, +data_1, +data_2 +); + +shift_3b shift_3b_1( +{shift_3,1'b0}, +data_2, +data_3 +); + +shift_7b shift_7b_0( +{shift_4,3'b0}, +data_3, +o_data +); +/* +shift_7b shift_7b_0( +{shift_4,3'b0}, +data_3, +data_4 +); + +shift_15b shift_15b_0( +{shift_5,7'b0}, +data_4, +data_5 +); + +shift_15b shift_15b_1( +{shift_6,1'b0}, +data_5, +o_data +); +*/ +// number of shifted bits determination +wire [4:0]shifted_1,shifted_2,shifted_3,shifted_4,shifted_5; +assign shifted_1=shift_1?1:0; +assign shifted_2= (shift_2==2'b11)?3: + (shift_2==2'b10)?2:shifted_1; +assign shifted_3= (shift_3==2'b11)?5: + (shift_3==2'b10)?4:shifted_2; + +assign o_shifted= (shift_4==4'b1111)?9: + (shift_4==4'b1110)?8: + (shift_4==4'b1100)?7: + (shift_4==4'b1000)?6:shifted_3; + +/* +assign shifted_4= (shift_4==4'b1111)?9: + (shift_4==4'b1110)?8: + (shift_4==4'b1100)?7: + (shift_4==4'b1000)?6:shifted_3; +assign shifted_5= (shift_5==8'b11111111)?17: + (shift_5==8'b11111110)?16: + (shift_5==8'b11111100)?15: + (shift_5==8'b11111000)?14: + (shift_5==8'b11110000)?13: + (shift_5==8'b11100000)?12: + (shift_5==8'b11000000)?11: + (shift_5==8'b10000000)?10:shifted_4; +assign o_shifted= (shift_6==14'b11111111111111)?31: + (shift_6==14'b11111111111110)?30: + (shift_6==14'b11111111111100)?29: + (shift_6==14'b11111111111000)?28: + (shift_6==14'b11111111110000)?27: + (shift_6==14'b11111111100000)?26: + (shift_6==14'b11111111000000)?25: + (shift_6==14'b11111110000000)?24: + (shift_6==14'b11111100000000)?23: + (shift_6==14'b11111000000000)?22: + (shift_6==14'b11110000000000)?21: + (shift_6==14'b11100000000000)?20: + (shift_6==14'b11000000000000)?19: + (shift_6==14'b10000000000000)?18:shifted_5; +*/ + + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pid_test/top.v b/designs/encrypted_ip/pid_test/top.v new file mode 100644 index 000000000..55c69b191 --- /dev/null +++ b/designs/encrypted_ip/pid_test/top.v @@ -0,0 +1,115 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/11/2017 12:13:08 PM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module top( + input clk, + input reset, + input [15:0] sw, // Not used + input [4:0] btn, // Not used + output [15:0] led, // Not used + output [6:0] seg, // Not used + output reg dp, + output [7:0] an // Not used + ); + + + + parameter wb_nb=32; + parameter adr_wb_nb=32; + wire i_wb_cyc; + wire i_wb_stb; + wire i_wb_we; + wire [adr_wb_nb-1:0]i_wb_adr; + wire [wb_nb-1:0]i_wb_data; + wire o_wb_ack; + wire [wb_nb-1:0]o_wb_data; + + //u(n) output + wire [31:0]o_un; + wire o_valid; + + +/* module divider_dshift( + input i_clk, + input i_rst, + input [31:0]i_dividend, + input [31:0]i_divisor, + input i_start, + output o_ready, + output reg [31:0]o_quotient, + output reg [31:0]o_remainder + );*/ + + wire [31:0] d0_q; + wire [31:0] d0_r; + + wire [31:0] d1_q; + wire [31:0] d1_r; + + wire [31:0] d2_q; + wire [31:0] d2_r; + + wire [31:0] d3_q; + wire [31:0] d3_r; + + wire [31:0] d4_q; + wire [31:0] d4_r; + + + wire d0_done; + wire d1_done; + wire d2_done; + wire d3_done; + wire d4_done; + + + assign d0_q = 32'hDEADBEEF; + assign d0_r = 32'hDEADBEEF; + assign d0_done = 1'b1; + assign i_wb_cyc = ^d2_r; + assign i_wb_we = ^d2_q; + + divider_dshift divider_dshift_1(.i_clk(clk), .i_rst(reset), .i_dividend(d0_q), .i_divisor(d0_r), .i_start(d0_done), .o_ready(d1_done), .o_quotient(d1_q), .o_remainder(d1_r)); + divider_dshift divider_dshift_2(.i_clk(clk), .i_rst(reset), .i_dividend(d1_q), .i_divisor(d1_r), .i_start(d1_done), .o_ready(d2_done), .o_quotient(d2_q), .o_remainder(d2_r)); + divider_dshift divider_dshift_3(.i_clk(clk), .i_rst(reset), .i_dividend(d2_q), .i_divisor(d2_r), .i_start(d2_done), .o_ready(d3_done), .o_quotient(d3_q), .o_remainder(d3_r)); + + + pid pid_0(.i_clk(clk), + .i_rst(reset), + .i_wb_cyc(i_wb_cyc), + .i_wb_stb(d3_done), + .i_wb_we(i_wb_we), + .i_wb_adr(d3_r), + .i_wb_data(d3_q), + .o_wb_ack(o_wb_ack), + .o_wb_data(o_wb_data), + .o_un(o_un), + .o_valid(o_valid)); + + always @(posedge clk) + begin + if (o_un == 0) begin + dp = 1; + end else + dp = 0; + end + +endmodule From c955fab4a84dfde176d5a35f2381defb417229bb Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Fri, 8 Dec 2023 11:46:40 -0700 Subject: [PATCH 06/25] Working on part2 --- .gitignore | 2 ++ bfasst/flows/encrypted_ip.py | 9 ++++++++- bfasst/paths.py | 2 +- bfasst/tools/ip/loader_vivado.tcl.mustache | 2 +- bfasst/tools/synth/vivado_synth.py | 4 +++- bfasst/tools/synth/vivado_synth.tcl.mustache | 1 + bfasst/yaml_parser.py | 1 + designs/encrypted_ip/pid_test/design.yaml | 3 ++- notes.txt | 13 +++++++++++++ 9 files changed, 32 insertions(+), 5 deletions(-) create mode 100644 notes.txt diff --git a/.gitignore b/.gitignore index cbe2befd3..8faa89bc6 100644 --- a/.gitignore +++ b/.gitignore @@ -38,3 +38,5 @@ env.sh build.ninja .ninja_log .ninja_deps + +/_build diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py index aa76e6c82..083621429 100644 --- a/bfasst/flows/encrypted_ip.py +++ b/bfasst/flows/encrypted_ip.py @@ -11,6 +11,8 @@ class EncryptedIP(Flow): def __init__(self, design): super().__init__(design) + encrypted_ip_paths = [] + # Synthesize and encrypt each encrypte IP for ip in self.design_props.encrypted_ip: synth_tool = VivadoSynth( @@ -18,7 +20,7 @@ def __init__(self, design): design, ooc=True, top=ip, - synth_options="-mode out_of_context -flatten_hierarchy full", + synth_options="-flatten_hierarchy full", ) synth_tool.override_build_path( synth_tool.build_path.parent / f"{synth_tool.build_path.name}_{ip}" @@ -29,9 +31,14 @@ def __init__(self, design): ip_encrypter_tool.override_build_path( ip_encrypter_tool.build_path.parent / f"{ip_encrypter_tool.build_path.name}_{ip}" ) + encrypted_ip_paths.append(ip_encrypter_tool.outputs["encrypted_verilog"]) # Synthesize the top module synth_tool = VivadoSynth(self, design, ooc=True, synth_options="-flatten_hierarchy rebuilt") + synth_tool.verilog = [ + self.design_path / v for v in self.design_props.encrypted_ip_user_files + ] + synth_tool.verilog.extend(encrypted_ip_paths) # Encrypted IP Shell EncryptedIpLoader(self, design, user_synth_dcp_path=synth_tool.outputs["synth_dcp"]) diff --git a/bfasst/paths.py b/bfasst/paths.py index 1cb9b1926..fe56d9c26 100644 --- a/bfasst/paths.py +++ b/bfasst/paths.py @@ -5,7 +5,7 @@ ROOT_PATH = pathlib.Path(__file__).resolve().parent.parent -BUILD_PATH = pathlib.Path().cwd() / "build" +BUILD_PATH = pathlib.Path().cwd() / "_build" DESIGNS_PATH = ROOT_PATH / "designs" BFASST_PATH = ROOT_PATH / "bfasst" diff --git a/bfasst/tools/ip/loader_vivado.tcl.mustache b/bfasst/tools/ip/loader_vivado.tcl.mustache index 4fb1ac906..f2167487d 100644 --- a/bfasst/tools/ip/loader_vivado.tcl.mustache +++ b/bfasst/tools/ip/loader_vivado.tcl.mustache @@ -4,7 +4,6 @@ open_checkpoint {{ loader_impl_dcp }} #set_property dont_touch true [get_cells $env(USER_SPACE_BLOCK_NAME)] read_checkpoint -cell "static_top_i/top_0" {{ user_synth_dcp }} -exit # Step 4: Place and route puts "Time starting implementing partition DTIMING" @@ -13,6 +12,7 @@ place_design route_design puts "Time ending implementing partition DTIMING" puts [exec date] +exit # Step 4: Write out implemented checkpoints write_checkpoint ./checkpoints/$env(BITSTREAM_NAME_FULL).dcp -force diff --git a/bfasst/tools/synth/vivado_synth.py b/bfasst/tools/synth/vivado_synth.py index c173b8333..45eda4940 100644 --- a/bfasst/tools/synth/vivado_synth.py +++ b/bfasst/tools/synth/vivado_synth.py @@ -14,6 +14,8 @@ def __init__(self, flow, design_path, ooc=False, synth_options="", top=None): super().__init__(flow, design_path, top=top, ooc=ooc) self.synth_options = synth_options self._my_dir_path = pathlib.Path(__file__).parent + if ooc: + self.synth_options += " -mode out_of_context" # outputs must be initialized AFTER output paths are set self._init_outputs() @@ -38,7 +40,7 @@ def create_build_snippets(self): "top": self.design_props.top if not self.top else self.top, "vhdl": self.vhdl, "vhdl_libs": list(self.vhdl_file_lib_map.items()), - "verilog": self.verilog, + "verilog": [str(path) for path in self.verilog], "system_verilog": self.system_verilog, "io": str(self.build_path / "report_io.txt") if not self.ooc else False, "synth_output": str(self.build_path), diff --git a/bfasst/tools/synth/vivado_synth.tcl.mustache b/bfasst/tools/synth/vivado_synth.tcl.mustache index a1707e250..fd6d2ccf2 100644 --- a/bfasst/tools/synth/vivado_synth.tcl.mustache +++ b/bfasst/tools/synth/vivado_synth.tcl.mustache @@ -24,6 +24,7 @@ place_ports {{/io}} write_edif -force {{ synth_output }}/viv_synth.edf write_checkpoint -force -file {{ synth_output }}/synth.dcp +write_verilog -force -file {{ synth_output }}/viv_synth.v {{#io}} report_io -force -file {{ . }} diff --git a/bfasst/yaml_parser.py b/bfasst/yaml_parser.py index f6d701398..f81ed0fc0 100644 --- a/bfasst/yaml_parser.py +++ b/bfasst/yaml_parser.py @@ -114,6 +114,7 @@ def __init__(self, yaml_path): self.encrypted_ip = None if "encrypted_ip" in self.props: self.encrypted_ip = self.props["encrypted_ip"] + self.encrypted_ip_user_files = self.props["encrypted_ip_user_files"] class FlowDescriptionParser(YamlParser): diff --git a/designs/encrypted_ip/pid_test/design.yaml b/designs/encrypted_ip/pid_test/design.yaml index dd64f661d..0f7e762de 100644 --- a/designs/encrypted_ip/pid_test/design.yaml +++ b/designs/encrypted_ip/pid_test/design.yaml @@ -1,3 +1,4 @@ top: top -encrypted_ip: ["pid", "divider_dshift"] \ No newline at end of file +encrypted_ip: ["pid", "divider_dshift"] +encrypted_ip_user_files: ["top.v"] \ No newline at end of file diff --git a/notes.txt b/notes.txt new file mode 100644 index 000000000..511374d03 --- /dev/null +++ b/notes.txt @@ -0,0 +1,13 @@ + checkpoints/divider_dshift_synthed_encrypted.dcp + checkpoints/divider_dshift_synthed.dcp +x checkpoints/divider_dshift_synthed.edif +x src/pid_test/encrypted/divider_dshift_synthed_encrypted.v +x src/pid_test/nonencrypted/divider_dshift_synthed.v + + checkpoints/pid_synthed_encrypted.dcp + checkpoints/pid_synthed.dcp +x checkpoints/pid_synthed.edif +x src/pid_test/encrypted/pid_synthed_encrypted.v +x src/pid_test/nonencrypted/pid_synthed.v + + user_space_synthed.v \ No newline at end of file From 2be2a33e95065dd71858a8f8788691b966b5ccf8 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Fri, 8 Dec 2023 13:11:14 -0700 Subject: [PATCH 07/25] user partial bitstream --- bfasst/tools/ip/loader.py | 5 +++++ bfasst/tools/ip/loader_build.ninja.mustache | 2 +- bfasst/tools/ip/loader_vivado.tcl.mustache | 11 +++++------ 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/bfasst/tools/ip/loader.py b/bfasst/tools/ip/loader.py index 181e74cbb..1d1bad8ae 100644 --- a/bfasst/tools/ip/loader.py +++ b/bfasst/tools/ip/loader.py @@ -30,6 +30,8 @@ def create_build_snippets(self): ENCRYPTED_IP_PATH / "Project" / "loader_imp_design" / "implemented_loader.dcp" ), "user_synth_dcp": str(self.user_synth_dcp_path), + "user_partial_bitstream": str(self.build_path / "user_partial.bit"), + "final": str(self.build_path / "final"), } vivado_tcl_json = json.dumps(vivado_tcl_dict, indent=4) json_write_if_changed(self.build_path / "vivado.json", vivado_tcl_json) @@ -40,6 +42,9 @@ def create_build_snippets(self): "cwd": self.build_path, "loader_tcl_template": self._my_dir_path / "loader_vivado.tcl.mustache", "top_dcp": str(self.user_synth_dcp_path), + "final": str(self.build_path / "final"), + "user_partial_bitstream": str(self.build_path / "user_partial.bit"), + }, ) diff --git a/bfasst/tools/ip/loader_build.ninja.mustache b/bfasst/tools/ip/loader_build.ninja.mustache index b273a475d..87b2b5bee 100644 --- a/bfasst/tools/ip/loader_build.ninja.mustache +++ b/bfasst/tools/ip/loader_build.ninja.mustache @@ -1,6 +1,6 @@ build {{ cwd }}/vivado.tcl: template {{ cwd }}/vivado.json {{ loader_tcl_template }} -build abc: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} +build {{ final }}.dcp {{ final }}.edif {{ user_partial_bitstream }}: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} cwd = {{ cwd }} journal = {{ cwd }}/vivado.jou log = {{ cwd }}/vivado.log diff --git a/bfasst/tools/ip/loader_vivado.tcl.mustache b/bfasst/tools/ip/loader_vivado.tcl.mustache index f2167487d..0fb7ee98d 100644 --- a/bfasst/tools/ip/loader_vivado.tcl.mustache +++ b/bfasst/tools/ip/loader_vivado.tcl.mustache @@ -12,19 +12,18 @@ place_design route_design puts "Time ending implementing partition DTIMING" puts [exec date] -exit # Step 4: Write out implemented checkpoints -write_checkpoint ./checkpoints/$env(BITSTREAM_NAME_FULL).dcp -force -write_edif ./checkpoints/$env(BITSTREAM_NAME_FULL).edif -force +write_checkpoint {{ final }}.dcp -force +write_edif {{ final }}.edif -force puts "Time starting writing bitstream DTIMING" -set a [exec date] -puts $a +puts [exec date] # Step 5.1: Bitstream for timing purposes -write_bitstream -bin_file -cell $env(USER_SPACE_BLOCK_NAME) partialpartialtiming.bit -force +write_bitstream -bin_file -cell "static_top_i/top_0" {{ user_partial_bit }} -force +exit puts "Time starting writing bitstreams not applicable for timing DTIMING" From 9e871b889f7f8d473b908cbcd236786a1aa33f0c Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Fri, 8 Dec 2023 14:05:58 -0700 Subject: [PATCH 08/25] step 2 done --- bfasst/tools/ip/loader.py | 2 +- bfasst/tools/ip/loader_build.ninja.mustache | 2 +- bfasst/tools/ip/loader_vivado.tcl.mustache | 21 ++++++++++----------- 3 files changed, 12 insertions(+), 13 deletions(-) diff --git a/bfasst/tools/ip/loader.py b/bfasst/tools/ip/loader.py index 1d1bad8ae..6a49b648c 100644 --- a/bfasst/tools/ip/loader.py +++ b/bfasst/tools/ip/loader.py @@ -32,6 +32,7 @@ def create_build_snippets(self): "user_synth_dcp": str(self.user_synth_dcp_path), "user_partial_bitstream": str(self.build_path / "user_partial.bit"), "final": str(self.build_path / "final"), + "key_files": str(ENCRYPTED_IP_PATH / "Project" / "key_files"), } vivado_tcl_json = json.dumps(vivado_tcl_dict, indent=4) json_write_if_changed(self.build_path / "vivado.json", vivado_tcl_json) @@ -44,7 +45,6 @@ def create_build_snippets(self): "top_dcp": str(self.user_synth_dcp_path), "final": str(self.build_path / "final"), "user_partial_bitstream": str(self.build_path / "user_partial.bit"), - }, ) diff --git a/bfasst/tools/ip/loader_build.ninja.mustache b/bfasst/tools/ip/loader_build.ninja.mustache index 87b2b5bee..f10cbf99e 100644 --- a/bfasst/tools/ip/loader_build.ninja.mustache +++ b/bfasst/tools/ip/loader_build.ninja.mustache @@ -1,6 +1,6 @@ build {{ cwd }}/vivado.tcl: template {{ cwd }}/vivado.json {{ loader_tcl_template }} -build {{ final }}.dcp {{ final }}.edif {{ user_partial_bitstream }}: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} +build {{ final }}.dcp {{ final }}.edif {{ final }}_unencrypted.bit {{ final }}_encrypted.bit {{ user_partial_bitstream }}: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} cwd = {{ cwd }} journal = {{ cwd }}/vivado.jou log = {{ cwd }}/vivado.log diff --git a/bfasst/tools/ip/loader_vivado.tcl.mustache b/bfasst/tools/ip/loader_vivado.tcl.mustache index 0fb7ee98d..e48bbddb4 100644 --- a/bfasst/tools/ip/loader_vivado.tcl.mustache +++ b/bfasst/tools/ip/loader_vivado.tcl.mustache @@ -22,22 +22,21 @@ puts [exec date] # Step 5.1: Bitstream for timing purposes -write_bitstream -bin_file -cell "static_top_i/top_0" {{ user_partial_bit }} -force -exit +write_bitstream -bin_file -cell "static_top_i/top_0" {{ user_partial_bitstream }} -force puts "Time starting writing bitstreams not applicable for timing DTIMING" -set a [exec date] -puts $a +puts [exec date] + # Step 5.2: Write out full bitstream -write_bitstream -bin_file ./bitstreams/unencrypted/$env(BITSTREAM_NAME_FULL).bit -force +write_bitstream -bin_file {{ final }}_unencrypted.bit -force #Step 6: Write out encrypted bitstream -set_property BITSTREAM.ENCRYPTION.ENCRYPT YES [get_designs checkpoint_$env(LOADER_DESIGN_NAME_IMPLEMENTED)] -set_property BITSTREAM.ENCRYPTION.ENCRYPTKEYSELECT EFUSE [get_designs checkpoint_$env(LOADER_DESIGN_NAME_IMPLEMENTED)] -set_property BITSTREAM.ENCRYPTION.KEYFILE ./key_files/design_1_wrapper.nky [get_designs checkpoint_$env(LOADER_DESIGN_NAME_IMPLEMENTED)] +set_property BITSTREAM.ENCRYPTION.ENCRYPT YES [get_designs checkpoint_implemented_loader] +set_property BITSTREAM.ENCRYPTION.ENCRYPTKEYSELECT EFUSE [get_designs checkpoint_implemented_loader] +set_property BITSTREAM.ENCRYPTION.KEYFILE {{ key_files }}/design_1_wrapper.nky [get_designs checkpoint_implemented_loader] #set_property BITSTREAM.GENERAL.CRC DISABLE [get_designs checkpoint_$env(LOADER_DESIGN_NAME_IMPLEMENTED)] -write_bitstream -bin_file ./bitstreams/encrypted/$env(BITSTREAM_NAME_FULL)_encrypted.bit -force +write_bitstream -bin_file {{ final }}_encrypted.bit -force puts "Time ending writing bitstream not applicable for timing DTIMING" -set a [exec date] -puts $a \ No newline at end of file +puts [exec date] +exit \ No newline at end of file From 964c19d67bdb2da9f4acfddb47f4e29a74d5aa22 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Sat, 9 Dec 2023 17:22:22 -0700 Subject: [PATCH 09/25] working on part2 --- bfasst/flows/encrypted_ip.py | 15 +- bfasst/tools/ip/loader.py | 13 +- bfasst/tools/ip/loader_build.ninja.mustache | 7 +- bfasst/tools/ip/loader_rules.ninja | 4 + .../16x16bit_multiplier_pipelined.v | 1413 +++++++++++++++++ designs/encrypted_ip/pid_simple/CLA_fixed.v | 259 +++ designs/encrypted_ip/pid_simple/PID_defines.v | 8 + designs/encrypted_ip/pid_simple/booth.v | 37 + designs/encrypted_ip/pid_simple/design.yaml | 6 + designs/encrypted_ip/pid_simple/pid_simple.v | 434 +++++ designs/encrypted_ip/pid_simple/top.v | 57 + 11 files changed, 2250 insertions(+), 3 deletions(-) create mode 100644 bfasst/tools/ip/loader_rules.ninja create mode 100644 designs/encrypted_ip/pid_simple/16x16bit_multiplier_pipelined.v create mode 100644 designs/encrypted_ip/pid_simple/CLA_fixed.v create mode 100644 designs/encrypted_ip/pid_simple/PID_defines.v create mode 100644 designs/encrypted_ip/pid_simple/booth.v create mode 100644 designs/encrypted_ip/pid_simple/design.yaml create mode 100644 designs/encrypted_ip/pid_simple/pid_simple.v create mode 100644 designs/encrypted_ip/pid_simple/top.v diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py index 083621429..bc537f9cc 100644 --- a/bfasst/flows/encrypted_ip.py +++ b/bfasst/flows/encrypted_ip.py @@ -12,9 +12,15 @@ def __init__(self, design): super().__init__(design) encrypted_ip_paths = [] + encrypted_ip_names = [] + encrypted_ip_ciphertext_paths = [] + + assert self.design_props.encrypted_ip, "No encrypted IPs specified" # Synthesize and encrypt each encrypte IP for ip in self.design_props.encrypted_ip: + encrypted_ip_names.append(ip) + synth_tool = VivadoSynth( self, design, @@ -32,6 +38,7 @@ def __init__(self, design): ip_encrypter_tool.build_path.parent / f"{ip_encrypter_tool.build_path.name}_{ip}" ) encrypted_ip_paths.append(ip_encrypter_tool.outputs["encrypted_verilog"]) + encrypted_ip_ciphertext_paths.append(ip_encrypter_tool.outputs["lut_ciphertext"]) # Synthesize the top module synth_tool = VivadoSynth(self, design, ooc=True, synth_options="-flatten_hierarchy rebuilt") @@ -41,7 +48,13 @@ def __init__(self, design): synth_tool.verilog.extend(encrypted_ip_paths) # Encrypted IP Shell - EncryptedIpLoader(self, design, user_synth_dcp_path=synth_tool.outputs["synth_dcp"]) + EncryptedIpLoader( + self, + design, + user_synth_dcp_path=synth_tool.outputs["synth_dcp"], + ip_names=encrypted_ip_names, + ip_ciphertext_paths=encrypted_ip_ciphertext_paths, + ) def get_top_level_flow_path(self): return pathlib.Path(__file__) diff --git a/bfasst/tools/ip/loader.py b/bfasst/tools/ip/loader.py index 6a49b648c..dc084466c 100644 --- a/bfasst/tools/ip/loader.py +++ b/bfasst/tools/ip/loader.py @@ -7,14 +7,19 @@ class EncryptedIpLoader(Tool): - def __init__(self, flow, design_path, user_synth_dcp_path) -> None: + def __init__( + self, flow, design_path, user_synth_dcp_path, ip_names, ip_ciphertext_paths + ) -> None: super().__init__(flow, design_path) self.build_path = self.design_build_path / "loader" self._my_dir_path = pathlib.Path(__file__).parent self.user_synth_dcp_path = user_synth_dcp_path + self.ip_names = ip_names + self.ip_ciphertext_paths = ip_ciphertext_paths self._init_outputs() def create_rule_snippets(self): + self._append_rule_snippets_default(__file__) self._append_rule_snippets_default( None, { @@ -45,6 +50,12 @@ def create_build_snippets(self): "top_dcp": str(self.user_synth_dcp_path), "final": str(self.build_path / "final"), "user_partial_bitstream": str(self.build_path / "user_partial.bit"), + "ip_args": " ".join( + [ + f"--ip {ip_name} {cipher_path}" + for ip_name, cipher_path in zip(self.ip_names, self.ip_ciphertext_paths) + ] + ), }, ) diff --git a/bfasst/tools/ip/loader_build.ninja.mustache b/bfasst/tools/ip/loader_build.ninja.mustache index f10cbf99e..26a63293e 100644 --- a/bfasst/tools/ip/loader_build.ninja.mustache +++ b/bfasst/tools/ip/loader_build.ninja.mustache @@ -1,6 +1,11 @@ build {{ cwd }}/vivado.tcl: template {{ cwd }}/vivado.json {{ loader_tcl_template }} -build {{ final }}.dcp {{ final }}.edif {{ final }}_unencrypted.bit {{ final }}_encrypted.bit {{ user_partial_bitstream }}: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} +build {{ final }}.dcp {{ final }}.edif {{ final }}_unencrypted.bit {{ final }}_unencrypted_pblock_user_partial.bit {{ final }}_encrypted.bit {{ user_partial_bitstream }}: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} cwd = {{ cwd }} journal = {{ cwd }}/vivado.jou log = {{ cwd }}/vivado.log + +build {{ final }}_patched.bin: encrypted_ip_bit_patcher {{ final }}.dcp {{ final }}_unencrypted_pblock_user_partial.bit + cwd = {{ cwd }} + log = {{ cwd }}/patcher_log.txt + ip_args = {{ ip_args }} diff --git a/bfasst/tools/ip/loader_rules.ninja b/bfasst/tools/ip/loader_rules.ninja new file mode 100644 index 000000000..0211e80bf --- /dev/null +++ b/bfasst/tools/ip/loader_rules.ninja @@ -0,0 +1,4 @@ +rule encrypted_ip_bit_patcher + command = python3 third_party/encrypted_ip/Project/python_scripts/getLutDataGenPatched2.py $in $out $ip_args > $log + description = Patching user bitstream + diff --git a/designs/encrypted_ip/pid_simple/16x16bit_multiplier_pipelined.v b/designs/encrypted_ip/pid_simple/16x16bit_multiplier_pipelined.v new file mode 100644 index 000000000..7e9f45680 --- /dev/null +++ b/designs/encrypted_ip/pid_simple/16x16bit_multiplier_pipelined.v @@ -0,0 +1,1413 @@ +/*16x16-bit multiplier +Author: Zhu Xu +Email: m99a1@yahoo.cn +*/ + +//Booth Encoder Array +module booth_array( +input [15:0]multiplier, +output [7:0]zero, +output [7:0]double, +output [7:0]negation +); + +booth_radix4 booth_radix4_0( +{multiplier[1:0],1'b0}, +zero[0], +double[0], +negation[0] +); + +booth_radix4 booth_radix4_1( +multiplier[3:1], +zero[1], +double[1], +negation[1] +); + +booth_radix4 booth_radix4_2( +multiplier[5:3], +zero[2], +double[2], +negation[2] +); +booth_radix4 booth_radix4_3( +multiplier[7:5], +zero[3], +double[3], +negation[3] +); + +booth_radix4 booth_radix4_4( +multiplier[9:7], +zero[4], +double[4], +negation[4] +); + +booth_radix4 booth_radix4_5( +multiplier[11:9], +zero[5], +double[5], +negation[5] +); +booth_radix4 booth_radix4_6( +multiplier[13:11], +zero[6], +double[6], +negation[6] +); + +booth_radix4 booth_radix4_7( +multiplier[15:13], +zero[7], +double[7], +negation[7] +); + +endmodule + +/*partial product generator unit +generate one 17-bit partial with inversed MSB without correction bit for negation +*/ +module partial_product_gen( +input [15:0]md, //multiplicand +input zero, +input double, +input negation, +output [16:0]pp +); + +wire [15:0]nmd; +assign nmd=negation?~md:md; + +wire [15:0]zmd; +assign zmd=zero?0:nmd; + +assign pp=double?{~zmd[15],zmd[14:0],negation}:{~zmd[15],zmd[15:0]}; + +endmodule + +module half_adder( +input A, +input B, +output S, +output carry +); +assign S=A^B; +assign carry=A&B; +endmodule + +module full_adder( +input A, +input B, +input cin, +output S, +output cout +); +wire AB; +assign AB=A&B; +wire AxorB; +assign AxorB=A^B; +assign S=AxorB^cin; +assign cout=AB|(AxorB&cin); +endmodule + +module compressor42( +input A, +input B, +input C, +input D, +input cin, +output S, +output carry, +output cout +); +wire AB; +assign AB=A&B; +wire AxorB; +assign AxorB=A^B; +wire CD; +assign CD=C&D; +wire CxorD; +assign CxorD=C^D; + +wire AxBxCxD=AxorB^CxorD; + +assign cout=AB|CD; +assign carry=(AB&CD)|(AxorB&CxorD)|((AxBxCxD)&cin); + +assign S=AxBxCxD^cin; + +endmodule + + +module multiplier_16x16bit_pipelined( +input i_clk, +input i_rst, +input i_start, +input [15:0]i_md, +input [15:0]i_mr, +output [31:0]o_product, +output o_ready +); +/////////////////////////////////////////////////////////////stage 0/////////////////////////////////////////////////// + +reg [15:0]md; +reg [15:0]mr; +reg stage_0_ready; + +always @(posedge i_clk or negedge i_rst)begin + if(!i_rst)begin + md<=0; + mr<=0; + stage_0_ready<=0; + end + else begin + if(i_start)begin + md<=i_md; + mr<=i_mr; + end + stage_0_ready<=i_start; + end + +end + +wire [7:0]zero; +wire [7:0]double; +wire [7:0]negation; + +booth_array booth_array_0( +mr, +zero, +double, +negation +); + + +//layer 0 +wire layer_0_w0[1:0]; +wire layer_0_w1; +wire layer_0_w2[2:0]; +wire layer_0_w3[1:0]; +wire layer_0_w4[3:0]; +wire layer_0_w5[2:0]; +wire layer_0_w6[4:0]; +wire layer_0_w7[3:0]; +wire layer_0_w8[5:0]; +wire layer_0_w9[4:0]; +wire layer_0_w10[6:0]; +wire layer_0_w11[5:0]; +wire layer_0_w12[7:0]; +wire layer_0_w13[6:0]; +wire layer_0_w14[8:0]; +wire layer_0_w15[7:0]; +wire layer_0_w16[8:0]; +wire layer_0_w17[7:0]; +wire layer_0_w18[6:0]; +wire layer_0_w19[6:0]; +wire layer_0_w20[5:0]; +wire layer_0_w21[5:0]; +wire layer_0_w22[4:0]; +wire layer_0_w23[4:0]; +wire layer_0_w24[3:0]; +wire layer_0_w25[3:0]; +wire layer_0_w26[2:0]; +wire layer_0_w27[2:0]; +wire layer_0_w28[1:0]; +wire layer_0_w29[1:0]; +wire layer_0_w30; +wire layer_0_w31; +partial_product_gen partial_product_gen_0( +md, +zero[0], +double[0], +negation[0], +{layer_0_w16[0],layer_0_w15[0],layer_0_w14[0],layer_0_w13[0],layer_0_w12[0],layer_0_w11[0],layer_0_w10[0],layer_0_w9[0],layer_0_w8[0],layer_0_w7[0],layer_0_w6[0],layer_0_w5[0],layer_0_w4[0],layer_0_w3[0],layer_0_w2[0],layer_0_w1,layer_0_w0[0]} +); +partial_product_gen partial_product_gen_1( +md, +zero[1], +double[1], +negation[1], +{layer_0_w18[0],layer_0_w17[0],layer_0_w16[1],layer_0_w15[1],layer_0_w14[1],layer_0_w13[1],layer_0_w12[1],layer_0_w11[1],layer_0_w10[1],layer_0_w9[1],layer_0_w8[1],layer_0_w7[1],layer_0_w6[1],layer_0_w5[1],layer_0_w4[1],layer_0_w3[1],layer_0_w2[1]} +); +partial_product_gen partial_product_gen_2( +md, +zero[2], +double[2], +negation[2], +{layer_0_w20[0],layer_0_w19[0],layer_0_w18[1],layer_0_w17[1],layer_0_w16[2],layer_0_w15[2],layer_0_w14[2],layer_0_w13[2],layer_0_w12[2],layer_0_w11[2],layer_0_w10[2],layer_0_w9[2],layer_0_w8[2],layer_0_w7[2],layer_0_w6[2],layer_0_w5[2],layer_0_w4[2]} +); +partial_product_gen partial_product_gen_3( +md, +zero[3], +double[3], +negation[3], +{layer_0_w22[0],layer_0_w21[0],layer_0_w20[1],layer_0_w19[1],layer_0_w18[2],layer_0_w17[2],layer_0_w16[3],layer_0_w15[3],layer_0_w14[3],layer_0_w13[3],layer_0_w12[3],layer_0_w11[3],layer_0_w10[3],layer_0_w9[3],layer_0_w8[3],layer_0_w7[3],layer_0_w6[3]} +); +partial_product_gen partial_product_gen_4( +md, +zero[4], +double[4], +negation[4], +{layer_0_w24[0],layer_0_w23[0],layer_0_w22[1],layer_0_w21[1],layer_0_w20[2],layer_0_w19[2],layer_0_w18[3],layer_0_w17[3],layer_0_w16[4],layer_0_w15[4],layer_0_w14[4],layer_0_w13[4],layer_0_w12[4],layer_0_w11[4],layer_0_w10[4],layer_0_w9[4],layer_0_w8[4]} +); +partial_product_gen partial_product_gen_5( +md, +zero[5], +double[5], +negation[5], +{layer_0_w26[0],layer_0_w25[0],layer_0_w24[1],layer_0_w23[1],layer_0_w22[2],layer_0_w21[2],layer_0_w20[3],layer_0_w19[3],layer_0_w18[4],layer_0_w17[4],layer_0_w16[5],layer_0_w15[5],layer_0_w14[5],layer_0_w13[5],layer_0_w12[5],layer_0_w11[5],layer_0_w10[5]} +); +partial_product_gen partial_product_gen_6( +md, +zero[6], +double[6], +negation[6], +{layer_0_w28[0],layer_0_w27[0],layer_0_w26[1],layer_0_w25[1],layer_0_w24[2],layer_0_w23[2],layer_0_w22[3],layer_0_w21[3],layer_0_w20[4],layer_0_w19[4],layer_0_w18[5],layer_0_w17[5],layer_0_w16[6],layer_0_w15[6],layer_0_w14[6],layer_0_w13[6],layer_0_w12[6]} +); +partial_product_gen partial_product_gen_7( +md, +zero[7], +double[7], +negation[7], +{layer_0_w30,layer_0_w29[0],layer_0_w28[1],layer_0_w27[1],layer_0_w26[2],layer_0_w25[2],layer_0_w24[3],layer_0_w23[3],layer_0_w22[4],layer_0_w21[4],layer_0_w20[5],layer_0_w19[5],layer_0_w18[6],layer_0_w17[6],layer_0_w16[7],layer_0_w15[7],layer_0_w14[7]} +); +//correction for negation +assign layer_0_w0[1]=negation[0]; +//sign extension +assign layer_0_w16[8]=1; +assign layer_0_w17[7]=1; +//correction for negation +assign layer_0_w2[2]=negation[1]; +//sign extension +assign layer_0_w19[6]=1; +//correction for negation +assign layer_0_w4[3]=negation[2]; +//sign extension +assign layer_0_w21[5]=1; +//correction for negation +assign layer_0_w6[4]=negation[3]; +//sign extension +assign layer_0_w23[4]=1; +//correction for negation +assign layer_0_w8[5]=negation[4]; +//sign extension +assign layer_0_w25[3]=1; +//correction for negation +assign layer_0_w10[6]=negation[5]; +//sign extension +assign layer_0_w27[2]=1; +//correction for negation +assign layer_0_w12[7]=negation[6]; +//sign extension +assign layer_0_w29[1]=1; +//correction for negation +assign layer_0_w14[8]=negation[7]; +//sign extension +assign layer_0_w31=1; + +//layer 1 +wire layer_1_w0[1:0]; +wire layer_1_w1; +wire layer_1_w2[2:0]; +wire layer_1_w3[1:0]; +wire layer_1_w4[1:0]; +wire layer_1_w5[1:0]; +wire layer_1_w6[1:0]; +wire layer_1_w7[3:0]; +wire layer_1_w8[2:0]; +wire layer_1_w9[2:0]; +wire layer_1_w10[4:0]; +wire layer_1_w11[3:0]; +wire layer_1_w12[3:0]; +wire layer_1_w13[5:0]; +wire layer_1_w14[4:0]; +wire layer_1_w15[4:0]; +wire layer_1_w16[5:0]; +wire layer_1_w17[4:0]; +wire layer_1_w18[5:0]; +wire layer_1_w19[4:0]; +wire layer_1_w20[3:0]; +wire layer_1_w21[3:0]; +wire layer_1_w22[2:0]; +wire layer_1_w23[2:0]; +wire layer_1_w24[3:0]; +wire layer_1_w25[2:0]; +wire layer_1_w26[1:0]; +wire layer_1_w27[1:0]; +wire layer_1_w28[2:0]; +wire layer_1_w29[1:0]; +wire layer_1_w30; +wire layer_1_w31; +assign layer_1_w0[0]=layer_0_w0[0]; +assign layer_1_w0[1]=layer_0_w0[1]; +assign layer_1_w1=layer_0_w1; +assign layer_1_w2[0]=layer_0_w2[0]; +assign layer_1_w2[1]=layer_0_w2[1]; +assign layer_1_w2[2]=layer_0_w2[2]; +assign layer_1_w3[0]=layer_0_w3[0]; +assign layer_1_w3[1]=layer_0_w3[1]; +full_adder layer_1_full_adder_0( +layer_0_w4[0], +layer_0_w4[1], +layer_0_w4[2], +layer_1_w4[0], +layer_1_w5[0] +); +assign layer_1_w4[1]=layer_0_w4[3]; +full_adder layer_1_full_adder_1( +layer_0_w5[0], +layer_0_w5[1], +layer_0_w5[2], +layer_1_w5[1], +layer_1_w6[0] +); +compressor42 layer_1_compressor42_0( +layer_0_w6[0], +layer_0_w6[1], +layer_0_w6[2], +layer_0_w6[3], +layer_0_w6[4], +layer_1_w6[1], +layer_1_w7[0], +layer_1_w7[1] +); +full_adder layer_1_full_adder_2( +layer_0_w7[0], +layer_0_w7[1], +layer_0_w7[2], +layer_1_w7[2], +layer_1_w8[0] +); +assign layer_1_w7[3]=layer_0_w7[3]; +compressor42 layer_1_compressor42_1( +layer_0_w8[0], +layer_0_w8[1], +layer_0_w8[2], +layer_0_w8[3], +layer_0_w8[4], +layer_1_w8[1], +layer_1_w9[0], +layer_1_w9[1] +); +assign layer_1_w8[2]=layer_0_w8[5]; +compressor42 layer_1_compressor42_2( +layer_0_w9[0], +layer_0_w9[1], +layer_0_w9[2], +layer_0_w9[3], +layer_0_w9[4], +layer_1_w9[2], +layer_1_w10[0], +layer_1_w10[1] +); +compressor42 layer_1_compressor42_3( +layer_0_w10[0], +layer_0_w10[1], +layer_0_w10[2], +layer_0_w10[3], +layer_0_w10[4], +layer_1_w10[2], +layer_1_w11[0], +layer_1_w11[1] +); +assign layer_1_w10[3]=layer_0_w10[5]; +assign layer_1_w10[4]=layer_0_w10[6]; +compressor42 layer_1_compressor42_4( +layer_0_w11[0], +layer_0_w11[1], +layer_0_w11[2], +layer_0_w11[3], +layer_0_w11[4], +layer_1_w11[2], +layer_1_w12[0], +layer_1_w12[1] +); +assign layer_1_w11[3]=layer_0_w11[5]; +compressor42 layer_1_compressor42_5( +layer_0_w12[0], +layer_0_w12[1], +layer_0_w12[2], +layer_0_w12[3], +layer_0_w12[4], +layer_1_w12[2], +layer_1_w13[0], +layer_1_w13[1] +); +full_adder layer_1_full_adder_3( +layer_0_w12[5], +layer_0_w12[6], +layer_0_w12[7], +layer_1_w12[3], +layer_1_w13[2] +); +compressor42 layer_1_compressor42_6( +layer_0_w13[0], +layer_0_w13[1], +layer_0_w13[2], +layer_0_w13[3], +layer_0_w13[4], +layer_1_w13[3], +layer_1_w14[0], +layer_1_w14[1] +); +assign layer_1_w13[4]=layer_0_w13[5]; +assign layer_1_w13[5]=layer_0_w13[6]; +compressor42 layer_1_compressor42_7( +layer_0_w14[0], +layer_0_w14[1], +layer_0_w14[2], +layer_0_w14[3], +layer_0_w14[4], +layer_1_w14[2], +layer_1_w15[0], +layer_1_w15[1] +); +full_adder layer_1_full_adder_4( +layer_0_w14[5], +layer_0_w14[6], +layer_0_w14[7], +layer_1_w14[3], +layer_1_w15[2] +); +assign layer_1_w14[4]=layer_0_w14[8]; +compressor42 layer_1_compressor42_8( +layer_0_w15[0], +layer_0_w15[1], +layer_0_w15[2], +layer_0_w15[3], +layer_0_w15[4], +layer_1_w15[3], +layer_1_w16[0], +layer_1_w16[1] +); +full_adder layer_1_full_adder_5( +layer_0_w15[5], +layer_0_w15[6], +layer_0_w15[7], +layer_1_w15[4], +layer_1_w16[2] +); +compressor42 layer_1_compressor42_9( +layer_0_w16[0], +layer_0_w16[1], +layer_0_w16[2], +layer_0_w16[3], +layer_0_w16[4], +layer_1_w16[3], +layer_1_w17[0], +layer_1_w17[1] +); +full_adder layer_1_full_adder_6( +layer_0_w16[5], +layer_0_w16[6], +layer_0_w16[7], +layer_1_w16[4], +layer_1_w17[2] +); +assign layer_1_w16[5]=layer_0_w16[8]; +compressor42 layer_1_compressor42_10( +layer_0_w17[0], +layer_0_w17[1], +layer_0_w17[2], +layer_0_w17[3], +layer_0_w17[4], +layer_1_w17[3], +layer_1_w18[0], +layer_1_w18[1] +); +full_adder layer_1_full_adder_7( +layer_0_w17[5], +layer_0_w17[6], +layer_0_w17[7], +layer_1_w17[4], +layer_1_w18[2] +); +compressor42 layer_1_compressor42_11( +layer_0_w18[0], +layer_0_w18[1], +layer_0_w18[2], +layer_0_w18[3], +layer_0_w18[4], +layer_1_w18[3], +layer_1_w19[0], +layer_1_w19[1] +); +assign layer_1_w18[4]=layer_0_w18[5]; +assign layer_1_w18[5]=layer_0_w18[6]; +compressor42 layer_1_compressor42_12( +layer_0_w19[0], +layer_0_w19[1], +layer_0_w19[2], +layer_0_w19[3], +layer_0_w19[4], +layer_1_w19[2], +layer_1_w20[0], +layer_1_w20[1] +); +assign layer_1_w19[3]=layer_0_w19[5]; +assign layer_1_w19[4]=layer_0_w19[6]; +compressor42 layer_1_compressor42_13( +layer_0_w20[0], +layer_0_w20[1], +layer_0_w20[2], +layer_0_w20[3], +layer_0_w20[4], +layer_1_w20[2], +layer_1_w21[0], +layer_1_w21[1] +); +assign layer_1_w20[3]=layer_0_w20[5]; +compressor42 layer_1_compressor42_14( +layer_0_w21[0], +layer_0_w21[1], +layer_0_w21[2], +layer_0_w21[3], +layer_0_w21[4], +layer_1_w21[2], +layer_1_w22[0], +layer_1_w22[1] +); +assign layer_1_w21[3]=layer_0_w21[5]; +compressor42 layer_1_compressor42_15( +layer_0_w22[0], +layer_0_w22[1], +layer_0_w22[2], +layer_0_w22[3], +layer_0_w22[4], +layer_1_w22[2], +layer_1_w23[0], +layer_1_w23[1] +); +compressor42 layer_1_compressor42_16( +layer_0_w23[0], +layer_0_w23[1], +layer_0_w23[2], +layer_0_w23[3], +layer_0_w23[4], +layer_1_w23[2], +layer_1_w24[0], +layer_1_w24[1] +); +full_adder layer_1_full_adder_8( +layer_0_w24[0], +layer_0_w24[1], +layer_0_w24[2], +layer_1_w24[2], +layer_1_w25[0] +); +assign layer_1_w24[3]=layer_0_w24[3]; +full_adder layer_1_full_adder_9( +layer_0_w25[0], +layer_0_w25[1], +layer_0_w25[2], +layer_1_w25[1], +layer_1_w26[0] +); +assign layer_1_w25[2]=layer_0_w25[3]; +full_adder layer_1_full_adder_10( +layer_0_w26[0], +layer_0_w26[1], +layer_0_w26[2], +layer_1_w26[1], +layer_1_w27[0] +); +full_adder layer_1_full_adder_11( +layer_0_w27[0], +layer_0_w27[1], +layer_0_w27[2], +layer_1_w27[1], +layer_1_w28[0] +); +assign layer_1_w28[1]=layer_0_w28[0]; +assign layer_1_w28[2]=layer_0_w28[1]; +assign layer_1_w29[0]=layer_0_w29[0]; +assign layer_1_w29[1]=layer_0_w29[1]; +assign layer_1_w30=layer_0_w30; +assign layer_1_w31=layer_0_w31; + +//layer 2 +wire [1:0]layer_2_w0; +wire layer_2_w1; +wire [2:0]layer_2_w2; +wire [1:0]layer_2_w3; +wire [1:0]layer_2_w4; +wire [1:0]layer_2_w5; +wire [1:0]layer_2_w6; +wire [1:0]layer_2_w7; +wire [1:0]layer_2_w8; +wire [1:0]layer_2_w9; +wire [1:0]layer_2_w10; +wire [3:0]layer_2_w11; +wire [2:0]layer_2_w12; +wire [2:0]layer_2_w13; +wire [2:0]layer_2_w14; +wire [2:0]layer_2_w15; +wire [3:0]layer_2_w16; +wire [2:0]layer_2_w17; +wire [3:0]layer_2_w18; +wire [2:0]layer_2_w19; +wire [3:0]layer_2_w20; +wire [2:0]layer_2_w21; +wire [1:0]layer_2_w22; +wire [1:0]layer_2_w23; +wire [2:0]layer_2_w24; +wire [1:0]layer_2_w25; +wire [2:0]layer_2_w26; +wire [1:0]layer_2_w27; +wire layer_2_w28; +wire [2:0]layer_2_w29; +wire layer_2_w30; +wire layer_2_w31; +assign layer_2_w0[0]=layer_1_w0[0]; +assign layer_2_w0[1]=layer_1_w0[1]; +assign layer_2_w1=layer_1_w1; +assign layer_2_w2[0]=layer_1_w2[0]; +assign layer_2_w2[1]=layer_1_w2[1]; +assign layer_2_w2[2]=layer_1_w2[2]; +assign layer_2_w3[0]=layer_1_w3[0]; +assign layer_2_w3[1]=layer_1_w3[1]; +assign layer_2_w4[0]=layer_1_w4[0]; +assign layer_2_w4[1]=layer_1_w4[1]; +assign layer_2_w5[0]=layer_1_w5[0]; +assign layer_2_w5[1]=layer_1_w5[1]; +assign layer_2_w6[0]=layer_1_w6[0]; +assign layer_2_w6[1]=layer_1_w6[1]; +full_adder layer_2_full_adder_0( +layer_1_w7[0], +layer_1_w7[1], +layer_1_w7[2], +layer_2_w7[0], +layer_2_w8[0] +); +assign layer_2_w7[1]=layer_1_w7[3]; +full_adder layer_2_full_adder_1( +layer_1_w8[0], +layer_1_w8[1], +layer_1_w8[2], +layer_2_w8[1], +layer_2_w9[0] +); +full_adder layer_2_full_adder_2( +layer_1_w9[0], +layer_1_w9[1], +layer_1_w9[2], +layer_2_w9[1], +layer_2_w10[0] +); +compressor42 layer_2_compressor42_0( +layer_1_w10[0], +layer_1_w10[1], +layer_1_w10[2], +layer_1_w10[3], +layer_1_w10[4], +layer_2_w10[1], +layer_2_w11[0], +layer_2_w11[1] +); +full_adder layer_2_full_adder_3( +layer_1_w11[0], +layer_1_w11[1], +layer_1_w11[2], +layer_2_w11[2], +layer_2_w12[0] +); +assign layer_2_w11[3]=layer_1_w11[3]; +full_adder layer_2_full_adder_4( +layer_1_w12[0], +layer_1_w12[1], +layer_1_w12[2], +layer_2_w12[1], +layer_2_w13[0] +); +assign layer_2_w12[2]=layer_1_w12[3]; +compressor42 layer_2_compressor42_1( +layer_1_w13[0], +layer_1_w13[1], +layer_1_w13[2], +layer_1_w13[3], +layer_1_w13[4], +layer_2_w13[1], +layer_2_w14[0], +layer_2_w14[1] +); +assign layer_2_w13[2]=layer_1_w13[5]; +compressor42 layer_2_compressor42_2( +layer_1_w14[0], +layer_1_w14[1], +layer_1_w14[2], +layer_1_w14[3], +layer_1_w14[4], +layer_2_w14[2], +layer_2_w15[0], +layer_2_w15[1] +); +compressor42 layer_2_compressor42_3( +layer_1_w15[0], +layer_1_w15[1], +layer_1_w15[2], +layer_1_w15[3], +layer_1_w15[4], +layer_2_w15[2], +layer_2_w16[0], +layer_2_w16[1] +); +compressor42 layer_2_compressor42_4( +layer_1_w16[0], +layer_1_w16[1], +layer_1_w16[2], +layer_1_w16[3], +layer_1_w16[4], +layer_2_w16[2], +layer_2_w17[0], +layer_2_w17[1] +); +assign layer_2_w16[3]=layer_1_w16[5]; +compressor42 layer_2_compressor42_5( +layer_1_w17[0], +layer_1_w17[1], +layer_1_w17[2], +layer_1_w17[3], +layer_1_w17[4], +layer_2_w17[2], +layer_2_w18[0], +layer_2_w18[1] +); +compressor42 layer_2_compressor42_6( +layer_1_w18[0], +layer_1_w18[1], +layer_1_w18[2], +layer_1_w18[3], +layer_1_w18[4], +layer_2_w18[2], +layer_2_w19[0], +layer_2_w19[1] +); +assign layer_2_w18[3]=layer_1_w18[5]; +compressor42 layer_2_compressor42_7( +layer_1_w19[0], +layer_1_w19[1], +layer_1_w19[2], +layer_1_w19[3], +layer_1_w19[4], +layer_2_w19[2], +layer_2_w20[0], +layer_2_w20[1] +); +full_adder layer_2_full_adder_5( +layer_1_w20[0], +layer_1_w20[1], +layer_1_w20[2], +layer_2_w20[2], +layer_2_w21[0] +); +assign layer_2_w20[3]=layer_1_w20[3]; +full_adder layer_2_full_adder_6( +layer_1_w21[0], +layer_1_w21[1], +layer_1_w21[2], +layer_2_w21[1], +layer_2_w22[0] +); +assign layer_2_w21[2]=layer_1_w21[3]; +full_adder layer_2_full_adder_7( +layer_1_w22[0], +layer_1_w22[1], +layer_1_w22[2], +layer_2_w22[1], +layer_2_w23[0] +); +full_adder layer_2_full_adder_8( +layer_1_w23[0], +layer_1_w23[1], +layer_1_w23[2], +layer_2_w23[1], +layer_2_w24[0] +); +full_adder layer_2_full_adder_9( +layer_1_w24[0], +layer_1_w24[1], +layer_1_w24[2], +layer_2_w24[1], +layer_2_w25[0] +); +assign layer_2_w24[2]=layer_1_w24[3]; +full_adder layer_2_full_adder_10( +layer_1_w25[0], +layer_1_w25[1], +layer_1_w25[2], +layer_2_w25[1], +layer_2_w26[0] +); +assign layer_2_w26[1]=layer_1_w26[0]; +assign layer_2_w26[2]=layer_1_w26[1]; +assign layer_2_w27[0]=layer_1_w27[0]; +assign layer_2_w27[1]=layer_1_w27[1]; +full_adder layer_2_full_adder_11( +layer_1_w28[0], +layer_1_w28[1], +layer_1_w28[2], +layer_2_w28, +layer_2_w29[0] +); +assign layer_2_w29[1]=layer_1_w29[0]; +assign layer_2_w29[2]=layer_1_w29[1]; +assign layer_2_w30=layer_1_w30; +assign layer_2_w31=layer_1_w31; + + +///////////////////////////////////////////////////////stage 1/////////////////////////////////////////////////////// +reg [1:0]reg_layer_2_w0; +reg reg_layer_2_w1; +reg [2:0]reg_layer_2_w2; +reg [1:0]reg_layer_2_w3; +reg [1:0]reg_layer_2_w4; +reg [1:0]reg_layer_2_w5; +reg [1:0]reg_layer_2_w6; +reg [1:0]reg_layer_2_w7; +reg [1:0]reg_layer_2_w8; +reg [1:0]reg_layer_2_w9; +reg [1:0]reg_layer_2_w10; +reg [3:0]reg_layer_2_w11; +reg [2:0]reg_layer_2_w12; +reg [2:0]reg_layer_2_w13; +reg [2:0]reg_layer_2_w14; +reg [2:0]reg_layer_2_w15; +reg [3:0]reg_layer_2_w16; +reg [2:0]reg_layer_2_w17; +reg [3:0]reg_layer_2_w18; +reg [2:0]reg_layer_2_w19; +reg [3:0]reg_layer_2_w20; +reg [2:0]reg_layer_2_w21; +reg [1:0]reg_layer_2_w22; +reg [1:0]reg_layer_2_w23; +reg [2:0]reg_layer_2_w24; +reg [1:0]reg_layer_2_w25; +reg [2:0]reg_layer_2_w26; +reg [1:0]reg_layer_2_w27; +reg reg_layer_2_w28; +reg [2:0]reg_layer_2_w29; +reg reg_layer_2_w30; +reg reg_layer_2_w31; +reg stage_1_ready; +assign o_ready=stage_1_ready; + +always @(posedge i_clk or negedge i_rst)begin + if(!i_rst)begin + stage_1_ready<=0; + reg_layer_2_w0<=0; + reg_layer_2_w1<=0; + reg_layer_2_w2<=0; + reg_layer_2_w3<=0; + reg_layer_2_w4<=0; + reg_layer_2_w5<=0; + reg_layer_2_w6<=0; + reg_layer_2_w7<=0; + reg_layer_2_w8<=0; + reg_layer_2_w9<=0; + reg_layer_2_w10<=0; + reg_layer_2_w11<=0; + reg_layer_2_w12<=0; + reg_layer_2_w13<=0; + reg_layer_2_w14<=0; + reg_layer_2_w15<=0; + reg_layer_2_w16<=0; + reg_layer_2_w17<=0; + reg_layer_2_w18<=0; + reg_layer_2_w19<=0; + reg_layer_2_w20<=0; + reg_layer_2_w21<=0; + reg_layer_2_w22<=0; + reg_layer_2_w23<=0; + reg_layer_2_w24<=0; + reg_layer_2_w25<=0; + reg_layer_2_w26<=0; + reg_layer_2_w27<=0; + reg_layer_2_w28<=0; + reg_layer_2_w29<=0; + reg_layer_2_w30<=0; + reg_layer_2_w31<=0; + end + else begin + if(stage_0_ready)begin + reg_layer_2_w0<=layer_2_w0; + reg_layer_2_w1<=layer_2_w1; + reg_layer_2_w2<=layer_2_w2; + reg_layer_2_w3<=layer_2_w3; + reg_layer_2_w4<=layer_2_w4; + reg_layer_2_w5<=layer_2_w5; + reg_layer_2_w6<=layer_2_w6; + reg_layer_2_w7<=layer_2_w7; + reg_layer_2_w8<=layer_2_w8; + reg_layer_2_w9<=layer_2_w9; + reg_layer_2_w10<=layer_2_w10; + reg_layer_2_w11<=layer_2_w11; + reg_layer_2_w12<=layer_2_w12; + reg_layer_2_w13<=layer_2_w13; + reg_layer_2_w14<=layer_2_w14; + reg_layer_2_w15<=layer_2_w15; + reg_layer_2_w16<=layer_2_w16; + reg_layer_2_w17<=layer_2_w17; + reg_layer_2_w18<=layer_2_w18; + reg_layer_2_w19<=layer_2_w19; + reg_layer_2_w20<=layer_2_w20; + reg_layer_2_w21<=layer_2_w21; + reg_layer_2_w22<=layer_2_w22; + reg_layer_2_w23<=layer_2_w23; + reg_layer_2_w24<=layer_2_w24; + reg_layer_2_w25<=layer_2_w25; + reg_layer_2_w26<=layer_2_w26; + reg_layer_2_w27<=layer_2_w27; + reg_layer_2_w28<=layer_2_w28; + reg_layer_2_w29<=layer_2_w29; + reg_layer_2_w30<=layer_2_w30; + reg_layer_2_w31<=layer_2_w31; + end + stage_1_ready<=stage_0_ready; + end +end + +//layer 3 +wire layer_3_w0[1:0]; +wire layer_3_w1; +wire layer_3_w2[2:0]; +wire layer_3_w3[1:0]; +wire layer_3_w4[1:0]; +wire layer_3_w5[1:0]; +wire layer_3_w6[1:0]; +wire layer_3_w7[1:0]; +wire layer_3_w8[1:0]; +wire layer_3_w9[1:0]; +wire layer_3_w10[1:0]; +wire layer_3_w11[1:0]; +wire layer_3_w12[1:0]; +wire layer_3_w13[1:0]; +wire layer_3_w14[1:0]; +wire layer_3_w15[1:0]; +wire layer_3_w16[2:0]; +wire layer_3_w17[1:0]; +wire layer_3_w18[2:0]; +wire layer_3_w19[1:0]; +wire layer_3_w20[2:0]; +wire layer_3_w21[1:0]; +wire layer_3_w22[2:0]; +wire layer_3_w23[1:0]; +wire layer_3_w24; +wire layer_3_w25[2:0]; +wire layer_3_w26; +wire layer_3_w27[2:0]; +wire layer_3_w28; +wire layer_3_w29; +wire layer_3_w30[1:0]; +wire layer_3_w31; +assign layer_3_w0[0]=reg_layer_2_w0[0]; +assign layer_3_w0[1]=reg_layer_2_w0[1]; +assign layer_3_w1=reg_layer_2_w1; +assign layer_3_w2[0]=reg_layer_2_w2[0]; +assign layer_3_w2[1]=reg_layer_2_w2[1]; +assign layer_3_w2[2]=reg_layer_2_w2[2]; +assign layer_3_w3[0]=reg_layer_2_w3[0]; +assign layer_3_w3[1]=reg_layer_2_w3[1]; +assign layer_3_w4[0]=reg_layer_2_w4[0]; +assign layer_3_w4[1]=reg_layer_2_w4[1]; +assign layer_3_w5[0]=reg_layer_2_w5[0]; +assign layer_3_w5[1]=reg_layer_2_w5[1]; +assign layer_3_w6[0]=reg_layer_2_w6[0]; +assign layer_3_w6[1]=reg_layer_2_w6[1]; +assign layer_3_w7[0]=reg_layer_2_w7[0]; +assign layer_3_w7[1]=reg_layer_2_w7[1]; +assign layer_3_w8[0]=reg_layer_2_w8[0]; +assign layer_3_w8[1]=reg_layer_2_w8[1]; +assign layer_3_w9[0]=reg_layer_2_w9[0]; +assign layer_3_w9[1]=reg_layer_2_w9[1]; +assign layer_3_w10[0]=reg_layer_2_w10[0]; +assign layer_3_w10[1]=reg_layer_2_w10[1]; +full_adder layer_3_full_adder_0( +reg_layer_2_w11[0], +reg_layer_2_w11[1], +reg_layer_2_w11[2], +layer_3_w11[0], +layer_3_w12[0] +); +assign layer_3_w11[1]=reg_layer_2_w11[3]; +full_adder layer_3_full_adder_1( +reg_layer_2_w12[0], +reg_layer_2_w12[1], +reg_layer_2_w12[2], +layer_3_w12[1], +layer_3_w13[0] +); +full_adder layer_3_full_adder_2( +reg_layer_2_w13[0], +reg_layer_2_w13[1], +reg_layer_2_w13[2], +layer_3_w13[1], +layer_3_w14[0] +); +full_adder layer_3_full_adder_3( +reg_layer_2_w14[0], +reg_layer_2_w14[1], +reg_layer_2_w14[2], +layer_3_w14[1], +layer_3_w15[0] +); +full_adder layer_3_full_adder_4( +reg_layer_2_w15[0], +reg_layer_2_w15[1], +reg_layer_2_w15[2], +layer_3_w15[1], +layer_3_w16[0] +); +full_adder layer_3_full_adder_5( +reg_layer_2_w16[0], +reg_layer_2_w16[1], +reg_layer_2_w16[2], +layer_3_w16[1], +layer_3_w17[0] +); +assign layer_3_w16[2]=reg_layer_2_w16[3]; +full_adder layer_3_full_adder_6( +reg_layer_2_w17[0], +reg_layer_2_w17[1], +reg_layer_2_w17[2], +layer_3_w17[1], +layer_3_w18[0] +); +full_adder layer_3_full_adder_7( +reg_layer_2_w18[0], +reg_layer_2_w18[1], +reg_layer_2_w18[2], +layer_3_w18[1], +layer_3_w19[0] +); +assign layer_3_w18[2]=reg_layer_2_w18[3]; +full_adder layer_3_full_adder_8( +reg_layer_2_w19[0], +reg_layer_2_w19[1], +reg_layer_2_w19[2], +layer_3_w19[1], +layer_3_w20[0] +); +full_adder layer_3_full_adder_9( +reg_layer_2_w20[0], +reg_layer_2_w20[1], +reg_layer_2_w20[2], +layer_3_w20[1], +layer_3_w21[0] +); +assign layer_3_w20[2]=reg_layer_2_w20[3]; +full_adder layer_3_full_adder_10( +reg_layer_2_w21[0], +reg_layer_2_w21[1], +reg_layer_2_w21[2], +layer_3_w21[1], +layer_3_w22[0] +); +assign layer_3_w22[1]=reg_layer_2_w22[0]; +assign layer_3_w22[2]=reg_layer_2_w22[1]; +assign layer_3_w23[0]=reg_layer_2_w23[0]; +assign layer_3_w23[1]=reg_layer_2_w23[1]; +full_adder layer_3_full_adder_11( +reg_layer_2_w24[0], +reg_layer_2_w24[1], +reg_layer_2_w24[2], +layer_3_w24, +layer_3_w25[0] +); +assign layer_3_w25[1]=reg_layer_2_w25[0]; +assign layer_3_w25[2]=reg_layer_2_w25[1]; +full_adder layer_3_full_adder_12( +reg_layer_2_w26[0], +reg_layer_2_w26[1], +reg_layer_2_w26[2], +layer_3_w26, +layer_3_w27[0] +); +assign layer_3_w27[1]=reg_layer_2_w27[0]; +assign layer_3_w27[2]=reg_layer_2_w27[1]; +assign layer_3_w28=reg_layer_2_w28; +full_adder layer_3_full_adder_13( +reg_layer_2_w29[0], +reg_layer_2_w29[1], +reg_layer_2_w29[2], +layer_3_w29, +layer_3_w30[0] +); +assign layer_3_w30[1]=reg_layer_2_w30; +assign layer_3_w31=reg_layer_2_w31; + +//layer 4 +wire layer_4_w0[1:0]; +wire layer_4_w1; +wire layer_4_w2; +wire layer_4_w3[1:0]; +wire layer_4_w4[1:0]; +wire layer_4_w5[1:0]; +wire layer_4_w6[1:0]; +wire layer_4_w7[1:0]; +wire layer_4_w8[1:0]; +wire layer_4_w9[1:0]; +wire layer_4_w10[1:0]; +wire layer_4_w11[1:0]; +wire layer_4_w12[1:0]; +wire layer_4_w13[1:0]; +wire layer_4_w14[1:0]; +wire layer_4_w15[1:0]; +wire layer_4_w16[1:0]; +wire layer_4_w17[1:0]; +wire layer_4_w18[1:0]; +wire layer_4_w19[1:0]; +wire layer_4_w20[1:0]; +wire layer_4_w21[1:0]; +wire layer_4_w22[1:0]; +wire layer_4_w23[1:0]; +wire layer_4_w24[1:0]; +wire layer_4_w25; +wire layer_4_w26[1:0]; +wire layer_4_w27; +wire layer_4_w28[1:0]; +wire layer_4_w29; +wire layer_4_w30[1:0]; +wire layer_4_w31; +assign layer_4_w0[0]=layer_3_w0[0]; +assign layer_4_w0[1]=layer_3_w0[1]; +assign layer_4_w1=layer_3_w1; +full_adder layer_4_full_adder_0( +layer_3_w2[0], +layer_3_w2[1], +layer_3_w2[2], +layer_4_w2, +layer_4_w3[0] +); +half_adder layer_4_half_adder_0( +layer_3_w3[0], +layer_3_w3[1], +layer_4_w3[1], +layer_4_w4[0] +); +half_adder layer_4_half_adder_1( +layer_3_w4[0], +layer_3_w4[1], +layer_4_w4[1], +layer_4_w5[0] +); +half_adder layer_4_half_adder_2( +layer_3_w5[0], +layer_3_w5[1], +layer_4_w5[1], +layer_4_w6[0] +); +half_adder layer_4_half_adder_3( +layer_3_w6[0], +layer_3_w6[1], +layer_4_w6[1], +layer_4_w7[0] +); +half_adder layer_4_half_adder_4( +layer_3_w7[0], +layer_3_w7[1], +layer_4_w7[1], +layer_4_w8[0] +); +half_adder layer_4_half_adder_5( +layer_3_w8[0], +layer_3_w8[1], +layer_4_w8[1], +layer_4_w9[0] +); +half_adder layer_4_half_adder_6( +layer_3_w9[0], +layer_3_w9[1], +layer_4_w9[1], +layer_4_w10[0] +); +half_adder layer_4_half_adder_7( +layer_3_w10[0], +layer_3_w10[1], +layer_4_w10[1], +layer_4_w11[0] +); +half_adder layer_4_half_adder_8( +layer_3_w11[0], +layer_3_w11[1], +layer_4_w11[1], +layer_4_w12[0] +); +half_adder layer_4_half_adder_9( +layer_3_w12[0], +layer_3_w12[1], +layer_4_w12[1], +layer_4_w13[0] +); +half_adder layer_4_half_adder_10( +layer_3_w13[0], +layer_3_w13[1], +layer_4_w13[1], +layer_4_w14[0] +); +half_adder layer_4_half_adder_11( +layer_3_w14[0], +layer_3_w14[1], +layer_4_w14[1], +layer_4_w15[0] +); +half_adder layer_4_half_adder_12( +layer_3_w15[0], +layer_3_w15[1], +layer_4_w15[1], +layer_4_w16[0] +); +full_adder layer_4_full_adder_1( +layer_3_w16[0], +layer_3_w16[1], +layer_3_w16[2], +layer_4_w16[1], +layer_4_w17[0] +); +half_adder layer_4_half_adder_13( +layer_3_w17[0], +layer_3_w17[1], +layer_4_w17[1], +layer_4_w18[0] +); +full_adder layer_4_full_adder_2( +layer_3_w18[0], +layer_3_w18[1], +layer_3_w18[2], +layer_4_w18[1], +layer_4_w19[0] +); +half_adder layer_4_half_adder_14( +layer_3_w19[0], +layer_3_w19[1], +layer_4_w19[1], +layer_4_w20[0] +); +full_adder layer_4_full_adder_3( +layer_3_w20[0], +layer_3_w20[1], +layer_3_w20[2], +layer_4_w20[1], +layer_4_w21[0] +); +half_adder layer_4_half_adder_15( +layer_3_w21[0], +layer_3_w21[1], +layer_4_w21[1], +layer_4_w22[0] +); +full_adder layer_4_full_adder_4( +layer_3_w22[0], +layer_3_w22[1], +layer_3_w22[2], +layer_4_w22[1], +layer_4_w23[0] +); +half_adder layer_4_half_adder_16( +layer_3_w23[0], +layer_3_w23[1], +layer_4_w23[1], +layer_4_w24[0] +); +assign layer_4_w24[1]=layer_3_w24; +full_adder layer_4_full_adder_5( +layer_3_w25[0], +layer_3_w25[1], +layer_3_w25[2], +layer_4_w25, +layer_4_w26[0] +); +assign layer_4_w26[1]=layer_3_w26; +full_adder layer_4_full_adder_6( +layer_3_w27[0], +layer_3_w27[1], +layer_3_w27[2], +layer_4_w27, +layer_4_w28[0] +); +assign layer_4_w28[1]=layer_3_w28; +assign layer_4_w29=layer_3_w29; +assign layer_4_w30[0]=layer_3_w30[0]; +assign layer_4_w30[1]=layer_3_w30[1]; +assign layer_4_w31=layer_3_w31; + +//group reduction results into 2 numbers +wire [31:0]A,B; +assign A[0]=layer_4_w0[0]; +assign B[0]=layer_4_w0[1]; +assign A[1]=layer_4_w1; +assign B[1]=0; +assign A[2]=layer_4_w2; +assign B[2]=0; +assign A[3]=layer_4_w3[0]; +assign B[3]=layer_4_w3[1]; +assign A[4]=layer_4_w4[0]; +assign B[4]=layer_4_w4[1]; +assign A[5]=layer_4_w5[0]; +assign B[5]=layer_4_w5[1]; +assign A[6]=layer_4_w6[0]; +assign B[6]=layer_4_w6[1]; +assign A[7]=layer_4_w7[0]; +assign B[7]=layer_4_w7[1]; +assign A[8]=layer_4_w8[0]; +assign B[8]=layer_4_w8[1]; +assign A[9]=layer_4_w9[0]; +assign B[9]=layer_4_w9[1]; +assign A[10]=layer_4_w10[0]; +assign B[10]=layer_4_w10[1]; +assign A[11]=layer_4_w11[0]; +assign B[11]=layer_4_w11[1]; +assign A[12]=layer_4_w12[0]; +assign B[12]=layer_4_w12[1]; +assign A[13]=layer_4_w13[0]; +assign B[13]=layer_4_w13[1]; +assign A[14]=layer_4_w14[0]; +assign B[14]=layer_4_w14[1]; +assign A[15]=layer_4_w15[0]; +assign B[15]=layer_4_w15[1]; +assign A[16]=layer_4_w16[0]; +assign B[16]=layer_4_w16[1]; +assign A[17]=layer_4_w17[0]; +assign B[17]=layer_4_w17[1]; +assign A[18]=layer_4_w18[0]; +assign B[18]=layer_4_w18[1]; +assign A[19]=layer_4_w19[0]; +assign B[19]=layer_4_w19[1]; +assign A[20]=layer_4_w20[0]; +assign B[20]=layer_4_w20[1]; +assign A[21]=layer_4_w21[0]; +assign B[21]=layer_4_w21[1]; +assign A[22]=layer_4_w22[0]; +assign B[22]=layer_4_w22[1]; +assign A[23]=layer_4_w23[0]; +assign B[23]=layer_4_w23[1]; +assign A[24]=layer_4_w24[0]; +assign B[24]=layer_4_w24[1]; +assign A[25]=layer_4_w25; +assign B[25]=0; +assign A[26]=layer_4_w26[0]; +assign B[26]=layer_4_w26[1]; +assign A[27]=layer_4_w27; +assign B[27]=0; +assign A[28]=layer_4_w28[0]; +assign B[28]=layer_4_w28[1]; +assign A[29]=layer_4_w29; +assign B[29]=0; +assign A[30]=layer_4_w30[0]; +assign B[30]=layer_4_w30[1]; +assign A[31]=layer_4_w31; +assign B[31]=0; + +wire carry; +adder_32bit adder_32bit( +A, +B, +1'b0, +o_product, +carry +); + + +endmodule diff --git a/designs/encrypted_ip/pid_simple/CLA_fixed.v b/designs/encrypted_ip/pid_simple/CLA_fixed.v new file mode 100644 index 000000000..bd68e0204 --- /dev/null +++ b/designs/encrypted_ip/pid_simple/CLA_fixed.v @@ -0,0 +1,259 @@ +/*Carry look-ahead adder +Author: Zhu Xu +Email: m99a1@yahoo.cn +*/ + +module operator_A( +input A, +input B, +output P, +output G +); + +assign P=A^B; +assign G=A&B; + +endmodule + +module operator_B( +input P,G,P1,G1, +output Po,Go +); + +assign Po=P&P1; +assign Go=G|(P&G1); + +endmodule + +module operator_C( +input P,G,G1, +output Go +); + +assign Go=G|(P&G1); + +endmodule + + +/* 32-bit prefix-2 Han-Carlson adder +stage 0: Number of Generation=32, NP=32, NOA=32, NOB=0, NOC=0. +stage 1: NG=16, NP=15, NOA=0, NOB=15, NOC=1. +stage 2: NG=16, NP=14, NOA=0, NOB=14, NOC=1. +stage 3: NG=16, NP=12, NOA=0, NOB=12, NOC=2. +stage 4: NG=16, NP=8, NOA=0, NOB=8, NOC=4. +stage 5: NG=16, NP=0, NOA=0, NOB=0, NOC=8. +stage 6; NG=32, NP=0, NOA=0, NOB=0, NOC=15. +*/ +module adder_32bit( +input [31:0]i_a,i_b, +input i_c, +output [31:0]o_s, +output o_c +); + +//stage 0 +wire [31:0]P0,G0; +operator_A operator_A_0(i_a[0],i_b[0],P0[0],G0[0]); +operator_A operator_A_1(i_a[1],i_b[1],P0[1],G0[1]); +operator_A operator_A_2(i_a[2],i_b[2],P0[2],G0[2]); +operator_A operator_A_3(i_a[3],i_b[3],P0[3],G0[3]); +operator_A operator_A_4(i_a[4],i_b[4],P0[4],G0[4]); +operator_A operator_A_5(i_a[5],i_b[5],P0[5],G0[5]); +operator_A operator_A_6(i_a[6],i_b[6],P0[6],G0[6]); +operator_A operator_A_7(i_a[7],i_b[7],P0[7],G0[7]); +operator_A operator_A_8(i_a[8],i_b[8],P0[8],G0[8]); +operator_A operator_A_9(i_a[9],i_b[9],P0[9],G0[9]); +operator_A operator_A_10(i_a[10],i_b[10],P0[10],G0[10]); +operator_A operator_A_11(i_a[11],i_b[11],P0[11],G0[11]); +operator_A operator_A_12(i_a[12],i_b[12],P0[12],G0[12]); +operator_A operator_A_13(i_a[13],i_b[13],P0[13],G0[13]); +operator_A operator_A_14(i_a[14],i_b[14],P0[14],G0[14]); +operator_A operator_A_15(i_a[15],i_b[15],P0[15],G0[15]); +operator_A operator_A_16(i_a[16],i_b[16],P0[16],G0[16]); +operator_A operator_A_17(i_a[17],i_b[17],P0[17],G0[17]); +operator_A operator_A_18(i_a[18],i_b[18],P0[18],G0[18]); +operator_A operator_A_19(i_a[19],i_b[19],P0[19],G0[19]); +operator_A operator_A_20(i_a[20],i_b[20],P0[20],G0[20]); +operator_A operator_A_21(i_a[21],i_b[21],P0[21],G0[21]); +operator_A operator_A_22(i_a[22],i_b[22],P0[22],G0[22]); +operator_A operator_A_23(i_a[23],i_b[23],P0[23],G0[23]); +operator_A operator_A_24(i_a[24],i_b[24],P0[24],G0[24]); +operator_A operator_A_25(i_a[25],i_b[25],P0[25],G0[25]); +operator_A operator_A_26(i_a[26],i_b[26],P0[26],G0[26]); +operator_A operator_A_27(i_a[27],i_b[27],P0[27],G0[27]); +operator_A operator_A_28(i_a[28],i_b[28],P0[28],G0[28]); +operator_A operator_A_29(i_a[29],i_b[29],P0[29],G0[29]); +operator_A operator_A_30(i_a[30],i_b[30],P0[30],G0[30]); +operator_A operator_A_31(i_a[31],i_b[31],P0[31],G0[31]); + +//stage 1 +wire [15:0]G1; +wire [15:1]P1; +operator_C operator_C_stage_1_0(P0[0],G0[0],i_c,G1[0]); +operator_B operator_B_stage_1_1(P0[2],G0[2],P0[1],G0[1],P1[1],G1[1]); +operator_B operator_B_stage_1_2(P0[4],G0[4],P0[3],G0[3],P1[2],G1[2]); +operator_B operator_B_stage_1_3(P0[6],G0[6],P0[5],G0[5],P1[3],G1[3]); +operator_B operator_B_stage_1_4(P0[8],G0[8],P0[7],G0[7],P1[4],G1[4]); +operator_B operator_B_stage_1_5(P0[10],G0[10],P0[9],G0[9],P1[5],G1[5]); +operator_B operator_B_stage_1_6(P0[12],G0[12],P0[11],G0[11],P1[6],G1[6]); +operator_B operator_B_stage_1_7(P0[14],G0[14],P0[13],G0[13],P1[7],G1[7]); +operator_B operator_B_stage_1_8(P0[16],G0[16],P0[15],G0[15],P1[8],G1[8]); +operator_B operator_B_stage_1_9(P0[18],G0[18],P0[17],G0[17],P1[9],G1[9]); +operator_B operator_B_stage_1_10(P0[20],G0[20],P0[19],G0[19],P1[10],G1[10]); +operator_B operator_B_stage_1_11(P0[22],G0[22],P0[21],G0[21],P1[11],G1[11]); +operator_B operator_B_stage_1_12(P0[24],G0[24],P0[23],G0[23],P1[12],G1[12]); +operator_B operator_B_stage_1_13(P0[26],G0[26],P0[25],G0[25],P1[13],G1[13]); +operator_B operator_B_stage_1_14(P0[28],G0[28],P0[27],G0[27],P1[14],G1[14]); +operator_B operator_B_stage_1_15(P0[30],G0[30],P0[29],G0[29],P1[15],G1[15]); + + + +//stage 2 +wire [15:0]G2; +wire [15:2]P2; +assign G2[0]=G1[0]; +operator_C operator_C_stage_2_1(P1[1],G1[1],G1[0],G2[1]); +operator_B operator_B_stage_2_2(P1[2], G1[2],P1[1],G1[1],P2[2],G2[2]); +operator_B operator_B_stage_2_3(P1[3], G1[3],P1[2],G1[2],P2[3],G2[3]); +operator_B operator_B_stage_2_4(P1[4], G1[4],P1[3],G1[3],P2[4],G2[4]); +operator_B operator_B_stage_2_5(P1[5], G1[5],P1[4],G1[4],P2[5],G2[5]); +operator_B operator_B_stage_2_6(P1[6], G1[6],P1[5],G1[5],P2[6],G2[6]); +operator_B operator_B_stage_2_7(P1[7], G1[7],P1[6],G1[6],P2[7],G2[7]); +operator_B operator_B_stage_2_8(P1[8], G1[8],P1[7],G1[7],P2[8],G2[8]); +operator_B operator_B_stage_2_9(P1[9], G1[9],P1[8],G1[8],P2[9],G2[9]); +operator_B operator_B_stage_2_10(P1[10], G1[10],P1[9],G1[9],P2[10],G2[10]); +operator_B operator_B_stage_2_11(P1[11], G1[11],P1[10],G1[10],P2[11],G2[11]); +operator_B operator_B_stage_2_12(P1[12], G1[12],P1[11],G1[11],P2[12],G2[12]); +operator_B operator_B_stage_2_13(P1[13], G1[13],P1[12],G1[12],P2[13],G2[13]); +operator_B operator_B_stage_2_14(P1[14], G1[14],P1[13],G1[13],P2[14],G2[14]); +operator_B operator_B_stage_2_15(P1[15], G1[15],P1[14],G1[14],P2[15],G2[15]); + +//stage 3 +wire [15:0]G3; +wire [15:4]P3; +assign G3[0]=G2[0]; +assign G3[1]=G2[1]; +operator_C operator_C_stage_3_2(P2[2],G2[2],G2[0],G3[2]); +operator_C operator_C_stage_3_3(P2[3],G2[3],G2[1],G3[3]); +operator_B operator_B_stage_3_4(P2[4], G2[4],P2[2],G2[2],P3[4],G3[4]); +operator_B operator_B_stage_3_5(P2[5], G2[5],P2[3],G2[3],P3[5],G3[5]); +operator_B operator_B_stage_3_6(P2[6], G2[6],P2[4],G2[4],P3[6],G3[6]); +operator_B operator_B_stage_3_7(P2[7], G2[7],P2[5],G2[5],P3[7],G3[7]); +operator_B operator_B_stage_3_8(P2[8], G2[8],P2[6],G2[6],P3[8],G3[8]); +operator_B operator_B_stage_3_9(P2[9], G2[9],P2[7],G2[7],P3[9],G3[9]); +operator_B operator_B_stage_3_10(P2[10], G2[10],P2[8],G2[8],P3[10],G3[10]); +operator_B operator_B_stage_3_11(P2[11], G2[11],P2[9],G2[9],P3[11],G3[11]); +operator_B operator_B_stage_3_12(P2[12], G2[12],P2[10],G2[10],P3[12],G3[12]); +operator_B operator_B_stage_3_13(P2[13], G2[13],P2[11],G2[11],P3[13],G3[13]); +operator_B operator_B_stage_3_14(P2[14], G2[14],P2[12],G2[12],P3[14],G3[14]); +operator_B operator_B_stage_3_15(P2[15], G2[15],P2[13],G2[13],P3[15],G3[15]); + +//stage 4 +wire [15:0]G4; +wire [15:8]P4; +assign G4[0]=G3[0]; +assign G4[1]=G3[1]; +assign G4[2]=G3[2]; +assign G4[3]=G3[3]; +operator_C operator_C_stage_4_4(P3[4],G3[4],G3[0],G4[4]); +operator_C operator_C_stage_4_5(P3[5],G3[5],G3[1],G4[5]); +operator_C operator_C_stage_4_6(P3[6],G3[6],G3[2],G4[6]); +operator_C operator_C_stage_4_7(P3[7],G3[7],G3[3],G4[7]); +operator_B operator_B_stage_4_8(P3[8], G3[8],P3[4],G3[4],P4[8],G4[8]); +operator_B operator_B_stage_4_9(P3[9], G3[9],P3[5],G3[5],P4[9],G4[9]); +operator_B operator_B_stage_4_10(P3[10], G3[10],P3[6],G3[6],P4[10],G4[10]); +operator_B operator_B_stage_4_11(P3[11], G3[11],P3[7],G3[7],P4[11],G4[11]); +operator_B operator_B_stage_4_12(P3[12], G3[12],P3[8],G3[8],P4[12],G4[12]); +operator_B operator_B_stage_4_13(P3[13], G3[13],P3[9],G3[9],P4[13],G4[13]); +operator_B operator_B_stage_4_14(P3[14], G3[14],P3[10],G3[10],P4[14],G4[14]); +operator_B operator_B_stage_4_15(P3[15], G3[15],P3[11],G3[11],P4[15],G4[15]); + +//stage 5 +wire [15:0]G5; +assign G5[0]=G4[0]; +assign G5[1]=G4[1]; +assign G5[2]=G4[2]; +assign G5[3]=G4[3]; +assign G5[4]=G4[4]; +assign G5[5]=G4[5]; +assign G5[6]=G4[6]; +assign G5[7]=G4[7]; +operator_C operator_C_stage_5_8(P4[8],G4[8],G4[0],G5[8]); +operator_C operator_C_stage_5_9(P4[9],G4[9],G4[1],G5[9]); +operator_C operator_C_stage_5_10(P4[10],G4[10],G4[2],G5[10]); +operator_C operator_C_stage_5_11(P4[11],G4[11],G4[3],G5[11]); +operator_C operator_C_stage_5_12(P4[12],G4[12],G4[4],G5[12]); +operator_C operator_C_stage_5_13(P4[13],G4[13],G4[5],G5[13]); +operator_C operator_C_stage_5_14(P4[14],G4[14],G4[6],G5[14]); +operator_C operator_C_stage_5_15(P4[15],G4[15],G4[7],G5[15]); + +//stage 6 +wire [31:0]G6; +assign G6[0]=G5[0]; +assign G6[2]=G5[1]; +assign G6[4]=G5[2]; +assign G6[6]=G5[3]; +assign G6[8]=G5[4]; +assign G6[10]=G5[5]; +assign G6[12]=G5[6]; +assign G6[14]=G5[7]; +assign G6[16]=G5[8]; +assign G6[18]=G5[9]; +assign G6[20]=G5[10]; +assign G6[22]=G5[11]; +assign G6[24]=G5[12]; +assign G6[26]=G5[13]; +assign G6[28]=G5[14]; +assign G6[30]=G5[15]; +operator_C operator_C_stage_6_0(P0[1],G0[1],G5[0],G6[1]); +operator_C operator_C_stage_6_1(P0[3],G0[3],G5[1],G6[3]); +operator_C operator_C_stage_6_2(P0[5],G0[5],G5[2],G6[5]); +operator_C operator_C_stage_6_3(P0[7],G0[7],G5[3],G6[7]); +operator_C operator_C_stage_6_4(P0[9],G0[9],G5[4],G6[9]); +operator_C operator_C_stage_6_5(P0[11],G0[11],G5[5],G6[11]); +operator_C operator_C_stage_6_6(P0[13],G0[13],G5[6],G6[13]); +operator_C operator_C_stage_6_7(P0[15],G0[15],G5[7],G6[15]); +operator_C operator_C_stage_6_8(P0[17],G0[17],G5[8],G6[17]); +operator_C operator_C_stage_6_9(P0[19],G0[19],G5[9],G6[19]); +operator_C operator_C_stage_6_10(P0[21],G0[21],G5[10],G6[21]); +operator_C operator_C_stage_6_11(P0[23],G0[23],G5[11],G6[23]); +operator_C operator_C_stage_6_12(P0[25],G0[25],G5[12],G6[25]); +operator_C operator_C_stage_6_13(P0[27],G0[27],G5[13],G6[27]); +operator_C operator_C_stage_6_14(P0[29],G0[29],G5[14],G6[29]); +operator_C operator_C_stage_6_15(P0[31],G0[31],G5[15],G6[31]); + +assign o_s[0]=P0[0]^i_c; +assign o_s[1]=P0[1]^G6[0]; +assign o_s[2]=P0[2]^G6[1]; +assign o_s[3]=P0[3]^G6[2]; +assign o_s[4]=P0[4]^G6[3]; +assign o_s[5]=P0[5]^G6[4]; +assign o_s[6]=P0[6]^G6[5]; +assign o_s[7]=P0[7]^G6[6]; +assign o_s[8]=P0[8]^G6[7]; +assign o_s[9]=P0[9]^G6[8]; +assign o_s[10]=P0[10]^G6[9]; +assign o_s[11]=P0[11]^G6[10]; +assign o_s[12]=P0[12]^G6[11]; +assign o_s[13]=P0[13]^G6[12]; +assign o_s[14]=P0[14]^G6[13]; +assign o_s[15]=P0[15]^G6[14]; +assign o_s[16]=P0[16]^G6[15]; +assign o_s[17]=P0[17]^G6[16]; +assign o_s[18]=P0[18]^G6[17]; +assign o_s[19]=P0[19]^G6[18]; +assign o_s[20]=P0[20]^G6[19]; +assign o_s[21]=P0[21]^G6[20]; +assign o_s[22]=P0[22]^G6[21]; +assign o_s[23]=P0[23]^G6[22]; +assign o_s[24]=P0[24]^G6[23]; +assign o_s[25]=P0[25]^G6[24]; +assign o_s[26]=P0[26]^G6[25]; +assign o_s[27]=P0[27]^G6[26]; +assign o_s[28]=P0[28]^G6[27]; +assign o_s[29]=P0[29]^G6[28]; +assign o_s[30]=P0[30]^G6[29]; +assign o_s[31]=P0[31]^G6[30]; +assign o_c=G6[31]; + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pid_simple/PID_defines.v b/designs/encrypted_ip/pid_simple/PID_defines.v new file mode 100644 index 000000000..a43f6b38d --- /dev/null +++ b/designs/encrypted_ip/pid_simple/PID_defines.v @@ -0,0 +1,8 @@ +//`define wb_16bit +`define wb_32bit +//`define wb_64bit + + +//`define PID_test + +//`define PID_direct_test \ No newline at end of file diff --git a/designs/encrypted_ip/pid_simple/booth.v b/designs/encrypted_ip/pid_simple/booth.v new file mode 100644 index 000000000..f33b3d80e --- /dev/null +++ b/designs/encrypted_ip/pid_simple/booth.v @@ -0,0 +1,37 @@ +/*Booth Encoder +Author: Zhu Xu +Email: m99a1@yahoo.cn +*/ +module booth_radix4( +input [2:0]codes, +output zero, +output double, +output negation +); + +wire A; +assign A=codes[2]; +wire B; +assign B=codes[1]; +wire C; +assign C=codes[0]; +wire nB,nC,nA; +assign nB=~B; +assign nC=~C; +assign nA=~A; + +wire BC; +assign BC=B&C; +wire nBnC; +assign nBnC=nB&nC; +wire nBanC; +assign nBanC=nB|nC; + +assign double=(nBnC&A)|(BC&nA); +assign negation=A&nBanC; +assign zero=(A&BC)|(nA&nBnC); + + + + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pid_simple/design.yaml b/designs/encrypted_ip/pid_simple/design.yaml new file mode 100644 index 000000000..4506112bf --- /dev/null +++ b/designs/encrypted_ip/pid_simple/design.yaml @@ -0,0 +1,6 @@ +top: top + +encrypted_ip: + - "pid_simple": ["pid_simple_0"] + +encrypted_ip_user_files: ["top.v"] \ No newline at end of file diff --git a/designs/encrypted_ip/pid_simple/pid_simple.v b/designs/encrypted_ip/pid_simple/pid_simple.v new file mode 100644 index 000000000..00895ff38 --- /dev/null +++ b/designs/encrypted_ip/pid_simple/pid_simple.v @@ -0,0 +1,434 @@ +/* PID controller + +sigma=Ki*e(n)+sigma +u(n)=(Kp+Kd)*e(n)+sigma+Kd*(-e(n-1)) + +Data width of Wishbone slave port can be can be toggled between 64-bit, 32-bit and 16-bit. +Address width of Wishbone slave port can be can be modified by changing parameter adr_wb_nb. + +Wishbone compliant +Work as Wishbone slave, support Classic standard SINGLE/BLOCK READ/WRITE Cycle + +registers or wires +[15:0]kp,ki,kd,sp,pv; can be both read and written +[15:0]kpd; read only +[15:0]err[0:1]; read only +[15:0]mr,md; not accessable +[31:0]p,b; not accessable +[31:0]un,sigma; read only +RS write 0 to RS will reset err[0], OF, un and sigma + + + +[4:0]of; overflow register, read only through Wishbone interface, address: 0x40 +of[0]==1 : kpd overflow +of[1]==1 : err[0] overflow +of[2]==1 : err[1] overflow +of[3]==1 : un overflow +of[4]==1 : sigma overflow +[0:15]rl; read lock, when asserted corelated reagister can not be read through Wishbone interface +[0:7]wl; write lock, when asserted corelated reagister can not be written through Wishbone interface + + + +*/ + +`include "PID_defines.v" + +module pid_simple #( +`ifdef wb_16bit +parameter wb_nb=16, +`endif +`ifdef wb_32bit +parameter wb_nb=32, +`endif +`ifdef wb_64bit +parameter wb_nb=64, +`endif + adr_wb_nb=16, + kp_adr = 0, + ki_adr = 1, + kd_adr = 2, + sp_adr = 3, + pv_adr = 4, + kpd_adr = 5, + err_0_adr = 6, + err_1_adr = 7, + un_adr = 8, + sigma_adr = 9, + of_adr = 10, + RS_adr = 11 +)( +input i_clk, +input i_rst, //reset when high +//Wishbone Slave port +input i_wb_cyc, +input i_wb_stb, +input i_wb_we, +input [adr_wb_nb-1:0]i_wb_adr, +input [wb_nb-1:0]i_wb_data, +output o_wb_ack, +output [wb_nb-1:0]o_wb_data, + +//u(n) output +output [31:0]o_un, +output o_valid +); + + + +reg [15:0]kp,ki,kd,sp,pv; +reg wla,wlb; // write locks +wire wlRS; +assign wlRS=wla|wlb; +wire [0:7]wl={{3{wla}},{2{wlb}},3'h0}; + +reg wack; //write acknowledged + +wire [2:0]adr; // address for write +`ifdef wb_16bit +assign adr=i_wb_adr[3:1]; +`endif +`ifdef wb_32bit +assign adr=i_wb_adr[4:2]; +`endif +`ifdef wb_64bit +assign adr=i_wb_adr[5:3]; +`endif + +wire [3:0]adr_1; // address for read +`ifdef wb_32bit +assign adr_1=i_wb_adr[5:2]; +`endif +`ifdef wb_16bit +assign adr_1=i_wb_adr[4:1]; +`endif +`ifdef wb_64bit +assign adr_1=i_wb_adr[6:3]; +`endif + + +wire we; // write enable +assign we=i_wb_cyc&i_wb_we&i_wb_stb; +wire re; //read enable +assign re=i_wb_cyc&(~i_wb_we)&i_wb_stb; + +reg state_0; //state machine No.1's state register + +wire adr_check_1; // A '1' means address is within the range of adr_1 +`ifdef wb_32bit +assign adr_check_1=i_wb_adr[adr_wb_nb-1:6]==0; +`endif +`ifdef wb_16bit +assign adr_check_1=i_wb_adr[adr_wb_nb-1:5]==0; +`endif +`ifdef wb_64bit +assign adr_check_1=i_wb_adr[adr_wb_nb-1:7]==0; +`endif + +wire adr_check; // A '1' means address is within the range of adr +`ifdef wb_16bit +assign adr_check=i_wb_adr[4]==0&&adr_check_1; +`endif +`ifdef wb_32bit +assign adr_check=i_wb_adr[5]==0&&adr_check_1; +`endif +`ifdef wb_64bit +assign adr_check=i_wb_adr[6]==0&&adr_check_1; +`endif + + //state machine No.1 +reg RS; +always@(posedge i_clk or posedge i_rst) + if(i_rst)begin + state_0<=0; + wack<=0; + kp<=0; + ki<=0; + kd<=0; + sp<=0; + pv<=0; + RS<=0; + end + else begin + if(wack&&(!i_wb_stb)) wack<=0; + if(RS)RS<=0; + case(state_0) + 0: begin + if(we&&(!wack)) state_0<=1; + end + 1: begin + if(adr_check)begin + if(!wl[adr])begin + wack<=1; + state_0<=0; + case(adr) + 0: begin + kp<=i_wb_data[15:0]; + end + 1: begin + ki<=i_wb_data[15:0]; + end + 2: begin + kd<=i_wb_data[15:0]; + end + 3: begin + sp<=i_wb_data[15:0]; + end + 4: begin + pv<=i_wb_data[15:0]; + end + endcase + + end + end + else if((adr_1==RS_adr)&&(!wlRS)&&(i_wb_data==0))begin + wack<=1; + state_0<=0; + RS<=1; + end + else begin + wack<=1; + state_0<=0; + end + end + endcase + end + + + //state machine No.2 +reg [9:0]state_1; + +wire update_kpd; +assign update_kpd=wack&&(~adr[2])&&(~adr[0])&&adr_check; //adr==0||adr==2 + +wire update_esu; //update e(n), sigma and u(n) +assign update_esu=wack&&(adr==4)&&adr_check; + +reg rla; // read locks +reg rlb; + + +reg [4:0]of; +reg [15:0]kpd; +reg [15:0]err[0:1]; + +wire [15:0]mr,md; + +reg [31:0]p; +reg [31:0]a,sigma,un; + +reg cout; +wire cin; +wire [31:0]sum; +wire [31:0]product; + +reg start; //start signal for multiplier + +reg [1:0]mr_index; +reg [1:0]md_index; +assign mr= mr_index==1?kpd: + mr_index==2?kd:ki; +assign md= md_index==2?err[1]: + md_index==1?err[0]:sum[15:0]; + + +wire of_addition[0:1]; +assign of_addition[0]=(p[15]&&a[15]&&(!sum[15]))||((!p[15])&&(!a[15])&&sum[15]); +assign of_addition[1]=(p[31]&&a[31]&&(!sum[31]))||((!p[31])&&(!a[31])&&sum[31]); + +always@(posedge i_clk or posedge i_rst) + if(i_rst)begin + state_1<=12'b000000000001; + wla<=0; + wlb<=0; + rla<=0; + rlb<=0; + of<=0; + kpd<=0; + err[0]<=0; + err[1]<=0; + p<=0; + a<=0; + sigma<=0; + un<=0; + start<=0; + mr_index<=0; + md_index<=0; + cout<=0; + end + else begin + case(state_1) + 10'b0000000001: begin + if(update_kpd)begin + state_1<=10'b0000000010; + wla<=1; + rla<=1; + end + else if(update_esu)begin + state_1<=10'b0000001000; + wla<=1; + wlb<=1; + rlb<=1; + end + else if(RS)begin //start a new sequance of U(n) + un<=0; + sigma<=0; + of<=0; + err[0]<=0; + end + end + 10'b0000000010: begin + p<={{16{kp[15]}},kp}; + a<={{16{kd[15]}},kd}; + state_1<=10'b0000000100; + end + 10'b0000000100: begin + kpd<=sum[15:0]; + wla<=0; + rla<=0; + of[0]<=of_addition[0]; + state_1<=10'b0000000001; + end + 10'b0000001000: begin + p<={{16{sp[15]}},sp}; + a<={{16{~pv[15]}},~pv}; + cout<=1; + start<=1; // start calculate err0 * ki + state_1<=10'b0000010000; + end + 10'b0000010000: begin + err[0]<=sum[15:0]; + of[1]<=of_addition[0]; + of[2]<=of[1]; + p<={{16{~err[0][15]}},~err[0]}; + a<={31'b0,1'b1}; + cout<=0; + mr_index<=1; // start calculate err0 * kpd + md_index<=1; + state_1<=10'b0000100000; + end + 10'b0000100000: begin + err[1]<=sum[15:0]; + mr_index<=2; // start calculate err1 * kd + md_index<=2; + state_1<=10'b0001000000; + end + 10'b0001000000: begin + mr_index<=0; + md_index<=0; + start<=0; + p<=product; // start calculate err0*ki + sigma_last + a<=sigma; + state_1<=10'b0010000000; + end + 10'b0010000000: begin + a<=sum; // start calculate err0*kpd + sigma_recent + sigma<=sum; + of[3]<=of[4]|of_addition[1]; + of[4]<=of[4]|of_addition[1]; + p<=product; + state_1<=10'b0100000000; + end + 10'b0100000000: begin + a<=sum; // start calculate err0*kpd + sigma_recent+err1*kd + of[3]<=of[3]|of_addition[1]; + p<=product; + state_1<=10'b1000000000; + end + 10'b1000000000: begin + un<=sum; + of[3]<=of[3]|of_addition[1]; + state_1<=10'b0000000001; + wla<=0; + wlb<=0; + rlb<=0; + end + endcase + end + + +wire ready; +multiplier_16x16bit_pipelined multiplier_16x16bit_pipelined( +i_clk, +~i_rst, +start, +md, +mr, +product, +ready +); + +adder_32bit adder_32bit_0( +a, +p, +cout, +sum, +cin +); + + +wire [wb_nb-1:0]rdata[0:15]; //wishbone read data array +`ifdef wb_16bit +assign rdata[0]=kp; +assign rdata[1]=ki; +assign rdata[2]=kd; +assign rdata[3]=sp; +assign rdata[4]=pv; +assign rdata[5]=kpd; +assign rdata[6]=err[0]; +assign rdata[7]=err[1]; +assign rdata[8]=un[15:0]; +assign rdata[9]=sigma[15:0]; +assign rdata[10]={11'b0,of}; +`endif + +`ifdef wb_32bit +assign rdata[0]={{16{kp[15]}},kp}; +assign rdata[1]={{16{ki[15]}},ki}; +assign rdata[2]={{16{kd[15]}},kd}; +assign rdata[3]={{16{sp[15]}},sp}; +assign rdata[4]={{16{pv[15]}},pv}; +assign rdata[5]={{16{kpd[15]}},kpd}; +assign rdata[6]={{16{err[0][15]}},err[0]}; +assign rdata[7]={{16{err[1][15]}},err[1]}; +assign rdata[8]=un; +assign rdata[9]=sigma; +assign rdata[10]={27'b0,of}; +`endif + +`ifdef wb_64bit +assign rdata[0]={{48{kp[15]}},kp}; +assign rdata[1]={{48{ki[15]}},ki}; +assign rdata[2]={{48{kd[15]}},kd}; +assign rdata[3]={{48{sp[15]}},sp}; +assign rdata[4]={{48{pv[15]}},pv}; +assign rdata[5]={{48{kpd[15]}},kpd}; +assign rdata[6]={{48{err[0][15]}},err[0]}; +assign rdata[7]={{48{err[1][15]}},err[1]}; +assign rdata[8]={{32{un[31]}},un}; +assign rdata[9]={{32{sigma[31]}},sigma}; +assign rdata[10]={59'b0,of}; +`endif + +assign rdata[11]=0; +assign rdata[12]=0; +assign rdata[13]=0; +assign rdata[14]=0; +assign rdata[15]=0; + + +wire [0:15]rl; +assign rl={5'b0,rla,{4{rlb}},rla|rlb,5'b0}; + +wire rack; // wishbone read acknowledged +assign rack=(re&adr_check_1&(~rl[adr_1]))|(re&(~adr_check_1)); + +assign o_wb_ack=(wack|rack)&i_wb_stb; + +assign o_wb_data=adr_check_1?rdata[adr_1]:0; +assign o_un=un; +assign o_valid=~rlb; + + +endmodule diff --git a/designs/encrypted_ip/pid_simple/top.v b/designs/encrypted_ip/pid_simple/top.v new file mode 100644 index 000000000..8a515eab6 --- /dev/null +++ b/designs/encrypted_ip/pid_simple/top.v @@ -0,0 +1,57 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 07/13/2017 04:11:09 PM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module top( + input clk, + input reset, // Not used + input [15:0] sw, + input [4:0] btn, // Not used + output [15:0] led, + output [6:0] seg, // Not used + output dp, // Not used + output [7:0] an // Not used + ); + + assign seg = {btn, reset, 1'b0}; + assign dp = 1'b0; + assign an = 8'b00000000; + + wire [15:0] adr_in = sw[15:0]; + wire [31:0] data_in = {2{sw[15:0]}}; + + wire wb_ack_top, valid_top; + wire [31:0] wb_data_top, un_top; + + pid_simple pid_simple_0(.i_clk(clk), + .i_rst(sw[0]), + .i_wb_cyc(sw[1]), + .i_wb_stb(sw[2]), + .i_wb_we(sw[3]), + .i_wb_adr(adr_in), + .i_wb_data(data_in), + .o_wb_ack(wb_ack_top), + .o_wb_data(wb_data_top), + .o_un(un_top), + .o_valid(valid_top)); + + assign led = {16{wb_ack_top ^ valid_top ^ ^{wb_data_top} ^ ^{un_top}}}; + +endmodule From 616aa285cd7003d002d2dfa9b7ed0e38043b064b Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Sat, 9 Dec 2023 17:24:43 -0700 Subject: [PATCH 10/25] update submodule --- third_party/encrypted_ip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/third_party/encrypted_ip b/third_party/encrypted_ip index c6e09baa7..9677fe602 160000 --- a/third_party/encrypted_ip +++ b/third_party/encrypted_ip @@ -1 +1 @@ -Subproject commit c6e09baa757f5a5f031f787a25229c72ece7c3e1 +Subproject commit 9677fe602d88d1abd80bd9828fba05d894866700 From 073f804c177f715ea7d9b64464ec80ea29a89787 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Sat, 9 Dec 2023 17:25:48 -0700 Subject: [PATCH 11/25] submodule --- third_party/encrypted_ip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/third_party/encrypted_ip b/third_party/encrypted_ip index 9677fe602..21ae601b9 160000 --- a/third_party/encrypted_ip +++ b/third_party/encrypted_ip @@ -1 +1 @@ -Subproject commit 9677fe602d88d1abd80bd9828fba05d894866700 +Subproject commit 21ae601b93eb77a3a240bd9e66679062893c8698 From d2f8da591cfd365132cf5149bf4f77cf43b1f43a Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Sun, 10 Dec 2023 13:50:39 -0700 Subject: [PATCH 12/25] part 2 working --- Makefile | 3 ++- bfasst/flows/encrypted_ip.py | 28 +++++++++++++-------- bfasst/tools/ip/ipencrypter_rules.ninja | 2 +- bfasst/tools/ip/loader.py | 14 +++-------- bfasst/tools/ip/loader_build.ninja.mustache | 4 +-- bfasst/tools/ip/loader_rules.ninja | 2 +- bfasst/yaml_parser.py | 1 - designs/encrypted_ip/pid_simple/design.yaml | 9 ++++--- 8 files changed, 32 insertions(+), 31 deletions(-) diff --git a/Makefile b/Makefile index c9de4c949..72e7a5c2c 100644 --- a/Makefile +++ b/Makefile @@ -10,7 +10,8 @@ PUBLIC_SUBMODULES = \ third_party/WaFoVe PRIVATE_SUBMODULES = \ - third_party/gmt_tools + third_party/gmt_tools \ + third_party/encrypted_ip install: submodules venv python_packages rapidwright env install_fasm2bels install_yosys install_wafove diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py index bc537f9cc..b4bfcba03 100644 --- a/bfasst/flows/encrypted_ip.py +++ b/bfasst/flows/encrypted_ip.py @@ -1,5 +1,7 @@ """Flow to create Vivado synthesis and implementation ninja snippets.""" import pathlib + +import yaml from bfasst.flows.flow import Flow from bfasst.tools.ip.ipencrypter import IpEncrypter @@ -12,48 +14,52 @@ def __init__(self, design): super().__init__(design) encrypted_ip_paths = [] - encrypted_ip_names = [] encrypted_ip_ciphertext_paths = [] assert self.design_props.encrypted_ip, "No encrypted IPs specified" - # Synthesize and encrypt each encrypte IP - for ip in self.design_props.encrypted_ip: - encrypted_ip_names.append(ip) + # ip_definitions = [ip["definition"] for ip in self.design_props.encrypted_ip["ip"]] + # Synthesize and encrypt each encrypte IP + for ip in self.design_props.encrypted_ip["ip"]: + ip_definition = ip["definition"] synth_tool = VivadoSynth( self, design, ooc=True, - top=ip, + top=ip_definition, synth_options="-flatten_hierarchy full", ) synth_tool.override_build_path( - synth_tool.build_path.parent / f"{synth_tool.build_path.name}_{ip}" + synth_tool.build_path.parent / f"{synth_tool.build_path.name}_{ip_definition}" ) synth_tool._init_outputs() ip_encrypter_tool = IpEncrypter(self, design, synth_tool.outputs["synth_dcp"]) ip_encrypter_tool.override_build_path( - ip_encrypter_tool.build_path.parent / f"{ip_encrypter_tool.build_path.name}_{ip}" + ip_encrypter_tool.build_path.parent + / f"{ip_encrypter_tool.build_path.name}_{ip_definition}" ) encrypted_ip_paths.append(ip_encrypter_tool.outputs["encrypted_verilog"]) - encrypted_ip_ciphertext_paths.append(ip_encrypter_tool.outputs["lut_ciphertext"]) + ip["ciphertext_path"] = str(ip_encrypter_tool.outputs["lut_ciphertext"]) # Synthesize the top module synth_tool = VivadoSynth(self, design, ooc=True, synth_options="-flatten_hierarchy rebuilt") synth_tool.verilog = [ - self.design_path / v for v in self.design_props.encrypted_ip_user_files + self.design_path / v for v in self.design_props.encrypted_ip["user_files"] ] synth_tool.verilog.extend(encrypted_ip_paths) + encrypted_ip_yaml_path = self.design_build_path / "encrypted_ip.yaml" + with open(encrypted_ip_yaml_path, "w") as f: + yaml.dump(self.design_props.encrypted_ip["ip"], f) + # Encrypted IP Shell EncryptedIpLoader( self, design, user_synth_dcp_path=synth_tool.outputs["synth_dcp"], - ip_names=encrypted_ip_names, - ip_ciphertext_paths=encrypted_ip_ciphertext_paths, + encrypted_ip_yaml_path=encrypted_ip_yaml_path, ) def get_top_level_flow_path(self): diff --git a/bfasst/tools/ip/ipencrypter_rules.ninja b/bfasst/tools/ip/ipencrypter_rules.ninja index 1d8227473..ec982968e 100644 --- a/bfasst/tools/ip/ipencrypter_rules.ninja +++ b/bfasst/tools/ip/ipencrypter_rules.ninja @@ -1,4 +1,4 @@ rule encrypt_ip command = python third_party/encrypted_ip/Project/python_scripts/encryptDesign.py $in $key $dcp_encrypted $lut_ciphertext > $log_file - description = encrypt ip $dcp_unencrypted + description = encrypt ip $in diff --git a/bfasst/tools/ip/loader.py b/bfasst/tools/ip/loader.py index dc084466c..59fd52247 100644 --- a/bfasst/tools/ip/loader.py +++ b/bfasst/tools/ip/loader.py @@ -7,15 +7,12 @@ class EncryptedIpLoader(Tool): - def __init__( - self, flow, design_path, user_synth_dcp_path, ip_names, ip_ciphertext_paths - ) -> None: + def __init__(self, flow, design_path, user_synth_dcp_path, encrypted_ip_yaml_path) -> None: super().__init__(flow, design_path) self.build_path = self.design_build_path / "loader" self._my_dir_path = pathlib.Path(__file__).parent self.user_synth_dcp_path = user_synth_dcp_path - self.ip_names = ip_names - self.ip_ciphertext_paths = ip_ciphertext_paths + self.encrypted_ip_yaml_path = encrypted_ip_yaml_path self._init_outputs() def create_rule_snippets(self): @@ -50,12 +47,7 @@ def create_build_snippets(self): "top_dcp": str(self.user_synth_dcp_path), "final": str(self.build_path / "final"), "user_partial_bitstream": str(self.build_path / "user_partial.bit"), - "ip_args": " ".join( - [ - f"--ip {ip_name} {cipher_path}" - for ip_name, cipher_path in zip(self.ip_names, self.ip_ciphertext_paths) - ] - ), + "encrypted_ip_yaml_path": self.encrypted_ip_yaml_path, }, ) diff --git a/bfasst/tools/ip/loader_build.ninja.mustache b/bfasst/tools/ip/loader_build.ninja.mustache index 26a63293e..b9890a1d8 100644 --- a/bfasst/tools/ip/loader_build.ninja.mustache +++ b/bfasst/tools/ip/loader_build.ninja.mustache @@ -1,6 +1,6 @@ build {{ cwd }}/vivado.tcl: template {{ cwd }}/vivado.json {{ loader_tcl_template }} -build {{ final }}.dcp {{ final }}.edif {{ final }}_unencrypted.bit {{ final }}_unencrypted_pblock_user_partial.bit {{ final }}_encrypted.bit {{ user_partial_bitstream }}: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} +build {{ final }}.dcp {{ final }}.edif {{ final }}_unencrypted.bit {{ final }}_unencrypted_pblock_user_partial.bit {{ final }}_encrypted.bit {{ user_partial_bitstream }}: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} | third_party/encrypted_ip/Project/python_scripts/getLutDataGenPatched2.py cwd = {{ cwd }} journal = {{ cwd }}/vivado.jou log = {{ cwd }}/vivado.log @@ -8,4 +8,4 @@ build {{ final }}.dcp {{ final }}.edif {{ final }}_unencrypted.bit {{ final }}_u build {{ final }}_patched.bin: encrypted_ip_bit_patcher {{ final }}.dcp {{ final }}_unencrypted_pblock_user_partial.bit cwd = {{ cwd }} log = {{ cwd }}/patcher_log.txt - ip_args = {{ ip_args }} + encypted_ip_yaml_path = {{ encrypted_ip_yaml_path }} diff --git a/bfasst/tools/ip/loader_rules.ninja b/bfasst/tools/ip/loader_rules.ninja index 0211e80bf..756b5b667 100644 --- a/bfasst/tools/ip/loader_rules.ninja +++ b/bfasst/tools/ip/loader_rules.ninja @@ -1,4 +1,4 @@ rule encrypted_ip_bit_patcher - command = python3 third_party/encrypted_ip/Project/python_scripts/getLutDataGenPatched2.py $in $out $ip_args > $log + command = python3 third_party/encrypted_ip/Project/python_scripts/getLutDataGenPatched2.py $in $out $encypted_ip_yaml_path > $log description = Patching user bitstream diff --git a/bfasst/yaml_parser.py b/bfasst/yaml_parser.py index f81ed0fc0..f6d701398 100644 --- a/bfasst/yaml_parser.py +++ b/bfasst/yaml_parser.py @@ -114,7 +114,6 @@ def __init__(self, yaml_path): self.encrypted_ip = None if "encrypted_ip" in self.props: self.encrypted_ip = self.props["encrypted_ip"] - self.encrypted_ip_user_files = self.props["encrypted_ip_user_files"] class FlowDescriptionParser(YamlParser): diff --git a/designs/encrypted_ip/pid_simple/design.yaml b/designs/encrypted_ip/pid_simple/design.yaml index 4506112bf..6f2ad839d 100644 --- a/designs/encrypted_ip/pid_simple/design.yaml +++ b/designs/encrypted_ip/pid_simple/design.yaml @@ -1,6 +1,9 @@ top: top -encrypted_ip: - - "pid_simple": ["pid_simple_0"] +encrypted_ip: + ip: + - definition: "pid_simple" + instances: + - "pid_simple_0" -encrypted_ip_user_files: ["top.v"] \ No newline at end of file + user_files: ["top.v"] \ No newline at end of file From 3508e37323984a7f87a794caf247f67e39ba958e Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Mon, 11 Dec 2023 17:42:03 -0700 Subject: [PATCH 13/25] Add dont touch to flow --- bfasst/flows/encrypted_ip.py | 11 +- bfasst/tools/common/dont_touch.ninja | 4 + bfasst/tools/ip/ipencrypter.py | 12 +- .../tools/ip/ipencrypter_build.ninja.mustache | 5 +- bfasst/tools/ip/loader_build.ninja.mustache | 4 +- bfasst/utils/dont_touch.py | 27 + designs/encrypted_ip/des3_area/ac97_cra.v | 192 + designs/encrypted_ip/des3_area/ac97_defines.v | 169 + designs/encrypted_ip/des3_area/ac97_dma_if.v | 216 + designs/encrypted_ip/des3_area/ac97_dma_req.v | 115 + .../encrypted_ip/des3_area/ac97_fifo_ctrl.v | 113 + designs/encrypted_ip/des3_area/ac97_in_fifo.v | 339 + designs/encrypted_ip/des3_area/ac97_int.v | 124 + .../encrypted_ip/des3_area/ac97_out_fifo.v | 344 + designs/encrypted_ip/des3_area/ac97_prc.v | 332 + designs/encrypted_ip/des3_area/ac97_rf.v | 302 + designs/encrypted_ip/des3_area/ac97_rst.v | 98 + designs/encrypted_ip/des3_area/ac97_sin.v | 141 + designs/encrypted_ip/des3_area/ac97_soc.v | 201 + designs/encrypted_ip/des3_area/ac97_sout.v | 179 + designs/encrypted_ip/des3_area/ac97_top.v | 757 + .../encrypted_ip/des3_area/ac97_top_synthed.v | 16776 ++++++++++++++ designs/encrypted_ip/des3_area/ac97_wb_if.v | 200 + designs/encrypted_ip/des3_area/crp.v | 69 + designs/encrypted_ip/des3_area/des3_area.v | 148 + .../des3_area/des3_area_synthed.v | 8605 ++++++++ designs/encrypted_ip/des3_area/design.yaml | 16 + designs/encrypted_ip/des3_area/key_sel3.v | 865 + designs/encrypted_ip/des3_area/mc_adr_sel.v | 286 + designs/encrypted_ip/des3_area/mc_cs_rf.v | 272 + designs/encrypted_ip/des3_area/mc_defines.v | 228 + designs/encrypted_ip/des3_area/mc_dp.v | 240 + designs/encrypted_ip/des3_area/mc_incn_r.v | 98 + designs/encrypted_ip/des3_area/mc_mem_if.v | 358 + designs/encrypted_ip/des3_area/mc_obct.v | 232 + designs/encrypted_ip/des3_area/mc_obct_top.v | 422 + designs/encrypted_ip/des3_area/mc_rd_fifo.v | 126 + designs/encrypted_ip/des3_area/mc_refresh.v | 206 + designs/encrypted_ip/des3_area/mc_rf.v | 832 + designs/encrypted_ip/des3_area/mc_timing.v | 1731 ++ designs/encrypted_ip/des3_area/mc_top.v | 545 + .../encrypted_ip/des3_area/mc_top_synthed.v | 18190 ++++++++++++++++ designs/encrypted_ip/des3_area/mc_wb_if.v | 248 + designs/encrypted_ip/des3_area/sbox1.v | 113 + designs/encrypted_ip/des3_area/sbox2.v | 113 + designs/encrypted_ip/des3_area/sbox3.v | 113 + designs/encrypted_ip/des3_area/sbox4.v | 113 + designs/encrypted_ip/des3_area/sbox5.v | 113 + designs/encrypted_ip/des3_area/sbox6.v | 113 + designs/encrypted_ip/des3_area/sbox7.v | 113 + designs/encrypted_ip/des3_area/sbox8.v | 113 + designs/encrypted_ip/des3_area/top.v | 200 + 52 files changed, 55472 insertions(+), 10 deletions(-) create mode 100644 bfasst/tools/common/dont_touch.ninja create mode 100644 bfasst/utils/dont_touch.py create mode 100644 designs/encrypted_ip/des3_area/ac97_cra.v create mode 100644 designs/encrypted_ip/des3_area/ac97_defines.v create mode 100644 designs/encrypted_ip/des3_area/ac97_dma_if.v create mode 100644 designs/encrypted_ip/des3_area/ac97_dma_req.v create mode 100644 designs/encrypted_ip/des3_area/ac97_fifo_ctrl.v create mode 100644 designs/encrypted_ip/des3_area/ac97_in_fifo.v create mode 100644 designs/encrypted_ip/des3_area/ac97_int.v create mode 100644 designs/encrypted_ip/des3_area/ac97_out_fifo.v create mode 100644 designs/encrypted_ip/des3_area/ac97_prc.v create mode 100644 designs/encrypted_ip/des3_area/ac97_rf.v create mode 100644 designs/encrypted_ip/des3_area/ac97_rst.v create mode 100644 designs/encrypted_ip/des3_area/ac97_sin.v create mode 100644 designs/encrypted_ip/des3_area/ac97_soc.v create mode 100644 designs/encrypted_ip/des3_area/ac97_sout.v create mode 100644 designs/encrypted_ip/des3_area/ac97_top.v create mode 100644 designs/encrypted_ip/des3_area/ac97_top_synthed.v create mode 100644 designs/encrypted_ip/des3_area/ac97_wb_if.v create mode 100644 designs/encrypted_ip/des3_area/crp.v create mode 100644 designs/encrypted_ip/des3_area/des3_area.v create mode 100644 designs/encrypted_ip/des3_area/des3_area_synthed.v create mode 100644 designs/encrypted_ip/des3_area/design.yaml create mode 100644 designs/encrypted_ip/des3_area/key_sel3.v create mode 100644 designs/encrypted_ip/des3_area/mc_adr_sel.v create mode 100644 designs/encrypted_ip/des3_area/mc_cs_rf.v create mode 100644 designs/encrypted_ip/des3_area/mc_defines.v create mode 100644 designs/encrypted_ip/des3_area/mc_dp.v create mode 100644 designs/encrypted_ip/des3_area/mc_incn_r.v create mode 100644 designs/encrypted_ip/des3_area/mc_mem_if.v create mode 100644 designs/encrypted_ip/des3_area/mc_obct.v create mode 100644 designs/encrypted_ip/des3_area/mc_obct_top.v create mode 100644 designs/encrypted_ip/des3_area/mc_rd_fifo.v create mode 100644 designs/encrypted_ip/des3_area/mc_refresh.v create mode 100644 designs/encrypted_ip/des3_area/mc_rf.v create mode 100644 designs/encrypted_ip/des3_area/mc_timing.v create mode 100644 designs/encrypted_ip/des3_area/mc_top.v create mode 100644 designs/encrypted_ip/des3_area/mc_top_synthed.v create mode 100644 designs/encrypted_ip/des3_area/mc_wb_if.v create mode 100644 designs/encrypted_ip/des3_area/sbox1.v create mode 100644 designs/encrypted_ip/des3_area/sbox2.v create mode 100644 designs/encrypted_ip/des3_area/sbox3.v create mode 100644 designs/encrypted_ip/des3_area/sbox4.v create mode 100644 designs/encrypted_ip/des3_area/sbox5.v create mode 100644 designs/encrypted_ip/des3_area/sbox6.v create mode 100644 designs/encrypted_ip/des3_area/sbox7.v create mode 100644 designs/encrypted_ip/des3_area/sbox8.v create mode 100644 designs/encrypted_ip/des3_area/top.v diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py index b4bfcba03..89716d3d7 100644 --- a/bfasst/flows/encrypted_ip.py +++ b/bfasst/flows/encrypted_ip.py @@ -35,11 +35,13 @@ def __init__(self, design): ) synth_tool._init_outputs() - ip_encrypter_tool = IpEncrypter(self, design, synth_tool.outputs["synth_dcp"]) - ip_encrypter_tool.override_build_path( - ip_encrypter_tool.build_path.parent - / f"{ip_encrypter_tool.build_path.name}_{ip_definition}" + ip_encrypter_tool = IpEncrypter( + self, design, ip_definition, synth_tool.outputs["synth_dcp"] ) + # ip_encrypter_tool.override_build_path( + # ip_encrypter_tool.build_path.parent + # / f"{ip_encrypter_tool.build_path.name}_{ip_definition}" + # ) encrypted_ip_paths.append(ip_encrypter_tool.outputs["encrypted_verilog"]) ip["ciphertext_path"] = str(ip_encrypter_tool.outputs["lut_ciphertext"]) @@ -51,6 +53,7 @@ def __init__(self, design): synth_tool.verilog.extend(encrypted_ip_paths) encrypted_ip_yaml_path = self.design_build_path / "encrypted_ip.yaml" + encrypted_ip_yaml_path.parent.mkdir(exist_ok=True, parents=True) with open(encrypted_ip_yaml_path, "w") as f: yaml.dump(self.design_props.encrypted_ip["ip"], f) diff --git a/bfasst/tools/common/dont_touch.ninja b/bfasst/tools/common/dont_touch.ninja new file mode 100644 index 000000000..3a4d2f4f8 --- /dev/null +++ b/bfasst/tools/common/dont_touch.ninja @@ -0,0 +1,4 @@ +rule apply_dont_touch + command = python bfasst/utils/dont_touch.py $in $out $module_name + description = applying don't touch to $in + diff --git a/bfasst/tools/ip/ipencrypter.py b/bfasst/tools/ip/ipencrypter.py index a022c51b4..ca90fb263 100644 --- a/bfasst/tools/ip/ipencrypter.py +++ b/bfasst/tools/ip/ipencrypter.py @@ -6,9 +6,10 @@ class IpEncrypter(Tool): - def __init__(self, flow, design_path, ip_dcp_path) -> None: + def __init__(self, flow, design_path, ip_defn_name, ip_dcp_path) -> None: super().__init__(flow, design_path) - self.build_path = self.design_build_path / "ip_encrypter" + self.build_path = self.design_build_path / f"ip_encrypter_{ip_defn_name}" + self.ip_defn_name = ip_defn_name self.ip_dcp_path = ip_dcp_path self._init_outputs() @@ -22,11 +23,12 @@ def create_rule_snippets(self): }, COMMON_TOOLS_PATH / "vivado_rules.ninja.mustache", ) + self._append_rule_snippets_default(None, None, COMMON_TOOLS_PATH / "dont_touch.ninja") def create_build_snippets(self): dcp_to_v = { "dcp": str(self.outputs["encrypted_ip_dcp"]), - "verilog": str(self.outputs["encrypted_verilog"]), + "verilog": str(self.outputs["encrypted_verilog_touch"]), } dcp_to_v_json = json.dumps(dcp_to_v, indent=4) json_write_if_changed(self.build_path / "dcp_to_v.json", dcp_to_v_json) @@ -36,19 +38,23 @@ def create_build_snippets(self): { "dcp_unencrypted": self.ip_dcp_path, "dcp_encrypted": self.outputs["encrypted_ip_dcp"], + "verilog_encrypted_touch": self.outputs["encrypted_verilog_touch"], "verilog_encrypted": self.outputs["encrypted_verilog"], "lut_ciphertext": self.outputs["lut_ciphertext"], "log_file": self.outputs["log"], "cwd": self.build_path, "gen_encrypted_verilog_template": COMMON_TOOLS_PATH / "dcp_to_v.tcl.mustache", + "ip_defn_name": self.ip_defn_name, }, ) def add_ninja_deps(self, deps): self._add_ninja_deps_default(deps, __file__) + deps.append(BFASST_UTILS_PATH / "dont_touch.py") def _init_outputs(self): self.outputs["encrypted_ip_dcp"] = self.build_path / "encrypted_ip.dcp" + self.outputs["encrypted_verilog_touch"] = self.build_path / "encrypted_ip_touch.v" self.outputs["encrypted_verilog"] = self.build_path / "encrypted_ip.v" self.outputs["lut_ciphertext"] = self.build_path / "lut_ciphertext.txt" self.outputs["log"] = self.build_path / "log.txt" diff --git a/bfasst/tools/ip/ipencrypter_build.ninja.mustache b/bfasst/tools/ip/ipencrypter_build.ninja.mustache index 03911efbf..354d7076c 100644 --- a/bfasst/tools/ip/ipencrypter_build.ninja.mustache +++ b/bfasst/tools/ip/ipencrypter_build.ninja.mustache @@ -7,8 +7,11 @@ build {{ log_file }} {{ dcp_encrypted }}: encrypt_ip {{ dcp_unencrypted }} build {{ cwd }}/dcp_to_v.tcl: template {{ cwd }}/dcp_to_v.json {{ gen_encrypted_verilog_template }} cwd = {{ cwd }} -build {{ verilog_encrypted }}: vivado {{ cwd }}/dcp_to_v.tcl {{ dcp_encrypted }} +build {{ verilog_encrypted_touch }}: vivado {{ cwd }}/dcp_to_v.tcl {{ dcp_encrypted }} cwd = {{ cwd }} journal = {{ cwd }}/vivado.jou log = {{ cwd }}/vivado.log +build {{ verilog_encrypted }}: apply_dont_touch {{ verilog_encrypted_touch }} + module_name = {{ ip_defn_name }} + diff --git a/bfasst/tools/ip/loader_build.ninja.mustache b/bfasst/tools/ip/loader_build.ninja.mustache index b9890a1d8..48e1e38f5 100644 --- a/bfasst/tools/ip/loader_build.ninja.mustache +++ b/bfasst/tools/ip/loader_build.ninja.mustache @@ -1,11 +1,11 @@ build {{ cwd }}/vivado.tcl: template {{ cwd }}/vivado.json {{ loader_tcl_template }} -build {{ final }}.dcp {{ final }}.edif {{ final }}_unencrypted.bit {{ final }}_unencrypted_pblock_user_partial.bit {{ final }}_encrypted.bit {{ user_partial_bitstream }}: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} | third_party/encrypted_ip/Project/python_scripts/getLutDataGenPatched2.py +build {{ final }}.dcp {{ final }}.edif {{ final }}_unencrypted.bit {{ final }}_unencrypted_pblock_user_partial.bit {{ final }}_encrypted.bit {{ user_partial_bitstream }}: vivado {{ cwd }}/vivado.tcl {{ top_dcp }} cwd = {{ cwd }} journal = {{ cwd }}/vivado.jou log = {{ cwd }}/vivado.log -build {{ final }}_patched.bin: encrypted_ip_bit_patcher {{ final }}.dcp {{ final }}_unencrypted_pblock_user_partial.bit +build {{ final }}_patched.bin: encrypted_ip_bit_patcher {{ final }}.dcp {{ final }}_unencrypted_pblock_user_partial.bit | third_party/encrypted_ip/Project/python_scripts/getLutDataGenPatched2.py cwd = {{ cwd }} log = {{ cwd }}/patcher_log.txt encypted_ip_yaml_path = {{ encrypted_ip_yaml_path }} diff --git a/bfasst/utils/dont_touch.py b/bfasst/utils/dont_touch.py new file mode 100644 index 000000000..770ca1d42 --- /dev/null +++ b/bfasst/utils/dont_touch.py @@ -0,0 +1,27 @@ +import argparse +import pathlib +import re + + +def main(verilog_in, verilog_out, module_name): + assert verilog_in.is_file() + + with open(verilog_in, "r") as fp: + text = fp.read() + + match = re.match("(.*)^(\w*module " + module_name + ".*)", text, re.M | re.DOTALL) + assert match + + new_text = match.group(1) + '(* DONT_TOUCH = "yes" *)\n' + match.group(2) + with open(verilog_out, "w") as fp: + fp.write(new_text) + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument("verilog_in", type=pathlib.Path) + parser.add_argument("verilog_out", type=pathlib.Path) + parser.add_argument("module_name", type=str) + args = parser.parse_args() + + main(args.verilog_in, args.verilog_out, args.module_name) diff --git a/designs/encrypted_ip/des3_area/ac97_cra.v b/designs/encrypted_ip/des3_area/ac97_cra.v new file mode 100644 index 000000000..5c4beb475 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_cra.v @@ -0,0 +1,192 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Codec Register Access Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +// CVS Log +// +// $Id: ac97_cra.v,v 1.3 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:49 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:18 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_cra(clk, rst, + + crac_we, crac_din, crac_out, + crac_wr_done, crac_rd_done, + + valid, out_slt1, out_slt2, + in_slt2, + + crac_valid, crac_wr + ); + +input clk, rst; +input crac_we; +output [15:0] crac_din; +input [31:0] crac_out; +output crac_wr_done, crac_rd_done; + +input valid; +output [19:0] out_slt1; +output [19:0] out_slt2; +input [19:0] in_slt2; + +output crac_valid; +output crac_wr; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg crac_wr; +reg crac_rd; +reg crac_rd_done; +reg [15:0] crac_din; +reg crac_we_r; +reg valid_r; +wire valid_ne; +wire valid_pe; +reg rdd1, rdd2, rdd3; + +//////////////////////////////////////////////////////////////////// +// +// Codec Register Data Path +// + +// Control +assign out_slt1[19] = crac_out[31]; +assign out_slt1[18:12] = crac_out[22:16]; +assign out_slt1[11:0] = 12'h0; + +// Write Data +assign out_slt2[19:4] = crac_out[15:0]; +assign out_slt2[3:0] = 4'h0; + +// Read Data +always @(posedge clk or negedge rst) + begin + if(!rst) crac_din <= #1 16'h0; + else + if(crac_rd_done) crac_din <= #1 in_slt2[19:4]; + end + +//////////////////////////////////////////////////////////////////// +// +// Codec Register Access Tracking +// + +assign crac_valid = crac_wr | crac_rd; + +always @(posedge clk) + crac_we_r <= #1 crac_we; + +always @(posedge clk or negedge rst) + if(!rst) crac_wr <= #1 1'b0; + else + if(crac_we_r & !crac_out[31]) crac_wr <= #1 1'b1; + else + if(valid_ne) crac_wr <= #1 1'b0; + +assign crac_wr_done = crac_wr & valid_ne; + +always @(posedge clk or negedge rst) + if(!rst) crac_rd <= #1 1'b0; + else + if(crac_we_r & crac_out[31]) crac_rd <= #1 1'b1; + else + if(rdd1 & valid_pe) crac_rd <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) rdd1 <= #1 1'b0; + else + if(crac_rd & valid_ne) rdd1 <= #1 1'b1; + else + if(!crac_rd) rdd1 <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) rdd2 <= #1 1'b0; + else + if( (crac_rd & valid_ne) | (!rdd3 & rdd2) ) rdd2 <= #1 1'b1; + else + if(crac_rd_done) rdd2 <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) rdd3 <= #1 1'b0; + else + if(rdd2 & valid_pe) rdd3 <= #1 1'b1; + else + if(crac_rd_done) rdd3 <= #1 1'b0; + +always @(posedge clk) + crac_rd_done <= #1 rdd3 & valid_pe; + +always @(posedge clk) + valid_r <= #1 valid; + +assign valid_ne = !valid & valid_r; + +assign valid_pe = valid & !valid_r; + +endmodule diff --git a/designs/encrypted_ip/des3_area/ac97_defines.v b/designs/encrypted_ip/des3_area/ac97_defines.v new file mode 100644 index 000000000..ac2e215c4 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_defines.v @@ -0,0 +1,169 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_defines.v,v 1.5 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.4 2002/03/11 03:21:22 rudi +// +// - Added defines to select fifo depth between 4, 8 and 16 entries. +// +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:49 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:14 rudi +// Initial Checkin +// +// +// +// + +`timescale 1ns / 10ps + +///////////////////////////////////////////////////////////////////// +// This AC97 Controller supports up to 6 Output and 3 Input Channels. +// Comment out the define statement for which channels you do not wish +// to support in your implementation. The main Left and Right channels +// are always supported. + +// Surround Left + Right +`define AC97_SURROUND 1 + +// Center Channel +`define AC97_CENTER 1 + +// LFE Channel +`define AC97_LFE 1 + +// Stereo Input +`define AC97_SIN 1 + +// Mono Microphone Input +`define AC97_MICIN 1 + +///////////////////////////////////////////////////////////////////// +// +// This define selects how the WISHBONE interface determines if +// the internal register file is selected. +// This should be a simple address decoder. "wb_addr_i" is the +// WISHBONE address bus (32 bits wide). +`define AC97_REG_SEL (wb_addr_i[31:29] == 3'h0) + +///////////////////////////////////////////////////////////////////// +// +// This is a prescaler that generates a pulse every 250 nS. +// The value here should one less than the actually calculated +// value. +// For a 200 MHz wishbone clock, this value is 49 (50-1). +`define AC97_250_PS 6'h31 + +///////////////////////////////////////////////////////////////////// +// +// AC97 Cold reset Must be asserted for at least 1uS. The AC97 +// controller will stretch the reset pulse to at least 1uS. +// The reset timer is driven by the AC97_250_PS prescaler. +// This value should probably be never changed. Adjust the +// AC97_250_PS instead. +`define AC97_RST_DEL 3'h4 + +///////////////////////////////////////////////////////////////////// +// +// This value indicates for how long the resume signaling (asserting sync) +// should be done. This counter is driven by the AC97_250_PS prescaler. +// This value times 250nS is the duration of the resume signaling. +// The actual value must be incremented by one, as we do not know +// the current state of the prescaler, and must somehow insure we +// meet the minimum 1uS length. This value should probably be never +// changed. Modify the AC97_250_PS instead. +`define AC97_RES_SIG 3'h5 + +///////////////////////////////////////////////////////////////////// +// +// If the bit clock is absent for at least two "predicted" bit +// clock periods (163 nS) we should signal "suspended". +// This value defines how many WISHBONE cycles must pass without +// any change on the bit clock input before we signal "suspended". +// For a 200 MHz WISHBONE clock this would be about (163/5) 33 cycles. +`define AC97_SUSP_DET 6'h21 + +///////////////////////////////////////////////////////////////////// +// +// Select FIFO Depth. For most applications a FIFO depth of 4 should +// be sufficient. For systems with slow interrupt processing or slow +// DMA response or systems with low internal bus bandwidth you might +// want to increase the FIFO sizes to reduce the interrupt/DMA service +// request frequencies. +// Service request frequency can be calculated as follows: +// Channel bandwidth / FIFO size = Service Request Frequency +// For Example: 48KHz / 4 = 12 kHz +// +// Select Input FIFO depth by uncommenting ONE of the following define +// statements: +`define AC97_IN_FIFO_DEPTH_4 +//`define AC97_IN_FIFO_DEPTH_8 +//`define AC97_IN_FIFO_DEPTH_16 +// +// Select Output FIFO depth by uncommenting ONE of the following define +// statements: +`define AC97_OUT_FIFO_DEPTH_4 +//`define AC97_OUT_FIFO_DEPTH_8 +//`define AC97_OUT_FIFO_DEPTH_16 + diff --git a/designs/encrypted_ip/des3_area/ac97_dma_if.v b/designs/encrypted_ip/des3_area/ac97_dma_if.v new file mode 100644 index 000000000..ea6789f3d --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_dma_if.v @@ -0,0 +1,216 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// DMA Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_dma_if.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:49 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:18 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_dma_if(clk, rst, + o3_status, o4_status, o6_status, o7_status, o8_status, o9_status, + o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty, + i3_status, i4_status, i6_status, + i3_full, i4_full, i6_full, + + oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg, + ic0_cfg, ic1_cfg, ic2_cfg, + + dma_req, dma_ack); + +input clk, rst; +input [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status; +input o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty; +input [1:0] i3_status, i4_status, i6_status; +input i3_full, i4_full, i6_full; +input [7:0] oc0_cfg; +input [7:0] oc1_cfg; +input [7:0] oc2_cfg; +input [7:0] oc3_cfg; +input [7:0] oc4_cfg; +input [7:0] oc5_cfg; +input [7:0] ic0_cfg; +input [7:0] ic1_cfg; +input [7:0] ic2_cfg; +output [8:0] dma_req; +input [8:0] dma_ack; + +//////////////////////////////////////////////////////////////////// +// +// DMA Request Modules +// + +ac97_dma_req u0(.clk( clk ), + .rst( rst ), + .cfg( oc0_cfg ), + .status( o3_status ), + .full_empty( o3_empty ), + .dma_req( dma_req[0] ), + .dma_ack( dma_ack[0] ) + ); + +ac97_dma_req u1(.clk( clk ), + .rst( rst ), + .cfg( oc1_cfg ), + .status( o4_status ), + .full_empty( o4_empty ), + .dma_req( dma_req[1] ), + .dma_ack( dma_ack[1] ) + ); + +`ifdef AC97_CENTER +ac97_dma_req u2(.clk( clk ), + .rst( rst ), + .cfg( oc2_cfg ), + .status( o6_status ), + .full_empty( o6_empty ), + .dma_req( dma_req[2] ), + .dma_ack( dma_ack[2] ) + ); +`else +assign dma_req[2] = 1'b0; +`endif + +`ifdef AC97_SURROUND +ac97_dma_req u3(.clk( clk ), + .rst( rst ), + .cfg( oc3_cfg ), + .status( o7_status ), + .full_empty( o7_empty ), + .dma_req( dma_req[3] ), + .dma_ack( dma_ack[3] ) + ); + +ac97_dma_req u4(.clk( clk ), + .rst( rst ), + .cfg( oc4_cfg ), + .status( o8_status ), + .full_empty( o8_empty ), + .dma_req( dma_req[4] ), + .dma_ack( dma_ack[4] ) + ); +`else +assign dma_req[3] = 1'b0; +assign dma_req[4] = 1'b0; +`endif + +`ifdef AC97_LFE +ac97_dma_req u5(.clk( clk ), + .rst( rst ), + .cfg( oc5_cfg ), + .status( o9_status ), + .full_empty( o9_empty ), + .dma_req( dma_req[5] ), + .dma_ack( dma_ack[5] ) + ); +`else +assign dma_req[5] = 1'b0; +`endif + +`ifdef AC97_SIN +ac97_dma_req u6(.clk( clk ), + .rst( rst ), + .cfg( ic0_cfg ), + .status( i3_status ), + .full_empty( i3_full ), + .dma_req( dma_req[6] ), + .dma_ack( dma_ack[6] ) + ); + +ac97_dma_req u7(.clk( clk ), + .rst( rst ), + .cfg( ic1_cfg ), + .status( i4_status ), + .full_empty( i4_full ), + .dma_req( dma_req[7] ), + .dma_ack( dma_ack[7] ) + ); +`else +assign dma_req[6] = 1'b0; +assign dma_req[7] = 1'b0; +`endif + +`ifdef AC97_MICIN +ac97_dma_req u8(.clk( clk ), + .rst( rst ), + .cfg( ic2_cfg ), + .status( i6_status ), + .full_empty( i6_full ), + .dma_req( dma_req[8] ), + .dma_ack( dma_ack[8] ) + ); +`else +assign dma_req[8] = 1'b0; +`endif + +endmodule + + diff --git a/designs/encrypted_ip/des3_area/ac97_dma_req.v b/designs/encrypted_ip/des3_area/ac97_dma_req.v new file mode 100644 index 000000000..95fbf3da6 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_dma_req.v @@ -0,0 +1,115 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// DMA Request Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_dma_req.v,v 1.3 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:49 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:16 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_dma_req(clk, rst, cfg, status, full_empty, dma_req, dma_ack); +input clk, rst; +input [7:0] cfg; +input [1:0] status; +input full_empty; +output dma_req; +input dma_ack; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// +reg dma_req_d; +reg dma_req_r1; +reg dma_req; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(cfg or status or full_empty) + case(cfg[5:4]) // synopsys parallel_case full_case + // REQ = Ch_EN & DMA_EN & Status + // 1/4 full/empty + 2'h2: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status == 2'h0)); + // 1/2 full/empty + 2'h1: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status[1] == 1'h0)); + // 3/4 full/empty + 2'h0: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status < 2'h3)); + 2'h3: dma_req_d = cfg[0] & cfg[6] & full_empty; + endcase + +always @(posedge clk) + dma_req_r1 <= #1 dma_req_d & !dma_ack; + +always @(posedge clk or negedge rst) + if(!rst) dma_req <= #1 1'b0; + else + if(dma_req_r1 & dma_req_d & !dma_ack) dma_req <= #1 1'b1; + else + if(dma_ack) dma_req <= #1 1'b0; + +endmodule + diff --git a/designs/encrypted_ip/des3_area/ac97_fifo_ctrl.v b/designs/encrypted_ip/des3_area/ac97_fifo_ctrl.v new file mode 100644 index 000000000..3f0c0cc5b --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_fifo_ctrl.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// FIFO Control Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_fifo_ctrl.v,v 1.3 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:49 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:18 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_fifo_ctrl( clk, + valid, ch_en, srs, full_empty, req, crdy, + en_out, en_out_l + ); +input clk; +input valid; +input ch_en; // Channel Enable +input srs; // Sample Rate Select +input full_empty; // Fifo Status +input req; // Codec Request +input crdy; // Codec Ready +output en_out; // Output read/write pulse +output en_out_l; // Latched Output + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg en_out_l, en_out_l2; +reg full_empty_r; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + if(!valid) full_empty_r <= #1 full_empty; + +always @(posedge clk) + if(valid & ch_en & !full_empty_r & crdy & (!srs | (srs & req) ) ) + en_out_l <= #1 1'b1; + else + if(!valid & !(ch_en & !full_empty_r & crdy & (!srs | (srs & req) )) ) + en_out_l <= #1 1'b0; + +always @(posedge clk) + en_out_l2 <= #1 en_out_l & valid; + +assign en_out = en_out_l & !en_out_l2 & valid; + +endmodule diff --git a/designs/encrypted_ip/des3_area/ac97_in_fifo.v b/designs/encrypted_ip/des3_area/ac97_in_fifo.v new file mode 100644 index 000000000..b3b10b205 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_in_fifo.v @@ -0,0 +1,339 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Output FIFO //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_in_fifo.v,v 1.5 2002-11-14 17:10:12 rudi Exp $ +// +// $Date: 2002-11-14 17:10:12 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.4 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.3 2002/03/11 03:21:22 rudi +// +// - Added defines to select fifo depth between 4, 8 and 16 entries. +// +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:14 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +`ifdef AC97_IN_FIFO_DEPTH_4 + +// 4 entry deep verion of the input FIFO + +module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [19:0] din; +input we; +output [31:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:3]; +reg [31:0] dout; + +reg [3:0] wp; +reg [2:0] rp; + +wire [3:0] wp_p1; + +reg [1:0] status; +reg [15:0] din_tmp1; +reg [31:0] din_tmp; +wire m16b; +reg full, empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 4'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2); + +always @(posedge clk) + if(!en) rp <= #1 3'h0; + else + if(re) rp <= #1 rp + 3'h1; + +always @(posedge clk) + status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1); + +always @(posedge clk) + empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0); + +always @(posedge clk) + full <= #1 (wp[2:1] == rp[1:0]) & (wp[3] != rp[2]); + +// Fifo Output +always @(posedge clk) + dout <= #1 mem[ rp[1:0] ]; + +// Fifo Input Half Word Latch +always @(posedge clk) + if(we & !wp[0]) din_tmp1 <= #1 din[19:4]; + +always @(mode or din_tmp1 or din) + case(mode) // synopsys parallel_case full_case + 2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output + 2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output + 2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output + endcase + +always @(posedge clk) + if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp; + +endmodule + +`endif + +`ifdef AC97_IN_FIFO_DEPTH_8 + +// 8 entry deep verion of the input FIFO + +module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [19:0] din; +input we; +output [31:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:7]; +reg [31:0] dout; + +reg [4:0] wp; +reg [3:0] rp; + +wire [4:0] wp_p1; + +reg [1:0] status; +reg [15:0] din_tmp1; +reg [31:0] din_tmp; +wire m16b; +reg full, empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 5'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2); + +always @(posedge clk) + if(!en) rp <= #1 4'h0; + else + if(re) rp <= #1 rp + 4'h1; + +always @(posedge clk) + status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1); + +always @(posedge clk) + empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0); + +always @(posedge clk) + full <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]); + +// Fifo Output +always @(posedge clk) + dout <= #1 mem[ rp[2:0] ]; + +// Fifo Input Half Word Latch +always @(posedge clk) + if(we & !wp[0]) din_tmp1 <= #1 din[19:4]; + +always @(mode or din_tmp1 or din) + case(mode) // synopsys parallel_case full_case + 2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output + 2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output + 2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output + endcase + +always @(posedge clk) + if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[3:1] ] <= #1 din_tmp; + +endmodule + +`endif + + +`ifdef AC97_IN_FIFO_DEPTH_16 + +// 16 entry deep verion of the input FIFO + +module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [19:0] din; +input we; +output [31:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:15]; +reg [31:0] dout; + +reg [5:0] wp; +reg [4:0] rp; + +wire [5:0] wp_p1; + +reg [1:0] status; +reg [15:0] din_tmp1; +reg [31:0] din_tmp; +wire m16b; +reg full, empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 6'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2); + +always @(posedge clk) + if(!en) rp <= #1 5'h0; + else + if(re) rp <= #1 rp + 5'h1; + +always @(posedge clk) + status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1); + +always @(posedge clk) + empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0); + +always @(posedge clk) + full <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]); + +// Fifo Output +always @(posedge clk) + dout <= #1 mem[ rp[3:0] ]; + +// Fifo Input Half Word Latch +always @(posedge clk) + if(we & !wp[0]) din_tmp1 <= #1 din[19:4]; + +always @(mode or din_tmp1 or din) + case(mode) // synopsys parallel_case full_case + 2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output + 2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output + 2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output + endcase + +always @(posedge clk) + if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[4:1] ] <= #1 din_tmp; + +endmodule + +`endif diff --git a/designs/encrypted_ip/des3_area/ac97_int.v b/designs/encrypted_ip/des3_area/ac97_int.v new file mode 100644 index 000000000..86fda0ed1 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_int.v @@ -0,0 +1,124 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Interrupt Logic //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_int.v,v 1.3 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:18 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_int(clk, rst, + + // Register File Interface + int_set, + + // FIFO Interface + cfg, status, full_empty, full, empty, re, we + ); + +input clk, rst; +output [2:0] int_set; + +input [7:0] cfg; +input [1:0] status; +input full_empty, full, empty, re, we; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [2:0] int_set; + +//////////////////////////////////////////////////////////////////// +// +// Interrupt Logic +// + +always @(posedge clk or negedge rst) + if(!rst) int_set[0] <= #1 1'b0; + else + case(cfg[5:4]) // synopsys parallel_case full_case + // 1/4 full/empty + 2'h2: int_set[0] <= #1 cfg[0] & (full_empty | (status == 2'h0)); + // 1/2 full/empty + 2'h1: int_set[0] <= #1 cfg[0] & (full_empty | (status[1] == 1'h0)); + // 3/4 full/empty + 2'h0: int_set[0] <= #1 cfg[0] & (full_empty | (status < 2'h3)); + 2'h3: int_set[0] <= #1 cfg[0] & full_empty; + endcase + +always @(posedge clk or negedge rst) + if(!rst) int_set[1] <= #1 1'b0; + else + if(empty & re) int_set[1] <= #1 1'b1; + else int_set[1] <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) int_set[2] <= #1 1'b0; + else + if(full & we) int_set[2] <= #1 1'b1; + else int_set[2] <= #1 1'b0; + +endmodule diff --git a/designs/encrypted_ip/des3_area/ac97_out_fifo.v b/designs/encrypted_ip/des3_area/ac97_out_fifo.v new file mode 100644 index 000000000..ae981c195 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_out_fifo.v @@ -0,0 +1,344 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Output FIFO //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_out_fifo.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/03/11 03:21:22 rudi +// +// - Added defines to select fifo depth between 4, 8 and 16 entries. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:16 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +`ifdef AC97_OUT_FIFO_DEPTH_4 + +// 4 Entry Deep version of the Output FIFO + +module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [31:0] din; +input we; +output [19:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:3]; + +reg [2:0] wp; +reg [3:0] rp; + +wire [2:0] wp_p1; + +reg [1:0] status; +reg [19:0] dout; +wire [31:0] dout_tmp; +wire [15:0] dout_tmp1; +wire m16b; +reg empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 3'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = wp + 3'h1; + +always @(posedge clk) + if(!en) rp <= #1 4'h0; + else + if(re & m16b) rp <= #1 rp + 4'h1; + else + if(re & !m16b) rp <= #1 rp + 4'h2; + +always @(posedge clk) + status <= #1 (wp[1:0] - rp[2:1]) - 2'h1; + +wire [3:0] rp_p1 = rp[3:0] + 4'h1; + +always @(posedge clk) + empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1); + +assign full = (wp[1:0] == rp[2:1]) & (wp[2] != rp[3]); + +// Fifo Output +assign dout_tmp = mem[ rp[2:1] ]; + +// Fifo Output Half Word Select +assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0]; + +always @(posedge clk) + if(!en) dout <= #1 20'h0; + else + if(re) + case(mode) // synopsys parallel_case full_case + 2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output + 2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output + 2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output + endcase + +always @(posedge clk) + if(we) mem[wp[1:0]] <= #1 din; + +endmodule + +`endif + +`ifdef AC97_OUT_FIFO_DEPTH_8 + +// 8 Entry Deep version of the Output FIFO + +module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [31:0] din; +input we; +output [19:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:7]; + +reg [3:0] wp; +reg [4:0] rp; + +wire [3:0] wp_p1; + +reg [1:0] status; +reg [19:0] dout; +wire [31:0] dout_tmp; +wire [15:0] dout_tmp1; +wire m16b; +reg empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 4'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = wp + 4'h1; + +always @(posedge clk) + if(!en) rp <= #1 5'h0; + else + if(re & m16b) rp <= #1 rp + 5'h1; + else + if(re & !m16b) rp <= #1 rp + 5'h2; + +always @(posedge clk) + status <= #1 (wp[2:1] - rp[3:2]) - 2'h1; + +wire [4:0] rp_p1 = rp[4:0] + 5'h1; + +always @(posedge clk) + empty <= #1 (rp_p1[4:1] == wp[3:0]) & (m16b ? rp_p1[0] : 1'b1); + +assign full = (wp[2:0] == rp[3:1]) & (wp[3] != rp[4]); + +// Fifo Output +assign dout_tmp = mem[ rp[3:1] ]; + +// Fifo Output Half Word Select +assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0]; + +always @(posedge clk) + if(!en) dout <= #1 20'h0; + else + if(re) + case(mode) // synopsys parallel_case full_case + 2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output + 2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output + 2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output + endcase + + +always @(posedge clk) + if(we) mem[wp[2:0]] <= #1 din; + +endmodule + +`endif + + +`ifdef AC97_OUT_FIFO_DEPTH_16 + +// 16 Entry Deep version of the Output FIFO + +module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [31:0] din; +input we; +output [19:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:15]; + +reg [4:0] wp; +reg [5:0] rp; + +wire [4:0] wp_p1; + +reg [1:0] status; +reg [19:0] dout; +wire [31:0] dout_tmp; +wire [15:0] dout_tmp1; +wire m16b; +reg empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 5'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = wp + 4'h1; + +always @(posedge clk) + if(!en) rp <= #1 6'h0; + else + if(re & m16b) rp <= #1 rp + 6'h1; + else + if(re & !m16b) rp <= #1 rp + 6'h2; + +always @(posedge clk) + status <= #1 (wp[3:2] - rp[4:3]) - 2'h1; + +wire [5:0] rp_p1 = rp[5:0] + 6'h1; + +always @(posedge clk) + empty <= #1 (rp_p1[5:1] == wp[4:0]) & (m16b ? rp_p1[0] : 1'b1); + +assign full = (wp[3:0] == rp[4:1]) & (wp[4] != rp[5]); + +// Fifo Output +assign dout_tmp = mem[ rp[4:1] ]; + +// Fifo Output Half Word Select +assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0]; + +always @(posedge clk) + if(!en) dout <= #1 20'h0; + else + if(re) + case(mode) // synopsys parallel_case full_case + 2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output + 2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output + 2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output + endcase + + +always @(posedge clk) + if(we) mem[wp[3:0]] <= #1 din; + +endmodule + +`endif diff --git a/designs/encrypted_ip/des3_area/ac97_prc.v b/designs/encrypted_ip/des3_area/ac97_prc.v new file mode 100644 index 000000000..7f7b76256 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_prc.v @@ -0,0 +1,332 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// PCM Request Controller //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_prc.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:17 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_prc(clk, rst, + + // SR Slot Interface + valid, in_valid, out_slt0, + in_slt0, in_slt1, + + // Codec Register Access + crac_valid, crac_wr, + + // Channel Configuration + oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg, + ic0_cfg, ic1_cfg, ic2_cfg, + + // FIFO Status + o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, + o9_empty, i3_full, i4_full, i6_full, + + // FIFO Control + o3_re, o4_re, o6_re, o7_re, o8_re, o9_re, + i3_we, i4_we, i6_we + + ); +input clk, rst; + +input valid; +input [2:0] in_valid; +output [15:0] out_slt0; +input [15:0] in_slt0; +input [19:0] in_slt1; + +input crac_valid; +input crac_wr; + +input [7:0] oc0_cfg; +input [7:0] oc1_cfg; +input [7:0] oc2_cfg; +input [7:0] oc3_cfg; +input [7:0] oc4_cfg; +input [7:0] oc5_cfg; + +input [7:0] ic0_cfg; +input [7:0] ic1_cfg; +input [7:0] ic2_cfg; + +input o3_empty; +input o4_empty; +input o6_empty; +input o7_empty; +input o8_empty; +input o9_empty; +input i3_full; +input i4_full; +input i6_full; + +output o3_re; +output o4_re; +output o6_re; +output o7_re; +output o8_re; +output o9_re; +output i3_we; +output i4_we; +output i6_we; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire o3_re_l; +wire o4_re_l; +wire o6_re_l; +wire o7_re_l; +wire o8_re_l; +wire o9_re_l; + +reg crac_valid_r; +reg crac_wr_r; + +//////////////////////////////////////////////////////////////////// +// +// Output Tag Assembly +// + +assign out_slt0[15] = |out_slt0[14:6]; + +assign out_slt0[14] = crac_valid_r; +assign out_slt0[13] = crac_wr_r; + +assign out_slt0[12] = o3_re_l; +assign out_slt0[11] = o4_re_l; +assign out_slt0[10] = 1'b0; +assign out_slt0[09] = o6_re_l; +assign out_slt0[08] = o7_re_l; +assign out_slt0[07] = o8_re_l; +assign out_slt0[06] = o9_re_l; +assign out_slt0[5:0] = 6'h0; + +//////////////////////////////////////////////////////////////////// +// +// FIFO Control +// + +always @(posedge clk) + if(valid) crac_valid_r <= #1 crac_valid; + +always @(posedge clk) + if(valid) crac_wr_r <= #1 crac_valid & crac_wr; + +// Output Channel 0 (Out Slot 3) +ac97_fifo_ctrl u0( + .clk( clk ), + .valid( valid ), + .ch_en( oc0_cfg[0] ), + .srs( oc0_cfg[1] ), + .full_empty( o3_empty ), + .req( ~in_slt1[11] ), + .crdy( in_slt0[15] ), + .en_out( o3_re ), + .en_out_l( o3_re_l ) + ); + +// Output Channel 1 (Out Slot 4) +ac97_fifo_ctrl u1( + .clk( clk ), + .valid( valid ), + .ch_en( oc1_cfg[0] ), + .srs( oc1_cfg[1] ), + .full_empty( o4_empty ), + .req( ~in_slt1[10] ), + .crdy( in_slt0[15] ), + .en_out( o4_re ), + .en_out_l( o4_re_l ) + ); + +`ifdef AC97_CENTER +// Output Channel 2 (Out Slot 6) +ac97_fifo_ctrl u2( + .clk( clk ), + .valid( valid ), + .ch_en( oc2_cfg[0] ), + .srs( oc2_cfg[1] ), + .full_empty( o6_empty ), + .req( ~in_slt1[8] ), + .crdy( in_slt0[15] ), + .en_out( o6_re ), + .en_out_l( o6_re_l ) + ); +`else +assign o6_re = 1'b0; +assign o6_re_l = 1'b0; +`endif + +`ifdef AC97_SURROUND +// Output Channel 3 (Out Slot 7) +ac97_fifo_ctrl u3( + .clk( clk ), + .valid( valid ), + .ch_en( oc3_cfg[0] ), + .srs( oc3_cfg[1] ), + .full_empty( o7_empty ), + .req( ~in_slt1[7] ), + .crdy( in_slt0[15] ), + .en_out( o7_re ), + .en_out_l( o7_re_l ) + ); + +// Output Channel 4 (Out Slot 8) +ac97_fifo_ctrl u4( + .clk( clk ), + .valid( valid ), + .ch_en( oc4_cfg[0] ), + .srs( oc4_cfg[1] ), + .full_empty( o8_empty ), + .req( ~in_slt1[6] ), + .crdy( in_slt0[15] ), + .en_out( o8_re ), + .en_out_l( o8_re_l ) + ); +`else +assign o7_re = 1'b0; +assign o7_re_l = 1'b0; +assign o8_re = 1'b0; +assign o8_re_l = 1'b0; +`endif + +`ifdef AC97_LFE +// Output Channel 5 (Out Slot 9) +ac97_fifo_ctrl u5( + .clk( clk ), + .valid( valid ), + .ch_en( oc5_cfg[0] ), + .srs( oc5_cfg[1] ), + .full_empty( o9_empty ), + .req( ~in_slt1[5] ), + .crdy( in_slt0[15] ), + .en_out( o9_re ), + .en_out_l( o9_re_l ) + ); +`else +assign o9_re = 1'b0; +assign o9_re_l = 1'b0; +`endif + +`ifdef AC97_SIN +// Input Channel 0 (In Slot 3) +ac97_fifo_ctrl u6( + .clk( clk ), + .valid( in_valid[0] ), + .ch_en( ic0_cfg[0] ), + .srs( ic0_cfg[1] ), + .full_empty( i3_full ), + .req( in_slt0[12] ), + .crdy( in_slt0[15] ), + .en_out( i3_we ), + .en_out_l( ) + ); + +// Input Channel 1 (In Slot 4) +ac97_fifo_ctrl u7( + .clk( clk ), + .valid( in_valid[1] ), + .ch_en( ic1_cfg[0] ), + .srs( ic1_cfg[1] ), + .full_empty( i4_full ), + .req( in_slt0[11] ), + .crdy( in_slt0[15] ), + .en_out( i4_we ), + .en_out_l( ) + ); +`else +assign i3_we = 1'b0; +assign i4_we = 1'b0; +`endif + +`ifdef AC97_MICIN +// Input Channel 2 (In Slot 6) +ac97_fifo_ctrl u8( + .clk( clk ), + .valid( in_valid[2] ), + .ch_en( ic2_cfg[0] ), + .srs( ic2_cfg[1] ), + .full_empty( i6_full ), + .req( in_slt0[9] ), + .crdy( in_slt0[15] ), + .en_out( i6_we ), + .en_out_l( ) + ); +`else +assign i6_we = 1'b0; +`endif + +endmodule + + diff --git a/designs/encrypted_ip/des3_area/ac97_rf.v b/designs/encrypted_ip/des3_area/ac97_rf.v new file mode 100644 index 000000000..fd9785d3f --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_rf.v @@ -0,0 +1,302 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_rf.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:17 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_rf(clk, rst, + + adr, rf_dout, rf_din, + rf_we, rf_re, int, ac97_rst_force, + resume_req, suspended, + + crac_we, crac_din, crac_out, + crac_rd_done, crac_wr_done, + + oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg, + ic0_cfg, ic1_cfg, ic2_cfg, + oc0_int_set, oc1_int_set, oc2_int_set, oc3_int_set, + oc4_int_set, oc5_int_set, + ic0_int_set, ic1_int_set, ic2_int_set + + ); + +input clk,rst; + +input [3:0] adr; +output [31:0] rf_dout; +input [31:0] rf_din; +input rf_we; +input rf_re; +output int; +output ac97_rst_force; +output resume_req; +input suspended; + +output crac_we; +input [15:0] crac_din; +output [31:0] crac_out; +input crac_rd_done, crac_wr_done; + +output [7:0] oc0_cfg; +output [7:0] oc1_cfg; +output [7:0] oc2_cfg; +output [7:0] oc3_cfg; +output [7:0] oc4_cfg; +output [7:0] oc5_cfg; + +output [7:0] ic0_cfg; +output [7:0] ic1_cfg; +output [7:0] ic2_cfg; + +input [2:0] oc0_int_set; +input [2:0] oc1_int_set; +input [2:0] oc2_int_set; +input [2:0] oc3_int_set; +input [2:0] oc4_int_set; +input [2:0] oc5_int_set; +input [2:0] ic0_int_set; +input [2:0] ic1_int_set; +input [2:0] ic2_int_set; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] rf_dout; + +reg [31:0] csr_r; +reg [31:0] occ0_r; +reg [15:0] occ1_r; +reg [23:0] icc_r; +reg [31:0] crac_r; +reg [28:0] intm_r; +reg [28:0] ints_r; +reg int; +wire [28:0] int_all; +wire [31:0] csr, occ0, occ1, icc, crac, intm, ints; +reg [15:0] crac_dout_r; +reg ac97_rst_force; +reg resume_req; + +// Aliases +assign csr = {30'h0, suspended, 1'h0}; +assign occ0 = occ0_r; +assign occ1 = {16'h0, occ1_r}; +assign icc = {8'h0, icc_r}; +assign crac = {crac_r[7], 8'h0, crac_r[6:0], crac_din}; +assign intm = {3'h0, intm_r}; +assign ints = {3'h0, ints_r}; + +assign crac_out = {crac_r[7], 8'h0, crac_r[6:0], crac_dout_r}; + +//////////////////////////////////////////////////////////////////// +// +// Register WISHBONE Interface +// + +always @(adr or csr or occ0 or occ1 or icc or crac or intm or ints) + case(adr[2:0]) // synopsys parallel_case full_case + 0: rf_dout = csr; + 1: rf_dout = occ0; + 2: rf_dout = occ1; + 3: rf_dout = icc; + 4: rf_dout = crac; + 5: rf_dout = intm; + 6: rf_dout = ints; + endcase + +always @(posedge clk or negedge rst) + if(!rst) csr_r <= #1 1'b0; + else + if(rf_we & (adr[2:0]==3'h0)) csr_r <= #1 rf_din; + +always @(posedge clk) + if(rf_we & (adr[2:0]==3'h0)) ac97_rst_force <= #1 rf_din[0]; + else ac97_rst_force <= #1 1'b0; + +always @(posedge clk) + if(rf_we & (adr[2:0]==3'h0)) resume_req <= #1 rf_din[1]; + else resume_req <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) occ0_r <= #1 1'b0; + else + if(rf_we & (adr[2:0]==3'h1)) occ0_r <= #1 rf_din; + +always @(posedge clk or negedge rst) + if(!rst) occ1_r <= #1 1'b0; + else + if(rf_we & (adr[2:0]==3'h2)) occ1_r <= #1 rf_din[23:0]; + +always @(posedge clk or negedge rst) + if(!rst) icc_r <= #1 1'b0; + else + if(rf_we & (adr[2:0]==3'h3)) icc_r <= #1 rf_din[23:0]; + +assign crac_we = rf_we & (adr[2:0]==3'h4); + +always @(posedge clk or negedge rst) + if(!rst) crac_r <= #1 1'b0; + else + if(crac_we) crac_r <= #1 {rf_din[31], rf_din[22:16]}; + +always @(posedge clk) + if(crac_we) crac_dout_r <= #1 rf_din[15:0]; + +always @(posedge clk or negedge rst) + if(!rst) intm_r <= #1 1'b0; + else + if(rf_we & (adr[2:0]==3'h5)) intm_r <= #1 rf_din[28:0]; + +// Interrupt Source Register +always @(posedge clk or negedge rst) + if(!rst) ints_r <= #1 1'b0; + else + if(rf_re & (adr[2:0]==3'h6)) ints_r <= #1 1'b0; + else + begin + if(crac_rd_done) ints_r[0] <= #1 1'b1; + if(crac_wr_done) ints_r[1] <= #1 1'b1; + if(oc0_int_set[0]) ints_r[2] <= #1 1'b1; + if(oc0_int_set[1]) ints_r[3] <= #1 1'b1; + if(oc0_int_set[2]) ints_r[4] <= #1 1'b1; + if(oc1_int_set[0]) ints_r[5] <= #1 1'b1; + if(oc1_int_set[1]) ints_r[6] <= #1 1'b1; + if(oc1_int_set[2]) ints_r[7] <= #1 1'b1; +`ifdef AC97_CENTER + if(oc2_int_set[0]) ints_r[8] <= #1 1'b1; + if(oc2_int_set[1]) ints_r[9] <= #1 1'b1; + if(oc2_int_set[2]) ints_r[10] <= #1 1'b1; +`endif + +`ifdef AC97_SURROUND + if(oc3_int_set[0]) ints_r[11] <= #1 1'b1; + if(oc3_int_set[1]) ints_r[12] <= #1 1'b1; + if(oc3_int_set[2]) ints_r[13] <= #1 1'b1; + if(oc4_int_set[0]) ints_r[14] <= #1 1'b1; + if(oc4_int_set[1]) ints_r[15] <= #1 1'b1; + if(oc4_int_set[2]) ints_r[16] <= #1 1'b1; +`endif + +`ifdef AC97_LFE + if(oc5_int_set[0]) ints_r[17] <= #1 1'b1; + if(oc5_int_set[1]) ints_r[18] <= #1 1'b1; + if(oc5_int_set[2]) ints_r[19] <= #1 1'b1; +`endif + +`ifdef AC97_SIN + if(ic0_int_set[0]) ints_r[20] <= #1 1'b1; + if(ic0_int_set[1]) ints_r[21] <= #1 1'b1; + if(ic0_int_set[2]) ints_r[22] <= #1 1'b1; + if(ic1_int_set[0]) ints_r[23] <= #1 1'b1; + if(ic1_int_set[1]) ints_r[24] <= #1 1'b1; + if(ic1_int_set[2]) ints_r[25] <= #1 1'b1; +`endif + +`ifdef AC97_MICIN + if(ic2_int_set[0]) ints_r[26] <= #1 1'b1; + if(ic2_int_set[1]) ints_r[27] <= #1 1'b1; + if(ic2_int_set[2]) ints_r[28] <= #1 1'b1; +`endif + end + +//////////////////////////////////////////////////////////////////// +// +// Register Internal Interface +// + +assign oc0_cfg = occ0[7:0]; +assign oc1_cfg = occ0[15:8]; +assign oc2_cfg = occ0[23:16]; +assign oc3_cfg = occ0[31:24]; +assign oc4_cfg = occ1[7:0]; +assign oc5_cfg = occ1[15:8]; + +assign ic0_cfg = icc[7:0]; +assign ic1_cfg = icc[15:8]; +assign ic2_cfg = icc[23:16]; + +//////////////////////////////////////////////////////////////////// +// +// Interrupt Generation +// + +assign int_all = intm_r & ints_r; + +always @(posedge clk) + int <= #1 |int_all; + +endmodule diff --git a/designs/encrypted_ip/des3_area/ac97_rst.v b/designs/encrypted_ip/des3_area/ac97_rst.v new file mode 100644 index 000000000..ac791d5bb --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_rst.v @@ -0,0 +1,98 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller Reset Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_rst.v,v 1.1 2001-08-03 06:54:50 rudi Exp $ +// +// $Date: 2001-08-03 06:54:50 $ +// $Revision: 1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/05/19 02:29:19 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_rst(clk, rst, rst_force, ps_ce, ac97_rst_); +input clk, rst; +input rst_force; +output ps_ce; +output ac97_rst_; + +reg ac97_rst_; +reg [2:0] cnt; +wire ce; +wire to; +reg [5:0] ps_cnt; +wire ps_ce; + +always @(posedge clk or negedge rst) + if(!rst) ac97_rst_ <= #1 0; + else + if(rst_force) ac97_rst_ <= #1 0; + else + if(to) ac97_rst_ <= #1 1; + +assign to = (cnt == `AC97_RST_DEL); + +always @(posedge clk or negedge rst) + if(!rst) cnt <= #1 0; + else + if(rst_force) cnt <= #1 0; + else + if(ce) cnt <= #1 cnt + 1; + +assign ce = ps_ce & (cnt != `AC97_RST_DEL); + +always @(posedge clk or negedge rst) + if(!rst) ps_cnt <= #1 0; + else + if(ps_ce | rst_force) ps_cnt <= #1 0; + else ps_cnt <= #1 ps_cnt + 1; + +assign ps_ce = (ps_cnt == `AC97_250_PS); + +endmodule diff --git a/designs/encrypted_ip/des3_area/ac97_sin.v b/designs/encrypted_ip/des3_area/ac97_sin.v new file mode 100644 index 000000000..03c392fe3 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_sin.v @@ -0,0 +1,141 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Serial Input Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_sin.v,v 1.2 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:15 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_sin(clk, rst, + + out_le, slt0, slt1, slt2, slt3, slt4, + slt6, + + sdata_in + ); + +input clk, rst; + +// -------------------------------------- +// Misc Signals +input [5:0] out_le; +output [15:0] slt0; +output [19:0] slt1; +output [19:0] slt2; +output [19:0] slt3; +output [19:0] slt4; +output [19:0] slt6; + +// -------------------------------------- +// AC97 Codec Interface +input sdata_in; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg sdata_in_r; +reg [19:0] sr; + +reg [15:0] slt0; +reg [19:0] slt1; +reg [19:0] slt2; +reg [19:0] slt3; +reg [19:0] slt4; +reg [19:0] slt6; + +//////////////////////////////////////////////////////////////////// +// +// Output Registers +// + +always @(posedge clk) + if(out_le[0]) slt0 <= #1 sr[15:0]; + +always @(posedge clk) + if(out_le[1]) slt1 <= #1 sr; + +always @(posedge clk) + if(out_le[2]) slt2 <= #1 sr; + +always @(posedge clk) + if(out_le[3]) slt3 <= #1 sr; + +always @(posedge clk) + if(out_le[4]) slt4 <= #1 sr; + +always @(posedge clk) + if(out_le[5]) slt6 <= #1 sr; + +//////////////////////////////////////////////////////////////////// +// +// Serial Shift Register +// + +always @(negedge clk) + sdata_in_r <= #1 sdata_in; + +always @(posedge clk) + sr <= #1 {sr[18:0], sdata_in_r }; + +endmodule + + diff --git a/designs/encrypted_ip/des3_area/ac97_soc.v b/designs/encrypted_ip/des3_area/ac97_soc.v new file mode 100644 index 000000000..ec0cc0a8d --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_soc.v @@ -0,0 +1,201 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Serial Output Controller //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_soc.v,v 1.3 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:15 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_soc(clk, wclk, rst, + ps_ce, resume, suspended, + sync, out_le, in_valid, ld, valid + ); + +input clk, wclk, rst; +input ps_ce; +input resume; +output suspended; +output sync; +output [5:0] out_le; +output [2:0] in_valid; +output ld; +output valid; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [7:0] cnt; +reg sync_beat; +reg sync_resume; +reg [5:0] out_le; +reg ld; +reg valid; +reg [2:0] in_valid; +reg bit_clk_r; +reg bit_clk_r1; +reg bit_clk_e; +reg suspended; +wire to; +reg [5:0] to_cnt; +reg [3:0] res_cnt; +wire resume_done; + +assign sync = sync_beat | sync_resume; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk or negedge rst) + if(!rst) cnt <= #1 8'hff; + else + if(suspended) cnt <= #1 8'hff; + else cnt <= #1 cnt + 8'h1; + +always @(posedge clk) + ld <= #1 (cnt == 8'h00); + +always @(posedge clk) + sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10)); + +always @(posedge clk) + valid <= #1 (cnt > 8'h39); + +always @(posedge clk) + out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable + +always @(posedge clk) + out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable + +always @(posedge clk) + out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable + +always @(posedge clk) + out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable + +always @(posedge clk) + out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable + +always @(posedge clk) + out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable + +always @(posedge clk) + in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid + +always @(posedge clk) + in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid + +always @(posedge clk) + in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid + +//////////////////////////////////////////////////////////////////// +// +// Suspend Detect +// + +always @(posedge wclk) + bit_clk_r <= #1 clk; + +always @(posedge wclk) + bit_clk_r1 <= #1 bit_clk_r; + +always @(posedge wclk) + bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1); + +always @(posedge wclk) + suspended <= #1 to; + +assign to = (to_cnt == `AC97_SUSP_DET); + +always @(posedge wclk or negedge rst) + if(!rst) to_cnt <= #1 6'h0; + else + if(bit_clk_e) to_cnt <= #1 6'h0; + else + if(!to) to_cnt <= #1 to_cnt + 6'h1; + +//////////////////////////////////////////////////////////////////// +// +// Resume Signaling +// + +always @(posedge wclk or negedge rst) + if(!rst) sync_resume <= #1 1'b0; + else + if(resume_done) sync_resume <= #1 1'b0; + else + if(suspended & resume) sync_resume <= #1 1'b1; + +assign resume_done = (res_cnt == `AC97_RES_SIG); + +always @(posedge wclk) + if(!sync_resume) res_cnt <= #1 4'h0; + else + if(ps_ce) res_cnt <= #1 res_cnt + 4'h1; + +endmodule diff --git a/designs/encrypted_ip/des3_area/ac97_sout.v b/designs/encrypted_ip/des3_area/ac97_sout.v new file mode 100644 index 000000000..3a1312331 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_sout.v @@ -0,0 +1,179 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Serial Output Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_sout.v,v 1.2 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:15 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_sout(clk, rst, + + so_ld, slt0, slt1, slt2, slt3, slt4, + slt6, slt7, slt8, slt9, + + sdata_out + ); + +input clk, rst; + +// -------------------------------------- +// Misc Signals +input so_ld; +input [15:0] slt0; +input [19:0] slt1; +input [19:0] slt2; +input [19:0] slt3; +input [19:0] slt4; +input [19:0] slt6; +input [19:0] slt7; +input [19:0] slt8; +input [19:0] slt9; + +// -------------------------------------- +// AC97 Codec Interface +output sdata_out; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire sdata_out; + +reg [15:0] slt0_r; +reg [19:0] slt1_r; +reg [19:0] slt2_r; +reg [19:0] slt3_r; +reg [19:0] slt4_r; +reg [19:0] slt5_r; +reg [19:0] slt6_r; +reg [19:0] slt7_r; +reg [19:0] slt8_r; +reg [19:0] slt9_r; +reg [19:0] slt10_r; +reg [19:0] slt11_r; +reg [19:0] slt12_r; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +//////////////////////////////////////////////////////////////////// +// +// Serial Shift Register +// + +assign sdata_out = slt0_r[15]; + +always @(posedge clk) + if(so_ld) slt0_r <= #1 slt0; + else slt0_r <= #1 {slt0_r[14:0], slt1_r[19]}; + +always @(posedge clk) + if(so_ld) slt1_r <= #1 slt1; + else slt1_r <= #1 {slt1_r[18:0], slt2_r[19]}; + +always @(posedge clk) + if(so_ld) slt2_r <= #1 slt2; + else slt2_r <= #1 {slt2_r[18:0], slt3_r[19]}; + +always @(posedge clk) + if(so_ld) slt3_r <= #1 slt3; + else slt3_r <= #1 {slt3_r[18:0], slt4_r[19]}; + +always @(posedge clk) + if(so_ld) slt4_r <= #1 slt4; + else slt4_r <= #1 {slt4_r[18:0], slt5_r[19]}; + +always @(posedge clk) + if(so_ld) slt5_r <= #1 20'h0; + else slt5_r <= #1 {slt5_r[18:0], slt6_r[19]}; + +always @(posedge clk) + if(so_ld) slt6_r <= #1 slt6; + else slt6_r <= #1 {slt6_r[18:0], slt7_r[19]}; + +always @(posedge clk) + if(so_ld) slt7_r <= #1 slt7; + else slt7_r <= #1 {slt7_r[18:0], slt8_r[19]}; + +always @(posedge clk) + if(so_ld) slt8_r <= #1 slt8; + else slt8_r <= #1 {slt8_r[18:0], slt9_r[19]}; + +always @(posedge clk) + if(so_ld) slt9_r <= #1 slt9; + else slt9_r <= #1 {slt9_r[18:0], slt10_r[19]}; + +always @(posedge clk) + if(so_ld) slt10_r <= #1 20'h0; + else slt10_r <= #1 {slt10_r[18:0], slt11_r[19]}; + +always @(posedge clk) + if(so_ld) slt11_r <= #1 20'h0; + else slt11_r <= #1 {slt11_r[18:0], slt12_r[19]}; + +always @(posedge clk) + if(so_ld) slt12_r <= #1 20'h0; + else slt12_r <= #1 {slt12_r[18:0], 1'b0 }; + +endmodule + diff --git a/designs/encrypted_ip/des3_area/ac97_top.v b/designs/encrypted_ip/des3_area/ac97_top.v new file mode 100644 index 000000000..6f2923e25 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_top.v @@ -0,0 +1,757 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_top.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:14 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_top(clk_i, rst_i, + + wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, + + int_o, dma_req_o, dma_ack_i, + suspended_o, + + bit_clk_pad_i, sync_pad_o, sdata_pad_o, sdata_pad_i, + ac97_reset_pad_o_ + ); + +input clk_i, rst_i; + +// -------------------------------------- +// WISHBONE SLAVE INTERFACE +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input [31:0] wb_addr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// -------------------------------------- +// Misc Signals +output int_o; +output [8:0] dma_req_o; +input [8:0] dma_ack_i; + +// -------------------------------------- +// Suspend Resume Interface +output suspended_o; + +// -------------------------------------- +// AC97 Codec Interface +input bit_clk_pad_i; +output sync_pad_o; +output sdata_pad_o; +input sdata_pad_i; +output ac97_reset_pad_o_; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +// Serial Output register interface +wire [15:0] out_slt0; +wire [19:0] out_slt1; +wire [19:0] out_slt2; +wire [19:0] out_slt3; +wire [19:0] out_slt4; +wire [19:0] out_slt6; +wire [19:0] out_slt7; +wire [19:0] out_slt8; +wire [19:0] out_slt9; + +// Serial Input register interface +wire [15:0] in_slt0; +wire [19:0] in_slt1; +wire [19:0] in_slt2; +wire [19:0] in_slt3; +wire [19:0] in_slt4; +wire [19:0] in_slt6; + +// Serial IO Controller Interface +wire ld; +wire valid; +wire [5:0] out_le; +wire [2:0] in_valid; +wire ps_ce; + +// Valid Sync +reg valid_s1, valid_s; +reg [2:0] in_valid_s1, in_valid_s; + +// Out FIFO interface +wire [31:0] wb_din; +wire [1:0] o3_mode, o4_mode, o6_mode, o7_mode, o8_mode, o9_mode; +wire o3_re, o4_re, o6_re, o7_re, o8_re, o9_re; +wire o3_we, o4_we, o6_we, o7_we, o8_we, o9_we; +wire [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status; +wire o3_full, o4_full, o6_full, o7_full, o8_full, o9_full; +wire o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty; + +// In FIFO interface +wire [31:0] i3_dout, i4_dout, i6_dout; +wire [1:0] i3_mode, i4_mode, i6_mode; +wire i3_we, i4_we, i6_we; +wire i3_re, i4_re, i6_re; +wire [1:0] i3_status, i4_status, i6_status; +wire i3_full, i4_full, i6_full; +wire i3_empty, i4_empty, i6_empty; + +// Register File Interface +wire [3:0] adr; +wire [31:0] rf_dout; +wire [31:0] rf_din; +wire rf_we; +wire rf_re; +wire ac97_rst_force; +wire resume_req; +wire crac_we; +wire [15:0] crac_din; +wire [31:0] crac_out; +wire [7:0] oc0_cfg; +wire [7:0] oc1_cfg; +wire [7:0] oc2_cfg; +wire [7:0] oc3_cfg; +wire [7:0] oc4_cfg; +wire [7:0] oc5_cfg; +wire [7:0] ic0_cfg; +wire [7:0] ic1_cfg; +wire [7:0] ic2_cfg; +wire [2:0] oc0_int_set; +wire [2:0] oc1_int_set; +wire [2:0] oc2_int_set; +wire [2:0] oc3_int_set; +wire [2:0] oc4_int_set; +wire [2:0] oc5_int_set; +wire [2:0] ic0_int_set; +wire [2:0] ic1_int_set; +wire [2:0] ic2_int_set; + +// CRA Module interface +wire crac_valid; +wire crac_wr; +wire crac_wr_done, crac_rd_done; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +// Sync Valid to WISHBONE Clock +always @(posedge clk_i) + valid_s1 <= #1 valid; + +always @(posedge clk_i) + valid_s <= #1 valid_s1; + +always @(posedge clk_i) + in_valid_s1 <= #1 in_valid; + +always @(posedge clk_i) + in_valid_s <= #1 in_valid_s1; + +// "valid_s" Indicates when any of the outputs to the output S/R may +// change or when outputs from input S/R may be sampled +assign o3_mode = oc0_cfg[3:2]; +assign o4_mode = oc1_cfg[3:2]; +assign o6_mode = oc2_cfg[3:2]; +assign o7_mode = oc3_cfg[3:2]; +assign o8_mode = oc4_cfg[3:2]; +assign o9_mode = oc5_cfg[3:2]; +assign i3_mode = ic0_cfg[3:2]; +assign i4_mode = ic1_cfg[3:2]; +assign i6_mode = ic2_cfg[3:2]; + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +ac97_sout u0( + .clk( bit_clk_pad_i ), + .rst( rst_i ), + .so_ld( ld ), + .slt0( out_slt0 ), + .slt1( out_slt1 ), + .slt2( out_slt2 ), + .slt3( out_slt3 ), + .slt4( out_slt4 ), + .slt6( out_slt6 ), + .slt7( out_slt7 ), + .slt8( out_slt8 ), + .slt9( out_slt9 ), + .sdata_out( sdata_pad_o ) + ); + +ac97_sin u1( + .clk( bit_clk_pad_i ), + .rst( rst_i ), + .out_le( out_le ), + .slt0( in_slt0 ), + .slt1( in_slt1 ), + .slt2( in_slt2 ), + .slt3( in_slt3 ), + .slt4( in_slt4 ), + .slt6( in_slt6 ), + .sdata_in( sdata_pad_i ) + ); + +ac97_soc u2( + .clk( bit_clk_pad_i ), + .wclk( clk_i ), + .rst( rst_i ), + .ps_ce( ps_ce ), + .resume( resume_req ), + .suspended( suspended_o ), + .sync( sync_pad_o ), + .out_le( out_le ), + .in_valid( in_valid ), + .ld( ld ), + .valid( valid ) + ); + +ac97_out_fifo u3( + .clk( clk_i ), + .rst( rst_i ), + .en( oc0_cfg[0] ), + .mode( o3_mode ), + .din( wb_din ), + .we( o3_we ), + .dout( out_slt3 ), + .re( o3_re ), + .status( o3_status ), + .full( o3_full ), + .empty( o3_empty ) + ); + +ac97_out_fifo u4( + .clk( clk_i ), + .rst( rst_i ), + .en( oc1_cfg[0] ), + .mode( o4_mode ), + .din( wb_din ), + .we( o4_we ), + .dout( out_slt4 ), + .re( o4_re ), + .status( o4_status ), + .full( o4_full ), + .empty( o4_empty ) + ); + +`ifdef AC97_CENTER +ac97_out_fifo u5( + .clk( clk_i ), + .rst( rst_i ), + .en( oc2_cfg[0] ), + .mode( o6_mode ), + .din( wb_din ), + .we( o6_we ), + .dout( out_slt6 ), + .re( o6_re ), + .status( o6_status ), + .full( o6_full ), + .empty( o6_empty ) + ); +`else +assign out_slt6 = 20'h0; +assign o6_status = 2'h0; +assign o6_full = 1'b0; +assign o6_empty = 1'b0; +`endif + +`ifdef AC97_SURROUND +ac97_out_fifo u6( + .clk( clk_i ), + .rst( rst_i ), + .en( oc3_cfg[0] ), + .mode( o7_mode ), + .din( wb_din ), + .we( o7_we ), + .dout( out_slt7 ), + .re( o7_re ), + .status( o7_status ), + .full( o7_full ), + .empty( o7_empty ) + ); + +ac97_out_fifo u7( + .clk( clk_i ), + .rst( rst_i ), + .en( oc4_cfg[0] ), + .mode( o8_mode ), + .din( wb_din ), + .we( o8_we ), + .dout( out_slt8 ), + .re( o8_re ), + .status( o8_status ), + .full( o8_full ), + .empty( o8_empty ) + ); +`else +assign out_slt7 = 20'h0; +assign o7_status = 2'h0; +assign o7_full = 1'b0; +assign o7_empty = 1'b0; +assign out_slt8 = 20'h0; +assign o8_status = 2'h0; +assign o8_full = 1'b0; +assign o8_empty = 1'b0; +`endif + +`ifdef AC97_LFE +ac97_out_fifo u8( + .clk( clk_i ), + .rst( rst_i ), + .en( oc5_cfg[0] ), + .mode( o9_mode ), + .din( wb_din ), + .we( o9_we ), + .dout( out_slt9 ), + .re( o9_re ), + .status( o9_status ), + .full( o9_full ), + .empty( o9_empty ) + ); +`else +assign out_slt9 = 20'h0; +assign o9_status = 2'h0; +assign o9_full = 1'b0; +assign o9_empty = 1'b0; +`endif + +`ifdef AC97_SIN +ac97_in_fifo u9( + .clk( clk_i ), + .rst( rst_i ), + .en( ic0_cfg[0] ), + .mode( i3_mode ), + .din( in_slt3 ), + .we( i3_we ), + .dout( i3_dout ), + .re( i3_re ), + .status( i3_status ), + .full( i3_full ), + .empty( i3_empty ) + ); + +ac97_in_fifo u10( + .clk( clk_i ), + .rst( rst_i ), + .en( ic1_cfg[0] ), + .mode( i4_mode ), + .din( in_slt4 ), + .we( i4_we ), + .dout( i4_dout ), + .re( i4_re ), + .status( i4_status ), + .full( i4_full ), + .empty( i4_empty ) + ); +`else +assign i3_dout = 20'h0; +assign i3_status = 2'h0; +assign i3_full = 1'b0; +assign i3_empty = 1'b0; +assign i4_dout = 20'h0; +assign i4_status = 2'h0; +assign i4_full = 1'b0; +assign i4_empty = 1'b0; +`endif + +`ifdef AC97_MICIN +ac97_in_fifo u11( + .clk( clk_i ), + .rst( rst_i ), + .en( ic2_cfg[0] ), + .mode( i6_mode ), + .din( in_slt6 ), + .we( i6_we ), + .dout( i6_dout ), + .re( i6_re ), + .status( i6_status ), + .full( i6_full ), + .empty( i6_empty ) + ); +`else +assign i6_dout = 20'h0; +assign i6_status = 2'h0; +assign i6_full = 1'b0; +assign i6_empty = 1'b0; +`endif + +ac97_wb_if u12( + .clk( clk_i ), + .rst( rst_i ), + .wb_data_i( wb_data_i ), + .wb_data_o( wb_data_o ), + .wb_addr_i( wb_addr_i ), + .wb_sel_i( wb_sel_i ), + .wb_we_i( wb_we_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_ack_o( wb_ack_o ), + .wb_err_o( wb_err_o ), + .adr( adr ), + .dout( wb_din ), + .rf_din( rf_dout ), + .i3_din( i3_dout ), + .i4_din( i4_dout ), + .i6_din( i6_dout ), + .rf_we( rf_we ), + .rf_re( rf_re ), + .o3_we( o3_we ), + .o4_we( o4_we ), + .o6_we( o6_we ), + .o7_we( o7_we ), + .o8_we( o8_we ), + .o9_we( o9_we ), + .i3_re( i3_re ), + .i4_re( i4_re ), + .i6_re( i6_re ) + ); + +ac97_rf u13( .clk( clk_i ), + .rst( rst_i ), + .adr( adr ), + .rf_dout( rf_dout ), + .rf_din( wb_din ), + .rf_we( rf_we ), + .rf_re( rf_re ), + .int( int_o ), + .ac97_rst_force(ac97_rst_force ), + .resume_req( resume_req ), + .suspended( suspended_o ), + .crac_we( crac_we ), + .crac_din( crac_din ), + .crac_out( crac_out ), + .crac_wr_done( crac_wr_done ), + .crac_rd_done( crac_rd_done ), + .oc0_cfg( oc0_cfg ), + .oc1_cfg( oc1_cfg ), + .oc2_cfg( oc2_cfg ), + .oc3_cfg( oc3_cfg ), + .oc4_cfg( oc4_cfg ), + .oc5_cfg( oc5_cfg ), + .ic0_cfg( ic0_cfg ), + .ic1_cfg( ic1_cfg ), + .ic2_cfg( ic2_cfg ), + .oc0_int_set( oc0_int_set ), + .oc1_int_set( oc1_int_set ), + .oc2_int_set( oc2_int_set ), + .oc3_int_set( oc3_int_set ), + .oc4_int_set( oc4_int_set ), + .oc5_int_set( oc5_int_set ), + .ic0_int_set( ic0_int_set ), + .ic1_int_set( ic1_int_set ), + .ic2_int_set( ic2_int_set ) + ); + +ac97_prc u14( .clk( clk_i ), + .rst( rst_i ), + .valid( valid_s ), + .in_valid( in_valid_s ), + .out_slt0( out_slt0 ), + .in_slt0( in_slt0 ), + .in_slt1( in_slt1 ), + .crac_valid( crac_valid ), + .crac_wr( crac_wr ), + .oc0_cfg( oc0_cfg ), + .oc1_cfg( oc1_cfg ), + .oc2_cfg( oc2_cfg ), + .oc3_cfg( oc3_cfg ), + .oc4_cfg( oc4_cfg ), + .oc5_cfg( oc5_cfg ), + .ic0_cfg( ic0_cfg ), + .ic1_cfg( ic1_cfg ), + .ic2_cfg( ic2_cfg ), + .o3_empty( o3_empty ), + .o4_empty( o4_empty ), + .o6_empty( o6_empty ), + .o7_empty( o7_empty ), + .o8_empty( o8_empty ), + .o9_empty( o9_empty ), + .i3_full( i3_full ), + .i4_full( i4_full ), + .i6_full( i6_full ), + .o3_re( o3_re ), + .o4_re( o4_re ), + .o6_re( o6_re ), + .o7_re( o7_re ), + .o8_re( o8_re ), + .o9_re( o9_re ), + .i3_we( i3_we ), + .i4_we( i4_we ), + .i6_we( i6_we ) + ); + +ac97_cra u15( .clk( clk_i ), + .rst( rst_i ), + .crac_we( crac_we ), + .crac_din( crac_din ), + .crac_out( crac_out ), + .crac_wr_done( crac_wr_done ), + .crac_rd_done( crac_rd_done ), + .valid( valid_s ), + .out_slt1( out_slt1 ), + .out_slt2( out_slt2 ), + .in_slt2( in_slt2 ), + .crac_valid( crac_valid ), + .crac_wr( crac_wr ) + ); + +ac97_dma_if u16(.clk( clk_i ), + .rst( rst_i ), + .o3_status( o3_status ), + .o4_status( o4_status ), + .o6_status( o6_status ), + .o7_status( o7_status ), + .o8_status( o8_status ), + .o9_status( o9_status ), + .o3_empty( o3_empty ), + .o4_empty( o4_empty ), + .o6_empty( o6_empty ), + .o7_empty( o7_empty ), + .o8_empty( o8_empty ), + .o9_empty( o9_empty ), + .i3_status( i3_status ), + .i4_status( i4_status ), + .i6_status( i6_status ), + .i3_full( i3_full ), + .i4_full( i4_full ), + .i6_full( i6_full ), + .oc0_cfg( oc0_cfg ), + .oc1_cfg( oc1_cfg ), + .oc2_cfg( oc2_cfg ), + .oc3_cfg( oc3_cfg ), + .oc4_cfg( oc4_cfg ), + .oc5_cfg( oc5_cfg ), + .ic0_cfg( ic0_cfg ), + .ic1_cfg( ic1_cfg ), + .ic2_cfg( ic2_cfg ), + .dma_req( dma_req_o ), + .dma_ack( dma_ack_i ) + ); + +ac97_int u17( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc0_int_set ), + .cfg( oc0_cfg ), + .status( o3_status ), + .full_empty( o3_empty ), + .full( o3_full ), + .empty( o3_empty ), + .re( o3_re ), + .we( o3_we ) + ); + +ac97_int u18( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc1_int_set ), + .cfg( oc1_cfg ), + .status( o4_status ), + .full_empty( o4_empty ), + .full( o4_full ), + .empty( o4_empty ), + .re( o4_re ), + .we( o4_we ) + ); + +`ifdef AC97_CENTER +ac97_int u19( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc2_int_set ), + .cfg( oc2_cfg ), + .status( o6_status ), + .full_empty( o6_empty ), + .full( o6_full ), + .empty( o6_empty ), + .re( o6_re ), + .we( o6_we ) + ); +`else +assign oc2_int_set = 1'b0; +`endif + +`ifdef AC97_SURROUND +ac97_int u20( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc3_int_set ), + .cfg( oc3_cfg ), + .status( o7_status ), + .full_empty( o7_empty ), + .full( o7_full ), + .empty( o7_empty ), + .re( o7_re ), + .we( o7_we ) + ); + +ac97_int u21( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc4_int_set ), + .cfg( oc4_cfg ), + .status( o8_status ), + .full_empty( o8_empty ), + .full( o8_full ), + .empty( o8_empty ), + .re( o8_re ), + .we( o8_we ) + ); +`else +assign oc3_int_set = 1'b0; +assign oc4_int_set = 1'b0; +`endif + +`ifdef AC97_LFE +ac97_int u22( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc5_int_set ), + .cfg( oc5_cfg ), + .status( o9_status ), + .full_empty( o9_empty ), + .full( o9_full ), + .empty( o9_empty ), + .re( o9_re ), + .we( o9_we ) + ); +`else +assign oc5_int_set = 1'b0; +`endif + +`ifdef AC97_SIN +ac97_int u23( + .clk( clk_i ), + .rst( rst_i ), + .int_set( ic0_int_set ), + .cfg( ic0_cfg ), + .status( i3_status ), + .full_empty( i3_full ), + .full( i3_full ), + .empty( i3_empty ), + .re( i3_re ), + .we( i3_we ) + ); + +ac97_int u24( + .clk( clk_i ), + .rst( rst_i ), + .int_set( ic1_int_set ), + .cfg( ic1_cfg ), + .status( i4_status ), + .full_empty( i4_full ), + .full( i4_full ), + .empty( i4_empty ), + .re( i4_re ), + .we( i4_we ) + ); +`else +assign ic0_int_set = 1'b0; +assign ic1_int_set = 1'b0; +`endif + +`ifdef AC97_MICIN +ac97_int u25( + .clk( clk_i ), + .rst( rst_i ), + .int_set( ic2_int_set ), + .cfg( ic2_cfg ), + .status( i6_status ), + .full_empty( i6_full ), + .full( i6_full ), + .empty( i6_empty ), + .re( i6_re ), + .we( i6_we ) + ); +`else +assign ic2_int_set = 1'b0; +`endif + +ac97_rst u26( + .clk( clk_i ), + .rst( rst_i ), + .rst_force( ac97_rst_force ), + .ps_ce( ps_ce ), + .ac97_rst_( ac97_reset_pad_o_ ) + ); + +endmodule + diff --git a/designs/encrypted_ip/des3_area/ac97_top_synthed.v b/designs/encrypted_ip/des3_area/ac97_top_synthed.v new file mode 100644 index 000000000..3352a48e3 --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_top_synthed.v @@ -0,0 +1,16776 @@ +// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021 +// Date : Fri May 26 10:14:45 2023 +// Host : goeders1 running 64-bit Ubuntu 20.04.3 LTS +// Command : write_verilog ./ac97_top_synthed.v -force +// Design : ac97_top +// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an +// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input +// design files. +// Device : xc7a100tcsg324-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* STRUCTURAL_NETLIST = "yes" *) +module ac97_top + (clk_i, + rst_i, + wb_data_i, + wb_data_o, + wb_addr_i, + wb_sel_i, + wb_we_i, + wb_cyc_i, + wb_stb_i, + wb_ack_o, + .wb_err_o(\ ), + int_o, + dma_req_o, + dma_ack_i, + suspended_o, + bit_clk_pad_i, + sync_pad_o, + sdata_pad_o, + sdata_pad_i, + ac97_reset_pad_o_); + input clk_i; + input rst_i; + input [31:0]wb_data_i; + output [31:0]wb_data_o; + input [31:0]wb_addr_i; + input [3:0]wb_sel_i; + input wb_we_i; + input wb_cyc_i; + input wb_stb_i; + output wb_ack_o; + output int_o; + output [8:0]dma_req_o; + input [8:0]dma_ack_i; + output suspended_o; + input bit_clk_pad_i; + output sync_pad_o; + output sdata_pad_o; + input sdata_pad_i; + output ac97_reset_pad_o_; + output \ ; + + wire \ ; + wire \ ; + wire ac97_reset_pad_o_; + wire ac97_rst__i_1_n_0; + wire ac97_rst_force; + wire ac97_rst_force_i_1_n_0; + wire bit_clk_pad_i; + wire clk_i; + wire \cnt[0]_i_1__0_n_0 ; + wire \cnt[0]_i_1_n_0 ; + wire \cnt[1]_i_1_n_0 ; + wire \cnt[2]_i_1_n_0 ; + wire \cnt[2]_i_2_n_0 ; + wire \cnt[7]_i_2_n_0 ; + wire [15:0]crac_din; + wire [31:0]crac_out; + wire crac_rd_done; + wire crac_rd_i_1_n_0; + wire crac_valid_r_i_1_n_0; + wire crac_we; + wire crac_wr; + wire crac_wr_i_1_n_0; + wire crac_wr_r_i_1_n_0; + wire [8:0]dma_ack_i; + wire dma_req_i_1__0_n_0; + wire dma_req_i_1__1_n_0; + wire dma_req_i_1__2_n_0; + wire dma_req_i_1__3_n_0; + wire dma_req_i_1__4_n_0; + wire dma_req_i_1__5_n_0; + wire dma_req_i_1__6_n_0; + wire dma_req_i_1__7_n_0; + wire dma_req_i_1_n_0; + wire dma_req_i_2_n_0; + wire [8:0]dma_req_o; + wire [31:0]dout0; + wire [31:0]dout0__0; + wire [31:0]dout0__1; + wire \dout[19]_i_1__0_n_0 ; + wire \dout[19]_i_1__1_n_0 ; + wire \dout[19]_i_1__2_n_0 ; + wire \dout[19]_i_1__3_n_0 ; + wire \dout[19]_i_1__4_n_0 ; + wire \dout[19]_i_1_n_0 ; + wire [31:0]dout_tmp; + wire [31:0]dout_tmp__0; + wire [31:0]dout_tmp__1; + wire [31:0]dout_tmp__2; + wire [31:0]dout_tmp__3; + wire [31:0]dout_tmp__4; + wire empty_i_2__0_n_0; + wire empty_i_2__1_n_0; + wire empty_i_2__2_n_0; + wire empty_i_2__3_n_0; + wire empty_i_2__4_n_0; + wire empty_i_2__5_n_0; + wire empty_i_2__6_n_0; + wire empty_i_2__7_n_0; + wire empty_i_2_n_0; + wire en_out_l_i_1__0_n_0; + wire en_out_l_i_1__1_n_0; + wire en_out_l_i_1__2_n_0; + wire en_out_l_i_1__3_n_0; + wire en_out_l_i_1__4_n_0; + wire en_out_l_i_1__5_n_0; + wire en_out_l_i_1__6_n_0; + wire en_out_l_i_1__7_n_0; + wire en_out_l_i_1_n_0; + wire en_out_l_i_2__0_n_0; + wire en_out_l_i_2__1_n_0; + wire en_out_l_i_2__2_n_0; + wire en_out_l_i_2__3_n_0; + wire en_out_l_i_2__4_n_0; + wire en_out_l_i_2__5_n_0; + wire en_out_l_i_2__6_n_0; + wire en_out_l_i_2__7_n_0; + wire en_out_l_i_2_n_0; + wire full_empty_r_i_1__0_n_0; + wire full_empty_r_i_1__1_n_0; + wire full_empty_r_i_1__2_n_0; + wire [31:0]i3_dout; + wire i3_empty; + wire i3_full; + wire [1:0]i3_mode; + wire i3_re; + wire [1:0]i3_status; + wire i3_we; + wire [31:0]i4_dout; + wire i4_empty; + wire i4_full; + wire [1:0]i4_mode; + wire i4_re; + wire [1:0]i4_status; + wire i4_we; + wire [31:0]i6_dout; + wire i6_empty; + wire i6_full; + wire [1:0]i6_mode; + wire i6_re; + wire [1:0]i6_status; + wire i6_we; + wire [2:0]ic0_int_set; + wire [2:0]ic1_int_set; + wire [2:0]ic2_int_set; + wire [15:9]in_slt0; + wire [11:5]in_slt1; + wire [19:4]in_slt2; + wire [19:0]in_slt3; + wire [19:0]in_slt4; + wire [19:0]in_slt6; + wire [2:0]in_valid; + wire \in_valid[1]_i_1_n_0 ; + wire \in_valid[2]_i_1_n_0 ; + wire [2:0]in_valid_s; + wire [2:0]in_valid_s1; + wire int_i_10_n_0; + wire int_i_11_n_0; + wire int_i_12_n_0; + wire int_i_1_n_0; + wire int_i_2_n_0; + wire int_i_3_n_0; + wire int_i_4_n_0; + wire int_i_5_n_0; + wire int_i_6_n_0; + wire int_i_7_n_0; + wire int_i_8_n_0; + wire int_i_9_n_0; + wire int_o; + wire \int_set[0]_i_1__0_n_0 ; + wire \int_set[0]_i_1__1_n_0 ; + wire \int_set[0]_i_1__2_n_0 ; + wire \int_set[0]_i_1__3_n_0 ; + wire \int_set[0]_i_1__4_n_0 ; + wire \int_set[0]_i_1__5_n_0 ; + wire \int_set[0]_i_1__6_n_0 ; + wire \int_set[0]_i_1__7_n_0 ; + wire \int_set[0]_i_1_n_0 ; + wire \ints_r[0]_i_1_n_0 ; + wire \ints_r[10]_i_1_n_0 ; + wire \ints_r[11]_i_1_n_0 ; + wire \ints_r[12]_i_1_n_0 ; + wire \ints_r[13]_i_1_n_0 ; + wire \ints_r[14]_i_1_n_0 ; + wire \ints_r[15]_i_1_n_0 ; + wire \ints_r[16]_i_1_n_0 ; + wire \ints_r[17]_i_1_n_0 ; + wire \ints_r[18]_i_1_n_0 ; + wire \ints_r[19]_i_1_n_0 ; + wire \ints_r[1]_i_1_n_0 ; + wire \ints_r[20]_i_1_n_0 ; + wire \ints_r[21]_i_1_n_0 ; + wire \ints_r[22]_i_1_n_0 ; + wire \ints_r[23]_i_1_n_0 ; + wire \ints_r[24]_i_1_n_0 ; + wire \ints_r[25]_i_1_n_0 ; + wire \ints_r[26]_i_1_n_0 ; + wire \ints_r[27]_i_1_n_0 ; + wire \ints_r[28]_i_1_n_0 ; + wire \ints_r[28]_i_2_n_0 ; + wire \ints_r[2]_i_1_n_0 ; + wire \ints_r[3]_i_1_n_0 ; + wire \ints_r[4]_i_1_n_0 ; + wire \ints_r[5]_i_1_n_0 ; + wire \ints_r[6]_i_1_n_0 ; + wire \ints_r[7]_i_1_n_0 ; + wire \ints_r[8]_i_1_n_0 ; + wire \ints_r[9]_i_1_n_0 ; + wire ld; + wire ld_i_1_n_0; + wire o3_empty; + wire [1:0]o3_mode; + wire o3_re; + wire [1:0]o3_status; + wire o3_we; + wire o3_we_i_1_n_0; + wire o3_we_i_2_n_0; + wire o3_we_i_3_n_0; + wire o4_empty; + wire [1:0]o4_mode; + wire o4_re; + wire [1:0]o4_status; + wire o4_we; + wire o4_we_i_1_n_0; + wire o6_empty; + wire [1:0]o6_mode; + wire o6_re; + wire [1:0]o6_status; + wire o6_we; + wire o6_we_i_1_n_0; + wire o7_empty; + wire [1:0]o7_mode; + wire o7_re; + wire [1:0]o7_status; + wire o7_we; + wire o7_we_i_1_n_0; + wire o8_empty; + wire [1:0]o8_mode; + wire o8_re; + wire [1:0]o8_status; + wire o8_we; + wire o8_we_i_1_n_0; + wire o9_empty; + wire [1:0]o9_mode; + wire o9_re; + wire [1:0]o9_status; + wire o9_we; + wire o9_we_i_1_n_0; + wire [2:0]oc0_int_set; + wire [2:0]oc1_int_set; + wire [2:0]oc2_int_set; + wire [2:0]oc3_int_set; + wire [2:0]oc4_int_set; + wire [2:0]oc5_int_set; + wire [5:0]out_le; + wire \out_le[0]_i_1_n_0 ; + wire \out_le[0]_i_2_n_0 ; + wire \out_le[1]_i_1_n_0 ; + wire \out_le[1]_i_2_n_0 ; + wire \out_le[1]_i_3_n_0 ; + wire \out_le[2]_i_1_n_0 ; + wire \out_le[2]_i_2_n_0 ; + wire \out_le[3]_i_1_n_0 ; + wire \out_le[3]_i_2_n_0 ; + wire \out_le[4]_i_1_n_0 ; + wire \out_le[5]_i_1_n_0 ; + wire [14:6]out_slt0; + wire [19:0]out_slt3; + wire [19:0]out_slt4; + wire [19:0]out_slt6; + wire [19:0]out_slt7; + wire [19:0]out_slt8; + wire [19:0]out_slt9; + wire [19:0]p_0_in; + wire p_0_in__0; + wire [3:0]p_0_in__0__0; + wire p_0_in__1; + wire [7:1]p_0_in__1__0; + wire p_0_in__2; + wire [3:1]p_0_in__2__0; + wire [5:1]p_0_in__3; + wire [3:1]p_0_in__3__0; + wire [3:1]p_0_in__4; + wire [3:1]p_0_in__5; + wire [3:1]p_0_in__6; + wire [3:1]p_0_in__7; + wire [5:1]p_0_in__8; + wire ps_ce; + wire \ps_cnt[0]_i_1_n_0 ; + wire \ps_cnt[4]_i_2_n_0 ; + wire \ps_cnt[5]_i_2_n_0 ; + wire rdd1_i_1_n_0; + wire rdd2_i_1_n_0; + wire rdd3_i_1_n_0; + wire re1_i_2_n_0; + wire resume_req; + wire resume_req_i_1_n_0; + wire rf_we; + wire \rp[0]_i_1__0_n_0 ; + wire \rp[0]_i_1__1_n_0 ; + wire \rp[0]_i_1__2_n_0 ; + wire \rp[0]_i_1__3_n_0 ; + wire \rp[0]_i_1__4_n_0 ; + wire \rp[0]_i_1__5_n_0 ; + wire \rp[0]_i_1__6_n_0 ; + wire \rp[0]_i_1__7_n_0 ; + wire \rp[0]_i_1_n_0 ; + wire \rp[1]_i_1__0_n_0 ; + wire \rp[1]_i_1__1_n_0 ; + wire \rp[1]_i_1_n_0 ; + wire \rp[2]_i_1__0_n_0 ; + wire \rp[2]_i_1__1_n_0 ; + wire \rp[2]_i_1_n_0 ; + wire \rp[3]_i_2__0_n_0 ; + wire \rp[3]_i_2__1_n_0 ; + wire \rp[3]_i_2__2_n_0 ; + wire \rp[3]_i_2__3_n_0 ; + wire \rp[3]_i_2__4_n_0 ; + wire \rp[3]_i_2_n_0 ; + wire rst_i; + wire sdata_pad_i; + wire sdata_pad_o; + wire \slt0_r[11]_i_1_n_0 ; + wire \slt0_r[12]_i_1_n_0 ; + wire \slt0_r[13]_i_1_n_0 ; + wire \slt0_r[14]_i_1_n_0 ; + wire \slt0_r[15]_i_1_n_0 ; + wire \slt0_r[15]_i_2_n_0 ; + wire \slt0_r[6]_i_1_n_0 ; + wire \slt0_r[7]_i_1_n_0 ; + wire \slt0_r[8]_i_1_n_0 ; + wire \slt0_r[9]_i_1_n_0 ; + wire \slt1_r[12]_i_1_n_0 ; + wire \slt1_r[13]_i_1_n_0 ; + wire \slt1_r[14]_i_1_n_0 ; + wire \slt1_r[15]_i_1_n_0 ; + wire \slt1_r[16]_i_1_n_0 ; + wire \slt1_r[17]_i_1_n_0 ; + wire \slt1_r[18]_i_1_n_0 ; + wire \slt1_r[19]_i_1_n_0 ; + wire \slt2_r[10]_i_1_n_0 ; + wire \slt2_r[11]_i_1_n_0 ; + wire \slt2_r[12]_i_1_n_0 ; + wire \slt2_r[13]_i_1_n_0 ; + wire \slt2_r[14]_i_1_n_0 ; + wire \slt2_r[15]_i_1_n_0 ; + wire \slt2_r[16]_i_1_n_0 ; + wire \slt2_r[17]_i_1_n_0 ; + wire \slt2_r[18]_i_1_n_0 ; + wire \slt2_r[19]_i_1_n_0 ; + wire \slt2_r[4]_i_1_n_0 ; + wire \slt2_r[5]_i_1_n_0 ; + wire \slt2_r[6]_i_1_n_0 ; + wire \slt2_r[7]_i_1_n_0 ; + wire \slt2_r[8]_i_1_n_0 ; + wire \slt2_r[9]_i_1_n_0 ; + wire \slt3_r[0]_i_1_n_0 ; + wire \slt3_r[10]_i_1_n_0 ; + wire \slt3_r[11]_i_1_n_0 ; + wire \slt3_r[12]_i_1_n_0 ; + wire \slt3_r[13]_i_1_n_0 ; + wire \slt3_r[14]_i_1_n_0 ; + wire \slt3_r[15]_i_1_n_0 ; + wire \slt3_r[16]_i_1_n_0 ; + wire \slt3_r[17]_i_1_n_0 ; + wire \slt3_r[18]_i_1_n_0 ; + wire \slt3_r[19]_i_1_n_0 ; + wire \slt3_r[1]_i_1_n_0 ; + wire \slt3_r[2]_i_1_n_0 ; + wire \slt3_r[3]_i_1_n_0 ; + wire \slt3_r[4]_i_1_n_0 ; + wire \slt3_r[5]_i_1_n_0 ; + wire \slt3_r[6]_i_1_n_0 ; + wire \slt3_r[7]_i_1_n_0 ; + wire \slt3_r[8]_i_1_n_0 ; + wire \slt3_r[9]_i_1_n_0 ; + wire \slt4_r[0]_i_1_n_0 ; + wire \slt4_r[10]_i_1_n_0 ; + wire \slt4_r[11]_i_1_n_0 ; + wire \slt4_r[12]_i_1_n_0 ; + wire \slt4_r[13]_i_1_n_0 ; + wire \slt4_r[14]_i_1_n_0 ; + wire \slt4_r[15]_i_1_n_0 ; + wire \slt4_r[16]_i_1_n_0 ; + wire \slt4_r[17]_i_1_n_0 ; + wire \slt4_r[18]_i_1_n_0 ; + wire \slt4_r[19]_i_1_n_0 ; + wire \slt4_r[1]_i_1_n_0 ; + wire \slt4_r[2]_i_1_n_0 ; + wire \slt4_r[3]_i_1_n_0 ; + wire \slt4_r[4]_i_1_n_0 ; + wire \slt4_r[5]_i_1_n_0 ; + wire \slt4_r[6]_i_1_n_0 ; + wire \slt4_r[7]_i_1_n_0 ; + wire \slt4_r[8]_i_1_n_0 ; + wire \slt4_r[9]_i_1_n_0 ; + wire \slt6_r[0]_i_1_n_0 ; + wire \slt6_r[10]_i_1_n_0 ; + wire \slt6_r[11]_i_1_n_0 ; + wire \slt6_r[12]_i_1_n_0 ; + wire \slt6_r[13]_i_1_n_0 ; + wire \slt6_r[14]_i_1_n_0 ; + wire \slt6_r[15]_i_1_n_0 ; + wire \slt6_r[16]_i_1_n_0 ; + wire \slt6_r[17]_i_1_n_0 ; + wire \slt6_r[18]_i_1_n_0 ; + wire \slt6_r[19]_i_1_n_0 ; + wire \slt6_r[1]_i_1_n_0 ; + wire \slt6_r[2]_i_1_n_0 ; + wire \slt6_r[3]_i_1_n_0 ; + wire \slt6_r[4]_i_1_n_0 ; + wire \slt6_r[5]_i_1_n_0 ; + wire \slt6_r[6]_i_1_n_0 ; + wire \slt6_r[7]_i_1_n_0 ; + wire \slt6_r[8]_i_1_n_0 ; + wire \slt6_r[9]_i_1_n_0 ; + wire \slt7_r[0]_i_1_n_0 ; + wire \slt7_r[10]_i_1_n_0 ; + wire \slt7_r[11]_i_1_n_0 ; + wire \slt7_r[12]_i_1_n_0 ; + wire \slt7_r[13]_i_1_n_0 ; + wire \slt7_r[14]_i_1_n_0 ; + wire \slt7_r[15]_i_1_n_0 ; + wire \slt7_r[16]_i_1_n_0 ; + wire \slt7_r[17]_i_1_n_0 ; + wire \slt7_r[18]_i_1_n_0 ; + wire \slt7_r[19]_i_1_n_0 ; + wire \slt7_r[1]_i_1_n_0 ; + wire \slt7_r[2]_i_1_n_0 ; + wire \slt7_r[3]_i_1_n_0 ; + wire \slt7_r[4]_i_1_n_0 ; + wire \slt7_r[5]_i_1_n_0 ; + wire \slt7_r[6]_i_1_n_0 ; + wire \slt7_r[7]_i_1_n_0 ; + wire \slt7_r[8]_i_1_n_0 ; + wire \slt7_r[9]_i_1_n_0 ; + wire \slt8_r[0]_i_1_n_0 ; + wire \slt8_r[10]_i_1_n_0 ; + wire \slt8_r[11]_i_1_n_0 ; + wire \slt8_r[12]_i_1_n_0 ; + wire \slt8_r[13]_i_1_n_0 ; + wire \slt8_r[14]_i_1_n_0 ; + wire \slt8_r[15]_i_1_n_0 ; + wire \slt8_r[16]_i_1_n_0 ; + wire \slt8_r[17]_i_1_n_0 ; + wire \slt8_r[18]_i_1_n_0 ; + wire \slt8_r[19]_i_1_n_0 ; + wire \slt8_r[1]_i_1_n_0 ; + wire \slt8_r[2]_i_1_n_0 ; + wire \slt8_r[3]_i_1_n_0 ; + wire \slt8_r[4]_i_1_n_0 ; + wire \slt8_r[5]_i_1_n_0 ; + wire \slt8_r[6]_i_1_n_0 ; + wire \slt8_r[7]_i_1_n_0 ; + wire \slt8_r[8]_i_1_n_0 ; + wire \slt8_r[9]_i_1_n_0 ; + wire \slt9_r[0]_i_1_n_0 ; + wire \status[0]_i_1__0_n_0 ; + wire \status[0]_i_1__1_n_0 ; + wire \status[0]_i_1__2_n_0 ; + wire \status[0]_i_1__3_n_0 ; + wire \status[0]_i_1__4_n_0 ; + wire \status[0]_i_1__5_n_0 ; + wire \status[0]_i_1__6_n_0 ; + wire \status[0]_i_1__7_n_0 ; + wire \status[0]_i_1_n_0 ; + wire suspended_o; + wire sync_pad_o; + wire sync_resume_i_1_n_0; + wire sync_resume_i_2_n_0; + wire \to_cnt[0]_i_1_n_0 ; + wire \to_cnt[5]_i_1_n_0 ; + wire \to_cnt[5]_i_3_n_0 ; + wire \to_cnt[5]_i_4_n_0 ; + wire [19:1]\u0/p_0_in ; + wire [14:5]\u0/slt0_r ; + wire \u0/slt0_r_reg[3]_srl4___u0_slt5_r_reg_r_2_n_0 ; + wire \u0/slt0_r_reg[4]_u0_slt5_r_reg_r_3_n_0 ; + wire \u0/slt0_r_reg_gate_n_0 ; + wire [19:11]\u0/slt1_r ; + wire \u0/slt1_r_reg[10]_u0_slt5_r_reg_r_9_n_0 ; + wire \u0/slt1_r_reg[9]_srl10___u0_slt5_r_reg_r_8_n_0 ; + wire \u0/slt1_r_reg_gate_n_0 ; + wire [19:3]\u0/slt2_r ; + wire \u0/slt2_r_reg[1]_srl2___u0_slt5_r_reg_r_0_n_0 ; + wire \u0/slt2_r_reg[2]_u0_slt5_r_reg_r_1_n_0 ; + wire \u0/slt2_r_reg_gate_n_0 ; + wire [19:0]\u0/slt3_r ; + wire [19:0]\u0/slt4_r ; + wire [19:19]\u0/slt5_r ; + wire \u0/slt5_r_reg[17]_srl18___u0_slt5_r_reg_r_16_n_0 ; + wire \u0/slt5_r_reg[18]_u0_slt5_r_reg_r_17_n_0 ; + wire \u0/slt5_r_reg_gate_n_0 ; + wire \u0/slt5_r_reg_r_0_n_0 ; + wire \u0/slt5_r_reg_r_10_n_0 ; + wire \u0/slt5_r_reg_r_11_n_0 ; + wire \u0/slt5_r_reg_r_12_n_0 ; + wire \u0/slt5_r_reg_r_13_n_0 ; + wire \u0/slt5_r_reg_r_14_n_0 ; + wire \u0/slt5_r_reg_r_15_n_0 ; + wire \u0/slt5_r_reg_r_16_n_0 ; + wire \u0/slt5_r_reg_r_17_n_0 ; + wire \u0/slt5_r_reg_r_1_n_0 ; + wire \u0/slt5_r_reg_r_2_n_0 ; + wire \u0/slt5_r_reg_r_3_n_0 ; + wire \u0/slt5_r_reg_r_4_n_0 ; + wire \u0/slt5_r_reg_r_5_n_0 ; + wire \u0/slt5_r_reg_r_6_n_0 ; + wire \u0/slt5_r_reg_r_7_n_0 ; + wire \u0/slt5_r_reg_r_8_n_0 ; + wire \u0/slt5_r_reg_r_9_n_0 ; + wire \u0/slt5_r_reg_r_n_0 ; + wire [19:0]\u0/slt6_r ; + wire [19:0]\u0/slt7_r ; + wire [19:0]\u0/slt8_r ; + wire [19:0]\u0/slt9_r ; + wire \u1/sr_reg_n_0_[19] ; + wire [31:0]\u10/din_tmp ; + wire [15:0]\u10/din_tmp1 ; + wire \u10/din_tmp10 ; + wire \u10/empty0 ; + wire \u10/full0 ; + wire [1:0]\u10/p_1_in ; + wire \u10/rp_reg_n_0_[0] ; + wire \u10/rp_reg_n_0_[1] ; + wire \u10/rp_reg_n_0_[2] ; + wire [1:1]\u10/status0 ; + wire \u10/wp_reg_n_0_[0] ; + wire \u10/wp_reg_n_0_[3] ; + wire [31:0]\u11/din_tmp ; + wire [15:0]\u11/din_tmp1 ; + wire \u11/din_tmp10 ; + wire \u11/empty0 ; + wire \u11/full0 ; + wire [1:0]\u11/p_1_in ; + wire \u11/rp_reg_n_0_[0] ; + wire \u11/rp_reg_n_0_[1] ; + wire \u11/rp_reg_n_0_[2] ; + wire [1:1]\u11/status0 ; + wire \u11/wp_reg_n_0_[0] ; + wire \u11/wp_reg_n_0_[3] ; + wire \u12/i3_re0 ; + wire \u12/i4_re0 ; + wire \u12/i6_re0 ; + wire \u12/re1 ; + wire \u12/re10 ; + wire \u12/re2 ; + wire \u12/re20 ; + wire \u12/rf_we0 ; + wire \u12/wb_ack_o0 ; + wire \u12/we1 ; + wire \u12/we10 ; + wire \u12/we2 ; + wire \u12/we20 ; + wire \u13/icc_r0 ; + wire \u13/icc_r_reg_n_0_[0] ; + wire \u13/icc_r_reg_n_0_[12] ; + wire \u13/icc_r_reg_n_0_[13] ; + wire \u13/icc_r_reg_n_0_[14] ; + wire \u13/icc_r_reg_n_0_[15] ; + wire \u13/icc_r_reg_n_0_[16] ; + wire \u13/icc_r_reg_n_0_[17] ; + wire \u13/icc_r_reg_n_0_[1] ; + wire \u13/icc_r_reg_n_0_[20] ; + wire \u13/icc_r_reg_n_0_[21] ; + wire \u13/icc_r_reg_n_0_[22] ; + wire \u13/icc_r_reg_n_0_[23] ; + wire \u13/icc_r_reg_n_0_[4] ; + wire \u13/icc_r_reg_n_0_[5] ; + wire \u13/icc_r_reg_n_0_[6] ; + wire \u13/icc_r_reg_n_0_[7] ; + wire \u13/icc_r_reg_n_0_[8] ; + wire \u13/icc_r_reg_n_0_[9] ; + wire [28:0]\u13/intm ; + wire \u13/intm_r0 ; + wire [28:0]\u13/ints ; + wire \u13/occ00 ; + wire \u13/occ0_r_reg_n_0_[0] ; + wire \u13/occ0_r_reg_n_0_[12] ; + wire \u13/occ0_r_reg_n_0_[13] ; + wire \u13/occ0_r_reg_n_0_[14] ; + wire \u13/occ0_r_reg_n_0_[15] ; + wire \u13/occ0_r_reg_n_0_[16] ; + wire \u13/occ0_r_reg_n_0_[17] ; + wire \u13/occ0_r_reg_n_0_[1] ; + wire \u13/occ0_r_reg_n_0_[20] ; + wire \u13/occ0_r_reg_n_0_[21] ; + wire \u13/occ0_r_reg_n_0_[22] ; + wire \u13/occ0_r_reg_n_0_[23] ; + wire \u13/occ0_r_reg_n_0_[24] ; + wire \u13/occ0_r_reg_n_0_[25] ; + wire \u13/occ0_r_reg_n_0_[28] ; + wire \u13/occ0_r_reg_n_0_[29] ; + wire \u13/occ0_r_reg_n_0_[30] ; + wire \u13/occ0_r_reg_n_0_[31] ; + wire \u13/occ0_r_reg_n_0_[4] ; + wire \u13/occ0_r_reg_n_0_[5] ; + wire \u13/occ0_r_reg_n_0_[6] ; + wire \u13/occ0_r_reg_n_0_[7] ; + wire \u13/occ0_r_reg_n_0_[8] ; + wire \u13/occ0_r_reg_n_0_[9] ; + wire \u13/occ1_r0 ; + wire \u13/occ1_r_reg_n_0_[0] ; + wire \u13/occ1_r_reg_n_0_[12] ; + wire \u13/occ1_r_reg_n_0_[13] ; + wire \u13/occ1_r_reg_n_0_[14] ; + wire \u13/occ1_r_reg_n_0_[15] ; + wire \u13/occ1_r_reg_n_0_[1] ; + wire \u13/occ1_r_reg_n_0_[4] ; + wire \u13/occ1_r_reg_n_0_[5] ; + wire \u13/occ1_r_reg_n_0_[6] ; + wire \u13/occ1_r_reg_n_0_[7] ; + wire \u13/occ1_r_reg_n_0_[8] ; + wire \u13/occ1_r_reg_n_0_[9] ; + wire \u14/p_0_in ; + wire \u14/u0/en_out_l20 ; + wire \u14/u0/en_out_l2_reg_n_0 ; + wire \u14/u0/full_empty_r ; + wire \u14/u1/en_out_l20 ; + wire \u14/u1/en_out_l2_reg_n_0 ; + wire \u14/u1/full_empty_r ; + wire \u14/u2/en_out_l20 ; + wire \u14/u2/en_out_l2_reg_n_0 ; + wire \u14/u2/full_empty_r ; + wire \u14/u3/en_out_l20 ; + wire \u14/u3/en_out_l2_reg_n_0 ; + wire \u14/u3/full_empty_r ; + wire \u14/u4/en_out_l20 ; + wire \u14/u4/en_out_l2_reg_n_0 ; + wire \u14/u4/full_empty_r ; + wire \u14/u5/en_out_l20 ; + wire \u14/u5/en_out_l2_reg_n_0 ; + wire \u14/u5/full_empty_r ; + wire \u14/u6/en_out_l20 ; + wire \u14/u6/en_out_l2_reg_n_0 ; + wire \u14/u6/en_out_l_reg_n_0 ; + wire \u14/u6/full_empty_r ; + wire \u14/u7/en_out_l20 ; + wire \u14/u7/en_out_l2_reg_n_0 ; + wire \u14/u7/en_out_l_reg_n_0 ; + wire \u14/u7/full_empty_r ; + wire \u14/u8/en_out_l20 ; + wire \u14/u8/en_out_l2_reg_n_0 ; + wire \u14/u8/en_out_l_reg_n_0 ; + wire \u14/u8/full_empty_r ; + wire \u15/crac_rd ; + wire \u15/crac_rd_done0 ; + wire \u15/crac_we_r ; + wire \u15/rdd1 ; + wire \u15/rdd2 ; + wire \u15/rdd3 ; + wire \u15/valid_r ; + wire \u16/u0/dma_req_r1 ; + wire \u16/u0/dma_req_r10 ; + wire \u16/u1/dma_req_r1 ; + wire \u16/u1/dma_req_r10 ; + wire \u16/u2/dma_req_r1 ; + wire \u16/u2/dma_req_r10 ; + wire \u16/u3/dma_req_r1 ; + wire \u16/u3/dma_req_r10 ; + wire \u16/u4/dma_req_r1 ; + wire \u16/u4/dma_req_r10 ; + wire \u16/u5/dma_req_r1 ; + wire \u16/u5/dma_req_r10 ; + wire \u16/u6/dma_req_r1 ; + wire \u16/u6/dma_req_r10 ; + wire \u16/u7/dma_req_r1 ; + wire \u16/u7/dma_req_r10 ; + wire \u16/u8/dma_req_r1 ; + wire \u16/u8/dma_req_r10 ; + wire \u17/int_set_reg0 ; + wire \u17/int_set_reg00_out ; + wire \u18/int_set_reg0 ; + wire \u18/int_set_reg00_out ; + wire \u19/int_set_reg0 ; + wire \u19/int_set_reg00_out ; + wire \u2/bit_clk_e ; + wire \u2/bit_clk_e0 ; + wire \u2/bit_clk_r ; + wire \u2/bit_clk_r1 ; + wire \u2/clear ; + wire [7:0]\u2/cnt_reg ; + wire \u2/p_0_in ; + wire [3:0]\u2/res_cnt_reg ; + wire \u2/sync_beat ; + wire \u2/sync_beat0 ; + wire \u2/sync_resume_reg_n_0 ; + wire \u2/to ; + wire [5:0]\u2/to_cnt_reg ; + wire \u20/int_set_reg0 ; + wire \u20/int_set_reg00_out ; + wire \u21/int_set_reg0 ; + wire \u21/int_set_reg00_out ; + wire \u22/int_set_reg0 ; + wire \u22/int_set_reg00_out ; + wire \u23/int_set_reg0 ; + wire \u23/int_set_reg00_out ; + wire \u24/int_set_reg0 ; + wire \u24/int_set_reg00_out ; + wire \u25/int_set_reg0 ; + wire \u25/int_set_reg00_out ; + wire [2:0]\u26/cnt ; + wire [5:0]\u26/ps_cnt_reg ; + wire \u3/dout[0]_i_1_n_0 ; + wire \u3/dout[10]_i_1_n_0 ; + wire \u3/dout[10]_i_2_n_0 ; + wire \u3/dout[11]_i_1_n_0 ; + wire \u3/dout[11]_i_2_n_0 ; + wire \u3/dout[12]_i_1_n_0 ; + wire \u3/dout[12]_i_2_n_0 ; + wire \u3/dout[13]_i_1_n_0 ; + wire \u3/dout[13]_i_2_n_0 ; + wire \u3/dout[14]_i_1_n_0 ; + wire \u3/dout[14]_i_2_n_0 ; + wire \u3/dout[15]_i_1_n_0 ; + wire \u3/dout[15]_i_2_n_0 ; + wire \u3/dout[16]_i_1_n_0 ; + wire \u3/dout[16]_i_2_n_0 ; + wire \u3/dout[17]_i_1_n_0 ; + wire \u3/dout[17]_i_2_n_0 ; + wire \u3/dout[18]_i_1_n_0 ; + wire \u3/dout[18]_i_2_n_0 ; + wire \u3/dout[19]_i_3_n_0 ; + wire \u3/dout[19]_i_4_n_0 ; + wire \u3/dout[1]_i_1_n_0 ; + wire \u3/dout[2]_i_1_n_0 ; + wire \u3/dout[3]_i_1_n_0 ; + wire \u3/dout[4]_i_1_n_0 ; + wire \u3/dout[4]_i_2_n_0 ; + wire \u3/dout[5]_i_1_n_0 ; + wire \u3/dout[5]_i_2_n_0 ; + wire \u3/dout[6]_i_1_n_0 ; + wire \u3/dout[6]_i_2_n_0 ; + wire \u3/dout[7]_i_1_n_0 ; + wire \u3/dout[7]_i_2_n_0 ; + wire \u3/dout[8]_i_1_n_0 ; + wire \u3/dout[8]_i_2_n_0 ; + wire \u3/dout[9]_i_1_n_0 ; + wire \u3/dout[9]_i_2_n_0 ; + wire \u3/empty0 ; + wire [1:0]\u3/p_0_in ; + wire \u3/p_1_in ; + wire \u3/rp_reg_n_0_[0] ; + wire \u3/rp_reg_n_0_[3] ; + wire [1:1]\u3/status0 ; + wire \u3/wp_reg_n_0_[0] ; + wire \u3/wp_reg_n_0_[1] ; + wire \u4/dout[0]_i_1_n_0 ; + wire \u4/dout[10]_i_1_n_0 ; + wire \u4/dout[10]_i_2_n_0 ; + wire \u4/dout[11]_i_1_n_0 ; + wire \u4/dout[11]_i_2_n_0 ; + wire \u4/dout[12]_i_1_n_0 ; + wire \u4/dout[12]_i_2_n_0 ; + wire \u4/dout[13]_i_1_n_0 ; + wire \u4/dout[13]_i_2_n_0 ; + wire \u4/dout[14]_i_1_n_0 ; + wire \u4/dout[14]_i_2_n_0 ; + wire \u4/dout[15]_i_1_n_0 ; + wire \u4/dout[15]_i_2_n_0 ; + wire \u4/dout[16]_i_1_n_0 ; + wire \u4/dout[16]_i_2_n_0 ; + wire \u4/dout[17]_i_1_n_0 ; + wire \u4/dout[17]_i_2_n_0 ; + wire \u4/dout[18]_i_1_n_0 ; + wire \u4/dout[18]_i_2_n_0 ; + wire \u4/dout[19]_i_3_n_0 ; + wire \u4/dout[19]_i_4_n_0 ; + wire \u4/dout[1]_i_1_n_0 ; + wire \u4/dout[2]_i_1_n_0 ; + wire \u4/dout[3]_i_1_n_0 ; + wire \u4/dout[4]_i_1_n_0 ; + wire \u4/dout[4]_i_2_n_0 ; + wire \u4/dout[5]_i_1_n_0 ; + wire \u4/dout[5]_i_2_n_0 ; + wire \u4/dout[6]_i_1_n_0 ; + wire \u4/dout[6]_i_2_n_0 ; + wire \u4/dout[7]_i_1_n_0 ; + wire \u4/dout[7]_i_2_n_0 ; + wire \u4/dout[8]_i_1_n_0 ; + wire \u4/dout[8]_i_2_n_0 ; + wire \u4/dout[9]_i_1_n_0 ; + wire \u4/dout[9]_i_2_n_0 ; + wire \u4/empty0 ; + wire [1:0]\u4/p_0_in ; + wire \u4/p_1_in ; + wire \u4/rp_reg_n_0_[0] ; + wire \u4/rp_reg_n_0_[3] ; + wire [1:1]\u4/status0 ; + wire \u4/wp_reg_n_0_[0] ; + wire \u4/wp_reg_n_0_[1] ; + wire \u5/dout[0]_i_1_n_0 ; + wire \u5/dout[10]_i_1_n_0 ; + wire \u5/dout[10]_i_2_n_0 ; + wire \u5/dout[11]_i_1_n_0 ; + wire \u5/dout[11]_i_2_n_0 ; + wire \u5/dout[12]_i_1_n_0 ; + wire \u5/dout[12]_i_2_n_0 ; + wire \u5/dout[13]_i_1_n_0 ; + wire \u5/dout[13]_i_2_n_0 ; + wire \u5/dout[14]_i_1_n_0 ; + wire \u5/dout[14]_i_2_n_0 ; + wire \u5/dout[15]_i_1_n_0 ; + wire \u5/dout[15]_i_2_n_0 ; + wire \u5/dout[16]_i_1_n_0 ; + wire \u5/dout[16]_i_2_n_0 ; + wire \u5/dout[17]_i_1_n_0 ; + wire \u5/dout[17]_i_2_n_0 ; + wire \u5/dout[18]_i_1_n_0 ; + wire \u5/dout[18]_i_2_n_0 ; + wire \u5/dout[19]_i_3_n_0 ; + wire \u5/dout[19]_i_4_n_0 ; + wire \u5/dout[1]_i_1_n_0 ; + wire \u5/dout[2]_i_1_n_0 ; + wire \u5/dout[3]_i_1_n_0 ; + wire \u5/dout[4]_i_1_n_0 ; + wire \u5/dout[4]_i_2_n_0 ; + wire \u5/dout[5]_i_1_n_0 ; + wire \u5/dout[5]_i_2_n_0 ; + wire \u5/dout[6]_i_1_n_0 ; + wire \u5/dout[6]_i_2_n_0 ; + wire \u5/dout[7]_i_1_n_0 ; + wire \u5/dout[7]_i_2_n_0 ; + wire \u5/dout[8]_i_1_n_0 ; + wire \u5/dout[8]_i_2_n_0 ; + wire \u5/dout[9]_i_1_n_0 ; + wire \u5/dout[9]_i_2_n_0 ; + wire \u5/empty0 ; + wire [1:0]\u5/p_0_in ; + wire \u5/p_1_in ; + wire \u5/rp_reg_n_0_[0] ; + wire \u5/rp_reg_n_0_[3] ; + wire [1:1]\u5/status0 ; + wire \u5/wp_reg_n_0_[0] ; + wire \u5/wp_reg_n_0_[1] ; + wire \u6/dout[0]_i_1_n_0 ; + wire \u6/dout[10]_i_1_n_0 ; + wire \u6/dout[10]_i_2_n_0 ; + wire \u6/dout[11]_i_1_n_0 ; + wire \u6/dout[11]_i_2_n_0 ; + wire \u6/dout[12]_i_1_n_0 ; + wire \u6/dout[12]_i_2_n_0 ; + wire \u6/dout[13]_i_1_n_0 ; + wire \u6/dout[13]_i_2_n_0 ; + wire \u6/dout[14]_i_1_n_0 ; + wire \u6/dout[14]_i_2_n_0 ; + wire \u6/dout[15]_i_1_n_0 ; + wire \u6/dout[15]_i_2_n_0 ; + wire \u6/dout[16]_i_1_n_0 ; + wire \u6/dout[16]_i_2_n_0 ; + wire \u6/dout[17]_i_1_n_0 ; + wire \u6/dout[17]_i_2_n_0 ; + wire \u6/dout[18]_i_1_n_0 ; + wire \u6/dout[18]_i_2_n_0 ; + wire \u6/dout[19]_i_3_n_0 ; + wire \u6/dout[19]_i_4_n_0 ; + wire \u6/dout[1]_i_1_n_0 ; + wire \u6/dout[2]_i_1_n_0 ; + wire \u6/dout[3]_i_1_n_0 ; + wire \u6/dout[4]_i_1_n_0 ; + wire \u6/dout[4]_i_2_n_0 ; + wire \u6/dout[5]_i_1_n_0 ; + wire \u6/dout[5]_i_2_n_0 ; + wire \u6/dout[6]_i_1_n_0 ; + wire \u6/dout[6]_i_2_n_0 ; + wire \u6/dout[7]_i_1_n_0 ; + wire \u6/dout[7]_i_2_n_0 ; + wire \u6/dout[8]_i_1_n_0 ; + wire \u6/dout[8]_i_2_n_0 ; + wire \u6/dout[9]_i_1_n_0 ; + wire \u6/dout[9]_i_2_n_0 ; + wire \u6/empty0 ; + wire [1:0]\u6/p_0_in ; + wire \u6/p_1_in ; + wire \u6/rp_reg_n_0_[0] ; + wire \u6/rp_reg_n_0_[3] ; + wire [1:1]\u6/status0 ; + wire \u6/wp_reg_n_0_[0] ; + wire \u6/wp_reg_n_0_[1] ; + wire \u7/dout[0]_i_1_n_0 ; + wire \u7/dout[10]_i_1_n_0 ; + wire \u7/dout[10]_i_2_n_0 ; + wire \u7/dout[11]_i_1_n_0 ; + wire \u7/dout[11]_i_2_n_0 ; + wire \u7/dout[12]_i_1_n_0 ; + wire \u7/dout[12]_i_2_n_0 ; + wire \u7/dout[13]_i_1_n_0 ; + wire \u7/dout[13]_i_2_n_0 ; + wire \u7/dout[14]_i_1_n_0 ; + wire \u7/dout[14]_i_2_n_0 ; + wire \u7/dout[15]_i_1_n_0 ; + wire \u7/dout[15]_i_2_n_0 ; + wire \u7/dout[16]_i_1_n_0 ; + wire \u7/dout[16]_i_2_n_0 ; + wire \u7/dout[17]_i_1_n_0 ; + wire \u7/dout[17]_i_2_n_0 ; + wire \u7/dout[18]_i_1_n_0 ; + wire \u7/dout[18]_i_2_n_0 ; + wire \u7/dout[19]_i_3_n_0 ; + wire \u7/dout[19]_i_4_n_0 ; + wire \u7/dout[1]_i_1_n_0 ; + wire \u7/dout[2]_i_1_n_0 ; + wire \u7/dout[3]_i_1_n_0 ; + wire \u7/dout[4]_i_1_n_0 ; + wire \u7/dout[4]_i_2_n_0 ; + wire \u7/dout[5]_i_1_n_0 ; + wire \u7/dout[5]_i_2_n_0 ; + wire \u7/dout[6]_i_1_n_0 ; + wire \u7/dout[6]_i_2_n_0 ; + wire \u7/dout[7]_i_1_n_0 ; + wire \u7/dout[7]_i_2_n_0 ; + wire \u7/dout[8]_i_1_n_0 ; + wire \u7/dout[8]_i_2_n_0 ; + wire \u7/dout[9]_i_1_n_0 ; + wire \u7/dout[9]_i_2_n_0 ; + wire \u7/empty0 ; + wire [1:0]\u7/p_0_in ; + wire \u7/p_1_in ; + wire \u7/rp_reg_n_0_[0] ; + wire \u7/rp_reg_n_0_[3] ; + wire [1:1]\u7/status0 ; + wire \u7/wp_reg_n_0_[0] ; + wire \u7/wp_reg_n_0_[1] ; + wire \u8/dout[0]_i_1_n_0 ; + wire \u8/dout[10]_i_1_n_0 ; + wire \u8/dout[10]_i_2_n_0 ; + wire \u8/dout[11]_i_1_n_0 ; + wire \u8/dout[11]_i_2_n_0 ; + wire \u8/dout[12]_i_1_n_0 ; + wire \u8/dout[12]_i_2_n_0 ; + wire \u8/dout[13]_i_1_n_0 ; + wire \u8/dout[13]_i_2_n_0 ; + wire \u8/dout[14]_i_1_n_0 ; + wire \u8/dout[14]_i_2_n_0 ; + wire \u8/dout[15]_i_1_n_0 ; + wire \u8/dout[15]_i_2_n_0 ; + wire \u8/dout[16]_i_1_n_0 ; + wire \u8/dout[16]_i_2_n_0 ; + wire \u8/dout[17]_i_1_n_0 ; + wire \u8/dout[17]_i_2_n_0 ; + wire \u8/dout[18]_i_1_n_0 ; + wire \u8/dout[18]_i_2_n_0 ; + wire \u8/dout[19]_i_3_n_0 ; + wire \u8/dout[19]_i_4_n_0 ; + wire \u8/dout[1]_i_1_n_0 ; + wire \u8/dout[2]_i_1_n_0 ; + wire \u8/dout[3]_i_1_n_0 ; + wire \u8/dout[4]_i_1_n_0 ; + wire \u8/dout[4]_i_2_n_0 ; + wire \u8/dout[5]_i_1_n_0 ; + wire \u8/dout[5]_i_2_n_0 ; + wire \u8/dout[6]_i_1_n_0 ; + wire \u8/dout[6]_i_2_n_0 ; + wire \u8/dout[7]_i_1_n_0 ; + wire \u8/dout[7]_i_2_n_0 ; + wire \u8/dout[8]_i_1_n_0 ; + wire \u8/dout[8]_i_2_n_0 ; + wire \u8/dout[9]_i_1_n_0 ; + wire \u8/dout[9]_i_2_n_0 ; + wire \u8/empty0 ; + wire [1:0]\u8/p_0_in ; + wire \u8/p_1_in ; + wire \u8/rp_reg_n_0_[0] ; + wire \u8/rp_reg_n_0_[3] ; + wire [1:1]\u8/status0 ; + wire \u8/wp_reg_n_0_[0] ; + wire \u8/wp_reg_n_0_[1] ; + wire [31:0]\u9/din_tmp ; + wire [15:0]\u9/din_tmp1 ; + wire \u9/din_tmp10 ; + wire \u9/empty0 ; + wire \u9/full0 ; + wire [1:0]\u9/p_1_in ; + wire \u9/rp_reg_n_0_[0] ; + wire \u9/rp_reg_n_0_[1] ; + wire \u9/rp_reg_n_0_[2] ; + wire [1:1]\u9/status0 ; + wire \u9/wp_reg_n_0_[0] ; + wire \u9/wp_reg_n_0_[3] ; + wire valid; + wire valid_i_1_n_0; + wire valid_s; + wire valid_s1; + wire wb_ack_o; + wire wb_ack_o_i_2_n_0; + wire wb_ack_o_i_3_n_0; + wire [31:0]wb_addr_i; + wire wb_cyc_i; + wire [31:0]wb_data_i; + wire [31:0]wb_data_o; + wire \wb_data_o[0]_i_1_n_0 ; + wire \wb_data_o[0]_i_2_n_0 ; + wire \wb_data_o[0]_i_3_n_0 ; + wire \wb_data_o[0]_i_4_n_0 ; + wire \wb_data_o[10]_i_1_n_0 ; + wire \wb_data_o[10]_i_2_n_0 ; + wire \wb_data_o[10]_i_3_n_0 ; + wire \wb_data_o[10]_i_4_n_0 ; + wire \wb_data_o[11]_i_1_n_0 ; + wire \wb_data_o[11]_i_2_n_0 ; + wire \wb_data_o[11]_i_3_n_0 ; + wire \wb_data_o[11]_i_4_n_0 ; + wire \wb_data_o[12]_i_1_n_0 ; + wire \wb_data_o[12]_i_2_n_0 ; + wire \wb_data_o[12]_i_3_n_0 ; + wire \wb_data_o[12]_i_4_n_0 ; + wire \wb_data_o[13]_i_1_n_0 ; + wire \wb_data_o[13]_i_2_n_0 ; + wire \wb_data_o[13]_i_3_n_0 ; + wire \wb_data_o[13]_i_4_n_0 ; + wire \wb_data_o[14]_i_1_n_0 ; + wire \wb_data_o[14]_i_2_n_0 ; + wire \wb_data_o[14]_i_3_n_0 ; + wire \wb_data_o[14]_i_4_n_0 ; + wire \wb_data_o[15]_i_1_n_0 ; + wire \wb_data_o[15]_i_2_n_0 ; + wire \wb_data_o[15]_i_3_n_0 ; + wire \wb_data_o[15]_i_4_n_0 ; + wire \wb_data_o[16]_i_1_n_0 ; + wire \wb_data_o[16]_i_2_n_0 ; + wire \wb_data_o[16]_i_3_n_0 ; + wire \wb_data_o[17]_i_1_n_0 ; + wire \wb_data_o[17]_i_2_n_0 ; + wire \wb_data_o[17]_i_3_n_0 ; + wire \wb_data_o[18]_i_1_n_0 ; + wire \wb_data_o[18]_i_2_n_0 ; + wire \wb_data_o[18]_i_3_n_0 ; + wire \wb_data_o[19]_i_1_n_0 ; + wire \wb_data_o[19]_i_2_n_0 ; + wire \wb_data_o[19]_i_3_n_0 ; + wire \wb_data_o[1]_i_1_n_0 ; + wire \wb_data_o[1]_i_2_n_0 ; + wire \wb_data_o[1]_i_3_n_0 ; + wire \wb_data_o[1]_i_4_n_0 ; + wire \wb_data_o[1]_i_5_n_0 ; + wire \wb_data_o[20]_i_1_n_0 ; + wire \wb_data_o[20]_i_2_n_0 ; + wire \wb_data_o[20]_i_3_n_0 ; + wire \wb_data_o[21]_i_1_n_0 ; + wire \wb_data_o[21]_i_2_n_0 ; + wire \wb_data_o[21]_i_3_n_0 ; + wire \wb_data_o[22]_i_1_n_0 ; + wire \wb_data_o[22]_i_2_n_0 ; + wire \wb_data_o[22]_i_3_n_0 ; + wire \wb_data_o[23]_i_1_n_0 ; + wire \wb_data_o[23]_i_2_n_0 ; + wire \wb_data_o[23]_i_3_n_0 ; + wire \wb_data_o[23]_i_4_n_0 ; + wire \wb_data_o[23]_i_5_n_0 ; + wire \wb_data_o[24]_i_1_n_0 ; + wire \wb_data_o[24]_i_2_n_0 ; + wire \wb_data_o[24]_i_3_n_0 ; + wire \wb_data_o[25]_i_1_n_0 ; + wire \wb_data_o[25]_i_2_n_0 ; + wire \wb_data_o[25]_i_3_n_0 ; + wire \wb_data_o[26]_i_1_n_0 ; + wire \wb_data_o[26]_i_2_n_0 ; + wire \wb_data_o[26]_i_3_n_0 ; + wire \wb_data_o[27]_i_1_n_0 ; + wire \wb_data_o[27]_i_2_n_0 ; + wire \wb_data_o[27]_i_3_n_0 ; + wire \wb_data_o[28]_i_1_n_0 ; + wire \wb_data_o[28]_i_2_n_0 ; + wire \wb_data_o[28]_i_3_n_0 ; + wire \wb_data_o[29]_i_1_n_0 ; + wire \wb_data_o[29]_i_2_n_0 ; + wire \wb_data_o[2]_i_1_n_0 ; + wire \wb_data_o[2]_i_2_n_0 ; + wire \wb_data_o[2]_i_3_n_0 ; + wire \wb_data_o[2]_i_4_n_0 ; + wire \wb_data_o[30]_i_1_n_0 ; + wire \wb_data_o[30]_i_2_n_0 ; + wire \wb_data_o[30]_i_3_n_0 ; + wire \wb_data_o[31]_i_1_n_0 ; + wire \wb_data_o[31]_i_2_n_0 ; + wire \wb_data_o[31]_i_3_n_0 ; + wire \wb_data_o[3]_i_1_n_0 ; + wire \wb_data_o[3]_i_2_n_0 ; + wire \wb_data_o[3]_i_3_n_0 ; + wire \wb_data_o[3]_i_4_n_0 ; + wire \wb_data_o[4]_i_1_n_0 ; + wire \wb_data_o[4]_i_2_n_0 ; + wire \wb_data_o[4]_i_3_n_0 ; + wire \wb_data_o[4]_i_4_n_0 ; + wire \wb_data_o[5]_i_1_n_0 ; + wire \wb_data_o[5]_i_2_n_0 ; + wire \wb_data_o[5]_i_3_n_0 ; + wire \wb_data_o[5]_i_4_n_0 ; + wire \wb_data_o[6]_i_1_n_0 ; + wire \wb_data_o[6]_i_2_n_0 ; + wire \wb_data_o[6]_i_3_n_0 ; + wire \wb_data_o[6]_i_4_n_0 ; + wire \wb_data_o[7]_i_1_n_0 ; + wire \wb_data_o[7]_i_2_n_0 ; + wire \wb_data_o[7]_i_3_n_0 ; + wire \wb_data_o[7]_i_4_n_0 ; + wire \wb_data_o[8]_i_1_n_0 ; + wire \wb_data_o[8]_i_2_n_0 ; + wire \wb_data_o[8]_i_3_n_0 ; + wire \wb_data_o[8]_i_4_n_0 ; + wire \wb_data_o[9]_i_1_n_0 ; + wire \wb_data_o[9]_i_2_n_0 ; + wire \wb_data_o[9]_i_3_n_0 ; + wire \wb_data_o[9]_i_4_n_0 ; + wire [31:0]wb_din; + wire wb_stb_i; + wire wb_we_i; + wire we1_i_2_n_0; + wire \wp[0]_i_1__0_n_0 ; + wire \wp[0]_i_1__1_n_0 ; + wire \wp[0]_i_1__2_n_0 ; + wire \wp[0]_i_1__3_n_0 ; + wire \wp[0]_i_1__4_n_0 ; + wire \wp[0]_i_1__5_n_0 ; + wire \wp[0]_i_1__6_n_0 ; + wire \wp[0]_i_1__7_n_0 ; + wire \wp[0]_i_1_n_0 ; + wire \wp[1]_i_1__0_n_0 ; + wire \wp[1]_i_1__1_n_0 ; + wire \wp[1]_i_1__2_n_0 ; + wire \wp[1]_i_1__3_n_0 ; + wire \wp[1]_i_1__4_n_0 ; + wire \wp[1]_i_1_n_0 ; + wire \wp[2]_i_1__0_n_0 ; + wire \wp[2]_i_1__1_n_0 ; + wire \wp[2]_i_1__2_n_0 ; + wire \wp[2]_i_1__3_n_0 ; + wire \wp[2]_i_1__4_n_0 ; + wire \wp[2]_i_1_n_0 ; + wire \wp[3]_i_1__0_n_0 ; + wire \wp[3]_i_1__1_n_0 ; + wire \wp[3]_i_1_n_0 ; + wire [3:1]wp_p1; + wire [3:1]wp_p1__0; + wire [3:1]wp_p1__1; + + GND GND + (.G(\ )); + VCC VCC + (.P(\ )); + LUT5 #( + .INIT(32'h55550100)) + ac97_rst__i_1 + (.I0(ac97_rst_force), + .I1(\u26/cnt [0]), + .I2(\u26/cnt [1]), + .I3(\u26/cnt [2]), + .I4(ac97_reset_pad_o_), + .O(ac97_rst__i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT5 #( + .INIT(32'h00000008)) + ac97_rst_force_i_1 + (.I0(wb_din[0]), + .I1(rf_we), + .I2(wb_addr_i[2]), + .I3(wb_addr_i[3]), + .I4(wb_addr_i[4]), + .O(ac97_rst_force_i_1_n_0)); + LUT2 #( + .INIT(4'h6)) + bit_clk_e_i_1 + (.I0(\u2/bit_clk_r1 ), + .I1(\u2/bit_clk_r ), + .O(\u2/bit_clk_e0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h0000AA51)) + \cnt[0]_i_1 + (.I0(\cnt[2]_i_2_n_0 ), + .I1(\u26/cnt [2]), + .I2(\u26/cnt [1]), + .I3(\u26/cnt [0]), + .I4(ac97_rst_force), + .O(\cnt[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair219" *) + LUT2 #( + .INIT(4'hB)) + \cnt[0]_i_1__0 + (.I0(suspended_o), + .I1(\u2/cnt_reg [0]), + .O(\cnt[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT4 #( + .INIT(16'h009C)) + \cnt[1]_i_1 + (.I0(\cnt[2]_i_2_n_0 ), + .I1(\u26/cnt [1]), + .I2(\u26/cnt [0]), + .I3(ac97_rst_force), + .O(\cnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT3 #( + .INIT(8'hF6)) + \cnt[1]_i_1__0 + (.I0(\u2/cnt_reg [1]), + .I1(\u2/cnt_reg [0]), + .I2(suspended_o), + .O(p_0_in__1__0[1])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h00009CCC)) + \cnt[2]_i_1 + (.I0(\cnt[2]_i_2_n_0 ), + .I1(\u26/cnt [2]), + .I2(\u26/cnt [1]), + .I3(\u26/cnt [0]), + .I4(ac97_rst_force), + .O(\cnt[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT4 #( + .INIT(16'hFF6A)) + \cnt[2]_i_1__0 + (.I0(\u2/cnt_reg [2]), + .I1(\u2/cnt_reg [1]), + .I2(\u2/cnt_reg [0]), + .I3(suspended_o), + .O(p_0_in__1__0[2])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF7FF)) + \cnt[2]_i_2 + (.I0(\u26/ps_cnt_reg [0]), + .I1(\u26/ps_cnt_reg [4]), + .I2(\u26/ps_cnt_reg [3]), + .I3(\u26/ps_cnt_reg [5]), + .I4(\u26/ps_cnt_reg [2]), + .I5(\u26/ps_cnt_reg [1]), + .O(\cnt[2]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT5 #( + .INIT(32'hFFFF6AAA)) + \cnt[3]_i_1 + (.I0(\u2/cnt_reg [3]), + .I1(\u2/cnt_reg [2]), + .I2(\u2/cnt_reg [0]), + .I3(\u2/cnt_reg [1]), + .I4(suspended_o), + .O(p_0_in__1__0[3])); + LUT6 #( + .INIT(64'hFFFFFFFF6AAAAAAA)) + \cnt[4]_i_1 + (.I0(\u2/cnt_reg [4]), + .I1(\u2/cnt_reg [3]), + .I2(\u2/cnt_reg [1]), + .I3(\u2/cnt_reg [2]), + .I4(\u2/cnt_reg [0]), + .I5(suspended_o), + .O(p_0_in__1__0[4])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hFF6A)) + \cnt[5]_i_1 + (.I0(\u2/cnt_reg [5]), + .I1(\cnt[7]_i_2_n_0 ), + .I2(\u2/cnt_reg [4]), + .I3(suspended_o), + .O(p_0_in__1__0[5])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT5 #( + .INIT(32'hFFFF6AAA)) + \cnt[6]_i_1 + (.I0(\u2/cnt_reg [6]), + .I1(\cnt[7]_i_2_n_0 ), + .I2(\u2/cnt_reg [5]), + .I3(\u2/cnt_reg [4]), + .I4(suspended_o), + .O(p_0_in__1__0[6])); + LUT6 #( + .INIT(64'hFFFFFFFF6AAAAAAA)) + \cnt[7]_i_1 + (.I0(\u2/cnt_reg [7]), + .I1(\u2/cnt_reg [6]), + .I2(\u2/cnt_reg [4]), + .I3(\u2/cnt_reg [5]), + .I4(\cnt[7]_i_2_n_0 ), + .I5(suspended_o), + .O(p_0_in__1__0[7])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h8000)) + \cnt[7]_i_2 + (.I0(\u2/cnt_reg [3]), + .I1(\u2/cnt_reg [1]), + .I2(\u2/cnt_reg [2]), + .I3(\u2/cnt_reg [0]), + .O(\cnt[7]_i_2_n_0 )); + LUT4 #( + .INIT(16'h0400)) + \crac_dout_r[15]_i_1 + (.I0(wb_addr_i[2]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[3]), + .I3(rf_we), + .O(crac_we)); + LUT3 #( + .INIT(8'h40)) + crac_rd_done_i_1 + (.I0(\u15/valid_r ), + .I1(valid_s), + .I2(\u15/rdd3 ), + .O(\u15/crac_rd_done0 )); + LUT6 #( + .INIT(64'hFFFF8FFF88888888)) + crac_rd_i_1 + (.I0(crac_out[31]), + .I1(\u15/crac_we_r ), + .I2(\u15/rdd1 ), + .I3(valid_s), + .I4(\u15/valid_r ), + .I5(\u15/crac_rd ), + .O(crac_rd_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT4 #( + .INIT(16'hEFE0)) + crac_valid_r_i_1 + (.I0(\u15/crac_rd ), + .I1(crac_wr), + .I2(valid_s), + .I3(out_slt0[14]), + .O(crac_valid_r_i_1_n_0)); + LUT5 #( + .INIT(32'hF4FF4444)) + crac_wr_i_1 + (.I0(crac_out[31]), + .I1(\u15/crac_we_r ), + .I2(valid_s), + .I3(\u15/valid_r ), + .I4(crac_wr), + .O(crac_wr_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT3 #( + .INIT(8'hB8)) + crac_wr_r_i_1 + (.I0(crac_wr), + .I1(valid_s), + .I2(out_slt0[13]), + .O(crac_wr_r_i_1_n_0)); + LUT4 #( + .INIT(16'h0040)) + \din_tmp1[15]_i_1 + (.I0(\u14/u6/en_out_l2_reg_n_0 ), + .I1(\u14/u6/en_out_l_reg_n_0 ), + .I2(in_valid_s[0]), + .I3(\u9/wp_reg_n_0_[0] ), + .O(\u9/din_tmp10 )); + LUT4 #( + .INIT(16'h0040)) + \din_tmp1[15]_i_1__0 + (.I0(\u14/u7/en_out_l2_reg_n_0 ), + .I1(\u14/u7/en_out_l_reg_n_0 ), + .I2(in_valid_s[1]), + .I3(\u10/wp_reg_n_0_[0] ), + .O(\u10/din_tmp10 )); + LUT4 #( + .INIT(16'h0040)) + \din_tmp1[15]_i_1__1 + (.I0(\u14/u8/en_out_l2_reg_n_0 ), + .I1(\u14/u8/en_out_l_reg_n_0 ), + .I2(in_valid_s[2]), + .I3(\u11/wp_reg_n_0_[0] ), + .O(\u11/din_tmp10 )); + LUT5 #( + .INIT(32'h00FF0080)) + dma_req_i_1 + (.I0(\int_set[0]_i_1_n_0 ), + .I1(\u16/u0/dma_req_r1 ), + .I2(\u13/occ0_r_reg_n_0_[6] ), + .I3(dma_ack_i[0]), + .I4(dma_req_o[0]), + .O(dma_req_i_1_n_0)); + LUT5 #( + .INIT(32'h00FF0080)) + dma_req_i_1__0 + (.I0(\int_set[0]_i_1__0_n_0 ), + .I1(\u16/u1/dma_req_r1 ), + .I2(\u13/occ0_r_reg_n_0_[14] ), + .I3(dma_ack_i[1]), + .I4(dma_req_o[1]), + .O(dma_req_i_1__0_n_0)); + LUT5 #( + .INIT(32'h00FF0080)) + dma_req_i_1__1 + (.I0(\int_set[0]_i_1__1_n_0 ), + .I1(\u16/u2/dma_req_r1 ), + .I2(\u13/occ0_r_reg_n_0_[22] ), + .I3(dma_ack_i[2]), + .I4(dma_req_o[2]), + .O(dma_req_i_1__1_n_0)); + LUT5 #( + .INIT(32'h00FF0080)) + dma_req_i_1__2 + (.I0(\int_set[0]_i_1__2_n_0 ), + .I1(\u16/u3/dma_req_r1 ), + .I2(\u13/occ0_r_reg_n_0_[30] ), + .I3(dma_ack_i[3]), + .I4(dma_req_o[3]), + .O(dma_req_i_1__2_n_0)); + LUT5 #( + .INIT(32'h00FF0080)) + dma_req_i_1__3 + (.I0(\int_set[0]_i_1__3_n_0 ), + .I1(\u16/u4/dma_req_r1 ), + .I2(\u13/occ1_r_reg_n_0_[6] ), + .I3(dma_ack_i[4]), + .I4(dma_req_o[4]), + .O(dma_req_i_1__3_n_0)); + LUT5 #( + .INIT(32'h00FF0080)) + dma_req_i_1__4 + (.I0(\int_set[0]_i_1__4_n_0 ), + .I1(\u16/u5/dma_req_r1 ), + .I2(\u13/occ1_r_reg_n_0_[14] ), + .I3(dma_ack_i[5]), + .I4(dma_req_o[5]), + .O(dma_req_i_1__4_n_0)); + LUT5 #( + .INIT(32'h00FF0080)) + dma_req_i_1__5 + (.I0(\int_set[0]_i_1__5_n_0 ), + .I1(\u16/u6/dma_req_r1 ), + .I2(\u13/icc_r_reg_n_0_[6] ), + .I3(dma_ack_i[6]), + .I4(dma_req_o[6]), + .O(dma_req_i_1__5_n_0)); + LUT5 #( + .INIT(32'h00FF0080)) + dma_req_i_1__6 + (.I0(\int_set[0]_i_1__6_n_0 ), + .I1(\u16/u7/dma_req_r1 ), + .I2(\u13/icc_r_reg_n_0_[14] ), + .I3(dma_ack_i[7]), + .I4(dma_req_o[7]), + .O(dma_req_i_1__6_n_0)); + LUT5 #( + .INIT(32'h00FF0080)) + dma_req_i_1__7 + (.I0(\int_set[0]_i_1__7_n_0 ), + .I1(\u16/u8/dma_req_r1 ), + .I2(\u13/icc_r_reg_n_0_[22] ), + .I3(dma_ack_i[8]), + .I4(dma_req_o[8]), + .O(dma_req_i_1__7_n_0)); + LUT1 #( + .INIT(2'h1)) + dma_req_i_2 + (.I0(rst_i), + .O(dma_req_i_2_n_0)); + LUT3 #( + .INIT(8'h40)) + dma_req_r1_i_1 + (.I0(dma_ack_i[0]), + .I1(\u13/occ0_r_reg_n_0_[6] ), + .I2(\int_set[0]_i_1_n_0 ), + .O(\u16/u0/dma_req_r10 )); + LUT3 #( + .INIT(8'h40)) + dma_req_r1_i_1__0 + (.I0(dma_ack_i[1]), + .I1(\u13/occ0_r_reg_n_0_[14] ), + .I2(\int_set[0]_i_1__0_n_0 ), + .O(\u16/u1/dma_req_r10 )); + LUT3 #( + .INIT(8'h40)) + dma_req_r1_i_1__1 + (.I0(dma_ack_i[2]), + .I1(\u13/occ0_r_reg_n_0_[22] ), + .I2(\int_set[0]_i_1__1_n_0 ), + .O(\u16/u2/dma_req_r10 )); + LUT3 #( + .INIT(8'h40)) + dma_req_r1_i_1__2 + (.I0(dma_ack_i[3]), + .I1(\u13/occ0_r_reg_n_0_[30] ), + .I2(\int_set[0]_i_1__2_n_0 ), + .O(\u16/u3/dma_req_r10 )); + LUT3 #( + .INIT(8'h40)) + dma_req_r1_i_1__3 + (.I0(dma_ack_i[4]), + .I1(\u13/occ1_r_reg_n_0_[6] ), + .I2(\int_set[0]_i_1__3_n_0 ), + .O(\u16/u4/dma_req_r10 )); + LUT3 #( + .INIT(8'h40)) + dma_req_r1_i_1__4 + (.I0(dma_ack_i[5]), + .I1(\u13/occ1_r_reg_n_0_[14] ), + .I2(\int_set[0]_i_1__4_n_0 ), + .O(\u16/u5/dma_req_r10 )); + LUT3 #( + .INIT(8'h40)) + dma_req_r1_i_1__5 + (.I0(dma_ack_i[6]), + .I1(\u13/icc_r_reg_n_0_[6] ), + .I2(\int_set[0]_i_1__5_n_0 ), + .O(\u16/u6/dma_req_r10 )); + LUT3 #( + .INIT(8'h40)) + dma_req_r1_i_1__6 + (.I0(dma_ack_i[7]), + .I1(\u13/icc_r_reg_n_0_[14] ), + .I2(\int_set[0]_i_1__6_n_0 ), + .O(\u16/u7/dma_req_r10 )); + LUT3 #( + .INIT(8'h40)) + dma_req_r1_i_1__7 + (.I0(dma_ack_i[8]), + .I1(\u13/icc_r_reg_n_0_[22] ), + .I2(\int_set[0]_i_1__7_n_0 ), + .O(\u16/u8/dma_req_r10 )); + LUT1 #( + .INIT(2'h1)) + \dout[19]_i_1 + (.I0(\u13/occ0_r_reg_n_0_[0] ), + .O(\dout[19]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \dout[19]_i_1__0 + (.I0(\u13/occ0_r_reg_n_0_[8] ), + .O(\dout[19]_i_1__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \dout[19]_i_1__1 + (.I0(\u13/occ0_r_reg_n_0_[16] ), + .O(\dout[19]_i_1__1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \dout[19]_i_1__2 + (.I0(\u13/occ0_r_reg_n_0_[24] ), + .O(\dout[19]_i_1__2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \dout[19]_i_1__3 + (.I0(\u13/occ1_r_reg_n_0_[0] ), + .O(\dout[19]_i_1__3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \dout[19]_i_1__4 + (.I0(\u13/occ1_r_reg_n_0_[8] ), + .O(\dout[19]_i_1__4_n_0 )); + LUT3 #( + .INIT(8'h40)) + \dout[19]_i_2 + (.I0(\u14/u0/en_out_l2_reg_n_0 ), + .I1(out_slt0[12]), + .I2(valid_s), + .O(o3_re)); + LUT3 #( + .INIT(8'h40)) + \dout[19]_i_2__0 + (.I0(\u14/u1/en_out_l2_reg_n_0 ), + .I1(out_slt0[11]), + .I2(valid_s), + .O(o4_re)); + LUT3 #( + .INIT(8'h40)) + \dout[19]_i_2__1 + (.I0(\u14/u2/en_out_l2_reg_n_0 ), + .I1(out_slt0[9]), + .I2(valid_s), + .O(o6_re)); + LUT3 #( + .INIT(8'h40)) + \dout[19]_i_2__2 + (.I0(\u14/u3/en_out_l2_reg_n_0 ), + .I1(out_slt0[8]), + .I2(valid_s), + .O(o7_re)); + LUT3 #( + .INIT(8'h40)) + \dout[19]_i_2__3 + (.I0(\u14/u4/en_out_l2_reg_n_0 ), + .I1(out_slt0[7]), + .I2(valid_s), + .O(o8_re)); + LUT3 #( + .INIT(8'h40)) + \dout[19]_i_2__4 + (.I0(\u14/u5/en_out_l2_reg_n_0 ), + .I1(out_slt0[6]), + .I2(valid_s), + .O(o9_re)); + LUT6 #( + .INIT(64'h6090609060900090)) + empty_i_1 + (.I0(\u3/wp_reg_n_0_[0] ), + .I1(\u3/p_0_in [0]), + .I2(empty_i_2_n_0), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(o3_mode[0]), + .I5(o3_mode[1]), + .O(\u3/empty0 )); + LUT6 #( + .INIT(64'h6090609060900090)) + empty_i_1__0 + (.I0(\u4/wp_reg_n_0_[0] ), + .I1(\u4/p_0_in [0]), + .I2(empty_i_2__0_n_0), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(o4_mode[0]), + .I5(o4_mode[1]), + .O(\u4/empty0 )); + LUT6 #( + .INIT(64'h6090609060900090)) + empty_i_1__1 + (.I0(\u5/wp_reg_n_0_[0] ), + .I1(\u5/p_0_in [0]), + .I2(empty_i_2__1_n_0), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(o6_mode[0]), + .I5(o6_mode[1]), + .O(\u5/empty0 )); + LUT6 #( + .INIT(64'h6090609060900090)) + empty_i_1__2 + (.I0(\u6/wp_reg_n_0_[0] ), + .I1(\u6/p_0_in [0]), + .I2(empty_i_2__2_n_0), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(o7_mode[0]), + .I5(o7_mode[1]), + .O(\u6/empty0 )); + LUT6 #( + .INIT(64'h6090609060900090)) + empty_i_1__3 + (.I0(\u7/wp_reg_n_0_[0] ), + .I1(\u7/p_0_in [0]), + .I2(empty_i_2__3_n_0), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(o8_mode[0]), + .I5(o8_mode[1]), + .O(\u7/empty0 )); + LUT6 #( + .INIT(64'h6090609060900090)) + empty_i_1__4 + (.I0(\u8/wp_reg_n_0_[0] ), + .I1(\u8/p_0_in [0]), + .I2(empty_i_2__4_n_0), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(o9_mode[0]), + .I5(o9_mode[1]), + .O(\u8/empty0 )); + LUT6 #( + .INIT(64'h0000000082000082)) + empty_i_1__5 + (.I0(\status[0]_i_1__7_n_0 ), + .I1(\u9/p_1_in [1]), + .I2(\u9/rp_reg_n_0_[1] ), + .I3(\u9/wp_reg_n_0_[3] ), + .I4(\u9/rp_reg_n_0_[2] ), + .I5(empty_i_2__5_n_0), + .O(\u9/empty0 )); + LUT6 #( + .INIT(64'h0000000082000082)) + empty_i_1__6 + (.I0(\status[0]_i_1__6_n_0 ), + .I1(\u10/p_1_in [1]), + .I2(\u10/rp_reg_n_0_[1] ), + .I3(\u10/wp_reg_n_0_[3] ), + .I4(\u10/rp_reg_n_0_[2] ), + .I5(empty_i_2__6_n_0), + .O(\u10/empty0 )); + LUT6 #( + .INIT(64'h0000000082000082)) + empty_i_1__7 + (.I0(\status[0]_i_1__5_n_0 ), + .I1(\u11/p_1_in [1]), + .I2(\u11/rp_reg_n_0_[1] ), + .I3(\u11/wp_reg_n_0_[3] ), + .I4(\u11/rp_reg_n_0_[2] ), + .I5(empty_i_2__7_n_0), + .O(\u11/empty0 )); + LUT6 #( + .INIT(64'h2A95400040002A95)) + empty_i_2 + (.I0(\u3/wp_reg_n_0_[1] ), + .I1(\u3/rp_reg_n_0_[0] ), + .I2(\u3/p_0_in [0]), + .I3(\u3/p_0_in [1]), + .I4(\u3/rp_reg_n_0_[3] ), + .I5(\u3/p_1_in ), + .O(empty_i_2_n_0)); + LUT6 #( + .INIT(64'h2A95400040002A95)) + empty_i_2__0 + (.I0(\u4/wp_reg_n_0_[1] ), + .I1(\u4/rp_reg_n_0_[0] ), + .I2(\u4/p_0_in [0]), + .I3(\u4/p_0_in [1]), + .I4(\u4/rp_reg_n_0_[3] ), + .I5(\u4/p_1_in ), + .O(empty_i_2__0_n_0)); + LUT6 #( + .INIT(64'h2A95400040002A95)) + empty_i_2__1 + (.I0(\u5/wp_reg_n_0_[1] ), + .I1(\u5/rp_reg_n_0_[0] ), + .I2(\u5/p_0_in [0]), + .I3(\u5/p_0_in [1]), + .I4(\u5/rp_reg_n_0_[3] ), + .I5(\u5/p_1_in ), + .O(empty_i_2__1_n_0)); + LUT6 #( + .INIT(64'h2A95400040002A95)) + empty_i_2__2 + (.I0(\u6/wp_reg_n_0_[1] ), + .I1(\u6/rp_reg_n_0_[0] ), + .I2(\u6/p_0_in [0]), + .I3(\u6/p_0_in [1]), + .I4(\u6/rp_reg_n_0_[3] ), + .I5(\u6/p_1_in ), + .O(empty_i_2__2_n_0)); + LUT6 #( + .INIT(64'h2A95400040002A95)) + empty_i_2__3 + (.I0(\u7/wp_reg_n_0_[1] ), + .I1(\u7/rp_reg_n_0_[0] ), + .I2(\u7/p_0_in [0]), + .I3(\u7/p_0_in [1]), + .I4(\u7/rp_reg_n_0_[3] ), + .I5(\u7/p_1_in ), + .O(empty_i_2__3_n_0)); + LUT6 #( + .INIT(64'h2A95400040002A95)) + empty_i_2__4 + (.I0(\u8/wp_reg_n_0_[1] ), + .I1(\u8/rp_reg_n_0_[0] ), + .I2(\u8/p_0_in [0]), + .I3(\u8/p_0_in [1]), + .I4(\u8/rp_reg_n_0_[3] ), + .I5(\u8/p_1_in ), + .O(empty_i_2__4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair133" *) + LUT3 #( + .INIT(8'hFE)) + empty_i_2__5 + (.I0(i3_mode[1]), + .I1(i3_mode[0]), + .I2(\u9/wp_reg_n_0_[0] ), + .O(empty_i_2__5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair134" *) + LUT3 #( + .INIT(8'hFE)) + empty_i_2__6 + (.I0(i4_mode[1]), + .I1(i4_mode[0]), + .I2(\u10/wp_reg_n_0_[0] ), + .O(empty_i_2__6_n_0)); + (* SOFT_HLUTNM = "soft_lutpair135" *) + LUT3 #( + .INIT(8'hFE)) + empty_i_2__7 + (.I0(i6_mode[1]), + .I1(i6_mode[0]), + .I2(\u11/wp_reg_n_0_[0] ), + .O(empty_i_2__7_n_0)); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT2 #( + .INIT(4'h8)) + en_out_l2_i_1 + (.I0(valid_s), + .I1(out_slt0[12]), + .O(\u14/u0/en_out_l20 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT2 #( + .INIT(4'h8)) + en_out_l2_i_1__0 + (.I0(valid_s), + .I1(out_slt0[11]), + .O(\u14/u1/en_out_l20 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT2 #( + .INIT(4'h8)) + en_out_l2_i_1__1 + (.I0(valid_s), + .I1(out_slt0[9]), + .O(\u14/u2/en_out_l20 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h8)) + en_out_l2_i_1__2 + (.I0(valid_s), + .I1(out_slt0[8]), + .O(\u14/u3/en_out_l20 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'h8)) + en_out_l2_i_1__3 + (.I0(valid_s), + .I1(out_slt0[7]), + .O(\u14/u4/en_out_l20 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT2 #( + .INIT(4'h8)) + en_out_l2_i_1__4 + (.I0(valid_s), + .I1(out_slt0[6]), + .O(\u14/u5/en_out_l20 )); + (* SOFT_HLUTNM = "soft_lutpair138" *) + LUT2 #( + .INIT(4'h8)) + en_out_l2_i_1__5 + (.I0(\u14/u6/en_out_l_reg_n_0 ), + .I1(in_valid_s[0]), + .O(\u14/u6/en_out_l20 )); + (* SOFT_HLUTNM = "soft_lutpair139" *) + LUT2 #( + .INIT(4'h8)) + en_out_l2_i_1__6 + (.I0(\u14/u7/en_out_l_reg_n_0 ), + .I1(in_valid_s[1]), + .O(\u14/u7/en_out_l20 )); + (* SOFT_HLUTNM = "soft_lutpair140" *) + LUT2 #( + .INIT(4'h8)) + en_out_l2_i_1__7 + (.I0(\u14/u8/en_out_l_reg_n_0 ), + .I1(in_valid_s[2]), + .O(\u14/u8/en_out_l20 )); + LUT4 #( + .INIT(16'hDC40)) + en_out_l_i_1 + (.I0(en_out_l_i_2__4_n_0), + .I1(valid_s), + .I2(in_slt0[15]), + .I3(out_slt0[6]), + .O(en_out_l_i_1_n_0)); + LUT4 #( + .INIT(16'hDC40)) + en_out_l_i_1__0 + (.I0(en_out_l_i_2__3_n_0), + .I1(valid_s), + .I2(in_slt0[15]), + .I3(out_slt0[7]), + .O(en_out_l_i_1__0_n_0)); + LUT4 #( + .INIT(16'hDC40)) + en_out_l_i_1__1 + (.I0(en_out_l_i_2__2_n_0), + .I1(valid_s), + .I2(in_slt0[15]), + .I3(out_slt0[8]), + .O(en_out_l_i_1__1_n_0)); + LUT4 #( + .INIT(16'hDC40)) + en_out_l_i_1__2 + (.I0(en_out_l_i_2__1_n_0), + .I1(valid_s), + .I2(in_slt0[15]), + .I3(out_slt0[9]), + .O(en_out_l_i_1__2_n_0)); + LUT4 #( + .INIT(16'hDC40)) + en_out_l_i_1__3 + (.I0(en_out_l_i_2__0_n_0), + .I1(valid_s), + .I2(in_slt0[15]), + .I3(out_slt0[11]), + .O(en_out_l_i_1__3_n_0)); + LUT4 #( + .INIT(16'hDC40)) + en_out_l_i_1__4 + (.I0(en_out_l_i_2_n_0), + .I1(valid_s), + .I2(in_slt0[15]), + .I3(out_slt0[12]), + .O(en_out_l_i_1__4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair138" *) + LUT3 #( + .INIT(8'hD4)) + en_out_l_i_1__5 + (.I0(en_out_l_i_2__5_n_0), + .I1(in_valid_s[0]), + .I2(\u14/u6/en_out_l_reg_n_0 ), + .O(en_out_l_i_1__5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair139" *) + LUT3 #( + .INIT(8'hD4)) + en_out_l_i_1__6 + (.I0(en_out_l_i_2__6_n_0), + .I1(in_valid_s[1]), + .I2(\u14/u7/en_out_l_reg_n_0 ), + .O(en_out_l_i_1__6_n_0)); + (* SOFT_HLUTNM = "soft_lutpair140" *) + LUT3 #( + .INIT(8'hD4)) + en_out_l_i_1__7 + (.I0(en_out_l_i_2__7_n_0), + .I1(in_valid_s[2]), + .I2(\u14/u8/en_out_l_reg_n_0 ), + .O(en_out_l_i_1__7_n_0)); + LUT4 #( + .INIT(16'hFDDD)) + en_out_l_i_2 + (.I0(\u13/occ0_r_reg_n_0_[0] ), + .I1(\u14/u0/full_empty_r ), + .I2(\u13/occ0_r_reg_n_0_[1] ), + .I3(in_slt1[11]), + .O(en_out_l_i_2_n_0)); + LUT4 #( + .INIT(16'hFDDD)) + en_out_l_i_2__0 + (.I0(\u13/occ0_r_reg_n_0_[8] ), + .I1(\u14/u1/full_empty_r ), + .I2(\u13/occ0_r_reg_n_0_[9] ), + .I3(in_slt1[10]), + .O(en_out_l_i_2__0_n_0)); + LUT4 #( + .INIT(16'hFDDD)) + en_out_l_i_2__1 + (.I0(\u13/occ0_r_reg_n_0_[16] ), + .I1(\u14/u2/full_empty_r ), + .I2(\u13/occ0_r_reg_n_0_[17] ), + .I3(in_slt1[8]), + .O(en_out_l_i_2__1_n_0)); + LUT4 #( + .INIT(16'hFDDD)) + en_out_l_i_2__2 + (.I0(\u13/occ0_r_reg_n_0_[24] ), + .I1(\u14/u3/full_empty_r ), + .I2(\u13/occ0_r_reg_n_0_[25] ), + .I3(in_slt1[7]), + .O(en_out_l_i_2__2_n_0)); + LUT4 #( + .INIT(16'hFDDD)) + en_out_l_i_2__3 + (.I0(\u13/occ1_r_reg_n_0_[0] ), + .I1(\u14/u4/full_empty_r ), + .I2(\u13/occ1_r_reg_n_0_[1] ), + .I3(in_slt1[6]), + .O(en_out_l_i_2__3_n_0)); + LUT4 #( + .INIT(16'hFDDD)) + en_out_l_i_2__4 + (.I0(\u13/occ1_r_reg_n_0_[8] ), + .I1(\u14/u5/full_empty_r ), + .I2(\u13/occ1_r_reg_n_0_[9] ), + .I3(in_slt1[5]), + .O(en_out_l_i_2__4_n_0)); + LUT5 #( + .INIT(32'hF4FFFFFF)) + en_out_l_i_2__5 + (.I0(in_slt0[12]), + .I1(\u13/icc_r_reg_n_0_[1] ), + .I2(\u14/u6/full_empty_r ), + .I3(\u13/icc_r_reg_n_0_[0] ), + .I4(in_slt0[15]), + .O(en_out_l_i_2__5_n_0)); + LUT5 #( + .INIT(32'hF4FFFFFF)) + en_out_l_i_2__6 + (.I0(in_slt0[11]), + .I1(\u13/icc_r_reg_n_0_[9] ), + .I2(\u14/u7/full_empty_r ), + .I3(\u13/icc_r_reg_n_0_[8] ), + .I4(in_slt0[15]), + .O(en_out_l_i_2__6_n_0)); + LUT5 #( + .INIT(32'hF4FFFFFF)) + en_out_l_i_2__7 + (.I0(in_slt0[9]), + .I1(\u13/icc_r_reg_n_0_[17] ), + .I2(\u14/u8/full_empty_r ), + .I3(\u13/icc_r_reg_n_0_[16] ), + .I4(in_slt0[15]), + .O(en_out_l_i_2__7_n_0)); + LUT1 #( + .INIT(2'h1)) + full_empty_r_i_1 + (.I0(valid_s), + .O(\u14/p_0_in )); + LUT3 #( + .INIT(8'hB8)) + full_empty_r_i_1__0 + (.I0(\u14/u6/full_empty_r ), + .I1(in_valid_s[0]), + .I2(i3_full), + .O(full_empty_r_i_1__0_n_0)); + LUT3 #( + .INIT(8'hB8)) + full_empty_r_i_1__1 + (.I0(\u14/u7/full_empty_r ), + .I1(in_valid_s[1]), + .I2(i4_full), + .O(full_empty_r_i_1__1_n_0)); + LUT3 #( + .INIT(8'hB8)) + full_empty_r_i_1__2 + (.I0(\u14/u8/full_empty_r ), + .I1(in_valid_s[2]), + .I2(i6_full), + .O(full_empty_r_i_1__2_n_0)); + LUT6 #( + .INIT(64'h6006000000006006)) + full_i_1 + (.I0(\u9/rp_reg_n_0_[2] ), + .I1(\u9/wp_reg_n_0_[3] ), + .I2(\u9/rp_reg_n_0_[1] ), + .I3(\u9/p_1_in [1]), + .I4(\u9/p_1_in [0]), + .I5(\u9/rp_reg_n_0_[0] ), + .O(\u9/full0 )); + LUT6 #( + .INIT(64'h6006000000006006)) + full_i_1__0 + (.I0(\u10/rp_reg_n_0_[2] ), + .I1(\u10/wp_reg_n_0_[3] ), + .I2(\u10/rp_reg_n_0_[1] ), + .I3(\u10/p_1_in [1]), + .I4(\u10/p_1_in [0]), + .I5(\u10/rp_reg_n_0_[0] ), + .O(\u10/full0 )); + LUT6 #( + .INIT(64'h6006000000006006)) + full_i_1__1 + (.I0(\u11/rp_reg_n_0_[2] ), + .I1(\u11/wp_reg_n_0_[3] ), + .I2(\u11/rp_reg_n_0_[1] ), + .I3(\u11/p_1_in [1]), + .I4(\u11/p_1_in [0]), + .I5(\u11/rp_reg_n_0_[0] ), + .O(\u11/full0 )); + LUT6 #( + .INIT(64'h0000000010000000)) + i3_re_i_1 + (.I0(wb_addr_i[2]), + .I1(wb_addr_i[6]), + .I2(wb_addr_i[5]), + .I3(wb_addr_i[3]), + .I4(wb_addr_i[4]), + .I5(wb_ack_o_i_3_n_0), + .O(\u12/i3_re0 )); + LUT6 #( + .INIT(64'h0000000040000000)) + i4_re_i_1 + (.I0(wb_addr_i[6]), + .I1(wb_addr_i[5]), + .I2(wb_addr_i[2]), + .I3(wb_addr_i[3]), + .I4(wb_addr_i[4]), + .I5(wb_ack_o_i_3_n_0), + .O(\u12/i4_re0 )); + LUT6 #( + .INIT(64'h0008000000000000)) + i6_re_i_1 + (.I0(\wb_data_o[31]_i_3_n_0 ), + .I1(\u12/re1 ), + .I2(wb_we_i), + .I3(\u12/re2 ), + .I4(wb_stb_i), + .I5(wb_cyc_i), + .O(\u12/i6_re0 )); + LUT4 #( + .INIT(16'h0800)) + \icc_r[23]_i_1 + (.I0(wb_addr_i[2]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rf_we), + .O(\u13/icc_r0 )); + LUT6 #( + .INIT(64'hFEEEAAAAEEEEAAAA)) + \in_valid[0]_i_1 + (.I0(\u2/cnt_reg [7]), + .I1(\out_le[3]_i_2_n_0 ), + .I2(\u2/cnt_reg [1]), + .I3(\u2/cnt_reg [3]), + .I4(\u2/cnt_reg [6]), + .I5(\u2/cnt_reg [2]), + .O(\u2/p_0_in )); + LUT6 #( + .INIT(64'hFFFEAAAAAAAAAAAA)) + \in_valid[1]_i_1 + (.I0(\u2/cnt_reg [7]), + .I1(\u2/cnt_reg [4]), + .I2(\out_le[2]_i_2_n_0 ), + .I3(\u2/cnt_reg [3]), + .I4(\u2/cnt_reg [6]), + .I5(\u2/cnt_reg [5]), + .O(\in_valid[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFF00FF00FF00E000)) + \in_valid[2]_i_1 + (.I0(\u2/cnt_reg [1]), + .I1(\u2/cnt_reg [2]), + .I2(\u2/cnt_reg [3]), + .I3(\u2/cnt_reg [7]), + .I4(\out_le[3]_i_2_n_0 ), + .I5(\u2/cnt_reg [6]), + .O(\in_valid[2]_i_1_n_0 )); + FDRE \in_valid_s1_reg[0] + (.C(clk_i), + .CE(\ ), + .D(in_valid[0]), + .Q(in_valid_s1[0]), + .R(\ )); + FDRE \in_valid_s1_reg[1] + (.C(clk_i), + .CE(\ ), + .D(in_valid[1]), + .Q(in_valid_s1[1]), + .R(\ )); + FDRE \in_valid_s1_reg[2] + (.C(clk_i), + .CE(\ ), + .D(in_valid[2]), + .Q(in_valid_s1[2]), + .R(\ )); + FDRE \in_valid_s_reg[0] + (.C(clk_i), + .CE(\ ), + .D(in_valid_s1[0]), + .Q(in_valid_s[0]), + .R(\ )); + FDRE \in_valid_s_reg[1] + (.C(clk_i), + .CE(\ ), + .D(in_valid_s1[1]), + .Q(in_valid_s[1]), + .R(\ )); + FDRE \in_valid_s_reg[2] + (.C(clk_i), + .CE(\ ), + .D(in_valid_s1[2]), + .Q(in_valid_s[2]), + .R(\ )); + LUT3 #( + .INIT(8'hFE)) + int_i_1 + (.I0(int_i_2_n_0), + .I1(int_i_3_n_0), + .I2(int_i_4_n_0), + .O(int_i_1_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + int_i_10 + (.I0(\u13/intm [16]), + .I1(\u13/ints [16]), + .I2(\u13/intm [15]), + .I3(\u13/ints [15]), + .I4(\u13/ints [14]), + .I5(\u13/intm [14]), + .O(int_i_10_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + int_i_11 + (.I0(\u13/intm [10]), + .I1(\u13/ints [10]), + .I2(\u13/intm [9]), + .I3(\u13/ints [9]), + .I4(\u13/ints [8]), + .I5(\u13/intm [8]), + .O(int_i_11_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + int_i_12 + (.I0(\u13/intm [7]), + .I1(\u13/ints [7]), + .I2(\u13/intm [6]), + .I3(\u13/ints [6]), + .I4(\u13/ints [5]), + .I5(\u13/intm [5]), + .O(int_i_12_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + int_i_2 + (.I0(\u13/intm [4]), + .I1(\u13/ints [4]), + .I2(\u13/intm [3]), + .I3(\u13/ints [3]), + .I4(\u13/ints [2]), + .I5(\u13/intm [2]), + .O(int_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + int_i_3 + (.I0(\u13/intm [1]), + .I1(\u13/ints [1]), + .I2(\u13/intm [0]), + .I3(\u13/ints [0]), + .I4(int_i_5_n_0), + .I5(int_i_6_n_0), + .O(int_i_3_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + int_i_4 + (.I0(int_i_7_n_0), + .I1(int_i_8_n_0), + .I2(int_i_9_n_0), + .I3(int_i_10_n_0), + .I4(int_i_11_n_0), + .I5(int_i_12_n_0), + .O(int_i_4_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + int_i_5 + (.I0(\u13/intm [28]), + .I1(\u13/ints [28]), + .I2(\u13/intm [27]), + .I3(\u13/ints [27]), + .I4(\u13/ints [26]), + .I5(\u13/intm [26]), + .O(int_i_5_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + int_i_6 + (.I0(\u13/intm [25]), + .I1(\u13/ints [25]), + .I2(\u13/intm [24]), + .I3(\u13/ints [24]), + .I4(\u13/ints [23]), + .I5(\u13/intm [23]), + .O(int_i_6_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + int_i_7 + (.I0(\u13/intm [19]), + .I1(\u13/ints [19]), + .I2(\u13/intm [18]), + .I3(\u13/ints [18]), + .I4(\u13/ints [17]), + .I5(\u13/intm [17]), + .O(int_i_7_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + int_i_8 + (.I0(\u13/intm [22]), + .I1(\u13/ints [22]), + .I2(\u13/intm [21]), + .I3(\u13/ints [21]), + .I4(\u13/ints [20]), + .I5(\u13/intm [20]), + .O(int_i_8_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + int_i_9 + (.I0(\u13/intm [13]), + .I1(\u13/ints [13]), + .I2(\u13/intm [12]), + .I3(\u13/ints [12]), + .I4(\u13/ints [11]), + .I5(\u13/intm [11]), + .O(int_i_9_n_0)); + LUT6 #( + .INIT(64'hFFFF111700000000)) + \int_set[0]_i_1 + (.I0(o3_status[1]), + .I1(\u13/occ0_r_reg_n_0_[5] ), + .I2(o3_status[0]), + .I3(\u13/occ0_r_reg_n_0_[4] ), + .I4(o3_empty), + .I5(\u13/occ0_r_reg_n_0_[0] ), + .O(\int_set[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAABABFF00000000)) + \int_set[0]_i_1__0 + (.I0(o4_empty), + .I1(o4_status[0]), + .I2(\u13/occ0_r_reg_n_0_[12] ), + .I3(\u13/occ0_r_reg_n_0_[13] ), + .I4(o4_status[1]), + .I5(\u13/occ0_r_reg_n_0_[8] ), + .O(\int_set[0]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hAAABABFF00000000)) + \int_set[0]_i_1__1 + (.I0(o6_empty), + .I1(o6_status[0]), + .I2(\u13/occ0_r_reg_n_0_[20] ), + .I3(\u13/occ0_r_reg_n_0_[21] ), + .I4(o6_status[1]), + .I5(\u13/occ0_r_reg_n_0_[16] ), + .O(\int_set[0]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hAAABABFF00000000)) + \int_set[0]_i_1__2 + (.I0(o7_empty), + .I1(o7_status[0]), + .I2(\u13/occ0_r_reg_n_0_[28] ), + .I3(\u13/occ0_r_reg_n_0_[29] ), + .I4(o7_status[1]), + .I5(\u13/occ0_r_reg_n_0_[24] ), + .O(\int_set[0]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hAAABABFF00000000)) + \int_set[0]_i_1__3 + (.I0(o8_empty), + .I1(o8_status[0]), + .I2(\u13/occ1_r_reg_n_0_[4] ), + .I3(\u13/occ1_r_reg_n_0_[5] ), + .I4(o8_status[1]), + .I5(\u13/occ1_r_reg_n_0_[0] ), + .O(\int_set[0]_i_1__3_n_0 )); + LUT6 #( + .INIT(64'hAAABABFF00000000)) + \int_set[0]_i_1__4 + (.I0(o9_empty), + .I1(o9_status[0]), + .I2(\u13/occ1_r_reg_n_0_[12] ), + .I3(\u13/occ1_r_reg_n_0_[13] ), + .I4(o9_status[1]), + .I5(\u13/occ1_r_reg_n_0_[8] ), + .O(\int_set[0]_i_1__4_n_0 )); + LUT6 #( + .INIT(64'hAAABABFF00000000)) + \int_set[0]_i_1__5 + (.I0(i3_full), + .I1(i3_status[0]), + .I2(\u13/icc_r_reg_n_0_[4] ), + .I3(\u13/icc_r_reg_n_0_[5] ), + .I4(i3_status[1]), + .I5(\u13/icc_r_reg_n_0_[0] ), + .O(\int_set[0]_i_1__5_n_0 )); + LUT6 #( + .INIT(64'hAAABABFF00000000)) + \int_set[0]_i_1__6 + (.I0(i4_full), + .I1(i4_status[0]), + .I2(\u13/icc_r_reg_n_0_[12] ), + .I3(\u13/icc_r_reg_n_0_[13] ), + .I4(i4_status[1]), + .I5(\u13/icc_r_reg_n_0_[8] ), + .O(\int_set[0]_i_1__6_n_0 )); + LUT6 #( + .INIT(64'hAAABABFF00000000)) + \int_set[0]_i_1__7 + (.I0(i6_full), + .I1(i6_status[0]), + .I2(\u13/icc_r_reg_n_0_[20] ), + .I3(\u13/icc_r_reg_n_0_[21] ), + .I4(i6_status[1]), + .I5(\u13/icc_r_reg_n_0_[16] ), + .O(\int_set[0]_i_1__7_n_0 )); + LUT4 #( + .INIT(16'h2000)) + \int_set[1]_i_1 + (.I0(o3_empty), + .I1(\u14/u0/en_out_l2_reg_n_0 ), + .I2(out_slt0[12]), + .I3(valid_s), + .O(\u17/int_set_reg00_out )); + LUT4 #( + .INIT(16'h2000)) + \int_set[1]_i_1__0 + (.I0(o4_empty), + .I1(\u14/u1/en_out_l2_reg_n_0 ), + .I2(out_slt0[11]), + .I3(valid_s), + .O(\u18/int_set_reg00_out )); + LUT4 #( + .INIT(16'h2000)) + \int_set[1]_i_1__1 + (.I0(o6_empty), + .I1(\u14/u2/en_out_l2_reg_n_0 ), + .I2(out_slt0[9]), + .I3(valid_s), + .O(\u19/int_set_reg00_out )); + LUT4 #( + .INIT(16'h2000)) + \int_set[1]_i_1__2 + (.I0(o7_empty), + .I1(\u14/u3/en_out_l2_reg_n_0 ), + .I2(out_slt0[8]), + .I3(valid_s), + .O(\u20/int_set_reg00_out )); + LUT4 #( + .INIT(16'h2000)) + \int_set[1]_i_1__3 + (.I0(o8_empty), + .I1(\u14/u4/en_out_l2_reg_n_0 ), + .I2(out_slt0[7]), + .I3(valid_s), + .O(\u21/int_set_reg00_out )); + LUT4 #( + .INIT(16'h2000)) + \int_set[1]_i_1__4 + (.I0(o9_empty), + .I1(\u14/u5/en_out_l2_reg_n_0 ), + .I2(out_slt0[6]), + .I3(valid_s), + .O(\u22/int_set_reg00_out )); + LUT2 #( + .INIT(4'h8)) + \int_set[1]_i_1__5 + (.I0(i3_empty), + .I1(i3_re), + .O(\u23/int_set_reg00_out )); + LUT2 #( + .INIT(4'h8)) + \int_set[1]_i_1__6 + (.I0(i4_empty), + .I1(i4_re), + .O(\u24/int_set_reg00_out )); + LUT2 #( + .INIT(4'h8)) + \int_set[1]_i_1__7 + (.I0(i6_empty), + .I1(i6_re), + .O(\u25/int_set_reg00_out )); + LUT4 #( + .INIT(16'h4000)) + \int_set[2]_i_1 + (.I0(\u14/u6/en_out_l2_reg_n_0 ), + .I1(\u14/u6/en_out_l_reg_n_0 ), + .I2(in_valid_s[0]), + .I3(i3_full), + .O(\u23/int_set_reg0 )); + LUT4 #( + .INIT(16'h4000)) + \int_set[2]_i_1__0 + (.I0(\u14/u7/en_out_l2_reg_n_0 ), + .I1(\u14/u7/en_out_l_reg_n_0 ), + .I2(in_valid_s[1]), + .I3(i4_full), + .O(\u24/int_set_reg0 )); + LUT4 #( + .INIT(16'h4000)) + \int_set[2]_i_1__1 + (.I0(\u14/u8/en_out_l2_reg_n_0 ), + .I1(\u14/u8/en_out_l_reg_n_0 ), + .I2(in_valid_s[2]), + .I3(i6_full), + .O(\u25/int_set_reg0 )); + LUT6 #( + .INIT(64'h0090900000000000)) + \int_set[2]_i_1__2 + (.I0(\u3/wp_reg_n_0_[1] ), + .I1(\u3/p_0_in [1]), + .I2(o3_we), + .I3(\u3/p_1_in ), + .I4(\u3/rp_reg_n_0_[3] ), + .I5(\status[0]_i_1_n_0 ), + .O(\u17/int_set_reg0 )); + LUT6 #( + .INIT(64'h0090900000000000)) + \int_set[2]_i_1__3 + (.I0(\u4/wp_reg_n_0_[1] ), + .I1(\u4/p_0_in [1]), + .I2(o4_we), + .I3(\u4/p_1_in ), + .I4(\u4/rp_reg_n_0_[3] ), + .I5(\status[0]_i_1__0_n_0 ), + .O(\u18/int_set_reg0 )); + LUT6 #( + .INIT(64'h0090900000000000)) + \int_set[2]_i_1__4 + (.I0(\u5/wp_reg_n_0_[1] ), + .I1(\u5/p_0_in [1]), + .I2(o6_we), + .I3(\u5/p_1_in ), + .I4(\u5/rp_reg_n_0_[3] ), + .I5(\status[0]_i_1__1_n_0 ), + .O(\u19/int_set_reg0 )); + LUT6 #( + .INIT(64'h0090900000000000)) + \int_set[2]_i_1__5 + (.I0(\u6/wp_reg_n_0_[1] ), + .I1(\u6/p_0_in [1]), + .I2(o7_we), + .I3(\u6/p_1_in ), + .I4(\u6/rp_reg_n_0_[3] ), + .I5(\status[0]_i_1__2_n_0 ), + .O(\u20/int_set_reg0 )); + LUT6 #( + .INIT(64'h0090900000000000)) + \int_set[2]_i_1__6 + (.I0(\u7/wp_reg_n_0_[1] ), + .I1(\u7/p_0_in [1]), + .I2(o8_we), + .I3(\u7/p_1_in ), + .I4(\u7/rp_reg_n_0_[3] ), + .I5(\status[0]_i_1__3_n_0 ), + .O(\u21/int_set_reg0 )); + LUT6 #( + .INIT(64'h0090900000000000)) + \int_set[2]_i_1__7 + (.I0(\u8/wp_reg_n_0_[1] ), + .I1(\u8/p_0_in [1]), + .I2(o9_we), + .I3(\u8/p_1_in ), + .I4(\u8/rp_reg_n_0_[3] ), + .I5(\status[0]_i_1__4_n_0 ), + .O(\u22/int_set_reg0 )); + LUT4 #( + .INIT(16'h0800)) + \intm_r[28]_i_1 + (.I0(wb_addr_i[2]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[3]), + .I3(rf_we), + .O(\u13/intm_r0 )); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[0]_i_1 + (.I0(crac_rd_done), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [0]), + .O(\ints_r[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[10]_i_1 + (.I0(oc2_int_set[2]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [10]), + .O(\ints_r[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[11]_i_1 + (.I0(oc3_int_set[0]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [11]), + .O(\ints_r[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[12]_i_1 + (.I0(oc3_int_set[1]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [12]), + .O(\ints_r[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[13]_i_1 + (.I0(oc3_int_set[2]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [13]), + .O(\ints_r[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[14]_i_1 + (.I0(oc4_int_set[0]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [14]), + .O(\ints_r[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[15]_i_1 + (.I0(oc4_int_set[1]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [15]), + .O(\ints_r[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[16]_i_1 + (.I0(oc4_int_set[2]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [16]), + .O(\ints_r[16]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[17]_i_1 + (.I0(oc5_int_set[0]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [17]), + .O(\ints_r[17]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[18]_i_1 + (.I0(oc5_int_set[1]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [18]), + .O(\ints_r[18]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[19]_i_1 + (.I0(oc5_int_set[2]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [19]), + .O(\ints_r[19]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFF000800)) + \ints_r[1]_i_1 + (.I0(crac_wr), + .I1(\u15/valid_r ), + .I2(valid_s), + .I3(\ints_r[28]_i_2_n_0 ), + .I4(\u13/ints [1]), + .O(\ints_r[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[20]_i_1 + (.I0(ic0_int_set[0]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [20]), + .O(\ints_r[20]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[21]_i_1 + (.I0(ic0_int_set[1]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [21]), + .O(\ints_r[21]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[22]_i_1 + (.I0(ic0_int_set[2]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [22]), + .O(\ints_r[22]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[23]_i_1 + (.I0(ic1_int_set[0]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [23]), + .O(\ints_r[23]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[24]_i_1 + (.I0(ic1_int_set[1]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [24]), + .O(\ints_r[24]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[25]_i_1 + (.I0(ic1_int_set[2]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [25]), + .O(\ints_r[25]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[26]_i_1 + (.I0(ic2_int_set[0]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [26]), + .O(\ints_r[26]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[27]_i_1 + (.I0(ic2_int_set[1]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [27]), + .O(\ints_r[27]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[28]_i_1 + (.I0(ic2_int_set[2]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [28]), + .O(\ints_r[28]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFEFFFFFF)) + \ints_r[28]_i_2 + (.I0(wb_addr_i[6]), + .I1(wb_addr_i[2]), + .I2(wb_addr_i[5]), + .I3(wb_addr_i[3]), + .I4(wb_addr_i[4]), + .I5(wb_ack_o_i_3_n_0), + .O(\ints_r[28]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[2]_i_1 + (.I0(oc0_int_set[0]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [2]), + .O(\ints_r[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[3]_i_1 + (.I0(oc0_int_set[1]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [3]), + .O(\ints_r[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[4]_i_1 + (.I0(oc0_int_set[2]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [4]), + .O(\ints_r[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[5]_i_1 + (.I0(oc1_int_set[0]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [5]), + .O(\ints_r[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[6]_i_1 + (.I0(oc1_int_set[1]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [6]), + .O(\ints_r[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[7]_i_1 + (.I0(oc1_int_set[2]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [7]), + .O(\ints_r[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[8]_i_1 + (.I0(oc2_int_set[0]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [8]), + .O(\ints_r[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT3 #( + .INIT(8'hC8)) + \ints_r[9]_i_1 + (.I0(oc2_int_set[1]), + .I1(\ints_r[28]_i_2_n_0 ), + .I2(\u13/ints [9]), + .O(\ints_r[9]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + ld_i_1 + (.I0(\u2/cnt_reg [6]), + .I1(\u2/cnt_reg [7]), + .I2(\u2/cnt_reg [5]), + .I3(\u2/cnt_reg [4]), + .I4(\u2/cnt_reg [0]), + .I5(\out_le[0]_i_2_n_0 ), + .O(ld_i_1_n_0)); + LUT6 #( + .INIT(64'h4040404040404000)) + mem_reg_0_3_0_5_i_1 + (.I0(\u14/u6/en_out_l2_reg_n_0 ), + .I1(\u14/u6/en_out_l_reg_n_0 ), + .I2(in_valid_s[0]), + .I3(\u9/wp_reg_n_0_[0] ), + .I4(i3_mode[0]), + .I5(i3_mode[1]), + .O(p_0_in__0)); + LUT6 #( + .INIT(64'h4040404040404000)) + mem_reg_0_3_0_5_i_1__0 + (.I0(\u14/u7/en_out_l2_reg_n_0 ), + .I1(\u14/u7/en_out_l_reg_n_0 ), + .I2(in_valid_s[1]), + .I3(\u10/wp_reg_n_0_[0] ), + .I4(i4_mode[0]), + .I5(i4_mode[1]), + .O(p_0_in__1)); + LUT6 #( + .INIT(64'h4040404040404000)) + mem_reg_0_3_0_5_i_1__1 + (.I0(\u14/u8/en_out_l2_reg_n_0 ), + .I1(\u14/u8/en_out_l_reg_n_0 ), + .I2(in_valid_s[2]), + .I3(\u11/wp_reg_n_0_[0] ), + .I4(i6_mode[0]), + .I5(i6_mode[1]), + .O(p_0_in__2)); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_2 + (.I0(\u9/din_tmp1 [1]), + .I1(i3_mode[0]), + .I2(in_slt3[3]), + .I3(i3_mode[1]), + .I4(in_slt3[1]), + .O(\u9/din_tmp [1])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_2__0 + (.I0(\u10/din_tmp1 [1]), + .I1(i4_mode[0]), + .I2(in_slt4[3]), + .I3(i4_mode[1]), + .I4(in_slt4[1]), + .O(\u10/din_tmp [1])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_2__1 + (.I0(\u11/din_tmp1 [1]), + .I1(i6_mode[0]), + .I2(in_slt6[3]), + .I3(i6_mode[1]), + .I4(in_slt6[1]), + .O(\u11/din_tmp [1])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_3 + (.I0(\u9/din_tmp1 [0]), + .I1(i3_mode[0]), + .I2(in_slt3[2]), + .I3(i3_mode[1]), + .I4(in_slt3[0]), + .O(\u9/din_tmp [0])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_3__0 + (.I0(\u10/din_tmp1 [0]), + .I1(i4_mode[0]), + .I2(in_slt4[2]), + .I3(i4_mode[1]), + .I4(in_slt4[0]), + .O(\u10/din_tmp [0])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_3__1 + (.I0(\u11/din_tmp1 [0]), + .I1(i6_mode[0]), + .I2(in_slt6[2]), + .I3(i6_mode[1]), + .I4(in_slt6[0]), + .O(\u11/din_tmp [0])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_4 + (.I0(\u9/din_tmp1 [3]), + .I1(i3_mode[0]), + .I2(in_slt3[5]), + .I3(i3_mode[1]), + .I4(in_slt3[3]), + .O(\u9/din_tmp [3])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_4__0 + (.I0(\u10/din_tmp1 [3]), + .I1(i4_mode[0]), + .I2(in_slt4[5]), + .I3(i4_mode[1]), + .I4(in_slt4[3]), + .O(\u10/din_tmp [3])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_4__1 + (.I0(\u11/din_tmp1 [3]), + .I1(i6_mode[0]), + .I2(in_slt6[5]), + .I3(i6_mode[1]), + .I4(in_slt6[3]), + .O(\u11/din_tmp [3])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_5 + (.I0(\u9/din_tmp1 [2]), + .I1(i3_mode[0]), + .I2(in_slt3[4]), + .I3(i3_mode[1]), + .I4(in_slt3[2]), + .O(\u9/din_tmp [2])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_5__0 + (.I0(\u10/din_tmp1 [2]), + .I1(i4_mode[0]), + .I2(in_slt4[4]), + .I3(i4_mode[1]), + .I4(in_slt4[2]), + .O(\u10/din_tmp [2])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_5__1 + (.I0(\u11/din_tmp1 [2]), + .I1(i6_mode[0]), + .I2(in_slt6[4]), + .I3(i6_mode[1]), + .I4(in_slt6[2]), + .O(\u11/din_tmp [2])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_6 + (.I0(\u9/din_tmp1 [5]), + .I1(i3_mode[0]), + .I2(in_slt3[7]), + .I3(i3_mode[1]), + .I4(in_slt3[5]), + .O(\u9/din_tmp [5])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_6__0 + (.I0(\u10/din_tmp1 [5]), + .I1(i4_mode[0]), + .I2(in_slt4[7]), + .I3(i4_mode[1]), + .I4(in_slt4[5]), + .O(\u10/din_tmp [5])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_6__1 + (.I0(\u11/din_tmp1 [5]), + .I1(i6_mode[0]), + .I2(in_slt6[7]), + .I3(i6_mode[1]), + .I4(in_slt6[5]), + .O(\u11/din_tmp [5])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_7 + (.I0(\u9/din_tmp1 [4]), + .I1(i3_mode[0]), + .I2(in_slt3[6]), + .I3(i3_mode[1]), + .I4(in_slt3[4]), + .O(\u9/din_tmp [4])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_7__0 + (.I0(\u10/din_tmp1 [4]), + .I1(i4_mode[0]), + .I2(in_slt4[6]), + .I3(i4_mode[1]), + .I4(in_slt4[4]), + .O(\u10/din_tmp [4])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_0_5_i_7__1 + (.I0(\u11/din_tmp1 [4]), + .I1(i6_mode[0]), + .I2(in_slt6[6]), + .I3(i6_mode[1]), + .I4(in_slt6[4]), + .O(\u11/din_tmp [4])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_1 + (.I0(\u9/din_tmp1 [13]), + .I1(i3_mode[0]), + .I2(in_slt3[15]), + .I3(i3_mode[1]), + .I4(in_slt3[13]), + .O(\u9/din_tmp [13])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_1__0 + (.I0(\u10/din_tmp1 [13]), + .I1(i4_mode[0]), + .I2(in_slt4[15]), + .I3(i4_mode[1]), + .I4(in_slt4[13]), + .O(\u10/din_tmp [13])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_1__1 + (.I0(\u11/din_tmp1 [13]), + .I1(i6_mode[0]), + .I2(in_slt6[15]), + .I3(i6_mode[1]), + .I4(in_slt6[13]), + .O(\u11/din_tmp [13])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_2 + (.I0(\u9/din_tmp1 [12]), + .I1(i3_mode[0]), + .I2(in_slt3[14]), + .I3(i3_mode[1]), + .I4(in_slt3[12]), + .O(\u9/din_tmp [12])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_2__0 + (.I0(\u10/din_tmp1 [12]), + .I1(i4_mode[0]), + .I2(in_slt4[14]), + .I3(i4_mode[1]), + .I4(in_slt4[12]), + .O(\u10/din_tmp [12])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_2__1 + (.I0(\u11/din_tmp1 [12]), + .I1(i6_mode[0]), + .I2(in_slt6[14]), + .I3(i6_mode[1]), + .I4(in_slt6[12]), + .O(\u11/din_tmp [12])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_3 + (.I0(\u9/din_tmp1 [15]), + .I1(i3_mode[0]), + .I2(in_slt3[17]), + .I3(i3_mode[1]), + .I4(in_slt3[15]), + .O(\u9/din_tmp [15])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_3__0 + (.I0(\u10/din_tmp1 [15]), + .I1(i4_mode[0]), + .I2(in_slt4[17]), + .I3(i4_mode[1]), + .I4(in_slt4[15]), + .O(\u10/din_tmp [15])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_3__1 + (.I0(\u11/din_tmp1 [15]), + .I1(i6_mode[0]), + .I2(in_slt6[17]), + .I3(i6_mode[1]), + .I4(in_slt6[15]), + .O(\u11/din_tmp [15])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_4 + (.I0(\u9/din_tmp1 [14]), + .I1(i3_mode[0]), + .I2(in_slt3[16]), + .I3(i3_mode[1]), + .I4(in_slt3[14]), + .O(\u9/din_tmp [14])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_4__0 + (.I0(\u10/din_tmp1 [14]), + .I1(i4_mode[0]), + .I2(in_slt4[16]), + .I3(i4_mode[1]), + .I4(in_slt4[14]), + .O(\u10/din_tmp [14])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_4__1 + (.I0(\u11/din_tmp1 [14]), + .I1(i6_mode[0]), + .I2(in_slt6[16]), + .I3(i6_mode[1]), + .I4(in_slt6[14]), + .O(\u11/din_tmp [14])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_5 + (.I0(in_slt3[5]), + .I1(i3_mode[0]), + .I2(in_slt3[19]), + .I3(i3_mode[1]), + .I4(in_slt3[17]), + .O(\u9/din_tmp [17])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_5__0 + (.I0(in_slt4[5]), + .I1(i4_mode[0]), + .I2(in_slt4[19]), + .I3(i4_mode[1]), + .I4(in_slt4[17]), + .O(\u10/din_tmp [17])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_5__1 + (.I0(in_slt6[5]), + .I1(i6_mode[0]), + .I2(in_slt6[19]), + .I3(i6_mode[1]), + .I4(in_slt6[17]), + .O(\u11/din_tmp [17])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_6 + (.I0(in_slt3[4]), + .I1(i3_mode[0]), + .I2(in_slt3[18]), + .I3(i3_mode[1]), + .I4(in_slt3[16]), + .O(\u9/din_tmp [16])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_6__0 + (.I0(in_slt4[4]), + .I1(i4_mode[0]), + .I2(in_slt4[18]), + .I3(i4_mode[1]), + .I4(in_slt4[16]), + .O(\u10/din_tmp [16])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_12_17_i_6__1 + (.I0(in_slt6[4]), + .I1(i6_mode[0]), + .I2(in_slt6[18]), + .I3(i6_mode[1]), + .I4(in_slt6[16]), + .O(\u11/din_tmp [16])); + LUT4 #( + .INIT(16'h2320)) + mem_reg_0_3_18_23_i_1 + (.I0(in_slt3[19]), + .I1(i3_mode[0]), + .I2(i3_mode[1]), + .I3(in_slt3[7]), + .O(\u9/din_tmp [19])); + LUT4 #( + .INIT(16'h2320)) + mem_reg_0_3_18_23_i_1__0 + (.I0(in_slt4[19]), + .I1(i4_mode[0]), + .I2(i4_mode[1]), + .I3(in_slt4[7]), + .O(\u10/din_tmp [19])); + LUT4 #( + .INIT(16'h2320)) + mem_reg_0_3_18_23_i_1__1 + (.I0(in_slt6[19]), + .I1(i6_mode[0]), + .I2(i6_mode[1]), + .I3(in_slt6[7]), + .O(\u11/din_tmp [19])); + LUT4 #( + .INIT(16'h2320)) + mem_reg_0_3_18_23_i_2 + (.I0(in_slt3[18]), + .I1(i3_mode[0]), + .I2(i3_mode[1]), + .I3(in_slt3[6]), + .O(\u9/din_tmp [18])); + LUT4 #( + .INIT(16'h2320)) + mem_reg_0_3_18_23_i_2__0 + (.I0(in_slt4[18]), + .I1(i4_mode[0]), + .I2(i4_mode[1]), + .I3(in_slt4[6]), + .O(\u10/din_tmp [18])); + LUT4 #( + .INIT(16'h2320)) + mem_reg_0_3_18_23_i_2__1 + (.I0(in_slt6[18]), + .I1(i6_mode[0]), + .I2(i6_mode[1]), + .I3(in_slt6[6]), + .O(\u11/din_tmp [18])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_3 + (.I0(in_slt3[9]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [21])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_3__0 + (.I0(in_slt4[9]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [21])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_3__1 + (.I0(in_slt6[9]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [21])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_4 + (.I0(in_slt3[8]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [20])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_4__0 + (.I0(in_slt4[8]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [20])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_4__1 + (.I0(in_slt6[8]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [20])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_5 + (.I0(in_slt3[11]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [23])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_5__0 + (.I0(in_slt4[11]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [23])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_5__1 + (.I0(in_slt6[11]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [23])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_6 + (.I0(in_slt3[10]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [22])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_6__0 + (.I0(in_slt4[10]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [22])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_18_23_i_6__1 + (.I0(in_slt6[10]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [22])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_1 + (.I0(in_slt3[13]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [25])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_1__0 + (.I0(in_slt4[13]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [25])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_1__1 + (.I0(in_slt6[13]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [25])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_2 + (.I0(in_slt3[12]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [24])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_2__0 + (.I0(in_slt4[12]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [24])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_2__1 + (.I0(in_slt6[12]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [24])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_3 + (.I0(in_slt3[15]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [27])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_3__0 + (.I0(in_slt4[15]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [27])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_3__1 + (.I0(in_slt6[15]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [27])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_4 + (.I0(in_slt3[14]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [26])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_4__0 + (.I0(in_slt4[14]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [26])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_4__1 + (.I0(in_slt6[14]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [26])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_5 + (.I0(in_slt3[17]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [29])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_5__0 + (.I0(in_slt4[17]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [29])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_5__1 + (.I0(in_slt6[17]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [29])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_6 + (.I0(in_slt3[16]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [28])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_6__0 + (.I0(in_slt4[16]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [28])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_24_29_i_6__1 + (.I0(in_slt6[16]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [28])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_30_31__0_i_1 + (.I0(in_slt3[19]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [31])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_30_31__0_i_1__0 + (.I0(in_slt4[19]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [31])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_30_31_i_1 + (.I0(in_slt3[18]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\u9/din_tmp [30])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_30_31_i_1__0 + (.I0(in_slt4[18]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\u10/din_tmp [30])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_30_31_i_1__1 + (.I0(in_slt6[19]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [31])); + LUT3 #( + .INIT(8'h02)) + mem_reg_0_3_30_31_i_1__2 + (.I0(in_slt6[18]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\u11/din_tmp [30])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_1 + (.I0(\u9/din_tmp1 [7]), + .I1(i3_mode[0]), + .I2(in_slt3[9]), + .I3(i3_mode[1]), + .I4(in_slt3[7]), + .O(\u9/din_tmp [7])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_1__0 + (.I0(\u10/din_tmp1 [7]), + .I1(i4_mode[0]), + .I2(in_slt4[9]), + .I3(i4_mode[1]), + .I4(in_slt4[7]), + .O(\u10/din_tmp [7])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_1__1 + (.I0(\u11/din_tmp1 [7]), + .I1(i6_mode[0]), + .I2(in_slt6[9]), + .I3(i6_mode[1]), + .I4(in_slt6[7]), + .O(\u11/din_tmp [7])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_2 + (.I0(\u9/din_tmp1 [6]), + .I1(i3_mode[0]), + .I2(in_slt3[8]), + .I3(i3_mode[1]), + .I4(in_slt3[6]), + .O(\u9/din_tmp [6])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_2__0 + (.I0(\u10/din_tmp1 [6]), + .I1(i4_mode[0]), + .I2(in_slt4[8]), + .I3(i4_mode[1]), + .I4(in_slt4[6]), + .O(\u10/din_tmp [6])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_2__1 + (.I0(\u11/din_tmp1 [6]), + .I1(i6_mode[0]), + .I2(in_slt6[8]), + .I3(i6_mode[1]), + .I4(in_slt6[6]), + .O(\u11/din_tmp [6])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_3 + (.I0(\u9/din_tmp1 [9]), + .I1(i3_mode[0]), + .I2(in_slt3[11]), + .I3(i3_mode[1]), + .I4(in_slt3[9]), + .O(\u9/din_tmp [9])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_3__0 + (.I0(\u10/din_tmp1 [9]), + .I1(i4_mode[0]), + .I2(in_slt4[11]), + .I3(i4_mode[1]), + .I4(in_slt4[9]), + .O(\u10/din_tmp [9])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_3__1 + (.I0(\u11/din_tmp1 [9]), + .I1(i6_mode[0]), + .I2(in_slt6[11]), + .I3(i6_mode[1]), + .I4(in_slt6[9]), + .O(\u11/din_tmp [9])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_4 + (.I0(\u9/din_tmp1 [8]), + .I1(i3_mode[0]), + .I2(in_slt3[10]), + .I3(i3_mode[1]), + .I4(in_slt3[8]), + .O(\u9/din_tmp [8])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_4__0 + (.I0(\u10/din_tmp1 [8]), + .I1(i4_mode[0]), + .I2(in_slt4[10]), + .I3(i4_mode[1]), + .I4(in_slt4[8]), + .O(\u10/din_tmp [8])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_4__1 + (.I0(\u11/din_tmp1 [8]), + .I1(i6_mode[0]), + .I2(in_slt6[10]), + .I3(i6_mode[1]), + .I4(in_slt6[8]), + .O(\u11/din_tmp [8])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_5 + (.I0(\u9/din_tmp1 [11]), + .I1(i3_mode[0]), + .I2(in_slt3[13]), + .I3(i3_mode[1]), + .I4(in_slt3[11]), + .O(\u9/din_tmp [11])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_5__0 + (.I0(\u10/din_tmp1 [11]), + .I1(i4_mode[0]), + .I2(in_slt4[13]), + .I3(i4_mode[1]), + .I4(in_slt4[11]), + .O(\u10/din_tmp [11])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_5__1 + (.I0(\u11/din_tmp1 [11]), + .I1(i6_mode[0]), + .I2(in_slt6[13]), + .I3(i6_mode[1]), + .I4(in_slt6[11]), + .O(\u11/din_tmp [11])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_6 + (.I0(\u9/din_tmp1 [10]), + .I1(i3_mode[0]), + .I2(in_slt3[12]), + .I3(i3_mode[1]), + .I4(in_slt3[10]), + .O(\u9/din_tmp [10])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_6__0 + (.I0(\u10/din_tmp1 [10]), + .I1(i4_mode[0]), + .I2(in_slt4[12]), + .I3(i4_mode[1]), + .I4(in_slt4[10]), + .O(\u10/din_tmp [10])); + LUT5 #( + .INIT(32'hFFE200E2)) + mem_reg_0_3_6_11_i_6__1 + (.I0(\u11/din_tmp1 [10]), + .I1(i6_mode[0]), + .I2(in_slt6[12]), + .I3(i6_mode[1]), + .I4(in_slt6[10]), + .O(\u11/din_tmp [10])); + LUT6 #( + .INIT(64'hEFFFFFFFFFFFFFFF)) + o3_we_i_1 + (.I0(o3_we_i_3_n_0), + .I1(\u12/we2 ), + .I2(\u12/we1 ), + .I3(wb_we_i), + .I4(wb_stb_i), + .I5(wb_cyc_i), + .O(o3_we_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair137" *) + LUT3 #( + .INIT(8'h01)) + o3_we_i_2 + (.I0(wb_addr_i[4]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[2]), + .O(o3_we_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'hB)) + o3_we_i_3 + (.I0(wb_addr_i[6]), + .I1(wb_addr_i[5]), + .O(o3_we_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h10)) + o4_we_i_1 + (.I0(wb_addr_i[4]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[2]), + .O(o4_we_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'h04)) + o6_we_i_1 + (.I0(wb_addr_i[4]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[2]), + .O(o6_we_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'h40)) + o7_we_i_1 + (.I0(wb_addr_i[4]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[2]), + .O(o7_we_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair137" *) + LUT3 #( + .INIT(8'h04)) + o8_we_i_1 + (.I0(wb_addr_i[3]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[2]), + .O(o8_we_i_1_n_0)); + LUT3 #( + .INIT(8'h40)) + o9_we_i_1 + (.I0(wb_addr_i[3]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[2]), + .O(o9_we_i_1_n_0)); + LUT4 #( + .INIT(16'h0200)) + \occ0_r[31]_i_1 + (.I0(wb_addr_i[2]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rf_we), + .O(\u13/occ00 )); + LUT4 #( + .INIT(16'h0400)) + \occ1_r[15]_i_1 + (.I0(wb_addr_i[2]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rf_we), + .O(\u13/occ1_r0 )); + LUT6 #( + .INIT(64'h0000000001000000)) + \out_le[0]_i_1 + (.I0(\u2/cnt_reg [6]), + .I1(\u2/cnt_reg [7]), + .I2(\u2/cnt_reg [5]), + .I3(\u2/cnt_reg [4]), + .I4(\u2/cnt_reg [0]), + .I5(\out_le[0]_i_2_n_0 ), + .O(\out_le[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair218" *) + LUT3 #( + .INIT(8'hFE)) + \out_le[0]_i_2 + (.I0(\u2/cnt_reg [2]), + .I1(\u2/cnt_reg [1]), + .I2(\u2/cnt_reg [3]), + .O(\out_le[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000000000040)) + \out_le[1]_i_1 + (.I0(\out_le[1]_i_2_n_0 ), + .I1(\out_le[1]_i_3_n_0 ), + .I2(\u2/cnt_reg [5]), + .I3(\u2/cnt_reg [4]), + .I4(\u2/cnt_reg [1]), + .I5(\u2/cnt_reg [3]), + .O(\out_le[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT2 #( + .INIT(4'hE)) + \out_le[1]_i_2 + (.I0(\u2/cnt_reg [6]), + .I1(\u2/cnt_reg [7]), + .O(\out_le[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair219" *) + LUT2 #( + .INIT(4'h8)) + \out_le[1]_i_3 + (.I0(\u2/cnt_reg [0]), + .I1(\u2/cnt_reg [2]), + .O(\out_le[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h1000000000000000)) + \out_le[2]_i_1 + (.I0(\out_le[2]_i_2_n_0 ), + .I1(\out_le[1]_i_2_n_0 ), + .I2(\u2/cnt_reg [4]), + .I3(\u2/cnt_reg [5]), + .I4(\u2/cnt_reg [0]), + .I5(\u2/cnt_reg [3]), + .O(\out_le[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair218" *) + LUT2 #( + .INIT(4'hE)) + \out_le[2]_i_2 + (.I0(\u2/cnt_reg [1]), + .I1(\u2/cnt_reg [2]), + .O(\out_le[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000000400000)) + \out_le[3]_i_1 + (.I0(\out_le[3]_i_2_n_0 ), + .I1(\out_le[1]_i_3_n_0 ), + .I2(\u2/cnt_reg [6]), + .I3(\u2/cnt_reg [7]), + .I4(\u2/cnt_reg [3]), + .I5(\u2/cnt_reg [1]), + .O(\out_le[3]_i_1_n_0 )); + LUT2 #( + .INIT(4'hE)) + \out_le[3]_i_2 + (.I0(\u2/cnt_reg [4]), + .I1(\u2/cnt_reg [5]), + .O(\out_le[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000002000000)) + \out_le[4]_i_1 + (.I0(\u2/cnt_reg [6]), + .I1(\u2/cnt_reg [7]), + .I2(\u2/cnt_reg [4]), + .I3(\u2/cnt_reg [5]), + .I4(\u2/cnt_reg [0]), + .I5(\out_le[0]_i_2_n_0 ), + .O(\out_le[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000004000)) + \out_le[5]_i_1 + (.I0(\out_le[2]_i_2_n_0 ), + .I1(\u2/cnt_reg [7]), + .I2(\u2/cnt_reg [3]), + .I3(\u2/cnt_reg [0]), + .I4(\u2/cnt_reg [6]), + .I5(\out_le[3]_i_2_n_0 ), + .O(\out_le[5]_i_1_n_0 )); + LUT2 #( + .INIT(4'h1)) + \ps_cnt[0]_i_1 + (.I0(\u26/ps_cnt_reg [0]), + .I1(ac97_rst_force), + .O(\ps_cnt[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair141" *) + LUT3 #( + .INIT(8'h28)) + \ps_cnt[1]_i_1 + (.I0(\ps_cnt[4]_i_2_n_0 ), + .I1(\u26/ps_cnt_reg [1]), + .I2(\u26/ps_cnt_reg [0]), + .O(p_0_in__8[1])); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT4 #( + .INIT(16'h2888)) + \ps_cnt[2]_i_1 + (.I0(\ps_cnt[4]_i_2_n_0 ), + .I1(\u26/ps_cnt_reg [2]), + .I2(\u26/ps_cnt_reg [0]), + .I3(\u26/ps_cnt_reg [1]), + .O(p_0_in__8[2])); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT5 #( + .INIT(32'h28888888)) + \ps_cnt[3]_i_1 + (.I0(\ps_cnt[4]_i_2_n_0 ), + .I1(\u26/ps_cnt_reg [3]), + .I2(\u26/ps_cnt_reg [2]), + .I3(\u26/ps_cnt_reg [1]), + .I4(\u26/ps_cnt_reg [0]), + .O(p_0_in__8[3])); + LUT6 #( + .INIT(64'h2888888888888888)) + \ps_cnt[4]_i_1 + (.I0(\ps_cnt[4]_i_2_n_0 ), + .I1(\u26/ps_cnt_reg [4]), + .I2(\u26/ps_cnt_reg [1]), + .I3(\u26/ps_cnt_reg [0]), + .I4(\u26/ps_cnt_reg [3]), + .I5(\u26/ps_cnt_reg [2]), + .O(p_0_in__8[4])); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT2 #( + .INIT(4'h2)) + \ps_cnt[4]_i_2 + (.I0(\cnt[2]_i_2_n_0 ), + .I1(ac97_rst_force), + .O(\ps_cnt[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'h4444444414444440)) + \ps_cnt[5]_i_1 + (.I0(ac97_rst_force), + .I1(\u26/ps_cnt_reg [5]), + .I2(\u26/ps_cnt_reg [1]), + .I3(\u26/ps_cnt_reg [2]), + .I4(\u26/ps_cnt_reg [3]), + .I5(\ps_cnt[5]_i_2_n_0 ), + .O(p_0_in__8[5])); + (* SOFT_HLUTNM = "soft_lutpair141" *) + LUT2 #( + .INIT(4'h7)) + \ps_cnt[5]_i_2 + (.I0(\u26/ps_cnt_reg [0]), + .I1(\u26/ps_cnt_reg [4]), + .O(\ps_cnt[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF040)) + rdd1_i_1 + (.I0(valid_s), + .I1(\u15/valid_r ), + .I2(\u15/crac_rd ), + .I3(\u15/rdd1 ), + .O(rdd1_i_1_n_0)); + LUT6 #( + .INIT(64'h4040FF40FF40FF40)) + rdd2_i_1 + (.I0(valid_s), + .I1(\u15/valid_r ), + .I2(\u15/crac_rd ), + .I3(\u15/rdd2 ), + .I4(\u15/rdd3 ), + .I5(crac_rd_done), + .O(rdd2_i_1_n_0)); + LUT5 #( + .INIT(32'h08FF0808)) + rdd3_i_1 + (.I0(\u15/rdd2 ), + .I1(valid_s), + .I2(\u15/valid_r ), + .I3(crac_rd_done), + .I4(\u15/rdd3 ), + .O(rdd3_i_1_n_0)); + LUT4 #( + .INIT(16'h0001)) + re1_i_1 + (.I0(wb_addr_i[29]), + .I1(wb_addr_i[30]), + .I2(wb_addr_i[31]), + .I3(re1_i_2_n_0), + .O(\u12/re10 )); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT4 #( + .INIT(16'hEFFF)) + re1_i_2 + (.I0(wb_we_i), + .I1(\u12/re2 ), + .I2(wb_stb_i), + .I3(wb_cyc_i), + .O(re1_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT5 #( + .INIT(32'h02000000)) + re2_i_1 + (.I0(\u12/re1 ), + .I1(wb_we_i), + .I2(\u12/re2 ), + .I3(wb_stb_i), + .I4(wb_cyc_i), + .O(\u12/re20 )); + LUT1 #( + .INIT(2'h1)) + \res_cnt[0]_i_1 + (.I0(\u2/res_cnt_reg [0]), + .O(p_0_in__0__0[0])); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT2 #( + .INIT(4'h6)) + \res_cnt[1]_i_1 + (.I0(\u2/res_cnt_reg [0]), + .I1(\u2/res_cnt_reg [1]), + .O(p_0_in__0__0[1])); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT3 #( + .INIT(8'h78)) + \res_cnt[2]_i_1 + (.I0(\u2/res_cnt_reg [1]), + .I1(\u2/res_cnt_reg [0]), + .I2(\u2/res_cnt_reg [2]), + .O(p_0_in__0__0[2])); + LUT1 #( + .INIT(2'h1)) + \res_cnt[3]_i_1 + (.I0(\u2/sync_resume_reg_n_0 ), + .O(\u2/clear )); + LUT6 #( + .INIT(64'h0010000000000000)) + \res_cnt[3]_i_2 + (.I0(\u26/ps_cnt_reg [1]), + .I1(\u26/ps_cnt_reg [2]), + .I2(\u26/ps_cnt_reg [5]), + .I3(\u26/ps_cnt_reg [3]), + .I4(\u26/ps_cnt_reg [4]), + .I5(\u26/ps_cnt_reg [0]), + .O(ps_ce)); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT4 #( + .INIT(16'h7F80)) + \res_cnt[3]_i_3 + (.I0(\u2/res_cnt_reg [0]), + .I1(\u2/res_cnt_reg [2]), + .I2(\u2/res_cnt_reg [1]), + .I3(\u2/res_cnt_reg [3]), + .O(p_0_in__0__0[3])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT5 #( + .INIT(32'h00000008)) + resume_req_i_1 + (.I0(wb_din[1]), + .I1(rf_we), + .I2(wb_addr_i[2]), + .I3(wb_addr_i[3]), + .I4(wb_addr_i[4]), + .O(resume_req_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair136" *) + LUT3 #( + .INIT(8'h10)) + rf_we_i_1 + (.I0(wb_addr_i[6]), + .I1(wb_addr_i[5]), + .I2(wb_ack_o_i_2_n_0), + .O(\u12/rf_we0 )); + LUT3 #( + .INIT(8'h60)) + \rp[0]_i_1 + (.I0(\u9/rp_reg_n_0_[0] ), + .I1(i3_re), + .I2(\u13/icc_r_reg_n_0_[0] ), + .O(\rp[0]_i_1_n_0 )); + LUT3 #( + .INIT(8'h60)) + \rp[0]_i_1__0 + (.I0(\u10/rp_reg_n_0_[0] ), + .I1(i4_re), + .I2(\u13/icc_r_reg_n_0_[8] ), + .O(\rp[0]_i_1__0_n_0 )); + LUT3 #( + .INIT(8'h60)) + \rp[0]_i_1__1 + (.I0(\u11/rp_reg_n_0_[0] ), + .I1(i6_re), + .I2(\u13/icc_r_reg_n_0_[16] ), + .O(\rp[0]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair127" *) + LUT3 #( + .INIT(8'hE1)) + \rp[0]_i_1__2 + (.I0(o3_mode[0]), + .I1(o3_mode[1]), + .I2(\u3/rp_reg_n_0_[0] ), + .O(\rp[0]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair128" *) + LUT3 #( + .INIT(8'hE1)) + \rp[0]_i_1__3 + (.I0(o4_mode[0]), + .I1(o4_mode[1]), + .I2(\u4/rp_reg_n_0_[0] ), + .O(\rp[0]_i_1__3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair129" *) + LUT3 #( + .INIT(8'hE1)) + \rp[0]_i_1__4 + (.I0(o6_mode[0]), + .I1(o6_mode[1]), + .I2(\u5/rp_reg_n_0_[0] ), + .O(\rp[0]_i_1__4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair130" *) + LUT3 #( + .INIT(8'hE1)) + \rp[0]_i_1__5 + (.I0(o7_mode[0]), + .I1(o7_mode[1]), + .I2(\u6/rp_reg_n_0_[0] ), + .O(\rp[0]_i_1__5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair131" *) + LUT3 #( + .INIT(8'hE1)) + \rp[0]_i_1__6 + (.I0(o8_mode[0]), + .I1(o8_mode[1]), + .I2(\u7/rp_reg_n_0_[0] ), + .O(\rp[0]_i_1__6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair132" *) + LUT3 #( + .INIT(8'hE1)) + \rp[0]_i_1__7 + (.I0(o9_mode[0]), + .I1(o9_mode[1]), + .I2(\u8/rp_reg_n_0_[0] ), + .O(\rp[0]_i_1__7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h6A00)) + \rp[1]_i_1 + (.I0(\u9/rp_reg_n_0_[1] ), + .I1(i3_re), + .I2(\u9/rp_reg_n_0_[0] ), + .I3(\u13/icc_r_reg_n_0_[0] ), + .O(\rp[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'h6A00)) + \rp[1]_i_1__0 + (.I0(\u10/rp_reg_n_0_[1] ), + .I1(i4_re), + .I2(\u10/rp_reg_n_0_[0] ), + .I3(\u13/icc_r_reg_n_0_[8] ), + .O(\rp[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'h6A00)) + \rp[1]_i_1__1 + (.I0(\u11/rp_reg_n_0_[1] ), + .I1(i6_re), + .I2(\u11/rp_reg_n_0_[0] ), + .I3(\u13/icc_r_reg_n_0_[16] ), + .O(\rp[1]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair127" *) + LUT3 #( + .INIT(8'h1E)) + \rp[1]_i_1__2 + (.I0(\rp[3]_i_2_n_0 ), + .I1(\u3/rp_reg_n_0_[0] ), + .I2(\u3/p_0_in [0]), + .O(p_0_in__2__0[1])); + (* SOFT_HLUTNM = "soft_lutpair128" *) + LUT3 #( + .INIT(8'h1E)) + \rp[1]_i_1__3 + (.I0(\rp[3]_i_2__0_n_0 ), + .I1(\u4/rp_reg_n_0_[0] ), + .I2(\u4/p_0_in [0]), + .O(p_0_in__3__0[1])); + (* SOFT_HLUTNM = "soft_lutpair129" *) + LUT3 #( + .INIT(8'h1E)) + \rp[1]_i_1__4 + (.I0(\rp[3]_i_2__1_n_0 ), + .I1(\u5/rp_reg_n_0_[0] ), + .I2(\u5/p_0_in [0]), + .O(p_0_in__4[1])); + (* SOFT_HLUTNM = "soft_lutpair130" *) + LUT3 #( + .INIT(8'h1E)) + \rp[1]_i_1__5 + (.I0(\rp[3]_i_2__2_n_0 ), + .I1(\u6/rp_reg_n_0_[0] ), + .I2(\u6/p_0_in [0]), + .O(p_0_in__5[1])); + (* SOFT_HLUTNM = "soft_lutpair131" *) + LUT3 #( + .INIT(8'h1E)) + \rp[1]_i_1__6 + (.I0(\rp[3]_i_2__3_n_0 ), + .I1(\u7/rp_reg_n_0_[0] ), + .I2(\u7/p_0_in [0]), + .O(p_0_in__6[1])); + (* SOFT_HLUTNM = "soft_lutpair132" *) + LUT3 #( + .INIT(8'h1E)) + \rp[1]_i_1__7 + (.I0(\rp[3]_i_2__4_n_0 ), + .I1(\u8/rp_reg_n_0_[0] ), + .I2(\u8/p_0_in [0]), + .O(p_0_in__7[1])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h6AAA0000)) + \rp[2]_i_1 + (.I0(\u9/rp_reg_n_0_[2] ), + .I1(i3_re), + .I2(\u9/rp_reg_n_0_[0] ), + .I3(\u9/rp_reg_n_0_[1] ), + .I4(\u13/icc_r_reg_n_0_[0] ), + .O(\rp[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h6AAA0000)) + \rp[2]_i_1__0 + (.I0(\u10/rp_reg_n_0_[2] ), + .I1(i4_re), + .I2(\u10/rp_reg_n_0_[0] ), + .I3(\u10/rp_reg_n_0_[1] ), + .I4(\u13/icc_r_reg_n_0_[8] ), + .O(\rp[2]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h6AAA0000)) + \rp[2]_i_1__1 + (.I0(\u11/rp_reg_n_0_[2] ), + .I1(i6_re), + .I2(\u11/rp_reg_n_0_[0] ), + .I3(\u11/rp_reg_n_0_[1] ), + .I4(\u13/icc_r_reg_n_0_[16] ), + .O(\rp[2]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'h1FE0)) + \rp[2]_i_1__2 + (.I0(\rp[3]_i_2_n_0 ), + .I1(\u3/rp_reg_n_0_[0] ), + .I2(\u3/p_0_in [0]), + .I3(\u3/p_0_in [1]), + .O(p_0_in__2__0[2])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'h1FE0)) + \rp[2]_i_1__3 + (.I0(\rp[3]_i_2__0_n_0 ), + .I1(\u4/rp_reg_n_0_[0] ), + .I2(\u4/p_0_in [0]), + .I3(\u4/p_0_in [1]), + .O(p_0_in__3__0[2])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h37C8)) + \rp[2]_i_1__4 + (.I0(\rp[3]_i_2__1_n_0 ), + .I1(\u5/p_0_in [0]), + .I2(\u5/rp_reg_n_0_[0] ), + .I3(\u5/p_0_in [1]), + .O(p_0_in__4[2])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT4 #( + .INIT(16'h37C8)) + \rp[2]_i_1__5 + (.I0(\rp[3]_i_2__2_n_0 ), + .I1(\u6/p_0_in [0]), + .I2(\u6/rp_reg_n_0_[0] ), + .I3(\u6/p_0_in [1]), + .O(p_0_in__5[2])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT4 #( + .INIT(16'h37C8)) + \rp[2]_i_1__6 + (.I0(\rp[3]_i_2__3_n_0 ), + .I1(\u7/p_0_in [0]), + .I2(\u7/rp_reg_n_0_[0] ), + .I3(\u7/p_0_in [1]), + .O(p_0_in__6[2])); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT4 #( + .INIT(16'h37C8)) + \rp[2]_i_1__7 + (.I0(\rp[3]_i_2__4_n_0 ), + .I1(\u8/p_0_in [0]), + .I2(\u8/rp_reg_n_0_[0] ), + .I3(\u8/p_0_in [1]), + .O(p_0_in__7[2])); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT5 #( + .INIT(32'h1FFFE000)) + \rp[3]_i_1 + (.I0(\rp[3]_i_2_n_0 ), + .I1(\u3/rp_reg_n_0_[0] ), + .I2(\u3/p_0_in [0]), + .I3(\u3/p_0_in [1]), + .I4(\u3/rp_reg_n_0_[3] ), + .O(p_0_in__2__0[3])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT5 #( + .INIT(32'h1FFFE000)) + \rp[3]_i_1__0 + (.I0(\rp[3]_i_2__0_n_0 ), + .I1(\u4/rp_reg_n_0_[0] ), + .I2(\u4/p_0_in [0]), + .I3(\u4/p_0_in [1]), + .I4(\u4/rp_reg_n_0_[3] ), + .O(p_0_in__3__0[3])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT5 #( + .INIT(32'h1FFFE000)) + \rp[3]_i_1__1 + (.I0(\rp[3]_i_2__1_n_0 ), + .I1(\u5/rp_reg_n_0_[0] ), + .I2(\u5/p_0_in [0]), + .I3(\u5/p_0_in [1]), + .I4(\u5/rp_reg_n_0_[3] ), + .O(p_0_in__4[3])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT5 #( + .INIT(32'h1FFFE000)) + \rp[3]_i_1__2 + (.I0(\rp[3]_i_2__2_n_0 ), + .I1(\u6/rp_reg_n_0_[0] ), + .I2(\u6/p_0_in [0]), + .I3(\u6/p_0_in [1]), + .I4(\u6/rp_reg_n_0_[3] ), + .O(p_0_in__5[3])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT5 #( + .INIT(32'h1FFFE000)) + \rp[3]_i_1__3 + (.I0(\rp[3]_i_2__3_n_0 ), + .I1(\u7/rp_reg_n_0_[0] ), + .I2(\u7/p_0_in [0]), + .I3(\u7/p_0_in [1]), + .I4(\u7/rp_reg_n_0_[3] ), + .O(p_0_in__6[3])); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT5 #( + .INIT(32'h1FFFE000)) + \rp[3]_i_1__4 + (.I0(\rp[3]_i_2__4_n_0 ), + .I1(\u8/rp_reg_n_0_[0] ), + .I2(\u8/p_0_in [0]), + .I3(\u8/p_0_in [1]), + .I4(\u8/rp_reg_n_0_[3] ), + .O(p_0_in__7[3])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT5 #( + .INIT(32'hFFFFFFBF)) + \rp[3]_i_2 + (.I0(\u14/u0/en_out_l2_reg_n_0 ), + .I1(out_slt0[12]), + .I2(valid_s), + .I3(o3_mode[1]), + .I4(o3_mode[0]), + .O(\rp[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT5 #( + .INIT(32'hFFFFFFBF)) + \rp[3]_i_2__0 + (.I0(\u14/u1/en_out_l2_reg_n_0 ), + .I1(out_slt0[11]), + .I2(valid_s), + .I3(o4_mode[1]), + .I4(o4_mode[0]), + .O(\rp[3]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT5 #( + .INIT(32'hFFFFFFBF)) + \rp[3]_i_2__1 + (.I0(\u14/u2/en_out_l2_reg_n_0 ), + .I1(out_slt0[9]), + .I2(valid_s), + .I3(o6_mode[1]), + .I4(o6_mode[0]), + .O(\rp[3]_i_2__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT5 #( + .INIT(32'hFFFFFFBF)) + \rp[3]_i_2__2 + (.I0(\u14/u3/en_out_l2_reg_n_0 ), + .I1(out_slt0[8]), + .I2(valid_s), + .I3(o7_mode[1]), + .I4(o7_mode[0]), + .O(\rp[3]_i_2__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT5 #( + .INIT(32'hFFFFFFBF)) + \rp[3]_i_2__3 + (.I0(\u14/u4/en_out_l2_reg_n_0 ), + .I1(out_slt0[7]), + .I2(valid_s), + .I3(o8_mode[1]), + .I4(o8_mode[0]), + .O(\rp[3]_i_2__3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT5 #( + .INIT(32'hFFFFFFBF)) + \rp[3]_i_2__4 + (.I0(\u14/u5/en_out_l2_reg_n_0 ), + .I1(out_slt0[6]), + .I2(valid_s), + .I3(o9_mode[1]), + .I4(o9_mode[0]), + .O(\rp[3]_i_2__4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair215" *) + LUT3 #( + .INIT(8'hB8)) + \slt0_r[11]_i_1 + (.I0(out_slt0[11]), + .I1(ld), + .I2(\u0/slt0_r [10]), + .O(\slt0_r[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair215" *) + LUT3 #( + .INIT(8'hB8)) + \slt0_r[12]_i_1 + (.I0(out_slt0[12]), + .I1(ld), + .I2(\u0/slt0_r [11]), + .O(\slt0_r[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair214" *) + LUT3 #( + .INIT(8'hB8)) + \slt0_r[13]_i_1 + (.I0(out_slt0[13]), + .I1(ld), + .I2(\u0/slt0_r [12]), + .O(\slt0_r[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair214" *) + LUT3 #( + .INIT(8'hB8)) + \slt0_r[14]_i_1 + (.I0(out_slt0[14]), + .I1(ld), + .I2(\u0/slt0_r [13]), + .O(\slt0_r[14]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFAAFFFCFFAA)) + \slt0_r[15]_i_1 + (.I0(\u0/slt0_r [14]), + .I1(out_slt0[6]), + .I2(out_slt0[7]), + .I3(\slt0_r[15]_i_2_n_0 ), + .I4(ld), + .I5(out_slt0[8]), + .O(\slt0_r[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFF0000FFFE0000)) + \slt0_r[15]_i_2 + (.I0(out_slt0[9]), + .I1(out_slt0[13]), + .I2(out_slt0[14]), + .I3(out_slt0[12]), + .I4(ld), + .I5(out_slt0[11]), + .O(\slt0_r[15]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair217" *) + LUT3 #( + .INIT(8'hB8)) + \slt0_r[6]_i_1 + (.I0(out_slt0[6]), + .I1(ld), + .I2(\u0/slt0_r [5]), + .O(\slt0_r[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair217" *) + LUT3 #( + .INIT(8'hB8)) + \slt0_r[7]_i_1 + (.I0(out_slt0[7]), + .I1(ld), + .I2(\u0/slt0_r [6]), + .O(\slt0_r[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair216" *) + LUT3 #( + .INIT(8'hB8)) + \slt0_r[8]_i_1 + (.I0(out_slt0[8]), + .I1(ld), + .I2(\u0/slt0_r [7]), + .O(\slt0_r[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair216" *) + LUT3 #( + .INIT(8'hB8)) + \slt0_r[9]_i_1 + (.I0(out_slt0[9]), + .I1(ld), + .I2(\u0/slt0_r [8]), + .O(\slt0_r[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair213" *) + LUT3 #( + .INIT(8'hB8)) + \slt1_r[12]_i_1 + (.I0(crac_out[16]), + .I1(ld), + .I2(\u0/slt1_r [11]), + .O(\slt1_r[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair213" *) + LUT3 #( + .INIT(8'hB8)) + \slt1_r[13]_i_1 + (.I0(crac_out[17]), + .I1(ld), + .I2(\u0/slt1_r [12]), + .O(\slt1_r[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair212" *) + LUT3 #( + .INIT(8'hB8)) + \slt1_r[14]_i_1 + (.I0(crac_out[18]), + .I1(ld), + .I2(\u0/slt1_r [13]), + .O(\slt1_r[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair212" *) + LUT3 #( + .INIT(8'hB8)) + \slt1_r[15]_i_1 + (.I0(crac_out[19]), + .I1(ld), + .I2(\u0/slt1_r [14]), + .O(\slt1_r[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair211" *) + LUT3 #( + .INIT(8'hB8)) + \slt1_r[16]_i_1 + (.I0(crac_out[20]), + .I1(ld), + .I2(\u0/slt1_r [15]), + .O(\slt1_r[16]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair211" *) + LUT3 #( + .INIT(8'hB8)) + \slt1_r[17]_i_1 + (.I0(crac_out[21]), + .I1(ld), + .I2(\u0/slt1_r [16]), + .O(\slt1_r[17]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair210" *) + LUT3 #( + .INIT(8'hB8)) + \slt1_r[18]_i_1 + (.I0(crac_out[22]), + .I1(ld), + .I2(\u0/slt1_r [17]), + .O(\slt1_r[18]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair210" *) + LUT3 #( + .INIT(8'hB8)) + \slt1_r[19]_i_1 + (.I0(crac_out[31]), + .I1(ld), + .I2(\u0/slt1_r [18]), + .O(\slt1_r[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair206" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[10]_i_1 + (.I0(crac_out[6]), + .I1(ld), + .I2(\u0/slt2_r [9]), + .O(\slt2_r[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair206" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[11]_i_1 + (.I0(crac_out[7]), + .I1(ld), + .I2(\u0/slt2_r [10]), + .O(\slt2_r[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair205" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[12]_i_1 + (.I0(crac_out[8]), + .I1(ld), + .I2(\u0/slt2_r [11]), + .O(\slt2_r[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair205" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[13]_i_1 + (.I0(crac_out[9]), + .I1(ld), + .I2(\u0/slt2_r [12]), + .O(\slt2_r[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair204" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[14]_i_1 + (.I0(crac_out[10]), + .I1(ld), + .I2(\u0/slt2_r [13]), + .O(\slt2_r[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair204" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[15]_i_1 + (.I0(crac_out[11]), + .I1(ld), + .I2(\u0/slt2_r [14]), + .O(\slt2_r[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair203" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[16]_i_1 + (.I0(crac_out[12]), + .I1(ld), + .I2(\u0/slt2_r [15]), + .O(\slt2_r[16]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair203" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[17]_i_1 + (.I0(crac_out[13]), + .I1(ld), + .I2(\u0/slt2_r [16]), + .O(\slt2_r[17]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair202" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[18]_i_1 + (.I0(crac_out[14]), + .I1(ld), + .I2(\u0/slt2_r [17]), + .O(\slt2_r[18]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair202" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[19]_i_1 + (.I0(crac_out[15]), + .I1(ld), + .I2(\u0/slt2_r [18]), + .O(\slt2_r[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair209" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[4]_i_1 + (.I0(crac_out[0]), + .I1(ld), + .I2(\u0/slt2_r [3]), + .O(\slt2_r[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair209" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[5]_i_1 + (.I0(crac_out[1]), + .I1(ld), + .I2(\u0/slt2_r [4]), + .O(\slt2_r[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair208" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[6]_i_1 + (.I0(crac_out[2]), + .I1(ld), + .I2(\u0/slt2_r [5]), + .O(\slt2_r[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair208" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[7]_i_1 + (.I0(crac_out[3]), + .I1(ld), + .I2(\u0/slt2_r [6]), + .O(\slt2_r[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair207" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[8]_i_1 + (.I0(crac_out[4]), + .I1(ld), + .I2(\u0/slt2_r [7]), + .O(\slt2_r[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair207" *) + LUT3 #( + .INIT(8'hB8)) + \slt2_r[9]_i_1 + (.I0(crac_out[5]), + .I1(ld), + .I2(\u0/slt2_r [8]), + .O(\slt2_r[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair201" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[0]_i_1 + (.I0(out_slt3[0]), + .I1(ld), + .I2(\u0/slt4_r [19]), + .O(\slt3_r[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair196" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[10]_i_1 + (.I0(out_slt3[10]), + .I1(ld), + .I2(\u0/slt3_r [9]), + .O(\slt3_r[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair196" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[11]_i_1 + (.I0(out_slt3[11]), + .I1(ld), + .I2(\u0/slt3_r [10]), + .O(\slt3_r[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair195" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[12]_i_1 + (.I0(out_slt3[12]), + .I1(ld), + .I2(\u0/slt3_r [11]), + .O(\slt3_r[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair195" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[13]_i_1 + (.I0(out_slt3[13]), + .I1(ld), + .I2(\u0/slt3_r [12]), + .O(\slt3_r[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair194" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[14]_i_1 + (.I0(out_slt3[14]), + .I1(ld), + .I2(\u0/slt3_r [13]), + .O(\slt3_r[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair194" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[15]_i_1 + (.I0(out_slt3[15]), + .I1(ld), + .I2(\u0/slt3_r [14]), + .O(\slt3_r[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair193" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[16]_i_1 + (.I0(out_slt3[16]), + .I1(ld), + .I2(\u0/slt3_r [15]), + .O(\slt3_r[16]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair193" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[17]_i_1 + (.I0(out_slt3[17]), + .I1(ld), + .I2(\u0/slt3_r [16]), + .O(\slt3_r[17]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair192" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[18]_i_1 + (.I0(out_slt3[18]), + .I1(ld), + .I2(\u0/slt3_r [17]), + .O(\slt3_r[18]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair192" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[19]_i_1 + (.I0(out_slt3[19]), + .I1(ld), + .I2(\u0/slt3_r [18]), + .O(\slt3_r[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair201" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[1]_i_1 + (.I0(out_slt3[1]), + .I1(ld), + .I2(\u0/slt3_r [0]), + .O(\slt3_r[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair200" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[2]_i_1 + (.I0(out_slt3[2]), + .I1(ld), + .I2(\u0/slt3_r [1]), + .O(\slt3_r[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair200" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[3]_i_1 + (.I0(out_slt3[3]), + .I1(ld), + .I2(\u0/slt3_r [2]), + .O(\slt3_r[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair199" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[4]_i_1 + (.I0(out_slt3[4]), + .I1(ld), + .I2(\u0/slt3_r [3]), + .O(\slt3_r[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair199" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[5]_i_1 + (.I0(out_slt3[5]), + .I1(ld), + .I2(\u0/slt3_r [4]), + .O(\slt3_r[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair198" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[6]_i_1 + (.I0(out_slt3[6]), + .I1(ld), + .I2(\u0/slt3_r [5]), + .O(\slt3_r[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair198" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[7]_i_1 + (.I0(out_slt3[7]), + .I1(ld), + .I2(\u0/slt3_r [6]), + .O(\slt3_r[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair197" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[8]_i_1 + (.I0(out_slt3[8]), + .I1(ld), + .I2(\u0/slt3_r [7]), + .O(\slt3_r[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair197" *) + LUT3 #( + .INIT(8'hB8)) + \slt3_r[9]_i_1 + (.I0(out_slt3[9]), + .I1(ld), + .I2(\u0/slt3_r [8]), + .O(\slt3_r[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair191" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[0]_i_1 + (.I0(out_slt4[0]), + .I1(ld), + .I2(\u0/slt5_r ), + .O(\slt4_r[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair186" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[10]_i_1 + (.I0(out_slt4[10]), + .I1(ld), + .I2(\u0/slt4_r [9]), + .O(\slt4_r[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair186" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[11]_i_1 + (.I0(out_slt4[11]), + .I1(ld), + .I2(\u0/slt4_r [10]), + .O(\slt4_r[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair185" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[12]_i_1 + (.I0(out_slt4[12]), + .I1(ld), + .I2(\u0/slt4_r [11]), + .O(\slt4_r[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair185" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[13]_i_1 + (.I0(out_slt4[13]), + .I1(ld), + .I2(\u0/slt4_r [12]), + .O(\slt4_r[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair184" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[14]_i_1 + (.I0(out_slt4[14]), + .I1(ld), + .I2(\u0/slt4_r [13]), + .O(\slt4_r[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair184" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[15]_i_1 + (.I0(out_slt4[15]), + .I1(ld), + .I2(\u0/slt4_r [14]), + .O(\slt4_r[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair183" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[16]_i_1 + (.I0(out_slt4[16]), + .I1(ld), + .I2(\u0/slt4_r [15]), + .O(\slt4_r[16]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair183" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[17]_i_1 + (.I0(out_slt4[17]), + .I1(ld), + .I2(\u0/slt4_r [16]), + .O(\slt4_r[17]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair182" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[18]_i_1 + (.I0(out_slt4[18]), + .I1(ld), + .I2(\u0/slt4_r [17]), + .O(\slt4_r[18]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair182" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[19]_i_1 + (.I0(out_slt4[19]), + .I1(ld), + .I2(\u0/slt4_r [18]), + .O(\slt4_r[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair191" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[1]_i_1 + (.I0(out_slt4[1]), + .I1(ld), + .I2(\u0/slt4_r [0]), + .O(\slt4_r[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair190" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[2]_i_1 + (.I0(out_slt4[2]), + .I1(ld), + .I2(\u0/slt4_r [1]), + .O(\slt4_r[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair190" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[3]_i_1 + (.I0(out_slt4[3]), + .I1(ld), + .I2(\u0/slt4_r [2]), + .O(\slt4_r[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair189" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[4]_i_1 + (.I0(out_slt4[4]), + .I1(ld), + .I2(\u0/slt4_r [3]), + .O(\slt4_r[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair189" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[5]_i_1 + (.I0(out_slt4[5]), + .I1(ld), + .I2(\u0/slt4_r [4]), + .O(\slt4_r[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair188" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[6]_i_1 + (.I0(out_slt4[6]), + .I1(ld), + .I2(\u0/slt4_r [5]), + .O(\slt4_r[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair188" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[7]_i_1 + (.I0(out_slt4[7]), + .I1(ld), + .I2(\u0/slt4_r [6]), + .O(\slt4_r[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair187" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[8]_i_1 + (.I0(out_slt4[8]), + .I1(ld), + .I2(\u0/slt4_r [7]), + .O(\slt4_r[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair187" *) + LUT3 #( + .INIT(8'hB8)) + \slt4_r[9]_i_1 + (.I0(out_slt4[9]), + .I1(ld), + .I2(\u0/slt4_r [8]), + .O(\slt4_r[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair181" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[0]_i_1 + (.I0(out_slt6[0]), + .I1(ld), + .I2(\u0/slt7_r [19]), + .O(\slt6_r[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair176" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[10]_i_1 + (.I0(out_slt6[10]), + .I1(ld), + .I2(\u0/slt6_r [9]), + .O(\slt6_r[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair176" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[11]_i_1 + (.I0(out_slt6[11]), + .I1(ld), + .I2(\u0/slt6_r [10]), + .O(\slt6_r[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair175" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[12]_i_1 + (.I0(out_slt6[12]), + .I1(ld), + .I2(\u0/slt6_r [11]), + .O(\slt6_r[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair175" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[13]_i_1 + (.I0(out_slt6[13]), + .I1(ld), + .I2(\u0/slt6_r [12]), + .O(\slt6_r[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair174" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[14]_i_1 + (.I0(out_slt6[14]), + .I1(ld), + .I2(\u0/slt6_r [13]), + .O(\slt6_r[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair174" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[15]_i_1 + (.I0(out_slt6[15]), + .I1(ld), + .I2(\u0/slt6_r [14]), + .O(\slt6_r[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair173" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[16]_i_1 + (.I0(out_slt6[16]), + .I1(ld), + .I2(\u0/slt6_r [15]), + .O(\slt6_r[16]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair173" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[17]_i_1 + (.I0(out_slt6[17]), + .I1(ld), + .I2(\u0/slt6_r [16]), + .O(\slt6_r[17]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair172" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[18]_i_1 + (.I0(out_slt6[18]), + .I1(ld), + .I2(\u0/slt6_r [17]), + .O(\slt6_r[18]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair172" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[19]_i_1 + (.I0(out_slt6[19]), + .I1(ld), + .I2(\u0/slt6_r [18]), + .O(\slt6_r[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair181" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[1]_i_1 + (.I0(out_slt6[1]), + .I1(ld), + .I2(\u0/slt6_r [0]), + .O(\slt6_r[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair180" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[2]_i_1 + (.I0(out_slt6[2]), + .I1(ld), + .I2(\u0/slt6_r [1]), + .O(\slt6_r[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair180" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[3]_i_1 + (.I0(out_slt6[3]), + .I1(ld), + .I2(\u0/slt6_r [2]), + .O(\slt6_r[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair179" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[4]_i_1 + (.I0(out_slt6[4]), + .I1(ld), + .I2(\u0/slt6_r [3]), + .O(\slt6_r[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair179" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[5]_i_1 + (.I0(out_slt6[5]), + .I1(ld), + .I2(\u0/slt6_r [4]), + .O(\slt6_r[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair178" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[6]_i_1 + (.I0(out_slt6[6]), + .I1(ld), + .I2(\u0/slt6_r [5]), + .O(\slt6_r[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair178" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[7]_i_1 + (.I0(out_slt6[7]), + .I1(ld), + .I2(\u0/slt6_r [6]), + .O(\slt6_r[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair177" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[8]_i_1 + (.I0(out_slt6[8]), + .I1(ld), + .I2(\u0/slt6_r [7]), + .O(\slt6_r[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair177" *) + LUT3 #( + .INIT(8'hB8)) + \slt6_r[9]_i_1 + (.I0(out_slt6[9]), + .I1(ld), + .I2(\u0/slt6_r [8]), + .O(\slt6_r[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair171" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[0]_i_1 + (.I0(out_slt7[0]), + .I1(ld), + .I2(\u0/slt8_r [19]), + .O(\slt7_r[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair166" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[10]_i_1 + (.I0(out_slt7[10]), + .I1(ld), + .I2(\u0/slt7_r [9]), + .O(\slt7_r[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair166" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[11]_i_1 + (.I0(out_slt7[11]), + .I1(ld), + .I2(\u0/slt7_r [10]), + .O(\slt7_r[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair165" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[12]_i_1 + (.I0(out_slt7[12]), + .I1(ld), + .I2(\u0/slt7_r [11]), + .O(\slt7_r[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair165" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[13]_i_1 + (.I0(out_slt7[13]), + .I1(ld), + .I2(\u0/slt7_r [12]), + .O(\slt7_r[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair164" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[14]_i_1 + (.I0(out_slt7[14]), + .I1(ld), + .I2(\u0/slt7_r [13]), + .O(\slt7_r[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair164" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[15]_i_1 + (.I0(out_slt7[15]), + .I1(ld), + .I2(\u0/slt7_r [14]), + .O(\slt7_r[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair163" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[16]_i_1 + (.I0(out_slt7[16]), + .I1(ld), + .I2(\u0/slt7_r [15]), + .O(\slt7_r[16]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair163" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[17]_i_1 + (.I0(out_slt7[17]), + .I1(ld), + .I2(\u0/slt7_r [16]), + .O(\slt7_r[17]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair162" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[18]_i_1 + (.I0(out_slt7[18]), + .I1(ld), + .I2(\u0/slt7_r [17]), + .O(\slt7_r[18]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair162" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[19]_i_1 + (.I0(out_slt7[19]), + .I1(ld), + .I2(\u0/slt7_r [18]), + .O(\slt7_r[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair171" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[1]_i_1 + (.I0(out_slt7[1]), + .I1(ld), + .I2(\u0/slt7_r [0]), + .O(\slt7_r[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair170" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[2]_i_1 + (.I0(out_slt7[2]), + .I1(ld), + .I2(\u0/slt7_r [1]), + .O(\slt7_r[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair170" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[3]_i_1 + (.I0(out_slt7[3]), + .I1(ld), + .I2(\u0/slt7_r [2]), + .O(\slt7_r[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair169" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[4]_i_1 + (.I0(out_slt7[4]), + .I1(ld), + .I2(\u0/slt7_r [3]), + .O(\slt7_r[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair169" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[5]_i_1 + (.I0(out_slt7[5]), + .I1(ld), + .I2(\u0/slt7_r [4]), + .O(\slt7_r[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair168" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[6]_i_1 + (.I0(out_slt7[6]), + .I1(ld), + .I2(\u0/slt7_r [5]), + .O(\slt7_r[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair168" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[7]_i_1 + (.I0(out_slt7[7]), + .I1(ld), + .I2(\u0/slt7_r [6]), + .O(\slt7_r[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair167" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[8]_i_1 + (.I0(out_slt7[8]), + .I1(ld), + .I2(\u0/slt7_r [7]), + .O(\slt7_r[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair167" *) + LUT3 #( + .INIT(8'hB8)) + \slt7_r[9]_i_1 + (.I0(out_slt7[9]), + .I1(ld), + .I2(\u0/slt7_r [8]), + .O(\slt7_r[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair161" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[0]_i_1 + (.I0(out_slt8[0]), + .I1(ld), + .I2(\u0/slt9_r [19]), + .O(\slt8_r[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair156" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[10]_i_1 + (.I0(out_slt8[10]), + .I1(ld), + .I2(\u0/slt8_r [9]), + .O(\slt8_r[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair156" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[11]_i_1 + (.I0(out_slt8[11]), + .I1(ld), + .I2(\u0/slt8_r [10]), + .O(\slt8_r[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair155" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[12]_i_1 + (.I0(out_slt8[12]), + .I1(ld), + .I2(\u0/slt8_r [11]), + .O(\slt8_r[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair155" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[13]_i_1 + (.I0(out_slt8[13]), + .I1(ld), + .I2(\u0/slt8_r [12]), + .O(\slt8_r[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair154" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[14]_i_1 + (.I0(out_slt8[14]), + .I1(ld), + .I2(\u0/slt8_r [13]), + .O(\slt8_r[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair154" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[15]_i_1 + (.I0(out_slt8[15]), + .I1(ld), + .I2(\u0/slt8_r [14]), + .O(\slt8_r[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair153" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[16]_i_1 + (.I0(out_slt8[16]), + .I1(ld), + .I2(\u0/slt8_r [15]), + .O(\slt8_r[16]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair153" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[17]_i_1 + (.I0(out_slt8[17]), + .I1(ld), + .I2(\u0/slt8_r [16]), + .O(\slt8_r[17]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair152" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[18]_i_1 + (.I0(out_slt8[18]), + .I1(ld), + .I2(\u0/slt8_r [17]), + .O(\slt8_r[18]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair152" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[19]_i_1 + (.I0(out_slt8[19]), + .I1(ld), + .I2(\u0/slt8_r [18]), + .O(\slt8_r[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair161" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[1]_i_1 + (.I0(out_slt8[1]), + .I1(ld), + .I2(\u0/slt8_r [0]), + .O(\slt8_r[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair160" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[2]_i_1 + (.I0(out_slt8[2]), + .I1(ld), + .I2(\u0/slt8_r [1]), + .O(\slt8_r[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair160" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[3]_i_1 + (.I0(out_slt8[3]), + .I1(ld), + .I2(\u0/slt8_r [2]), + .O(\slt8_r[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair159" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[4]_i_1 + (.I0(out_slt8[4]), + .I1(ld), + .I2(\u0/slt8_r [3]), + .O(\slt8_r[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair159" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[5]_i_1 + (.I0(out_slt8[5]), + .I1(ld), + .I2(\u0/slt8_r [4]), + .O(\slt8_r[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair158" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[6]_i_1 + (.I0(out_slt8[6]), + .I1(ld), + .I2(\u0/slt8_r [5]), + .O(\slt8_r[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair158" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[7]_i_1 + (.I0(out_slt8[7]), + .I1(ld), + .I2(\u0/slt8_r [6]), + .O(\slt8_r[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair157" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[8]_i_1 + (.I0(out_slt8[8]), + .I1(ld), + .I2(\u0/slt8_r [7]), + .O(\slt8_r[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair157" *) + LUT3 #( + .INIT(8'hB8)) + \slt8_r[9]_i_1 + (.I0(out_slt8[9]), + .I1(ld), + .I2(\u0/slt8_r [8]), + .O(\slt8_r[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair142" *) + LUT2 #( + .INIT(4'h8)) + \slt9_r[0]_i_1 + (.I0(out_slt9[0]), + .I1(ld), + .O(\slt9_r[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair147" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[10]_i_1 + (.I0(out_slt9[10]), + .I1(ld), + .I2(\u0/slt9_r [9]), + .O(\u0/p_0_in [10])); + (* SOFT_HLUTNM = "soft_lutpair146" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[11]_i_1 + (.I0(out_slt9[11]), + .I1(ld), + .I2(\u0/slt9_r [10]), + .O(\u0/p_0_in [11])); + (* SOFT_HLUTNM = "soft_lutpair146" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[12]_i_1 + (.I0(out_slt9[12]), + .I1(ld), + .I2(\u0/slt9_r [11]), + .O(\u0/p_0_in [12])); + (* SOFT_HLUTNM = "soft_lutpair145" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[13]_i_1 + (.I0(out_slt9[13]), + .I1(ld), + .I2(\u0/slt9_r [12]), + .O(\u0/p_0_in [13])); + (* SOFT_HLUTNM = "soft_lutpair145" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[14]_i_1 + (.I0(out_slt9[14]), + .I1(ld), + .I2(\u0/slt9_r [13]), + .O(\u0/p_0_in [14])); + (* SOFT_HLUTNM = "soft_lutpair144" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[15]_i_1 + (.I0(out_slt9[15]), + .I1(ld), + .I2(\u0/slt9_r [14]), + .O(\u0/p_0_in [15])); + (* SOFT_HLUTNM = "soft_lutpair144" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[16]_i_1 + (.I0(out_slt9[16]), + .I1(ld), + .I2(\u0/slt9_r [15]), + .O(\u0/p_0_in [16])); + (* SOFT_HLUTNM = "soft_lutpair143" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[17]_i_1 + (.I0(out_slt9[17]), + .I1(ld), + .I2(\u0/slt9_r [16]), + .O(\u0/p_0_in [17])); + (* SOFT_HLUTNM = "soft_lutpair143" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[18]_i_1 + (.I0(out_slt9[18]), + .I1(ld), + .I2(\u0/slt9_r [17]), + .O(\u0/p_0_in [18])); + (* SOFT_HLUTNM = "soft_lutpair142" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[19]_i_1 + (.I0(out_slt9[19]), + .I1(ld), + .I2(\u0/slt9_r [18]), + .O(\u0/p_0_in [19])); + (* SOFT_HLUTNM = "soft_lutpair151" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[1]_i_1 + (.I0(out_slt9[1]), + .I1(ld), + .I2(\u0/slt9_r [0]), + .O(\u0/p_0_in [1])); + (* SOFT_HLUTNM = "soft_lutpair151" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[2]_i_1 + (.I0(out_slt9[2]), + .I1(ld), + .I2(\u0/slt9_r [1]), + .O(\u0/p_0_in [2])); + (* SOFT_HLUTNM = "soft_lutpair150" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[3]_i_1 + (.I0(out_slt9[3]), + .I1(ld), + .I2(\u0/slt9_r [2]), + .O(\u0/p_0_in [3])); + (* SOFT_HLUTNM = "soft_lutpair150" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[4]_i_1 + (.I0(out_slt9[4]), + .I1(ld), + .I2(\u0/slt9_r [3]), + .O(\u0/p_0_in [4])); + (* SOFT_HLUTNM = "soft_lutpair149" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[5]_i_1 + (.I0(out_slt9[5]), + .I1(ld), + .I2(\u0/slt9_r [4]), + .O(\u0/p_0_in [5])); + (* SOFT_HLUTNM = "soft_lutpair149" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[6]_i_1 + (.I0(out_slt9[6]), + .I1(ld), + .I2(\u0/slt9_r [5]), + .O(\u0/p_0_in [6])); + (* SOFT_HLUTNM = "soft_lutpair148" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[7]_i_1 + (.I0(out_slt9[7]), + .I1(ld), + .I2(\u0/slt9_r [6]), + .O(\u0/p_0_in [7])); + (* SOFT_HLUTNM = "soft_lutpair148" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[8]_i_1 + (.I0(out_slt9[8]), + .I1(ld), + .I2(\u0/slt9_r [7]), + .O(\u0/p_0_in [8])); + (* SOFT_HLUTNM = "soft_lutpair147" *) + LUT3 #( + .INIT(8'hB8)) + \slt9_r[9]_i_1 + (.I0(out_slt9[9]), + .I1(ld), + .I2(\u0/slt9_r [8]), + .O(\u0/p_0_in [9])); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT2 #( + .INIT(4'h9)) + \status[0]_i_1 + (.I0(\u3/wp_reg_n_0_[0] ), + .I1(\u3/p_0_in [0]), + .O(\status[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT2 #( + .INIT(4'h9)) + \status[0]_i_1__0 + (.I0(\u4/wp_reg_n_0_[0] ), + .I1(\u4/p_0_in [0]), + .O(\status[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT2 #( + .INIT(4'h9)) + \status[0]_i_1__1 + (.I0(\u5/wp_reg_n_0_[0] ), + .I1(\u5/p_0_in [0]), + .O(\status[0]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT2 #( + .INIT(4'h9)) + \status[0]_i_1__2 + (.I0(\u6/wp_reg_n_0_[0] ), + .I1(\u6/p_0_in [0]), + .O(\status[0]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT2 #( + .INIT(4'h9)) + \status[0]_i_1__3 + (.I0(\u7/wp_reg_n_0_[0] ), + .I1(\u7/p_0_in [0]), + .O(\status[0]_i_1__3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT2 #( + .INIT(4'h9)) + \status[0]_i_1__4 + (.I0(\u8/wp_reg_n_0_[0] ), + .I1(\u8/p_0_in [0]), + .O(\status[0]_i_1__4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT2 #( + .INIT(4'h9)) + \status[0]_i_1__5 + (.I0(\u11/rp_reg_n_0_[0] ), + .I1(\u11/p_1_in [0]), + .O(\status[0]_i_1__5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT2 #( + .INIT(4'h9)) + \status[0]_i_1__6 + (.I0(\u10/rp_reg_n_0_[0] ), + .I1(\u10/p_1_in [0]), + .O(\status[0]_i_1__6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT2 #( + .INIT(4'h9)) + \status[0]_i_1__7 + (.I0(\u9/rp_reg_n_0_[0] ), + .I1(\u9/p_1_in [0]), + .O(\status[0]_i_1__7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT4 #( + .INIT(16'hB44B)) + \status[1]_i_1 + (.I0(\u3/p_0_in [0]), + .I1(\u3/wp_reg_n_0_[0] ), + .I2(\u3/p_0_in [1]), + .I3(\u3/wp_reg_n_0_[1] ), + .O(\u3/status0 )); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT4 #( + .INIT(16'hB44B)) + \status[1]_i_1__0 + (.I0(\u4/p_0_in [0]), + .I1(\u4/wp_reg_n_0_[0] ), + .I2(\u4/p_0_in [1]), + .I3(\u4/wp_reg_n_0_[1] ), + .O(\u4/status0 )); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT4 #( + .INIT(16'hB44B)) + \status[1]_i_1__1 + (.I0(\u5/p_0_in [0]), + .I1(\u5/wp_reg_n_0_[0] ), + .I2(\u5/p_0_in [1]), + .I3(\u5/wp_reg_n_0_[1] ), + .O(\u5/status0 )); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT4 #( + .INIT(16'hB44B)) + \status[1]_i_1__2 + (.I0(\u6/p_0_in [0]), + .I1(\u6/wp_reg_n_0_[0] ), + .I2(\u6/p_0_in [1]), + .I3(\u6/wp_reg_n_0_[1] ), + .O(\u6/status0 )); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT4 #( + .INIT(16'hB44B)) + \status[1]_i_1__3 + (.I0(\u7/p_0_in [0]), + .I1(\u7/wp_reg_n_0_[0] ), + .I2(\u7/p_0_in [1]), + .I3(\u7/wp_reg_n_0_[1] ), + .O(\u7/status0 )); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT4 #( + .INIT(16'hB44B)) + \status[1]_i_1__4 + (.I0(\u8/p_0_in [0]), + .I1(\u8/wp_reg_n_0_[0] ), + .I2(\u8/p_0_in [1]), + .I3(\u8/wp_reg_n_0_[1] ), + .O(\u8/status0 )); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT4 #( + .INIT(16'hB44B)) + \status[1]_i_1__5 + (.I0(\u9/p_1_in [0]), + .I1(\u9/rp_reg_n_0_[0] ), + .I2(\u9/p_1_in [1]), + .I3(\u9/rp_reg_n_0_[1] ), + .O(\u9/status0 )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT4 #( + .INIT(16'hB44B)) + \status[1]_i_1__6 + (.I0(\u10/p_1_in [0]), + .I1(\u10/rp_reg_n_0_[0] ), + .I2(\u10/p_1_in [1]), + .I3(\u10/rp_reg_n_0_[1] ), + .O(\u10/status0 )); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT4 #( + .INIT(16'hB44B)) + \status[1]_i_1__7 + (.I0(\u11/p_1_in [0]), + .I1(\u11/rp_reg_n_0_[0] ), + .I2(\u11/p_1_in [1]), + .I3(\u11/rp_reg_n_0_[1] ), + .O(\u11/status0 )); + LUT6 #( + .INIT(64'h0000001000000000)) + suspended_i_1 + (.I0(\u2/to_cnt_reg [2]), + .I1(\u2/to_cnt_reg [3]), + .I2(\u2/to_cnt_reg [0]), + .I3(\u2/to_cnt_reg [1]), + .I4(\u2/to_cnt_reg [4]), + .I5(\u2/to_cnt_reg [5]), + .O(\u2/to )); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT4 #( + .INIT(16'h0001)) + sync_beat_i_1 + (.I0(\u2/cnt_reg [7]), + .I1(\u2/cnt_reg [6]), + .I2(\u2/cnt_reg [5]), + .I3(\u2/cnt_reg [4]), + .O(\u2/sync_beat0 )); + LUT2 #( + .INIT(4'hE)) + sync_pad_o_INST_0 + (.I0(\u2/sync_beat ), + .I1(\u2/sync_resume_reg_n_0 ), + .O(sync_pad_o)); + LUT4 #( + .INIT(16'hF080)) + sync_resume_i_1 + (.I0(resume_req), + .I1(suspended_o), + .I2(sync_resume_i_2_n_0), + .I3(\u2/sync_resume_reg_n_0 ), + .O(sync_resume_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT4 #( + .INIT(16'hEFFF)) + sync_resume_i_2 + (.I0(\u2/res_cnt_reg [3]), + .I1(\u2/res_cnt_reg [1]), + .I2(\u2/res_cnt_reg [2]), + .I3(\u2/res_cnt_reg [0]), + .O(sync_resume_i_2_n_0)); + LUT2 #( + .INIT(4'h1)) + \to_cnt[0]_i_1 + (.I0(\u2/to_cnt_reg [0]), + .I1(\u2/bit_clk_e ), + .O(\to_cnt[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT3 #( + .INIT(8'h06)) + \to_cnt[1]_i_1 + (.I0(\u2/to_cnt_reg [1]), + .I1(\u2/to_cnt_reg [0]), + .I2(\u2/bit_clk_e ), + .O(p_0_in__3[1])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'h006A)) + \to_cnt[2]_i_1 + (.I0(\u2/to_cnt_reg [2]), + .I1(\u2/to_cnt_reg [0]), + .I2(\u2/to_cnt_reg [1]), + .I3(\u2/bit_clk_e ), + .O(p_0_in__3[2])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT5 #( + .INIT(32'h00006AAA)) + \to_cnt[3]_i_1 + (.I0(\u2/to_cnt_reg [3]), + .I1(\u2/to_cnt_reg [1]), + .I2(\u2/to_cnt_reg [0]), + .I3(\u2/to_cnt_reg [2]), + .I4(\u2/bit_clk_e ), + .O(p_0_in__3[3])); + LUT6 #( + .INIT(64'h000000006AAAAAAA)) + \to_cnt[4]_i_1 + (.I0(\u2/to_cnt_reg [4]), + .I1(\u2/to_cnt_reg [3]), + .I2(\u2/to_cnt_reg [2]), + .I3(\u2/to_cnt_reg [1]), + .I4(\u2/to_cnt_reg [0]), + .I5(\u2/bit_clk_e ), + .O(p_0_in__3[4])); + LUT2 #( + .INIT(4'hB)) + \to_cnt[5]_i_1 + (.I0(\to_cnt[5]_i_3_n_0 ), + .I1(\u2/to_cnt_reg [0]), + .O(\to_cnt[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h000000006AAAAAAA)) + \to_cnt[5]_i_2 + (.I0(\u2/to_cnt_reg [5]), + .I1(\u2/to_cnt_reg [2]), + .I2(\u2/to_cnt_reg [3]), + .I3(\u2/to_cnt_reg [4]), + .I4(\to_cnt[5]_i_4_n_0 ), + .I5(\u2/bit_clk_e ), + .O(p_0_in__3[5])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFB)) + \to_cnt[5]_i_3 + (.I0(\u2/bit_clk_e ), + .I1(\u2/to_cnt_reg [5]), + .I2(\u2/to_cnt_reg [3]), + .I3(\u2/to_cnt_reg [4]), + .I4(\u2/to_cnt_reg [2]), + .I5(\u2/to_cnt_reg [1]), + .O(\to_cnt[5]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT2 #( + .INIT(4'h8)) + \to_cnt[5]_i_4 + (.I0(\u2/to_cnt_reg [0]), + .I1(\u2/to_cnt_reg [1]), + .O(\to_cnt[5]_i_4_n_0 )); + FDRE \u0/slt0_r_reg[10] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt0_r [9]), + .Q(\u0/slt0_r [10]), + .R(ld)); + FDRE \u0/slt0_r_reg[11] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt0_r[11]_i_1_n_0 ), + .Q(\u0/slt0_r [11]), + .R(\ )); + FDRE \u0/slt0_r_reg[12] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt0_r[12]_i_1_n_0 ), + .Q(\u0/slt0_r [12]), + .R(\ )); + FDRE \u0/slt0_r_reg[13] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt0_r[13]_i_1_n_0 ), + .Q(\u0/slt0_r [13]), + .R(\ )); + FDRE \u0/slt0_r_reg[14] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt0_r[14]_i_1_n_0 ), + .Q(\u0/slt0_r [14]), + .R(\ )); + FDRE \u0/slt0_r_reg[15] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt0_r[15]_i_1_n_0 ), + .Q(sdata_pad_o), + .R(\ )); + (* srl_bus_name = "\u0/slt0_r_reg " *) + (* srl_name = "\u0/slt0_r_reg[3]_srl4___u0_slt5_r_reg_r_2 " *) + SRL16E \u0/slt0_r_reg[3]_srl4___u0_slt5_r_reg_r_2 + (.A0(\ ), + .A1(\ ), + .A2(\ ), + .A3(\ ), + .CE(\ ), + .CLK(bit_clk_pad_i), + .D(\u0/slt1_r [19]), + .Q(\u0/slt0_r_reg[3]_srl4___u0_slt5_r_reg_r_2_n_0 )); + FDRE \u0/slt0_r_reg[4]_u0_slt5_r_reg_r_3 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt0_r_reg[3]_srl4___u0_slt5_r_reg_r_2_n_0 ), + .Q(\u0/slt0_r_reg[4]_u0_slt5_r_reg_r_3_n_0 ), + .R(\ )); + FDRE \u0/slt0_r_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt0_r_reg_gate_n_0 ), + .Q(\u0/slt0_r [5]), + .R(ld)); + FDRE \u0/slt0_r_reg[6] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt0_r[6]_i_1_n_0 ), + .Q(\u0/slt0_r [6]), + .R(\ )); + FDRE \u0/slt0_r_reg[7] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt0_r[7]_i_1_n_0 ), + .Q(\u0/slt0_r [7]), + .R(\ )); + FDRE \u0/slt0_r_reg[8] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt0_r[8]_i_1_n_0 ), + .Q(\u0/slt0_r [8]), + .R(\ )); + FDRE \u0/slt0_r_reg[9] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt0_r[9]_i_1_n_0 ), + .Q(\u0/slt0_r [9]), + .R(\ )); + LUT2 #( + .INIT(4'h8)) + \u0/slt0_r_reg_gate + (.I0(\u0/slt0_r_reg[4]_u0_slt5_r_reg_r_3_n_0 ), + .I1(\u0/slt5_r_reg_r_3_n_0 ), + .O(\u0/slt0_r_reg_gate_n_0 )); + FDRE \u0/slt1_r_reg[10]_u0_slt5_r_reg_r_9 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt1_r_reg[9]_srl10___u0_slt5_r_reg_r_8_n_0 ), + .Q(\u0/slt1_r_reg[10]_u0_slt5_r_reg_r_9_n_0 ), + .R(\ )); + FDRE \u0/slt1_r_reg[11] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt1_r_reg_gate_n_0 ), + .Q(\u0/slt1_r [11]), + .R(ld)); + FDRE \u0/slt1_r_reg[12] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt1_r[12]_i_1_n_0 ), + .Q(\u0/slt1_r [12]), + .R(\ )); + FDRE \u0/slt1_r_reg[13] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt1_r[13]_i_1_n_0 ), + .Q(\u0/slt1_r [13]), + .R(\ )); + FDRE \u0/slt1_r_reg[14] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt1_r[14]_i_1_n_0 ), + .Q(\u0/slt1_r [14]), + .R(\ )); + FDRE \u0/slt1_r_reg[15] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt1_r[15]_i_1_n_0 ), + .Q(\u0/slt1_r [15]), + .R(\ )); + FDRE \u0/slt1_r_reg[16] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt1_r[16]_i_1_n_0 ), + .Q(\u0/slt1_r [16]), + .R(\ )); + FDRE \u0/slt1_r_reg[17] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt1_r[17]_i_1_n_0 ), + .Q(\u0/slt1_r [17]), + .R(\ )); + FDRE \u0/slt1_r_reg[18] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt1_r[18]_i_1_n_0 ), + .Q(\u0/slt1_r [18]), + .R(\ )); + FDRE \u0/slt1_r_reg[19] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt1_r[19]_i_1_n_0 ), + .Q(\u0/slt1_r [19]), + .R(\ )); + (* srl_bus_name = "\u0/slt1_r_reg " *) + (* srl_name = "\u0/slt1_r_reg[9]_srl10___u0_slt5_r_reg_r_8 " *) + SRL16E \u0/slt1_r_reg[9]_srl10___u0_slt5_r_reg_r_8 + (.A0(\ ), + .A1(\ ), + .A2(\ ), + .A3(\ ), + .CE(\ ), + .CLK(bit_clk_pad_i), + .D(\u0/slt2_r [19]), + .Q(\u0/slt1_r_reg[9]_srl10___u0_slt5_r_reg_r_8_n_0 )); + LUT2 #( + .INIT(4'h8)) + \u0/slt1_r_reg_gate + (.I0(\u0/slt1_r_reg[10]_u0_slt5_r_reg_r_9_n_0 ), + .I1(\u0/slt5_r_reg_r_9_n_0 ), + .O(\u0/slt1_r_reg_gate_n_0 )); + FDRE \u0/slt2_r_reg[10] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[10]_i_1_n_0 ), + .Q(\u0/slt2_r [10]), + .R(\ )); + FDRE \u0/slt2_r_reg[11] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[11]_i_1_n_0 ), + .Q(\u0/slt2_r [11]), + .R(\ )); + FDRE \u0/slt2_r_reg[12] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[12]_i_1_n_0 ), + .Q(\u0/slt2_r [12]), + .R(\ )); + FDRE \u0/slt2_r_reg[13] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[13]_i_1_n_0 ), + .Q(\u0/slt2_r [13]), + .R(\ )); + FDRE \u0/slt2_r_reg[14] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[14]_i_1_n_0 ), + .Q(\u0/slt2_r [14]), + .R(\ )); + FDRE \u0/slt2_r_reg[15] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[15]_i_1_n_0 ), + .Q(\u0/slt2_r [15]), + .R(\ )); + FDRE \u0/slt2_r_reg[16] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[16]_i_1_n_0 ), + .Q(\u0/slt2_r [16]), + .R(\ )); + FDRE \u0/slt2_r_reg[17] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[17]_i_1_n_0 ), + .Q(\u0/slt2_r [17]), + .R(\ )); + FDRE \u0/slt2_r_reg[18] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[18]_i_1_n_0 ), + .Q(\u0/slt2_r [18]), + .R(\ )); + FDRE \u0/slt2_r_reg[19] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[19]_i_1_n_0 ), + .Q(\u0/slt2_r [19]), + .R(\ )); + (* srl_bus_name = "\u0/slt2_r_reg " *) + (* srl_name = "\u0/slt2_r_reg[1]_srl2___u0_slt5_r_reg_r_0 " *) + SRL16E \u0/slt2_r_reg[1]_srl2___u0_slt5_r_reg_r_0 + (.A0(\ ), + .A1(\ ), + .A2(\ ), + .A3(\ ), + .CE(\ ), + .CLK(bit_clk_pad_i), + .D(\u0/slt3_r [19]), + .Q(\u0/slt2_r_reg[1]_srl2___u0_slt5_r_reg_r_0_n_0 )); + FDRE \u0/slt2_r_reg[2]_u0_slt5_r_reg_r_1 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt2_r_reg[1]_srl2___u0_slt5_r_reg_r_0_n_0 ), + .Q(\u0/slt2_r_reg[2]_u0_slt5_r_reg_r_1_n_0 ), + .R(\ )); + FDRE \u0/slt2_r_reg[3] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt2_r_reg_gate_n_0 ), + .Q(\u0/slt2_r [3]), + .R(ld)); + FDRE \u0/slt2_r_reg[4] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[4]_i_1_n_0 ), + .Q(\u0/slt2_r [4]), + .R(\ )); + FDRE \u0/slt2_r_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[5]_i_1_n_0 ), + .Q(\u0/slt2_r [5]), + .R(\ )); + FDRE \u0/slt2_r_reg[6] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[6]_i_1_n_0 ), + .Q(\u0/slt2_r [6]), + .R(\ )); + FDRE \u0/slt2_r_reg[7] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[7]_i_1_n_0 ), + .Q(\u0/slt2_r [7]), + .R(\ )); + FDRE \u0/slt2_r_reg[8] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[8]_i_1_n_0 ), + .Q(\u0/slt2_r [8]), + .R(\ )); + FDRE \u0/slt2_r_reg[9] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt2_r[9]_i_1_n_0 ), + .Q(\u0/slt2_r [9]), + .R(\ )); + LUT2 #( + .INIT(4'h8)) + \u0/slt2_r_reg_gate + (.I0(\u0/slt2_r_reg[2]_u0_slt5_r_reg_r_1_n_0 ), + .I1(\u0/slt5_r_reg_r_1_n_0 ), + .O(\u0/slt2_r_reg_gate_n_0 )); + FDRE \u0/slt3_r_reg[0] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[0]_i_1_n_0 ), + .Q(\u0/slt3_r [0]), + .R(\ )); + FDRE \u0/slt3_r_reg[10] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[10]_i_1_n_0 ), + .Q(\u0/slt3_r [10]), + .R(\ )); + FDRE \u0/slt3_r_reg[11] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[11]_i_1_n_0 ), + .Q(\u0/slt3_r [11]), + .R(\ )); + FDRE \u0/slt3_r_reg[12] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[12]_i_1_n_0 ), + .Q(\u0/slt3_r [12]), + .R(\ )); + FDRE \u0/slt3_r_reg[13] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[13]_i_1_n_0 ), + .Q(\u0/slt3_r [13]), + .R(\ )); + FDRE \u0/slt3_r_reg[14] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[14]_i_1_n_0 ), + .Q(\u0/slt3_r [14]), + .R(\ )); + FDRE \u0/slt3_r_reg[15] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[15]_i_1_n_0 ), + .Q(\u0/slt3_r [15]), + .R(\ )); + FDRE \u0/slt3_r_reg[16] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[16]_i_1_n_0 ), + .Q(\u0/slt3_r [16]), + .R(\ )); + FDRE \u0/slt3_r_reg[17] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[17]_i_1_n_0 ), + .Q(\u0/slt3_r [17]), + .R(\ )); + FDRE \u0/slt3_r_reg[18] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[18]_i_1_n_0 ), + .Q(\u0/slt3_r [18]), + .R(\ )); + FDRE \u0/slt3_r_reg[19] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[19]_i_1_n_0 ), + .Q(\u0/slt3_r [19]), + .R(\ )); + FDRE \u0/slt3_r_reg[1] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[1]_i_1_n_0 ), + .Q(\u0/slt3_r [1]), + .R(\ )); + FDRE \u0/slt3_r_reg[2] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[2]_i_1_n_0 ), + .Q(\u0/slt3_r [2]), + .R(\ )); + FDRE \u0/slt3_r_reg[3] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[3]_i_1_n_0 ), + .Q(\u0/slt3_r [3]), + .R(\ )); + FDRE \u0/slt3_r_reg[4] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[4]_i_1_n_0 ), + .Q(\u0/slt3_r [4]), + .R(\ )); + FDRE \u0/slt3_r_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[5]_i_1_n_0 ), + .Q(\u0/slt3_r [5]), + .R(\ )); + FDRE \u0/slt3_r_reg[6] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[6]_i_1_n_0 ), + .Q(\u0/slt3_r [6]), + .R(\ )); + FDRE \u0/slt3_r_reg[7] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[7]_i_1_n_0 ), + .Q(\u0/slt3_r [7]), + .R(\ )); + FDRE \u0/slt3_r_reg[8] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[8]_i_1_n_0 ), + .Q(\u0/slt3_r [8]), + .R(\ )); + FDRE \u0/slt3_r_reg[9] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt3_r[9]_i_1_n_0 ), + .Q(\u0/slt3_r [9]), + .R(\ )); + FDRE \u0/slt4_r_reg[0] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[0]_i_1_n_0 ), + .Q(\u0/slt4_r [0]), + .R(\ )); + FDRE \u0/slt4_r_reg[10] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[10]_i_1_n_0 ), + .Q(\u0/slt4_r [10]), + .R(\ )); + FDRE \u0/slt4_r_reg[11] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[11]_i_1_n_0 ), + .Q(\u0/slt4_r [11]), + .R(\ )); + FDRE \u0/slt4_r_reg[12] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[12]_i_1_n_0 ), + .Q(\u0/slt4_r [12]), + .R(\ )); + FDRE \u0/slt4_r_reg[13] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[13]_i_1_n_0 ), + .Q(\u0/slt4_r [13]), + .R(\ )); + FDRE \u0/slt4_r_reg[14] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[14]_i_1_n_0 ), + .Q(\u0/slt4_r [14]), + .R(\ )); + FDRE \u0/slt4_r_reg[15] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[15]_i_1_n_0 ), + .Q(\u0/slt4_r [15]), + .R(\ )); + FDRE \u0/slt4_r_reg[16] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[16]_i_1_n_0 ), + .Q(\u0/slt4_r [16]), + .R(\ )); + FDRE \u0/slt4_r_reg[17] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[17]_i_1_n_0 ), + .Q(\u0/slt4_r [17]), + .R(\ )); + FDRE \u0/slt4_r_reg[18] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[18]_i_1_n_0 ), + .Q(\u0/slt4_r [18]), + .R(\ )); + FDRE \u0/slt4_r_reg[19] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[19]_i_1_n_0 ), + .Q(\u0/slt4_r [19]), + .R(\ )); + FDRE \u0/slt4_r_reg[1] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[1]_i_1_n_0 ), + .Q(\u0/slt4_r [1]), + .R(\ )); + FDRE \u0/slt4_r_reg[2] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[2]_i_1_n_0 ), + .Q(\u0/slt4_r [2]), + .R(\ )); + FDRE \u0/slt4_r_reg[3] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[3]_i_1_n_0 ), + .Q(\u0/slt4_r [3]), + .R(\ )); + FDRE \u0/slt4_r_reg[4] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[4]_i_1_n_0 ), + .Q(\u0/slt4_r [4]), + .R(\ )); + FDRE \u0/slt4_r_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[5]_i_1_n_0 ), + .Q(\u0/slt4_r [5]), + .R(\ )); + FDRE \u0/slt4_r_reg[6] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[6]_i_1_n_0 ), + .Q(\u0/slt4_r [6]), + .R(\ )); + FDRE \u0/slt4_r_reg[7] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[7]_i_1_n_0 ), + .Q(\u0/slt4_r [7]), + .R(\ )); + FDRE \u0/slt4_r_reg[8] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[8]_i_1_n_0 ), + .Q(\u0/slt4_r [8]), + .R(\ )); + FDRE \u0/slt4_r_reg[9] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt4_r[9]_i_1_n_0 ), + .Q(\u0/slt4_r [9]), + .R(\ )); + (* srl_bus_name = "\u0/slt5_r_reg " *) + (* srl_name = "\u0/slt5_r_reg[17]_srl18___u0_slt5_r_reg_r_16 " *) + SRLC32E \u0/slt5_r_reg[17]_srl18___u0_slt5_r_reg_r_16 + (.A({\ ,\ ,\ ,\ ,\ }), + .CE(\ ), + .CLK(bit_clk_pad_i), + .D(\u0/slt6_r [19]), + .Q(\u0/slt5_r_reg[17]_srl18___u0_slt5_r_reg_r_16_n_0 )); + FDRE \u0/slt5_r_reg[18]_u0_slt5_r_reg_r_17 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg[17]_srl18___u0_slt5_r_reg_r_16_n_0 ), + .Q(\u0/slt5_r_reg[18]_u0_slt5_r_reg_r_17_n_0 ), + .R(\ )); + FDRE \u0/slt5_r_reg[19] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_gate_n_0 ), + .Q(\u0/slt5_r ), + .R(ld)); + LUT2 #( + .INIT(4'h8)) + \u0/slt5_r_reg_gate + (.I0(\u0/slt5_r_reg[18]_u0_slt5_r_reg_r_17_n_0 ), + .I1(\u0/slt5_r_reg_r_17_n_0 ), + .O(\u0/slt5_r_reg_gate_n_0 )); + FDRE \u0/slt5_r_reg_r + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\ ), + .Q(\u0/slt5_r_reg_r_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_0 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_n_0 ), + .Q(\u0/slt5_r_reg_r_0_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_1 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_0_n_0 ), + .Q(\u0/slt5_r_reg_r_1_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_10 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_9_n_0 ), + .Q(\u0/slt5_r_reg_r_10_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_11 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_10_n_0 ), + .Q(\u0/slt5_r_reg_r_11_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_12 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_11_n_0 ), + .Q(\u0/slt5_r_reg_r_12_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_13 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_12_n_0 ), + .Q(\u0/slt5_r_reg_r_13_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_14 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_13_n_0 ), + .Q(\u0/slt5_r_reg_r_14_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_15 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_14_n_0 ), + .Q(\u0/slt5_r_reg_r_15_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_16 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_15_n_0 ), + .Q(\u0/slt5_r_reg_r_16_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_17 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_16_n_0 ), + .Q(\u0/slt5_r_reg_r_17_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_2 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_1_n_0 ), + .Q(\u0/slt5_r_reg_r_2_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_3 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_2_n_0 ), + .Q(\u0/slt5_r_reg_r_3_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_4 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_3_n_0 ), + .Q(\u0/slt5_r_reg_r_4_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_5 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_4_n_0 ), + .Q(\u0/slt5_r_reg_r_5_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_6 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_5_n_0 ), + .Q(\u0/slt5_r_reg_r_6_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_7 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_6_n_0 ), + .Q(\u0/slt5_r_reg_r_7_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_8 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_7_n_0 ), + .Q(\u0/slt5_r_reg_r_8_n_0 ), + .R(ld)); + FDRE \u0/slt5_r_reg_r_9 + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/slt5_r_reg_r_8_n_0 ), + .Q(\u0/slt5_r_reg_r_9_n_0 ), + .R(ld)); + FDRE \u0/slt6_r_reg[0] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[0]_i_1_n_0 ), + .Q(\u0/slt6_r [0]), + .R(\ )); + FDRE \u0/slt6_r_reg[10] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[10]_i_1_n_0 ), + .Q(\u0/slt6_r [10]), + .R(\ )); + FDRE \u0/slt6_r_reg[11] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[11]_i_1_n_0 ), + .Q(\u0/slt6_r [11]), + .R(\ )); + FDRE \u0/slt6_r_reg[12] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[12]_i_1_n_0 ), + .Q(\u0/slt6_r [12]), + .R(\ )); + FDRE \u0/slt6_r_reg[13] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[13]_i_1_n_0 ), + .Q(\u0/slt6_r [13]), + .R(\ )); + FDRE \u0/slt6_r_reg[14] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[14]_i_1_n_0 ), + .Q(\u0/slt6_r [14]), + .R(\ )); + FDRE \u0/slt6_r_reg[15] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[15]_i_1_n_0 ), + .Q(\u0/slt6_r [15]), + .R(\ )); + FDRE \u0/slt6_r_reg[16] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[16]_i_1_n_0 ), + .Q(\u0/slt6_r [16]), + .R(\ )); + FDRE \u0/slt6_r_reg[17] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[17]_i_1_n_0 ), + .Q(\u0/slt6_r [17]), + .R(\ )); + FDRE \u0/slt6_r_reg[18] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[18]_i_1_n_0 ), + .Q(\u0/slt6_r [18]), + .R(\ )); + FDRE \u0/slt6_r_reg[19] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[19]_i_1_n_0 ), + .Q(\u0/slt6_r [19]), + .R(\ )); + FDRE \u0/slt6_r_reg[1] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[1]_i_1_n_0 ), + .Q(\u0/slt6_r [1]), + .R(\ )); + FDRE \u0/slt6_r_reg[2] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[2]_i_1_n_0 ), + .Q(\u0/slt6_r [2]), + .R(\ )); + FDRE \u0/slt6_r_reg[3] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[3]_i_1_n_0 ), + .Q(\u0/slt6_r [3]), + .R(\ )); + FDRE \u0/slt6_r_reg[4] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[4]_i_1_n_0 ), + .Q(\u0/slt6_r [4]), + .R(\ )); + FDRE \u0/slt6_r_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[5]_i_1_n_0 ), + .Q(\u0/slt6_r [5]), + .R(\ )); + FDRE \u0/slt6_r_reg[6] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[6]_i_1_n_0 ), + .Q(\u0/slt6_r [6]), + .R(\ )); + FDRE \u0/slt6_r_reg[7] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[7]_i_1_n_0 ), + .Q(\u0/slt6_r [7]), + .R(\ )); + FDRE \u0/slt6_r_reg[8] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[8]_i_1_n_0 ), + .Q(\u0/slt6_r [8]), + .R(\ )); + FDRE \u0/slt6_r_reg[9] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt6_r[9]_i_1_n_0 ), + .Q(\u0/slt6_r [9]), + .R(\ )); + FDRE \u0/slt7_r_reg[0] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[0]_i_1_n_0 ), + .Q(\u0/slt7_r [0]), + .R(\ )); + FDRE \u0/slt7_r_reg[10] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[10]_i_1_n_0 ), + .Q(\u0/slt7_r [10]), + .R(\ )); + FDRE \u0/slt7_r_reg[11] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[11]_i_1_n_0 ), + .Q(\u0/slt7_r [11]), + .R(\ )); + FDRE \u0/slt7_r_reg[12] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[12]_i_1_n_0 ), + .Q(\u0/slt7_r [12]), + .R(\ )); + FDRE \u0/slt7_r_reg[13] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[13]_i_1_n_0 ), + .Q(\u0/slt7_r [13]), + .R(\ )); + FDRE \u0/slt7_r_reg[14] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[14]_i_1_n_0 ), + .Q(\u0/slt7_r [14]), + .R(\ )); + FDRE \u0/slt7_r_reg[15] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[15]_i_1_n_0 ), + .Q(\u0/slt7_r [15]), + .R(\ )); + FDRE \u0/slt7_r_reg[16] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[16]_i_1_n_0 ), + .Q(\u0/slt7_r [16]), + .R(\ )); + FDRE \u0/slt7_r_reg[17] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[17]_i_1_n_0 ), + .Q(\u0/slt7_r [17]), + .R(\ )); + FDRE \u0/slt7_r_reg[18] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[18]_i_1_n_0 ), + .Q(\u0/slt7_r [18]), + .R(\ )); + FDRE \u0/slt7_r_reg[19] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[19]_i_1_n_0 ), + .Q(\u0/slt7_r [19]), + .R(\ )); + FDRE \u0/slt7_r_reg[1] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[1]_i_1_n_0 ), + .Q(\u0/slt7_r [1]), + .R(\ )); + FDRE \u0/slt7_r_reg[2] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[2]_i_1_n_0 ), + .Q(\u0/slt7_r [2]), + .R(\ )); + FDRE \u0/slt7_r_reg[3] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[3]_i_1_n_0 ), + .Q(\u0/slt7_r [3]), + .R(\ )); + FDRE \u0/slt7_r_reg[4] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[4]_i_1_n_0 ), + .Q(\u0/slt7_r [4]), + .R(\ )); + FDRE \u0/slt7_r_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[5]_i_1_n_0 ), + .Q(\u0/slt7_r [5]), + .R(\ )); + FDRE \u0/slt7_r_reg[6] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[6]_i_1_n_0 ), + .Q(\u0/slt7_r [6]), + .R(\ )); + FDRE \u0/slt7_r_reg[7] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[7]_i_1_n_0 ), + .Q(\u0/slt7_r [7]), + .R(\ )); + FDRE \u0/slt7_r_reg[8] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[8]_i_1_n_0 ), + .Q(\u0/slt7_r [8]), + .R(\ )); + FDRE \u0/slt7_r_reg[9] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt7_r[9]_i_1_n_0 ), + .Q(\u0/slt7_r [9]), + .R(\ )); + FDRE \u0/slt8_r_reg[0] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[0]_i_1_n_0 ), + .Q(\u0/slt8_r [0]), + .R(\ )); + FDRE \u0/slt8_r_reg[10] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[10]_i_1_n_0 ), + .Q(\u0/slt8_r [10]), + .R(\ )); + FDRE \u0/slt8_r_reg[11] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[11]_i_1_n_0 ), + .Q(\u0/slt8_r [11]), + .R(\ )); + FDRE \u0/slt8_r_reg[12] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[12]_i_1_n_0 ), + .Q(\u0/slt8_r [12]), + .R(\ )); + FDRE \u0/slt8_r_reg[13] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[13]_i_1_n_0 ), + .Q(\u0/slt8_r [13]), + .R(\ )); + FDRE \u0/slt8_r_reg[14] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[14]_i_1_n_0 ), + .Q(\u0/slt8_r [14]), + .R(\ )); + FDRE \u0/slt8_r_reg[15] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[15]_i_1_n_0 ), + .Q(\u0/slt8_r [15]), + .R(\ )); + FDRE \u0/slt8_r_reg[16] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[16]_i_1_n_0 ), + .Q(\u0/slt8_r [16]), + .R(\ )); + FDRE \u0/slt8_r_reg[17] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[17]_i_1_n_0 ), + .Q(\u0/slt8_r [17]), + .R(\ )); + FDRE \u0/slt8_r_reg[18] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[18]_i_1_n_0 ), + .Q(\u0/slt8_r [18]), + .R(\ )); + FDRE \u0/slt8_r_reg[19] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[19]_i_1_n_0 ), + .Q(\u0/slt8_r [19]), + .R(\ )); + FDRE \u0/slt8_r_reg[1] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[1]_i_1_n_0 ), + .Q(\u0/slt8_r [1]), + .R(\ )); + FDRE \u0/slt8_r_reg[2] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[2]_i_1_n_0 ), + .Q(\u0/slt8_r [2]), + .R(\ )); + FDRE \u0/slt8_r_reg[3] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[3]_i_1_n_0 ), + .Q(\u0/slt8_r [3]), + .R(\ )); + FDRE \u0/slt8_r_reg[4] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[4]_i_1_n_0 ), + .Q(\u0/slt8_r [4]), + .R(\ )); + FDRE \u0/slt8_r_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[5]_i_1_n_0 ), + .Q(\u0/slt8_r [5]), + .R(\ )); + FDRE \u0/slt8_r_reg[6] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[6]_i_1_n_0 ), + .Q(\u0/slt8_r [6]), + .R(\ )); + FDRE \u0/slt8_r_reg[7] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[7]_i_1_n_0 ), + .Q(\u0/slt8_r [7]), + .R(\ )); + FDRE \u0/slt8_r_reg[8] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[8]_i_1_n_0 ), + .Q(\u0/slt8_r [8]), + .R(\ )); + FDRE \u0/slt8_r_reg[9] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt8_r[9]_i_1_n_0 ), + .Q(\u0/slt8_r [9]), + .R(\ )); + FDRE \u0/slt9_r_reg[0] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\slt9_r[0]_i_1_n_0 ), + .Q(\u0/slt9_r [0]), + .R(\ )); + FDRE \u0/slt9_r_reg[10] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [10]), + .Q(\u0/slt9_r [10]), + .R(\ )); + FDRE \u0/slt9_r_reg[11] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [11]), + .Q(\u0/slt9_r [11]), + .R(\ )); + FDRE \u0/slt9_r_reg[12] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [12]), + .Q(\u0/slt9_r [12]), + .R(\ )); + FDRE \u0/slt9_r_reg[13] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [13]), + .Q(\u0/slt9_r [13]), + .R(\ )); + FDRE \u0/slt9_r_reg[14] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [14]), + .Q(\u0/slt9_r [14]), + .R(\ )); + FDRE \u0/slt9_r_reg[15] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [15]), + .Q(\u0/slt9_r [15]), + .R(\ )); + FDRE \u0/slt9_r_reg[16] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [16]), + .Q(\u0/slt9_r [16]), + .R(\ )); + FDRE \u0/slt9_r_reg[17] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [17]), + .Q(\u0/slt9_r [17]), + .R(\ )); + FDRE \u0/slt9_r_reg[18] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [18]), + .Q(\u0/slt9_r [18]), + .R(\ )); + FDRE \u0/slt9_r_reg[19] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [19]), + .Q(\u0/slt9_r [19]), + .R(\ )); + FDRE \u0/slt9_r_reg[1] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [1]), + .Q(\u0/slt9_r [1]), + .R(\ )); + FDRE \u0/slt9_r_reg[2] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [2]), + .Q(\u0/slt9_r [2]), + .R(\ )); + FDRE \u0/slt9_r_reg[3] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [3]), + .Q(\u0/slt9_r [3]), + .R(\ )); + FDRE \u0/slt9_r_reg[4] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [4]), + .Q(\u0/slt9_r [4]), + .R(\ )); + FDRE \u0/slt9_r_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [5]), + .Q(\u0/slt9_r [5]), + .R(\ )); + FDRE \u0/slt9_r_reg[6] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [6]), + .Q(\u0/slt9_r [6]), + .R(\ )); + FDRE \u0/slt9_r_reg[7] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [7]), + .Q(\u0/slt9_r [7]), + .R(\ )); + FDRE \u0/slt9_r_reg[8] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [8]), + .Q(\u0/slt9_r [8]), + .R(\ )); + FDRE \u0/slt9_r_reg[9] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u0/p_0_in [9]), + .Q(\u0/slt9_r [9]), + .R(\ )); + FDRE #( + .IS_C_INVERTED(1'b1)) + \u1/sdata_in_r_reg + (.C(bit_clk_pad_i), + .CE(\ ), + .D(sdata_pad_i), + .Q(p_0_in[0]), + .R(\ )); + FDRE \u1/slt0_reg[11] + (.C(bit_clk_pad_i), + .CE(out_le[0]), + .D(p_0_in[12]), + .Q(in_slt0[11]), + .R(\ )); + FDRE \u1/slt0_reg[12] + (.C(bit_clk_pad_i), + .CE(out_le[0]), + .D(p_0_in[13]), + .Q(in_slt0[12]), + .R(\ )); + FDRE \u1/slt0_reg[15] + (.C(bit_clk_pad_i), + .CE(out_le[0]), + .D(p_0_in[16]), + .Q(in_slt0[15]), + .R(\ )); + FDRE \u1/slt0_reg[9] + (.C(bit_clk_pad_i), + .CE(out_le[0]), + .D(p_0_in[10]), + .Q(in_slt0[9]), + .R(\ )); + FDRE \u1/slt1_reg[10] + (.C(bit_clk_pad_i), + .CE(out_le[1]), + .D(p_0_in[11]), + .Q(in_slt1[10]), + .R(\ )); + FDRE \u1/slt1_reg[11] + (.C(bit_clk_pad_i), + .CE(out_le[1]), + .D(p_0_in[12]), + .Q(in_slt1[11]), + .R(\ )); + FDRE \u1/slt1_reg[5] + (.C(bit_clk_pad_i), + .CE(out_le[1]), + .D(p_0_in[6]), + .Q(in_slt1[5]), + .R(\ )); + FDRE \u1/slt1_reg[6] + (.C(bit_clk_pad_i), + .CE(out_le[1]), + .D(p_0_in[7]), + .Q(in_slt1[6]), + .R(\ )); + FDRE \u1/slt1_reg[7] + (.C(bit_clk_pad_i), + .CE(out_le[1]), + .D(p_0_in[8]), + .Q(in_slt1[7]), + .R(\ )); + FDRE \u1/slt1_reg[8] + (.C(bit_clk_pad_i), + .CE(out_le[1]), + .D(p_0_in[9]), + .Q(in_slt1[8]), + .R(\ )); + FDRE \u1/slt2_reg[10] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[11]), + .Q(in_slt2[10]), + .R(\ )); + FDRE \u1/slt2_reg[11] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[12]), + .Q(in_slt2[11]), + .R(\ )); + FDRE \u1/slt2_reg[12] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[13]), + .Q(in_slt2[12]), + .R(\ )); + FDRE \u1/slt2_reg[13] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[14]), + .Q(in_slt2[13]), + .R(\ )); + FDRE \u1/slt2_reg[14] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[15]), + .Q(in_slt2[14]), + .R(\ )); + FDRE \u1/slt2_reg[15] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[16]), + .Q(in_slt2[15]), + .R(\ )); + FDRE \u1/slt2_reg[16] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[17]), + .Q(in_slt2[16]), + .R(\ )); + FDRE \u1/slt2_reg[17] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[18]), + .Q(in_slt2[17]), + .R(\ )); + FDRE \u1/slt2_reg[18] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[19]), + .Q(in_slt2[18]), + .R(\ )); + FDRE \u1/slt2_reg[19] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(\u1/sr_reg_n_0_[19] ), + .Q(in_slt2[19]), + .R(\ )); + FDRE \u1/slt2_reg[4] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[5]), + .Q(in_slt2[4]), + .R(\ )); + FDRE \u1/slt2_reg[5] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[6]), + .Q(in_slt2[5]), + .R(\ )); + FDRE \u1/slt2_reg[6] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[7]), + .Q(in_slt2[6]), + .R(\ )); + FDRE \u1/slt2_reg[7] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[8]), + .Q(in_slt2[7]), + .R(\ )); + FDRE \u1/slt2_reg[8] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[9]), + .Q(in_slt2[8]), + .R(\ )); + FDRE \u1/slt2_reg[9] + (.C(bit_clk_pad_i), + .CE(out_le[2]), + .D(p_0_in[10]), + .Q(in_slt2[9]), + .R(\ )); + FDRE \u1/slt3_reg[0] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[1]), + .Q(in_slt3[0]), + .R(\ )); + FDRE \u1/slt3_reg[10] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[11]), + .Q(in_slt3[10]), + .R(\ )); + FDRE \u1/slt3_reg[11] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[12]), + .Q(in_slt3[11]), + .R(\ )); + FDRE \u1/slt3_reg[12] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[13]), + .Q(in_slt3[12]), + .R(\ )); + FDRE \u1/slt3_reg[13] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[14]), + .Q(in_slt3[13]), + .R(\ )); + FDRE \u1/slt3_reg[14] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[15]), + .Q(in_slt3[14]), + .R(\ )); + FDRE \u1/slt3_reg[15] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[16]), + .Q(in_slt3[15]), + .R(\ )); + FDRE \u1/slt3_reg[16] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[17]), + .Q(in_slt3[16]), + .R(\ )); + FDRE \u1/slt3_reg[17] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[18]), + .Q(in_slt3[17]), + .R(\ )); + FDRE \u1/slt3_reg[18] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[19]), + .Q(in_slt3[18]), + .R(\ )); + FDRE \u1/slt3_reg[19] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(\u1/sr_reg_n_0_[19] ), + .Q(in_slt3[19]), + .R(\ )); + FDRE \u1/slt3_reg[1] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[2]), + .Q(in_slt3[1]), + .R(\ )); + FDRE \u1/slt3_reg[2] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[3]), + .Q(in_slt3[2]), + .R(\ )); + FDRE \u1/slt3_reg[3] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[4]), + .Q(in_slt3[3]), + .R(\ )); + FDRE \u1/slt3_reg[4] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[5]), + .Q(in_slt3[4]), + .R(\ )); + FDRE \u1/slt3_reg[5] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[6]), + .Q(in_slt3[5]), + .R(\ )); + FDRE \u1/slt3_reg[6] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[7]), + .Q(in_slt3[6]), + .R(\ )); + FDRE \u1/slt3_reg[7] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[8]), + .Q(in_slt3[7]), + .R(\ )); + FDRE \u1/slt3_reg[8] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[9]), + .Q(in_slt3[8]), + .R(\ )); + FDRE \u1/slt3_reg[9] + (.C(bit_clk_pad_i), + .CE(out_le[3]), + .D(p_0_in[10]), + .Q(in_slt3[9]), + .R(\ )); + FDRE \u1/slt4_reg[0] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[1]), + .Q(in_slt4[0]), + .R(\ )); + FDRE \u1/slt4_reg[10] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[11]), + .Q(in_slt4[10]), + .R(\ )); + FDRE \u1/slt4_reg[11] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[12]), + .Q(in_slt4[11]), + .R(\ )); + FDRE \u1/slt4_reg[12] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[13]), + .Q(in_slt4[12]), + .R(\ )); + FDRE \u1/slt4_reg[13] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[14]), + .Q(in_slt4[13]), + .R(\ )); + FDRE \u1/slt4_reg[14] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[15]), + .Q(in_slt4[14]), + .R(\ )); + FDRE \u1/slt4_reg[15] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[16]), + .Q(in_slt4[15]), + .R(\ )); + FDRE \u1/slt4_reg[16] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[17]), + .Q(in_slt4[16]), + .R(\ )); + FDRE \u1/slt4_reg[17] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[18]), + .Q(in_slt4[17]), + .R(\ )); + FDRE \u1/slt4_reg[18] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[19]), + .Q(in_slt4[18]), + .R(\ )); + FDRE \u1/slt4_reg[19] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(\u1/sr_reg_n_0_[19] ), + .Q(in_slt4[19]), + .R(\ )); + FDRE \u1/slt4_reg[1] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[2]), + .Q(in_slt4[1]), + .R(\ )); + FDRE \u1/slt4_reg[2] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[3]), + .Q(in_slt4[2]), + .R(\ )); + FDRE \u1/slt4_reg[3] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[4]), + .Q(in_slt4[3]), + .R(\ )); + FDRE \u1/slt4_reg[4] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[5]), + .Q(in_slt4[4]), + .R(\ )); + FDRE \u1/slt4_reg[5] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[6]), + .Q(in_slt4[5]), + .R(\ )); + FDRE \u1/slt4_reg[6] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[7]), + .Q(in_slt4[6]), + .R(\ )); + FDRE \u1/slt4_reg[7] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[8]), + .Q(in_slt4[7]), + .R(\ )); + FDRE \u1/slt4_reg[8] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[9]), + .Q(in_slt4[8]), + .R(\ )); + FDRE \u1/slt4_reg[9] + (.C(bit_clk_pad_i), + .CE(out_le[4]), + .D(p_0_in[10]), + .Q(in_slt4[9]), + .R(\ )); + FDRE \u1/slt6_reg[0] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[1]), + .Q(in_slt6[0]), + .R(\ )); + FDRE \u1/slt6_reg[10] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[11]), + .Q(in_slt6[10]), + .R(\ )); + FDRE \u1/slt6_reg[11] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[12]), + .Q(in_slt6[11]), + .R(\ )); + FDRE \u1/slt6_reg[12] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[13]), + .Q(in_slt6[12]), + .R(\ )); + FDRE \u1/slt6_reg[13] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[14]), + .Q(in_slt6[13]), + .R(\ )); + FDRE \u1/slt6_reg[14] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[15]), + .Q(in_slt6[14]), + .R(\ )); + FDRE \u1/slt6_reg[15] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[16]), + .Q(in_slt6[15]), + .R(\ )); + FDRE \u1/slt6_reg[16] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[17]), + .Q(in_slt6[16]), + .R(\ )); + FDRE \u1/slt6_reg[17] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[18]), + .Q(in_slt6[17]), + .R(\ )); + FDRE \u1/slt6_reg[18] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[19]), + .Q(in_slt6[18]), + .R(\ )); + FDRE \u1/slt6_reg[19] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(\u1/sr_reg_n_0_[19] ), + .Q(in_slt6[19]), + .R(\ )); + FDRE \u1/slt6_reg[1] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[2]), + .Q(in_slt6[1]), + .R(\ )); + FDRE \u1/slt6_reg[2] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[3]), + .Q(in_slt6[2]), + .R(\ )); + FDRE \u1/slt6_reg[3] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[4]), + .Q(in_slt6[3]), + .R(\ )); + FDRE \u1/slt6_reg[4] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[5]), + .Q(in_slt6[4]), + .R(\ )); + FDRE \u1/slt6_reg[5] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[6]), + .Q(in_slt6[5]), + .R(\ )); + FDRE \u1/slt6_reg[6] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[7]), + .Q(in_slt6[6]), + .R(\ )); + FDRE \u1/slt6_reg[7] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[8]), + .Q(in_slt6[7]), + .R(\ )); + FDRE \u1/slt6_reg[8] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[9]), + .Q(in_slt6[8]), + .R(\ )); + FDRE \u1/slt6_reg[9] + (.C(bit_clk_pad_i), + .CE(out_le[5]), + .D(p_0_in[10]), + .Q(in_slt6[9]), + .R(\ )); + FDRE \u1/sr_reg[0] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[0]), + .Q(p_0_in[1]), + .R(\ )); + FDRE \u1/sr_reg[10] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[10]), + .Q(p_0_in[11]), + .R(\ )); + FDRE \u1/sr_reg[11] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[11]), + .Q(p_0_in[12]), + .R(\ )); + FDRE \u1/sr_reg[12] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[12]), + .Q(p_0_in[13]), + .R(\ )); + FDRE \u1/sr_reg[13] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[13]), + .Q(p_0_in[14]), + .R(\ )); + FDRE \u1/sr_reg[14] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[14]), + .Q(p_0_in[15]), + .R(\ )); + FDRE \u1/sr_reg[15] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[15]), + .Q(p_0_in[16]), + .R(\ )); + FDRE \u1/sr_reg[16] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[16]), + .Q(p_0_in[17]), + .R(\ )); + FDRE \u1/sr_reg[17] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[17]), + .Q(p_0_in[18]), + .R(\ )); + FDRE \u1/sr_reg[18] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[18]), + .Q(p_0_in[19]), + .R(\ )); + FDRE \u1/sr_reg[19] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[19]), + .Q(\u1/sr_reg_n_0_[19] ), + .R(\ )); + FDRE \u1/sr_reg[1] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[1]), + .Q(p_0_in[2]), + .R(\ )); + FDRE \u1/sr_reg[2] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[2]), + .Q(p_0_in[3]), + .R(\ )); + FDRE \u1/sr_reg[3] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[3]), + .Q(p_0_in[4]), + .R(\ )); + FDRE \u1/sr_reg[4] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[4]), + .Q(p_0_in[5]), + .R(\ )); + FDRE \u1/sr_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[5]), + .Q(p_0_in[6]), + .R(\ )); + FDRE \u1/sr_reg[6] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[6]), + .Q(p_0_in[7]), + .R(\ )); + FDRE \u1/sr_reg[7] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[7]), + .Q(p_0_in[8]), + .R(\ )); + FDRE \u1/sr_reg[8] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[8]), + .Q(p_0_in[9]), + .R(\ )); + FDRE \u1/sr_reg[9] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in[9]), + .Q(p_0_in[10]), + .R(\ )); + FDRE \u10/din_tmp1_reg[0] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[4]), + .Q(\u10/din_tmp1 [0]), + .R(\ )); + FDRE \u10/din_tmp1_reg[10] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[14]), + .Q(\u10/din_tmp1 [10]), + .R(\ )); + FDRE \u10/din_tmp1_reg[11] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[15]), + .Q(\u10/din_tmp1 [11]), + .R(\ )); + FDRE \u10/din_tmp1_reg[12] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[16]), + .Q(\u10/din_tmp1 [12]), + .R(\ )); + FDRE \u10/din_tmp1_reg[13] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[17]), + .Q(\u10/din_tmp1 [13]), + .R(\ )); + FDRE \u10/din_tmp1_reg[14] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[18]), + .Q(\u10/din_tmp1 [14]), + .R(\ )); + FDRE \u10/din_tmp1_reg[15] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[19]), + .Q(\u10/din_tmp1 [15]), + .R(\ )); + FDRE \u10/din_tmp1_reg[1] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[5]), + .Q(\u10/din_tmp1 [1]), + .R(\ )); + FDRE \u10/din_tmp1_reg[2] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[6]), + .Q(\u10/din_tmp1 [2]), + .R(\ )); + FDRE \u10/din_tmp1_reg[3] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[7]), + .Q(\u10/din_tmp1 [3]), + .R(\ )); + FDRE \u10/din_tmp1_reg[4] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[8]), + .Q(\u10/din_tmp1 [4]), + .R(\ )); + FDRE \u10/din_tmp1_reg[5] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[9]), + .Q(\u10/din_tmp1 [5]), + .R(\ )); + FDRE \u10/din_tmp1_reg[6] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[10]), + .Q(\u10/din_tmp1 [6]), + .R(\ )); + FDRE \u10/din_tmp1_reg[7] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[11]), + .Q(\u10/din_tmp1 [7]), + .R(\ )); + FDRE \u10/din_tmp1_reg[8] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[12]), + .Q(\u10/din_tmp1 [8]), + .R(\ )); + FDRE \u10/din_tmp1_reg[9] + (.C(clk_i), + .CE(\u10/din_tmp10 ), + .D(in_slt4[13]), + .Q(\u10/din_tmp1 [9]), + .R(\ )); + FDRE \u10/dout_reg[0] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[0]), + .Q(i4_dout[0]), + .R(\ )); + FDRE \u10/dout_reg[10] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[10]), + .Q(i4_dout[10]), + .R(\ )); + FDRE \u10/dout_reg[11] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[11]), + .Q(i4_dout[11]), + .R(\ )); + FDRE \u10/dout_reg[12] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[12]), + .Q(i4_dout[12]), + .R(\ )); + FDRE \u10/dout_reg[13] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[13]), + .Q(i4_dout[13]), + .R(\ )); + FDRE \u10/dout_reg[14] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[14]), + .Q(i4_dout[14]), + .R(\ )); + FDRE \u10/dout_reg[15] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[15]), + .Q(i4_dout[15]), + .R(\ )); + FDRE \u10/dout_reg[16] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[16]), + .Q(i4_dout[16]), + .R(\ )); + FDRE \u10/dout_reg[17] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[17]), + .Q(i4_dout[17]), + .R(\ )); + FDRE \u10/dout_reg[18] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[18]), + .Q(i4_dout[18]), + .R(\ )); + FDRE \u10/dout_reg[19] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[19]), + .Q(i4_dout[19]), + .R(\ )); + FDRE \u10/dout_reg[1] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[1]), + .Q(i4_dout[1]), + .R(\ )); + FDRE \u10/dout_reg[20] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[20]), + .Q(i4_dout[20]), + .R(\ )); + FDRE \u10/dout_reg[21] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[21]), + .Q(i4_dout[21]), + .R(\ )); + FDRE \u10/dout_reg[22] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[22]), + .Q(i4_dout[22]), + .R(\ )); + FDRE \u10/dout_reg[23] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[23]), + .Q(i4_dout[23]), + .R(\ )); + FDRE \u10/dout_reg[24] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[24]), + .Q(i4_dout[24]), + .R(\ )); + FDRE \u10/dout_reg[25] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[25]), + .Q(i4_dout[25]), + .R(\ )); + FDRE \u10/dout_reg[26] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[26]), + .Q(i4_dout[26]), + .R(\ )); + FDRE \u10/dout_reg[27] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[27]), + .Q(i4_dout[27]), + .R(\ )); + FDRE \u10/dout_reg[28] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[28]), + .Q(i4_dout[28]), + .R(\ )); + FDRE \u10/dout_reg[29] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[29]), + .Q(i4_dout[29]), + .R(\ )); + FDRE \u10/dout_reg[2] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[2]), + .Q(i4_dout[2]), + .R(\ )); + FDRE \u10/dout_reg[30] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[30]), + .Q(i4_dout[30]), + .R(\ )); + FDRE \u10/dout_reg[31] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[31]), + .Q(i4_dout[31]), + .R(\ )); + FDRE \u10/dout_reg[3] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[3]), + .Q(i4_dout[3]), + .R(\ )); + FDRE \u10/dout_reg[4] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[4]), + .Q(i4_dout[4]), + .R(\ )); + FDRE \u10/dout_reg[5] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[5]), + .Q(i4_dout[5]), + .R(\ )); + FDRE \u10/dout_reg[6] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[6]), + .Q(i4_dout[6]), + .R(\ )); + FDRE \u10/dout_reg[7] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[7]), + .Q(i4_dout[7]), + .R(\ )); + FDRE \u10/dout_reg[8] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[8]), + .Q(i4_dout[8]), + .R(\ )); + FDRE \u10/dout_reg[9] + (.C(clk_i), + .CE(\ ), + .D(dout0__0[9]), + .Q(i4_dout[9]), + .R(\ )); + FDRE \u10/empty_reg + (.C(clk_i), + .CE(\ ), + .D(\u10/empty0 ), + .Q(i4_empty), + .R(\ )); + FDRE \u10/full_reg + (.C(clk_i), + .CE(\ ), + .D(\u10/full0 ), + .Q(i4_full), + .R(\ )); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u10/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "0" *) + (* ram_slice_end = "5" *) + RAM32M \u10/mem_reg_0_3_0_5 + (.ADDRA({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u10/p_1_in }), + .DIA(\u10/din_tmp [1:0]), + .DIB(\u10/din_tmp [3:2]), + .DIC(\u10/din_tmp [5:4]), + .DID({\ ,\ }), + .DOA(dout0__0[1:0]), + .DOB(dout0__0[3:2]), + .DOC(dout0__0[5:4]), + .WCLK(clk_i), + .WE(p_0_in__1)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u10/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "12" *) + (* ram_slice_end = "17" *) + RAM32M \u10/mem_reg_0_3_12_17 + (.ADDRA({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u10/p_1_in }), + .DIA(\u10/din_tmp [13:12]), + .DIB(\u10/din_tmp [15:14]), + .DIC(\u10/din_tmp [17:16]), + .DID({\ ,\ }), + .DOA(dout0__0[13:12]), + .DOB(dout0__0[15:14]), + .DOC(dout0__0[17:16]), + .WCLK(clk_i), + .WE(p_0_in__1)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u10/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "18" *) + (* ram_slice_end = "23" *) + RAM32M \u10/mem_reg_0_3_18_23 + (.ADDRA({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u10/p_1_in }), + .DIA(\u10/din_tmp [19:18]), + .DIB(\u10/din_tmp [21:20]), + .DIC(\u10/din_tmp [23:22]), + .DID({\ ,\ }), + .DOA(dout0__0[19:18]), + .DOB(dout0__0[21:20]), + .DOC(dout0__0[23:22]), + .WCLK(clk_i), + .WE(p_0_in__1)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u10/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "24" *) + (* ram_slice_end = "29" *) + RAM32M \u10/mem_reg_0_3_24_29 + (.ADDRA({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u10/p_1_in }), + .DIA(\u10/din_tmp [25:24]), + .DIB(\u10/din_tmp [27:26]), + .DIC(\u10/din_tmp [29:28]), + .DID({\ ,\ }), + .DOA(dout0__0[25:24]), + .DOB(dout0__0[27:26]), + .DOC(dout0__0[29:28]), + .WCLK(clk_i), + .WE(p_0_in__1)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u10/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u10/mem_reg_0_3_30_31 + (.A0(\u10/p_1_in [0]), + .A1(\u10/p_1_in [1]), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(\u10/din_tmp [30]), + .DPO(dout0__0[30]), + .DPRA0(\u10/rp_reg_n_0_[0] ), + .DPRA1(\u10/rp_reg_n_0_[1] ), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(p_0_in__1)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u10/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u10/mem_reg_0_3_30_31__0 + (.A0(\u10/p_1_in [0]), + .A1(\u10/p_1_in [1]), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(\u10/din_tmp [31]), + .DPO(dout0__0[31]), + .DPRA0(\u10/rp_reg_n_0_[0] ), + .DPRA1(\u10/rp_reg_n_0_[1] ), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(p_0_in__1)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u10/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "6" *) + (* ram_slice_end = "11" *) + RAM32M \u10/mem_reg_0_3_6_11 + (.ADDRA({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u10/rp_reg_n_0_[1] ,\u10/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u10/p_1_in }), + .DIA(\u10/din_tmp [7:6]), + .DIB(\u10/din_tmp [9:8]), + .DIC(\u10/din_tmp [11:10]), + .DID({\ ,\ }), + .DOA(dout0__0[7:6]), + .DOB(dout0__0[9:8]), + .DOC(dout0__0[11:10]), + .WCLK(clk_i), + .WE(p_0_in__1)); + FDRE \u10/rp_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\rp[0]_i_1__0_n_0 ), + .Q(\u10/rp_reg_n_0_[0] ), + .R(\ )); + FDRE \u10/rp_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\rp[1]_i_1__0_n_0 ), + .Q(\u10/rp_reg_n_0_[1] ), + .R(\ )); + FDRE \u10/rp_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\rp[2]_i_1__0_n_0 ), + .Q(\u10/rp_reg_n_0_[2] ), + .R(\ )); + FDRE \u10/status_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\status[0]_i_1__6_n_0 ), + .Q(i4_status[0]), + .R(\ )); + FDRE \u10/status_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u10/status0 ), + .Q(i4_status[1]), + .R(\ )); + FDRE \u10/wp_reg[0] + (.C(clk_i), + .CE(i4_we), + .D(\wp[0]_i_1__6_n_0 ), + .Q(\u10/wp_reg_n_0_[0] ), + .R(\wp[3]_i_1__0_n_0 )); + FDRE \u10/wp_reg[1] + (.C(clk_i), + .CE(i4_we), + .D(wp_p1__0[1]), + .Q(\u10/p_1_in [0]), + .R(\wp[3]_i_1__0_n_0 )); + FDRE \u10/wp_reg[2] + (.C(clk_i), + .CE(i4_we), + .D(wp_p1__0[2]), + .Q(\u10/p_1_in [1]), + .R(\wp[3]_i_1__0_n_0 )); + FDRE \u10/wp_reg[3] + (.C(clk_i), + .CE(i4_we), + .D(wp_p1__0[3]), + .Q(\u10/wp_reg_n_0_[3] ), + .R(\wp[3]_i_1__0_n_0 )); + FDRE \u11/din_tmp1_reg[0] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[4]), + .Q(\u11/din_tmp1 [0]), + .R(\ )); + FDRE \u11/din_tmp1_reg[10] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[14]), + .Q(\u11/din_tmp1 [10]), + .R(\ )); + FDRE \u11/din_tmp1_reg[11] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[15]), + .Q(\u11/din_tmp1 [11]), + .R(\ )); + FDRE \u11/din_tmp1_reg[12] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[16]), + .Q(\u11/din_tmp1 [12]), + .R(\ )); + FDRE \u11/din_tmp1_reg[13] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[17]), + .Q(\u11/din_tmp1 [13]), + .R(\ )); + FDRE \u11/din_tmp1_reg[14] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[18]), + .Q(\u11/din_tmp1 [14]), + .R(\ )); + FDRE \u11/din_tmp1_reg[15] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[19]), + .Q(\u11/din_tmp1 [15]), + .R(\ )); + FDRE \u11/din_tmp1_reg[1] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[5]), + .Q(\u11/din_tmp1 [1]), + .R(\ )); + FDRE \u11/din_tmp1_reg[2] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[6]), + .Q(\u11/din_tmp1 [2]), + .R(\ )); + FDRE \u11/din_tmp1_reg[3] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[7]), + .Q(\u11/din_tmp1 [3]), + .R(\ )); + FDRE \u11/din_tmp1_reg[4] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[8]), + .Q(\u11/din_tmp1 [4]), + .R(\ )); + FDRE \u11/din_tmp1_reg[5] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[9]), + .Q(\u11/din_tmp1 [5]), + .R(\ )); + FDRE \u11/din_tmp1_reg[6] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[10]), + .Q(\u11/din_tmp1 [6]), + .R(\ )); + FDRE \u11/din_tmp1_reg[7] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[11]), + .Q(\u11/din_tmp1 [7]), + .R(\ )); + FDRE \u11/din_tmp1_reg[8] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[12]), + .Q(\u11/din_tmp1 [8]), + .R(\ )); + FDRE \u11/din_tmp1_reg[9] + (.C(clk_i), + .CE(\u11/din_tmp10 ), + .D(in_slt6[13]), + .Q(\u11/din_tmp1 [9]), + .R(\ )); + FDRE \u11/dout_reg[0] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[0]), + .Q(i6_dout[0]), + .R(\ )); + FDRE \u11/dout_reg[10] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[10]), + .Q(i6_dout[10]), + .R(\ )); + FDRE \u11/dout_reg[11] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[11]), + .Q(i6_dout[11]), + .R(\ )); + FDRE \u11/dout_reg[12] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[12]), + .Q(i6_dout[12]), + .R(\ )); + FDRE \u11/dout_reg[13] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[13]), + .Q(i6_dout[13]), + .R(\ )); + FDRE \u11/dout_reg[14] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[14]), + .Q(i6_dout[14]), + .R(\ )); + FDRE \u11/dout_reg[15] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[15]), + .Q(i6_dout[15]), + .R(\ )); + FDRE \u11/dout_reg[16] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[16]), + .Q(i6_dout[16]), + .R(\ )); + FDRE \u11/dout_reg[17] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[17]), + .Q(i6_dout[17]), + .R(\ )); + FDRE \u11/dout_reg[18] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[18]), + .Q(i6_dout[18]), + .R(\ )); + FDRE \u11/dout_reg[19] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[19]), + .Q(i6_dout[19]), + .R(\ )); + FDRE \u11/dout_reg[1] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[1]), + .Q(i6_dout[1]), + .R(\ )); + FDRE \u11/dout_reg[20] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[20]), + .Q(i6_dout[20]), + .R(\ )); + FDRE \u11/dout_reg[21] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[21]), + .Q(i6_dout[21]), + .R(\ )); + FDRE \u11/dout_reg[22] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[22]), + .Q(i6_dout[22]), + .R(\ )); + FDRE \u11/dout_reg[23] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[23]), + .Q(i6_dout[23]), + .R(\ )); + FDRE \u11/dout_reg[24] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[24]), + .Q(i6_dout[24]), + .R(\ )); + FDRE \u11/dout_reg[25] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[25]), + .Q(i6_dout[25]), + .R(\ )); + FDRE \u11/dout_reg[26] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[26]), + .Q(i6_dout[26]), + .R(\ )); + FDRE \u11/dout_reg[27] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[27]), + .Q(i6_dout[27]), + .R(\ )); + FDRE \u11/dout_reg[28] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[28]), + .Q(i6_dout[28]), + .R(\ )); + FDRE \u11/dout_reg[29] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[29]), + .Q(i6_dout[29]), + .R(\ )); + FDRE \u11/dout_reg[2] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[2]), + .Q(i6_dout[2]), + .R(\ )); + FDRE \u11/dout_reg[30] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[30]), + .Q(i6_dout[30]), + .R(\ )); + FDRE \u11/dout_reg[31] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[31]), + .Q(i6_dout[31]), + .R(\ )); + FDRE \u11/dout_reg[3] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[3]), + .Q(i6_dout[3]), + .R(\ )); + FDRE \u11/dout_reg[4] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[4]), + .Q(i6_dout[4]), + .R(\ )); + FDRE \u11/dout_reg[5] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[5]), + .Q(i6_dout[5]), + .R(\ )); + FDRE \u11/dout_reg[6] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[6]), + .Q(i6_dout[6]), + .R(\ )); + FDRE \u11/dout_reg[7] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[7]), + .Q(i6_dout[7]), + .R(\ )); + FDRE \u11/dout_reg[8] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[8]), + .Q(i6_dout[8]), + .R(\ )); + FDRE \u11/dout_reg[9] + (.C(clk_i), + .CE(\ ), + .D(dout0__1[9]), + .Q(i6_dout[9]), + .R(\ )); + FDRE \u11/empty_reg + (.C(clk_i), + .CE(\ ), + .D(\u11/empty0 ), + .Q(i6_empty), + .R(\ )); + FDRE \u11/full_reg + (.C(clk_i), + .CE(\ ), + .D(\u11/full0 ), + .Q(i6_full), + .R(\ )); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u11/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "0" *) + (* ram_slice_end = "5" *) + RAM32M \u11/mem_reg_0_3_0_5 + (.ADDRA({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u11/p_1_in }), + .DIA(\u11/din_tmp [1:0]), + .DIB(\u11/din_tmp [3:2]), + .DIC(\u11/din_tmp [5:4]), + .DID({\ ,\ }), + .DOA(dout0__1[1:0]), + .DOB(dout0__1[3:2]), + .DOC(dout0__1[5:4]), + .WCLK(clk_i), + .WE(p_0_in__2)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u11/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "12" *) + (* ram_slice_end = "17" *) + RAM32M \u11/mem_reg_0_3_12_17 + (.ADDRA({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u11/p_1_in }), + .DIA(\u11/din_tmp [13:12]), + .DIB(\u11/din_tmp [15:14]), + .DIC(\u11/din_tmp [17:16]), + .DID({\ ,\ }), + .DOA(dout0__1[13:12]), + .DOB(dout0__1[15:14]), + .DOC(dout0__1[17:16]), + .WCLK(clk_i), + .WE(p_0_in__2)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u11/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "18" *) + (* ram_slice_end = "23" *) + RAM32M \u11/mem_reg_0_3_18_23 + (.ADDRA({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u11/p_1_in }), + .DIA(\u11/din_tmp [19:18]), + .DIB(\u11/din_tmp [21:20]), + .DIC(\u11/din_tmp [23:22]), + .DID({\ ,\ }), + .DOA(dout0__1[19:18]), + .DOB(dout0__1[21:20]), + .DOC(dout0__1[23:22]), + .WCLK(clk_i), + .WE(p_0_in__2)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u11/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "24" *) + (* ram_slice_end = "29" *) + RAM32M \u11/mem_reg_0_3_24_29 + (.ADDRA({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u11/p_1_in }), + .DIA(\u11/din_tmp [25:24]), + .DIB(\u11/din_tmp [27:26]), + .DIC(\u11/din_tmp [29:28]), + .DID({\ ,\ }), + .DOA(dout0__1[25:24]), + .DOB(dout0__1[27:26]), + .DOC(dout0__1[29:28]), + .WCLK(clk_i), + .WE(p_0_in__2)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u11/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u11/mem_reg_0_3_30_31 + (.A0(\u11/p_1_in [0]), + .A1(\u11/p_1_in [1]), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(\u11/din_tmp [30]), + .DPO(dout0__1[30]), + .DPRA0(\u11/rp_reg_n_0_[0] ), + .DPRA1(\u11/rp_reg_n_0_[1] ), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(p_0_in__2)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u11/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u11/mem_reg_0_3_30_31__0 + (.A0(\u11/p_1_in [0]), + .A1(\u11/p_1_in [1]), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(\u11/din_tmp [31]), + .DPO(dout0__1[31]), + .DPRA0(\u11/rp_reg_n_0_[0] ), + .DPRA1(\u11/rp_reg_n_0_[1] ), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(p_0_in__2)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u11/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "6" *) + (* ram_slice_end = "11" *) + RAM32M \u11/mem_reg_0_3_6_11 + (.ADDRA({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u11/rp_reg_n_0_[1] ,\u11/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u11/p_1_in }), + .DIA(\u11/din_tmp [7:6]), + .DIB(\u11/din_tmp [9:8]), + .DIC(\u11/din_tmp [11:10]), + .DID({\ ,\ }), + .DOA(dout0__1[7:6]), + .DOB(dout0__1[9:8]), + .DOC(dout0__1[11:10]), + .WCLK(clk_i), + .WE(p_0_in__2)); + FDRE \u11/rp_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\rp[0]_i_1__1_n_0 ), + .Q(\u11/rp_reg_n_0_[0] ), + .R(\ )); + FDRE \u11/rp_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\rp[1]_i_1__1_n_0 ), + .Q(\u11/rp_reg_n_0_[1] ), + .R(\ )); + FDRE \u11/rp_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\rp[2]_i_1__1_n_0 ), + .Q(\u11/rp_reg_n_0_[2] ), + .R(\ )); + FDRE \u11/status_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\status[0]_i_1__5_n_0 ), + .Q(i6_status[0]), + .R(\ )); + FDRE \u11/status_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u11/status0 ), + .Q(i6_status[1]), + .R(\ )); + FDRE \u11/wp_reg[0] + (.C(clk_i), + .CE(i6_we), + .D(\wp[0]_i_1__7_n_0 ), + .Q(\u11/wp_reg_n_0_[0] ), + .R(\wp[3]_i_1__1_n_0 )); + FDRE \u11/wp_reg[1] + (.C(clk_i), + .CE(i6_we), + .D(wp_p1__1[1]), + .Q(\u11/p_1_in [0]), + .R(\wp[3]_i_1__1_n_0 )); + FDRE \u11/wp_reg[2] + (.C(clk_i), + .CE(i6_we), + .D(wp_p1__1[2]), + .Q(\u11/p_1_in [1]), + .R(\wp[3]_i_1__1_n_0 )); + FDRE \u11/wp_reg[3] + (.C(clk_i), + .CE(i6_we), + .D(wp_p1__1[3]), + .Q(\u11/wp_reg_n_0_[3] ), + .R(\wp[3]_i_1__1_n_0 )); + FDRE \u12/dout_reg[0] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[0]), + .Q(wb_din[0]), + .R(\ )); + FDRE \u12/dout_reg[10] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[10]), + .Q(wb_din[10]), + .R(\ )); + FDRE \u12/dout_reg[11] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[11]), + .Q(wb_din[11]), + .R(\ )); + FDRE \u12/dout_reg[12] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[12]), + .Q(wb_din[12]), + .R(\ )); + FDRE \u12/dout_reg[13] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[13]), + .Q(wb_din[13]), + .R(\ )); + FDRE \u12/dout_reg[14] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[14]), + .Q(wb_din[14]), + .R(\ )); + FDRE \u12/dout_reg[15] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[15]), + .Q(wb_din[15]), + .R(\ )); + FDRE \u12/dout_reg[16] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[16]), + .Q(wb_din[16]), + .R(\ )); + FDRE \u12/dout_reg[17] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[17]), + .Q(wb_din[17]), + .R(\ )); + FDRE \u12/dout_reg[18] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[18]), + .Q(wb_din[18]), + .R(\ )); + FDRE \u12/dout_reg[19] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[19]), + .Q(wb_din[19]), + .R(\ )); + FDRE \u12/dout_reg[1] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[1]), + .Q(wb_din[1]), + .R(\ )); + FDRE \u12/dout_reg[20] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[20]), + .Q(wb_din[20]), + .R(\ )); + FDRE \u12/dout_reg[21] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[21]), + .Q(wb_din[21]), + .R(\ )); + FDRE \u12/dout_reg[22] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[22]), + .Q(wb_din[22]), + .R(\ )); + FDRE \u12/dout_reg[23] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[23]), + .Q(wb_din[23]), + .R(\ )); + FDRE \u12/dout_reg[24] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[24]), + .Q(wb_din[24]), + .R(\ )); + FDRE \u12/dout_reg[25] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[25]), + .Q(wb_din[25]), + .R(\ )); + FDRE \u12/dout_reg[26] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[26]), + .Q(wb_din[26]), + .R(\ )); + FDRE \u12/dout_reg[27] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[27]), + .Q(wb_din[27]), + .R(\ )); + FDRE \u12/dout_reg[28] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[28]), + .Q(wb_din[28]), + .R(\ )); + FDRE \u12/dout_reg[29] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[29]), + .Q(wb_din[29]), + .R(\ )); + FDRE \u12/dout_reg[2] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[2]), + .Q(wb_din[2]), + .R(\ )); + FDRE \u12/dout_reg[30] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[30]), + .Q(wb_din[30]), + .R(\ )); + FDRE \u12/dout_reg[31] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[31]), + .Q(wb_din[31]), + .R(\ )); + FDRE \u12/dout_reg[3] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[3]), + .Q(wb_din[3]), + .R(\ )); + FDRE \u12/dout_reg[4] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[4]), + .Q(wb_din[4]), + .R(\ )); + FDRE \u12/dout_reg[5] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[5]), + .Q(wb_din[5]), + .R(\ )); + FDRE \u12/dout_reg[6] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[6]), + .Q(wb_din[6]), + .R(\ )); + FDRE \u12/dout_reg[7] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[7]), + .Q(wb_din[7]), + .R(\ )); + FDRE \u12/dout_reg[8] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[8]), + .Q(wb_din[8]), + .R(\ )); + FDRE \u12/dout_reg[9] + (.C(clk_i), + .CE(\ ), + .D(wb_data_i[9]), + .Q(wb_din[9]), + .R(\ )); + FDRE \u12/i3_re_reg + (.C(clk_i), + .CE(\ ), + .D(\u12/i3_re0 ), + .Q(i3_re), + .R(\ )); + FDRE \u12/i4_re_reg + (.C(clk_i), + .CE(\ ), + .D(\u12/i4_re0 ), + .Q(i4_re), + .R(\ )); + FDRE \u12/i6_re_reg + (.C(clk_i), + .CE(\ ), + .D(\u12/i6_re0 ), + .Q(i6_re), + .R(\ )); + FDRE \u12/o3_we_reg + (.C(clk_i), + .CE(\ ), + .D(o3_we_i_2_n_0), + .Q(o3_we), + .R(o3_we_i_1_n_0)); + FDRE \u12/o4_we_reg + (.C(clk_i), + .CE(\ ), + .D(o4_we_i_1_n_0), + .Q(o4_we), + .R(o3_we_i_1_n_0)); + FDRE \u12/o6_we_reg + (.C(clk_i), + .CE(\ ), + .D(o6_we_i_1_n_0), + .Q(o6_we), + .R(o3_we_i_1_n_0)); + FDRE \u12/o7_we_reg + (.C(clk_i), + .CE(\ ), + .D(o7_we_i_1_n_0), + .Q(o7_we), + .R(o3_we_i_1_n_0)); + FDRE \u12/o8_we_reg + (.C(clk_i), + .CE(\ ), + .D(o8_we_i_1_n_0), + .Q(o8_we), + .R(o3_we_i_1_n_0)); + FDRE \u12/o9_we_reg + (.C(clk_i), + .CE(\ ), + .D(o9_we_i_1_n_0), + .Q(o9_we), + .R(o3_we_i_1_n_0)); + FDRE \u12/re1_reg + (.C(clk_i), + .CE(\ ), + .D(\u12/re10 ), + .Q(\u12/re1 ), + .R(\ )); + FDRE \u12/re2_reg + (.C(clk_i), + .CE(\ ), + .D(\u12/re20 ), + .Q(\u12/re2 ), + .R(\ )); + FDRE \u12/rf_we_reg + (.C(clk_i), + .CE(\ ), + .D(\u12/rf_we0 ), + .Q(rf_we), + .R(\ )); + FDRE \u12/wb_ack_o_reg + (.C(clk_i), + .CE(\ ), + .D(\u12/wb_ack_o0 ), + .Q(wb_ack_o), + .R(\ )); + FDRE \u12/wb_data_o_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[0]_i_1_n_0 ), + .Q(wb_data_o[0]), + .R(\ )); + FDRE \u12/wb_data_o_reg[10] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[10]_i_1_n_0 ), + .Q(wb_data_o[10]), + .R(\ )); + FDRE \u12/wb_data_o_reg[11] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[11]_i_1_n_0 ), + .Q(wb_data_o[11]), + .R(\ )); + FDRE \u12/wb_data_o_reg[12] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[12]_i_1_n_0 ), + .Q(wb_data_o[12]), + .R(\ )); + FDRE \u12/wb_data_o_reg[13] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[13]_i_1_n_0 ), + .Q(wb_data_o[13]), + .R(\ )); + FDRE \u12/wb_data_o_reg[14] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[14]_i_1_n_0 ), + .Q(wb_data_o[14]), + .R(\ )); + FDRE \u12/wb_data_o_reg[15] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[15]_i_1_n_0 ), + .Q(wb_data_o[15]), + .R(\ )); + FDRE \u12/wb_data_o_reg[16] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[16]_i_1_n_0 ), + .Q(wb_data_o[16]), + .R(\ )); + FDRE \u12/wb_data_o_reg[17] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[17]_i_1_n_0 ), + .Q(wb_data_o[17]), + .R(\ )); + FDRE \u12/wb_data_o_reg[18] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[18]_i_1_n_0 ), + .Q(wb_data_o[18]), + .R(\ )); + FDRE \u12/wb_data_o_reg[19] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[19]_i_1_n_0 ), + .Q(wb_data_o[19]), + .R(\ )); + FDRE \u12/wb_data_o_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[1]_i_1_n_0 ), + .Q(wb_data_o[1]), + .R(\ )); + FDRE \u12/wb_data_o_reg[20] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[20]_i_1_n_0 ), + .Q(wb_data_o[20]), + .R(\ )); + FDRE \u12/wb_data_o_reg[21] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[21]_i_1_n_0 ), + .Q(wb_data_o[21]), + .R(\ )); + FDRE \u12/wb_data_o_reg[22] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[22]_i_1_n_0 ), + .Q(wb_data_o[22]), + .R(\ )); + FDRE \u12/wb_data_o_reg[23] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[23]_i_1_n_0 ), + .Q(wb_data_o[23]), + .R(\ )); + FDRE \u12/wb_data_o_reg[24] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[24]_i_1_n_0 ), + .Q(wb_data_o[24]), + .R(\ )); + FDRE \u12/wb_data_o_reg[25] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[25]_i_1_n_0 ), + .Q(wb_data_o[25]), + .R(\ )); + FDRE \u12/wb_data_o_reg[26] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[26]_i_1_n_0 ), + .Q(wb_data_o[26]), + .R(\ )); + FDRE \u12/wb_data_o_reg[27] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[27]_i_1_n_0 ), + .Q(wb_data_o[27]), + .R(\ )); + FDRE \u12/wb_data_o_reg[28] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[28]_i_1_n_0 ), + .Q(wb_data_o[28]), + .R(\ )); + FDRE \u12/wb_data_o_reg[29] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[29]_i_1_n_0 ), + .Q(wb_data_o[29]), + .R(\ )); + FDRE \u12/wb_data_o_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[2]_i_1_n_0 ), + .Q(wb_data_o[2]), + .R(\ )); + FDRE \u12/wb_data_o_reg[30] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[30]_i_1_n_0 ), + .Q(wb_data_o[30]), + .R(\ )); + FDRE \u12/wb_data_o_reg[31] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[31]_i_1_n_0 ), + .Q(wb_data_o[31]), + .R(\ )); + FDRE \u12/wb_data_o_reg[3] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[3]_i_1_n_0 ), + .Q(wb_data_o[3]), + .R(\ )); + FDRE \u12/wb_data_o_reg[4] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[4]_i_1_n_0 ), + .Q(wb_data_o[4]), + .R(\ )); + FDRE \u12/wb_data_o_reg[5] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[5]_i_1_n_0 ), + .Q(wb_data_o[5]), + .R(\ )); + FDRE \u12/wb_data_o_reg[6] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[6]_i_1_n_0 ), + .Q(wb_data_o[6]), + .R(\ )); + FDRE \u12/wb_data_o_reg[7] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[7]_i_1_n_0 ), + .Q(wb_data_o[7]), + .R(\ )); + FDRE \u12/wb_data_o_reg[8] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[8]_i_1_n_0 ), + .Q(wb_data_o[8]), + .R(\ )); + FDRE \u12/wb_data_o_reg[9] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[9]_i_1_n_0 ), + .Q(wb_data_o[9]), + .R(\ )); + FDRE \u12/we1_reg + (.C(clk_i), + .CE(\ ), + .D(\u12/we10 ), + .Q(\u12/we1 ), + .R(\ )); + FDRE \u12/we2_reg + (.C(clk_i), + .CE(\ ), + .D(\u12/we20 ), + .Q(\u12/we2 ), + .R(\ )); + FDRE \u13/ac97_rst_force_reg + (.C(clk_i), + .CE(\ ), + .D(ac97_rst_force_i_1_n_0), + .Q(ac97_rst_force), + .R(\ )); + FDRE \u13/crac_dout_r_reg[0] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[0]), + .Q(crac_out[0]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[10] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[10]), + .Q(crac_out[10]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[11] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[11]), + .Q(crac_out[11]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[12] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[12]), + .Q(crac_out[12]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[13] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[13]), + .Q(crac_out[13]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[14] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[14]), + .Q(crac_out[14]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[15] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[15]), + .Q(crac_out[15]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[1] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[1]), + .Q(crac_out[1]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[2] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[2]), + .Q(crac_out[2]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[3] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[3]), + .Q(crac_out[3]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[4] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[4]), + .Q(crac_out[4]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[5] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[5]), + .Q(crac_out[5]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[6] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[6]), + .Q(crac_out[6]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[7] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[7]), + .Q(crac_out[7]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[8] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[8]), + .Q(crac_out[8]), + .R(\ )); + FDRE \u13/crac_dout_r_reg[9] + (.C(clk_i), + .CE(crac_we), + .D(wb_din[9]), + .Q(crac_out[9]), + .R(\ )); + FDCE \u13/crac_r_reg[0] + (.C(clk_i), + .CE(crac_we), + .CLR(dma_req_i_2_n_0), + .D(wb_din[16]), + .Q(crac_out[16])); + FDCE \u13/crac_r_reg[1] + (.C(clk_i), + .CE(crac_we), + .CLR(dma_req_i_2_n_0), + .D(wb_din[17]), + .Q(crac_out[17])); + FDCE \u13/crac_r_reg[2] + (.C(clk_i), + .CE(crac_we), + .CLR(dma_req_i_2_n_0), + .D(wb_din[18]), + .Q(crac_out[18])); + FDCE \u13/crac_r_reg[3] + (.C(clk_i), + .CE(crac_we), + .CLR(dma_req_i_2_n_0), + .D(wb_din[19]), + .Q(crac_out[19])); + FDCE \u13/crac_r_reg[4] + (.C(clk_i), + .CE(crac_we), + .CLR(dma_req_i_2_n_0), + .D(wb_din[20]), + .Q(crac_out[20])); + FDCE \u13/crac_r_reg[5] + (.C(clk_i), + .CE(crac_we), + .CLR(dma_req_i_2_n_0), + .D(wb_din[21]), + .Q(crac_out[21])); + FDCE \u13/crac_r_reg[6] + (.C(clk_i), + .CE(crac_we), + .CLR(dma_req_i_2_n_0), + .D(wb_din[22]), + .Q(crac_out[22])); + FDCE \u13/crac_r_reg[7] + (.C(clk_i), + .CE(crac_we), + .CLR(dma_req_i_2_n_0), + .D(wb_din[31]), + .Q(crac_out[31])); + FDCE \u13/icc_r_reg[0] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[0]), + .Q(\u13/icc_r_reg_n_0_[0] )); + FDCE \u13/icc_r_reg[10] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[10]), + .Q(i4_mode[0])); + FDCE \u13/icc_r_reg[11] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[11]), + .Q(i4_mode[1])); + FDCE \u13/icc_r_reg[12] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[12]), + .Q(\u13/icc_r_reg_n_0_[12] )); + FDCE \u13/icc_r_reg[13] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[13]), + .Q(\u13/icc_r_reg_n_0_[13] )); + FDCE \u13/icc_r_reg[14] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[14]), + .Q(\u13/icc_r_reg_n_0_[14] )); + FDCE \u13/icc_r_reg[15] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[15]), + .Q(\u13/icc_r_reg_n_0_[15] )); + FDCE \u13/icc_r_reg[16] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[16]), + .Q(\u13/icc_r_reg_n_0_[16] )); + FDCE \u13/icc_r_reg[17] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[17]), + .Q(\u13/icc_r_reg_n_0_[17] )); + FDCE \u13/icc_r_reg[18] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[18]), + .Q(i6_mode[0])); + FDCE \u13/icc_r_reg[19] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[19]), + .Q(i6_mode[1])); + FDCE \u13/icc_r_reg[1] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[1]), + .Q(\u13/icc_r_reg_n_0_[1] )); + FDCE \u13/icc_r_reg[20] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[20]), + .Q(\u13/icc_r_reg_n_0_[20] )); + FDCE \u13/icc_r_reg[21] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[21]), + .Q(\u13/icc_r_reg_n_0_[21] )); + FDCE \u13/icc_r_reg[22] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[22]), + .Q(\u13/icc_r_reg_n_0_[22] )); + FDCE \u13/icc_r_reg[23] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[23]), + .Q(\u13/icc_r_reg_n_0_[23] )); + FDCE \u13/icc_r_reg[2] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[2]), + .Q(i3_mode[0])); + FDCE \u13/icc_r_reg[3] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[3]), + .Q(i3_mode[1])); + FDCE \u13/icc_r_reg[4] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[4]), + .Q(\u13/icc_r_reg_n_0_[4] )); + FDCE \u13/icc_r_reg[5] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[5]), + .Q(\u13/icc_r_reg_n_0_[5] )); + FDCE \u13/icc_r_reg[6] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[6]), + .Q(\u13/icc_r_reg_n_0_[6] )); + FDCE \u13/icc_r_reg[7] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[7]), + .Q(\u13/icc_r_reg_n_0_[7] )); + FDCE \u13/icc_r_reg[8] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[8]), + .Q(\u13/icc_r_reg_n_0_[8] )); + FDCE \u13/icc_r_reg[9] + (.C(clk_i), + .CE(\u13/icc_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[9]), + .Q(\u13/icc_r_reg_n_0_[9] )); + FDRE \u13/int_reg + (.C(clk_i), + .CE(\ ), + .D(int_i_1_n_0), + .Q(int_o), + .R(\ )); + FDCE \u13/intm_r_reg[0] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[0]), + .Q(\u13/intm [0])); + FDCE \u13/intm_r_reg[10] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[10]), + .Q(\u13/intm [10])); + FDCE \u13/intm_r_reg[11] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[11]), + .Q(\u13/intm [11])); + FDCE \u13/intm_r_reg[12] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[12]), + .Q(\u13/intm [12])); + FDCE \u13/intm_r_reg[13] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[13]), + .Q(\u13/intm [13])); + FDCE \u13/intm_r_reg[14] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[14]), + .Q(\u13/intm [14])); + FDCE \u13/intm_r_reg[15] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[15]), + .Q(\u13/intm [15])); + FDCE \u13/intm_r_reg[16] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[16]), + .Q(\u13/intm [16])); + FDCE \u13/intm_r_reg[17] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[17]), + .Q(\u13/intm [17])); + FDCE \u13/intm_r_reg[18] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[18]), + .Q(\u13/intm [18])); + FDCE \u13/intm_r_reg[19] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[19]), + .Q(\u13/intm [19])); + FDCE \u13/intm_r_reg[1] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[1]), + .Q(\u13/intm [1])); + FDCE \u13/intm_r_reg[20] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[20]), + .Q(\u13/intm [20])); + FDCE \u13/intm_r_reg[21] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[21]), + .Q(\u13/intm [21])); + FDCE \u13/intm_r_reg[22] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[22]), + .Q(\u13/intm [22])); + FDCE \u13/intm_r_reg[23] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[23]), + .Q(\u13/intm [23])); + FDCE \u13/intm_r_reg[24] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[24]), + .Q(\u13/intm [24])); + FDCE \u13/intm_r_reg[25] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[25]), + .Q(\u13/intm [25])); + FDCE \u13/intm_r_reg[26] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[26]), + .Q(\u13/intm [26])); + FDCE \u13/intm_r_reg[27] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[27]), + .Q(\u13/intm [27])); + FDCE \u13/intm_r_reg[28] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[28]), + .Q(\u13/intm [28])); + FDCE \u13/intm_r_reg[2] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[2]), + .Q(\u13/intm [2])); + FDCE \u13/intm_r_reg[3] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[3]), + .Q(\u13/intm [3])); + FDCE \u13/intm_r_reg[4] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[4]), + .Q(\u13/intm [4])); + FDCE \u13/intm_r_reg[5] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[5]), + .Q(\u13/intm [5])); + FDCE \u13/intm_r_reg[6] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[6]), + .Q(\u13/intm [6])); + FDCE \u13/intm_r_reg[7] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[7]), + .Q(\u13/intm [7])); + FDCE \u13/intm_r_reg[8] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[8]), + .Q(\u13/intm [8])); + FDCE \u13/intm_r_reg[9] + (.C(clk_i), + .CE(\u13/intm_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[9]), + .Q(\u13/intm [9])); + FDCE \u13/ints_r_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[0]_i_1_n_0 ), + .Q(\u13/ints [0])); + FDCE \u13/ints_r_reg[10] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[10]_i_1_n_0 ), + .Q(\u13/ints [10])); + FDCE \u13/ints_r_reg[11] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[11]_i_1_n_0 ), + .Q(\u13/ints [11])); + FDCE \u13/ints_r_reg[12] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[12]_i_1_n_0 ), + .Q(\u13/ints [12])); + FDCE \u13/ints_r_reg[13] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[13]_i_1_n_0 ), + .Q(\u13/ints [13])); + FDCE \u13/ints_r_reg[14] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[14]_i_1_n_0 ), + .Q(\u13/ints [14])); + FDCE \u13/ints_r_reg[15] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[15]_i_1_n_0 ), + .Q(\u13/ints [15])); + FDCE \u13/ints_r_reg[16] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[16]_i_1_n_0 ), + .Q(\u13/ints [16])); + FDCE \u13/ints_r_reg[17] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[17]_i_1_n_0 ), + .Q(\u13/ints [17])); + FDCE \u13/ints_r_reg[18] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[18]_i_1_n_0 ), + .Q(\u13/ints [18])); + FDCE \u13/ints_r_reg[19] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[19]_i_1_n_0 ), + .Q(\u13/ints [19])); + FDCE \u13/ints_r_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[1]_i_1_n_0 ), + .Q(\u13/ints [1])); + FDCE \u13/ints_r_reg[20] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[20]_i_1_n_0 ), + .Q(\u13/ints [20])); + FDCE \u13/ints_r_reg[21] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[21]_i_1_n_0 ), + .Q(\u13/ints [21])); + FDCE \u13/ints_r_reg[22] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[22]_i_1_n_0 ), + .Q(\u13/ints [22])); + FDCE \u13/ints_r_reg[23] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[23]_i_1_n_0 ), + .Q(\u13/ints [23])); + FDCE \u13/ints_r_reg[24] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[24]_i_1_n_0 ), + .Q(\u13/ints [24])); + FDCE \u13/ints_r_reg[25] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[25]_i_1_n_0 ), + .Q(\u13/ints [25])); + FDCE \u13/ints_r_reg[26] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[26]_i_1_n_0 ), + .Q(\u13/ints [26])); + FDCE \u13/ints_r_reg[27] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[27]_i_1_n_0 ), + .Q(\u13/ints [27])); + FDCE \u13/ints_r_reg[28] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[28]_i_1_n_0 ), + .Q(\u13/ints [28])); + FDCE \u13/ints_r_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[2]_i_1_n_0 ), + .Q(\u13/ints [2])); + FDCE \u13/ints_r_reg[3] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[3]_i_1_n_0 ), + .Q(\u13/ints [3])); + FDCE \u13/ints_r_reg[4] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[4]_i_1_n_0 ), + .Q(\u13/ints [4])); + FDCE \u13/ints_r_reg[5] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[5]_i_1_n_0 ), + .Q(\u13/ints [5])); + FDCE \u13/ints_r_reg[6] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[6]_i_1_n_0 ), + .Q(\u13/ints [6])); + FDCE \u13/ints_r_reg[7] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[7]_i_1_n_0 ), + .Q(\u13/ints [7])); + FDCE \u13/ints_r_reg[8] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[8]_i_1_n_0 ), + .Q(\u13/ints [8])); + FDCE \u13/ints_r_reg[9] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ints_r[9]_i_1_n_0 ), + .Q(\u13/ints [9])); + FDCE \u13/occ0_r_reg[0] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[0]), + .Q(\u13/occ0_r_reg_n_0_[0] )); + FDCE \u13/occ0_r_reg[10] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[10]), + .Q(o4_mode[0])); + FDCE \u13/occ0_r_reg[11] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[11]), + .Q(o4_mode[1])); + FDCE \u13/occ0_r_reg[12] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[12]), + .Q(\u13/occ0_r_reg_n_0_[12] )); + FDCE \u13/occ0_r_reg[13] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[13]), + .Q(\u13/occ0_r_reg_n_0_[13] )); + FDCE \u13/occ0_r_reg[14] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[14]), + .Q(\u13/occ0_r_reg_n_0_[14] )); + FDCE \u13/occ0_r_reg[15] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[15]), + .Q(\u13/occ0_r_reg_n_0_[15] )); + FDCE \u13/occ0_r_reg[16] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[16]), + .Q(\u13/occ0_r_reg_n_0_[16] )); + FDCE \u13/occ0_r_reg[17] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[17]), + .Q(\u13/occ0_r_reg_n_0_[17] )); + FDCE \u13/occ0_r_reg[18] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[18]), + .Q(o6_mode[0])); + FDCE \u13/occ0_r_reg[19] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[19]), + .Q(o6_mode[1])); + FDCE \u13/occ0_r_reg[1] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[1]), + .Q(\u13/occ0_r_reg_n_0_[1] )); + FDCE \u13/occ0_r_reg[20] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[20]), + .Q(\u13/occ0_r_reg_n_0_[20] )); + FDCE \u13/occ0_r_reg[21] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[21]), + .Q(\u13/occ0_r_reg_n_0_[21] )); + FDCE \u13/occ0_r_reg[22] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[22]), + .Q(\u13/occ0_r_reg_n_0_[22] )); + FDCE \u13/occ0_r_reg[23] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[23]), + .Q(\u13/occ0_r_reg_n_0_[23] )); + FDCE \u13/occ0_r_reg[24] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[24]), + .Q(\u13/occ0_r_reg_n_0_[24] )); + FDCE \u13/occ0_r_reg[25] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[25]), + .Q(\u13/occ0_r_reg_n_0_[25] )); + FDCE \u13/occ0_r_reg[26] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[26]), + .Q(o7_mode[0])); + FDCE \u13/occ0_r_reg[27] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[27]), + .Q(o7_mode[1])); + FDCE \u13/occ0_r_reg[28] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[28]), + .Q(\u13/occ0_r_reg_n_0_[28] )); + FDCE \u13/occ0_r_reg[29] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[29]), + .Q(\u13/occ0_r_reg_n_0_[29] )); + FDCE \u13/occ0_r_reg[2] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[2]), + .Q(o3_mode[0])); + FDCE \u13/occ0_r_reg[30] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[30]), + .Q(\u13/occ0_r_reg_n_0_[30] )); + FDCE \u13/occ0_r_reg[31] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[31]), + .Q(\u13/occ0_r_reg_n_0_[31] )); + FDCE \u13/occ0_r_reg[3] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[3]), + .Q(o3_mode[1])); + FDCE \u13/occ0_r_reg[4] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[4]), + .Q(\u13/occ0_r_reg_n_0_[4] )); + FDCE \u13/occ0_r_reg[5] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[5]), + .Q(\u13/occ0_r_reg_n_0_[5] )); + FDCE \u13/occ0_r_reg[6] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[6]), + .Q(\u13/occ0_r_reg_n_0_[6] )); + FDCE \u13/occ0_r_reg[7] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[7]), + .Q(\u13/occ0_r_reg_n_0_[7] )); + FDCE \u13/occ0_r_reg[8] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[8]), + .Q(\u13/occ0_r_reg_n_0_[8] )); + FDCE \u13/occ0_r_reg[9] + (.C(clk_i), + .CE(\u13/occ00 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[9]), + .Q(\u13/occ0_r_reg_n_0_[9] )); + FDCE \u13/occ1_r_reg[0] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[0]), + .Q(\u13/occ1_r_reg_n_0_[0] )); + FDCE \u13/occ1_r_reg[10] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[10]), + .Q(o9_mode[0])); + FDCE \u13/occ1_r_reg[11] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[11]), + .Q(o9_mode[1])); + FDCE \u13/occ1_r_reg[12] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[12]), + .Q(\u13/occ1_r_reg_n_0_[12] )); + FDCE \u13/occ1_r_reg[13] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[13]), + .Q(\u13/occ1_r_reg_n_0_[13] )); + FDCE \u13/occ1_r_reg[14] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[14]), + .Q(\u13/occ1_r_reg_n_0_[14] )); + FDCE \u13/occ1_r_reg[15] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[15]), + .Q(\u13/occ1_r_reg_n_0_[15] )); + FDCE \u13/occ1_r_reg[1] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[1]), + .Q(\u13/occ1_r_reg_n_0_[1] )); + FDCE \u13/occ1_r_reg[2] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[2]), + .Q(o8_mode[0])); + FDCE \u13/occ1_r_reg[3] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[3]), + .Q(o8_mode[1])); + FDCE \u13/occ1_r_reg[4] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[4]), + .Q(\u13/occ1_r_reg_n_0_[4] )); + FDCE \u13/occ1_r_reg[5] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[5]), + .Q(\u13/occ1_r_reg_n_0_[5] )); + FDCE \u13/occ1_r_reg[6] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[6]), + .Q(\u13/occ1_r_reg_n_0_[6] )); + FDCE \u13/occ1_r_reg[7] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[7]), + .Q(\u13/occ1_r_reg_n_0_[7] )); + FDCE \u13/occ1_r_reg[8] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[8]), + .Q(\u13/occ1_r_reg_n_0_[8] )); + FDCE \u13/occ1_r_reg[9] + (.C(clk_i), + .CE(\u13/occ1_r0 ), + .CLR(dma_req_i_2_n_0), + .D(wb_din[9]), + .Q(\u13/occ1_r_reg_n_0_[9] )); + FDRE \u13/resume_req_reg + (.C(clk_i), + .CE(\ ), + .D(resume_req_i_1_n_0), + .Q(resume_req), + .R(\ )); + FDRE \u14/crac_valid_r_reg + (.C(clk_i), + .CE(\ ), + .D(crac_valid_r_i_1_n_0), + .Q(out_slt0[14]), + .R(\ )); + FDRE \u14/crac_wr_r_reg + (.C(clk_i), + .CE(\ ), + .D(crac_wr_r_i_1_n_0), + .Q(out_slt0[13]), + .R(\ )); + FDRE \u14/u0/en_out_l2_reg + (.C(clk_i), + .CE(\ ), + .D(\u14/u0/en_out_l20 ), + .Q(\u14/u0/en_out_l2_reg_n_0 ), + .R(\ )); + FDRE \u14/u0/en_out_l_reg + (.C(clk_i), + .CE(\ ), + .D(en_out_l_i_1__4_n_0), + .Q(out_slt0[12]), + .R(\ )); + FDRE \u14/u0/full_empty_r_reg + (.C(clk_i), + .CE(\u14/p_0_in ), + .D(o3_empty), + .Q(\u14/u0/full_empty_r ), + .R(\ )); + FDRE \u14/u1/en_out_l2_reg + (.C(clk_i), + .CE(\ ), + .D(\u14/u1/en_out_l20 ), + .Q(\u14/u1/en_out_l2_reg_n_0 ), + .R(\ )); + FDRE \u14/u1/en_out_l_reg + (.C(clk_i), + .CE(\ ), + .D(en_out_l_i_1__3_n_0), + .Q(out_slt0[11]), + .R(\ )); + FDRE \u14/u1/full_empty_r_reg + (.C(clk_i), + .CE(\u14/p_0_in ), + .D(o4_empty), + .Q(\u14/u1/full_empty_r ), + .R(\ )); + FDRE \u14/u2/en_out_l2_reg + (.C(clk_i), + .CE(\ ), + .D(\u14/u2/en_out_l20 ), + .Q(\u14/u2/en_out_l2_reg_n_0 ), + .R(\ )); + FDRE \u14/u2/en_out_l_reg + (.C(clk_i), + .CE(\ ), + .D(en_out_l_i_1__2_n_0), + .Q(out_slt0[9]), + .R(\ )); + FDRE \u14/u2/full_empty_r_reg + (.C(clk_i), + .CE(\u14/p_0_in ), + .D(o6_empty), + .Q(\u14/u2/full_empty_r ), + .R(\ )); + FDRE \u14/u3/en_out_l2_reg + (.C(clk_i), + .CE(\ ), + .D(\u14/u3/en_out_l20 ), + .Q(\u14/u3/en_out_l2_reg_n_0 ), + .R(\ )); + FDRE \u14/u3/en_out_l_reg + (.C(clk_i), + .CE(\ ), + .D(en_out_l_i_1__1_n_0), + .Q(out_slt0[8]), + .R(\ )); + FDRE \u14/u3/full_empty_r_reg + (.C(clk_i), + .CE(\u14/p_0_in ), + .D(o7_empty), + .Q(\u14/u3/full_empty_r ), + .R(\ )); + FDRE \u14/u4/en_out_l2_reg + (.C(clk_i), + .CE(\ ), + .D(\u14/u4/en_out_l20 ), + .Q(\u14/u4/en_out_l2_reg_n_0 ), + .R(\ )); + FDRE \u14/u4/en_out_l_reg + (.C(clk_i), + .CE(\ ), + .D(en_out_l_i_1__0_n_0), + .Q(out_slt0[7]), + .R(\ )); + FDRE \u14/u4/full_empty_r_reg + (.C(clk_i), + .CE(\u14/p_0_in ), + .D(o8_empty), + .Q(\u14/u4/full_empty_r ), + .R(\ )); + FDRE \u14/u5/en_out_l2_reg + (.C(clk_i), + .CE(\ ), + .D(\u14/u5/en_out_l20 ), + .Q(\u14/u5/en_out_l2_reg_n_0 ), + .R(\ )); + FDRE \u14/u5/en_out_l_reg + (.C(clk_i), + .CE(\ ), + .D(en_out_l_i_1_n_0), + .Q(out_slt0[6]), + .R(\ )); + FDRE \u14/u5/full_empty_r_reg + (.C(clk_i), + .CE(\u14/p_0_in ), + .D(o9_empty), + .Q(\u14/u5/full_empty_r ), + .R(\ )); + FDRE \u14/u6/en_out_l2_reg + (.C(clk_i), + .CE(\ ), + .D(\u14/u6/en_out_l20 ), + .Q(\u14/u6/en_out_l2_reg_n_0 ), + .R(\ )); + FDRE \u14/u6/en_out_l_reg + (.C(clk_i), + .CE(\ ), + .D(en_out_l_i_1__5_n_0), + .Q(\u14/u6/en_out_l_reg_n_0 ), + .R(\ )); + FDRE \u14/u6/full_empty_r_reg + (.C(clk_i), + .CE(\ ), + .D(full_empty_r_i_1__0_n_0), + .Q(\u14/u6/full_empty_r ), + .R(\ )); + FDRE \u14/u7/en_out_l2_reg + (.C(clk_i), + .CE(\ ), + .D(\u14/u7/en_out_l20 ), + .Q(\u14/u7/en_out_l2_reg_n_0 ), + .R(\ )); + FDRE \u14/u7/en_out_l_reg + (.C(clk_i), + .CE(\ ), + .D(en_out_l_i_1__6_n_0), + .Q(\u14/u7/en_out_l_reg_n_0 ), + .R(\ )); + FDRE \u14/u7/full_empty_r_reg + (.C(clk_i), + .CE(\ ), + .D(full_empty_r_i_1__1_n_0), + .Q(\u14/u7/full_empty_r ), + .R(\ )); + FDRE \u14/u8/en_out_l2_reg + (.C(clk_i), + .CE(\ ), + .D(\u14/u8/en_out_l20 ), + .Q(\u14/u8/en_out_l2_reg_n_0 ), + .R(\ )); + FDRE \u14/u8/en_out_l_reg + (.C(clk_i), + .CE(\ ), + .D(en_out_l_i_1__7_n_0), + .Q(\u14/u8/en_out_l_reg_n_0 ), + .R(\ )); + FDRE \u14/u8/full_empty_r_reg + (.C(clk_i), + .CE(\ ), + .D(full_empty_r_i_1__2_n_0), + .Q(\u14/u8/full_empty_r ), + .R(\ )); + FDCE \u15/crac_din_reg[0] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[4]), + .Q(crac_din[0])); + FDCE \u15/crac_din_reg[10] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[14]), + .Q(crac_din[10])); + FDCE \u15/crac_din_reg[11] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[15]), + .Q(crac_din[11])); + FDCE \u15/crac_din_reg[12] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[16]), + .Q(crac_din[12])); + FDCE \u15/crac_din_reg[13] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[17]), + .Q(crac_din[13])); + FDCE \u15/crac_din_reg[14] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[18]), + .Q(crac_din[14])); + FDCE \u15/crac_din_reg[15] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[19]), + .Q(crac_din[15])); + FDCE \u15/crac_din_reg[1] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[5]), + .Q(crac_din[1])); + FDCE \u15/crac_din_reg[2] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[6]), + .Q(crac_din[2])); + FDCE \u15/crac_din_reg[3] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[7]), + .Q(crac_din[3])); + FDCE \u15/crac_din_reg[4] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[8]), + .Q(crac_din[4])); + FDCE \u15/crac_din_reg[5] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[9]), + .Q(crac_din[5])); + FDCE \u15/crac_din_reg[6] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[10]), + .Q(crac_din[6])); + FDCE \u15/crac_din_reg[7] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[11]), + .Q(crac_din[7])); + FDCE \u15/crac_din_reg[8] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[12]), + .Q(crac_din[8])); + FDCE \u15/crac_din_reg[9] + (.C(clk_i), + .CE(crac_rd_done), + .CLR(dma_req_i_2_n_0), + .D(in_slt2[13]), + .Q(crac_din[9])); + FDRE \u15/crac_rd_done_reg + (.C(clk_i), + .CE(\ ), + .D(\u15/crac_rd_done0 ), + .Q(crac_rd_done), + .R(\ )); + FDCE \u15/crac_rd_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(crac_rd_i_1_n_0), + .Q(\u15/crac_rd )); + FDRE \u15/crac_we_r_reg + (.C(clk_i), + .CE(\ ), + .D(crac_we), + .Q(\u15/crac_we_r ), + .R(\ )); + FDCE \u15/crac_wr_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(crac_wr_i_1_n_0), + .Q(crac_wr)); + FDCE \u15/rdd1_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(rdd1_i_1_n_0), + .Q(\u15/rdd1 )); + FDCE \u15/rdd2_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(rdd2_i_1_n_0), + .Q(\u15/rdd2 )); + FDCE \u15/rdd3_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(rdd3_i_1_n_0), + .Q(\u15/rdd3 )); + FDRE \u15/valid_r_reg + (.C(clk_i), + .CE(\ ), + .D(valid_s), + .Q(\u15/valid_r ), + .R(\ )); + FDRE \u16/u0/dma_req_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\u16/u0/dma_req_r10 ), + .Q(\u16/u0/dma_req_r1 ), + .R(\ )); + FDCE \u16/u0/dma_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(dma_req_i_1_n_0), + .Q(dma_req_o[0])); + FDRE \u16/u1/dma_req_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\u16/u1/dma_req_r10 ), + .Q(\u16/u1/dma_req_r1 ), + .R(\ )); + FDCE \u16/u1/dma_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(dma_req_i_1__0_n_0), + .Q(dma_req_o[1])); + FDRE \u16/u2/dma_req_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\u16/u2/dma_req_r10 ), + .Q(\u16/u2/dma_req_r1 ), + .R(\ )); + FDCE \u16/u2/dma_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(dma_req_i_1__1_n_0), + .Q(dma_req_o[2])); + FDRE \u16/u3/dma_req_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\u16/u3/dma_req_r10 ), + .Q(\u16/u3/dma_req_r1 ), + .R(\ )); + FDCE \u16/u3/dma_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(dma_req_i_1__2_n_0), + .Q(dma_req_o[3])); + FDRE \u16/u4/dma_req_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\u16/u4/dma_req_r10 ), + .Q(\u16/u4/dma_req_r1 ), + .R(\ )); + FDCE \u16/u4/dma_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(dma_req_i_1__3_n_0), + .Q(dma_req_o[4])); + FDRE \u16/u5/dma_req_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\u16/u5/dma_req_r10 ), + .Q(\u16/u5/dma_req_r1 ), + .R(\ )); + FDCE \u16/u5/dma_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(dma_req_i_1__4_n_0), + .Q(dma_req_o[5])); + FDRE \u16/u6/dma_req_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\u16/u6/dma_req_r10 ), + .Q(\u16/u6/dma_req_r1 ), + .R(\ )); + FDCE \u16/u6/dma_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(dma_req_i_1__5_n_0), + .Q(dma_req_o[6])); + FDRE \u16/u7/dma_req_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\u16/u7/dma_req_r10 ), + .Q(\u16/u7/dma_req_r1 ), + .R(\ )); + FDCE \u16/u7/dma_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(dma_req_i_1__6_n_0), + .Q(dma_req_o[7])); + FDRE \u16/u8/dma_req_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\u16/u8/dma_req_r10 ), + .Q(\u16/u8/dma_req_r1 ), + .R(\ )); + FDCE \u16/u8/dma_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(dma_req_i_1__7_n_0), + .Q(dma_req_o[8])); + FDCE \u17/int_set_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\int_set[0]_i_1_n_0 ), + .Q(oc0_int_set[0])); + FDCE \u17/int_set_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u17/int_set_reg00_out ), + .Q(oc0_int_set[1])); + FDCE \u17/int_set_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u17/int_set_reg0 ), + .Q(oc0_int_set[2])); + FDCE \u18/int_set_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\int_set[0]_i_1__0_n_0 ), + .Q(oc1_int_set[0])); + FDCE \u18/int_set_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u18/int_set_reg00_out ), + .Q(oc1_int_set[1])); + FDCE \u18/int_set_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u18/int_set_reg0 ), + .Q(oc1_int_set[2])); + FDCE \u19/int_set_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\int_set[0]_i_1__1_n_0 ), + .Q(oc2_int_set[0])); + FDCE \u19/int_set_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u19/int_set_reg00_out ), + .Q(oc2_int_set[1])); + FDCE \u19/int_set_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u19/int_set_reg0 ), + .Q(oc2_int_set[2])); + FDRE \u2/bit_clk_e_reg + (.C(clk_i), + .CE(\ ), + .D(\u2/bit_clk_e0 ), + .Q(\u2/bit_clk_e ), + .R(\ )); + FDRE \u2/bit_clk_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\u2/bit_clk_r ), + .Q(\u2/bit_clk_r1 ), + .R(\ )); + FDRE \u2/bit_clk_r_reg + (.C(clk_i), + .CE(\ ), + .D(bit_clk_pad_i), + .Q(\u2/bit_clk_r ), + .R(\ )); + FDPE \u2/cnt_reg[0] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\cnt[0]_i_1__0_n_0 ), + .PRE(dma_req_i_2_n_0), + .Q(\u2/cnt_reg [0])); + FDPE \u2/cnt_reg[1] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in__1__0[1]), + .PRE(dma_req_i_2_n_0), + .Q(\u2/cnt_reg [1])); + FDPE \u2/cnt_reg[2] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in__1__0[2]), + .PRE(dma_req_i_2_n_0), + .Q(\u2/cnt_reg [2])); + FDPE \u2/cnt_reg[3] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in__1__0[3]), + .PRE(dma_req_i_2_n_0), + .Q(\u2/cnt_reg [3])); + FDPE \u2/cnt_reg[4] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in__1__0[4]), + .PRE(dma_req_i_2_n_0), + .Q(\u2/cnt_reg [4])); + FDPE \u2/cnt_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in__1__0[5]), + .PRE(dma_req_i_2_n_0), + .Q(\u2/cnt_reg [5])); + FDPE \u2/cnt_reg[6] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in__1__0[6]), + .PRE(dma_req_i_2_n_0), + .Q(\u2/cnt_reg [6])); + FDPE \u2/cnt_reg[7] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(p_0_in__1__0[7]), + .PRE(dma_req_i_2_n_0), + .Q(\u2/cnt_reg [7])); + FDRE \u2/in_valid_reg[0] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u2/p_0_in ), + .Q(in_valid[0]), + .R(\ )); + FDRE \u2/in_valid_reg[1] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\in_valid[1]_i_1_n_0 ), + .Q(in_valid[1]), + .R(\ )); + FDRE \u2/in_valid_reg[2] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\in_valid[2]_i_1_n_0 ), + .Q(in_valid[2]), + .R(\ )); + FDRE \u2/ld_reg + (.C(bit_clk_pad_i), + .CE(\ ), + .D(ld_i_1_n_0), + .Q(ld), + .R(\ )); + FDRE \u2/out_le_reg[0] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\out_le[0]_i_1_n_0 ), + .Q(out_le[0]), + .R(\ )); + FDRE \u2/out_le_reg[1] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\out_le[1]_i_1_n_0 ), + .Q(out_le[1]), + .R(\ )); + FDRE \u2/out_le_reg[2] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\out_le[2]_i_1_n_0 ), + .Q(out_le[2]), + .R(\ )); + FDRE \u2/out_le_reg[3] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\out_le[3]_i_1_n_0 ), + .Q(out_le[3]), + .R(\ )); + FDRE \u2/out_le_reg[4] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\out_le[4]_i_1_n_0 ), + .Q(out_le[4]), + .R(\ )); + FDRE \u2/out_le_reg[5] + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\out_le[5]_i_1_n_0 ), + .Q(out_le[5]), + .R(\ )); + FDRE \u2/res_cnt_reg[0] + (.C(clk_i), + .CE(ps_ce), + .D(p_0_in__0__0[0]), + .Q(\u2/res_cnt_reg [0]), + .R(\u2/clear )); + FDRE \u2/res_cnt_reg[1] + (.C(clk_i), + .CE(ps_ce), + .D(p_0_in__0__0[1]), + .Q(\u2/res_cnt_reg [1]), + .R(\u2/clear )); + FDRE \u2/res_cnt_reg[2] + (.C(clk_i), + .CE(ps_ce), + .D(p_0_in__0__0[2]), + .Q(\u2/res_cnt_reg [2]), + .R(\u2/clear )); + FDRE \u2/res_cnt_reg[3] + (.C(clk_i), + .CE(ps_ce), + .D(p_0_in__0__0[3]), + .Q(\u2/res_cnt_reg [3]), + .R(\u2/clear )); + FDRE \u2/suspended_reg + (.C(clk_i), + .CE(\ ), + .D(\u2/to ), + .Q(suspended_o), + .R(\ )); + FDRE \u2/sync_beat_reg + (.C(bit_clk_pad_i), + .CE(\ ), + .D(\u2/sync_beat0 ), + .Q(\u2/sync_beat ), + .R(\ )); + FDCE \u2/sync_resume_reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(sync_resume_i_1_n_0), + .Q(\u2/sync_resume_reg_n_0 )); + FDCE \u2/to_cnt_reg[0] + (.C(clk_i), + .CE(\to_cnt[5]_i_1_n_0 ), + .CLR(dma_req_i_2_n_0), + .D(\to_cnt[0]_i_1_n_0 ), + .Q(\u2/to_cnt_reg [0])); + FDCE \u2/to_cnt_reg[1] + (.C(clk_i), + .CE(\to_cnt[5]_i_1_n_0 ), + .CLR(dma_req_i_2_n_0), + .D(p_0_in__3[1]), + .Q(\u2/to_cnt_reg [1])); + FDCE \u2/to_cnt_reg[2] + (.C(clk_i), + .CE(\to_cnt[5]_i_1_n_0 ), + .CLR(dma_req_i_2_n_0), + .D(p_0_in__3[2]), + .Q(\u2/to_cnt_reg [2])); + FDCE \u2/to_cnt_reg[3] + (.C(clk_i), + .CE(\to_cnt[5]_i_1_n_0 ), + .CLR(dma_req_i_2_n_0), + .D(p_0_in__3[3]), + .Q(\u2/to_cnt_reg [3])); + FDCE \u2/to_cnt_reg[4] + (.C(clk_i), + .CE(\to_cnt[5]_i_1_n_0 ), + .CLR(dma_req_i_2_n_0), + .D(p_0_in__3[4]), + .Q(\u2/to_cnt_reg [4])); + FDCE \u2/to_cnt_reg[5] + (.C(clk_i), + .CE(\to_cnt[5]_i_1_n_0 ), + .CLR(dma_req_i_2_n_0), + .D(p_0_in__3[5]), + .Q(\u2/to_cnt_reg [5])); + FDRE \u2/valid_reg + (.C(bit_clk_pad_i), + .CE(\ ), + .D(valid_i_1_n_0), + .Q(valid), + .R(\ )); + FDCE \u20/int_set_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\int_set[0]_i_1__2_n_0 ), + .Q(oc3_int_set[0])); + FDCE \u20/int_set_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u20/int_set_reg00_out ), + .Q(oc3_int_set[1])); + FDCE \u20/int_set_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u20/int_set_reg0 ), + .Q(oc3_int_set[2])); + FDCE \u21/int_set_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\int_set[0]_i_1__3_n_0 ), + .Q(oc4_int_set[0])); + FDCE \u21/int_set_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u21/int_set_reg00_out ), + .Q(oc4_int_set[1])); + FDCE \u21/int_set_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u21/int_set_reg0 ), + .Q(oc4_int_set[2])); + FDCE \u22/int_set_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\int_set[0]_i_1__4_n_0 ), + .Q(oc5_int_set[0])); + FDCE \u22/int_set_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u22/int_set_reg00_out ), + .Q(oc5_int_set[1])); + FDCE \u22/int_set_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u22/int_set_reg0 ), + .Q(oc5_int_set[2])); + FDCE \u23/int_set_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\int_set[0]_i_1__5_n_0 ), + .Q(ic0_int_set[0])); + FDCE \u23/int_set_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u23/int_set_reg00_out ), + .Q(ic0_int_set[1])); + FDCE \u23/int_set_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u23/int_set_reg0 ), + .Q(ic0_int_set[2])); + FDCE \u24/int_set_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\int_set[0]_i_1__6_n_0 ), + .Q(ic1_int_set[0])); + FDCE \u24/int_set_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u24/int_set_reg00_out ), + .Q(ic1_int_set[1])); + FDCE \u24/int_set_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u24/int_set_reg0 ), + .Q(ic1_int_set[2])); + FDCE \u25/int_set_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\int_set[0]_i_1__7_n_0 ), + .Q(ic2_int_set[0])); + FDCE \u25/int_set_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u25/int_set_reg00_out ), + .Q(ic2_int_set[1])); + FDCE \u25/int_set_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\u25/int_set_reg0 ), + .Q(ic2_int_set[2])); + FDCE \u26/ac97_rst__reg + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(ac97_rst__i_1_n_0), + .Q(ac97_reset_pad_o_)); + FDCE \u26/cnt_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\cnt[0]_i_1_n_0 ), + .Q(\u26/cnt [0])); + FDCE \u26/cnt_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\cnt[1]_i_1_n_0 ), + .Q(\u26/cnt [1])); + FDCE \u26/cnt_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\cnt[2]_i_1_n_0 ), + .Q(\u26/cnt [2])); + FDCE \u26/ps_cnt_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(\ps_cnt[0]_i_1_n_0 ), + .Q(\u26/ps_cnt_reg [0])); + FDCE \u26/ps_cnt_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(p_0_in__8[1]), + .Q(\u26/ps_cnt_reg [1])); + FDCE \u26/ps_cnt_reg[2] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(p_0_in__8[2]), + .Q(\u26/ps_cnt_reg [2])); + FDCE \u26/ps_cnt_reg[3] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(p_0_in__8[3]), + .Q(\u26/ps_cnt_reg [3])); + FDCE \u26/ps_cnt_reg[4] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(p_0_in__8[4]), + .Q(\u26/ps_cnt_reg [4])); + FDCE \u26/ps_cnt_reg[5] + (.C(clk_i), + .CE(\ ), + .CLR(dma_req_i_2_n_0), + .D(p_0_in__8[5]), + .Q(\u26/ps_cnt_reg [5])); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT2 #( + .INIT(4'h8)) + \u3/dout[0]_i_1 + (.I0(o3_mode[1]), + .I1(dout_tmp[0]), + .O(\u3/dout[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[10]_i_1 + (.I0(dout_tmp[10]), + .I1(o3_mode[1]), + .I2(\u3/dout[10]_i_2_n_0 ), + .O(\u3/dout[10]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[10]_i_2 + (.I0(dout_tmp[8]), + .I1(o3_mode[0]), + .I2(dout_tmp[22]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[6]), + .O(\u3/dout[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[11]_i_1 + (.I0(dout_tmp[11]), + .I1(o3_mode[1]), + .I2(\u3/dout[11]_i_2_n_0 ), + .O(\u3/dout[11]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[11]_i_2 + (.I0(dout_tmp[9]), + .I1(o3_mode[0]), + .I2(dout_tmp[23]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[7]), + .O(\u3/dout[11]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[12]_i_1 + (.I0(dout_tmp[12]), + .I1(o3_mode[1]), + .I2(\u3/dout[12]_i_2_n_0 ), + .O(\u3/dout[12]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[12]_i_2 + (.I0(dout_tmp[10]), + .I1(o3_mode[0]), + .I2(dout_tmp[24]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[8]), + .O(\u3/dout[12]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[13]_i_1 + (.I0(dout_tmp[13]), + .I1(o3_mode[1]), + .I2(\u3/dout[13]_i_2_n_0 ), + .O(\u3/dout[13]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[13]_i_2 + (.I0(dout_tmp[11]), + .I1(o3_mode[0]), + .I2(dout_tmp[25]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[9]), + .O(\u3/dout[13]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[14]_i_1 + (.I0(dout_tmp[14]), + .I1(o3_mode[1]), + .I2(\u3/dout[14]_i_2_n_0 ), + .O(\u3/dout[14]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[14]_i_2 + (.I0(dout_tmp[12]), + .I1(o3_mode[0]), + .I2(dout_tmp[26]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[10]), + .O(\u3/dout[14]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[15]_i_1 + (.I0(dout_tmp[15]), + .I1(o3_mode[1]), + .I2(\u3/dout[15]_i_2_n_0 ), + .O(\u3/dout[15]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[15]_i_2 + (.I0(dout_tmp[13]), + .I1(o3_mode[0]), + .I2(dout_tmp[27]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[11]), + .O(\u3/dout[15]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[16]_i_1 + (.I0(dout_tmp[16]), + .I1(o3_mode[1]), + .I2(\u3/dout[16]_i_2_n_0 ), + .O(\u3/dout[16]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[16]_i_2 + (.I0(dout_tmp[14]), + .I1(o3_mode[0]), + .I2(dout_tmp[28]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[12]), + .O(\u3/dout[16]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[17]_i_1 + (.I0(dout_tmp[17]), + .I1(o3_mode[1]), + .I2(\u3/dout[17]_i_2_n_0 ), + .O(\u3/dout[17]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[17]_i_2 + (.I0(dout_tmp[15]), + .I1(o3_mode[0]), + .I2(dout_tmp[29]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[13]), + .O(\u3/dout[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[18]_i_1 + (.I0(dout_tmp[18]), + .I1(o3_mode[1]), + .I2(\u3/dout[18]_i_2_n_0 ), + .O(\u3/dout[18]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[18]_i_2 + (.I0(dout_tmp[16]), + .I1(o3_mode[0]), + .I2(dout_tmp[30]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[14]), + .O(\u3/dout[18]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[19]_i_3 + (.I0(dout_tmp[19]), + .I1(o3_mode[1]), + .I2(\u3/dout[19]_i_4_n_0 ), + .O(\u3/dout[19]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[19]_i_4 + (.I0(dout_tmp[17]), + .I1(o3_mode[0]), + .I2(dout_tmp[31]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[15]), + .O(\u3/dout[19]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h8)) + \u3/dout[1]_i_1 + (.I0(o3_mode[1]), + .I1(dout_tmp[1]), + .O(\u3/dout[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT4 #( + .INIT(16'hF888)) + \u3/dout[2]_i_1 + (.I0(dout_tmp[0]), + .I1(o3_mode[0]), + .I2(dout_tmp[2]), + .I3(o3_mode[1]), + .O(\u3/dout[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT4 #( + .INIT(16'hF888)) + \u3/dout[3]_i_1 + (.I0(dout_tmp[1]), + .I1(o3_mode[0]), + .I2(dout_tmp[3]), + .I3(o3_mode[1]), + .O(\u3/dout[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[4]_i_1 + (.I0(dout_tmp[4]), + .I1(o3_mode[1]), + .I2(\u3/dout[4]_i_2_n_0 ), + .O(\u3/dout[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[4]_i_2 + (.I0(dout_tmp[2]), + .I1(o3_mode[0]), + .I2(dout_tmp[16]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[0]), + .O(\u3/dout[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[5]_i_1 + (.I0(dout_tmp[5]), + .I1(o3_mode[1]), + .I2(\u3/dout[5]_i_2_n_0 ), + .O(\u3/dout[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[5]_i_2 + (.I0(dout_tmp[3]), + .I1(o3_mode[0]), + .I2(dout_tmp[17]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[1]), + .O(\u3/dout[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[6]_i_1 + (.I0(dout_tmp[6]), + .I1(o3_mode[1]), + .I2(\u3/dout[6]_i_2_n_0 ), + .O(\u3/dout[6]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[6]_i_2 + (.I0(dout_tmp[4]), + .I1(o3_mode[0]), + .I2(dout_tmp[18]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[2]), + .O(\u3/dout[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[7]_i_1 + (.I0(dout_tmp[7]), + .I1(o3_mode[1]), + .I2(\u3/dout[7]_i_2_n_0 ), + .O(\u3/dout[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[7]_i_2 + (.I0(dout_tmp[5]), + .I1(o3_mode[0]), + .I2(dout_tmp[19]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[3]), + .O(\u3/dout[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[8]_i_1 + (.I0(dout_tmp[8]), + .I1(o3_mode[1]), + .I2(\u3/dout[8]_i_2_n_0 ), + .O(\u3/dout[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[8]_i_2 + (.I0(dout_tmp[6]), + .I1(o3_mode[0]), + .I2(dout_tmp[20]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[4]), + .O(\u3/dout[8]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT3 #( + .INIT(8'hB8)) + \u3/dout[9]_i_1 + (.I0(dout_tmp[9]), + .I1(o3_mode[1]), + .I2(\u3/dout[9]_i_2_n_0 ), + .O(\u3/dout[9]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u3/dout[9]_i_2 + (.I0(dout_tmp[7]), + .I1(o3_mode[0]), + .I2(dout_tmp[21]), + .I3(\u3/rp_reg_n_0_[0] ), + .I4(dout_tmp[5]), + .O(\u3/dout[9]_i_2_n_0 )); + FDRE \u3/dout_reg[0] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[0]_i_1_n_0 ), + .Q(out_slt3[0]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[10] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[10]_i_1_n_0 ), + .Q(out_slt3[10]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[11] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[11]_i_1_n_0 ), + .Q(out_slt3[11]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[12] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[12]_i_1_n_0 ), + .Q(out_slt3[12]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[13] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[13]_i_1_n_0 ), + .Q(out_slt3[13]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[14] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[14]_i_1_n_0 ), + .Q(out_slt3[14]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[15] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[15]_i_1_n_0 ), + .Q(out_slt3[15]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[16] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[16]_i_1_n_0 ), + .Q(out_slt3[16]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[17] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[17]_i_1_n_0 ), + .Q(out_slt3[17]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[18] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[18]_i_1_n_0 ), + .Q(out_slt3[18]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[19] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[19]_i_3_n_0 ), + .Q(out_slt3[19]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[1] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[1]_i_1_n_0 ), + .Q(out_slt3[1]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[2] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[2]_i_1_n_0 ), + .Q(out_slt3[2]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[3] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[3]_i_1_n_0 ), + .Q(out_slt3[3]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[4] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[4]_i_1_n_0 ), + .Q(out_slt3[4]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[5] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[5]_i_1_n_0 ), + .Q(out_slt3[5]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[6] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[6]_i_1_n_0 ), + .Q(out_slt3[6]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[7] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[7]_i_1_n_0 ), + .Q(out_slt3[7]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[8] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[8]_i_1_n_0 ), + .Q(out_slt3[8]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/dout_reg[9] + (.C(clk_i), + .CE(o3_re), + .D(\u3/dout[9]_i_1_n_0 ), + .Q(out_slt3[9]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/empty_reg + (.C(clk_i), + .CE(\ ), + .D(\u3/empty0 ), + .Q(o3_empty), + .R(\ )); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u3/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "0" *) + (* ram_slice_end = "5" *) + RAM32M \u3/mem_reg_0_3_0_5 + (.ADDRA({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u3/wp_reg_n_0_[1] ,\u3/wp_reg_n_0_[0] }), + .DIA(wb_din[1:0]), + .DIB(wb_din[3:2]), + .DIC(wb_din[5:4]), + .DID({\ ,\ }), + .DOA(dout_tmp[1:0]), + .DOB(dout_tmp[3:2]), + .DOC(dout_tmp[5:4]), + .WCLK(clk_i), + .WE(o3_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u3/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "12" *) + (* ram_slice_end = "17" *) + RAM32M \u3/mem_reg_0_3_12_17 + (.ADDRA({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u3/wp_reg_n_0_[1] ,\u3/wp_reg_n_0_[0] }), + .DIA(wb_din[13:12]), + .DIB(wb_din[15:14]), + .DIC(wb_din[17:16]), + .DID({\ ,\ }), + .DOA(dout_tmp[13:12]), + .DOB(dout_tmp[15:14]), + .DOC(dout_tmp[17:16]), + .WCLK(clk_i), + .WE(o3_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u3/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "18" *) + (* ram_slice_end = "23" *) + RAM32M \u3/mem_reg_0_3_18_23 + (.ADDRA({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u3/wp_reg_n_0_[1] ,\u3/wp_reg_n_0_[0] }), + .DIA(wb_din[19:18]), + .DIB(wb_din[21:20]), + .DIC(wb_din[23:22]), + .DID({\ ,\ }), + .DOA(dout_tmp[19:18]), + .DOB(dout_tmp[21:20]), + .DOC(dout_tmp[23:22]), + .WCLK(clk_i), + .WE(o3_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u3/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "24" *) + (* ram_slice_end = "29" *) + RAM32M \u3/mem_reg_0_3_24_29 + (.ADDRA({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u3/wp_reg_n_0_[1] ,\u3/wp_reg_n_0_[0] }), + .DIA(wb_din[25:24]), + .DIB(wb_din[27:26]), + .DIC(wb_din[29:28]), + .DID({\ ,\ }), + .DOA(dout_tmp[25:24]), + .DOB(dout_tmp[27:26]), + .DOC(dout_tmp[29:28]), + .WCLK(clk_i), + .WE(o3_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u3/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u3/mem_reg_0_3_30_31 + (.A0(\u3/wp_reg_n_0_[0] ), + .A1(\u3/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[30]), + .DPO(dout_tmp[30]), + .DPRA0(\u3/p_0_in [0]), + .DPRA1(\u3/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o3_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u3/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u3/mem_reg_0_3_30_31__0 + (.A0(\u3/wp_reg_n_0_[0] ), + .A1(\u3/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[31]), + .DPO(dout_tmp[31]), + .DPRA0(\u3/p_0_in [0]), + .DPRA1(\u3/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o3_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u3/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "6" *) + (* ram_slice_end = "11" *) + RAM32M \u3/mem_reg_0_3_6_11 + (.ADDRA({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u3/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u3/wp_reg_n_0_[1] ,\u3/wp_reg_n_0_[0] }), + .DIA(wb_din[7:6]), + .DIB(wb_din[9:8]), + .DIC(wb_din[11:10]), + .DID({\ ,\ }), + .DOA(dout_tmp[7:6]), + .DOB(dout_tmp[9:8]), + .DOC(dout_tmp[11:10]), + .WCLK(clk_i), + .WE(o3_we)); + FDRE \u3/rp_reg[0] + (.C(clk_i), + .CE(o3_re), + .D(\rp[0]_i_1__2_n_0 ), + .Q(\u3/rp_reg_n_0_[0] ), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/rp_reg[1] + (.C(clk_i), + .CE(o3_re), + .D(p_0_in__2__0[1]), + .Q(\u3/p_0_in [0]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/rp_reg[2] + (.C(clk_i), + .CE(o3_re), + .D(p_0_in__2__0[2]), + .Q(\u3/p_0_in [1]), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/rp_reg[3] + (.C(clk_i), + .CE(o3_re), + .D(p_0_in__2__0[3]), + .Q(\u3/rp_reg_n_0_[3] ), + .R(\dout[19]_i_1_n_0 )); + FDRE \u3/status_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\status[0]_i_1_n_0 ), + .Q(o3_status[0]), + .R(\ )); + FDRE \u3/status_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u3/status0 ), + .Q(o3_status[1]), + .R(\ )); + FDRE \u3/wp_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\wp[0]_i_1_n_0 ), + .Q(\u3/wp_reg_n_0_[0] ), + .R(\ )); + FDRE \u3/wp_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\wp[1]_i_1_n_0 ), + .Q(\u3/wp_reg_n_0_[1] ), + .R(\ )); + FDRE \u3/wp_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\wp[2]_i_1_n_0 ), + .Q(\u3/p_1_in ), + .R(\ )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT2 #( + .INIT(4'h8)) + \u4/dout[0]_i_1 + (.I0(o4_mode[1]), + .I1(dout_tmp__0[0]), + .O(\u4/dout[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[10]_i_1 + (.I0(dout_tmp__0[10]), + .I1(o4_mode[1]), + .I2(\u4/dout[10]_i_2_n_0 ), + .O(\u4/dout[10]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[10]_i_2 + (.I0(dout_tmp__0[8]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[22]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[6]), + .O(\u4/dout[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[11]_i_1 + (.I0(dout_tmp__0[11]), + .I1(o4_mode[1]), + .I2(\u4/dout[11]_i_2_n_0 ), + .O(\u4/dout[11]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[11]_i_2 + (.I0(dout_tmp__0[9]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[23]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[7]), + .O(\u4/dout[11]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[12]_i_1 + (.I0(dout_tmp__0[12]), + .I1(o4_mode[1]), + .I2(\u4/dout[12]_i_2_n_0 ), + .O(\u4/dout[12]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[12]_i_2 + (.I0(dout_tmp__0[10]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[24]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[8]), + .O(\u4/dout[12]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[13]_i_1 + (.I0(dout_tmp__0[13]), + .I1(o4_mode[1]), + .I2(\u4/dout[13]_i_2_n_0 ), + .O(\u4/dout[13]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[13]_i_2 + (.I0(dout_tmp__0[11]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[25]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[9]), + .O(\u4/dout[13]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[14]_i_1 + (.I0(dout_tmp__0[14]), + .I1(o4_mode[1]), + .I2(\u4/dout[14]_i_2_n_0 ), + .O(\u4/dout[14]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[14]_i_2 + (.I0(dout_tmp__0[12]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[26]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[10]), + .O(\u4/dout[14]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[15]_i_1 + (.I0(dout_tmp__0[15]), + .I1(o4_mode[1]), + .I2(\u4/dout[15]_i_2_n_0 ), + .O(\u4/dout[15]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[15]_i_2 + (.I0(dout_tmp__0[13]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[27]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[11]), + .O(\u4/dout[15]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[16]_i_1 + (.I0(dout_tmp__0[16]), + .I1(o4_mode[1]), + .I2(\u4/dout[16]_i_2_n_0 ), + .O(\u4/dout[16]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[16]_i_2 + (.I0(dout_tmp__0[14]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[28]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[12]), + .O(\u4/dout[16]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[17]_i_1 + (.I0(dout_tmp__0[17]), + .I1(o4_mode[1]), + .I2(\u4/dout[17]_i_2_n_0 ), + .O(\u4/dout[17]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[17]_i_2 + (.I0(dout_tmp__0[15]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[29]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[13]), + .O(\u4/dout[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[18]_i_1 + (.I0(dout_tmp__0[18]), + .I1(o4_mode[1]), + .I2(\u4/dout[18]_i_2_n_0 ), + .O(\u4/dout[18]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[18]_i_2 + (.I0(dout_tmp__0[16]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[30]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[14]), + .O(\u4/dout[18]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[19]_i_3 + (.I0(dout_tmp__0[19]), + .I1(o4_mode[1]), + .I2(\u4/dout[19]_i_4_n_0 ), + .O(\u4/dout[19]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[19]_i_4 + (.I0(dout_tmp__0[17]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[31]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[15]), + .O(\u4/dout[19]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT2 #( + .INIT(4'h8)) + \u4/dout[1]_i_1 + (.I0(o4_mode[1]), + .I1(dout_tmp__0[1]), + .O(\u4/dout[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT4 #( + .INIT(16'hF888)) + \u4/dout[2]_i_1 + (.I0(dout_tmp__0[0]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[2]), + .I3(o4_mode[1]), + .O(\u4/dout[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT4 #( + .INIT(16'hF888)) + \u4/dout[3]_i_1 + (.I0(dout_tmp__0[1]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[3]), + .I3(o4_mode[1]), + .O(\u4/dout[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[4]_i_1 + (.I0(dout_tmp__0[4]), + .I1(o4_mode[1]), + .I2(\u4/dout[4]_i_2_n_0 ), + .O(\u4/dout[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[4]_i_2 + (.I0(dout_tmp__0[2]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[16]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[0]), + .O(\u4/dout[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[5]_i_1 + (.I0(dout_tmp__0[5]), + .I1(o4_mode[1]), + .I2(\u4/dout[5]_i_2_n_0 ), + .O(\u4/dout[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[5]_i_2 + (.I0(dout_tmp__0[3]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[17]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[1]), + .O(\u4/dout[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[6]_i_1 + (.I0(dout_tmp__0[6]), + .I1(o4_mode[1]), + .I2(\u4/dout[6]_i_2_n_0 ), + .O(\u4/dout[6]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[6]_i_2 + (.I0(dout_tmp__0[4]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[18]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[2]), + .O(\u4/dout[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[7]_i_1 + (.I0(dout_tmp__0[7]), + .I1(o4_mode[1]), + .I2(\u4/dout[7]_i_2_n_0 ), + .O(\u4/dout[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[7]_i_2 + (.I0(dout_tmp__0[5]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[19]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[3]), + .O(\u4/dout[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[8]_i_1 + (.I0(dout_tmp__0[8]), + .I1(o4_mode[1]), + .I2(\u4/dout[8]_i_2_n_0 ), + .O(\u4/dout[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[8]_i_2 + (.I0(dout_tmp__0[6]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[20]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[4]), + .O(\u4/dout[8]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT3 #( + .INIT(8'hB8)) + \u4/dout[9]_i_1 + (.I0(dout_tmp__0[9]), + .I1(o4_mode[1]), + .I2(\u4/dout[9]_i_2_n_0 ), + .O(\u4/dout[9]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u4/dout[9]_i_2 + (.I0(dout_tmp__0[7]), + .I1(o4_mode[0]), + .I2(dout_tmp__0[21]), + .I3(\u4/rp_reg_n_0_[0] ), + .I4(dout_tmp__0[5]), + .O(\u4/dout[9]_i_2_n_0 )); + FDRE \u4/dout_reg[0] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[0]_i_1_n_0 ), + .Q(out_slt4[0]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[10] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[10]_i_1_n_0 ), + .Q(out_slt4[10]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[11] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[11]_i_1_n_0 ), + .Q(out_slt4[11]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[12] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[12]_i_1_n_0 ), + .Q(out_slt4[12]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[13] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[13]_i_1_n_0 ), + .Q(out_slt4[13]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[14] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[14]_i_1_n_0 ), + .Q(out_slt4[14]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[15] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[15]_i_1_n_0 ), + .Q(out_slt4[15]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[16] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[16]_i_1_n_0 ), + .Q(out_slt4[16]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[17] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[17]_i_1_n_0 ), + .Q(out_slt4[17]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[18] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[18]_i_1_n_0 ), + .Q(out_slt4[18]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[19] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[19]_i_3_n_0 ), + .Q(out_slt4[19]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[1] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[1]_i_1_n_0 ), + .Q(out_slt4[1]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[2] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[2]_i_1_n_0 ), + .Q(out_slt4[2]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[3] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[3]_i_1_n_0 ), + .Q(out_slt4[3]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[4] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[4]_i_1_n_0 ), + .Q(out_slt4[4]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[5] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[5]_i_1_n_0 ), + .Q(out_slt4[5]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[6] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[6]_i_1_n_0 ), + .Q(out_slt4[6]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[7] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[7]_i_1_n_0 ), + .Q(out_slt4[7]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[8] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[8]_i_1_n_0 ), + .Q(out_slt4[8]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/dout_reg[9] + (.C(clk_i), + .CE(o4_re), + .D(\u4/dout[9]_i_1_n_0 ), + .Q(out_slt4[9]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/empty_reg + (.C(clk_i), + .CE(\ ), + .D(\u4/empty0 ), + .Q(o4_empty), + .R(\ )); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u4/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "0" *) + (* ram_slice_end = "5" *) + RAM32M \u4/mem_reg_0_3_0_5 + (.ADDRA({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u4/wp_reg_n_0_[1] ,\u4/wp_reg_n_0_[0] }), + .DIA(wb_din[1:0]), + .DIB(wb_din[3:2]), + .DIC(wb_din[5:4]), + .DID({\ ,\ }), + .DOA(dout_tmp__0[1:0]), + .DOB(dout_tmp__0[3:2]), + .DOC(dout_tmp__0[5:4]), + .WCLK(clk_i), + .WE(o4_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u4/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "12" *) + (* ram_slice_end = "17" *) + RAM32M \u4/mem_reg_0_3_12_17 + (.ADDRA({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u4/wp_reg_n_0_[1] ,\u4/wp_reg_n_0_[0] }), + .DIA(wb_din[13:12]), + .DIB(wb_din[15:14]), + .DIC(wb_din[17:16]), + .DID({\ ,\ }), + .DOA(dout_tmp__0[13:12]), + .DOB(dout_tmp__0[15:14]), + .DOC(dout_tmp__0[17:16]), + .WCLK(clk_i), + .WE(o4_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u4/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "18" *) + (* ram_slice_end = "23" *) + RAM32M \u4/mem_reg_0_3_18_23 + (.ADDRA({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u4/wp_reg_n_0_[1] ,\u4/wp_reg_n_0_[0] }), + .DIA(wb_din[19:18]), + .DIB(wb_din[21:20]), + .DIC(wb_din[23:22]), + .DID({\ ,\ }), + .DOA(dout_tmp__0[19:18]), + .DOB(dout_tmp__0[21:20]), + .DOC(dout_tmp__0[23:22]), + .WCLK(clk_i), + .WE(o4_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u4/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "24" *) + (* ram_slice_end = "29" *) + RAM32M \u4/mem_reg_0_3_24_29 + (.ADDRA({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u4/wp_reg_n_0_[1] ,\u4/wp_reg_n_0_[0] }), + .DIA(wb_din[25:24]), + .DIB(wb_din[27:26]), + .DIC(wb_din[29:28]), + .DID({\ ,\ }), + .DOA(dout_tmp__0[25:24]), + .DOB(dout_tmp__0[27:26]), + .DOC(dout_tmp__0[29:28]), + .WCLK(clk_i), + .WE(o4_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u4/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u4/mem_reg_0_3_30_31 + (.A0(\u4/wp_reg_n_0_[0] ), + .A1(\u4/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[30]), + .DPO(dout_tmp__0[30]), + .DPRA0(\u4/p_0_in [0]), + .DPRA1(\u4/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o4_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u4/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u4/mem_reg_0_3_30_31__0 + (.A0(\u4/wp_reg_n_0_[0] ), + .A1(\u4/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[31]), + .DPO(dout_tmp__0[31]), + .DPRA0(\u4/p_0_in [0]), + .DPRA1(\u4/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o4_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u4/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "6" *) + (* ram_slice_end = "11" *) + RAM32M \u4/mem_reg_0_3_6_11 + (.ADDRA({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u4/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u4/wp_reg_n_0_[1] ,\u4/wp_reg_n_0_[0] }), + .DIA(wb_din[7:6]), + .DIB(wb_din[9:8]), + .DIC(wb_din[11:10]), + .DID({\ ,\ }), + .DOA(dout_tmp__0[7:6]), + .DOB(dout_tmp__0[9:8]), + .DOC(dout_tmp__0[11:10]), + .WCLK(clk_i), + .WE(o4_we)); + FDRE \u4/rp_reg[0] + (.C(clk_i), + .CE(o4_re), + .D(\rp[0]_i_1__3_n_0 ), + .Q(\u4/rp_reg_n_0_[0] ), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/rp_reg[1] + (.C(clk_i), + .CE(o4_re), + .D(p_0_in__3__0[1]), + .Q(\u4/p_0_in [0]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/rp_reg[2] + (.C(clk_i), + .CE(o4_re), + .D(p_0_in__3__0[2]), + .Q(\u4/p_0_in [1]), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/rp_reg[3] + (.C(clk_i), + .CE(o4_re), + .D(p_0_in__3__0[3]), + .Q(\u4/rp_reg_n_0_[3] ), + .R(\dout[19]_i_1__0_n_0 )); + FDRE \u4/status_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\status[0]_i_1__0_n_0 ), + .Q(o4_status[0]), + .R(\ )); + FDRE \u4/status_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u4/status0 ), + .Q(o4_status[1]), + .R(\ )); + FDRE \u4/wp_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\wp[0]_i_1__0_n_0 ), + .Q(\u4/wp_reg_n_0_[0] ), + .R(\ )); + FDRE \u4/wp_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\wp[1]_i_1__0_n_0 ), + .Q(\u4/wp_reg_n_0_[1] ), + .R(\ )); + FDRE \u4/wp_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\wp[2]_i_1__0_n_0 ), + .Q(\u4/p_1_in ), + .R(\ )); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT2 #( + .INIT(4'h8)) + \u5/dout[0]_i_1 + (.I0(o6_mode[1]), + .I1(dout_tmp__1[0]), + .O(\u5/dout[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[10]_i_1 + (.I0(dout_tmp__1[10]), + .I1(o6_mode[1]), + .I2(\u5/dout[10]_i_2_n_0 ), + .O(\u5/dout[10]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[10]_i_2 + (.I0(dout_tmp__1[8]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[22]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[6]), + .O(\u5/dout[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[11]_i_1 + (.I0(dout_tmp__1[11]), + .I1(o6_mode[1]), + .I2(\u5/dout[11]_i_2_n_0 ), + .O(\u5/dout[11]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[11]_i_2 + (.I0(dout_tmp__1[9]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[23]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[7]), + .O(\u5/dout[11]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[12]_i_1 + (.I0(dout_tmp__1[12]), + .I1(o6_mode[1]), + .I2(\u5/dout[12]_i_2_n_0 ), + .O(\u5/dout[12]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[12]_i_2 + (.I0(dout_tmp__1[10]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[24]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[8]), + .O(\u5/dout[12]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[13]_i_1 + (.I0(dout_tmp__1[13]), + .I1(o6_mode[1]), + .I2(\u5/dout[13]_i_2_n_0 ), + .O(\u5/dout[13]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[13]_i_2 + (.I0(dout_tmp__1[11]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[25]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[9]), + .O(\u5/dout[13]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[14]_i_1 + (.I0(dout_tmp__1[14]), + .I1(o6_mode[1]), + .I2(\u5/dout[14]_i_2_n_0 ), + .O(\u5/dout[14]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[14]_i_2 + (.I0(dout_tmp__1[12]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[26]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[10]), + .O(\u5/dout[14]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[15]_i_1 + (.I0(dout_tmp__1[15]), + .I1(o6_mode[1]), + .I2(\u5/dout[15]_i_2_n_0 ), + .O(\u5/dout[15]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[15]_i_2 + (.I0(dout_tmp__1[13]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[27]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[11]), + .O(\u5/dout[15]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[16]_i_1 + (.I0(dout_tmp__1[16]), + .I1(o6_mode[1]), + .I2(\u5/dout[16]_i_2_n_0 ), + .O(\u5/dout[16]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[16]_i_2 + (.I0(dout_tmp__1[14]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[28]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[12]), + .O(\u5/dout[16]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[17]_i_1 + (.I0(dout_tmp__1[17]), + .I1(o6_mode[1]), + .I2(\u5/dout[17]_i_2_n_0 ), + .O(\u5/dout[17]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[17]_i_2 + (.I0(dout_tmp__1[15]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[29]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[13]), + .O(\u5/dout[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[18]_i_1 + (.I0(dout_tmp__1[18]), + .I1(o6_mode[1]), + .I2(\u5/dout[18]_i_2_n_0 ), + .O(\u5/dout[18]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[18]_i_2 + (.I0(dout_tmp__1[16]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[30]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[14]), + .O(\u5/dout[18]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[19]_i_3 + (.I0(dout_tmp__1[19]), + .I1(o6_mode[1]), + .I2(\u5/dout[19]_i_4_n_0 ), + .O(\u5/dout[19]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[19]_i_4 + (.I0(dout_tmp__1[17]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[31]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[15]), + .O(\u5/dout[19]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT2 #( + .INIT(4'h8)) + \u5/dout[1]_i_1 + (.I0(o6_mode[1]), + .I1(dout_tmp__1[1]), + .O(\u5/dout[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT4 #( + .INIT(16'hF888)) + \u5/dout[2]_i_1 + (.I0(dout_tmp__1[0]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[2]), + .I3(o6_mode[1]), + .O(\u5/dout[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT4 #( + .INIT(16'hF888)) + \u5/dout[3]_i_1 + (.I0(dout_tmp__1[1]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[3]), + .I3(o6_mode[1]), + .O(\u5/dout[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[4]_i_1 + (.I0(dout_tmp__1[4]), + .I1(o6_mode[1]), + .I2(\u5/dout[4]_i_2_n_0 ), + .O(\u5/dout[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[4]_i_2 + (.I0(dout_tmp__1[2]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[16]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[0]), + .O(\u5/dout[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[5]_i_1 + (.I0(dout_tmp__1[5]), + .I1(o6_mode[1]), + .I2(\u5/dout[5]_i_2_n_0 ), + .O(\u5/dout[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[5]_i_2 + (.I0(dout_tmp__1[3]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[17]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[1]), + .O(\u5/dout[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[6]_i_1 + (.I0(dout_tmp__1[6]), + .I1(o6_mode[1]), + .I2(\u5/dout[6]_i_2_n_0 ), + .O(\u5/dout[6]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[6]_i_2 + (.I0(dout_tmp__1[4]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[18]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[2]), + .O(\u5/dout[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[7]_i_1 + (.I0(dout_tmp__1[7]), + .I1(o6_mode[1]), + .I2(\u5/dout[7]_i_2_n_0 ), + .O(\u5/dout[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[7]_i_2 + (.I0(dout_tmp__1[5]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[19]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[3]), + .O(\u5/dout[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[8]_i_1 + (.I0(dout_tmp__1[8]), + .I1(o6_mode[1]), + .I2(\u5/dout[8]_i_2_n_0 ), + .O(\u5/dout[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[8]_i_2 + (.I0(dout_tmp__1[6]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[20]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[4]), + .O(\u5/dout[8]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT3 #( + .INIT(8'hB8)) + \u5/dout[9]_i_1 + (.I0(dout_tmp__1[9]), + .I1(o6_mode[1]), + .I2(\u5/dout[9]_i_2_n_0 ), + .O(\u5/dout[9]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u5/dout[9]_i_2 + (.I0(dout_tmp__1[7]), + .I1(o6_mode[0]), + .I2(dout_tmp__1[21]), + .I3(\u5/rp_reg_n_0_[0] ), + .I4(dout_tmp__1[5]), + .O(\u5/dout[9]_i_2_n_0 )); + FDRE \u5/dout_reg[0] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[0]_i_1_n_0 ), + .Q(out_slt6[0]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[10] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[10]_i_1_n_0 ), + .Q(out_slt6[10]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[11] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[11]_i_1_n_0 ), + .Q(out_slt6[11]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[12] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[12]_i_1_n_0 ), + .Q(out_slt6[12]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[13] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[13]_i_1_n_0 ), + .Q(out_slt6[13]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[14] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[14]_i_1_n_0 ), + .Q(out_slt6[14]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[15] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[15]_i_1_n_0 ), + .Q(out_slt6[15]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[16] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[16]_i_1_n_0 ), + .Q(out_slt6[16]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[17] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[17]_i_1_n_0 ), + .Q(out_slt6[17]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[18] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[18]_i_1_n_0 ), + .Q(out_slt6[18]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[19] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[19]_i_3_n_0 ), + .Q(out_slt6[19]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[1] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[1]_i_1_n_0 ), + .Q(out_slt6[1]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[2] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[2]_i_1_n_0 ), + .Q(out_slt6[2]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[3] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[3]_i_1_n_0 ), + .Q(out_slt6[3]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[4] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[4]_i_1_n_0 ), + .Q(out_slt6[4]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[5] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[5]_i_1_n_0 ), + .Q(out_slt6[5]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[6] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[6]_i_1_n_0 ), + .Q(out_slt6[6]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[7] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[7]_i_1_n_0 ), + .Q(out_slt6[7]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[8] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[8]_i_1_n_0 ), + .Q(out_slt6[8]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/dout_reg[9] + (.C(clk_i), + .CE(o6_re), + .D(\u5/dout[9]_i_1_n_0 ), + .Q(out_slt6[9]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/empty_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/empty0 ), + .Q(o6_empty), + .R(\ )); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u5/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "0" *) + (* ram_slice_end = "5" *) + RAM32M \u5/mem_reg_0_3_0_5 + (.ADDRA({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u5/wp_reg_n_0_[1] ,\u5/wp_reg_n_0_[0] }), + .DIA(wb_din[1:0]), + .DIB(wb_din[3:2]), + .DIC(wb_din[5:4]), + .DID({\ ,\ }), + .DOA(dout_tmp__1[1:0]), + .DOB(dout_tmp__1[3:2]), + .DOC(dout_tmp__1[5:4]), + .WCLK(clk_i), + .WE(o6_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u5/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "12" *) + (* ram_slice_end = "17" *) + RAM32M \u5/mem_reg_0_3_12_17 + (.ADDRA({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u5/wp_reg_n_0_[1] ,\u5/wp_reg_n_0_[0] }), + .DIA(wb_din[13:12]), + .DIB(wb_din[15:14]), + .DIC(wb_din[17:16]), + .DID({\ ,\ }), + .DOA(dout_tmp__1[13:12]), + .DOB(dout_tmp__1[15:14]), + .DOC(dout_tmp__1[17:16]), + .WCLK(clk_i), + .WE(o6_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u5/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "18" *) + (* ram_slice_end = "23" *) + RAM32M \u5/mem_reg_0_3_18_23 + (.ADDRA({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u5/wp_reg_n_0_[1] ,\u5/wp_reg_n_0_[0] }), + .DIA(wb_din[19:18]), + .DIB(wb_din[21:20]), + .DIC(wb_din[23:22]), + .DID({\ ,\ }), + .DOA(dout_tmp__1[19:18]), + .DOB(dout_tmp__1[21:20]), + .DOC(dout_tmp__1[23:22]), + .WCLK(clk_i), + .WE(o6_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u5/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "24" *) + (* ram_slice_end = "29" *) + RAM32M \u5/mem_reg_0_3_24_29 + (.ADDRA({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u5/wp_reg_n_0_[1] ,\u5/wp_reg_n_0_[0] }), + .DIA(wb_din[25:24]), + .DIB(wb_din[27:26]), + .DIC(wb_din[29:28]), + .DID({\ ,\ }), + .DOA(dout_tmp__1[25:24]), + .DOB(dout_tmp__1[27:26]), + .DOC(dout_tmp__1[29:28]), + .WCLK(clk_i), + .WE(o6_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u5/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u5/mem_reg_0_3_30_31 + (.A0(\u5/wp_reg_n_0_[0] ), + .A1(\u5/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[30]), + .DPO(dout_tmp__1[30]), + .DPRA0(\u5/p_0_in [0]), + .DPRA1(\u5/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o6_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u5/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u5/mem_reg_0_3_30_31__0 + (.A0(\u5/wp_reg_n_0_[0] ), + .A1(\u5/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[31]), + .DPO(dout_tmp__1[31]), + .DPRA0(\u5/p_0_in [0]), + .DPRA1(\u5/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o6_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u5/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "6" *) + (* ram_slice_end = "11" *) + RAM32M \u5/mem_reg_0_3_6_11 + (.ADDRA({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u5/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u5/wp_reg_n_0_[1] ,\u5/wp_reg_n_0_[0] }), + .DIA(wb_din[7:6]), + .DIB(wb_din[9:8]), + .DIC(wb_din[11:10]), + .DID({\ ,\ }), + .DOA(dout_tmp__1[7:6]), + .DOB(dout_tmp__1[9:8]), + .DOC(dout_tmp__1[11:10]), + .WCLK(clk_i), + .WE(o6_we)); + FDRE \u5/rp_reg[0] + (.C(clk_i), + .CE(o6_re), + .D(\rp[0]_i_1__4_n_0 ), + .Q(\u5/rp_reg_n_0_[0] ), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/rp_reg[1] + (.C(clk_i), + .CE(o6_re), + .D(p_0_in__4[1]), + .Q(\u5/p_0_in [0]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/rp_reg[2] + (.C(clk_i), + .CE(o6_re), + .D(p_0_in__4[2]), + .Q(\u5/p_0_in [1]), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/rp_reg[3] + (.C(clk_i), + .CE(o6_re), + .D(p_0_in__4[3]), + .Q(\u5/rp_reg_n_0_[3] ), + .R(\dout[19]_i_1__1_n_0 )); + FDRE \u5/status_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\status[0]_i_1__1_n_0 ), + .Q(o6_status[0]), + .R(\ )); + FDRE \u5/status_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u5/status0 ), + .Q(o6_status[1]), + .R(\ )); + FDRE \u5/wp_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\wp[0]_i_1__1_n_0 ), + .Q(\u5/wp_reg_n_0_[0] ), + .R(\ )); + FDRE \u5/wp_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\wp[1]_i_1__1_n_0 ), + .Q(\u5/wp_reg_n_0_[1] ), + .R(\ )); + FDRE \u5/wp_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\wp[2]_i_1__1_n_0 ), + .Q(\u5/p_1_in ), + .R(\ )); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT2 #( + .INIT(4'h8)) + \u6/dout[0]_i_1 + (.I0(o7_mode[1]), + .I1(dout_tmp__2[0]), + .O(\u6/dout[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[10]_i_1 + (.I0(dout_tmp__2[10]), + .I1(o7_mode[1]), + .I2(\u6/dout[10]_i_2_n_0 ), + .O(\u6/dout[10]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[10]_i_2 + (.I0(dout_tmp__2[8]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[22]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[6]), + .O(\u6/dout[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[11]_i_1 + (.I0(dout_tmp__2[11]), + .I1(o7_mode[1]), + .I2(\u6/dout[11]_i_2_n_0 ), + .O(\u6/dout[11]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[11]_i_2 + (.I0(dout_tmp__2[9]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[23]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[7]), + .O(\u6/dout[11]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[12]_i_1 + (.I0(dout_tmp__2[12]), + .I1(o7_mode[1]), + .I2(\u6/dout[12]_i_2_n_0 ), + .O(\u6/dout[12]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[12]_i_2 + (.I0(dout_tmp__2[10]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[24]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[8]), + .O(\u6/dout[12]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[13]_i_1 + (.I0(dout_tmp__2[13]), + .I1(o7_mode[1]), + .I2(\u6/dout[13]_i_2_n_0 ), + .O(\u6/dout[13]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[13]_i_2 + (.I0(dout_tmp__2[11]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[25]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[9]), + .O(\u6/dout[13]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[14]_i_1 + (.I0(dout_tmp__2[14]), + .I1(o7_mode[1]), + .I2(\u6/dout[14]_i_2_n_0 ), + .O(\u6/dout[14]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[14]_i_2 + (.I0(dout_tmp__2[12]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[26]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[10]), + .O(\u6/dout[14]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[15]_i_1 + (.I0(dout_tmp__2[15]), + .I1(o7_mode[1]), + .I2(\u6/dout[15]_i_2_n_0 ), + .O(\u6/dout[15]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[15]_i_2 + (.I0(dout_tmp__2[13]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[27]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[11]), + .O(\u6/dout[15]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[16]_i_1 + (.I0(dout_tmp__2[16]), + .I1(o7_mode[1]), + .I2(\u6/dout[16]_i_2_n_0 ), + .O(\u6/dout[16]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[16]_i_2 + (.I0(dout_tmp__2[14]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[28]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[12]), + .O(\u6/dout[16]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[17]_i_1 + (.I0(dout_tmp__2[17]), + .I1(o7_mode[1]), + .I2(\u6/dout[17]_i_2_n_0 ), + .O(\u6/dout[17]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[17]_i_2 + (.I0(dout_tmp__2[15]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[29]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[13]), + .O(\u6/dout[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[18]_i_1 + (.I0(dout_tmp__2[18]), + .I1(o7_mode[1]), + .I2(\u6/dout[18]_i_2_n_0 ), + .O(\u6/dout[18]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[18]_i_2 + (.I0(dout_tmp__2[16]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[30]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[14]), + .O(\u6/dout[18]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[19]_i_3 + (.I0(dout_tmp__2[19]), + .I1(o7_mode[1]), + .I2(\u6/dout[19]_i_4_n_0 ), + .O(\u6/dout[19]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[19]_i_4 + (.I0(dout_tmp__2[17]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[31]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[15]), + .O(\u6/dout[19]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT2 #( + .INIT(4'h8)) + \u6/dout[1]_i_1 + (.I0(o7_mode[1]), + .I1(dout_tmp__2[1]), + .O(\u6/dout[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT4 #( + .INIT(16'hF888)) + \u6/dout[2]_i_1 + (.I0(dout_tmp__2[0]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[2]), + .I3(o7_mode[1]), + .O(\u6/dout[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT4 #( + .INIT(16'hF888)) + \u6/dout[3]_i_1 + (.I0(dout_tmp__2[1]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[3]), + .I3(o7_mode[1]), + .O(\u6/dout[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[4]_i_1 + (.I0(dout_tmp__2[4]), + .I1(o7_mode[1]), + .I2(\u6/dout[4]_i_2_n_0 ), + .O(\u6/dout[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[4]_i_2 + (.I0(dout_tmp__2[2]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[16]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[0]), + .O(\u6/dout[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[5]_i_1 + (.I0(dout_tmp__2[5]), + .I1(o7_mode[1]), + .I2(\u6/dout[5]_i_2_n_0 ), + .O(\u6/dout[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[5]_i_2 + (.I0(dout_tmp__2[3]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[17]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[1]), + .O(\u6/dout[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[6]_i_1 + (.I0(dout_tmp__2[6]), + .I1(o7_mode[1]), + .I2(\u6/dout[6]_i_2_n_0 ), + .O(\u6/dout[6]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[6]_i_2 + (.I0(dout_tmp__2[4]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[18]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[2]), + .O(\u6/dout[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[7]_i_1 + (.I0(dout_tmp__2[7]), + .I1(o7_mode[1]), + .I2(\u6/dout[7]_i_2_n_0 ), + .O(\u6/dout[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[7]_i_2 + (.I0(dout_tmp__2[5]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[19]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[3]), + .O(\u6/dout[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[8]_i_1 + (.I0(dout_tmp__2[8]), + .I1(o7_mode[1]), + .I2(\u6/dout[8]_i_2_n_0 ), + .O(\u6/dout[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[8]_i_2 + (.I0(dout_tmp__2[6]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[20]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[4]), + .O(\u6/dout[8]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT3 #( + .INIT(8'hB8)) + \u6/dout[9]_i_1 + (.I0(dout_tmp__2[9]), + .I1(o7_mode[1]), + .I2(\u6/dout[9]_i_2_n_0 ), + .O(\u6/dout[9]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u6/dout[9]_i_2 + (.I0(dout_tmp__2[7]), + .I1(o7_mode[0]), + .I2(dout_tmp__2[21]), + .I3(\u6/rp_reg_n_0_[0] ), + .I4(dout_tmp__2[5]), + .O(\u6/dout[9]_i_2_n_0 )); + FDRE \u6/dout_reg[0] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[0]_i_1_n_0 ), + .Q(out_slt7[0]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[10] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[10]_i_1_n_0 ), + .Q(out_slt7[10]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[11] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[11]_i_1_n_0 ), + .Q(out_slt7[11]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[12] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[12]_i_1_n_0 ), + .Q(out_slt7[12]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[13] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[13]_i_1_n_0 ), + .Q(out_slt7[13]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[14] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[14]_i_1_n_0 ), + .Q(out_slt7[14]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[15] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[15]_i_1_n_0 ), + .Q(out_slt7[15]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[16] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[16]_i_1_n_0 ), + .Q(out_slt7[16]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[17] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[17]_i_1_n_0 ), + .Q(out_slt7[17]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[18] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[18]_i_1_n_0 ), + .Q(out_slt7[18]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[19] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[19]_i_3_n_0 ), + .Q(out_slt7[19]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[1] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[1]_i_1_n_0 ), + .Q(out_slt7[1]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[2] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[2]_i_1_n_0 ), + .Q(out_slt7[2]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[3] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[3]_i_1_n_0 ), + .Q(out_slt7[3]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[4] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[4]_i_1_n_0 ), + .Q(out_slt7[4]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[5] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[5]_i_1_n_0 ), + .Q(out_slt7[5]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[6] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[6]_i_1_n_0 ), + .Q(out_slt7[6]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[7] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[7]_i_1_n_0 ), + .Q(out_slt7[7]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[8] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[8]_i_1_n_0 ), + .Q(out_slt7[8]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/dout_reg[9] + (.C(clk_i), + .CE(o7_re), + .D(\u6/dout[9]_i_1_n_0 ), + .Q(out_slt7[9]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/empty_reg + (.C(clk_i), + .CE(\ ), + .D(\u6/empty0 ), + .Q(o7_empty), + .R(\ )); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u6/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "0" *) + (* ram_slice_end = "5" *) + RAM32M \u6/mem_reg_0_3_0_5 + (.ADDRA({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u6/wp_reg_n_0_[1] ,\u6/wp_reg_n_0_[0] }), + .DIA(wb_din[1:0]), + .DIB(wb_din[3:2]), + .DIC(wb_din[5:4]), + .DID({\ ,\ }), + .DOA(dout_tmp__2[1:0]), + .DOB(dout_tmp__2[3:2]), + .DOC(dout_tmp__2[5:4]), + .WCLK(clk_i), + .WE(o7_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u6/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "12" *) + (* ram_slice_end = "17" *) + RAM32M \u6/mem_reg_0_3_12_17 + (.ADDRA({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u6/wp_reg_n_0_[1] ,\u6/wp_reg_n_0_[0] }), + .DIA(wb_din[13:12]), + .DIB(wb_din[15:14]), + .DIC(wb_din[17:16]), + .DID({\ ,\ }), + .DOA(dout_tmp__2[13:12]), + .DOB(dout_tmp__2[15:14]), + .DOC(dout_tmp__2[17:16]), + .WCLK(clk_i), + .WE(o7_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u6/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "18" *) + (* ram_slice_end = "23" *) + RAM32M \u6/mem_reg_0_3_18_23 + (.ADDRA({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u6/wp_reg_n_0_[1] ,\u6/wp_reg_n_0_[0] }), + .DIA(wb_din[19:18]), + .DIB(wb_din[21:20]), + .DIC(wb_din[23:22]), + .DID({\ ,\ }), + .DOA(dout_tmp__2[19:18]), + .DOB(dout_tmp__2[21:20]), + .DOC(dout_tmp__2[23:22]), + .WCLK(clk_i), + .WE(o7_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u6/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "24" *) + (* ram_slice_end = "29" *) + RAM32M \u6/mem_reg_0_3_24_29 + (.ADDRA({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u6/wp_reg_n_0_[1] ,\u6/wp_reg_n_0_[0] }), + .DIA(wb_din[25:24]), + .DIB(wb_din[27:26]), + .DIC(wb_din[29:28]), + .DID({\ ,\ }), + .DOA(dout_tmp__2[25:24]), + .DOB(dout_tmp__2[27:26]), + .DOC(dout_tmp__2[29:28]), + .WCLK(clk_i), + .WE(o7_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u6/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u6/mem_reg_0_3_30_31 + (.A0(\u6/wp_reg_n_0_[0] ), + .A1(\u6/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[30]), + .DPO(dout_tmp__2[30]), + .DPRA0(\u6/p_0_in [0]), + .DPRA1(\u6/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o7_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u6/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u6/mem_reg_0_3_30_31__0 + (.A0(\u6/wp_reg_n_0_[0] ), + .A1(\u6/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[31]), + .DPO(dout_tmp__2[31]), + .DPRA0(\u6/p_0_in [0]), + .DPRA1(\u6/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o7_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u6/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "6" *) + (* ram_slice_end = "11" *) + RAM32M \u6/mem_reg_0_3_6_11 + (.ADDRA({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u6/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u6/wp_reg_n_0_[1] ,\u6/wp_reg_n_0_[0] }), + .DIA(wb_din[7:6]), + .DIB(wb_din[9:8]), + .DIC(wb_din[11:10]), + .DID({\ ,\ }), + .DOA(dout_tmp__2[7:6]), + .DOB(dout_tmp__2[9:8]), + .DOC(dout_tmp__2[11:10]), + .WCLK(clk_i), + .WE(o7_we)); + FDRE \u6/rp_reg[0] + (.C(clk_i), + .CE(o7_re), + .D(\rp[0]_i_1__5_n_0 ), + .Q(\u6/rp_reg_n_0_[0] ), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/rp_reg[1] + (.C(clk_i), + .CE(o7_re), + .D(p_0_in__5[1]), + .Q(\u6/p_0_in [0]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/rp_reg[2] + (.C(clk_i), + .CE(o7_re), + .D(p_0_in__5[2]), + .Q(\u6/p_0_in [1]), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/rp_reg[3] + (.C(clk_i), + .CE(o7_re), + .D(p_0_in__5[3]), + .Q(\u6/rp_reg_n_0_[3] ), + .R(\dout[19]_i_1__2_n_0 )); + FDRE \u6/status_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\status[0]_i_1__2_n_0 ), + .Q(o7_status[0]), + .R(\ )); + FDRE \u6/status_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u6/status0 ), + .Q(o7_status[1]), + .R(\ )); + FDRE \u6/wp_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\wp[0]_i_1__2_n_0 ), + .Q(\u6/wp_reg_n_0_[0] ), + .R(\ )); + FDRE \u6/wp_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\wp[1]_i_1__2_n_0 ), + .Q(\u6/wp_reg_n_0_[1] ), + .R(\ )); + FDRE \u6/wp_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\wp[2]_i_1__2_n_0 ), + .Q(\u6/p_1_in ), + .R(\ )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT2 #( + .INIT(4'h8)) + \u7/dout[0]_i_1 + (.I0(o8_mode[1]), + .I1(dout_tmp__3[0]), + .O(\u7/dout[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[10]_i_1 + (.I0(dout_tmp__3[10]), + .I1(o8_mode[1]), + .I2(\u7/dout[10]_i_2_n_0 ), + .O(\u7/dout[10]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[10]_i_2 + (.I0(dout_tmp__3[8]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[22]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[6]), + .O(\u7/dout[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[11]_i_1 + (.I0(dout_tmp__3[11]), + .I1(o8_mode[1]), + .I2(\u7/dout[11]_i_2_n_0 ), + .O(\u7/dout[11]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[11]_i_2 + (.I0(dout_tmp__3[9]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[23]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[7]), + .O(\u7/dout[11]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[12]_i_1 + (.I0(dout_tmp__3[12]), + .I1(o8_mode[1]), + .I2(\u7/dout[12]_i_2_n_0 ), + .O(\u7/dout[12]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[12]_i_2 + (.I0(dout_tmp__3[10]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[24]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[8]), + .O(\u7/dout[12]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[13]_i_1 + (.I0(dout_tmp__3[13]), + .I1(o8_mode[1]), + .I2(\u7/dout[13]_i_2_n_0 ), + .O(\u7/dout[13]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[13]_i_2 + (.I0(dout_tmp__3[11]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[25]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[9]), + .O(\u7/dout[13]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[14]_i_1 + (.I0(dout_tmp__3[14]), + .I1(o8_mode[1]), + .I2(\u7/dout[14]_i_2_n_0 ), + .O(\u7/dout[14]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[14]_i_2 + (.I0(dout_tmp__3[12]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[26]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[10]), + .O(\u7/dout[14]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[15]_i_1 + (.I0(dout_tmp__3[15]), + .I1(o8_mode[1]), + .I2(\u7/dout[15]_i_2_n_0 ), + .O(\u7/dout[15]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[15]_i_2 + (.I0(dout_tmp__3[13]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[27]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[11]), + .O(\u7/dout[15]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[16]_i_1 + (.I0(dout_tmp__3[16]), + .I1(o8_mode[1]), + .I2(\u7/dout[16]_i_2_n_0 ), + .O(\u7/dout[16]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[16]_i_2 + (.I0(dout_tmp__3[14]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[28]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[12]), + .O(\u7/dout[16]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[17]_i_1 + (.I0(dout_tmp__3[17]), + .I1(o8_mode[1]), + .I2(\u7/dout[17]_i_2_n_0 ), + .O(\u7/dout[17]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[17]_i_2 + (.I0(dout_tmp__3[15]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[29]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[13]), + .O(\u7/dout[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[18]_i_1 + (.I0(dout_tmp__3[18]), + .I1(o8_mode[1]), + .I2(\u7/dout[18]_i_2_n_0 ), + .O(\u7/dout[18]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[18]_i_2 + (.I0(dout_tmp__3[16]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[30]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[14]), + .O(\u7/dout[18]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[19]_i_3 + (.I0(dout_tmp__3[19]), + .I1(o8_mode[1]), + .I2(\u7/dout[19]_i_4_n_0 ), + .O(\u7/dout[19]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[19]_i_4 + (.I0(dout_tmp__3[17]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[31]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[15]), + .O(\u7/dout[19]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT2 #( + .INIT(4'h8)) + \u7/dout[1]_i_1 + (.I0(o8_mode[1]), + .I1(dout_tmp__3[1]), + .O(\u7/dout[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT4 #( + .INIT(16'hF888)) + \u7/dout[2]_i_1 + (.I0(dout_tmp__3[0]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[2]), + .I3(o8_mode[1]), + .O(\u7/dout[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT4 #( + .INIT(16'hF888)) + \u7/dout[3]_i_1 + (.I0(dout_tmp__3[1]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[3]), + .I3(o8_mode[1]), + .O(\u7/dout[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[4]_i_1 + (.I0(dout_tmp__3[4]), + .I1(o8_mode[1]), + .I2(\u7/dout[4]_i_2_n_0 ), + .O(\u7/dout[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[4]_i_2 + (.I0(dout_tmp__3[2]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[16]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[0]), + .O(\u7/dout[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[5]_i_1 + (.I0(dout_tmp__3[5]), + .I1(o8_mode[1]), + .I2(\u7/dout[5]_i_2_n_0 ), + .O(\u7/dout[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[5]_i_2 + (.I0(dout_tmp__3[3]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[17]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[1]), + .O(\u7/dout[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[6]_i_1 + (.I0(dout_tmp__3[6]), + .I1(o8_mode[1]), + .I2(\u7/dout[6]_i_2_n_0 ), + .O(\u7/dout[6]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[6]_i_2 + (.I0(dout_tmp__3[4]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[18]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[2]), + .O(\u7/dout[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[7]_i_1 + (.I0(dout_tmp__3[7]), + .I1(o8_mode[1]), + .I2(\u7/dout[7]_i_2_n_0 ), + .O(\u7/dout[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[7]_i_2 + (.I0(dout_tmp__3[5]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[19]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[3]), + .O(\u7/dout[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[8]_i_1 + (.I0(dout_tmp__3[8]), + .I1(o8_mode[1]), + .I2(\u7/dout[8]_i_2_n_0 ), + .O(\u7/dout[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[8]_i_2 + (.I0(dout_tmp__3[6]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[20]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[4]), + .O(\u7/dout[8]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'hB8)) + \u7/dout[9]_i_1 + (.I0(dout_tmp__3[9]), + .I1(o8_mode[1]), + .I2(\u7/dout[9]_i_2_n_0 ), + .O(\u7/dout[9]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u7/dout[9]_i_2 + (.I0(dout_tmp__3[7]), + .I1(o8_mode[0]), + .I2(dout_tmp__3[21]), + .I3(\u7/rp_reg_n_0_[0] ), + .I4(dout_tmp__3[5]), + .O(\u7/dout[9]_i_2_n_0 )); + FDRE \u7/dout_reg[0] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[0]_i_1_n_0 ), + .Q(out_slt8[0]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[10] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[10]_i_1_n_0 ), + .Q(out_slt8[10]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[11] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[11]_i_1_n_0 ), + .Q(out_slt8[11]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[12] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[12]_i_1_n_0 ), + .Q(out_slt8[12]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[13] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[13]_i_1_n_0 ), + .Q(out_slt8[13]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[14] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[14]_i_1_n_0 ), + .Q(out_slt8[14]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[15] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[15]_i_1_n_0 ), + .Q(out_slt8[15]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[16] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[16]_i_1_n_0 ), + .Q(out_slt8[16]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[17] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[17]_i_1_n_0 ), + .Q(out_slt8[17]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[18] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[18]_i_1_n_0 ), + .Q(out_slt8[18]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[19] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[19]_i_3_n_0 ), + .Q(out_slt8[19]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[1] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[1]_i_1_n_0 ), + .Q(out_slt8[1]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[2] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[2]_i_1_n_0 ), + .Q(out_slt8[2]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[3] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[3]_i_1_n_0 ), + .Q(out_slt8[3]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[4] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[4]_i_1_n_0 ), + .Q(out_slt8[4]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[5] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[5]_i_1_n_0 ), + .Q(out_slt8[5]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[6] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[6]_i_1_n_0 ), + .Q(out_slt8[6]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[7] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[7]_i_1_n_0 ), + .Q(out_slt8[7]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[8] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[8]_i_1_n_0 ), + .Q(out_slt8[8]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/dout_reg[9] + (.C(clk_i), + .CE(o8_re), + .D(\u7/dout[9]_i_1_n_0 ), + .Q(out_slt8[9]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/empty_reg + (.C(clk_i), + .CE(\ ), + .D(\u7/empty0 ), + .Q(o8_empty), + .R(\ )); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u7/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "0" *) + (* ram_slice_end = "5" *) + RAM32M \u7/mem_reg_0_3_0_5 + (.ADDRA({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u7/wp_reg_n_0_[1] ,\u7/wp_reg_n_0_[0] }), + .DIA(wb_din[1:0]), + .DIB(wb_din[3:2]), + .DIC(wb_din[5:4]), + .DID({\ ,\ }), + .DOA(dout_tmp__3[1:0]), + .DOB(dout_tmp__3[3:2]), + .DOC(dout_tmp__3[5:4]), + .WCLK(clk_i), + .WE(o8_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u7/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "12" *) + (* ram_slice_end = "17" *) + RAM32M \u7/mem_reg_0_3_12_17 + (.ADDRA({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u7/wp_reg_n_0_[1] ,\u7/wp_reg_n_0_[0] }), + .DIA(wb_din[13:12]), + .DIB(wb_din[15:14]), + .DIC(wb_din[17:16]), + .DID({\ ,\ }), + .DOA(dout_tmp__3[13:12]), + .DOB(dout_tmp__3[15:14]), + .DOC(dout_tmp__3[17:16]), + .WCLK(clk_i), + .WE(o8_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u7/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "18" *) + (* ram_slice_end = "23" *) + RAM32M \u7/mem_reg_0_3_18_23 + (.ADDRA({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u7/wp_reg_n_0_[1] ,\u7/wp_reg_n_0_[0] }), + .DIA(wb_din[19:18]), + .DIB(wb_din[21:20]), + .DIC(wb_din[23:22]), + .DID({\ ,\ }), + .DOA(dout_tmp__3[19:18]), + .DOB(dout_tmp__3[21:20]), + .DOC(dout_tmp__3[23:22]), + .WCLK(clk_i), + .WE(o8_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u7/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "24" *) + (* ram_slice_end = "29" *) + RAM32M \u7/mem_reg_0_3_24_29 + (.ADDRA({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u7/wp_reg_n_0_[1] ,\u7/wp_reg_n_0_[0] }), + .DIA(wb_din[25:24]), + .DIB(wb_din[27:26]), + .DIC(wb_din[29:28]), + .DID({\ ,\ }), + .DOA(dout_tmp__3[25:24]), + .DOB(dout_tmp__3[27:26]), + .DOC(dout_tmp__3[29:28]), + .WCLK(clk_i), + .WE(o8_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u7/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u7/mem_reg_0_3_30_31 + (.A0(\u7/wp_reg_n_0_[0] ), + .A1(\u7/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[30]), + .DPO(dout_tmp__3[30]), + .DPRA0(\u7/p_0_in [0]), + .DPRA1(\u7/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o8_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u7/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u7/mem_reg_0_3_30_31__0 + (.A0(\u7/wp_reg_n_0_[0] ), + .A1(\u7/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[31]), + .DPO(dout_tmp__3[31]), + .DPRA0(\u7/p_0_in [0]), + .DPRA1(\u7/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o8_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u7/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "6" *) + (* ram_slice_end = "11" *) + RAM32M \u7/mem_reg_0_3_6_11 + (.ADDRA({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u7/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u7/wp_reg_n_0_[1] ,\u7/wp_reg_n_0_[0] }), + .DIA(wb_din[7:6]), + .DIB(wb_din[9:8]), + .DIC(wb_din[11:10]), + .DID({\ ,\ }), + .DOA(dout_tmp__3[7:6]), + .DOB(dout_tmp__3[9:8]), + .DOC(dout_tmp__3[11:10]), + .WCLK(clk_i), + .WE(o8_we)); + FDRE \u7/rp_reg[0] + (.C(clk_i), + .CE(o8_re), + .D(\rp[0]_i_1__6_n_0 ), + .Q(\u7/rp_reg_n_0_[0] ), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/rp_reg[1] + (.C(clk_i), + .CE(o8_re), + .D(p_0_in__6[1]), + .Q(\u7/p_0_in [0]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/rp_reg[2] + (.C(clk_i), + .CE(o8_re), + .D(p_0_in__6[2]), + .Q(\u7/p_0_in [1]), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/rp_reg[3] + (.C(clk_i), + .CE(o8_re), + .D(p_0_in__6[3]), + .Q(\u7/rp_reg_n_0_[3] ), + .R(\dout[19]_i_1__3_n_0 )); + FDRE \u7/status_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\status[0]_i_1__3_n_0 ), + .Q(o8_status[0]), + .R(\ )); + FDRE \u7/status_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u7/status0 ), + .Q(o8_status[1]), + .R(\ )); + FDRE \u7/wp_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\wp[0]_i_1__3_n_0 ), + .Q(\u7/wp_reg_n_0_[0] ), + .R(\ )); + FDRE \u7/wp_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\wp[1]_i_1__3_n_0 ), + .Q(\u7/wp_reg_n_0_[1] ), + .R(\ )); + FDRE \u7/wp_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\wp[2]_i_1__3_n_0 ), + .Q(\u7/p_1_in ), + .R(\ )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT2 #( + .INIT(4'h8)) + \u8/dout[0]_i_1 + (.I0(o9_mode[1]), + .I1(dout_tmp__4[0]), + .O(\u8/dout[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[10]_i_1 + (.I0(dout_tmp__4[10]), + .I1(o9_mode[1]), + .I2(\u8/dout[10]_i_2_n_0 ), + .O(\u8/dout[10]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[10]_i_2 + (.I0(dout_tmp__4[8]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[22]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[6]), + .O(\u8/dout[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[11]_i_1 + (.I0(dout_tmp__4[11]), + .I1(o9_mode[1]), + .I2(\u8/dout[11]_i_2_n_0 ), + .O(\u8/dout[11]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[11]_i_2 + (.I0(dout_tmp__4[9]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[23]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[7]), + .O(\u8/dout[11]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[12]_i_1 + (.I0(dout_tmp__4[12]), + .I1(o9_mode[1]), + .I2(\u8/dout[12]_i_2_n_0 ), + .O(\u8/dout[12]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[12]_i_2 + (.I0(dout_tmp__4[10]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[24]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[8]), + .O(\u8/dout[12]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[13]_i_1 + (.I0(dout_tmp__4[13]), + .I1(o9_mode[1]), + .I2(\u8/dout[13]_i_2_n_0 ), + .O(\u8/dout[13]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[13]_i_2 + (.I0(dout_tmp__4[11]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[25]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[9]), + .O(\u8/dout[13]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[14]_i_1 + (.I0(dout_tmp__4[14]), + .I1(o9_mode[1]), + .I2(\u8/dout[14]_i_2_n_0 ), + .O(\u8/dout[14]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[14]_i_2 + (.I0(dout_tmp__4[12]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[26]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[10]), + .O(\u8/dout[14]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[15]_i_1 + (.I0(dout_tmp__4[15]), + .I1(o9_mode[1]), + .I2(\u8/dout[15]_i_2_n_0 ), + .O(\u8/dout[15]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[15]_i_2 + (.I0(dout_tmp__4[13]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[27]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[11]), + .O(\u8/dout[15]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[16]_i_1 + (.I0(dout_tmp__4[16]), + .I1(o9_mode[1]), + .I2(\u8/dout[16]_i_2_n_0 ), + .O(\u8/dout[16]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[16]_i_2 + (.I0(dout_tmp__4[14]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[28]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[12]), + .O(\u8/dout[16]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[17]_i_1 + (.I0(dout_tmp__4[17]), + .I1(o9_mode[1]), + .I2(\u8/dout[17]_i_2_n_0 ), + .O(\u8/dout[17]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[17]_i_2 + (.I0(dout_tmp__4[15]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[29]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[13]), + .O(\u8/dout[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[18]_i_1 + (.I0(dout_tmp__4[18]), + .I1(o9_mode[1]), + .I2(\u8/dout[18]_i_2_n_0 ), + .O(\u8/dout[18]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[18]_i_2 + (.I0(dout_tmp__4[16]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[30]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[14]), + .O(\u8/dout[18]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[19]_i_3 + (.I0(dout_tmp__4[19]), + .I1(o9_mode[1]), + .I2(\u8/dout[19]_i_4_n_0 ), + .O(\u8/dout[19]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[19]_i_4 + (.I0(dout_tmp__4[17]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[31]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[15]), + .O(\u8/dout[19]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT2 #( + .INIT(4'h8)) + \u8/dout[1]_i_1 + (.I0(o9_mode[1]), + .I1(dout_tmp__4[1]), + .O(\u8/dout[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT4 #( + .INIT(16'hF888)) + \u8/dout[2]_i_1 + (.I0(dout_tmp__4[0]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[2]), + .I3(o9_mode[1]), + .O(\u8/dout[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT4 #( + .INIT(16'hF888)) + \u8/dout[3]_i_1 + (.I0(dout_tmp__4[1]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[3]), + .I3(o9_mode[1]), + .O(\u8/dout[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[4]_i_1 + (.I0(dout_tmp__4[4]), + .I1(o9_mode[1]), + .I2(\u8/dout[4]_i_2_n_0 ), + .O(\u8/dout[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[4]_i_2 + (.I0(dout_tmp__4[2]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[16]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[0]), + .O(\u8/dout[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[5]_i_1 + (.I0(dout_tmp__4[5]), + .I1(o9_mode[1]), + .I2(\u8/dout[5]_i_2_n_0 ), + .O(\u8/dout[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[5]_i_2 + (.I0(dout_tmp__4[3]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[17]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[1]), + .O(\u8/dout[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[6]_i_1 + (.I0(dout_tmp__4[6]), + .I1(o9_mode[1]), + .I2(\u8/dout[6]_i_2_n_0 ), + .O(\u8/dout[6]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[6]_i_2 + (.I0(dout_tmp__4[4]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[18]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[2]), + .O(\u8/dout[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[7]_i_1 + (.I0(dout_tmp__4[7]), + .I1(o9_mode[1]), + .I2(\u8/dout[7]_i_2_n_0 ), + .O(\u8/dout[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[7]_i_2 + (.I0(dout_tmp__4[5]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[19]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[3]), + .O(\u8/dout[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[8]_i_1 + (.I0(dout_tmp__4[8]), + .I1(o9_mode[1]), + .I2(\u8/dout[8]_i_2_n_0 ), + .O(\u8/dout[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[8]_i_2 + (.I0(dout_tmp__4[6]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[20]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[4]), + .O(\u8/dout[8]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'hB8)) + \u8/dout[9]_i_1 + (.I0(dout_tmp__4[9]), + .I1(o9_mode[1]), + .I2(\u8/dout[9]_i_2_n_0 ), + .O(\u8/dout[9]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \u8/dout[9]_i_2 + (.I0(dout_tmp__4[7]), + .I1(o9_mode[0]), + .I2(dout_tmp__4[21]), + .I3(\u8/rp_reg_n_0_[0] ), + .I4(dout_tmp__4[5]), + .O(\u8/dout[9]_i_2_n_0 )); + FDRE \u8/dout_reg[0] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[0]_i_1_n_0 ), + .Q(out_slt9[0]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[10] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[10]_i_1_n_0 ), + .Q(out_slt9[10]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[11] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[11]_i_1_n_0 ), + .Q(out_slt9[11]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[12] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[12]_i_1_n_0 ), + .Q(out_slt9[12]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[13] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[13]_i_1_n_0 ), + .Q(out_slt9[13]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[14] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[14]_i_1_n_0 ), + .Q(out_slt9[14]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[15] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[15]_i_1_n_0 ), + .Q(out_slt9[15]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[16] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[16]_i_1_n_0 ), + .Q(out_slt9[16]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[17] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[17]_i_1_n_0 ), + .Q(out_slt9[17]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[18] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[18]_i_1_n_0 ), + .Q(out_slt9[18]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[19] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[19]_i_3_n_0 ), + .Q(out_slt9[19]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[1] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[1]_i_1_n_0 ), + .Q(out_slt9[1]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[2] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[2]_i_1_n_0 ), + .Q(out_slt9[2]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[3] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[3]_i_1_n_0 ), + .Q(out_slt9[3]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[4] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[4]_i_1_n_0 ), + .Q(out_slt9[4]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[5] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[5]_i_1_n_0 ), + .Q(out_slt9[5]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[6] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[6]_i_1_n_0 ), + .Q(out_slt9[6]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[7] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[7]_i_1_n_0 ), + .Q(out_slt9[7]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[8] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[8]_i_1_n_0 ), + .Q(out_slt9[8]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/dout_reg[9] + (.C(clk_i), + .CE(o9_re), + .D(\u8/dout[9]_i_1_n_0 ), + .Q(out_slt9[9]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/empty_reg + (.C(clk_i), + .CE(\ ), + .D(\u8/empty0 ), + .Q(o9_empty), + .R(\ )); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u8/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "0" *) + (* ram_slice_end = "5" *) + RAM32M \u8/mem_reg_0_3_0_5 + (.ADDRA({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u8/wp_reg_n_0_[1] ,\u8/wp_reg_n_0_[0] }), + .DIA(wb_din[1:0]), + .DIB(wb_din[3:2]), + .DIC(wb_din[5:4]), + .DID({\ ,\ }), + .DOA(dout_tmp__4[1:0]), + .DOB(dout_tmp__4[3:2]), + .DOC(dout_tmp__4[5:4]), + .WCLK(clk_i), + .WE(o9_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u8/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "12" *) + (* ram_slice_end = "17" *) + RAM32M \u8/mem_reg_0_3_12_17 + (.ADDRA({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u8/wp_reg_n_0_[1] ,\u8/wp_reg_n_0_[0] }), + .DIA(wb_din[13:12]), + .DIB(wb_din[15:14]), + .DIC(wb_din[17:16]), + .DID({\ ,\ }), + .DOA(dout_tmp__4[13:12]), + .DOB(dout_tmp__4[15:14]), + .DOC(dout_tmp__4[17:16]), + .WCLK(clk_i), + .WE(o9_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u8/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "18" *) + (* ram_slice_end = "23" *) + RAM32M \u8/mem_reg_0_3_18_23 + (.ADDRA({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u8/wp_reg_n_0_[1] ,\u8/wp_reg_n_0_[0] }), + .DIA(wb_din[19:18]), + .DIB(wb_din[21:20]), + .DIC(wb_din[23:22]), + .DID({\ ,\ }), + .DOA(dout_tmp__4[19:18]), + .DOB(dout_tmp__4[21:20]), + .DOC(dout_tmp__4[23:22]), + .WCLK(clk_i), + .WE(o9_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u8/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "24" *) + (* ram_slice_end = "29" *) + RAM32M \u8/mem_reg_0_3_24_29 + (.ADDRA({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u8/wp_reg_n_0_[1] ,\u8/wp_reg_n_0_[0] }), + .DIA(wb_din[25:24]), + .DIB(wb_din[27:26]), + .DIC(wb_din[29:28]), + .DID({\ ,\ }), + .DOA(dout_tmp__4[25:24]), + .DOB(dout_tmp__4[27:26]), + .DOC(dout_tmp__4[29:28]), + .WCLK(clk_i), + .WE(o9_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u8/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u8/mem_reg_0_3_30_31 + (.A0(\u8/wp_reg_n_0_[0] ), + .A1(\u8/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[30]), + .DPO(dout_tmp__4[30]), + .DPRA0(\u8/p_0_in [0]), + .DPRA1(\u8/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o9_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u8/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u8/mem_reg_0_3_30_31__0 + (.A0(\u8/wp_reg_n_0_[0] ), + .A1(\u8/wp_reg_n_0_[1] ), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(wb_din[31]), + .DPO(dout_tmp__4[31]), + .DPRA0(\u8/p_0_in [0]), + .DPRA1(\u8/p_0_in [1]), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(o9_we)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u8/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "6" *) + (* ram_slice_end = "11" *) + RAM32M \u8/mem_reg_0_3_6_11 + (.ADDRA({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRB({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRC({\ ,\ ,\ ,\u8/p_0_in }), + .ADDRD({\ ,\ ,\ ,\u8/wp_reg_n_0_[1] ,\u8/wp_reg_n_0_[0] }), + .DIA(wb_din[7:6]), + .DIB(wb_din[9:8]), + .DIC(wb_din[11:10]), + .DID({\ ,\ }), + .DOA(dout_tmp__4[7:6]), + .DOB(dout_tmp__4[9:8]), + .DOC(dout_tmp__4[11:10]), + .WCLK(clk_i), + .WE(o9_we)); + FDRE \u8/rp_reg[0] + (.C(clk_i), + .CE(o9_re), + .D(\rp[0]_i_1__7_n_0 ), + .Q(\u8/rp_reg_n_0_[0] ), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/rp_reg[1] + (.C(clk_i), + .CE(o9_re), + .D(p_0_in__7[1]), + .Q(\u8/p_0_in [0]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/rp_reg[2] + (.C(clk_i), + .CE(o9_re), + .D(p_0_in__7[2]), + .Q(\u8/p_0_in [1]), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/rp_reg[3] + (.C(clk_i), + .CE(o9_re), + .D(p_0_in__7[3]), + .Q(\u8/rp_reg_n_0_[3] ), + .R(\dout[19]_i_1__4_n_0 )); + FDRE \u8/status_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\status[0]_i_1__4_n_0 ), + .Q(o9_status[0]), + .R(\ )); + FDRE \u8/status_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u8/status0 ), + .Q(o9_status[1]), + .R(\ )); + FDRE \u8/wp_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\wp[0]_i_1__4_n_0 ), + .Q(\u8/wp_reg_n_0_[0] ), + .R(\ )); + FDRE \u8/wp_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\wp[1]_i_1__4_n_0 ), + .Q(\u8/wp_reg_n_0_[1] ), + .R(\ )); + FDRE \u8/wp_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\wp[2]_i_1__4_n_0 ), + .Q(\u8/p_1_in ), + .R(\ )); + FDRE \u9/din_tmp1_reg[0] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[4]), + .Q(\u9/din_tmp1 [0]), + .R(\ )); + FDRE \u9/din_tmp1_reg[10] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[14]), + .Q(\u9/din_tmp1 [10]), + .R(\ )); + FDRE \u9/din_tmp1_reg[11] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[15]), + .Q(\u9/din_tmp1 [11]), + .R(\ )); + FDRE \u9/din_tmp1_reg[12] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[16]), + .Q(\u9/din_tmp1 [12]), + .R(\ )); + FDRE \u9/din_tmp1_reg[13] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[17]), + .Q(\u9/din_tmp1 [13]), + .R(\ )); + FDRE \u9/din_tmp1_reg[14] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[18]), + .Q(\u9/din_tmp1 [14]), + .R(\ )); + FDRE \u9/din_tmp1_reg[15] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[19]), + .Q(\u9/din_tmp1 [15]), + .R(\ )); + FDRE \u9/din_tmp1_reg[1] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[5]), + .Q(\u9/din_tmp1 [1]), + .R(\ )); + FDRE \u9/din_tmp1_reg[2] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[6]), + .Q(\u9/din_tmp1 [2]), + .R(\ )); + FDRE \u9/din_tmp1_reg[3] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[7]), + .Q(\u9/din_tmp1 [3]), + .R(\ )); + FDRE \u9/din_tmp1_reg[4] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[8]), + .Q(\u9/din_tmp1 [4]), + .R(\ )); + FDRE \u9/din_tmp1_reg[5] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[9]), + .Q(\u9/din_tmp1 [5]), + .R(\ )); + FDRE \u9/din_tmp1_reg[6] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[10]), + .Q(\u9/din_tmp1 [6]), + .R(\ )); + FDRE \u9/din_tmp1_reg[7] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[11]), + .Q(\u9/din_tmp1 [7]), + .R(\ )); + FDRE \u9/din_tmp1_reg[8] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[12]), + .Q(\u9/din_tmp1 [8]), + .R(\ )); + FDRE \u9/din_tmp1_reg[9] + (.C(clk_i), + .CE(\u9/din_tmp10 ), + .D(in_slt3[13]), + .Q(\u9/din_tmp1 [9]), + .R(\ )); + FDRE \u9/dout_reg[0] + (.C(clk_i), + .CE(\ ), + .D(dout0[0]), + .Q(i3_dout[0]), + .R(\ )); + FDRE \u9/dout_reg[10] + (.C(clk_i), + .CE(\ ), + .D(dout0[10]), + .Q(i3_dout[10]), + .R(\ )); + FDRE \u9/dout_reg[11] + (.C(clk_i), + .CE(\ ), + .D(dout0[11]), + .Q(i3_dout[11]), + .R(\ )); + FDRE \u9/dout_reg[12] + (.C(clk_i), + .CE(\ ), + .D(dout0[12]), + .Q(i3_dout[12]), + .R(\ )); + FDRE \u9/dout_reg[13] + (.C(clk_i), + .CE(\ ), + .D(dout0[13]), + .Q(i3_dout[13]), + .R(\ )); + FDRE \u9/dout_reg[14] + (.C(clk_i), + .CE(\ ), + .D(dout0[14]), + .Q(i3_dout[14]), + .R(\ )); + FDRE \u9/dout_reg[15] + (.C(clk_i), + .CE(\ ), + .D(dout0[15]), + .Q(i3_dout[15]), + .R(\ )); + FDRE \u9/dout_reg[16] + (.C(clk_i), + .CE(\ ), + .D(dout0[16]), + .Q(i3_dout[16]), + .R(\ )); + FDRE \u9/dout_reg[17] + (.C(clk_i), + .CE(\ ), + .D(dout0[17]), + .Q(i3_dout[17]), + .R(\ )); + FDRE \u9/dout_reg[18] + (.C(clk_i), + .CE(\ ), + .D(dout0[18]), + .Q(i3_dout[18]), + .R(\ )); + FDRE \u9/dout_reg[19] + (.C(clk_i), + .CE(\ ), + .D(dout0[19]), + .Q(i3_dout[19]), + .R(\ )); + FDRE \u9/dout_reg[1] + (.C(clk_i), + .CE(\ ), + .D(dout0[1]), + .Q(i3_dout[1]), + .R(\ )); + FDRE \u9/dout_reg[20] + (.C(clk_i), + .CE(\ ), + .D(dout0[20]), + .Q(i3_dout[20]), + .R(\ )); + FDRE \u9/dout_reg[21] + (.C(clk_i), + .CE(\ ), + .D(dout0[21]), + .Q(i3_dout[21]), + .R(\ )); + FDRE \u9/dout_reg[22] + (.C(clk_i), + .CE(\ ), + .D(dout0[22]), + .Q(i3_dout[22]), + .R(\ )); + FDRE \u9/dout_reg[23] + (.C(clk_i), + .CE(\ ), + .D(dout0[23]), + .Q(i3_dout[23]), + .R(\ )); + FDRE \u9/dout_reg[24] + (.C(clk_i), + .CE(\ ), + .D(dout0[24]), + .Q(i3_dout[24]), + .R(\ )); + FDRE \u9/dout_reg[25] + (.C(clk_i), + .CE(\ ), + .D(dout0[25]), + .Q(i3_dout[25]), + .R(\ )); + FDRE \u9/dout_reg[26] + (.C(clk_i), + .CE(\ ), + .D(dout0[26]), + .Q(i3_dout[26]), + .R(\ )); + FDRE \u9/dout_reg[27] + (.C(clk_i), + .CE(\ ), + .D(dout0[27]), + .Q(i3_dout[27]), + .R(\ )); + FDRE \u9/dout_reg[28] + (.C(clk_i), + .CE(\ ), + .D(dout0[28]), + .Q(i3_dout[28]), + .R(\ )); + FDRE \u9/dout_reg[29] + (.C(clk_i), + .CE(\ ), + .D(dout0[29]), + .Q(i3_dout[29]), + .R(\ )); + FDRE \u9/dout_reg[2] + (.C(clk_i), + .CE(\ ), + .D(dout0[2]), + .Q(i3_dout[2]), + .R(\ )); + FDRE \u9/dout_reg[30] + (.C(clk_i), + .CE(\ ), + .D(dout0[30]), + .Q(i3_dout[30]), + .R(\ )); + FDRE \u9/dout_reg[31] + (.C(clk_i), + .CE(\ ), + .D(dout0[31]), + .Q(i3_dout[31]), + .R(\ )); + FDRE \u9/dout_reg[3] + (.C(clk_i), + .CE(\ ), + .D(dout0[3]), + .Q(i3_dout[3]), + .R(\ )); + FDRE \u9/dout_reg[4] + (.C(clk_i), + .CE(\ ), + .D(dout0[4]), + .Q(i3_dout[4]), + .R(\ )); + FDRE \u9/dout_reg[5] + (.C(clk_i), + .CE(\ ), + .D(dout0[5]), + .Q(i3_dout[5]), + .R(\ )); + FDRE \u9/dout_reg[6] + (.C(clk_i), + .CE(\ ), + .D(dout0[6]), + .Q(i3_dout[6]), + .R(\ )); + FDRE \u9/dout_reg[7] + (.C(clk_i), + .CE(\ ), + .D(dout0[7]), + .Q(i3_dout[7]), + .R(\ )); + FDRE \u9/dout_reg[8] + (.C(clk_i), + .CE(\ ), + .D(dout0[8]), + .Q(i3_dout[8]), + .R(\ )); + FDRE \u9/dout_reg[9] + (.C(clk_i), + .CE(\ ), + .D(dout0[9]), + .Q(i3_dout[9]), + .R(\ )); + FDRE \u9/empty_reg + (.C(clk_i), + .CE(\ ), + .D(\u9/empty0 ), + .Q(i3_empty), + .R(\ )); + FDRE \u9/full_reg + (.C(clk_i), + .CE(\ ), + .D(\u9/full0 ), + .Q(i3_full), + .R(\ )); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u9/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "0" *) + (* ram_slice_end = "5" *) + RAM32M \u9/mem_reg_0_3_0_5 + (.ADDRA({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u9/p_1_in }), + .DIA(\u9/din_tmp [1:0]), + .DIB(\u9/din_tmp [3:2]), + .DIC(\u9/din_tmp [5:4]), + .DID({\ ,\ }), + .DOA(dout0[1:0]), + .DOB(dout0[3:2]), + .DOC(dout0[5:4]), + .WCLK(clk_i), + .WE(p_0_in__0)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u9/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "12" *) + (* ram_slice_end = "17" *) + RAM32M \u9/mem_reg_0_3_12_17 + (.ADDRA({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u9/p_1_in }), + .DIA(\u9/din_tmp [13:12]), + .DIB(\u9/din_tmp [15:14]), + .DIC(\u9/din_tmp [17:16]), + .DID({\ ,\ }), + .DOA(dout0[13:12]), + .DOB(dout0[15:14]), + .DOC(dout0[17:16]), + .WCLK(clk_i), + .WE(p_0_in__0)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u9/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "18" *) + (* ram_slice_end = "23" *) + RAM32M \u9/mem_reg_0_3_18_23 + (.ADDRA({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u9/p_1_in }), + .DIA(\u9/din_tmp [19:18]), + .DIB(\u9/din_tmp [21:20]), + .DIC(\u9/din_tmp [23:22]), + .DID({\ ,\ }), + .DOA(dout0[19:18]), + .DOB(dout0[21:20]), + .DOC(dout0[23:22]), + .WCLK(clk_i), + .WE(p_0_in__0)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u9/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "24" *) + (* ram_slice_end = "29" *) + RAM32M \u9/mem_reg_0_3_24_29 + (.ADDRA({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u9/p_1_in }), + .DIA(\u9/din_tmp [25:24]), + .DIB(\u9/din_tmp [27:26]), + .DIC(\u9/din_tmp [29:28]), + .DID({\ ,\ }), + .DOA(dout0[25:24]), + .DOB(dout0[27:26]), + .DOC(dout0[29:28]), + .WCLK(clk_i), + .WE(p_0_in__0)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u9/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u9/mem_reg_0_3_30_31 + (.A0(\u9/p_1_in [0]), + .A1(\u9/p_1_in [1]), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(\u9/din_tmp [30]), + .DPO(dout0[30]), + .DPRA0(\u9/rp_reg_n_0_[0] ), + .DPRA1(\u9/rp_reg_n_0_[1] ), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(p_0_in__0)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u9/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "30" *) + (* ram_slice_end = "31" *) + RAM32X1D \u9/mem_reg_0_3_30_31__0 + (.A0(\u9/p_1_in [0]), + .A1(\u9/p_1_in [1]), + .A2(\ ), + .A3(\ ), + .A4(\ ), + .D(\u9/din_tmp [31]), + .DPO(dout0[31]), + .DPRA0(\u9/rp_reg_n_0_[0] ), + .DPRA1(\u9/rp_reg_n_0_[1] ), + .DPRA2(\ ), + .DPRA3(\ ), + .DPRA4(\ ), + .WCLK(clk_i), + .WE(p_0_in__0)); + (* METHODOLOGY_DRC_VIOS = "" *) + (* RTL_RAM_BITS = "128" *) + (* RTL_RAM_NAME = "u9/mem" *) + (* RTL_RAM_TYPE = "RAM_SDP" *) + (* ram_addr_begin = "0" *) + (* ram_addr_end = "3" *) + (* ram_offset = "0" *) + (* ram_slice_begin = "6" *) + (* ram_slice_end = "11" *) + RAM32M \u9/mem_reg_0_3_6_11 + (.ADDRA({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRB({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRC({\ ,\ ,\ ,\u9/rp_reg_n_0_[1] ,\u9/rp_reg_n_0_[0] }), + .ADDRD({\ ,\ ,\ ,\u9/p_1_in }), + .DIA(\u9/din_tmp [7:6]), + .DIB(\u9/din_tmp [9:8]), + .DIC(\u9/din_tmp [11:10]), + .DID({\ ,\ }), + .DOA(dout0[7:6]), + .DOB(dout0[9:8]), + .DOC(dout0[11:10]), + .WCLK(clk_i), + .WE(p_0_in__0)); + FDRE \u9/rp_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\rp[0]_i_1_n_0 ), + .Q(\u9/rp_reg_n_0_[0] ), + .R(\ )); + FDRE \u9/rp_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\rp[1]_i_1_n_0 ), + .Q(\u9/rp_reg_n_0_[1] ), + .R(\ )); + FDRE \u9/rp_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\rp[2]_i_1_n_0 ), + .Q(\u9/rp_reg_n_0_[2] ), + .R(\ )); + FDRE \u9/status_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\status[0]_i_1__7_n_0 ), + .Q(i3_status[0]), + .R(\ )); + FDRE \u9/status_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u9/status0 ), + .Q(i3_status[1]), + .R(\ )); + FDRE \u9/wp_reg[0] + (.C(clk_i), + .CE(i3_we), + .D(\wp[0]_i_1__5_n_0 ), + .Q(\u9/wp_reg_n_0_[0] ), + .R(\wp[3]_i_1_n_0 )); + FDRE \u9/wp_reg[1] + (.C(clk_i), + .CE(i3_we), + .D(wp_p1[1]), + .Q(\u9/p_1_in [0]), + .R(\wp[3]_i_1_n_0 )); + FDRE \u9/wp_reg[2] + (.C(clk_i), + .CE(i3_we), + .D(wp_p1[2]), + .Q(\u9/p_1_in [1]), + .R(\wp[3]_i_1_n_0 )); + FDRE \u9/wp_reg[3] + (.C(clk_i), + .CE(i3_we), + .D(wp_p1[3]), + .Q(\u9/wp_reg_n_0_[3] ), + .R(\wp[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFE0000000)) + valid_i_1 + (.I0(\u2/cnt_reg [1]), + .I1(\u2/cnt_reg [2]), + .I2(\u2/cnt_reg [5]), + .I3(\u2/cnt_reg [4]), + .I4(\u2/cnt_reg [3]), + .I5(\out_le[1]_i_2_n_0 ), + .O(valid_i_1_n_0)); + FDRE valid_s1_reg + (.C(clk_i), + .CE(\ ), + .D(valid), + .Q(valid_s1), + .R(\ )); + FDRE valid_s_reg + (.C(clk_i), + .CE(\ ), + .D(valid_s1), + .Q(valid_s), + .R(\ )); + (* SOFT_HLUTNM = "soft_lutpair136" *) + LUT3 #( + .INIT(8'h23)) + wb_ack_o_i_1 + (.I0(wb_ack_o_i_2_n_0), + .I1(wb_ack_o), + .I2(wb_ack_o_i_3_n_0), + .O(\u12/wb_ack_o0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT5 #( + .INIT(32'h00008000)) + wb_ack_o_i_2 + (.I0(wb_cyc_i), + .I1(wb_stb_i), + .I2(wb_we_i), + .I3(\u12/we1 ), + .I4(\u12/we2 ), + .O(wb_ack_o_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT5 #( + .INIT(32'hFFF7FFFF)) + wb_ack_o_i_3 + (.I0(wb_cyc_i), + .I1(wb_stb_i), + .I2(\u12/re2 ), + .I3(wb_we_i), + .I4(\u12/re1 ), + .O(wb_ack_o_i_3_n_0)); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[0]_i_1 + (.I0(\wb_data_o[0]_i_2_n_0 ), + .I1(\wb_data_o[0]_i_3_n_0 ), + .I2(\u13/intm [0]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[0]_i_4_n_0 ), + .O(\wb_data_o[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[0]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[0] ), + .I1(\u13/occ1_r_reg_n_0_[0] ), + .I2(\u13/icc_r_reg_n_0_[0] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[0]_i_3 + (.I0(crac_din[0]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [0]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[0]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[0]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[0]), + .I4(i6_dout[0]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[0]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[10]_i_1 + (.I0(\wb_data_o[10]_i_2_n_0 ), + .I1(\wb_data_o[10]_i_3_n_0 ), + .I2(\u13/intm [10]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[10]_i_4_n_0 ), + .O(\wb_data_o[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[10]_i_2 + (.I0(o4_mode[0]), + .I1(o9_mode[0]), + .I2(i4_mode[0]), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[10]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[10]_i_3 + (.I0(crac_din[10]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [10]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[10]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[10]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[10]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[10]), + .I4(i6_dout[10]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[10]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[11]_i_1 + (.I0(\wb_data_o[11]_i_2_n_0 ), + .I1(\wb_data_o[11]_i_3_n_0 ), + .I2(\u13/intm [11]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[11]_i_4_n_0 ), + .O(\wb_data_o[11]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[11]_i_2 + (.I0(o4_mode[1]), + .I1(o9_mode[1]), + .I2(i4_mode[1]), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[11]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[11]_i_3 + (.I0(crac_din[11]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [11]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[11]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[11]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[11]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[11]), + .I4(i6_dout[11]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[11]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[12]_i_1 + (.I0(\wb_data_o[12]_i_2_n_0 ), + .I1(\wb_data_o[12]_i_3_n_0 ), + .I2(\u13/intm [12]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[12]_i_4_n_0 ), + .O(\wb_data_o[12]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[12]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[12] ), + .I1(\u13/occ1_r_reg_n_0_[12] ), + .I2(\u13/icc_r_reg_n_0_[12] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[12]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[12]_i_3 + (.I0(crac_din[12]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [12]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[12]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[12]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[12]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[12]), + .I4(i6_dout[12]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[12]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[13]_i_1 + (.I0(\wb_data_o[13]_i_2_n_0 ), + .I1(\wb_data_o[13]_i_3_n_0 ), + .I2(\u13/intm [13]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[13]_i_4_n_0 ), + .O(\wb_data_o[13]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[13]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[13] ), + .I1(\u13/occ1_r_reg_n_0_[13] ), + .I2(\u13/icc_r_reg_n_0_[13] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[13]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[13]_i_3 + (.I0(crac_din[13]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [13]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[13]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[13]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[13]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[13]), + .I4(i6_dout[13]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[13]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[14]_i_1 + (.I0(\wb_data_o[14]_i_2_n_0 ), + .I1(\wb_data_o[14]_i_3_n_0 ), + .I2(\u13/intm [14]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[14]_i_4_n_0 ), + .O(\wb_data_o[14]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[14]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[14] ), + .I1(\u13/occ1_r_reg_n_0_[14] ), + .I2(\u13/icc_r_reg_n_0_[14] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[14]_i_3 + (.I0(crac_din[14]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [14]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[14]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[14]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[14]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[14]), + .I4(i6_dout[14]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[14]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[15]_i_1 + (.I0(\wb_data_o[15]_i_2_n_0 ), + .I1(\wb_data_o[15]_i_3_n_0 ), + .I2(\u13/intm [15]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[15]_i_4_n_0 ), + .O(\wb_data_o[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[15]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[15] ), + .I1(\u13/occ1_r_reg_n_0_[15] ), + .I2(\u13/icc_r_reg_n_0_[15] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[15]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[15]_i_3 + (.I0(crac_din[15]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [15]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[15]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[15]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[15]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[15]), + .I4(i6_dout[15]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[15]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFEAFFEAFFEA)) + \wb_data_o[16]_i_1 + (.I0(\wb_data_o[16]_i_2_n_0 ), + .I1(o9_we_i_1_n_0), + .I2(\u13/intm [16]), + .I3(\wb_data_o[16]_i_3_n_0 ), + .I4(o8_we_i_1_n_0), + .I5(crac_out[16]), + .O(\wb_data_o[16]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[16]_i_2 + (.I0(\wb_data_o[30]_i_2_n_0 ), + .I1(i4_dout[16]), + .I2(\wb_data_o[31]_i_3_n_0 ), + .I3(i6_dout[16]), + .I4(\u13/ints [16]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[16]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[16]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(\u13/occ0_r_reg_n_0_[16] ), + .I2(o7_we_i_1_n_0), + .I3(\u13/icc_r_reg_n_0_[16] ), + .I4(i3_dout[16]), + .I5(\wb_data_o[23]_i_3_n_0 ), + .O(\wb_data_o[16]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFEAFFEAFFEA)) + \wb_data_o[17]_i_1 + (.I0(\wb_data_o[17]_i_2_n_0 ), + .I1(o9_we_i_1_n_0), + .I2(\u13/intm [17]), + .I3(\wb_data_o[17]_i_3_n_0 ), + .I4(o8_we_i_1_n_0), + .I5(crac_out[17]), + .O(\wb_data_o[17]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[17]_i_2 + (.I0(\wb_data_o[30]_i_2_n_0 ), + .I1(i4_dout[17]), + .I2(\wb_data_o[31]_i_3_n_0 ), + .I3(i6_dout[17]), + .I4(\u13/ints [17]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[17]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[17]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(\u13/occ0_r_reg_n_0_[17] ), + .I2(o7_we_i_1_n_0), + .I3(\u13/icc_r_reg_n_0_[17] ), + .I4(i3_dout[17]), + .I5(\wb_data_o[23]_i_3_n_0 ), + .O(\wb_data_o[17]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFEAFFEAFFEA)) + \wb_data_o[18]_i_1 + (.I0(\wb_data_o[18]_i_2_n_0 ), + .I1(o9_we_i_1_n_0), + .I2(\u13/intm [18]), + .I3(\wb_data_o[18]_i_3_n_0 ), + .I4(o8_we_i_1_n_0), + .I5(crac_out[18]), + .O(\wb_data_o[18]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[18]_i_2 + (.I0(\wb_data_o[30]_i_2_n_0 ), + .I1(i4_dout[18]), + .I2(\wb_data_o[31]_i_3_n_0 ), + .I3(i6_dout[18]), + .I4(\u13/ints [18]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[18]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[18]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(o6_mode[0]), + .I2(o7_we_i_1_n_0), + .I3(i6_mode[0]), + .I4(i3_dout[18]), + .I5(\wb_data_o[23]_i_3_n_0 ), + .O(\wb_data_o[18]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFEAFFEAFFEA)) + \wb_data_o[19]_i_1 + (.I0(\wb_data_o[19]_i_2_n_0 ), + .I1(o9_we_i_1_n_0), + .I2(\u13/intm [19]), + .I3(\wb_data_o[19]_i_3_n_0 ), + .I4(o8_we_i_1_n_0), + .I5(crac_out[19]), + .O(\wb_data_o[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[19]_i_2 + (.I0(\wb_data_o[30]_i_2_n_0 ), + .I1(i4_dout[19]), + .I2(\wb_data_o[31]_i_3_n_0 ), + .I3(i6_dout[19]), + .I4(\u13/ints [19]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[19]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[19]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(o6_mode[1]), + .I2(o7_we_i_1_n_0), + .I3(i6_mode[1]), + .I4(i3_dout[19]), + .I5(\wb_data_o[23]_i_3_n_0 ), + .O(\wb_data_o[19]_i_3_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFEA)) + \wb_data_o[1]_i_1 + (.I0(\wb_data_o[1]_i_2_n_0 ), + .I1(\u13/intm [1]), + .I2(o9_we_i_1_n_0), + .I3(\wb_data_o[1]_i_3_n_0 ), + .I4(\wb_data_o[1]_i_4_n_0 ), + .O(\wb_data_o[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCCCECCFCCCCECCCC)) + \wb_data_o[1]_i_2 + (.I0(crac_din[1]), + .I1(\wb_data_o[1]_i_5_n_0 ), + .I2(wb_addr_i[2]), + .I3(wb_addr_i[3]), + .I4(wb_addr_i[4]), + .I5(\u13/occ0_r_reg_n_0_[1] ), + .O(\wb_data_o[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[1]_i_3 + (.I0(o6_we_i_1_n_0), + .I1(\u13/occ1_r_reg_n_0_[1] ), + .I2(o7_we_i_1_n_0), + .I3(\u13/icc_r_reg_n_0_[1] ), + .I4(i3_dout[1]), + .I5(\wb_data_o[23]_i_3_n_0 ), + .O(\wb_data_o[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[1]_i_4 + (.I0(\wb_data_o[30]_i_2_n_0 ), + .I1(i4_dout[1]), + .I2(\wb_data_o[31]_i_3_n_0 ), + .I3(i6_dout[1]), + .I4(\u13/ints [1]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[1]_i_4_n_0 )); + LUT6 #( + .INIT(64'h000000000000008A)) + \wb_data_o[1]_i_5 + (.I0(suspended_o), + .I1(wb_addr_i[5]), + .I2(wb_addr_i[6]), + .I3(wb_addr_i[2]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[4]), + .O(\wb_data_o[1]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFEAFFEAFFEA)) + \wb_data_o[20]_i_1 + (.I0(\wb_data_o[20]_i_2_n_0 ), + .I1(o9_we_i_1_n_0), + .I2(\u13/intm [20]), + .I3(\wb_data_o[20]_i_3_n_0 ), + .I4(o8_we_i_1_n_0), + .I5(crac_out[20]), + .O(\wb_data_o[20]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[20]_i_2 + (.I0(\wb_data_o[30]_i_2_n_0 ), + .I1(i4_dout[20]), + .I2(\wb_data_o[31]_i_3_n_0 ), + .I3(i6_dout[20]), + .I4(\u13/ints [20]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[20]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[20]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(\u13/occ0_r_reg_n_0_[20] ), + .I2(o7_we_i_1_n_0), + .I3(\u13/icc_r_reg_n_0_[20] ), + .I4(i3_dout[20]), + .I5(\wb_data_o[23]_i_3_n_0 ), + .O(\wb_data_o[20]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFEAFFEAFFEA)) + \wb_data_o[21]_i_1 + (.I0(\wb_data_o[21]_i_2_n_0 ), + .I1(o9_we_i_1_n_0), + .I2(\u13/intm [21]), + .I3(\wb_data_o[21]_i_3_n_0 ), + .I4(o8_we_i_1_n_0), + .I5(crac_out[21]), + .O(\wb_data_o[21]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[21]_i_2 + (.I0(\wb_data_o[30]_i_2_n_0 ), + .I1(i4_dout[21]), + .I2(\wb_data_o[31]_i_3_n_0 ), + .I3(i6_dout[21]), + .I4(\u13/ints [21]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[21]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[21]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(\u13/occ0_r_reg_n_0_[21] ), + .I2(o7_we_i_1_n_0), + .I3(\u13/icc_r_reg_n_0_[21] ), + .I4(i3_dout[21]), + .I5(\wb_data_o[23]_i_3_n_0 ), + .O(\wb_data_o[21]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFEAFFEAFFEA)) + \wb_data_o[22]_i_1 + (.I0(\wb_data_o[22]_i_2_n_0 ), + .I1(o9_we_i_1_n_0), + .I2(\u13/intm [22]), + .I3(\wb_data_o[22]_i_3_n_0 ), + .I4(o8_we_i_1_n_0), + .I5(crac_out[22]), + .O(\wb_data_o[22]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[22]_i_2 + (.I0(\wb_data_o[30]_i_2_n_0 ), + .I1(i4_dout[22]), + .I2(\wb_data_o[31]_i_3_n_0 ), + .I3(i6_dout[22]), + .I4(\u13/ints [22]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[22]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[22]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(\u13/occ0_r_reg_n_0_[22] ), + .I2(o7_we_i_1_n_0), + .I3(\u13/icc_r_reg_n_0_[22] ), + .I4(i3_dout[22]), + .I5(\wb_data_o[23]_i_3_n_0 ), + .O(\wb_data_o[22]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFEAEAEA)) + \wb_data_o[23]_i_1 + (.I0(\wb_data_o[23]_i_2_n_0 ), + .I1(i3_dout[23]), + .I2(\wb_data_o[23]_i_3_n_0 ), + .I3(o9_we_i_1_n_0), + .I4(\u13/intm [23]), + .I5(\wb_data_o[23]_i_4_n_0 ), + .O(\wb_data_o[23]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT5 #( + .INIT(32'h0A0C0000)) + \wb_data_o[23]_i_2 + (.I0(\u13/icc_r_reg_n_0_[23] ), + .I1(\u13/occ0_r_reg_n_0_[23] ), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[3]), + .I4(wb_addr_i[2]), + .O(\wb_data_o[23]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00000800)) + \wb_data_o[23]_i_3 + (.I0(wb_addr_i[3]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[6]), + .I3(wb_addr_i[5]), + .I4(wb_addr_i[2]), + .O(\wb_data_o[23]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[23]_i_4 + (.I0(\wb_data_o[30]_i_2_n_0 ), + .I1(i4_dout[23]), + .I2(\wb_data_o[31]_i_3_n_0 ), + .I3(i6_dout[23]), + .I4(\u13/ints [23]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[23]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT4 #( + .INIT(16'hD000)) + \wb_data_o[23]_i_5 + (.I0(wb_addr_i[5]), + .I1(wb_addr_i[6]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[3]), + .O(\wb_data_o[23]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFF8F8F8)) + \wb_data_o[24]_i_1 + (.I0(o9_we_i_1_n_0), + .I1(\u13/intm [24]), + .I2(\wb_data_o[24]_i_2_n_0 ), + .I3(i6_dout[24]), + .I4(\wb_data_o[31]_i_3_n_0 ), + .I5(\wb_data_o[24]_i_3_n_0 ), + .O(\wb_data_o[24]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT5 #( + .INIT(32'h80880000)) + \wb_data_o[24]_i_2 + (.I0(wb_addr_i[3]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[6]), + .I3(wb_addr_i[5]), + .I4(\u13/ints [24]), + .O(\wb_data_o[24]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[24]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(\u13/occ0_r_reg_n_0_[24] ), + .I2(\wb_data_o[23]_i_3_n_0 ), + .I3(i3_dout[24]), + .I4(i4_dout[24]), + .I5(\wb_data_o[30]_i_2_n_0 ), + .O(\wb_data_o[24]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFF8F8F8)) + \wb_data_o[25]_i_1 + (.I0(o9_we_i_1_n_0), + .I1(\u13/intm [25]), + .I2(\wb_data_o[25]_i_2_n_0 ), + .I3(i6_dout[25]), + .I4(\wb_data_o[31]_i_3_n_0 ), + .I5(\wb_data_o[25]_i_3_n_0 ), + .O(\wb_data_o[25]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT5 #( + .INIT(32'h80880000)) + \wb_data_o[25]_i_2 + (.I0(wb_addr_i[3]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[6]), + .I3(wb_addr_i[5]), + .I4(\u13/ints [25]), + .O(\wb_data_o[25]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[25]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(\u13/occ0_r_reg_n_0_[25] ), + .I2(\wb_data_o[23]_i_3_n_0 ), + .I3(i3_dout[25]), + .I4(i4_dout[25]), + .I5(\wb_data_o[30]_i_2_n_0 ), + .O(\wb_data_o[25]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFF8F8F8)) + \wb_data_o[26]_i_1 + (.I0(o9_we_i_1_n_0), + .I1(\u13/intm [26]), + .I2(\wb_data_o[26]_i_2_n_0 ), + .I3(i6_dout[26]), + .I4(\wb_data_o[31]_i_3_n_0 ), + .I5(\wb_data_o[26]_i_3_n_0 ), + .O(\wb_data_o[26]_i_1_n_0 )); + LUT5 #( + .INIT(32'h80880000)) + \wb_data_o[26]_i_2 + (.I0(wb_addr_i[3]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[6]), + .I3(wb_addr_i[5]), + .I4(\u13/ints [26]), + .O(\wb_data_o[26]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[26]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(o7_mode[0]), + .I2(\wb_data_o[23]_i_3_n_0 ), + .I3(i3_dout[26]), + .I4(i4_dout[26]), + .I5(\wb_data_o[30]_i_2_n_0 ), + .O(\wb_data_o[26]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFF8F8F8)) + \wb_data_o[27]_i_1 + (.I0(o9_we_i_1_n_0), + .I1(\u13/intm [27]), + .I2(\wb_data_o[27]_i_2_n_0 ), + .I3(i6_dout[27]), + .I4(\wb_data_o[31]_i_3_n_0 ), + .I5(\wb_data_o[27]_i_3_n_0 ), + .O(\wb_data_o[27]_i_1_n_0 )); + LUT5 #( + .INIT(32'h80880000)) + \wb_data_o[27]_i_2 + (.I0(wb_addr_i[3]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[6]), + .I3(wb_addr_i[5]), + .I4(\u13/ints [27]), + .O(\wb_data_o[27]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[27]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(o7_mode[1]), + .I2(\wb_data_o[23]_i_3_n_0 ), + .I3(i3_dout[27]), + .I4(i4_dout[27]), + .I5(\wb_data_o[30]_i_2_n_0 ), + .O(\wb_data_o[27]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFF8F8F8)) + \wb_data_o[28]_i_1 + (.I0(o9_we_i_1_n_0), + .I1(\u13/intm [28]), + .I2(\wb_data_o[28]_i_2_n_0 ), + .I3(i6_dout[28]), + .I4(\wb_data_o[31]_i_3_n_0 ), + .I5(\wb_data_o[28]_i_3_n_0 ), + .O(\wb_data_o[28]_i_1_n_0 )); + LUT5 #( + .INIT(32'h80880000)) + \wb_data_o[28]_i_2 + (.I0(wb_addr_i[3]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[6]), + .I3(wb_addr_i[5]), + .I4(\u13/ints [28]), + .O(\wb_data_o[28]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[28]_i_3 + (.I0(o4_we_i_1_n_0), + .I1(\u13/occ0_r_reg_n_0_[28] ), + .I2(\wb_data_o[23]_i_3_n_0 ), + .I3(i3_dout[28]), + .I4(i4_dout[28]), + .I5(\wb_data_o[30]_i_2_n_0 ), + .O(\wb_data_o[28]_i_3_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[29]_i_1 + (.I0(i6_dout[29]), + .I1(\wb_data_o[31]_i_3_n_0 ), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[29]), + .I4(\wb_data_o[29]_i_2_n_0 ), + .O(\wb_data_o[29]_i_1_n_0 )); + LUT6 #( + .INIT(64'h888888F888888888)) + \wb_data_o[29]_i_2 + (.I0(i3_dout[29]), + .I1(\wb_data_o[23]_i_3_n_0 ), + .I2(\u13/occ0_r_reg_n_0_[29] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[29]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[2]_i_1 + (.I0(\wb_data_o[2]_i_2_n_0 ), + .I1(\wb_data_o[2]_i_3_n_0 ), + .I2(\u13/intm [2]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[2]_i_4_n_0 ), + .O(\wb_data_o[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[2]_i_2 + (.I0(o3_mode[0]), + .I1(o8_mode[0]), + .I2(i3_mode[0]), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[2]_i_3 + (.I0(crac_din[2]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [2]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[2]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[2]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[2]), + .I4(i6_dout[2]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[2]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[30]_i_1 + (.I0(i6_dout[30]), + .I1(\wb_data_o[31]_i_3_n_0 ), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[30]), + .I4(\wb_data_o[30]_i_3_n_0 ), + .O(\wb_data_o[30]_i_1_n_0 )); + LUT5 #( + .INIT(32'h08000000)) + \wb_data_o[30]_i_2 + (.I0(wb_addr_i[3]), + .I1(wb_addr_i[4]), + .I2(wb_addr_i[6]), + .I3(wb_addr_i[5]), + .I4(wb_addr_i[2]), + .O(\wb_data_o[30]_i_2_n_0 )); + LUT6 #( + .INIT(64'h888888F888888888)) + \wb_data_o[30]_i_3 + (.I0(i3_dout[30]), + .I1(\wb_data_o[23]_i_3_n_0 ), + .I2(\u13/occ0_r_reg_n_0_[30] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[30]_i_3_n_0 )); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \wb_data_o[31]_i_1 + (.I0(\wb_data_o[31]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_3_n_0 ), + .I2(i6_dout[31]), + .I3(crac_out[31]), + .I4(o8_we_i_1_n_0), + .O(\wb_data_o[31]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[31]_i_2 + (.I0(o4_we_i_1_n_0), + .I1(\u13/occ0_r_reg_n_0_[31] ), + .I2(\wb_data_o[23]_i_3_n_0 ), + .I3(i3_dout[31]), + .I4(i4_dout[31]), + .I5(\wb_data_o[30]_i_2_n_0 ), + .O(\wb_data_o[31]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00000002)) + \wb_data_o[31]_i_3 + (.I0(wb_addr_i[6]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[5]), + .I4(wb_addr_i[2]), + .O(\wb_data_o[31]_i_3_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[3]_i_1 + (.I0(\wb_data_o[3]_i_2_n_0 ), + .I1(\wb_data_o[3]_i_3_n_0 ), + .I2(\u13/intm [3]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[3]_i_4_n_0 ), + .O(\wb_data_o[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[3]_i_2 + (.I0(o3_mode[1]), + .I1(o8_mode[1]), + .I2(i3_mode[1]), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[3]_i_3 + (.I0(crac_din[3]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [3]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[3]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[3]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[3]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[3]), + .I4(i6_dout[3]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[3]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[4]_i_1 + (.I0(\wb_data_o[4]_i_2_n_0 ), + .I1(\wb_data_o[4]_i_3_n_0 ), + .I2(\u13/intm [4]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[4]_i_4_n_0 ), + .O(\wb_data_o[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[4]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[4] ), + .I1(\u13/occ1_r_reg_n_0_[4] ), + .I2(\u13/icc_r_reg_n_0_[4] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[4]_i_3 + (.I0(crac_din[4]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [4]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[4]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[4]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[4]), + .I4(i6_dout[4]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[4]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[5]_i_1 + (.I0(\wb_data_o[5]_i_2_n_0 ), + .I1(\wb_data_o[5]_i_3_n_0 ), + .I2(\u13/intm [5]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[5]_i_4_n_0 ), + .O(\wb_data_o[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[5]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[5] ), + .I1(\u13/occ1_r_reg_n_0_[5] ), + .I2(\u13/icc_r_reg_n_0_[5] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[5]_i_3 + (.I0(crac_din[5]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [5]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[5]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[5]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[5]), + .I4(i6_dout[5]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[5]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[6]_i_1 + (.I0(\wb_data_o[6]_i_2_n_0 ), + .I1(\wb_data_o[6]_i_3_n_0 ), + .I2(\u13/intm [6]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[6]_i_4_n_0 ), + .O(\wb_data_o[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[6]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[6] ), + .I1(\u13/occ1_r_reg_n_0_[6] ), + .I2(\u13/icc_r_reg_n_0_[6] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[6]_i_3 + (.I0(crac_din[6]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [6]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[6]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[6]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[6]), + .I4(i6_dout[6]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[6]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[7]_i_1 + (.I0(\wb_data_o[7]_i_2_n_0 ), + .I1(\wb_data_o[7]_i_3_n_0 ), + .I2(\u13/intm [7]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[7]_i_4_n_0 ), + .O(\wb_data_o[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[7]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[7] ), + .I1(\u13/occ1_r_reg_n_0_[7] ), + .I2(\u13/icc_r_reg_n_0_[7] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[7]_i_3 + (.I0(crac_din[7]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [7]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[7]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[7]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[7]), + .I4(i6_dout[7]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[7]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[8]_i_1 + (.I0(\wb_data_o[8]_i_2_n_0 ), + .I1(\wb_data_o[8]_i_3_n_0 ), + .I2(\u13/intm [8]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[8]_i_4_n_0 ), + .O(\wb_data_o[8]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[8]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[8] ), + .I1(\u13/occ1_r_reg_n_0_[8] ), + .I2(\u13/icc_r_reg_n_0_[8] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[8]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[8]_i_3 + (.I0(crac_din[8]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [8]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[8]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[8]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[8]), + .I4(i6_dout[8]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[8]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \wb_data_o[9]_i_1 + (.I0(\wb_data_o[9]_i_2_n_0 ), + .I1(\wb_data_o[9]_i_3_n_0 ), + .I2(\u13/intm [9]), + .I3(o9_we_i_1_n_0), + .I4(\wb_data_o[9]_i_4_n_0 ), + .O(\wb_data_o[9]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00F000AA00CC0000)) + \wb_data_o[9]_i_2 + (.I0(\u13/occ0_r_reg_n_0_[9] ), + .I1(\u13/occ1_r_reg_n_0_[9] ), + .I2(\u13/icc_r_reg_n_0_[9] ), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(wb_addr_i[2]), + .O(\wb_data_o[9]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF002000200020)) + \wb_data_o[9]_i_3 + (.I0(crac_din[9]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[2]), + .I4(\u13/ints [9]), + .I5(\wb_data_o[23]_i_5_n_0 ), + .O(\wb_data_o[9]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \wb_data_o[9]_i_4 + (.I0(\wb_data_o[23]_i_3_n_0 ), + .I1(i3_dout[9]), + .I2(\wb_data_o[30]_i_2_n_0 ), + .I3(i4_dout[9]), + .I4(i6_dout[9]), + .I5(\wb_data_o[31]_i_3_n_0 ), + .O(\wb_data_o[9]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0000000B00000000)) + we1_i_1 + (.I0(\u12/we2 ), + .I1(\u12/we1 ), + .I2(wb_addr_i[31]), + .I3(wb_addr_i[30]), + .I4(wb_addr_i[29]), + .I5(we1_i_2_n_0), + .O(\u12/we10 )); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT3 #( + .INIT(8'h80)) + we1_i_2 + (.I0(wb_we_i), + .I1(wb_stb_i), + .I2(wb_cyc_i), + .O(we1_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT4 #( + .INIT(16'h8000)) + we2_i_1 + (.I0(wb_cyc_i), + .I1(wb_stb_i), + .I2(wb_we_i), + .I3(\u12/we1 ), + .O(\u12/we20 )); + LUT3 #( + .INIT(8'h60)) + \wp[0]_i_1 + (.I0(\u3/wp_reg_n_0_[0] ), + .I1(o3_we), + .I2(\u13/occ0_r_reg_n_0_[0] ), + .O(\wp[0]_i_1_n_0 )); + LUT3 #( + .INIT(8'h60)) + \wp[0]_i_1__0 + (.I0(\u4/wp_reg_n_0_[0] ), + .I1(o4_we), + .I2(\u13/occ0_r_reg_n_0_[8] ), + .O(\wp[0]_i_1__0_n_0 )); + LUT3 #( + .INIT(8'h60)) + \wp[0]_i_1__1 + (.I0(\u5/wp_reg_n_0_[0] ), + .I1(o6_we), + .I2(\u13/occ0_r_reg_n_0_[16] ), + .O(\wp[0]_i_1__1_n_0 )); + LUT3 #( + .INIT(8'h60)) + \wp[0]_i_1__2 + (.I0(\u6/wp_reg_n_0_[0] ), + .I1(o7_we), + .I2(\u13/occ0_r_reg_n_0_[24] ), + .O(\wp[0]_i_1__2_n_0 )); + LUT3 #( + .INIT(8'h60)) + \wp[0]_i_1__3 + (.I0(\u7/wp_reg_n_0_[0] ), + .I1(o8_we), + .I2(\u13/occ1_r_reg_n_0_[0] ), + .O(\wp[0]_i_1__3_n_0 )); + LUT3 #( + .INIT(8'h60)) + \wp[0]_i_1__4 + (.I0(\u8/wp_reg_n_0_[0] ), + .I1(o9_we), + .I2(\u13/occ1_r_reg_n_0_[8] ), + .O(\wp[0]_i_1__4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair133" *) + LUT3 #( + .INIT(8'hA9)) + \wp[0]_i_1__5 + (.I0(\u9/wp_reg_n_0_[0] ), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .O(\wp[0]_i_1__5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair134" *) + LUT3 #( + .INIT(8'hA9)) + \wp[0]_i_1__6 + (.I0(\u10/wp_reg_n_0_[0] ), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .O(\wp[0]_i_1__6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair135" *) + LUT3 #( + .INIT(8'hA9)) + \wp[0]_i_1__7 + (.I0(\u11/wp_reg_n_0_[0] ), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .O(\wp[0]_i_1__7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'h6A00)) + \wp[1]_i_1 + (.I0(\u3/wp_reg_n_0_[1] ), + .I1(o3_we), + .I2(\u3/wp_reg_n_0_[0] ), + .I3(\u13/occ0_r_reg_n_0_[0] ), + .O(\wp[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h6A00)) + \wp[1]_i_1__0 + (.I0(\u4/wp_reg_n_0_[1] ), + .I1(o4_we), + .I2(\u4/wp_reg_n_0_[0] ), + .I3(\u13/occ0_r_reg_n_0_[8] ), + .O(\wp[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h6A00)) + \wp[1]_i_1__1 + (.I0(\u5/wp_reg_n_0_[1] ), + .I1(o6_we), + .I2(\u5/wp_reg_n_0_[0] ), + .I3(\u13/occ0_r_reg_n_0_[16] ), + .O(\wp[1]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h6A00)) + \wp[1]_i_1__2 + (.I0(\u6/wp_reg_n_0_[1] ), + .I1(o7_we), + .I2(\u6/wp_reg_n_0_[0] ), + .I3(\u13/occ0_r_reg_n_0_[24] ), + .O(\wp[1]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h6A00)) + \wp[1]_i_1__3 + (.I0(\u7/wp_reg_n_0_[1] ), + .I1(o8_we), + .I2(\u7/wp_reg_n_0_[0] ), + .I3(\u13/occ1_r_reg_n_0_[0] ), + .O(\wp[1]_i_1__3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h6A00)) + \wp[1]_i_1__4 + (.I0(\u8/wp_reg_n_0_[1] ), + .I1(o9_we), + .I2(\u8/wp_reg_n_0_[0] ), + .I3(\u13/occ1_r_reg_n_0_[8] ), + .O(\wp[1]_i_1__4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT4 #( + .INIT(16'h01FE)) + \wp[1]_i_1__5 + (.I0(\u9/wp_reg_n_0_[0] ), + .I1(i3_mode[0]), + .I2(i3_mode[1]), + .I3(\u9/p_1_in [0]), + .O(wp_p1[1])); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT4 #( + .INIT(16'h01FE)) + \wp[1]_i_1__6 + (.I0(\u10/wp_reg_n_0_[0] ), + .I1(i4_mode[0]), + .I2(i4_mode[1]), + .I3(\u10/p_1_in [0]), + .O(wp_p1__0[1])); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT4 #( + .INIT(16'h01FE)) + \wp[1]_i_1__7 + (.I0(\u11/wp_reg_n_0_[0] ), + .I1(i6_mode[0]), + .I2(i6_mode[1]), + .I3(\u11/p_1_in [0]), + .O(wp_p1__1[1])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h6AAA0000)) + \wp[2]_i_1 + (.I0(\u3/p_1_in ), + .I1(o3_we), + .I2(\u3/wp_reg_n_0_[0] ), + .I3(\u3/wp_reg_n_0_[1] ), + .I4(\u13/occ0_r_reg_n_0_[0] ), + .O(\wp[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h6AAA0000)) + \wp[2]_i_1__0 + (.I0(\u4/p_1_in ), + .I1(o4_we), + .I2(\u4/wp_reg_n_0_[0] ), + .I3(\u4/wp_reg_n_0_[1] ), + .I4(\u13/occ0_r_reg_n_0_[8] ), + .O(\wp[2]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h6AAA0000)) + \wp[2]_i_1__1 + (.I0(\u5/p_1_in ), + .I1(o6_we), + .I2(\u5/wp_reg_n_0_[0] ), + .I3(\u5/wp_reg_n_0_[1] ), + .I4(\u13/occ0_r_reg_n_0_[16] ), + .O(\wp[2]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'h6AAA0000)) + \wp[2]_i_1__2 + (.I0(\u6/p_1_in ), + .I1(o7_we), + .I2(\u6/wp_reg_n_0_[0] ), + .I3(\u6/wp_reg_n_0_[1] ), + .I4(\u13/occ0_r_reg_n_0_[24] ), + .O(\wp[2]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'h6AAA0000)) + \wp[2]_i_1__3 + (.I0(\u7/p_1_in ), + .I1(o8_we), + .I2(\u7/wp_reg_n_0_[0] ), + .I3(\u7/wp_reg_n_0_[1] ), + .I4(\u13/occ1_r_reg_n_0_[0] ), + .O(\wp[2]_i_1__3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'h6AAA0000)) + \wp[2]_i_1__4 + (.I0(\u8/p_1_in ), + .I1(o9_we), + .I2(\u8/wp_reg_n_0_[0] ), + .I3(\u8/wp_reg_n_0_[1] ), + .I4(\u13/occ1_r_reg_n_0_[8] ), + .O(\wp[2]_i_1__4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT5 #( + .INIT(32'h5557AAA8)) + \wp[2]_i_1__5 + (.I0(\u9/p_1_in [0]), + .I1(i3_mode[1]), + .I2(i3_mode[0]), + .I3(\u9/wp_reg_n_0_[0] ), + .I4(\u9/p_1_in [1]), + .O(wp_p1[2])); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT5 #( + .INIT(32'h5557AAA8)) + \wp[2]_i_1__6 + (.I0(\u10/p_1_in [0]), + .I1(i4_mode[1]), + .I2(i4_mode[0]), + .I3(\u10/wp_reg_n_0_[0] ), + .I4(\u10/p_1_in [1]), + .O(wp_p1__0[2])); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT5 #( + .INIT(32'h5557AAA8)) + \wp[2]_i_1__7 + (.I0(\u11/p_1_in [0]), + .I1(i6_mode[1]), + .I2(i6_mode[0]), + .I3(\u11/wp_reg_n_0_[0] ), + .I4(\u11/p_1_in [1]), + .O(wp_p1__1[2])); + LUT1 #( + .INIT(2'h1)) + \wp[3]_i_1 + (.I0(\u13/icc_r_reg_n_0_[0] ), + .O(\wp[3]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \wp[3]_i_1__0 + (.I0(\u13/icc_r_reg_n_0_[8] ), + .O(\wp[3]_i_1__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \wp[3]_i_1__1 + (.I0(\u13/icc_r_reg_n_0_[16] ), + .O(\wp[3]_i_1__1_n_0 )); + LUT3 #( + .INIT(8'h08)) + \wp[3]_i_2 + (.I0(in_valid_s[0]), + .I1(\u14/u6/en_out_l_reg_n_0 ), + .I2(\u14/u6/en_out_l2_reg_n_0 ), + .O(i3_we)); + LUT3 #( + .INIT(8'h08)) + \wp[3]_i_2__0 + (.I0(in_valid_s[1]), + .I1(\u14/u7/en_out_l_reg_n_0 ), + .I2(\u14/u7/en_out_l2_reg_n_0 ), + .O(i4_we)); + LUT3 #( + .INIT(8'h08)) + \wp[3]_i_2__1 + (.I0(in_valid_s[2]), + .I1(\u14/u8/en_out_l_reg_n_0 ), + .I2(\u14/u8/en_out_l2_reg_n_0 ), + .O(i6_we)); + LUT6 #( + .INIT(64'h01FFFFFFFE000000)) + \wp[3]_i_3 + (.I0(i3_mode[1]), + .I1(i3_mode[0]), + .I2(\u9/wp_reg_n_0_[0] ), + .I3(\u9/p_1_in [0]), + .I4(\u9/p_1_in [1]), + .I5(\u9/wp_reg_n_0_[3] ), + .O(wp_p1[3])); + LUT6 #( + .INIT(64'h01FFFFFFFE000000)) + \wp[3]_i_3__0 + (.I0(i4_mode[1]), + .I1(i4_mode[0]), + .I2(\u10/wp_reg_n_0_[0] ), + .I3(\u10/p_1_in [0]), + .I4(\u10/p_1_in [1]), + .I5(\u10/wp_reg_n_0_[3] ), + .O(wp_p1__0[3])); + LUT6 #( + .INIT(64'h01FFFFFFFE000000)) + \wp[3]_i_3__1 + (.I0(i6_mode[1]), + .I1(i6_mode[0]), + .I2(\u11/wp_reg_n_0_[0] ), + .I3(\u11/p_1_in [0]), + .I4(\u11/p_1_in [1]), + .I5(\u11/wp_reg_n_0_[3] ), + .O(wp_p1__1[3])); +endmodule diff --git a/designs/encrypted_ip/des3_area/ac97_wb_if.v b/designs/encrypted_ip/des3_area/ac97_wb_if.v new file mode 100644 index 000000000..ede42099e --- /dev/null +++ b/designs/encrypted_ip/des3_area/ac97_wb_if.v @@ -0,0 +1,200 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// WISHBONE Interface Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_wb_if.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ +// +// $Date: 2002-09-19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:16 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_wb_if(clk, rst, + + wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, + + adr, dout, rf_din, i3_din, i4_din, i6_din, + rf_we, rf_re, o3_we, o4_we, o6_we, o7_we, o8_we, o9_we, + i3_re, i4_re, i6_re + + ); + +input clk,rst; + +// WISHBONE Interface +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input [31:0] wb_addr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// Internal Interface +output [3:0] adr; +output [31:0] dout; +input [31:0] rf_din, i3_din, i4_din, i6_din; +output rf_we; +output rf_re; +output o3_we, o4_we, o6_we, o7_we, o8_we, o9_we; +output i3_re, i4_re, i6_re; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] wb_data_o; +reg [31:0] dout; +reg wb_ack_o; + +reg rf_we; +reg o3_we, o4_we, o6_we, o7_we, o8_we, o9_we; +reg i3_re, i4_re, i6_re; + +reg we1, we2; +wire we; +reg re2, re1; +wire re; + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +assign adr = wb_addr_i[5:2]; + +assign wb_err_o = 1'b0; + +always @(posedge clk) + dout <= #1 wb_data_i; + +always @(posedge clk) + case(wb_addr_i[6:2]) // synopsys parallel_case full_case + 5'he: wb_data_o <= #1 i3_din; + 5'hf: wb_data_o <= #1 i4_din; + 5'h10: wb_data_o <= #1 i6_din; + default: wb_data_o <= #1 rf_din; + endcase + +always @(posedge clk) + re1 <= #1 !re2 & wb_cyc_i & wb_stb_i & !wb_we_i & `AC97_REG_SEL; + +always @(posedge clk) + re2 <= #1 re & wb_cyc_i & wb_stb_i & !wb_we_i ; + +assign re = re1 & !re2 & wb_cyc_i & wb_stb_i & !wb_we_i; + +assign rf_re = re & (wb_addr_i[6:2] < 5'h8); + +always @(posedge clk) + we1 <= #1 !we & wb_cyc_i & wb_stb_i & wb_we_i & `AC97_REG_SEL; + +always @(posedge clk) + we2 <= #1 we1 & wb_cyc_i & wb_stb_i & wb_we_i; + +assign we = we1 & !we2 & wb_cyc_i & wb_stb_i & wb_we_i; + +always @(posedge clk) + wb_ack_o <= #1 (re | we) & wb_cyc_i & wb_stb_i & ~wb_ack_o; + +always @(posedge clk) + rf_we <= #1 we & (wb_addr_i[6:2] < 5'h8); + +always @(posedge clk) + o3_we <= #1 we & (wb_addr_i[6:2] == 5'h8); + +always @(posedge clk) + o4_we <= #1 we & (wb_addr_i[6:2] == 5'h9); + +always @(posedge clk) + o6_we <= #1 we & (wb_addr_i[6:2] == 5'ha); + +always @(posedge clk) + o7_we <= #1 we & (wb_addr_i[6:2] == 5'hb); + +always @(posedge clk) + o8_we <= #1 we & (wb_addr_i[6:2] == 5'hc); + +always @(posedge clk) + o9_we <= #1 we & (wb_addr_i[6:2] == 5'hd); + +always @(posedge clk) + i3_re <= #1 re & (wb_addr_i[6:2] == 5'he); + +always @(posedge clk) + i4_re <= #1 re & (wb_addr_i[6:2] == 5'hf); + +always @(posedge clk) + i6_re <= #1 re & (wb_addr_i[6:2] == 5'h10); + +endmodule diff --git a/designs/encrypted_ip/des3_area/crp.v b/designs/encrypted_ip/des3_area/crp.v new file mode 100644 index 000000000..5985f2f1a --- /dev/null +++ b/designs/encrypted_ip/des3_area/crp.v @@ -0,0 +1,69 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// CRP //// +//// DES Crypt Module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module crp(P, R, K_sub); +output [1:32] P; +input [1:32] R; +input [1:48] K_sub; + +wire [1:48] E; +wire [1:48] X; +wire [1:32] S; + +assign E[1:48] = { R[32], R[1], R[2], R[3], R[4], R[5], R[4], R[5], + R[6], R[7], R[8], R[9], R[8], R[9], R[10], R[11], + R[12], R[13], R[12], R[13], R[14], R[15], R[16], + R[17], R[16], R[17], R[18], R[19], R[20], R[21], + R[20], R[21], R[22], R[23], R[24], R[25], R[24], + R[25], R[26], R[27], R[28], R[29], R[28], R[29], + R[30], R[31], R[32], R[1]}; + +assign X = E ^ K_sub; + +sbox1 u0( .addr(X[01:06]), .dout(S[01:04]) ); +sbox2 u1( .addr(X[07:12]), .dout(S[05:08]) ); +sbox3 u2( .addr(X[13:18]), .dout(S[09:12]) ); +sbox4 u3( .addr(X[19:24]), .dout(S[13:16]) ); +sbox5 u4( .addr(X[25:30]), .dout(S[17:20]) ); +sbox6 u5( .addr(X[31:36]), .dout(S[21:24]) ); +sbox7 u6( .addr(X[37:42]), .dout(S[25:28]) ); +sbox8 u7( .addr(X[43:48]), .dout(S[29:32]) ); + +assign P[1:32] = { S[16], S[7], S[20], S[21], S[29], S[12], S[28], + S[17], S[1], S[15], S[23], S[26], S[5], S[18], + S[31], S[10], S[2], S[8], S[24], S[14], S[32], + S[27], S[3], S[9], S[19], S[13], S[30], S[6], + S[22], S[11], S[4], S[25]}; + +endmodule diff --git a/designs/encrypted_ip/des3_area/des3_area.v b/designs/encrypted_ip/des3_area/des3_area.v new file mode 100644 index 000000000..948d1c639 --- /dev/null +++ b/designs/encrypted_ip/des3_area/des3_area.v @@ -0,0 +1,148 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// DES //// +//// DES Top Level module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module des3_area(desOut, desIn, key1, key2, key3, decrypt, roundSel, clk); +output [63:0] desOut; +input [63:0] desIn; +input [55:0] key1; +input [55:0] key2; +input [55:0] key3; +input decrypt; +input [5:0] roundSel; +input clk; + +wire [1:48] K_sub; +wire [1:64] IP, FP, tmp; +reg [1:64] FP_R; +reg [1:32] L, R; +wire [1:32] Xin; +wire [1:32] Lout; +wire [1:32] Rout; +wire [1:32] out; + +//assign Lout = (roundSel == 0) ? IP[33:64] : R; +//assign Xin = (roundSel == 0) ? IP[01:32] : L; + + +assign Lout = (roundSel == 0) ? IP[33:64] : + ( (roundSel == 16) ? FP_R[33:64] : + ( (roundSel == 32) ? FP_R[33:64] : + R )); + +assign Xin = (roundSel == 0) ? IP[01:32] : + ( (roundSel == 16) ? FP_R[01:32] : + ( (roundSel == 32) ? FP_R[01:32] : + L )); + + + +/* +always @(roundSel or IP or tmp or R or FP) + case(roundSel) + 6'h0: Lout = IP[33:64]; + 6'h10: Lout = FP[33:64]; + 6'h20: Lout = FP[33:64]; + default: Lout = R; + endcase + +always @(roundSel or IP or tmp or L or FP) + case(roundSel) + 6'h0: Xin = IP[01:32]; + 6'h10: Xin = FP[01:32]; + 6'h20: Xin = FP[01:32]; + default: Xin = L; + endcase +*/ + +always @(posedge clk) + FP_R <= #1 FP; + +assign Rout = Xin ^ out; +assign FP = { Rout, Lout}; + +crp u0( .P(out), .R(Lout), .K_sub(K_sub) ); + +always @(posedge clk) + L <= #1 Lout; + +always @(posedge clk) + R <= #1 Rout; + +// Select a subkey from key. +key_sel3 u1( + .K_sub( K_sub ), + .key1( key1 ), + .key2( key2 ), + .key3( key3 ), + .roundSel( roundSel ), + .decrypt( decrypt ) + ); + +assign tmp[1:64] = { desOut[06], desOut[14], desOut[22], desOut[30], desOut[38], desOut[46], + desOut[54], desOut[62], desOut[04], desOut[12], desOut[20], desOut[28], + desOut[36], desOut[44], desOut[52], desOut[60], desOut[02], desOut[10], + desOut[18], desOut[26], desOut[34], desOut[42], desOut[50], desOut[58], + desOut[00], desOut[08], desOut[16], desOut[24], desOut[32], desOut[40], + desOut[48], desOut[56], desOut[07], desOut[15], desOut[23], desOut[31], + desOut[39], desOut[47], desOut[55], desOut[63], desOut[05], desOut[13], + desOut[21], desOut[29], desOut[37], desOut[45], desOut[53], desOut[61], + desOut[03], desOut[11], desOut[19], desOut[27], desOut[35], desOut[43], + desOut[51], desOut[59], desOut[01], desOut[09], desOut[17], desOut[25], + desOut[33], desOut[41], desOut[49], desOut[57] }; + +// Perform initial permutation +assign IP[1:64] = { desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46], + desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28], + desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10], + desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58], + desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40], + desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31], + desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13], + desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61], + desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43], + desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25], + desIn[33], desIn[41], desIn[49], desIn[57] }; + +// Perform final permutation +assign desOut = { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32], + FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31], + FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30], + FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29], + FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28], + FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27], + FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26], + FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] }; + + +endmodule diff --git a/designs/encrypted_ip/des3_area/des3_area_synthed.v b/designs/encrypted_ip/des3_area/des3_area_synthed.v new file mode 100644 index 000000000..deedbb1ba --- /dev/null +++ b/designs/encrypted_ip/des3_area/des3_area_synthed.v @@ -0,0 +1,8605 @@ +// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021 +// Date : Fri May 26 10:15:20 2023 +// Host : goeders1 running 64-bit Ubuntu 20.04.3 LTS +// Command : write_verilog ./des3_area_synthed.v -force +// Design : des3_area +// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an +// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input +// design files. +// Device : xc7a100tcsg324-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* STRUCTURAL_NETLIST = "yes" *) +module des3_area + (desOut, + desIn, + key1, + key2, + key3, + decrypt, + roundSel, + clk); + output [63:0]desOut; + input [63:0]desIn; + input [55:0]key1; + input [55:0]key2; + input [55:0]key3; + input decrypt; + input [5:0]roundSel; + input clk; + + wire \ ; + wire \ ; + wire \FP_R_reg_n_0_[33] ; + wire \FP_R_reg_n_0_[34] ; + wire \FP_R_reg_n_0_[35] ; + wire \FP_R_reg_n_0_[36] ; + wire \FP_R_reg_n_0_[37] ; + wire \FP_R_reg_n_0_[38] ; + wire \FP_R_reg_n_0_[39] ; + wire \FP_R_reg_n_0_[40] ; + wire \FP_R_reg_n_0_[41] ; + wire \FP_R_reg_n_0_[42] ; + wire \FP_R_reg_n_0_[43] ; + wire \FP_R_reg_n_0_[44] ; + wire \FP_R_reg_n_0_[45] ; + wire \FP_R_reg_n_0_[46] ; + wire \FP_R_reg_n_0_[47] ; + wire \FP_R_reg_n_0_[48] ; + wire \FP_R_reg_n_0_[49] ; + wire \FP_R_reg_n_0_[50] ; + wire \FP_R_reg_n_0_[51] ; + wire \FP_R_reg_n_0_[52] ; + wire \FP_R_reg_n_0_[53] ; + wire \FP_R_reg_n_0_[54] ; + wire \FP_R_reg_n_0_[55] ; + wire \FP_R_reg_n_0_[56] ; + wire \FP_R_reg_n_0_[57] ; + wire \FP_R_reg_n_0_[58] ; + wire \FP_R_reg_n_0_[59] ; + wire \FP_R_reg_n_0_[60] ; + wire \FP_R_reg_n_0_[61] ; + wire \FP_R_reg_n_0_[62] ; + wire \FP_R_reg_n_0_[63] ; + wire \FP_R_reg_n_0_[64] ; + wire [1:32]R; + wire clk; + wire decrypt; + wire [63:0]desIn; + wire [63:0]desOut; + wire \desOut[0]_INST_0_i_1_n_0 ; + wire \desOut[10]_INST_0_i_1_n_0 ; + wire \desOut[12]_INST_0_i_1_n_0 ; + wire \desOut[14]_INST_0_i_1_n_0 ; + wire \desOut[16]_INST_0_i_1_n_0 ; + wire \desOut[18]_INST_0_i_1_n_0 ; + wire \desOut[20]_INST_0_i_1_n_0 ; + wire \desOut[22]_INST_0_i_1_n_0 ; + wire \desOut[24]_INST_0_i_1_n_0 ; + wire \desOut[26]_INST_0_i_1_n_0 ; + wire \desOut[28]_INST_0_i_1_n_0 ; + wire \desOut[2]_INST_0_i_1_n_0 ; + wire \desOut[30]_INST_0_i_1_n_0 ; + wire \desOut[32]_INST_0_i_1_n_0 ; + wire \desOut[34]_INST_0_i_1_n_0 ; + wire \desOut[36]_INST_0_i_1_n_0 ; + wire \desOut[38]_INST_0_i_1_n_0 ; + wire \desOut[40]_INST_0_i_1_n_0 ; + wire \desOut[42]_INST_0_i_1_n_0 ; + wire \desOut[44]_INST_0_i_1_n_0 ; + wire \desOut[46]_INST_0_i_1_n_0 ; + wire \desOut[48]_INST_0_i_1_n_0 ; + wire \desOut[4]_INST_0_i_1_n_0 ; + wire \desOut[50]_INST_0_i_1_n_0 ; + wire \desOut[52]_INST_0_i_1_n_0 ; + wire \desOut[54]_INST_0_i_1_n_0 ; + wire \desOut[56]_INST_0_i_1_n_0 ; + wire \desOut[58]_INST_0_i_1_n_0 ; + wire \desOut[60]_INST_0_i_1_n_0 ; + wire \desOut[62]_INST_0_i_1_n_0 ; + wire \desOut[62]_INST_0_i_2_n_0 ; + wire \desOut[63]_INST_0_i_1_n_0 ; + wire \desOut[63]_INST_0_i_2_n_0 ; + wire \desOut[63]_INST_0_i_3_n_0 ; + wire \desOut[6]_INST_0_i_1_n_0 ; + wire \desOut[8]_INST_0_i_1_n_0 ; + wire g0_b0_i_100__0_n_0; + wire g0_b0_i_100_n_0; + wire g0_b0_i_101__0_n_0; + wire g0_b0_i_101_n_0; + wire g0_b0_i_102__0_n_0; + wire g0_b0_i_102_n_0; + wire g0_b0_i_103__0_n_0; + wire g0_b0_i_103_n_0; + wire g0_b0_i_104__0_n_0; + wire g0_b0_i_104_n_0; + wire g0_b0_i_105_n_0; + wire g0_b0_i_106__0_n_0; + wire g0_b0_i_106_n_0; + wire g0_b0_i_107__0_n_0; + wire g0_b0_i_107_n_0; + wire g0_b0_i_108__0_n_0; + wire g0_b0_i_108_n_0; + wire g0_b0_i_109__0_n_0; + wire g0_b0_i_109_n_0; + wire g0_b0_i_10__0_n_0; + wire g0_b0_i_10__1_n_0; + wire g0_b0_i_10__2_n_0; + wire g0_b0_i_10__3_n_0; + wire g0_b0_i_10__4_n_0; + wire g0_b0_i_10__5_n_0; + wire g0_b0_i_10__6_n_0; + wire g0_b0_i_10_n_0; + wire g0_b0_i_110__0_n_0; + wire g0_b0_i_110_n_0; + wire g0_b0_i_111__0_n_0; + wire g0_b0_i_111_n_0; + wire g0_b0_i_112__0_n_0; + wire g0_b0_i_112_n_0; + wire g0_b0_i_113__0_n_0; + wire g0_b0_i_113_n_0; + wire g0_b0_i_11__0_n_0; + wire g0_b0_i_11__1_n_0; + wire g0_b0_i_11__2_n_0; + wire g0_b0_i_11__3_n_0; + wire g0_b0_i_11__4_n_0; + wire g0_b0_i_11__5_n_0; + wire g0_b0_i_11__6_n_0; + wire g0_b0_i_11_n_0; + wire g0_b0_i_12__0_n_0; + wire g0_b0_i_12__1_n_0; + wire g0_b0_i_12__2_n_0; + wire g0_b0_i_12__3_n_0; + wire g0_b0_i_12__4_n_0; + wire g0_b0_i_12__5_n_0; + wire g0_b0_i_12__6_n_0; + wire g0_b0_i_12_n_0; + wire g0_b0_i_13__0_n_0; + wire g0_b0_i_13__1_n_0; + wire g0_b0_i_13__2_n_0; + wire g0_b0_i_13__3_n_0; + wire g0_b0_i_13__4_n_0; + wire g0_b0_i_13__5_n_0; + wire g0_b0_i_13__6_n_0; + wire g0_b0_i_13_n_0; + wire g0_b0_i_14__0_n_0; + wire g0_b0_i_14__1_n_0; + wire g0_b0_i_14__2_n_0; + wire g0_b0_i_14__3_n_0; + wire g0_b0_i_14__4_n_0; + wire g0_b0_i_14__5_n_0; + wire g0_b0_i_14__6_n_0; + wire g0_b0_i_14_n_0; + wire g0_b0_i_15__0_n_0; + wire g0_b0_i_15__1_n_0; + wire g0_b0_i_15__2_n_0; + wire g0_b0_i_15__3_n_0; + wire g0_b0_i_15__4_n_0; + wire g0_b0_i_15__5_n_0; + wire g0_b0_i_15__6_n_0; + wire g0_b0_i_15_n_0; + wire g0_b0_i_16__0_n_0; + wire g0_b0_i_16__1_n_0; + wire g0_b0_i_16__2_n_0; + wire g0_b0_i_16__3_n_0; + wire g0_b0_i_16__4_n_0; + wire g0_b0_i_16__5_n_0; + wire g0_b0_i_16__6_n_0; + wire g0_b0_i_16_n_0; + wire g0_b0_i_17__0_n_0; + wire g0_b0_i_17__1_n_0; + wire g0_b0_i_17__2_n_0; + wire g0_b0_i_17__3_n_0; + wire g0_b0_i_17__4_n_0; + wire g0_b0_i_17__5_n_0; + wire g0_b0_i_17__6_n_0; + wire g0_b0_i_17_n_0; + wire g0_b0_i_18__0_n_0; + wire g0_b0_i_18__1_n_0; + wire g0_b0_i_18__2_n_0; + wire g0_b0_i_18__3_n_0; + wire g0_b0_i_18__4_n_0; + wire g0_b0_i_18__5_n_0; + wire g0_b0_i_18__6_n_0; + wire g0_b0_i_18_n_0; + wire g0_b0_i_19__0_n_0; + wire g0_b0_i_19__1_n_0; + wire g0_b0_i_19__2_n_0; + wire g0_b0_i_19__3_n_0; + wire g0_b0_i_19__4_n_0; + wire g0_b0_i_19__5_n_0; + wire g0_b0_i_19__6_n_0; + wire g0_b0_i_19_n_0; + wire g0_b0_i_20__0_n_0; + wire g0_b0_i_20__1_n_0; + wire g0_b0_i_20__2_n_0; + wire g0_b0_i_20__3_n_0; + wire g0_b0_i_20__4_n_0; + wire g0_b0_i_20__5_n_0; + wire g0_b0_i_20__6_n_0; + wire g0_b0_i_20_n_0; + wire g0_b0_i_21__0_n_0; + wire g0_b0_i_21__1_n_0; + wire g0_b0_i_21__2_n_0; + wire g0_b0_i_21__3_n_0; + wire g0_b0_i_21__4_n_0; + wire g0_b0_i_21__5_n_0; + wire g0_b0_i_21__6_n_0; + wire g0_b0_i_21_n_0; + wire g0_b0_i_22__0_n_0; + wire g0_b0_i_22__1_n_0; + wire g0_b0_i_22__2_n_0; + wire g0_b0_i_22__3_n_0; + wire g0_b0_i_22__4_n_0; + wire g0_b0_i_22__5_n_0; + wire g0_b0_i_22__6_n_0; + wire g0_b0_i_22_n_0; + wire g0_b0_i_23__0_n_0; + wire g0_b0_i_23__1_n_0; + wire g0_b0_i_23__2_n_0; + wire g0_b0_i_23__3_n_0; + wire g0_b0_i_23__4_n_0; + wire g0_b0_i_23__5_n_0; + wire g0_b0_i_23__6_n_0; + wire g0_b0_i_23_n_0; + wire g0_b0_i_24__0_n_0; + wire g0_b0_i_24__1_n_0; + wire g0_b0_i_24__2_n_0; + wire g0_b0_i_24__3_n_0; + wire g0_b0_i_24__4_n_0; + wire g0_b0_i_24__5_n_0; + wire g0_b0_i_24__6_n_0; + wire g0_b0_i_24_n_0; + wire g0_b0_i_25__0_n_0; + wire g0_b0_i_25__1_n_0; + wire g0_b0_i_25__2_n_0; + wire g0_b0_i_25__3_n_0; + wire g0_b0_i_25__4_n_0; + wire g0_b0_i_25__5_n_0; + wire g0_b0_i_25__6_n_0; + wire g0_b0_i_25_n_0; + wire g0_b0_i_26__0_n_0; + wire g0_b0_i_26__1_n_0; + wire g0_b0_i_26__2_n_0; + wire g0_b0_i_26__3_n_0; + wire g0_b0_i_26__4_n_0; + wire g0_b0_i_26__5_n_0; + wire g0_b0_i_26__6_n_0; + wire g0_b0_i_26_n_0; + wire g0_b0_i_27__0_n_0; + wire g0_b0_i_27__1_n_0; + wire g0_b0_i_27__2_n_0; + wire g0_b0_i_27__3_n_0; + wire g0_b0_i_27__4_n_0; + wire g0_b0_i_27__5_n_0; + wire g0_b0_i_27__6_n_0; + wire g0_b0_i_27_n_0; + wire g0_b0_i_28__0_n_0; + wire g0_b0_i_28__1_n_0; + wire g0_b0_i_28__2_n_0; + wire g0_b0_i_28__3_n_0; + wire g0_b0_i_28__4_n_0; + wire g0_b0_i_28__5_n_0; + wire g0_b0_i_28__6_n_0; + wire g0_b0_i_28_n_0; + wire g0_b0_i_29__0_n_0; + wire g0_b0_i_29__1_n_0; + wire g0_b0_i_29__2_n_0; + wire g0_b0_i_29__3_n_0; + wire g0_b0_i_29__4_n_0; + wire g0_b0_i_29__5_n_0; + wire g0_b0_i_29__6_n_0; + wire g0_b0_i_29_n_0; + wire g0_b0_i_30__0_n_0; + wire g0_b0_i_30__1_n_0; + wire g0_b0_i_30__2_n_0; + wire g0_b0_i_30__3_n_0; + wire g0_b0_i_30__4_n_0; + wire g0_b0_i_30__5_n_0; + wire g0_b0_i_30__6_n_0; + wire g0_b0_i_30_n_0; + wire g0_b0_i_31__0_n_0; + wire g0_b0_i_31__1_n_0; + wire g0_b0_i_31__2_n_0; + wire g0_b0_i_31__3_n_0; + wire g0_b0_i_31__4_n_0; + wire g0_b0_i_31__5_n_0; + wire g0_b0_i_31__6_n_0; + wire g0_b0_i_31_n_0; + wire g0_b0_i_32__0_n_0; + wire g0_b0_i_32__1_n_0; + wire g0_b0_i_32__2_n_0; + wire g0_b0_i_32__3_n_0; + wire g0_b0_i_32__4_n_0; + wire g0_b0_i_32__5_n_0; + wire g0_b0_i_32__6_n_0; + wire g0_b0_i_32_n_0; + wire g0_b0_i_33__0_n_0; + wire g0_b0_i_33__1_n_0; + wire g0_b0_i_33__2_n_0; + wire g0_b0_i_33__3_n_0; + wire g0_b0_i_33__4_n_0; + wire g0_b0_i_33__5_n_0; + wire g0_b0_i_33__6_n_0; + wire g0_b0_i_33_n_0; + wire g0_b0_i_34__0_n_0; + wire g0_b0_i_34__1_n_0; + wire g0_b0_i_34__2_n_0; + wire g0_b0_i_34__3_n_0; + wire g0_b0_i_34__4_n_0; + wire g0_b0_i_34__5_n_0; + wire g0_b0_i_34__6_n_0; + wire g0_b0_i_34_n_0; + wire g0_b0_i_35__0_n_0; + wire g0_b0_i_35__1_n_0; + wire g0_b0_i_35__2_n_0; + wire g0_b0_i_35__3_n_0; + wire g0_b0_i_35__4_n_0; + wire g0_b0_i_35__5_n_0; + wire g0_b0_i_35__6_n_0; + wire g0_b0_i_35_n_0; + wire g0_b0_i_36__0_n_0; + wire g0_b0_i_36__1_n_0; + wire g0_b0_i_36__2_n_0; + wire g0_b0_i_36__3_n_0; + wire g0_b0_i_36__4_n_0; + wire g0_b0_i_36__5_n_0; + wire g0_b0_i_36__6_n_0; + wire g0_b0_i_36_n_0; + wire g0_b0_i_37__0_n_0; + wire g0_b0_i_37__1_n_0; + wire g0_b0_i_37__2_n_0; + wire g0_b0_i_37__3_n_0; + wire g0_b0_i_37__4_n_0; + wire g0_b0_i_37__5_n_0; + wire g0_b0_i_37__6_n_0; + wire g0_b0_i_37_n_0; + wire g0_b0_i_38__0_n_0; + wire g0_b0_i_38__1_n_0; + wire g0_b0_i_38__2_n_0; + wire g0_b0_i_38__3_n_0; + wire g0_b0_i_38__4_n_0; + wire g0_b0_i_38__5_n_0; + wire g0_b0_i_38__6_n_0; + wire g0_b0_i_38_n_0; + wire g0_b0_i_39__0_n_0; + wire g0_b0_i_39__1_n_0; + wire g0_b0_i_39__2_n_0; + wire g0_b0_i_39__3_n_0; + wire g0_b0_i_39__4_n_0; + wire g0_b0_i_39__5_n_0; + wire g0_b0_i_39__6_n_0; + wire g0_b0_i_39_n_0; + wire g0_b0_i_40__0_n_0; + wire g0_b0_i_40__1_n_0; + wire g0_b0_i_40__2_n_0; + wire g0_b0_i_40__3_n_0; + wire g0_b0_i_40__4_n_0; + wire g0_b0_i_40__5_n_0; + wire g0_b0_i_40__6_n_0; + wire g0_b0_i_40_n_0; + wire g0_b0_i_41__0_n_0; + wire g0_b0_i_41__1_n_0; + wire g0_b0_i_41__2_n_0; + wire g0_b0_i_41__3_n_0; + wire g0_b0_i_41__4_n_0; + wire g0_b0_i_41__5_n_0; + wire g0_b0_i_41__6_n_0; + wire g0_b0_i_41_n_0; + wire g0_b0_i_42__0_n_0; + wire g0_b0_i_42__1_n_0; + wire g0_b0_i_42__2_n_0; + wire g0_b0_i_42__3_n_0; + wire g0_b0_i_42__4_n_0; + wire g0_b0_i_42__5_n_0; + wire g0_b0_i_42__6_n_0; + wire g0_b0_i_42_n_0; + wire g0_b0_i_43__0_n_0; + wire g0_b0_i_43__1_n_0; + wire g0_b0_i_43__2_n_0; + wire g0_b0_i_43__3_n_0; + wire g0_b0_i_43__4_n_0; + wire g0_b0_i_43__5_n_0; + wire g0_b0_i_43__6_n_0; + wire g0_b0_i_43_n_0; + wire g0_b0_i_44__0_n_0; + wire g0_b0_i_44__1_n_0; + wire g0_b0_i_44__2_n_0; + wire g0_b0_i_44__3_n_0; + wire g0_b0_i_44__4_n_0; + wire g0_b0_i_44__5_n_0; + wire g0_b0_i_44__6_n_0; + wire g0_b0_i_44_n_0; + wire g0_b0_i_45__0_n_0; + wire g0_b0_i_45__1_n_0; + wire g0_b0_i_45__2_n_0; + wire g0_b0_i_45__3_n_0; + wire g0_b0_i_45__4_n_0; + wire g0_b0_i_45__5_n_0; + wire g0_b0_i_45__6_n_0; + wire g0_b0_i_45_n_0; + wire g0_b0_i_46__0_n_0; + wire g0_b0_i_46__1_n_0; + wire g0_b0_i_46__2_n_0; + wire g0_b0_i_46__3_n_0; + wire g0_b0_i_46__4_n_0; + wire g0_b0_i_46__5_n_0; + wire g0_b0_i_46__6_n_0; + wire g0_b0_i_46_n_0; + wire g0_b0_i_47__0_n_0; + wire g0_b0_i_47__1_n_0; + wire g0_b0_i_47__2_n_0; + wire g0_b0_i_47__3_n_0; + wire g0_b0_i_47__4_n_0; + wire g0_b0_i_47__5_n_0; + wire g0_b0_i_47__6_n_0; + wire g0_b0_i_47_n_0; + wire g0_b0_i_48__0_n_0; + wire g0_b0_i_48__1_n_0; + wire g0_b0_i_48__2_n_0; + wire g0_b0_i_48__3_n_0; + wire g0_b0_i_48__4_n_0; + wire g0_b0_i_48__5_n_0; + wire g0_b0_i_48__6_n_0; + wire g0_b0_i_48_n_0; + wire g0_b0_i_49__0_n_0; + wire g0_b0_i_49__1_n_0; + wire g0_b0_i_49__2_n_0; + wire g0_b0_i_49__3_n_0; + wire g0_b0_i_49__4_n_0; + wire g0_b0_i_49__5_n_0; + wire g0_b0_i_49__6_n_0; + wire g0_b0_i_49_n_0; + wire g0_b0_i_50__0_n_0; + wire g0_b0_i_50__1_n_0; + wire g0_b0_i_50__2_n_0; + wire g0_b0_i_50__3_n_0; + wire g0_b0_i_50__4_n_0; + wire g0_b0_i_50__5_n_0; + wire g0_b0_i_50__6_n_0; + wire g0_b0_i_50_n_0; + wire g0_b0_i_51__0_n_0; + wire g0_b0_i_51__1_n_0; + wire g0_b0_i_51__2_n_0; + wire g0_b0_i_51__3_n_0; + wire g0_b0_i_51__4_n_0; + wire g0_b0_i_51__5_n_0; + wire g0_b0_i_51__6_n_0; + wire g0_b0_i_51_n_0; + wire g0_b0_i_52__0_n_0; + wire g0_b0_i_52__1_n_0; + wire g0_b0_i_52__2_n_0; + wire g0_b0_i_52__3_n_0; + wire g0_b0_i_52__4_n_0; + wire g0_b0_i_52__5_n_0; + wire g0_b0_i_52__6_n_0; + wire g0_b0_i_52_n_0; + wire g0_b0_i_53__0_n_0; + wire g0_b0_i_53__1_n_0; + wire g0_b0_i_53__2_n_0; + wire g0_b0_i_53__3_n_0; + wire g0_b0_i_53__4_n_0; + wire g0_b0_i_53__5_n_0; + wire g0_b0_i_53__6_n_0; + wire g0_b0_i_53_n_0; + wire g0_b0_i_54__0_n_0; + wire g0_b0_i_54__1_n_0; + wire g0_b0_i_54__2_n_0; + wire g0_b0_i_54__3_n_0; + wire g0_b0_i_54__4_n_0; + wire g0_b0_i_54__5_n_0; + wire g0_b0_i_54__6_n_0; + wire g0_b0_i_54_n_0; + wire g0_b0_i_55__0_n_0; + wire g0_b0_i_55__1_n_0; + wire g0_b0_i_55__2_n_0; + wire g0_b0_i_55__3_n_0; + wire g0_b0_i_55__4_n_0; + wire g0_b0_i_55__5_n_0; + wire g0_b0_i_55__6_n_0; + wire g0_b0_i_55_n_0; + wire g0_b0_i_56__0_n_0; + wire g0_b0_i_56__1_n_0; + wire g0_b0_i_56__2_n_0; + wire g0_b0_i_56__3_n_0; + wire g0_b0_i_56__4_n_0; + wire g0_b0_i_56__5_n_0; + wire g0_b0_i_56__6_n_0; + wire g0_b0_i_56_n_0; + wire g0_b0_i_57__0_n_0; + wire g0_b0_i_57__1_n_0; + wire g0_b0_i_57__2_n_0; + wire g0_b0_i_57__3_n_0; + wire g0_b0_i_57__4_n_0; + wire g0_b0_i_57__5_n_0; + wire g0_b0_i_57__6_n_0; + wire g0_b0_i_57_n_0; + wire g0_b0_i_58__0_n_0; + wire g0_b0_i_58__1_n_0; + wire g0_b0_i_58__2_n_0; + wire g0_b0_i_58__3_n_0; + wire g0_b0_i_58__4_n_0; + wire g0_b0_i_58__5_n_0; + wire g0_b0_i_58__6_n_0; + wire g0_b0_i_58_n_0; + wire g0_b0_i_59__0_n_0; + wire g0_b0_i_59__1_n_0; + wire g0_b0_i_59__2_n_0; + wire g0_b0_i_59__3_n_0; + wire g0_b0_i_59__4_n_0; + wire g0_b0_i_59__5_n_0; + wire g0_b0_i_59__6_n_0; + wire g0_b0_i_59_n_0; + wire g0_b0_i_60__0_n_0; + wire g0_b0_i_60__1_n_0; + wire g0_b0_i_60__2_n_0; + wire g0_b0_i_60__3_n_0; + wire g0_b0_i_60__4_n_0; + wire g0_b0_i_60__5_n_0; + wire g0_b0_i_60__6_n_0; + wire g0_b0_i_60_n_0; + wire g0_b0_i_61__0_n_0; + wire g0_b0_i_61__1_n_0; + wire g0_b0_i_61__2_n_0; + wire g0_b0_i_61__3_n_0; + wire g0_b0_i_61__4_n_0; + wire g0_b0_i_61__5_n_0; + wire g0_b0_i_61__6_n_0; + wire g0_b0_i_61_n_0; + wire g0_b0_i_62__0_n_0; + wire g0_b0_i_62__1_n_0; + wire g0_b0_i_62__2_n_0; + wire g0_b0_i_62__3_n_0; + wire g0_b0_i_62__4_n_0; + wire g0_b0_i_62__5_n_0; + wire g0_b0_i_62__6_n_0; + wire g0_b0_i_62_n_0; + wire g0_b0_i_63__0_n_0; + wire g0_b0_i_63__1_n_0; + wire g0_b0_i_63__2_n_0; + wire g0_b0_i_63__3_n_0; + wire g0_b0_i_63__4_n_0; + wire g0_b0_i_63__5_n_0; + wire g0_b0_i_63__6_n_0; + wire g0_b0_i_63_n_0; + wire g0_b0_i_64__0_n_0; + wire g0_b0_i_64__1_n_0; + wire g0_b0_i_64__2_n_0; + wire g0_b0_i_64__3_n_0; + wire g0_b0_i_64__4_n_0; + wire g0_b0_i_64__5_n_0; + wire g0_b0_i_64__6_n_0; + wire g0_b0_i_64_n_0; + wire g0_b0_i_65__0_n_0; + wire g0_b0_i_65__1_n_0; + wire g0_b0_i_65__2_n_0; + wire g0_b0_i_65__3_n_0; + wire g0_b0_i_65__4_n_0; + wire g0_b0_i_65__6_n_0; + wire g0_b0_i_65_n_0; + wire g0_b0_i_66__0_n_0; + wire g0_b0_i_66__1_n_0; + wire g0_b0_i_66__2_n_0; + wire g0_b0_i_66__3_n_0; + wire g0_b0_i_66__4_n_0; + wire g0_b0_i_66__6_n_0; + wire g0_b0_i_66_n_0; + wire g0_b0_i_67__0_n_0; + wire g0_b0_i_67__1_n_0; + wire g0_b0_i_67__2_n_0; + wire g0_b0_i_67__3_n_0; + wire g0_b0_i_67__4_n_0; + wire g0_b0_i_67__5_n_0; + wire g0_b0_i_67_n_0; + wire g0_b0_i_68__0_n_0; + wire g0_b0_i_68__1_n_0; + wire g0_b0_i_68__2_n_0; + wire g0_b0_i_68__3_n_0; + wire g0_b0_i_68__4_n_0; + wire g0_b0_i_68__6_n_0; + wire g0_b0_i_68_n_0; + wire g0_b0_i_69__0_n_0; + wire g0_b0_i_69__1_n_0; + wire g0_b0_i_69__2_n_0; + wire g0_b0_i_69__3_n_0; + wire g0_b0_i_69__4_n_0; + wire g0_b0_i_69__5_n_0; + wire g0_b0_i_69_n_0; + wire g0_b0_i_70__0_n_0; + wire g0_b0_i_70__1_n_0; + wire g0_b0_i_70__2_n_0; + wire g0_b0_i_70__3_n_0; + wire g0_b0_i_70__4_n_0; + wire g0_b0_i_70__5_n_0; + wire g0_b0_i_70__6_n_0; + wire g0_b0_i_70_n_0; + wire g0_b0_i_71__0_n_0; + wire g0_b0_i_71__1_n_0; + wire g0_b0_i_71__2_n_0; + wire g0_b0_i_71__3_n_0; + wire g0_b0_i_71__4_n_0; + wire g0_b0_i_71__6_n_0; + wire g0_b0_i_71_n_0; + wire g0_b0_i_72__0_n_0; + wire g0_b0_i_72__1_n_0; + wire g0_b0_i_72__2_n_0; + wire g0_b0_i_72__3_n_0; + wire g0_b0_i_72__4_n_0; + wire g0_b0_i_72__6_n_0; + wire g0_b0_i_72_n_0; + wire g0_b0_i_73__0_n_0; + wire g0_b0_i_73__1_n_0; + wire g0_b0_i_73__2_n_0; + wire g0_b0_i_73__3_n_0; + wire g0_b0_i_73__4_n_0; + wire g0_b0_i_73__5_n_0; + wire g0_b0_i_73__6_n_0; + wire g0_b0_i_73_n_0; + wire g0_b0_i_74__0_n_0; + wire g0_b0_i_74__1_n_0; + wire g0_b0_i_74__2_n_0; + wire g0_b0_i_74__3_n_0; + wire g0_b0_i_74__4_n_0; + wire g0_b0_i_74__5_n_0; + wire g0_b0_i_74__6_n_0; + wire g0_b0_i_74_n_0; + wire g0_b0_i_75__0_n_0; + wire g0_b0_i_75__1_n_0; + wire g0_b0_i_75__2_n_0; + wire g0_b0_i_75__3_n_0; + wire g0_b0_i_75__4_n_0; + wire g0_b0_i_75__6_n_0; + wire g0_b0_i_75_n_0; + wire g0_b0_i_76__0_n_0; + wire g0_b0_i_76__1_n_0; + wire g0_b0_i_76__2_n_0; + wire g0_b0_i_76__3_n_0; + wire g0_b0_i_76__4_n_0; + wire g0_b0_i_76__5_n_0; + wire g0_b0_i_76_n_0; + wire g0_b0_i_77__0_n_0; + wire g0_b0_i_77__1_n_0; + wire g0_b0_i_77__2_n_0; + wire g0_b0_i_77__3_n_0; + wire g0_b0_i_77__4_n_0; + wire g0_b0_i_77__5_n_0; + wire g0_b0_i_77__6_n_0; + wire g0_b0_i_77_n_0; + wire g0_b0_i_78__0_n_0; + wire g0_b0_i_78__1_n_0; + wire g0_b0_i_78__2_n_0; + wire g0_b0_i_78__3_n_0; + wire g0_b0_i_78__4_n_0; + wire g0_b0_i_78__5_n_0; + wire g0_b0_i_78__6_n_0; + wire g0_b0_i_78_n_0; + wire g0_b0_i_79__0_n_0; + wire g0_b0_i_79__1_n_0; + wire g0_b0_i_79__2_n_0; + wire g0_b0_i_79__3_n_0; + wire g0_b0_i_79__4_n_0; + wire g0_b0_i_79__6_n_0; + wire g0_b0_i_79_n_0; + wire g0_b0_i_7__0_n_0; + wire g0_b0_i_7__1_n_0; + wire g0_b0_i_7__2_n_0; + wire g0_b0_i_7__3_n_0; + wire g0_b0_i_7__4_n_0; + wire g0_b0_i_7__5_n_0; + wire g0_b0_i_7__6_n_0; + wire g0_b0_i_7_n_0; + wire g0_b0_i_80__0_n_0; + wire g0_b0_i_80__1_n_0; + wire g0_b0_i_80__2_n_0; + wire g0_b0_i_80__3_n_0; + wire g0_b0_i_80__4_n_0; + wire g0_b0_i_80__6_n_0; + wire g0_b0_i_80_n_0; + wire g0_b0_i_81__0_n_0; + wire g0_b0_i_81__1_n_0; + wire g0_b0_i_81__2_n_0; + wire g0_b0_i_81__3_n_0; + wire g0_b0_i_81__4_n_0; + wire g0_b0_i_81__6_n_0; + wire g0_b0_i_81_n_0; + wire g0_b0_i_82__0_n_0; + wire g0_b0_i_82__1_n_0; + wire g0_b0_i_82__2_n_0; + wire g0_b0_i_82__3_n_0; + wire g0_b0_i_82__4_n_0; + wire g0_b0_i_82__5_n_0; + wire g0_b0_i_82__6_n_0; + wire g0_b0_i_82_n_0; + wire g0_b0_i_83__0_n_0; + wire g0_b0_i_83__1_n_0; + wire g0_b0_i_83__2_n_0; + wire g0_b0_i_83__3_n_0; + wire g0_b0_i_83__4_n_0; + wire g0_b0_i_83__5_n_0; + wire g0_b0_i_83__6_n_0; + wire g0_b0_i_83_n_0; + wire g0_b0_i_84__0_n_0; + wire g0_b0_i_84__1_n_0; + wire g0_b0_i_84__2_n_0; + wire g0_b0_i_84__3_n_0; + wire g0_b0_i_84__4_n_0; + wire g0_b0_i_84__5_n_0; + wire g0_b0_i_84__6_n_0; + wire g0_b0_i_84_n_0; + wire g0_b0_i_85__0_n_0; + wire g0_b0_i_85__1_n_0; + wire g0_b0_i_85_n_0; + wire g0_b0_i_86__0_n_0; + wire g0_b0_i_86_n_0; + wire g0_b0_i_87__0_n_0; + wire g0_b0_i_88__0_n_0; + wire g0_b0_i_88_n_0; + wire g0_b0_i_89__0_n_0; + wire g0_b0_i_89_n_0; + wire g0_b0_i_8__0_n_0; + wire g0_b0_i_8__1_n_0; + wire g0_b0_i_8__2_n_0; + wire g0_b0_i_8__3_n_0; + wire g0_b0_i_8__4_n_0; + wire g0_b0_i_8__5_n_0; + wire g0_b0_i_8__6_n_0; + wire g0_b0_i_8_n_0; + wire g0_b0_i_90__0_n_0; + wire g0_b0_i_91_n_0; + wire g0_b0_i_92_n_0; + wire g0_b0_i_93_n_0; + wire g0_b0_i_94__0_n_0; + wire g0_b0_i_94_n_0; + wire g0_b0_i_95__0_n_0; + wire g0_b0_i_95_n_0; + wire g0_b0_i_96__0_n_0; + wire g0_b0_i_96_n_0; + wire g0_b0_i_97__0_n_0; + wire g0_b0_i_97_n_0; + wire g0_b0_i_98__0_n_0; + wire g0_b0_i_98_n_0; + wire g0_b0_i_99__0_n_0; + wire g0_b0_i_99_n_0; + wire g0_b0_i_9__0_n_0; + wire g0_b0_i_9__1_n_0; + wire g0_b0_i_9__2_n_0; + wire g0_b0_i_9__3_n_0; + wire g0_b0_i_9__4_n_0; + wire g0_b0_i_9__5_n_0; + wire g0_b0_i_9__6_n_0; + wire g0_b0_i_9_n_0; + wire [55:0]key1; + wire [55:0]key2; + wire [55:0]key3; + wire [1:32]out; + wire [5:0]roundSel; + wire [1:48]\u0/X ; + wire \u1/decrypt_int__1 ; + wire \u1/p_0_in ; + wire \u1/p_10_in ; + wire \u1/p_11_in ; + wire \u1/p_13_in ; + wire \u1/p_14_in ; + wire \u1/p_15_in ; + wire \u1/p_16_in ; + wire \u1/p_17_in ; + wire \u1/p_18_in ; + wire \u1/p_19_in ; + wire \u1/p_1_in ; + wire \u1/p_2_in ; + wire \u1/p_3_in ; + wire \u1/p_5_in ; + wire \u1/p_7_in ; + wire \u1/p_8_in ; + wire \u1/p_9_in ; + + FDRE \FP_R_reg[33] + (.C(clk), + .CE(\ ), + .D(desOut[7]), + .Q(\FP_R_reg_n_0_[33] ), + .R(\ )); + FDRE \FP_R_reg[34] + (.C(clk), + .CE(\ ), + .D(desOut[15]), + .Q(\FP_R_reg_n_0_[34] ), + .R(\ )); + FDRE \FP_R_reg[35] + (.C(clk), + .CE(\ ), + .D(desOut[23]), + .Q(\FP_R_reg_n_0_[35] ), + .R(\ )); + FDRE \FP_R_reg[36] + (.C(clk), + .CE(\ ), + .D(desOut[31]), + .Q(\FP_R_reg_n_0_[36] ), + .R(\ )); + FDRE \FP_R_reg[37] + (.C(clk), + .CE(\ ), + .D(desOut[39]), + .Q(\FP_R_reg_n_0_[37] ), + .R(\ )); + FDRE \FP_R_reg[38] + (.C(clk), + .CE(\ ), + .D(desOut[47]), + .Q(\FP_R_reg_n_0_[38] ), + .R(\ )); + FDRE \FP_R_reg[39] + (.C(clk), + .CE(\ ), + .D(desOut[55]), + .Q(\FP_R_reg_n_0_[39] ), + .R(\ )); + FDRE \FP_R_reg[40] + (.C(clk), + .CE(\ ), + .D(desOut[63]), + .Q(\FP_R_reg_n_0_[40] ), + .R(\ )); + FDRE \FP_R_reg[41] + (.C(clk), + .CE(\ ), + .D(desOut[5]), + .Q(\FP_R_reg_n_0_[41] ), + .R(\ )); + FDRE \FP_R_reg[42] + (.C(clk), + .CE(\ ), + .D(desOut[13]), + .Q(\FP_R_reg_n_0_[42] ), + .R(\ )); + FDRE \FP_R_reg[43] + (.C(clk), + .CE(\ ), + .D(desOut[21]), + .Q(\FP_R_reg_n_0_[43] ), + .R(\ )); + FDRE \FP_R_reg[44] + (.C(clk), + .CE(\ ), + .D(desOut[29]), + .Q(\FP_R_reg_n_0_[44] ), + .R(\ )); + FDRE \FP_R_reg[45] + (.C(clk), + .CE(\ ), + .D(desOut[37]), + .Q(\FP_R_reg_n_0_[45] ), + .R(\ )); + FDRE \FP_R_reg[46] + (.C(clk), + .CE(\ ), + .D(desOut[45]), + .Q(\FP_R_reg_n_0_[46] ), + .R(\ )); + FDRE \FP_R_reg[47] + (.C(clk), + .CE(\ ), + .D(desOut[53]), + .Q(\FP_R_reg_n_0_[47] ), + .R(\ )); + FDRE \FP_R_reg[48] + (.C(clk), + .CE(\ ), + .D(desOut[61]), + .Q(\FP_R_reg_n_0_[48] ), + .R(\ )); + FDRE \FP_R_reg[49] + (.C(clk), + .CE(\ ), + .D(desOut[3]), + .Q(\FP_R_reg_n_0_[49] ), + .R(\ )); + FDRE \FP_R_reg[50] + (.C(clk), + .CE(\ ), + .D(desOut[11]), + .Q(\FP_R_reg_n_0_[50] ), + .R(\ )); + FDRE \FP_R_reg[51] + (.C(clk), + .CE(\ ), + .D(desOut[19]), + .Q(\FP_R_reg_n_0_[51] ), + .R(\ )); + FDRE \FP_R_reg[52] + (.C(clk), + .CE(\ ), + .D(desOut[27]), + .Q(\FP_R_reg_n_0_[52] ), + .R(\ )); + FDRE \FP_R_reg[53] + (.C(clk), + .CE(\ ), + .D(desOut[35]), + .Q(\FP_R_reg_n_0_[53] ), + .R(\ )); + FDRE \FP_R_reg[54] + (.C(clk), + .CE(\ ), + .D(desOut[43]), + .Q(\FP_R_reg_n_0_[54] ), + .R(\ )); + FDRE \FP_R_reg[55] + (.C(clk), + .CE(\ ), + .D(desOut[51]), + .Q(\FP_R_reg_n_0_[55] ), + .R(\ )); + FDRE \FP_R_reg[56] + (.C(clk), + .CE(\ ), + .D(desOut[59]), + .Q(\FP_R_reg_n_0_[56] ), + .R(\ )); + FDRE \FP_R_reg[57] + (.C(clk), + .CE(\ ), + .D(desOut[1]), + .Q(\FP_R_reg_n_0_[57] ), + .R(\ )); + FDRE \FP_R_reg[58] + (.C(clk), + .CE(\ ), + .D(desOut[9]), + .Q(\FP_R_reg_n_0_[58] ), + .R(\ )); + FDRE \FP_R_reg[59] + (.C(clk), + .CE(\ ), + .D(desOut[17]), + .Q(\FP_R_reg_n_0_[59] ), + .R(\ )); + FDRE \FP_R_reg[60] + (.C(clk), + .CE(\ ), + .D(desOut[25]), + .Q(\FP_R_reg_n_0_[60] ), + .R(\ )); + FDRE \FP_R_reg[61] + (.C(clk), + .CE(\ ), + .D(desOut[33]), + .Q(\FP_R_reg_n_0_[61] ), + .R(\ )); + FDRE \FP_R_reg[62] + (.C(clk), + .CE(\ ), + .D(desOut[41]), + .Q(\FP_R_reg_n_0_[62] ), + .R(\ )); + FDRE \FP_R_reg[63] + (.C(clk), + .CE(\ ), + .D(desOut[49]), + .Q(\FP_R_reg_n_0_[63] ), + .R(\ )); + FDRE \FP_R_reg[64] + (.C(clk), + .CE(\ ), + .D(desOut[57]), + .Q(\FP_R_reg_n_0_[64] ), + .R(\ )); + GND GND + (.G(\ )); + FDRE \R_reg[10] + (.C(clk), + .CE(\ ), + .D(desOut[12]), + .Q(R[10]), + .R(\ )); + FDRE \R_reg[11] + (.C(clk), + .CE(\ ), + .D(desOut[20]), + .Q(R[11]), + .R(\ )); + FDRE \R_reg[12] + (.C(clk), + .CE(\ ), + .D(desOut[28]), + .Q(R[12]), + .R(\ )); + FDRE \R_reg[13] + (.C(clk), + .CE(\ ), + .D(desOut[36]), + .Q(R[13]), + .R(\ )); + FDRE \R_reg[14] + (.C(clk), + .CE(\ ), + .D(desOut[44]), + .Q(R[14]), + .R(\ )); + FDRE \R_reg[15] + (.C(clk), + .CE(\ ), + .D(desOut[52]), + .Q(R[15]), + .R(\ )); + FDRE \R_reg[16] + (.C(clk), + .CE(\ ), + .D(desOut[60]), + .Q(R[16]), + .R(\ )); + FDRE \R_reg[17] + (.C(clk), + .CE(\ ), + .D(desOut[2]), + .Q(R[17]), + .R(\ )); + FDRE \R_reg[18] + (.C(clk), + .CE(\ ), + .D(desOut[10]), + .Q(R[18]), + .R(\ )); + FDRE \R_reg[19] + (.C(clk), + .CE(\ ), + .D(desOut[18]), + .Q(R[19]), + .R(\ )); + FDRE \R_reg[1] + (.C(clk), + .CE(\ ), + .D(desOut[6]), + .Q(R[1]), + .R(\ )); + FDRE \R_reg[20] + (.C(clk), + .CE(\ ), + .D(desOut[26]), + .Q(R[20]), + .R(\ )); + FDRE \R_reg[21] + (.C(clk), + .CE(\ ), + .D(desOut[34]), + .Q(R[21]), + .R(\ )); + FDRE \R_reg[22] + (.C(clk), + .CE(\ ), + .D(desOut[42]), + .Q(R[22]), + .R(\ )); + FDRE \R_reg[23] + (.C(clk), + .CE(\ ), + .D(desOut[50]), + .Q(R[23]), + .R(\ )); + FDRE \R_reg[24] + (.C(clk), + .CE(\ ), + .D(desOut[58]), + .Q(R[24]), + .R(\ )); + FDRE \R_reg[25] + (.C(clk), + .CE(\ ), + .D(desOut[0]), + .Q(R[25]), + .R(\ )); + FDRE \R_reg[26] + (.C(clk), + .CE(\ ), + .D(desOut[8]), + .Q(R[26]), + .R(\ )); + FDRE \R_reg[27] + (.C(clk), + .CE(\ ), + .D(desOut[16]), + .Q(R[27]), + .R(\ )); + FDRE \R_reg[28] + (.C(clk), + .CE(\ ), + .D(desOut[24]), + .Q(R[28]), + .R(\ )); + FDRE \R_reg[29] + (.C(clk), + .CE(\ ), + .D(desOut[32]), + .Q(R[29]), + .R(\ )); + FDRE \R_reg[2] + (.C(clk), + .CE(\ ), + .D(desOut[14]), + .Q(R[2]), + .R(\ )); + FDRE \R_reg[30] + (.C(clk), + .CE(\ ), + .D(desOut[40]), + .Q(R[30]), + .R(\ )); + FDRE \R_reg[31] + (.C(clk), + .CE(\ ), + .D(desOut[48]), + .Q(R[31]), + .R(\ )); + FDRE \R_reg[32] + (.C(clk), + .CE(\ ), + .D(desOut[56]), + .Q(R[32]), + .R(\ )); + FDRE \R_reg[3] + (.C(clk), + .CE(\ ), + .D(desOut[22]), + .Q(R[3]), + .R(\ )); + FDRE \R_reg[4] + (.C(clk), + .CE(\ ), + .D(desOut[30]), + .Q(R[4]), + .R(\ )); + FDRE \R_reg[5] + (.C(clk), + .CE(\ ), + .D(desOut[38]), + .Q(R[5]), + .R(\ )); + FDRE \R_reg[6] + (.C(clk), + .CE(\ ), + .D(desOut[46]), + .Q(R[6]), + .R(\ )); + FDRE \R_reg[7] + (.C(clk), + .CE(\ ), + .D(desOut[54]), + .Q(R[7]), + .R(\ )); + FDRE \R_reg[8] + (.C(clk), + .CE(\ ), + .D(desOut[62]), + .Q(R[8]), + .R(\ )); + FDRE \R_reg[9] + (.C(clk), + .CE(\ ), + .D(desOut[4]), + .Q(R[9]), + .R(\ )); + VCC VCC + (.P(\ )); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[0]_INST_0 + (.I0(out[25]), + .I1(\desOut[0]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[57] ), + .I5(roundSel[3]), + .O(desOut[0])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[0]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[57] ), + .I2(roundSel[5]), + .I3(R[25]), + .I4(roundSel[4]), + .I5(desIn[0]), + .O(\desOut[0]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[10]_INST_0 + (.I0(out[18]), + .I1(\desOut[10]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[50] ), + .I5(roundSel[3]), + .O(desOut[10])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[10]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[50] ), + .I2(roundSel[5]), + .I3(R[18]), + .I4(roundSel[4]), + .I5(desIn[10]), + .O(\desOut[10]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[11]_INST_0 + (.I0(desIn[11]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[18]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[50] ), + .O(desOut[11])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[12]_INST_0 + (.I0(out[10]), + .I1(\desOut[12]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[42] ), + .I5(roundSel[3]), + .O(desOut[12])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[12]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[42] ), + .I2(roundSel[5]), + .I3(R[10]), + .I4(roundSel[4]), + .I5(desIn[12]), + .O(\desOut[12]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[13]_INST_0 + (.I0(desIn[13]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[10]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[42] ), + .O(desOut[13])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[14]_INST_0 + (.I0(out[2]), + .I1(\desOut[14]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[34] ), + .I5(roundSel[3]), + .O(desOut[14])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[14]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[34] ), + .I2(roundSel[5]), + .I3(R[2]), + .I4(roundSel[4]), + .I5(desIn[14]), + .O(\desOut[14]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[15]_INST_0 + (.I0(desIn[15]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[2]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[34] ), + .O(desOut[15])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[16]_INST_0 + (.I0(out[27]), + .I1(\desOut[16]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[59] ), + .I5(roundSel[3]), + .O(desOut[16])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[16]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[59] ), + .I2(roundSel[5]), + .I3(R[27]), + .I4(roundSel[4]), + .I5(desIn[16]), + .O(\desOut[16]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[17]_INST_0 + (.I0(desIn[17]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[27]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[59] ), + .O(desOut[17])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[18]_INST_0 + (.I0(out[19]), + .I1(\desOut[18]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[51] ), + .I5(roundSel[3]), + .O(desOut[18])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[18]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[51] ), + .I2(roundSel[5]), + .I3(R[19]), + .I4(roundSel[4]), + .I5(desIn[18]), + .O(\desOut[18]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[19]_INST_0 + (.I0(desIn[19]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[19]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[51] ), + .O(desOut[19])); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[1]_INST_0 + (.I0(desIn[1]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[25]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[57] ), + .O(desOut[1])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[20]_INST_0 + (.I0(out[11]), + .I1(\desOut[20]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[43] ), + .I5(roundSel[3]), + .O(desOut[20])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[20]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[43] ), + .I2(roundSel[5]), + .I3(R[11]), + .I4(roundSel[4]), + .I5(desIn[20]), + .O(\desOut[20]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[21]_INST_0 + (.I0(desIn[21]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[11]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[43] ), + .O(desOut[21])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[22]_INST_0 + (.I0(out[3]), + .I1(\desOut[22]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[35] ), + .I5(roundSel[3]), + .O(desOut[22])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[22]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[35] ), + .I2(roundSel[5]), + .I3(R[3]), + .I4(roundSel[4]), + .I5(desIn[22]), + .O(\desOut[22]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[23]_INST_0 + (.I0(desIn[23]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[3]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[35] ), + .O(desOut[23])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[24]_INST_0 + (.I0(out[28]), + .I1(\desOut[24]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[60] ), + .I5(roundSel[3]), + .O(desOut[24])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[24]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[60] ), + .I2(roundSel[5]), + .I3(R[28]), + .I4(roundSel[4]), + .I5(desIn[24]), + .O(\desOut[24]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[25]_INST_0 + (.I0(desIn[25]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[28]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[60] ), + .O(desOut[25])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[26]_INST_0 + (.I0(out[20]), + .I1(\desOut[26]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[52] ), + .I5(roundSel[3]), + .O(desOut[26])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[26]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[52] ), + .I2(roundSel[5]), + .I3(R[20]), + .I4(roundSel[4]), + .I5(desIn[26]), + .O(\desOut[26]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[27]_INST_0 + (.I0(desIn[27]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[20]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[52] ), + .O(desOut[27])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[28]_INST_0 + (.I0(out[12]), + .I1(\desOut[28]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[44] ), + .I5(roundSel[3]), + .O(desOut[28])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[28]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[44] ), + .I2(roundSel[5]), + .I3(R[12]), + .I4(roundSel[4]), + .I5(desIn[28]), + .O(\desOut[28]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[29]_INST_0 + (.I0(desIn[29]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[12]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[44] ), + .O(desOut[29])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[2]_INST_0 + (.I0(out[17]), + .I1(\desOut[2]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[49] ), + .I5(roundSel[3]), + .O(desOut[2])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[2]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[49] ), + .I2(roundSel[5]), + .I3(R[17]), + .I4(roundSel[4]), + .I5(desIn[2]), + .O(\desOut[2]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[30]_INST_0 + (.I0(out[4]), + .I1(\desOut[30]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[36] ), + .I5(roundSel[3]), + .O(desOut[30])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[30]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[36] ), + .I2(roundSel[5]), + .I3(R[4]), + .I4(roundSel[4]), + .I5(desIn[30]), + .O(\desOut[30]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[31]_INST_0 + (.I0(desIn[31]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[4]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[36] ), + .O(desOut[31])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[32]_INST_0 + (.I0(out[29]), + .I1(\desOut[32]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[61] ), + .I5(roundSel[3]), + .O(desOut[32])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[32]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[61] ), + .I2(roundSel[5]), + .I3(R[29]), + .I4(roundSel[4]), + .I5(desIn[32]), + .O(\desOut[32]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[33]_INST_0 + (.I0(desIn[33]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[29]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[61] ), + .O(desOut[33])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[34]_INST_0 + (.I0(out[21]), + .I1(\desOut[34]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[53] ), + .I5(roundSel[3]), + .O(desOut[34])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[34]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[53] ), + .I2(roundSel[5]), + .I3(R[21]), + .I4(roundSel[4]), + .I5(desIn[34]), + .O(\desOut[34]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[35]_INST_0 + (.I0(desIn[35]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[21]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[53] ), + .O(desOut[35])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[36]_INST_0 + (.I0(out[13]), + .I1(\desOut[36]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[45] ), + .I5(roundSel[3]), + .O(desOut[36])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[36]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[45] ), + .I2(roundSel[5]), + .I3(R[13]), + .I4(roundSel[4]), + .I5(desIn[36]), + .O(\desOut[36]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[37]_INST_0 + (.I0(desIn[37]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[13]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[45] ), + .O(desOut[37])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[38]_INST_0 + (.I0(out[5]), + .I1(\desOut[38]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[37] ), + .I5(roundSel[3]), + .O(desOut[38])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[38]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[37] ), + .I2(roundSel[5]), + .I3(R[5]), + .I4(roundSel[4]), + .I5(desIn[38]), + .O(\desOut[38]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[39]_INST_0 + (.I0(desIn[39]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[5]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[37] ), + .O(desOut[39])); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[3]_INST_0 + (.I0(desIn[3]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[17]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[49] ), + .O(desOut[3])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[40]_INST_0 + (.I0(out[30]), + .I1(\desOut[40]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[62] ), + .I5(roundSel[3]), + .O(desOut[40])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[40]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[62] ), + .I2(roundSel[5]), + .I3(R[30]), + .I4(roundSel[4]), + .I5(desIn[40]), + .O(\desOut[40]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[41]_INST_0 + (.I0(desIn[41]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[30]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[62] ), + .O(desOut[41])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[42]_INST_0 + (.I0(out[22]), + .I1(\desOut[42]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[54] ), + .I5(roundSel[3]), + .O(desOut[42])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[42]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[54] ), + .I2(roundSel[5]), + .I3(R[22]), + .I4(roundSel[4]), + .I5(desIn[42]), + .O(\desOut[42]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[43]_INST_0 + (.I0(desIn[43]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[22]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[54] ), + .O(desOut[43])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[44]_INST_0 + (.I0(out[14]), + .I1(\desOut[44]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[46] ), + .I5(roundSel[3]), + .O(desOut[44])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[44]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[46] ), + .I2(roundSel[5]), + .I3(R[14]), + .I4(roundSel[4]), + .I5(desIn[44]), + .O(\desOut[44]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[45]_INST_0 + (.I0(desIn[45]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[14]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[46] ), + .O(desOut[45])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[46]_INST_0 + (.I0(out[6]), + .I1(\desOut[46]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[38] ), + .I5(roundSel[3]), + .O(desOut[46])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[46]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[38] ), + .I2(roundSel[5]), + .I3(R[6]), + .I4(roundSel[4]), + .I5(desIn[46]), + .O(\desOut[46]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[47]_INST_0 + (.I0(desIn[47]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[6]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[38] ), + .O(desOut[47])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[48]_INST_0 + (.I0(out[31]), + .I1(\desOut[48]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[63] ), + .I5(roundSel[3]), + .O(desOut[48])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[48]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[63] ), + .I2(roundSel[5]), + .I3(R[31]), + .I4(roundSel[4]), + .I5(desIn[48]), + .O(\desOut[48]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[49]_INST_0 + (.I0(desIn[49]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[31]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[63] ), + .O(desOut[49])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[4]_INST_0 + (.I0(out[9]), + .I1(\desOut[4]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[41] ), + .I5(roundSel[3]), + .O(desOut[4])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[4]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[41] ), + .I2(roundSel[5]), + .I3(R[9]), + .I4(roundSel[4]), + .I5(desIn[4]), + .O(\desOut[4]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[50]_INST_0 + (.I0(out[23]), + .I1(\desOut[50]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[55] ), + .I5(roundSel[3]), + .O(desOut[50])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[50]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[55] ), + .I2(roundSel[5]), + .I3(R[23]), + .I4(roundSel[4]), + .I5(desIn[50]), + .O(\desOut[50]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[51]_INST_0 + (.I0(desIn[51]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[23]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[55] ), + .O(desOut[51])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[52]_INST_0 + (.I0(out[15]), + .I1(\desOut[52]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[47] ), + .I5(roundSel[3]), + .O(desOut[52])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[52]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[47] ), + .I2(roundSel[5]), + .I3(R[15]), + .I4(roundSel[4]), + .I5(desIn[52]), + .O(\desOut[52]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[53]_INST_0 + (.I0(desIn[53]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[15]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[47] ), + .O(desOut[53])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[54]_INST_0 + (.I0(out[7]), + .I1(\desOut[54]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[39] ), + .I5(roundSel[3]), + .O(desOut[54])); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \desOut[54]_INST_0_i_1 + (.I0(\desOut[62]_INST_0_i_2_n_0 ), + .I1(\FP_R_reg_n_0_[39] ), + .I2(roundSel[5]), + .I3(R[7]), + .I4(roundSel[4]), + .I5(desIn[54]), + .O(\desOut[54]_INST_0_i_1_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB8888888B8)) + \desOut[55]_INST_0 + (.I0(desIn[55]), + .I1(\desOut[63]_INST_0_i_1_n_0 ), + .I2(R[7]), + .I3(\desOut[63]_INST_0_i_2_n_0 ), + .I4(\desOut[63]_INST_0_i_3_n_0 ), + .I5(\FP_R_reg_n_0_[39] ), + .O(desOut[55])); + LUT6 #( + .INIT(64'h5555AAAA5556AAA6)) + \desOut[56]_INST_0 + (.I0(out[32]), + .I1(\desOut[56]_INST_0_i_1_n_0 ), + .I2(roundSel[2]), + .I3(roundSel[1]), + .I4(\FP_R_reg_n_0_[64] ), + .I5(roundSel[3]), + .O(desOut[56])); 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+ LUT6 #( + .INIT(64'h5E8939E44B368771)) + g0_b1__0 + (.I0(\u0/X [5]), + .I1(\u0/X [4]), + .I2(\u0/X [3]), + .I3(\u0/X [2]), + .I4(\u0/X [6]), + .I5(\u0/X [1]), + .O(out[23])); + LUT6 #( + .INIT(64'h5E92E56269D25879)) + g0_b1__1 + (.I0(\u0/X [17]), + .I1(\u0/X [16]), + .I2(\u0/X [15]), + .I3(\u0/X [14]), + .I4(\u0/X [18]), + .I5(\u0/X [13]), + .O(out[30])); + LUT6 #( + .INIT(64'h1BC6C996691BB46C)) + g0_b1__2 + (.I0(\u0/X [35]), + .I1(\u0/X [34]), + .I2(\u0/X [33]), + .I3(\u0/X [32]), + .I4(\u0/X [36]), + .I5(\u0/X [31]), + .O(out[11])); + LUT6 #( + .INIT(64'h47B4E81E58B98679)) + g0_b1__3 + (.I0(\u0/X [11]), + .I1(\u0/X [10]), + .I2(\u0/X [9]), + .I3(\u0/X [8]), + .I4(\u0/X [12]), + .I5(\u0/X [7]), + .O(out[2])); + LUT6 #( + .INIT(64'hD12D36C3AC728D72)) + g0_b1__4 + (.I0(\u0/X [47]), + .I1(\u0/X [46]), + .I2(\u0/X [45]), + .I3(\u0/X [44]), + .I4(\u0/X [48]), + .I5(\u0/X [43]), + .O(out[15])); + LUT6 #( + .INIT(64'hE81B2D6366B492AD)) + g0_b1__5 + (.I0(\u0/X [23]), + .I1(\u0/X [22]), + .I2(\u0/X [21]), + .I3(\u0/X [20]), + .I4(\u0/X [24]), + .I5(\u0/X [19]), + .O(out[10])); + LUT6 #( + .INIT(64'h9369B15A9C274CF1)) + g0_b1__6 + (.I0(\u0/X [29]), + .I1(\u0/X [28]), + .I2(\u0/X [27]), + .I3(\u0/X [26]), + .I4(\u0/X [30]), + .I5(\u0/X [25]), + .O(out[25])); + LUT6 #( + .INIT(64'h9AA526DAAD195A99)) + g0_b2 + (.I0(\u0/X [41]), + .I1(\u0/X [40]), + .I2(\u0/X [39]), + .I3(\u0/X [38]), + .I4(\u0/X [42]), + .I5(\u0/X [37]), + .O(out[12])); + LUT6 #( + .INIT(64'hC9934B35265E9C27)) + g0_b2__0 + (.I0(\u0/X [5]), + .I1(\u0/X [4]), + .I2(\u0/X [3]), + .I3(\u0/X [2]), + .I4(\u0/X [6]), + .I5(\u0/X [1]), + .O(out[17])); + LUT6 #( + .INIT(64'hA794D8275C632ED8)) + g0_b2__1 + (.I0(\u0/X [17]), + .I1(\u0/X [16]), + .I2(\u0/X [15]), + .I3(\u0/X [14]), + .I4(\u0/X [18]), + .I5(\u0/X [13]), + .O(out[16])); + LUT6 #( + .INIT(64'h9A69A54E0DB67A49)) + g0_b2__2 + (.I0(\u0/X [35]), + .I1(\u0/X [34]), + .I2(\u0/X [33]), + .I3(\u0/X [32]), + .I4(\u0/X [36]), + .I5(\u0/X [31]), + .O(out[29])); + LUT6 #( + .INIT(64'h6E618D66919E5A99)) + g0_b2__3 + (.I0(\u0/X [11]), + .I1(\u0/X [10]), + .I2(\u0/X [9]), + .I3(\u0/X [8]), + .I4(\u0/X [12]), + .I5(\u0/X [7]), + .O(out[28])); + LUT6 #( + .INIT(64'h639C5A6527C6D839)) + g0_b2__4 + (.I0(\u0/X [47]), + .I1(\u0/X [46]), + .I2(\u0/X [45]), + .I3(\u0/X [44]), + .I4(\u0/X [48]), + .I5(\u0/X [43]), + .O(out[27])); + LUT6 #( + .INIT(64'hB64A99D24B39E827)) + g0_b2__5 + (.I0(\u0/X [23]), + .I1(\u0/X [22]), + .I2(\u0/X [21]), + .I3(\u0/X [20]), + .I4(\u0/X [24]), + .I5(\u0/X [19]), + .O(out[20])); + LUT6 #( + .INIT(64'h63AC9D6185795A96)) + g0_b2__6 + (.I0(\u0/X [29]), + .I1(\u0/X [28]), + .I2(\u0/X [27]), + .I3(\u0/X [26]), + .I4(\u0/X [30]), + .I5(\u0/X [25]), + .O(out[14])); + LUT6 #( + .INIT(64'h994E4B9C69A526DA)) + g0_b3 + (.I0(\u0/X [41]), + .I1(\u0/X [40]), + .I2(\u0/X [39]), + .I3(\u0/X [38]), + .I4(\u0/X [42]), + .I5(\u0/X [37]), + .O(out[32])); + LUT6 #( + .INIT(64'h9A27279C9D522AE5)) + g0_b3__0 + (.I0(\u0/X [5]), + .I1(\u0/X [4]), + .I2(\u0/X [3]), + .I3(\u0/X [2]), + .I4(\u0/X [6]), + .I5(\u0/X [1]), + .O(out[9])); + LUT6 #( + .INIT(64'h966669397A89964D)) + g0_b3__1 + (.I0(\u0/X [17]), + .I1(\u0/X [16]), + .I2(\u0/X [15]), + .I3(\u0/X [14]), + .I4(\u0/X [18]), + .I5(\u0/X [13]), + .O(out[24])); + LUT6 #( + .INIT(64'hC3D86867AC63929D)) + g0_b3__2 + (.I0(\u0/X [35]), + .I1(\u0/X [34]), + .I2(\u0/X [33]), + .I3(\u0/X [32]), + .I4(\u0/X [36]), + .I5(\u0/X [31]), + .O(out[4])); + LUT6 #( + .INIT(64'hC927965A69D2992D)) + g0_b3__3 + (.I0(\u0/X [11]), + .I1(\u0/X [10]), + .I2(\u0/X [9]), + .I3(\u0/X [8]), + .I4(\u0/X [12]), + .I5(\u0/X [7]), + .O(out[13])); + LUT6 #( + .INIT(64'h87E49C72691E4B65)) + g0_b3__4 + (.I0(\u0/X [47]), + .I1(\u0/X [46]), + .I2(\u0/X [45]), + .I3(\u0/X [44]), + .I4(\u0/X [48]), + .I5(\u0/X [43]), + .O(out[5])); + LUT6 #( + .INIT(64'h99D249B5E827B4C6)) + g0_b3__5 + (.I0(\u0/X [23]), + .I1(\u0/X [22]), + .I2(\u0/X [21]), + .I3(\u0/X [20]), + .I4(\u0/X [24]), + .I5(\u0/X [19]), + .O(out[26])); + LUT6 #( + .INIT(64'h1AA787B86C4BD962)) + g0_b3__6 + (.I0(\u0/X [29]), + .I1(\u0/X [28]), + .I2(\u0/X [27]), + .I3(\u0/X [26]), + .I4(\u0/X [30]), + .I5(\u0/X [25]), + .O(out[8])); +endmodule diff --git a/designs/encrypted_ip/des3_area/design.yaml b/designs/encrypted_ip/des3_area/design.yaml new file mode 100644 index 000000000..6dd25811b --- /dev/null +++ b/designs/encrypted_ip/des3_area/design.yaml @@ -0,0 +1,16 @@ +top: top + +encrypted_ip: + ip: + - definition: "mc_top" + instances: + - "mem_ctrl_0" + - definition: "ac97_top" + instances: + - "ac97_0" + - "ac97_1" + - definition: "des3_area" + instances: + - "des3_area_0" + + user_files: ["top.v"] \ No newline at end of file diff --git a/designs/encrypted_ip/des3_area/key_sel3.v b/designs/encrypted_ip/des3_area/key_sel3.v new file mode 100644 index 000000000..9f232c41d --- /dev/null +++ b/designs/encrypted_ip/des3_area/key_sel3.v @@ -0,0 +1,865 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// KEY_SEL //// +//// Select one of 16 sub-keys for round //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module key_sel3(K_sub, key1, key2, key3, roundSel, decrypt); +output [1:48] K_sub; +input [55:0] key1, key2, key3; +input [5:0] roundSel; +input decrypt; + +wire decrypt_int; +reg [55:0] K; +reg [1:48] K_sub; +wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9; +wire [1:48] K10, K11, K12, K13, K14, K15, K16; + +always @(roundSel or decrypt or key1 or key2 or key3) + case ({decrypt, roundSel[5:4]}) // synopsys full_case parallel_case + 3'b0_00: K = key1; + 3'b0_01: K = key2; + 3'b0_10: K = key3; + 3'b1_00: K = key3; + 3'b1_01: K = key2; + 3'b1_10: K = key1; + endcase + +assign decrypt_int = (roundSel[5:4]==2'h1) ? !decrypt : decrypt; + +always @(K1 or K2 or K3 or K4 or K5 or K6 or K7 or K8 or K9 or K10 + or K11 or K12 or K13 or K14 or K15 or K16 or roundSel) + case(roundSel[3:0]) // synopsys full_case parallel_case + 0: K_sub = K1; + 1: K_sub = K2; + 2: K_sub = K3; + 3: K_sub = K4; + 4: K_sub = K5; + 5: K_sub = K6; + 6: K_sub = K7; + 7: K_sub = K8; + 8: K_sub = K9; + 9: K_sub = K10; + 10: K_sub = K11; + 11: K_sub = K12; + 12: K_sub = K13; + 13: K_sub = K14; + 14: K_sub = K15; + 15: K_sub = K16; + endcase + + +assign K16[1] = decrypt_int ? K[47] : K[40]; +assign K16[2] = decrypt_int ? K[11] : K[4]; +assign K16[3] = decrypt_int ? K[26] : K[19]; +assign K16[4] = decrypt_int ? K[3] : K[53]; +assign K16[5] = decrypt_int ? K[13] : K[6]; +assign K16[6] = decrypt_int ? K[41] : K[34]; +assign K16[7] = decrypt_int ? K[27] : K[20]; +assign K16[8] = decrypt_int ? K[6] : K[24]; +assign K16[9] = decrypt_int ? K[54] : K[47]; +assign K16[10] = decrypt_int ? K[48] : K[41]; +assign K16[11] = decrypt_int ? K[39] : K[32]; +assign K16[12] = decrypt_int ? K[19] : K[12]; +assign K16[13] = decrypt_int ? K[53] : K[46]; +assign K16[14] = decrypt_int ? K[25] : K[18]; +assign K16[15] = decrypt_int ? K[33] : K[26]; +assign K16[16] = decrypt_int ? K[34] : K[27]; +assign K16[17] = decrypt_int ? K[17] : K[10]; +assign K16[18] = decrypt_int ? K[5] : K[55]; +assign K16[19] = decrypt_int ? K[4] : K[54]; +assign K16[20] = decrypt_int ? K[55] : K[48]; +assign K16[21] = decrypt_int ? K[24] : K[17]; +assign K16[22] = decrypt_int ? K[32] : K[25]; +assign K16[23] = decrypt_int ? K[40] : K[33]; +assign K16[24] = decrypt_int ? K[20] : K[13]; +assign K16[25] = decrypt_int ? K[36] : K[29]; +assign K16[26] = decrypt_int ? K[31] : K[51]; +assign K16[27] = decrypt_int ? K[21] : K[14]; +assign K16[28] = decrypt_int ? K[8] : K[1]; +assign K16[29] = decrypt_int ? K[23] : K[16]; +assign K16[30] = decrypt_int ? K[52] : K[45]; +assign K16[31] = decrypt_int ? K[14] : K[7]; +assign K16[32] = decrypt_int ? K[29] : K[22]; +assign K16[33] = decrypt_int ? K[51] : K[44]; +assign K16[34] = decrypt_int ? K[9] : K[2]; +assign K16[35] = decrypt_int ? K[35] : K[28]; +assign K16[36] = decrypt_int ? K[30] : K[23]; +assign K16[37] = decrypt_int ? K[2] : K[50]; +assign K16[38] = decrypt_int ? K[37] : K[30]; +assign K16[39] = decrypt_int ? K[22] : K[15]; +assign K16[40] = decrypt_int ? K[0] : K[52]; +assign K16[41] = decrypt_int ? K[42] : K[35]; +assign K16[42] = decrypt_int ? K[38] : K[31]; +assign K16[43] = decrypt_int ? K[16] : K[9]; +assign K16[44] = decrypt_int ? K[43] : K[36]; +assign K16[45] = decrypt_int ? K[44] : K[37]; +assign K16[46] = decrypt_int ? K[1] : K[49]; +assign K16[47] = decrypt_int ? K[7] : K[0]; +assign K16[48] = decrypt_int ? K[28] : K[21]; + +assign K15[1] = decrypt_int ? K[54] : K[33]; +assign K15[2] = decrypt_int ? K[18] : K[54]; +assign K15[3] = decrypt_int ? K[33] : K[12]; +assign K15[4] = decrypt_int ? K[10] : K[46]; +assign K15[5] = decrypt_int ? K[20] : K[24]; +assign K15[6] = decrypt_int ? K[48] : K[27]; +assign K15[7] = decrypt_int ? K[34] : K[13]; +assign K15[8] = decrypt_int ? K[13] : K[17]; +assign K15[9] = decrypt_int ? K[4] : K[40]; +assign K15[10] = decrypt_int ? K[55] : K[34]; +assign K15[11] = decrypt_int ? K[46] : K[25]; +assign K15[12] = decrypt_int ? K[26] : K[5]; +assign K15[13] = decrypt_int ? K[3] : K[39]; +assign K15[14] = decrypt_int ? K[32] : K[11]; +assign K15[15] = decrypt_int ? K[40] : K[19]; +assign K15[16] = decrypt_int ? K[41] : K[20]; +assign K15[17] = decrypt_int ? K[24] : K[3]; +assign K15[18] = decrypt_int ? K[12] : K[48]; +assign K15[19] = decrypt_int ? K[11] : K[47]; +assign K15[20] = decrypt_int ? K[5] : K[41]; +assign K15[21] = decrypt_int ? K[6] : K[10]; +assign K15[22] = decrypt_int ? K[39] : K[18]; +assign K15[23] = decrypt_int ? K[47] : K[26]; +assign K15[24] = decrypt_int ? K[27] : K[6]; +assign K15[25] = decrypt_int ? K[43] : K[22]; +assign K15[26] = decrypt_int ? K[38] : K[44]; +assign K15[27] = decrypt_int ? K[28] : K[7]; +assign K15[28] = decrypt_int ? K[15] : K[49]; +assign K15[29] = decrypt_int ? K[30] : K[9]; +assign K15[30] = decrypt_int ? K[0] : K[38]; +assign K15[31] = decrypt_int ? K[21] : K[0]; +assign K15[32] = decrypt_int ? K[36] : K[15]; +assign K15[33] = decrypt_int ? K[31] : K[37]; +assign K15[34] = decrypt_int ? K[16] : K[50]; +assign K15[35] = decrypt_int ? K[42] : K[21]; +assign K15[36] = decrypt_int ? K[37] : K[16]; +assign K15[37] = decrypt_int ? K[9] : K[43]; +assign K15[38] = decrypt_int ? K[44] : K[23]; +assign K15[39] = decrypt_int ? K[29] : K[8]; +assign K15[40] = decrypt_int ? K[7] : K[45]; +assign K15[41] = decrypt_int ? K[49] : K[28]; +assign K15[42] = decrypt_int ? K[45] : K[51]; +assign K15[43] = decrypt_int ? K[23] : K[2]; +assign K15[44] = decrypt_int ? K[50] : K[29]; +assign K15[45] = decrypt_int ? K[51] : K[30]; +assign K15[46] = decrypt_int ? K[8] : K[42]; +assign K15[47] = decrypt_int ? K[14] : K[52]; +assign K15[48] = decrypt_int ? K[35] : K[14]; + +assign K14[1] = decrypt_int ? K[11] : K[19]; +assign K14[2] = decrypt_int ? K[32] : K[40]; +assign K14[3] = decrypt_int ? K[47] : K[55]; +assign K14[4] = decrypt_int ? K[24] : K[32]; +assign K14[5] = decrypt_int ? K[34] : K[10]; +assign K14[6] = decrypt_int ? K[5] : K[13]; +assign K14[7] = decrypt_int ? K[48] : K[24]; +assign K14[8] = decrypt_int ? K[27] : K[3]; +assign K14[9] = decrypt_int ? K[18] : K[26]; +assign K14[10] = decrypt_int ? K[12] : K[20]; +assign K14[11] = decrypt_int ? K[3] : K[11]; +assign K14[12] = decrypt_int ? K[40] : K[48]; +assign K14[13] = decrypt_int ? K[17] : K[25]; +assign K14[14] = decrypt_int ? K[46] : K[54]; +assign K14[15] = decrypt_int ? K[54] : K[5]; +assign K14[16] = decrypt_int ? K[55] : K[6]; +assign K14[17] = decrypt_int ? K[13] : K[46]; +assign K14[18] = decrypt_int ? K[26] : K[34]; +assign K14[19] = decrypt_int ? K[25] : K[33]; +assign K14[20] = decrypt_int ? K[19] : K[27]; +assign K14[21] = decrypt_int ? K[20] : K[53]; +assign K14[22] = decrypt_int ? K[53] : K[4]; +assign K14[23] = decrypt_int ? K[4] : K[12]; +assign K14[24] = decrypt_int ? K[41] : K[17]; +assign K14[25] = decrypt_int ? K[2] : K[8]; +assign K14[26] = decrypt_int ? K[52] : K[30]; +assign K14[27] = decrypt_int ? K[42] : K[52]; +assign K14[28] = decrypt_int ? K[29] : K[35]; +assign K14[29] = decrypt_int ? K[44] : K[50]; +assign K14[30] = decrypt_int ? K[14] : K[51]; +assign K14[31] = decrypt_int ? K[35] : K[45]; +assign K14[32] = decrypt_int ? K[50] : K[1]; +assign K14[33] = decrypt_int ? K[45] : K[23]; +assign K14[34] = decrypt_int ? K[30] : K[36]; +assign K14[35] = decrypt_int ? K[1] : K[7]; +assign K14[36] = decrypt_int ? K[51] : K[2]; +assign K14[37] = decrypt_int ? K[23] : K[29]; +assign K14[38] = decrypt_int ? K[31] : K[9]; +assign K14[39] = decrypt_int ? K[43] : K[49]; +assign K14[40] = decrypt_int ? K[21] : K[31]; +assign K14[41] = decrypt_int ? K[8] : K[14]; +assign K14[42] = decrypt_int ? K[0] : K[37]; +assign K14[43] = decrypt_int ? K[37] : K[43]; +assign K14[44] = decrypt_int ? K[9] : K[15]; +assign K14[45] = decrypt_int ? K[38] : K[16]; +assign K14[46] = decrypt_int ? K[22] : K[28]; +assign K14[47] = decrypt_int ? K[28] : K[38]; +assign K14[48] = decrypt_int ? K[49] : K[0]; + +assign K13[1] = decrypt_int ? K[25] : K[5]; +assign K13[2] = decrypt_int ? K[46] : K[26]; +assign K13[3] = decrypt_int ? K[4] : K[41]; +assign K13[4] = decrypt_int ? K[13] : K[18]; +assign K13[5] = decrypt_int ? K[48] : K[53]; +assign K13[6] = decrypt_int ? K[19] : K[24]; +assign K13[7] = decrypt_int ? K[5] : K[10]; +assign K13[8] = decrypt_int ? K[41] : K[46]; +assign K13[9] = decrypt_int ? K[32] : K[12]; +assign K13[10] = decrypt_int ? K[26] : K[6]; +assign K13[11] = decrypt_int ? K[17] : K[54]; +assign K13[12] = decrypt_int ? K[54] : K[34]; +assign K13[13] = decrypt_int ? K[6] : K[11]; +assign K13[14] = decrypt_int ? K[3] : K[40]; +assign K13[15] = decrypt_int ? K[11] : K[48]; +assign K13[16] = decrypt_int ? K[12] : K[17]; +assign K13[17] = decrypt_int ? K[27] : K[32]; +assign K13[18] = decrypt_int ? K[40] : K[20]; +assign K13[19] = decrypt_int ? K[39] : K[19]; +assign K13[20] = decrypt_int ? K[33] : K[13]; +assign K13[21] = decrypt_int ? K[34] : K[39]; +assign K13[22] = decrypt_int ? K[10] : K[47]; +assign K13[23] = decrypt_int ? K[18] : K[55]; +assign K13[24] = decrypt_int ? K[55] : K[3]; +assign K13[25] = decrypt_int ? K[16] : K[49]; +assign K13[26] = decrypt_int ? K[7] : K[16]; +assign K13[27] = decrypt_int ? K[1] : K[38]; +assign K13[28] = decrypt_int ? K[43] : K[21]; +assign K13[29] = decrypt_int ? K[31] : K[36]; +assign K13[30] = decrypt_int ? K[28] : K[37]; +assign K13[31] = decrypt_int ? K[49] : K[31]; +assign K13[32] = decrypt_int ? K[9] : K[42]; +assign K13[33] = decrypt_int ? K[0] : K[9]; +assign K13[34] = decrypt_int ? K[44] : K[22]; +assign K13[35] = decrypt_int ? K[15] : K[52]; +assign K13[36] = decrypt_int ? K[38] : K[43]; +assign K13[37] = decrypt_int ? K[37] : K[15]; +assign K13[38] = decrypt_int ? K[45] : K[50]; +assign K13[39] = decrypt_int ? K[2] : K[35]; +assign K13[40] = decrypt_int ? K[35] : K[44]; +assign K13[41] = decrypt_int ? K[22] : K[0]; +assign K13[42] = decrypt_int ? K[14] : K[23]; +assign K13[43] = decrypt_int ? K[51] : K[29]; +assign K13[44] = decrypt_int ? K[23] : K[1]; +assign K13[45] = decrypt_int ? K[52] : K[2]; +assign K13[46] = decrypt_int ? K[36] : K[14]; +assign K13[47] = decrypt_int ? K[42] : K[51]; +assign K13[48] = decrypt_int ? K[8] : K[45]; + +assign K12[1] = decrypt_int ? K[39] : K[48]; +assign K12[2] = decrypt_int ? K[3] : K[12]; +assign K12[3] = decrypt_int ? K[18] : K[27]; +assign K12[4] = decrypt_int ? K[27] : K[4]; +assign K12[5] = decrypt_int ? K[5] : K[39]; +assign K12[6] = decrypt_int ? K[33] : K[10]; +assign K12[7] = decrypt_int ? K[19] : K[53]; +assign K12[8] = decrypt_int ? K[55] : K[32]; +assign K12[9] = decrypt_int ? K[46] : K[55]; +assign K12[10] = decrypt_int ? K[40] : K[17]; +assign K12[11] = decrypt_int ? K[6] : K[40]; +assign K12[12] = decrypt_int ? K[11] : K[20]; +assign K12[13] = decrypt_int ? K[20] : K[54]; +assign K12[14] = decrypt_int ? K[17] : K[26]; +assign K12[15] = decrypt_int ? K[25] : K[34]; +assign K12[16] = decrypt_int ? K[26] : K[3]; +assign K12[17] = decrypt_int ? K[41] : K[18]; +assign K12[18] = decrypt_int ? K[54] : K[6]; +assign K12[19] = decrypt_int ? K[53] : K[5]; +assign K12[20] = decrypt_int ? K[47] : K[24]; +assign K12[21] = decrypt_int ? K[48] : K[25]; +assign K12[22] = decrypt_int ? K[24] : K[33]; +assign K12[23] = decrypt_int ? K[32] : K[41]; +assign K12[24] = decrypt_int ? K[12] : K[46]; +assign K12[25] = decrypt_int ? K[30] : K[35]; +assign K12[26] = decrypt_int ? K[21] : K[2]; +assign K12[27] = decrypt_int ? K[15] : K[51]; +assign K12[28] = decrypt_int ? K[2] : K[7]; +assign K12[29] = decrypt_int ? K[45] : K[22]; +assign K12[30] = decrypt_int ? K[42] : K[23]; +assign K12[31] = decrypt_int ? K[8] : K[44]; +assign K12[32] = decrypt_int ? K[23] : K[28]; +assign K12[33] = decrypt_int ? K[14] : K[50]; +assign K12[34] = decrypt_int ? K[31] : K[8]; +assign K12[35] = decrypt_int ? K[29] : K[38]; +assign K12[36] = decrypt_int ? K[52] : K[29]; +assign K12[37] = decrypt_int ? K[51] : K[1]; +assign K12[38] = decrypt_int ? K[0] : K[36]; +assign K12[39] = decrypt_int ? K[16] : K[21]; +assign K12[40] = decrypt_int ? K[49] : K[30]; +assign K12[41] = decrypt_int ? K[36] : K[45]; +assign K12[42] = decrypt_int ? K[28] : K[9]; +assign K12[43] = decrypt_int ? K[38] : K[15]; +assign K12[44] = decrypt_int ? K[37] : K[42]; +assign K12[45] = decrypt_int ? K[7] : K[43]; +assign K12[46] = decrypt_int ? K[50] : K[0]; +assign K12[47] = decrypt_int ? K[1] : K[37]; +assign K12[48] = decrypt_int ? K[22] : K[31]; + +assign K11[1] = decrypt_int ? K[53] : K[34]; +assign K11[2] = decrypt_int ? K[17] : K[55]; +assign K11[3] = decrypt_int ? K[32] : K[13]; +assign K11[4] = decrypt_int ? K[41] : K[47]; +assign K11[5] = decrypt_int ? K[19] : K[25]; +assign K11[6] = decrypt_int ? K[47] : K[53]; +assign K11[7] = decrypt_int ? K[33] : K[39]; +assign K11[8] = decrypt_int ? K[12] : K[18]; +assign K11[9] = decrypt_int ? K[3] : K[41]; +assign K11[10] = decrypt_int ? K[54] : K[3]; +assign K11[11] = decrypt_int ? K[20] : K[26]; +assign K11[12] = decrypt_int ? K[25] : K[6]; +assign K11[13] = decrypt_int ? K[34] : K[40]; +assign K11[14] = decrypt_int ? K[6] : K[12]; +assign K11[15] = decrypt_int ? K[39] : K[20]; +assign K11[16] = decrypt_int ? K[40] : K[46]; +assign K11[17] = decrypt_int ? K[55] : K[4]; +assign K11[18] = decrypt_int ? K[11] : K[17]; +assign K11[19] = decrypt_int ? K[10] : K[48]; +assign K11[20] = decrypt_int ? K[4] : K[10]; +assign K11[21] = decrypt_int ? K[5] : K[11]; +assign K11[22] = decrypt_int ? K[13] : K[19]; +assign K11[23] = decrypt_int ? K[46] : K[27]; +assign K11[24] = decrypt_int ? K[26] : K[32]; +assign K11[25] = decrypt_int ? K[44] : K[21]; +assign K11[26] = decrypt_int ? K[35] : K[43]; +assign K11[27] = decrypt_int ? K[29] : K[37]; +assign K11[28] = decrypt_int ? K[16] : K[52]; +assign K11[29] = decrypt_int ? K[0] : K[8]; +assign K11[30] = decrypt_int ? K[1] : K[9]; +assign K11[31] = decrypt_int ? K[22] : K[30]; +assign K11[32] = decrypt_int ? K[37] : K[14]; +assign K11[33] = decrypt_int ? K[28] : K[36]; +assign K11[34] = decrypt_int ? K[45] : K[49]; +assign K11[35] = decrypt_int ? K[43] : K[51]; +assign K11[36] = decrypt_int ? K[7] : K[15]; +assign K11[37] = decrypt_int ? K[38] : K[42]; +assign K11[38] = decrypt_int ? K[14] : K[22]; +assign K11[39] = decrypt_int ? K[30] : K[7]; +assign K11[40] = decrypt_int ? K[8] : K[16]; +assign K11[41] = decrypt_int ? K[50] : K[31]; +assign K11[42] = decrypt_int ? K[42] : K[50]; +assign K11[43] = decrypt_int ? K[52] : K[1]; +assign K11[44] = decrypt_int ? K[51] : K[28]; +assign K11[45] = decrypt_int ? K[21] : K[29]; +assign K11[46] = decrypt_int ? K[9] : K[45]; +assign K11[47] = decrypt_int ? K[15] : K[23]; +assign K11[48] = decrypt_int ? K[36] : K[44]; + +assign K10[1] = decrypt_int ? K[10] : K[20]; +assign K10[2] = decrypt_int ? K[6] : K[41]; +assign K10[3] = decrypt_int ? K[46] : K[24]; +assign K10[4] = decrypt_int ? K[55] : K[33]; +assign K10[5] = decrypt_int ? K[33] : K[11]; +assign K10[6] = decrypt_int ? K[4] : K[39]; +assign K10[7] = decrypt_int ? K[47] : K[25]; +assign K10[8] = decrypt_int ? K[26] : K[4]; +assign K10[9] = decrypt_int ? K[17] : K[27]; +assign K10[10] = decrypt_int ? K[11] : K[46]; +assign K10[11] = decrypt_int ? K[34] : K[12]; +assign K10[12] = decrypt_int ? K[39] : K[17]; +assign K10[13] = decrypt_int ? K[48] : K[26]; +assign K10[14] = decrypt_int ? K[20] : K[55]; +assign K10[15] = decrypt_int ? K[53] : K[6]; +assign K10[16] = decrypt_int ? K[54] : K[32]; +assign K10[17] = decrypt_int ? K[12] : K[47]; +assign K10[18] = decrypt_int ? K[25] : K[3]; +assign K10[19] = decrypt_int ? K[24] : K[34]; +assign K10[20] = decrypt_int ? K[18] : K[53]; +assign K10[21] = decrypt_int ? K[19] : K[54]; +assign K10[22] = decrypt_int ? K[27] : K[5]; +assign K10[23] = decrypt_int ? K[3] : K[13]; +assign K10[24] = decrypt_int ? K[40] : K[18]; +assign K10[25] = decrypt_int ? K[31] : K[7]; +assign K10[26] = decrypt_int ? K[49] : K[29]; +assign K10[27] = decrypt_int ? K[43] : K[23]; +assign K10[28] = decrypt_int ? K[30] : K[38]; +assign K10[29] = decrypt_int ? K[14] : K[49]; +assign K10[30] = decrypt_int ? K[15] : K[50]; +assign K10[31] = decrypt_int ? K[36] : K[16]; +assign K10[32] = decrypt_int ? K[51] : K[0]; +assign K10[33] = decrypt_int ? K[42] : K[22]; +assign K10[34] = decrypt_int ? K[0] : K[35]; +assign K10[35] = decrypt_int ? K[2] : K[37]; +assign K10[36] = decrypt_int ? K[21] : K[1]; +assign K10[37] = decrypt_int ? K[52] : K[28]; +assign K10[38] = decrypt_int ? K[28] : K[8]; +assign K10[39] = decrypt_int ? K[44] : K[52]; +assign K10[40] = decrypt_int ? K[22] : K[2]; +assign K10[41] = decrypt_int ? K[9] : K[44]; +assign K10[42] = decrypt_int ? K[1] : K[36]; +assign K10[43] = decrypt_int ? K[7] : K[42]; +assign K10[44] = decrypt_int ? K[38] : K[14]; +assign K10[45] = decrypt_int ? K[35] : K[15]; +assign K10[46] = decrypt_int ? K[23] : K[31]; +assign K10[47] = decrypt_int ? K[29] : K[9]; +assign K10[48] = decrypt_int ? K[50] : K[30]; + +assign K9[1] = decrypt_int ? K[24] : K[6]; +assign K9[2] = decrypt_int ? K[20] : K[27]; +assign K9[3] = decrypt_int ? K[3] : K[10]; +assign K9[4] = decrypt_int ? K[12] : K[19]; +assign K9[5] = decrypt_int ? K[47] : K[54]; +assign K9[6] = decrypt_int ? K[18] : K[25]; +assign K9[7] = decrypt_int ? K[4] : K[11]; +assign K9[8] = decrypt_int ? K[40] : K[47]; +assign K9[9] = decrypt_int ? K[6] : K[13]; +assign K9[10] = decrypt_int ? K[25] : K[32]; +assign K9[11] = decrypt_int ? K[48] : K[55]; +assign K9[12] = decrypt_int ? K[53] : K[3]; +assign K9[13] = decrypt_int ? K[5] : K[12]; +assign K9[14] = decrypt_int ? K[34] : K[41]; +assign K9[15] = decrypt_int ? K[10] : K[17]; +assign K9[16] = decrypt_int ? K[11] : K[18]; +assign K9[17] = decrypt_int ? K[26] : K[33]; +assign K9[18] = decrypt_int ? K[39] : K[46]; +assign K9[19] = decrypt_int ? K[13] : K[20]; +assign K9[20] = decrypt_int ? K[32] : K[39]; +assign K9[21] = decrypt_int ? K[33] : K[40]; +assign K9[22] = decrypt_int ? K[41] : K[48]; +assign K9[23] = decrypt_int ? K[17] : K[24]; +assign K9[24] = decrypt_int ? K[54] : K[4]; +assign K9[25] = decrypt_int ? K[45] : K[52]; +assign K9[26] = decrypt_int ? K[8] : K[15]; +assign K9[27] = decrypt_int ? K[2] : K[9]; +assign K9[28] = decrypt_int ? K[44] : K[51]; +assign K9[29] = decrypt_int ? K[28] : K[35]; +assign K9[30] = decrypt_int ? K[29] : K[36]; +assign K9[31] = decrypt_int ? K[50] : K[2]; +assign K9[32] = decrypt_int ? K[38] : K[45]; +assign K9[33] = decrypt_int ? K[1] : K[8]; +assign K9[34] = decrypt_int ? K[14] : K[21]; +assign K9[35] = decrypt_int ? K[16] : K[23]; +assign K9[36] = decrypt_int ? K[35] : K[42]; +assign K9[37] = decrypt_int ? K[7] : K[14]; +assign K9[38] = decrypt_int ? K[42] : K[49]; +assign K9[39] = decrypt_int ? K[31] : K[38]; +assign K9[40] = decrypt_int ? K[36] : K[43]; +assign K9[41] = decrypt_int ? K[23] : K[30]; +assign K9[42] = decrypt_int ? K[15] : K[22]; +assign K9[43] = decrypt_int ? K[21] : K[28]; +assign K9[44] = decrypt_int ? K[52] : K[0]; +assign K9[45] = decrypt_int ? K[49] : K[1]; +assign K9[46] = decrypt_int ? K[37] : K[44]; +assign K9[47] = decrypt_int ? K[43] : K[50]; +assign K9[48] = decrypt_int ? K[9] : K[16]; + +assign K8[1] = decrypt_int ? K[6] : K[24]; +assign K8[2] = decrypt_int ? K[27] : K[20]; +assign K8[3] = decrypt_int ? K[10] : K[3]; +assign K8[4] = decrypt_int ? K[19] : K[12]; +assign K8[5] = decrypt_int ? K[54] : K[47]; +assign K8[6] = decrypt_int ? K[25] : K[18]; +assign K8[7] = decrypt_int ? K[11] : K[4]; +assign K8[8] = decrypt_int ? K[47] : K[40]; +assign K8[9] = decrypt_int ? K[13] : K[6]; +assign K8[10] = decrypt_int ? K[32] : K[25]; +assign K8[11] = decrypt_int ? K[55] : K[48]; +assign K8[12] = decrypt_int ? K[3] : K[53]; +assign K8[13] = decrypt_int ? K[12] : K[5]; +assign K8[14] = decrypt_int ? K[41] : K[34]; +assign K8[15] = decrypt_int ? K[17] : K[10]; +assign K8[16] = decrypt_int ? K[18] : K[11]; +assign K8[17] = decrypt_int ? K[33] : K[26]; +assign K8[18] = decrypt_int ? K[46] : K[39]; +assign K8[19] = decrypt_int ? K[20] : K[13]; +assign K8[20] = decrypt_int ? K[39] : K[32]; +assign K8[21] = decrypt_int ? K[40] : K[33]; +assign K8[22] = decrypt_int ? K[48] : K[41]; +assign K8[23] = decrypt_int ? K[24] : K[17]; +assign K8[24] = decrypt_int ? K[4] : K[54]; +assign K8[25] = decrypt_int ? K[52] : K[45]; +assign K8[26] = decrypt_int ? K[15] : K[8]; +assign K8[27] = decrypt_int ? K[9] : K[2]; +assign K8[28] = decrypt_int ? K[51] : K[44]; +assign K8[29] = decrypt_int ? K[35] : K[28]; +assign K8[30] = decrypt_int ? K[36] : K[29]; +assign K8[31] = decrypt_int ? K[2] : K[50]; +assign K8[32] = decrypt_int ? K[45] : K[38]; +assign K8[33] = decrypt_int ? K[8] : K[1]; +assign K8[34] = decrypt_int ? K[21] : K[14]; +assign K8[35] = decrypt_int ? K[23] : K[16]; +assign K8[36] = decrypt_int ? K[42] : K[35]; +assign K8[37] = decrypt_int ? K[14] : K[7]; +assign K8[38] = decrypt_int ? K[49] : K[42]; +assign K8[39] = decrypt_int ? K[38] : K[31]; +assign K8[40] = decrypt_int ? K[43] : K[36]; +assign K8[41] = decrypt_int ? K[30] : K[23]; +assign K8[42] = decrypt_int ? K[22] : K[15]; +assign K8[43] = decrypt_int ? K[28] : K[21]; +assign K8[44] = decrypt_int ? K[0] : K[52]; +assign K8[45] = decrypt_int ? K[1] : K[49]; +assign K8[46] = decrypt_int ? K[44] : K[37]; +assign K8[47] = decrypt_int ? K[50] : K[43]; +assign K8[48] = decrypt_int ? K[16] : K[9]; + +assign K7[1] = decrypt_int ? K[20] : K[10]; +assign K7[2] = decrypt_int ? K[41] : K[6]; +assign K7[3] = decrypt_int ? K[24] : K[46]; +assign K7[4] = decrypt_int ? K[33] : K[55]; +assign K7[5] = decrypt_int ? K[11] : K[33]; +assign K7[6] = decrypt_int ? K[39] : K[4]; +assign K7[7] = decrypt_int ? K[25] : K[47]; +assign K7[8] = decrypt_int ? K[4] : K[26]; +assign K7[9] = decrypt_int ? K[27] : K[17]; +assign K7[10] = decrypt_int ? K[46] : K[11]; +assign K7[11] = decrypt_int ? K[12] : K[34]; +assign K7[12] = decrypt_int ? K[17] : K[39]; +assign K7[13] = decrypt_int ? K[26] : K[48]; +assign K7[14] = decrypt_int ? K[55] : K[20]; +assign K7[15] = decrypt_int ? K[6] : K[53]; +assign K7[16] = decrypt_int ? K[32] : K[54]; +assign K7[17] = decrypt_int ? K[47] : K[12]; +assign K7[18] = decrypt_int ? K[3] : K[25]; +assign K7[19] = decrypt_int ? K[34] : K[24]; +assign K7[20] = decrypt_int ? K[53] : K[18]; +assign K7[21] = decrypt_int ? K[54] : K[19]; +assign K7[22] = decrypt_int ? K[5] : K[27]; +assign K7[23] = decrypt_int ? K[13] : K[3]; +assign K7[24] = decrypt_int ? K[18] : K[40]; +assign K7[25] = decrypt_int ? K[7] : K[31]; +assign K7[26] = decrypt_int ? K[29] : K[49]; +assign K7[27] = decrypt_int ? K[23] : K[43]; +assign K7[28] = decrypt_int ? K[38] : K[30]; +assign K7[29] = decrypt_int ? K[49] : K[14]; +assign K7[30] = decrypt_int ? K[50] : K[15]; +assign K7[31] = decrypt_int ? K[16] : K[36]; +assign K7[32] = decrypt_int ? K[0] : K[51]; +assign K7[33] = decrypt_int ? K[22] : K[42]; +assign K7[34] = decrypt_int ? K[35] : K[0]; +assign K7[35] = decrypt_int ? K[37] : K[2]; +assign K7[36] = decrypt_int ? K[1] : K[21]; +assign K7[37] = decrypt_int ? K[28] : K[52]; +assign K7[38] = decrypt_int ? K[8] : K[28]; +assign K7[39] = decrypt_int ? K[52] : K[44]; +assign K7[40] = decrypt_int ? K[2] : K[22]; +assign K7[41] = decrypt_int ? K[44] : K[9]; +assign K7[42] = decrypt_int ? K[36] : K[1]; +assign K7[43] = decrypt_int ? K[42] : K[7]; +assign K7[44] = decrypt_int ? K[14] : K[38]; +assign K7[45] = decrypt_int ? K[15] : K[35]; +assign K7[46] = decrypt_int ? K[31] : K[23]; +assign K7[47] = decrypt_int ? K[9] : K[29]; +assign K7[48] = decrypt_int ? K[30] : K[50]; + +assign K6[1] = decrypt_int ? K[34] : K[53]; +assign K6[2] = decrypt_int ? K[55] : K[17]; +assign K6[3] = decrypt_int ? K[13] : K[32]; +assign K6[4] = decrypt_int ? K[47] : K[41]; +assign K6[5] = decrypt_int ? K[25] : K[19]; +assign K6[6] = decrypt_int ? K[53] : K[47]; +assign K6[7] = decrypt_int ? K[39] : K[33]; +assign K6[8] = decrypt_int ? K[18] : K[12]; +assign K6[9] = decrypt_int ? K[41] : K[3]; +assign K6[10] = decrypt_int ? K[3] : K[54]; +assign K6[11] = decrypt_int ? K[26] : K[20]; +assign K6[12] = decrypt_int ? K[6] : K[25]; +assign K6[13] = decrypt_int ? K[40] : K[34]; +assign K6[14] = decrypt_int ? K[12] : K[6]; +assign K6[15] = decrypt_int ? K[20] : K[39]; +assign K6[16] = decrypt_int ? K[46] : K[40]; +assign K6[17] = decrypt_int ? K[4] : K[55]; +assign K6[18] = decrypt_int ? K[17] : K[11]; +assign K6[19] = decrypt_int ? K[48] : K[10]; +assign K6[20] = decrypt_int ? K[10] : K[4]; +assign K6[21] = decrypt_int ? K[11] : K[5]; +assign K6[22] = decrypt_int ? K[19] : K[13]; +assign K6[23] = decrypt_int ? K[27] : K[46]; +assign K6[24] = decrypt_int ? K[32] : K[26]; +assign K6[25] = decrypt_int ? K[21] : K[44]; +assign K6[26] = decrypt_int ? K[43] : K[35]; +assign K6[27] = decrypt_int ? K[37] : K[29]; +assign K6[28] = decrypt_int ? K[52] : K[16]; +assign K6[29] = decrypt_int ? K[8] : K[0]; +assign K6[30] = decrypt_int ? K[9] : K[1]; +assign K6[31] = decrypt_int ? K[30] : K[22]; +assign K6[32] = decrypt_int ? K[14] : K[37]; +assign K6[33] = decrypt_int ? K[36] : K[28]; +assign K6[34] = decrypt_int ? K[49] : K[45]; +assign K6[35] = decrypt_int ? K[51] : K[43]; +assign K6[36] = decrypt_int ? K[15] : K[7]; +assign K6[37] = decrypt_int ? K[42] : K[38]; +assign K6[38] = decrypt_int ? K[22] : K[14]; +assign K6[39] = decrypt_int ? K[7] : K[30]; +assign K6[40] = decrypt_int ? K[16] : K[8]; +assign K6[41] = decrypt_int ? K[31] : K[50]; +assign K6[42] = decrypt_int ? K[50] : K[42]; +assign K6[43] = decrypt_int ? K[1] : K[52]; +assign K6[44] = decrypt_int ? K[28] : K[51]; +assign K6[45] = decrypt_int ? K[29] : K[21]; +assign K6[46] = decrypt_int ? K[45] : K[9]; +assign K6[47] = decrypt_int ? K[23] : K[15]; +assign K6[48] = decrypt_int ? K[44] : K[36]; + +assign K5[1] = decrypt_int ? K[48] : K[39]; +assign K5[2] = decrypt_int ? K[12] : K[3]; +assign K5[3] = decrypt_int ? K[27] : K[18]; +assign K5[4] = decrypt_int ? K[4] : K[27]; +assign K5[5] = decrypt_int ? K[39] : K[5]; +assign K5[6] = decrypt_int ? K[10] : K[33]; +assign K5[7] = decrypt_int ? K[53] : K[19]; +assign K5[8] = decrypt_int ? K[32] : K[55]; +assign K5[9] = decrypt_int ? K[55] : K[46]; +assign K5[10] = decrypt_int ? K[17] : K[40]; +assign K5[11] = decrypt_int ? K[40] : K[6]; +assign K5[12] = decrypt_int ? K[20] : K[11]; +assign K5[13] = decrypt_int ? K[54] : K[20]; +assign K5[14] = decrypt_int ? K[26] : K[17]; +assign K5[15] = decrypt_int ? K[34] : K[25]; +assign K5[16] = decrypt_int ? K[3] : K[26]; +assign K5[17] = decrypt_int ? K[18] : K[41]; +assign K5[18] = decrypt_int ? K[6] : K[54]; +assign K5[19] = decrypt_int ? K[5] : K[53]; +assign K5[20] = decrypt_int ? K[24] : K[47]; +assign K5[21] = decrypt_int ? K[25] : K[48]; +assign K5[22] = decrypt_int ? K[33] : K[24]; +assign K5[23] = decrypt_int ? K[41] : K[32]; +assign K5[24] = decrypt_int ? K[46] : K[12]; +assign K5[25] = decrypt_int ? K[35] : K[30]; +assign K5[26] = decrypt_int ? K[2] : K[21]; +assign K5[27] = decrypt_int ? K[51] : K[15]; +assign K5[28] = decrypt_int ? K[7] : K[2]; +assign K5[29] = decrypt_int ? K[22] : K[45]; +assign K5[30] = decrypt_int ? K[23] : K[42]; +assign K5[31] = decrypt_int ? K[44] : K[8]; +assign K5[32] = decrypt_int ? K[28] : K[23]; +assign K5[33] = decrypt_int ? K[50] : K[14]; +assign K5[34] = decrypt_int ? K[8] : K[31]; +assign K5[35] = decrypt_int ? K[38] : K[29]; +assign K5[36] = decrypt_int ? K[29] : K[52]; +assign K5[37] = decrypt_int ? K[1] : K[51]; +assign K5[38] = decrypt_int ? K[36] : K[0]; +assign K5[39] = decrypt_int ? K[21] : K[16]; +assign K5[40] = decrypt_int ? K[30] : K[49]; +assign K5[41] = decrypt_int ? K[45] : K[36]; +assign K5[42] = decrypt_int ? K[9] : K[28]; +assign K5[43] = decrypt_int ? K[15] : K[38]; +assign K5[44] = decrypt_int ? K[42] : K[37]; +assign K5[45] = decrypt_int ? K[43] : K[7]; +assign K5[46] = decrypt_int ? K[0] : K[50]; +assign K5[47] = decrypt_int ? K[37] : K[1]; +assign K5[48] = decrypt_int ? K[31] : K[22]; + +assign K4[1] = decrypt_int ? K[5] : K[25]; +assign K4[2] = decrypt_int ? K[26] : K[46]; +assign K4[3] = decrypt_int ? K[41] : K[4]; +assign K4[4] = decrypt_int ? K[18] : K[13]; +assign K4[5] = decrypt_int ? K[53] : K[48]; +assign K4[6] = decrypt_int ? K[24] : K[19]; +assign K4[7] = decrypt_int ? K[10] : K[5]; +assign K4[8] = decrypt_int ? K[46] : K[41]; +assign K4[9] = decrypt_int ? K[12] : K[32]; +assign K4[10] = decrypt_int ? K[6] : K[26]; +assign K4[11] = decrypt_int ? K[54] : K[17]; +assign K4[12] = decrypt_int ? K[34] : K[54]; +assign K4[13] = decrypt_int ? K[11] : K[6]; +assign K4[14] = decrypt_int ? K[40] : K[3]; +assign K4[15] = decrypt_int ? K[48] : K[11]; +assign K4[16] = decrypt_int ? K[17] : K[12]; +assign K4[17] = decrypt_int ? K[32] : K[27]; +assign K4[18] = decrypt_int ? K[20] : K[40]; +assign K4[19] = decrypt_int ? K[19] : K[39]; +assign K4[20] = decrypt_int ? K[13] : K[33]; +assign K4[21] = decrypt_int ? K[39] : K[34]; +assign K4[22] = decrypt_int ? K[47] : K[10]; +assign K4[23] = decrypt_int ? K[55] : K[18]; +assign K4[24] = decrypt_int ? K[3] : K[55]; +assign K4[25] = decrypt_int ? K[49] : K[16]; +assign K4[26] = decrypt_int ? K[16] : K[7]; +assign K4[27] = decrypt_int ? K[38] : K[1]; +assign K4[28] = decrypt_int ? K[21] : K[43]; +assign K4[29] = decrypt_int ? K[36] : K[31]; +assign K4[30] = decrypt_int ? K[37] : K[28]; +assign K4[31] = decrypt_int ? K[31] : K[49]; +assign K4[32] = decrypt_int ? K[42] : K[9]; +assign K4[33] = decrypt_int ? K[9] : K[0]; +assign K4[34] = decrypt_int ? K[22] : K[44]; +assign K4[35] = decrypt_int ? K[52] : K[15]; +assign K4[36] = decrypt_int ? K[43] : K[38]; +assign K4[37] = decrypt_int ? K[15] : K[37]; +assign K4[38] = decrypt_int ? K[50] : K[45]; +assign K4[39] = decrypt_int ? K[35] : K[2]; +assign K4[40] = decrypt_int ? K[44] : K[35]; +assign K4[41] = decrypt_int ? K[0] : K[22]; +assign K4[42] = decrypt_int ? K[23] : K[14]; +assign K4[43] = decrypt_int ? K[29] : K[51]; +assign K4[44] = decrypt_int ? K[1] : K[23]; +assign K4[45] = decrypt_int ? K[2] : K[52]; +assign K4[46] = decrypt_int ? K[14] : K[36]; +assign K4[47] = decrypt_int ? K[51] : K[42]; +assign K4[48] = decrypt_int ? K[45] : K[8]; + +assign K3[1] = decrypt_int ? K[19] : K[11]; +assign K3[2] = decrypt_int ? K[40] : K[32]; +assign K3[3] = decrypt_int ? K[55] : K[47]; +assign K3[4] = decrypt_int ? K[32] : K[24]; +assign K3[5] = decrypt_int ? K[10] : K[34]; +assign K3[6] = decrypt_int ? K[13] : K[5]; +assign K3[7] = decrypt_int ? K[24] : K[48]; +assign K3[8] = decrypt_int ? K[3] : K[27]; +assign K3[9] = decrypt_int ? K[26] : K[18]; +assign K3[10] = decrypt_int ? K[20] : K[12]; +assign K3[11] = decrypt_int ? K[11] : K[3]; +assign K3[12] = decrypt_int ? K[48] : K[40]; +assign K3[13] = decrypt_int ? K[25] : K[17]; +assign K3[14] = decrypt_int ? K[54] : K[46]; +assign K3[15] = decrypt_int ? K[5] : K[54]; +assign K3[16] = decrypt_int ? K[6] : K[55]; +assign K3[17] = decrypt_int ? K[46] : K[13]; +assign K3[18] = decrypt_int ? K[34] : K[26]; +assign K3[19] = decrypt_int ? K[33] : K[25]; +assign K3[20] = decrypt_int ? K[27] : K[19]; +assign K3[21] = decrypt_int ? K[53] : K[20]; +assign K3[22] = decrypt_int ? K[4] : K[53]; +assign K3[23] = decrypt_int ? K[12] : K[4]; +assign K3[24] = decrypt_int ? K[17] : K[41]; +assign K3[25] = decrypt_int ? K[8] : K[2]; +assign K3[26] = decrypt_int ? K[30] : K[52]; +assign K3[27] = decrypt_int ? K[52] : K[42]; +assign K3[28] = decrypt_int ? K[35] : K[29]; +assign K3[29] = decrypt_int ? K[50] : K[44]; +assign K3[30] = decrypt_int ? K[51] : K[14]; +assign K3[31] = decrypt_int ? K[45] : K[35]; +assign K3[32] = decrypt_int ? K[1] : K[50]; +assign K3[33] = decrypt_int ? K[23] : K[45]; +assign K3[34] = decrypt_int ? K[36] : K[30]; +assign K3[35] = decrypt_int ? K[7] : K[1]; +assign K3[36] = decrypt_int ? K[2] : K[51]; +assign K3[37] = decrypt_int ? K[29] : K[23]; +assign K3[38] = decrypt_int ? K[9] : K[31]; +assign K3[39] = decrypt_int ? K[49] : K[43]; +assign K3[40] = decrypt_int ? K[31] : K[21]; +assign K3[41] = decrypt_int ? K[14] : K[8]; +assign K3[42] = decrypt_int ? K[37] : K[0]; +assign K3[43] = decrypt_int ? K[43] : K[37]; +assign K3[44] = decrypt_int ? K[15] : K[9]; +assign K3[45] = decrypt_int ? K[16] : K[38]; +assign K3[46] = decrypt_int ? K[28] : K[22]; +assign K3[47] = decrypt_int ? K[38] : K[28]; +assign K3[48] = decrypt_int ? K[0] : K[49]; + +assign K2[1] = decrypt_int ? K[33] : K[54]; +assign K2[2] = decrypt_int ? K[54] : K[18]; +assign K2[3] = decrypt_int ? K[12] : K[33]; +assign K2[4] = decrypt_int ? K[46] : K[10]; +assign K2[5] = decrypt_int ? K[24] : K[20]; +assign K2[6] = decrypt_int ? K[27] : K[48]; +assign K2[7] = decrypt_int ? K[13] : K[34]; +assign K2[8] = decrypt_int ? K[17] : K[13]; +assign K2[9] = decrypt_int ? K[40] : K[4]; +assign K2[10] = decrypt_int ? K[34] : K[55]; +assign K2[11] = decrypt_int ? K[25] : K[46]; +assign K2[12] = decrypt_int ? K[5] : K[26]; +assign K2[13] = decrypt_int ? K[39] : K[3]; +assign K2[14] = decrypt_int ? K[11] : K[32]; +assign K2[15] = decrypt_int ? K[19] : K[40]; +assign K2[16] = decrypt_int ? K[20] : K[41]; +assign K2[17] = decrypt_int ? K[3] : K[24]; +assign K2[18] = decrypt_int ? K[48] : K[12]; +assign K2[19] = decrypt_int ? K[47] : K[11]; +assign K2[20] = decrypt_int ? K[41] : K[5]; +assign K2[21] = decrypt_int ? K[10] : K[6]; +assign K2[22] = decrypt_int ? K[18] : K[39]; +assign K2[23] = decrypt_int ? K[26] : K[47]; +assign K2[24] = decrypt_int ? K[6] : K[27]; +assign K2[25] = decrypt_int ? K[22] : K[43]; +assign K2[26] = decrypt_int ? K[44] : K[38]; +assign K2[27] = decrypt_int ? K[7] : K[28]; +assign K2[28] = decrypt_int ? K[49] : K[15]; +assign K2[29] = decrypt_int ? K[9] : K[30]; +assign K2[30] = decrypt_int ? K[38] : K[0]; +assign K2[31] = decrypt_int ? K[0] : K[21]; +assign K2[32] = decrypt_int ? K[15] : K[36]; +assign K2[33] = decrypt_int ? K[37] : K[31]; +assign K2[34] = decrypt_int ? K[50] : K[16]; +assign K2[35] = decrypt_int ? K[21] : K[42]; +assign K2[36] = decrypt_int ? K[16] : K[37]; +assign K2[37] = decrypt_int ? K[43] : K[9]; +assign K2[38] = decrypt_int ? K[23] : K[44]; +assign K2[39] = decrypt_int ? K[8] : K[29]; +assign K2[40] = decrypt_int ? K[45] : K[7]; +assign K2[41] = decrypt_int ? K[28] : K[49]; +assign K2[42] = decrypt_int ? K[51] : K[45]; +assign K2[43] = decrypt_int ? K[2] : K[23]; +assign K2[44] = decrypt_int ? K[29] : K[50]; +assign K2[45] = decrypt_int ? K[30] : K[51]; +assign K2[46] = decrypt_int ? K[42] : K[8]; +assign K2[47] = decrypt_int ? K[52] : K[14]; +assign K2[48] = decrypt_int ? K[14] : K[35]; + +assign K1[1] = decrypt_int ? K[40] : K[47]; +assign K1[2] = decrypt_int ? K[4] : K[11]; +assign K1[3] = decrypt_int ? K[19] : K[26]; +assign K1[4] = decrypt_int ? K[53] : K[3]; +assign K1[5] = decrypt_int ? K[6] : K[13]; +assign K1[6] = decrypt_int ? K[34] : K[41]; +assign K1[7] = decrypt_int ? K[20] : K[27]; +assign K1[8] = decrypt_int ? K[24] : K[6]; +assign K1[9] = decrypt_int ? K[47] : K[54]; +assign K1[10] = decrypt_int ? K[41] : K[48]; +assign K1[11] = decrypt_int ? K[32] : K[39]; +assign K1[12] = decrypt_int ? K[12] : K[19]; +assign K1[13] = decrypt_int ? K[46] : K[53]; +assign K1[14] = decrypt_int ? K[18] : K[25]; +assign K1[15] = decrypt_int ? K[26] : K[33]; +assign K1[16] = decrypt_int ? K[27] : K[34]; +assign K1[17] = decrypt_int ? K[10] : K[17]; +assign K1[18] = decrypt_int ? K[55] : K[5]; +assign K1[19] = decrypt_int ? K[54] : K[4]; +assign K1[20] = decrypt_int ? K[48] : K[55]; +assign K1[21] = decrypt_int ? K[17] : K[24]; +assign K1[22] = decrypt_int ? K[25] : K[32]; +assign K1[23] = decrypt_int ? K[33] : K[40]; +assign K1[24] = decrypt_int ? K[13] : K[20]; +assign K1[25] = decrypt_int ? K[29] : K[36]; +assign K1[26] = decrypt_int ? K[51] : K[31]; +assign K1[27] = decrypt_int ? K[14] : K[21]; +assign K1[28] = decrypt_int ? K[1] : K[8]; +assign K1[29] = decrypt_int ? K[16] : K[23]; +assign K1[30] = decrypt_int ? K[45] : K[52]; +assign K1[31] = decrypt_int ? K[7] : K[14]; +assign K1[32] = decrypt_int ? K[22] : K[29]; +assign K1[33] = decrypt_int ? K[44] : K[51]; +assign K1[34] = decrypt_int ? K[2] : K[9]; +assign K1[35] = decrypt_int ? K[28] : K[35]; +assign K1[36] = decrypt_int ? K[23] : K[30]; +assign K1[37] = decrypt_int ? K[50] : K[2]; +assign K1[38] = decrypt_int ? K[30] : K[37]; +assign K1[39] = decrypt_int ? K[15] : K[22]; +assign K1[40] = decrypt_int ? K[52] : K[0]; +assign K1[41] = decrypt_int ? K[35] : K[42]; +assign K1[42] = decrypt_int ? K[31] : K[38]; +assign K1[43] = decrypt_int ? K[9] : K[16]; +assign K1[44] = decrypt_int ? K[36] : K[43]; +assign K1[45] = decrypt_int ? K[37] : K[44]; +assign K1[46] = decrypt_int ? K[49] : K[1]; +assign K1[47] = decrypt_int ? K[0] : K[7]; +assign K1[48] = decrypt_int ? K[21] : K[28]; + +endmodule diff --git a/designs/encrypted_ip/des3_area/mc_adr_sel.v b/designs/encrypted_ip/des3_area/mc_adr_sel.v new file mode 100644 index 000000000..372ca67b5 --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_adr_sel.v @@ -0,0 +1,286 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Address Select Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_adr_sel.v,v 1.4 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.2 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.1.1.1 2001/05/13 09:39:40 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_adr_sel(clk, csc, tms, wb_ack_o, wb_stb_i, wb_addr_i, wb_we_i, + wb_write_go, wr_hold, cas_, + mc_addr, row_adr, bank_adr, rfr_ack, + cs_le, cmd_a10, row_sel, lmr_sel, next_adr, wr_cycle, + page_size); + +input clk; +input [31:0] csc; +input [31:0] tms; +input wb_ack_o, wb_stb_i; +input [31:0] wb_addr_i; +input wb_we_i; +input wb_write_go; +input wr_hold; +input cas_; +output [23:0] mc_addr; +output [12:0] row_adr; +output [1:0] bank_adr; +input rfr_ack; +input cs_le; +input cmd_a10; +input row_sel; +input lmr_sel; +input next_adr; +input wr_cycle; +output [10:0] page_size; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg [23:0] mc_addr_d; +reg [23:0] acs_addr; +wire [23:0] acs_addr_pl1; +reg [23:0] sram_addr; +wire [14:0] sdram_adr; +reg [12:0] row_adr; +reg [9:0] col_adr; +reg [1:0] bank_adr; +reg [10:0] page_size; + +wire [2:0] mem_type; +wire [1:0] bus_width; +wire [1:0] mem_size; +wire bas; + +// Aliases +assign mem_type = csc[3:1]; +assign bus_width = csc[5:4]; +assign mem_size = csc[7:6]; +assign bas = csc[9]; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(mem_type or wr_hold or sdram_adr or acs_addr or sram_addr or wb_addr_i) + if(mem_type == `MC_MEM_TYPE_SDRAM) mc_addr_d = {9'h0, sdram_adr}; + else + if(mem_type == `MC_MEM_TYPE_ACS) mc_addr_d = acs_addr; + else + if((mem_type == `MC_MEM_TYPE_SRAM) & wr_hold) mc_addr_d = sram_addr; + else mc_addr_d = wb_addr_i[25:2]; + +assign mc_addr = rfr_ack ? {mc_addr_d[23:11], 1'b1, mc_addr_d[9:0]} : mc_addr_d; + +//////////////////////////////////////////////////////////////////// +// +// Async Devices Address Latch & Counter +// + +mc_incn_r #(24) u0( .clk( clk ), + .inc_in( acs_addr ), + .inc_out( acs_addr_pl1 ) ); + +always @(posedge clk) + if(wb_stb_i) sram_addr <= #1 wb_addr_i[25:2]; + +always @(posedge clk) + if(cs_le | wb_we_i) + case(bus_width) // synopsys full_case parallel_case + `MC_BW_8: acs_addr <= #1 wb_addr_i[23:0]; + `MC_BW_16: acs_addr <= #1 wb_addr_i[24:1]; + `MC_BW_32: acs_addr <= #1 wb_addr_i[25:2]; + endcase + else + if(next_adr) acs_addr <= #1 acs_addr_pl1; + +//////////////////////////////////////////////////////////////////// +// +// SDRAM Address Mux +// + +assign sdram_adr[12:0] = (lmr_sel & !cas_) ? tms[12:0] : + row_sel ? row_adr : + {2'h0, cmd_a10, col_adr}; + +assign sdram_adr[14:13] = bank_adr; + +always @(posedge clk) + if(wr_cycle ? wb_ack_o : wb_stb_i) + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: col_adr <= #1 {1'h0, wb_addr_i[10:2]}; + {`MC_BW_8, `MC_MEM_SIZE_128}: col_adr <= #1 wb_addr_i[11:2]; + {`MC_BW_8, `MC_MEM_SIZE_256}: col_adr <= #1 wb_addr_i[11:2]; + + {`MC_BW_16, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]}; + {`MC_BW_16, `MC_MEM_SIZE_128}: col_adr <= #1 {1'h0, wb_addr_i[10:2]}; + {`MC_BW_16, `MC_MEM_SIZE_256}: col_adr <= #1 {1'h0, wb_addr_i[10:2]}; + + {`MC_BW_32, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]}; + {`MC_BW_32, `MC_MEM_SIZE_128}: col_adr <= #1 {2'h0, wb_addr_i[09:2]}; + {`MC_BW_32, `MC_MEM_SIZE_256}: col_adr <= #1 {2'h0, wb_addr_i[09:2]}; + endcase + +always @(posedge clk) + if(cs_le) + begin + if(!bas) + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[24:13]}; + {`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[25:14]}; + {`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[26:14]; + + {`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[23:12]}; + {`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[24:13]}; + {`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[25:13]; + + {`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[22:12]}; + {`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]}; + {`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12]; + endcase + else + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[22:11]}; + {`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]}; + {`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12]; + + {`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[21:10]}; + {`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[22:11]}; + {`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[23:11]; + + {`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[20:10]}; + {`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[21:10]}; + {`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[22:10]; + endcase + end + + +always @(posedge clk) + if(cs_le) + begin + if(!bas) + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[12:11]; + {`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[13:12]; + {`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[13:12]; + + {`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10]; + {`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[12:11]; + {`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[12:11]; + + {`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10]; + {`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[11:10]; + {`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[11:10]; + endcase + else + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[24:23]; + {`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[25:24]; + {`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[26:25]; + + {`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[23:22]; + {`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[24:23]; + {`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[25:24]; + + {`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[22:21]; + {`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[23:22]; + {`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[24:23]; + endcase + end + +always @(bus_width or mem_size) + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: page_size = 11'd512; + {`MC_BW_8, `MC_MEM_SIZE_128}: page_size = 11'd1024; + {`MC_BW_8, `MC_MEM_SIZE_256}: page_size = 11'd1024; + + {`MC_BW_16, `MC_MEM_SIZE_64}: page_size = 11'd256; + {`MC_BW_16, `MC_MEM_SIZE_128}: page_size = 11'd512; + {`MC_BW_16, `MC_MEM_SIZE_256}: page_size = 11'd512; + + {`MC_BW_32, `MC_MEM_SIZE_64}: page_size = 11'd256; + {`MC_BW_32, `MC_MEM_SIZE_128}: page_size = 11'd256; + {`MC_BW_32, `MC_MEM_SIZE_256}: page_size = 11'd256; + endcase + +endmodule + diff --git a/designs/encrypted_ip/des3_area/mc_cs_rf.v b/designs/encrypted_ip/des3_area/mc_cs_rf.v new file mode 100644 index 000000000..98274d874 --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_cs_rf.v @@ -0,0 +1,272 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Chip Select Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_cs_rf.v,v 1.6 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.5 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.4 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.3 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:42 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_cs_rf(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs, + wp_err, lmr_req, lmr_ack, init_req, init_ack ); + +input clk, rst; +input wb_we_i; +input [31:0] din; +input rf_we; +input [31:0] addr; + +output [31:0] csc; +output [31:0] tms; +input [31:0] poc; +input [31:0] csc_mask; +output cs; +output wp_err; + +output lmr_req; +input lmr_ack; +output init_req; +input init_ack; + +parameter [2:0] this_cs = 0; +parameter [3:0] reg_select = this_cs + 2; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers and Wires +// + +reg [31:0] csc; +reg [31:0] tms; +wire sel; +wire cs_d; +wire wp; +reg inited; +reg init_req; +reg init_req_we; +reg lmr_req; +reg lmr_req_we; + +//////////////////////////////////////////////////////////////////// +// +// A kludge for cases where there is no clock during reset ... +// + +reg rst_r1, rst_r2; + +always @(posedge clk or posedge rst) + if(rst) rst_r1 <= #1 1'b1; + else rst_r1 <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) rst_r2 <= #1 1'b1; + else rst_r2 <= #1 rst_r1; + +//////////////////////////////////////////////////////////////////// +// +// Write Logic +// + +reg [6:0] addr_r; + +always @(posedge clk) + addr_r <= #1 addr[6:0]; + +assign sel = addr_r[6:3] == reg_select[3:0]; + +always @(posedge clk) + if(rst_r2) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? + {26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0; + else + if(rf_we & sel & !addr_r[2]) csc <= #1 din; + +always @(posedge clk) + if(rst_r2) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? + `MC_DEF_POR_TMS : 32'h0; + else + if(rf_we & sel & addr_r[2]) tms <= #1 din; + +//////////////////////////////////////////////////////////////////// +// +// Load Mode Register Request/Ack Logic +// +always @(posedge clk or posedge rst) + if(rst) lmr_req_we <= #1 1'b0; + else lmr_req_we <= #1 rf_we & sel & addr_r[2]; + +always @(posedge clk or posedge rst) + if(rst) lmr_req <= #1 1'b0; + else + if(lmr_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM)) + lmr_req <= #1 inited; + else + if(lmr_ack) lmr_req <= #1 1'b0; + +//////////////////////////////////////////////////////////////////// +// +// Initialize SDRAM Request/Ack & tracking logic +// +always @(posedge clk or posedge rst) + if(rst) init_req_we <= #1 1'b0; + else init_req_we <= #1 rf_we & sel & !addr_r[2]; + +always @(posedge clk or posedge rst) + if(rst) init_req <= #1 1'b0; + else + if(init_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM) & csc[0] & !inited) + init_req <= #1 1'b1; + else + if(init_ack) init_req <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) inited <= #1 1'b0; + else + if(init_ack) inited <= #1 1'b1; + +//////////////////////////////////////////////////////////////////// +// +// Chip Select Generation Logic +// + +assign cs_d = ((csc[23:16] & csc_mask[7:0]) == (addr[28:21] & csc_mask[7:0])) & csc[0]; + +assign wp = wb_we_i & csc[8]; + +assign wp_err = cs_d & wp; +assign cs = cs_d & !wp; + +endmodule + + + +// This dummy is used to terminate the outputs for non existing Chip Selects +module mc_cs_rf_dummy(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs, + wp_err, lmr_req, lmr_ack, init_req, init_ack ); + +parameter [2:0] this_cs = 0; + +input clk, rst; +input wb_we_i; +input [31:0] din; +input rf_we; +input [31:0] addr; + +output [31:0] csc; +output [31:0] tms; +input [31:0] poc; +input [31:0] csc_mask; +output cs; +output wp_err; + +output lmr_req; +input lmr_ack; +output init_req; +input init_ack; + +assign csc = 32'h0; +assign tms = 32'h0; +assign cs = 1'b0; +assign wp_err = 1'b0; +assign lmr_req = 1'b0; +assign init_req = 1'b0; + +endmodule diff --git a/designs/encrypted_ip/des3_area/mc_defines.v b/designs/encrypted_ip/des3_area/mc_defines.v new file mode 100644 index 000000000..876e71dba --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_defines.v @@ -0,0 +1,228 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_defines.v,v 1.7 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.7 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.6 2001/12/12 06:35:15 rudi +// *** empty log message *** +// +// Revision 1.5 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.4 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.3 2001/09/10 13:44:17 rudi +// *** empty log message *** +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug +// fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:38 rudi +// Created Directory Structure +// +// +// +// + +`timescale 1ns / 10ps + +///////////////////////////////////////////////////////////////////// +// +// This define selects how the WISHBONE interface determines if +// the internal register file is selected. +// This should be a simple address decoder. "wb_addr_i" is the +// WISHBONE address bus (32 bits wide). +`define MC_REG_SEL (wb_addr_i[31:29] == 3'b011) + +// This define selects how the WISHBONE interface determines if +// the memory is selected. +// This should be a simple address decoder. "wb_addr_i" is the +// WISHBONE address bus (32 bits wide). +`define MC_MEM_SEL (wb_addr_i[31:29] == 3'h0) + +///////////////////////////////////////////////////////////////////// +// +// This are the default Power-On Reset values for Chip Select +// + +// This will be defined by the run script for my test bench ... +// Alternatively force here for synthesis ... +//`define RUDIS_TB 1 + +// Defines which chip select is used for Power On booting + +// To run my default testbench default boot CS must be 3 !!! +`ifdef RUDIS_TB +`define MC_DEF_SEL 3'h3 +`else +`define MC_DEF_SEL 3'h0 +`endif + +// Defines the default (reset) TMS value for the DEF_SEL chip select +`define MC_DEF_POR_TMS 32'hffff_ffff + + +///////////////////////////////////////////////////////////////////// +// +// Define how many Chip Selects to Implement +// +`define MC_HAVE_CS1 1 +//`define MC_HAVE_CS2 1 +//`define MC_HAVE_CS3 1 +//`define MC_HAVE_CS4 1 +//`define MC_HAVE_CS5 1 +//`define MC_HAVE_CS6 1 +//`define MC_HAVE_CS7 1 + + +// To run my default testbench those need to there !!! +`ifdef RUDIS_TB +`define MC_HAVE_CS2 1 +`define MC_HAVE_CS3 1 +`define MC_HAVE_CS4 1 +`define MC_HAVE_CS5 1 +`endif + +///////////////////////////////////////////////////////////////////// +// +// Init Refresh +// +// Number of Refresh Cycles to perform during SDRAM initialization. +// This varies between SDRAM manufacturer. Typically this value is +// between 2 and 8. This number must be smaller than 16. +`define MC_INIT_RFRC_CNT 2 + +///////////////////////////////////////////////////////////////////// +// +// Power On Delay +// +// Most if SDRAMs require some time to initialize before they can be used +// after power on. If the Memory Controller shall stall after power on to +// allow SDRAMs to finish the initialization process uncomment the below +// define statement +`define MC_POR_DELAY 1 + +// This value defines how many MEM_CLK cycles the Memory Controller should +// stall. Default is 2.5uS. At a 10nS MEM_CLK cycle time, this would 250 +// cycles. +`define MC_POR_DELAY_VAL 8'd250 + + +// =============================================================== +// =============================================================== +// Various internal defines (DO NOT MODIFY !) +// =============================================================== +// =============================================================== + +// Register settings encodings +`define MC_BW_8 2'h0 +`define MC_BW_16 2'h1 +`define MC_BW_32 2'h2 + +`define MC_MEM_TYPE_SDRAM 3'h0 +`define MC_MEM_TYPE_SRAM 3'h1 +`define MC_MEM_TYPE_ACS 3'h2 +`define MC_MEM_TYPE_SCS 3'h3 + +`define MC_MEM_SIZE_64 2'h0 +`define MC_MEM_SIZE_128 2'h1 +`define MC_MEM_SIZE_256 2'h2 + +// Command Valid, Ras_, Cas_, We_ +`define MC_CMD_NOP 4'b0111 +`define MC_CMD_PC 4'b1010 +`define MC_CMD_ACT 4'b1011 +`define MC_CMD_WR 4'b1100 +`define MC_CMD_RD 4'b1101 +`define MC_CMD_BT 4'b1110 +`define MC_CMD_ARFR 4'b1001 +`define MC_CMD_LMR 4'b1000 +`define MC_CMD_XRD 4'b1111 +`define MC_CMD_XWR 4'b1110 + +`define MC_SINGLE_BANK 1'b0 +`define MC_ALL_BANKS 1'b1 + diff --git a/designs/encrypted_ip/des3_area/mc_dp.v b/designs/encrypted_ip/des3_area/mc_dp.v new file mode 100644 index 000000000..cff65e16b --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_dp.v @@ -0,0 +1,240 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Data Path Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_dp.v,v 1.6 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.5 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.4 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.3 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:47 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_dp( clk, rst, csc, + wb_cyc_i, wb_stb_i, wb_ack_o, mem_ack, wb_data_i, wb_data_o, + wb_read_go, wb_we_i, + mc_clk, mc_data_del, mc_dp_i, mc_data_o, mc_dp_o, + + dv, pack_le0, pack_le1, pack_le2, + byte_en, par_err + ); + +input clk, rst; +input [31:0] csc; + +input wb_cyc_i; +input wb_stb_i; +input mem_ack; +input wb_ack_o; +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input wb_read_go; +input wb_we_i; + +input mc_clk; +input [35:0] mc_data_del; +input [3:0] mc_dp_i; +output [31:0] mc_data_o; +output [3:0] mc_dp_o; + +input dv; +input pack_le0, pack_le1, pack_le2; // Pack Latch Enable +input [3:0] byte_en; // High Active byte enables +output par_err; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg [31:0] wb_data_o; +reg [31:0] mc_data_o; +wire [35:0] rd_fifo_out; +wire rd_fifo_clr; +reg [3:0] mc_dp_o; +reg par_err_r; + +reg [7:0] byte0, byte1, byte2; +reg [31:0] mc_data_d; + +wire [2:0] mem_type; +wire [1:0] bus_width; +wire pen; +wire re; + +// Aliases +assign mem_type = csc[3:1]; +assign bus_width = csc[5:4]; +assign pen = csc[11]; + +//////////////////////////////////////////////////////////////////// +// +// WB READ Data Path +// + +always @(mem_type or rd_fifo_out or mc_data_d) + if( (mem_type == `MC_MEM_TYPE_SDRAM) | + (mem_type == `MC_MEM_TYPE_SRAM) ) wb_data_o = rd_fifo_out[31:0]; + else wb_data_o = mc_data_d; + +//assign rd_fifo_clr = !(rst | !wb_cyc_i | (wb_we_i & wb_stb_i) ); +assign rd_fifo_clr = !wb_cyc_i | (wb_we_i & wb_stb_i); +assign re = wb_ack_o & wb_read_go; + +mc_rd_fifo u0( + .clk( clk ), + .rst( rst ), + .clr( rd_fifo_clr ), + .din( mc_data_del ), + .we( dv ), + .dout( rd_fifo_out ), + .re( re ) + ); + +//////////////////////////////////////////////////////////////////// +// +// WB WRITE Data Path +// + +always @(posedge clk) + if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) ) + mc_data_o <= #1 wb_data_i; + +//////////////////////////////////////////////////////////////////// +// +// Read Data Packing +// + +always @(posedge clk) + if(pack_le0) byte0 <= #1 mc_data_del[7:0]; + +always @(posedge clk) + if(pack_le1 & (bus_width == `MC_BW_8)) byte1 <= #1 mc_data_del[7:0]; + else + if(pack_le0 & (bus_width == `MC_BW_16)) byte1 <= #1 mc_data_del[15:8]; + +always @(posedge clk) + if(pack_le2) byte2 <= #1 mc_data_del[7:0]; + +always @(bus_width or mc_data_del or byte0 or byte1 or byte2) + if(bus_width == `MC_BW_8) mc_data_d = {mc_data_del[7:0], byte2, byte1, byte0}; + else + if(bus_width == `MC_BW_16) mc_data_d = {mc_data_del[15:0], byte1, byte0}; + else mc_data_d = mc_data_del[31:0]; + +//////////////////////////////////////////////////////////////////// +// +// Parity Generation +// + +always @(posedge clk) + if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) ) + mc_dp_o <= #1 { ^wb_data_i[31:24], ^wb_data_i[23:16], + ^wb_data_i[15:08], ^wb_data_i[07:00] }; + +//////////////////////////////////////////////////////////////////// +// +// Parity Checking +// + +assign par_err = !wb_we_i & mem_ack & pen & ( + (( ^rd_fifo_out[31:24] ^ rd_fifo_out[35] ) & byte_en[3] ) | + (( ^rd_fifo_out[23:16] ^ rd_fifo_out[34] ) & byte_en[2] ) | + (( ^rd_fifo_out[15:08] ^ rd_fifo_out[33] ) & byte_en[1] ) | + (( ^rd_fifo_out[07:00] ^ rd_fifo_out[32] ) & byte_en[0] ) + ); + +endmodule + diff --git a/designs/encrypted_ip/des3_area/mc_incn_r.v b/designs/encrypted_ip/des3_area/mc_incn_r.v new file mode 100644 index 000000000..54112019f --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_incn_r.v @@ -0,0 +1,98 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Parametarized, Pipelined Incrementer //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_incn_r.v,v 1.2 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.1 2001/06/12 15:18:47 rudi +// +// +// This is a pipelined primitive incrementor. +// +// +// +// +// + +`include "mc_defines.v" + +// +// USAGE: incN_r #() uN(clk, input, output); +// +module mc_incn_r(clk, inc_in, inc_out); + +parameter incN_width = 32; + +input clk; +input [incN_width-1:0] inc_in; +output [incN_width-1:0] inc_out; + +parameter incN_center = incN_width / 2; + +reg [incN_center:0] out_r; +wire [31:0] tmp_zeros = 32'h0; +wire [incN_center-1:0] inc_next; + +always @(posedge clk) + out_r <= #1 inc_in[incN_center - 1:0] + {tmp_zeros[incN_center-2:0], 1'h1}; + +assign inc_out[incN_width-1:incN_center] = inc_in[incN_width-1:incN_center] + inc_next; + +assign inc_next = out_r[incN_center] ? + {tmp_zeros[incN_center-2:0], 1'h1} : tmp_zeros[incN_center-2:0]; + +assign inc_out[incN_center-1:0] = out_r; + +endmodule + diff --git a/designs/encrypted_ip/des3_area/mc_mem_if.v b/designs/encrypted_ip/des3_area/mc_mem_if.v new file mode 100644 index 000000000..8bfdb0dc9 --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_mem_if.v @@ -0,0 +1,358 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Memory Bus Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_mem_if.v,v 1.6 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.5 2001/12/21 05:09:29 rudi +// +// - Fixed combinatorial loops in synthesis +// - Fixed byte select bug +// +// Revision 1.4 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.3 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.2 2001/09/02 02:28:28 rudi +// +// Many fixes for minor bugs that showed up in gate level simulations. +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/14 01:57:37 rudi +// +// +// Fixed a potential bug in a corner case situation where the TMS register +// does not propegate properly during initialisation. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:48 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_mem_if(clk, rst, mc_clk, mc_br, mc_bg, + mc_addr, mc_data_o, mc_dp_o, mc_data_oe, + mc_dqm, mc_oe_, mc_we_, mc_cas_, mc_ras_, mc_cke_, mc_cs_, + mc_adsc_, mc_adv_, mc_ack, mc_rp, mc_c_oe, mc_c_oe_d, + mc_br_r, mc_bg_d, mc_data_od, mc_dp_od, mc_addr_d, mc_ack_r, + we_, ras_, cas_, cke_, mc_adsc_d, mc_adv_d, cs_en, rfr_ack, + cs_need_rfr, lmr_sel, spec_req_cs, cs, fs, data_oe, susp_sel, + suspended_o, oe_, wb_cyc_i, wb_stb_i, wb_sel_i, wb_cycle, + wr_cycle, mc_data_ir, mc_data_i, mc_dp_i, mc_sts_ir, mc_sts_i, + mc_zz_o + ); +// Memory Interface +input clk; +input rst; +input mc_clk; +input mc_br; +output mc_bg; +output [23:0] mc_addr; +output [31:0] mc_data_o; +output [3:0] mc_dp_o; +output mc_data_oe; +output [3:0] mc_dqm; +output mc_oe_; +output mc_we_; +output mc_cas_; +output mc_ras_; +output mc_cke_; +output [7:0] mc_cs_; +output mc_adsc_; +output mc_adv_; +input mc_ack; +output mc_rp; +output mc_c_oe; +output [35:0] mc_data_ir; +output mc_sts_ir; +output mc_zz_o; + +// Internal Interface +output mc_br_r; +input mc_bg_d; +input data_oe; +input susp_sel; +input suspended_o; +input [31:0] mc_data_od; +input [3:0] mc_dp_od; +input [23:0] mc_addr_d; +output mc_ack_r; +input wb_cyc_i; +input wb_stb_i; +input [3:0] wb_sel_i; +input wb_cycle; +input wr_cycle; +input oe_ ; +input we_; +input ras_; +input cas_; +input cke_; +input cs_en; +input rfr_ack; +input [7:0] cs_need_rfr; +input lmr_sel; +input [7:0] spec_req_cs; +input [7:0] cs; +input fs; +input mc_adsc_d; +input mc_adv_d; +input mc_c_oe_d; +input [31:0] mc_data_i; +input [3:0] mc_dp_i; +input mc_sts_i; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg mc_data_oe; +reg [31:0] mc_data_o; +reg [3:0] mc_dp_o; +reg [3:0] mc_dqm; +reg [3:0] mc_dqm_r; +reg [23:0] mc_addr; +reg mc_oe_; +reg mc_we_; +reg mc_cas_; +reg mc_ras_; +wire mc_cke_; +reg [7:0] mc_cs_; +reg mc_bg; +reg mc_adsc_; +reg mc_adv_; +reg mc_br_r; +reg mc_ack_r; +reg mc_rp; +reg mc_c_oe; +reg mc_zz_o; + +reg [35:0] mc_data_ir; +reg mc_sts_ir; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge mc_clk) + mc_zz_o <= #1 suspended_o; + +always @(posedge mc_clk) + mc_sts_ir <= #1 mc_sts_i; + +always @(posedge mc_clk) + mc_data_ir <= #1 {mc_dp_i, mc_data_i}; + +always @(posedge mc_clk) + mc_c_oe <= #1 mc_c_oe_d; + +always @(posedge mc_clk) + mc_rp <= #1 !suspended_o & !fs; + +always @(posedge mc_clk) + mc_br_r <= #1 mc_br; + +always @(posedge mc_clk) + mc_ack_r <= #1 mc_ack; + +always @(posedge mc_clk) + mc_bg <= #1 mc_bg_d; + +always @(posedge mc_clk or posedge rst) + if(rst) mc_data_oe <= #1 1'b0; + else mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe_d; + +always @(posedge mc_clk) + mc_data_o <= #1 mc_data_od; + +always @(posedge mc_clk) + mc_dp_o <= #1 mc_dp_od; + +always @(posedge mc_clk) + mc_addr <= #1 mc_addr_d; + +always @(posedge clk) + if(wb_cyc_i & wb_stb_i) + mc_dqm_r <= #1 wb_sel_i; + +reg [3:0] mc_dqm_r2; +always @(posedge clk) + mc_dqm_r2 <= #1 mc_dqm_r; + +always @(posedge mc_clk) + mc_dqm <= #1 susp_sel ? 4'hf : + data_oe ? ~mc_dqm_r2 : + (wb_cycle & !wr_cycle) ? 4'h0 : 4'hf; + +always @(posedge mc_clk or posedge rst) + if(rst) mc_oe_ <= #1 1'b1; + else mc_oe_ <= #1 oe_ | susp_sel; + +always @(posedge mc_clk) + mc_we_ <= #1 we_; + +always @(posedge mc_clk) + mc_cas_ <= #1 cas_; + +always @(posedge mc_clk) + mc_ras_ <= #1 ras_; + +assign mc_cke_ = cke_; + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[0] <= #1 1'b1; + else + mc_cs_[0] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[0] : + lmr_sel ? spec_req_cs[0] : + cs[0] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[1] <= #1 1'b1; + else + mc_cs_[1] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[1] : + lmr_sel ? spec_req_cs[1] : + cs[1] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[2] <= #1 1'b1; + else + mc_cs_[2] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[2] : + lmr_sel ? spec_req_cs[2] : + cs[2] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[3] <= #1 1'b1; + else + mc_cs_[3] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[3] : + lmr_sel ? spec_req_cs[3] : + cs[3] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[4] <= #1 1'b1; + else + mc_cs_[4] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[4] : + lmr_sel ? spec_req_cs[4] : + cs[4] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[5] <= #1 1'b1; + else + mc_cs_[5] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[5] : + lmr_sel ? spec_req_cs[5] : + cs[5] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[6] <= #1 1'b1; + else + mc_cs_[6] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[6] : + lmr_sel ? spec_req_cs[6] : + cs[6] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[7] <= #1 1'b1; + else + mc_cs_[7] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[7] : + lmr_sel ? spec_req_cs[7] : + cs[7] + )); + +always @(posedge mc_clk) + mc_adsc_ <= #1 ~mc_adsc_d; + +always @(posedge mc_clk) + mc_adv_ <= #1 ~mc_adv_d; + +endmodule diff --git a/designs/encrypted_ip/des3_area/mc_obct.v b/designs/encrypted_ip/des3_area/mc_obct.v new file mode 100644 index 000000000..b11d41483 --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_obct.v @@ -0,0 +1,232 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Open Bank & Row Tracking Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_obct.v,v 1.4 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.2 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:45 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_obct(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all, + bank_open, any_bank_open, row_same); +input clk, rst; +input [12:0] row_adr; +input [1:0] bank_adr; +input bank_set; +input bank_clr; +input bank_clr_all; +output bank_open; +output any_bank_open; +output row_same; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg bank0_open, bank1_open, bank2_open, bank3_open; +reg bank_open; +reg [12:0] b0_last_row; +reg [12:0] b1_last_row; +reg [12:0] b2_last_row; +reg [12:0] b3_last_row; +wire row0_same, row1_same, row2_same, row3_same; +reg row_same; + +//////////////////////////////////////////////////////////////////// +// +// Bank Open/Closed Tracking +// + +always @(posedge clk or posedge rst) + if(rst) bank0_open <= #1 1'b0; + else + if((bank_adr == 2'h0) & bank_set) bank0_open <= #1 1'b1; + else + if((bank_adr == 2'h0) & bank_clr) bank0_open <= #1 1'b0; + else + if(bank_clr_all) bank0_open <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) bank1_open <= #1 1'b0; + else + if((bank_adr == 2'h1) & bank_set) bank1_open <= #1 1'b1; + else + if((bank_adr == 2'h1) & bank_clr) bank1_open <= #1 1'b0; + else + if(bank_clr_all) bank1_open <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) bank2_open <= #1 1'b0; + else + if((bank_adr == 2'h2) & bank_set) bank2_open <= #1 1'b1; + else + if((bank_adr == 2'h2) & bank_clr) bank2_open <= #1 1'b0; + else + if(bank_clr_all) bank2_open <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) bank3_open <= #1 1'b0; + else + if((bank_adr == 2'h3) & bank_set) bank3_open <= #1 1'b1; + else + if((bank_adr == 2'h3) & bank_clr) bank3_open <= #1 1'b0; + else + if(bank_clr_all) bank3_open <= #1 1'b0; + +always @(bank_adr or bank0_open or bank1_open or bank2_open or bank3_open) + case(bank_adr) // synopsys full_case parallel_case + 2'h0: bank_open = bank0_open; + 2'h1: bank_open = bank1_open; + 2'h2: bank_open = bank2_open; + 2'h3: bank_open = bank3_open; + endcase + +assign any_bank_open = bank0_open | bank1_open | bank2_open | bank3_open; + +//////////////////////////////////////////////////////////////////// +// +// Raw Address Tracking +// + +always @(posedge clk) + if((bank_adr == 2'h0) & bank_set) b0_last_row <= #1 row_adr; + +always @(posedge clk) + if((bank_adr == 2'h1) & bank_set) b1_last_row <= #1 row_adr; + +always @(posedge clk) + if((bank_adr == 2'h2) & bank_set) b2_last_row <= #1 row_adr; + +always @(posedge clk) + if((bank_adr == 2'h3) & bank_set) b3_last_row <= #1 row_adr; + +//////////////////////////////////////////////////////////////////// +// +// Raw address checking +// + +assign row0_same = (b0_last_row == row_adr); +assign row1_same = (b1_last_row == row_adr); +assign row2_same = (b2_last_row == row_adr); +assign row3_same = (b3_last_row == row_adr); + +always @(bank_adr or row0_same or row1_same or row2_same or row3_same) + case(bank_adr) // synopsys full_case parallel_case + 2'h0: row_same = row0_same; + 2'h1: row_same = row1_same; + 2'h2: row_same = row2_same; + 2'h3: row_same = row3_same; + endcase + +endmodule + + +// This is used for unused Chip Selects +module mc_obct_dummy(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all, + bank_open, any_bank_open, row_same); +input clk, rst; +input [12:0] row_adr; +input [1:0] bank_adr; +input bank_set; +input bank_clr; +input bank_clr_all; +output bank_open; +output any_bank_open; +output row_same; + +assign bank_open = 1'b0; +assign any_bank_open = 1'b0; +assign row_same = 1'b0; + +endmodule diff --git a/designs/encrypted_ip/des3_area/mc_obct_top.v b/designs/encrypted_ip/des3_area/mc_obct_top.v new file mode 100644 index 000000000..bbd8ccef2 --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_obct_top.v @@ -0,0 +1,422 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Open Bank & Row Tracking Block Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_obct_top.v,v 1.4 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/12/21 05:09:29 rudi +// +// - Fixed combinatorial loops in synthesis +// - Fixed byte select bug +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.1.1.1 2001/05/13 09:39:47 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_obct_top(clk, rst, cs, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all, + bank_open, any_bank_open, row_same, rfr_ack); +input clk, rst; +input [7:0] cs; +input [12:0] row_adr; +input [1:0] bank_adr; +input bank_set; +input bank_clr; +input bank_clr_all; +output bank_open; +output any_bank_open; +output row_same; +input rfr_ack; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg bank_open; +reg row_same; +reg any_bank_open; + +wire bank_set_0; +wire bank_clr_0; +wire bank_clr_all_0; +wire bank_open_0; +wire row_same_0; +wire any_bank_open_0; + +wire bank_set_1; +wire bank_clr_1; +wire bank_clr_all_1; +wire bank_open_1; +wire row_same_1; +wire any_bank_open_1; + +wire bank_set_2; +wire bank_clr_2; +wire bank_clr_all_2; +wire bank_open_2; +wire row_same_2; +wire any_bank_open_2; + +wire bank_set_3; +wire bank_clr_3; +wire bank_clr_all_3; +wire bank_open_3; +wire row_same_3; +wire any_bank_open_3; + +wire bank_set_4; +wire bank_clr_4; +wire bank_clr_all_4; +wire bank_open_4; +wire row_same_4; +wire any_bank_open_4; + +wire bank_set_5; +wire bank_clr_5; +wire bank_clr_all_5; +wire bank_open_5; +wire row_same_5; +wire any_bank_open_5; + +wire bank_set_6; +wire bank_clr_6; +wire bank_clr_all_6; +wire bank_open_6; +wire row_same_6; +wire any_bank_open_6; + +wire bank_set_7; +wire bank_clr_7; +wire bank_clr_all_7; +wire bank_open_7; +wire row_same_7; +wire any_bank_open_7; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign bank_set_0 = cs[0] & bank_set; +assign bank_set_1 = cs[1] & bank_set; +assign bank_set_2 = cs[2] & bank_set; +assign bank_set_3 = cs[3] & bank_set; +assign bank_set_4 = cs[4] & bank_set; +assign bank_set_5 = cs[5] & bank_set; +assign bank_set_6 = cs[6] & bank_set; +assign bank_set_7 = cs[7] & bank_set; + +assign bank_clr_0 = cs[0] & bank_clr; +assign bank_clr_1 = cs[1] & bank_clr; +assign bank_clr_2 = cs[2] & bank_clr; +assign bank_clr_3 = cs[3] & bank_clr; +assign bank_clr_4 = cs[4] & bank_clr; +assign bank_clr_5 = cs[5] & bank_clr; +assign bank_clr_6 = cs[6] & bank_clr; +assign bank_clr_7 = cs[7] & bank_clr; + +assign bank_clr_all_0 = (cs[0] & bank_clr_all) | rfr_ack; +assign bank_clr_all_1 = (cs[1] & bank_clr_all) | rfr_ack; +assign bank_clr_all_2 = (cs[2] & bank_clr_all) | rfr_ack; +assign bank_clr_all_3 = (cs[3] & bank_clr_all) | rfr_ack; +assign bank_clr_all_4 = (cs[4] & bank_clr_all) | rfr_ack; +assign bank_clr_all_5 = (cs[5] & bank_clr_all) | rfr_ack; +assign bank_clr_all_6 = (cs[6] & bank_clr_all) | rfr_ack; +assign bank_clr_all_7 = (cs[7] & bank_clr_all) | rfr_ack; + +always @(posedge clk) + bank_open <= #1 (cs[0] & bank_open_0) | (cs[1] & bank_open_1) | + (cs[2] & bank_open_2) | (cs[3] & bank_open_3) | + (cs[4] & bank_open_4) | (cs[5] & bank_open_5) | + (cs[6] & bank_open_6) | (cs[7] & bank_open_7); + +always @(posedge clk) + row_same <= #1 (cs[0] & row_same_0) | (cs[1] & row_same_1) | + (cs[2] & row_same_2) | (cs[3] & row_same_3) | + (cs[4] & row_same_4) | (cs[5] & row_same_5) | + (cs[6] & row_same_6) | (cs[7] & row_same_7); + +always @(posedge clk) + any_bank_open <= #1 (cs[0] & any_bank_open_0) | (cs[1] & any_bank_open_1) | + (cs[2] & any_bank_open_2) | (cs[3] & any_bank_open_3) | + (cs[4] & any_bank_open_4) | (cs[5] & any_bank_open_5) | + (cs[6] & any_bank_open_6) | (cs[7] & any_bank_open_7); + + +//////////////////////////////////////////////////////////////////// +// +// OBCT Modules for each Chip Select +// + +mc_obct u0( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_0 ), + .bank_clr( bank_clr_0 ), + .bank_clr_all( bank_clr_all_0 ), + .bank_open( bank_open_0 ), + .any_bank_open( any_bank_open_0 ), + .row_same( row_same_0 ) + ); + +`ifdef MC_HAVE_CS1 +mc_obct u1( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_1 ), + .bank_clr( bank_clr_1 ), + .bank_clr_all( bank_clr_all_1 ), + .bank_open( bank_open_1 ), + .any_bank_open( any_bank_open_1 ), + .row_same( row_same_1 ) + ); +`else +mc_obct_dummy u1( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_1 ), + .bank_clr( bank_clr_1 ), + .bank_clr_all( bank_clr_all_1 ), + .bank_open( bank_open_1 ), + .any_bank_open( any_bank_open_1 ), + .row_same( row_same_1 ) + ); +`endif + +`ifdef MC_HAVE_CS2 +mc_obct u2( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_2 ), + .bank_clr( bank_clr_2 ), + .bank_clr_all( bank_clr_all_2 ), + .bank_open( bank_open_2 ), + .any_bank_open( any_bank_open_2 ), + .row_same( row_same_2 ) + ); +`else +mc_obct_dummy u2( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_2 ), + .bank_clr( bank_clr_2 ), + .bank_clr_all( bank_clr_all_2 ), + .bank_open( bank_open_2 ), + .any_bank_open( any_bank_open_2 ), + .row_same( row_same_2 ) + ); +`endif + +`ifdef MC_HAVE_CS3 +mc_obct u3( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_3 ), + .bank_clr( bank_clr_3 ), + .bank_clr_all( bank_clr_all_3 ), + .bank_open( bank_open_3 ), + .any_bank_open( any_bank_open_3 ), + .row_same( row_same_3 ) + ); +`else +mc_obct_dummy u3( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_3 ), + .bank_clr( bank_clr_3 ), + .bank_clr_all( bank_clr_all_3 ), + .bank_open( bank_open_3 ), + .any_bank_open( any_bank_open_3 ), + .row_same( row_same_3 ) + ); +`endif + +`ifdef MC_HAVE_CS4 +mc_obct u4( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_4 ), + .bank_clr( bank_clr_4 ), + .bank_clr_all( bank_clr_all_4 ), + .bank_open( bank_open_4 ), + .any_bank_open( any_bank_open_4 ), + .row_same( row_same_4 ) + ); +`else +mc_obct_dummy u4( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_4 ), + .bank_clr( bank_clr_4 ), + .bank_clr_all( bank_clr_all_4 ), + .bank_open( bank_open_4 ), + .any_bank_open( any_bank_open_4 ), + .row_same( row_same_4 ) + ); +`endif + +`ifdef MC_HAVE_CS5 +mc_obct u5( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_5 ), + .bank_clr( bank_clr_5 ), + .bank_clr_all( bank_clr_all_5 ), + .bank_open( bank_open_5 ), + .any_bank_open( any_bank_open_5 ), + .row_same( row_same_5 ) + ); +`else +mc_obct_dummy u5( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_5 ), + .bank_clr( bank_clr_5 ), + .bank_clr_all( bank_clr_all_5 ), + .bank_open( bank_open_5 ), + .any_bank_open( any_bank_open_5 ), + .row_same( row_same_5 ) + ); +`endif + +`ifdef MC_HAVE_CS6 +mc_obct u6( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_6 ), + .bank_clr( bank_clr_6 ), + .bank_clr_all( bank_clr_all_6 ), + .bank_open( bank_open_6 ), + .any_bank_open( any_bank_open_6 ), + .row_same( row_same_6 ) + ); +`else +mc_obct_dummy u6( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_6 ), + .bank_clr( bank_clr_6 ), + .bank_clr_all( bank_clr_all_6 ), + .bank_open( bank_open_6 ), + .any_bank_open( any_bank_open_6 ), + .row_same( row_same_6 ) + ); +`endif + +`ifdef MC_HAVE_CS7 +mc_obct u7( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_7 ), + .bank_clr( bank_clr_7 ), + .bank_clr_all( bank_clr_all_7 ), + .bank_open( bank_open_7 ), + .any_bank_open( any_bank_open_7 ), + .row_same( row_same_7 ) + ); +`else +mc_obct_dummy u7( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_7 ), + .bank_clr( bank_clr_7 ), + .bank_clr_all( bank_clr_all_7 ), + .bank_open( bank_open_7 ), + .any_bank_open( any_bank_open_7 ), + .row_same( row_same_7 ) + ); +`endif + +endmodule diff --git a/designs/encrypted_ip/des3_area/mc_rd_fifo.v b/designs/encrypted_ip/des3_area/mc_rd_fifo.v new file mode 100644 index 000000000..88e6fd578 --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_rd_fifo.v @@ -0,0 +1,126 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Read FIFO //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_rd_fifo.v,v 1.4 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.2 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.1.1.1 2001/05/13 09:39:44 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_rd_fifo(clk, rst, clr, din, we, dout, re); + +input clk, rst, clr; +input [35:0] din; +input we; +output [35:0] dout; +input re; + +reg [3:0] rd_adr, wr_adr; +reg [35:0] r0, r1, r2, r3; +reg [35:0] dout; + +always @(posedge clk or posedge rst) + if(rst) rd_adr <= #1 4'h1; + else + if(clr) rd_adr <= #1 4'h1; + else + if(re) rd_adr <= #1 {rd_adr[2:0], rd_adr[3]}; + +always @(posedge clk or posedge rst) + if(rst) wr_adr <= #1 4'h1; + else + if(clr) wr_adr <= #1 4'h1; + else + if(we) wr_adr <= #1 {wr_adr[2:0], wr_adr[3]}; + +always @(posedge clk) + if(we & wr_adr[0]) r0 <= #1 din; + +always @(posedge clk) + if(we & wr_adr[1]) r1 <= #1 din; + +always @(posedge clk) + if(we & wr_adr[2]) r2 <= #1 din; + +always @(posedge clk) + if(we & wr_adr[3]) r3 <= #1 din; + +always @(rd_adr or r0 or r1 or r2 or r3 or re or we or din) + case(rd_adr) // synopsys full_case parallel_case + 4'h1: dout = r0; + 4'h2: dout = r1; + 4'h4: dout = r2; + 4'h8: dout = r3; + endcase + +endmodule diff --git a/designs/encrypted_ip/des3_area/mc_refresh.v b/designs/encrypted_ip/des3_area/mc_refresh.v new file mode 100644 index 000000000..fecbcfb61 --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_refresh.v @@ -0,0 +1,206 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Refresh Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_refresh.v,v 1.4 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.2 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:47 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_refresh(clk, rst, + cs_need_rfr, ref_int, rfr_req, rfr_ack, + rfr_ps_val + ); + +input clk, rst; +input [7:0] cs_need_rfr; +input [2:0] ref_int; +output rfr_req; +input rfr_ack; +input [7:0] rfr_ps_val; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg rfr_en; +reg [7:0] ps_cnt; +wire ps_cnt_clr; +reg rfr_ce; +reg [7:0] rfr_cnt; +reg rfr_clr; +reg rfr_req; +reg rfr_early; + +/* +Refresh generation + +The prescaler generates a 0.48828 uS clock enable + +The refresh counter generates the following refresh rates: +(Actual values are about 0.63% below the desired values). +This is for a 200 Mhz WISHBONE Bus. +0.970 uS, +1.940 +3.880 +7.760 +15.520 +32.040 +62.080 +124.160 uS + +(desired values) +0.976 uS +1.953 +3.906 +7.812 +15.625 +31.250 +62.500 +125.000 uS +*/ + +//////////////////////////////////////////////////////////////////// +// +// Prescaler +// + +always @(posedge clk or posedge rst) + if(rst) rfr_en <= #1 1'b0; + else rfr_en <= #1 |cs_need_rfr; + +always @(posedge clk or posedge rst) + if(rst) ps_cnt <= #1 8'h0; + else + if(ps_cnt_clr) ps_cnt <= #1 8'h0; + else + if(rfr_en) ps_cnt <= #1 ps_cnt + 8'h1; + +assign ps_cnt_clr = (ps_cnt == rfr_ps_val) & (rfr_ps_val != 8'h0); + +always @(posedge clk or posedge rst) + if(rst) rfr_early <= #1 1'b0; + else rfr_early <= #1 (ps_cnt == rfr_ps_val); + +//////////////////////////////////////////////////////////////////// +// +// Refresh Counter +// + +always @(posedge clk or posedge rst) + if(rst) rfr_ce <= #1 1'b0; + else rfr_ce <= #1 ps_cnt_clr; + +always @(posedge clk or posedge rst) + if(rst) rfr_cnt <= #1 8'h0; + else + if(rfr_ack) rfr_cnt <= #1 8'h0; + else + if(rfr_ce) rfr_cnt <= #1 rfr_cnt + 8'h1; + +always @(posedge clk) + case(ref_int) // synopsys full_case parallel_case + 3'h0: rfr_clr <= #1 rfr_cnt[0] & rfr_early; + 3'h1: rfr_clr <= #1 &rfr_cnt[1:0] & rfr_early; + 3'h2: rfr_clr <= #1 &rfr_cnt[2:0] & rfr_early; + 3'h3: rfr_clr <= #1 &rfr_cnt[3:0] & rfr_early; + 3'h4: rfr_clr <= #1 &rfr_cnt[4:0] & rfr_early; + 3'h5: rfr_clr <= #1 &rfr_cnt[5:0] & rfr_early; + 3'h6: rfr_clr <= #1 &rfr_cnt[6:0] & rfr_early; + 3'h7: rfr_clr <= #1 &rfr_cnt[7:0] & rfr_early; + endcase + +always @(posedge clk or posedge rst) + if(rst) rfr_req <= #1 1'b0; + else + if(rfr_ack) rfr_req <= #1 1'b0; + else + if(rfr_clr) rfr_req <= #1 1'b1; + +endmodule diff --git a/designs/encrypted_ip/des3_area/mc_rf.v b/designs/encrypted_ip/des3_area/mc_rf.v new file mode 100644 index 000000000..340e7e278 --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_rf.v @@ -0,0 +1,832 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_rf.v,v 1.8 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.8 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.7 2001/12/21 05:09:29 rudi +// +// - Fixed combinatorial loops in synthesis +// - Fixed byte select bug +// +// Revision 1.6 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.5 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.4 2001/10/04 03:19:37 rudi +// +// Fixed Register reads +// Tightened up timing for register rd/wr +// +// Revision 1.3 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:42 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_rf(clk, rst, + + wb_data_i, rf_dout, wb_addr_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wp_err, + + csc, tms, poc, + sp_csc, sp_tms, cs, + mc_data_i, mc_sts, mc_vpen, fs, + + cs_le_d, cs_le, cs_need_rfr, ref_int, rfr_ps_val, init_req, + init_ack, lmr_req, lmr_ack, + spec_req_cs + ); + +input clk, rst; + +// -------------------------------------- +// WISHBONE INTERFACE + +// Slave Interface +input [31:0] wb_data_i; +output [31:0] rf_dout; +input [31:0] wb_addr_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wp_err; + +// -------------------------------------- +// Misc Signals +output [31:0] csc; +output [31:0] tms; +output [31:0] poc; +output [31:0] sp_csc; +output [31:0] sp_tms; +output [7:0] cs; + +input [31:0] mc_data_i; +input mc_sts; +output mc_vpen; +output fs; + +input cs_le_d; +input cs_le; + +output [7:0] cs_need_rfr; // Indicates which chip selects have SDRAM + // attached and need to be refreshed +output [2:0] ref_int; // Refresh Interval +output [7:0] rfr_ps_val; + +output init_req; +input init_ack; +output lmr_req; +input lmr_ack; + +output [7:0] spec_req_cs; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg wb_ack_o; + +reg [31:0] csc; +reg [31:0] tms; +reg [31:0] sp_csc; +reg [31:0] sp_tms; +reg [31:0] rf_dout; +reg [7:0] cs; + +reg rf_we; +wire [31:0] csr; +reg [10:0] csr_r; +reg [7:0] csr_r2; +reg [31:0] poc; + +wire [31:0] csc_mask; +reg [10:0] csc_mask_r; + +wire [31:0] csc0, tms0; +wire [31:0] csc1, tms1; +wire [31:0] csc2, tms2; +wire [31:0] csc3, tms3; +wire [31:0] csc4, tms4; +wire [31:0] csc5, tms5; +wire [31:0] csc6, tms6; +wire [31:0] csc7, tms7; + +wire cs0, cs1, cs2, cs3; +wire cs4, cs5, cs6, cs7; +wire wp_err0, wp_err1, wp_err2, wp_err3; +wire wp_err4, wp_err5, wp_err6, wp_err7; +reg wp_err; + +wire lmr_req7, lmr_req6, lmr_req5, lmr_req4; +wire lmr_req3, lmr_req2, lmr_req1, lmr_req0; +wire lmr_ack7, lmr_ack6, lmr_ack5, lmr_ack4; +wire lmr_ack3, lmr_ack2, lmr_ack1, lmr_ack0; + +wire init_req7, init_req6, init_req5, init_req4; +wire init_req3, init_req2, init_req1, init_req0; +wire init_ack7, init_ack6, init_ack5, init_ack4; +wire init_ack3, init_ack2, init_ack1, init_ack0; + +reg init_ack_r; +wire init_ack_fe; +reg lmr_ack_r; +wire lmr_ack_fe; +wire [7:0] spec_req_cs_t; +wire [7:0] spec_req_cs_d; +reg [7:0] spec_req_cs; +reg init_req, lmr_req; +reg sreq_cs_le; + +// Aliases +assign csr = {csr_r2, 8'h0, 5'h0, csr_r}; +assign csc_mask = {21'h0, csc_mask_r}; + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Register Read logic +// + +always @(wb_addr_i or csr or poc or csc_mask or csc0 or tms0 or csc1 or + tms1 or csc2 or tms2 or csc3 or tms3 or csc4 or tms4 or csc5 or + tms5 or csc6 or tms6 or csc7 or tms7) + case(wb_addr_i[6:2]) // synopsys full_case parallel_case + 5'h00: rf_dout <= #1 csr; + 5'h01: rf_dout <= #1 poc; + 5'h02: rf_dout <= #1 csc_mask; + + 5'h04: rf_dout <= #1 csc0; + 5'h05: rf_dout <= #1 tms0; + 5'h06: rf_dout <= #1 csc1; + 5'h07: rf_dout <= #1 tms1; + 5'h08: rf_dout <= #1 csc2; + 5'h09: rf_dout <= #1 tms2; + 5'h0a: rf_dout <= #1 csc3; + 5'h0b: rf_dout <= #1 tms3; + 5'h0c: rf_dout <= #1 csc4; + 5'h0d: rf_dout <= #1 tms4; + 5'h0e: rf_dout <= #1 csc5; + 5'h0f: rf_dout <= #1 tms5; + 5'h10: rf_dout <= #1 csc6; + 5'h11: rf_dout <= #1 tms6; + 5'h12: rf_dout <= #1 csc7; + 5'h13: rf_dout <= #1 tms7; + endcase + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Register Write logic +// + +reg [6:0] wb_addr_r; + +always @(posedge clk) + wb_addr_r <= #1 wb_addr_i[6:0]; + +always @(posedge clk or posedge rst) + if(rst) rf_we <= #1 1'b0; + else rf_we <= #1 `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i & !rf_we; + +always @(posedge clk or posedge rst) + if(rst) csr_r2 <= #1 8'h0; + else + if(rf_we & (wb_addr_r[6:2] == 5'h0) ) + csr_r2 <= #1 wb_data_i[31:24]; + +always @(posedge clk or posedge rst) + if(rst) csr_r[10:1] <= #1 10'h0; + else + if(rf_we & (wb_addr_r[6:2] == 5'h0) ) + csr_r[10:1] <= #1 wb_data_i[10:1]; + +always @(posedge clk) + csr_r[0] <= #1 mc_sts; + +assign mc_vpen = csr_r[1]; +assign fs = csr_r[2]; +assign rfr_ps_val = csr_r2[7:0]; + +always @(posedge clk or posedge rst) + if(rst) csc_mask_r <= #1 11'h7ff; + else + if(rf_we & (wb_addr_r[6:2] == 5'h2) ) + csc_mask_r <= #1 wb_data_i[10:0]; + +//////////////////////////////////////////////////////////////////// +// +// A kludge for cases where there is no clock during reset ... +// + +reg rst_r1, rst_r2, rst_r3; + +always @(posedge clk or posedge rst) + if(rst) rst_r1 <= #1 1'b1; + else rst_r1 <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) rst_r2 <= #1 1'b1; + else rst_r2 <= #1 rst_r1; + +always @(posedge clk or posedge rst) + if(rst) rst_r3 <= #1 1'b1; + else rst_r3 <= #1 rst_r2; + +always @(posedge clk) + if(rst_r3) poc <= #1 mc_data_i; + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Register Ack logic +// + +always @(posedge clk) + wb_ack_o <= #1 `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o; + +//////////////////////////////////////////////////////////////////// +// +// Select CSC and TMS Registers +// + +always @(posedge clk or posedge rst) + if(rst) cs <= #1 8'h0; + else + if(cs_le) cs <= #1 {cs7, cs6, cs5, cs4, cs3, cs2, cs1, cs0}; + +always @(posedge clk or posedge rst) + if(rst) wp_err <= #1 1'b0; + else + if(cs_le & wb_cyc_i & wb_stb_i) + wp_err <= #1 wp_err7 | wp_err6 | wp_err5 | wp_err4 | + wp_err3 | wp_err2 | wp_err1 | wp_err0; + else + if(!wb_cyc_i) wp_err <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) csc <= #1 32'h0; + else + if(cs_le_d & wb_cyc_i & wb_stb_i) + begin + if(cs0) csc <= #1 csc0; + else + if(cs1) csc <= #1 csc1; + else + if(cs2) csc <= #1 csc2; + else + if(cs3) csc <= #1 csc3; + else + if(cs4) csc <= #1 csc4; + else + if(cs5) csc <= #1 csc5; + else + if(cs6) csc <= #1 csc6; + else csc <= #1 csc7; + end + +always @(posedge clk or posedge rst) + if(rst) tms <= #1 32'hffff_ffff; + else + if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i) + begin + if(cs0) tms <= #1 tms0; + else + if(cs1) tms <= #1 tms1; + else + if(cs2) tms <= #1 tms2; + else + if(cs3) tms <= #1 tms3; + else + if(cs4) tms <= #1 tms4; + else + if(cs5) tms <= #1 tms5; + else + if(cs6) tms <= #1 tms6; + else tms <= #1 tms7; + end + +always @(posedge clk or posedge rst) + if(rst) sp_csc <= #1 32'h0; + else + if(cs_le_d & wb_cyc_i & wb_stb_i) + begin + if(spec_req_cs[0]) sp_csc <= #1 csc0; + else + if(spec_req_cs[1]) sp_csc <= #1 csc1; + else + if(spec_req_cs[2]) sp_csc <= #1 csc2; + else + if(spec_req_cs[3]) sp_csc <= #1 csc3; + else + if(spec_req_cs[4]) sp_csc <= #1 csc4; + else + if(spec_req_cs[5]) sp_csc <= #1 csc5; + else + if(spec_req_cs[6]) sp_csc <= #1 csc6; + else sp_csc <= #1 csc7; + end + +always @(posedge clk or posedge rst) + if(rst) sp_tms <= #1 32'hffff_ffff; + else + if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i) + begin + if(spec_req_cs[0]) sp_tms <= #1 tms0; + else + if(spec_req_cs[1]) sp_tms <= #1 tms1; + else + if(spec_req_cs[2]) sp_tms <= #1 tms2; + else + if(spec_req_cs[3]) sp_tms <= #1 tms3; + else + if(spec_req_cs[4]) sp_tms <= #1 tms4; + else + if(spec_req_cs[5]) sp_tms <= #1 tms5; + else + if(spec_req_cs[6]) sp_tms <= #1 tms6; + else sp_tms <= #1 tms7; + end + +assign cs_need_rfr[0] = csc0[0] & (csc0[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[1] = csc1[0] & (csc1[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[2] = csc2[0] & (csc2[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[3] = csc3[0] & (csc3[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[4] = csc4[0] & (csc4[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[5] = csc5[0] & (csc5[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[6] = csc6[0] & (csc6[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[7] = csc7[0] & (csc7[3:1] == `MC_MEM_TYPE_SDRAM); + +assign ref_int = csr_r[10:8]; + +//////////////////////////////////////////////////////////////////// +// +// Init & Lmr Logic +// + +// Init Ack falling edge detector +always @(posedge clk) + init_ack_r <= #1 init_ack; + +assign init_ack_fe = init_ack_r & !init_ack; + +// LMR Ack falling edge detector +always @(posedge clk) + lmr_ack_r <= #1 lmr_ack; + +assign lmr_ack_fe = lmr_ack_r & !lmr_ack; + +// Chip Select Output +always @(posedge clk or posedge rst) + if(rst) spec_req_cs <= #1 8'h0; + else + if(sreq_cs_le) spec_req_cs <= #1 spec_req_cs_d; + +always @(posedge clk or posedge rst) + if(rst) sreq_cs_le <= #1 1'b0; + else sreq_cs_le <= #1 (!init_req & !lmr_req) | lmr_ack_fe | init_ack_fe; + +// Make sure only one is serviced at a time +assign spec_req_cs_d[0] = spec_req_cs_t[0]; +assign spec_req_cs_d[1] = spec_req_cs_t[1] & !spec_req_cs_t[0]; +assign spec_req_cs_d[2] = spec_req_cs_t[2] & !( |spec_req_cs_t[1:0] ); +assign spec_req_cs_d[3] = spec_req_cs_t[3] & !( |spec_req_cs_t[2:0] ); +assign spec_req_cs_d[4] = spec_req_cs_t[4] & !( |spec_req_cs_t[3:0] ); +assign spec_req_cs_d[5] = spec_req_cs_t[5] & !( |spec_req_cs_t[4:0] ); +assign spec_req_cs_d[6] = spec_req_cs_t[6] & !( |spec_req_cs_t[5:0] ); +assign spec_req_cs_d[7] = spec_req_cs_t[7] & !( |spec_req_cs_t[6:0] ); + +// Request Tracking +always @(posedge clk or posedge rst) + if(rst) init_req <= #1 1'b0; + else init_req <= #1 init_req0 | init_req1 | init_req2 | init_req3 | + init_req4 | init_req5 | init_req6 | init_req7; + +always @(posedge clk or posedge rst) + if(rst) lmr_req <= #1 1'b0; + else lmr_req <= #1 lmr_req0 | lmr_req1 | lmr_req2 | lmr_req3 | + lmr_req4 | lmr_req5 | lmr_req6 | lmr_req7; + +assign spec_req_cs_t = !init_req ? // Load Mode Register Requests + {lmr_req7, lmr_req6, lmr_req5, lmr_req4, + lmr_req3, lmr_req2, lmr_req1, lmr_req0 } : + // Initialize SDRAM Requests + {init_req7, init_req6, init_req5, init_req4, + init_req3, init_req2, init_req1, init_req0 }; + +// Ack distribution +assign lmr_ack0 = spec_req_cs[0] & lmr_ack_fe; +assign lmr_ack1 = spec_req_cs[1] & lmr_ack_fe; +assign lmr_ack2 = spec_req_cs[2] & lmr_ack_fe; +assign lmr_ack3 = spec_req_cs[3] & lmr_ack_fe; +assign lmr_ack4 = spec_req_cs[4] & lmr_ack_fe; +assign lmr_ack5 = spec_req_cs[5] & lmr_ack_fe; +assign lmr_ack6 = spec_req_cs[6] & lmr_ack_fe; +assign lmr_ack7 = spec_req_cs[7] & lmr_ack_fe; + +assign init_ack0 = spec_req_cs[0] & init_ack_fe; +assign init_ack1 = spec_req_cs[1] & init_ack_fe; +assign init_ack2 = spec_req_cs[2] & init_ack_fe; +assign init_ack3 = spec_req_cs[3] & init_ack_fe; +assign init_ack4 = spec_req_cs[4] & init_ack_fe; +assign init_ack5 = spec_req_cs[5] & init_ack_fe; +assign init_ack6 = spec_req_cs[6] & init_ack_fe; +assign init_ack7 = spec_req_cs[7] & init_ack_fe; + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +mc_cs_rf #(3'h0) u0( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc0 ), + .tms( tms0 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs0 ), + .wp_err( wp_err0 ), + .lmr_req( lmr_req0 ), + .lmr_ack( lmr_ack0 ), + .init_req( init_req0 ), + .init_ack( init_ack0 ) + ); + +`ifdef MC_HAVE_CS1 +mc_cs_rf #(3'h1) u1( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc1 ), + .tms( tms1 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs1 ), + .wp_err( wp_err1 ), + .lmr_req( lmr_req1 ), + .lmr_ack( lmr_ack1 ), + .init_req( init_req1 ), + .init_ack( init_ack1 ) + ); +`else +mc_cs_rf_dummy #(3'h1) u1( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc1 ), + .tms( tms1 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs1 ), + .wp_err( wp_err1 ), + .lmr_req( lmr_req1 ), + .lmr_ack( lmr_ack1 ), + .init_req( init_req1 ), + .init_ack( init_ack1 ) + ); +`endif + +`ifdef MC_HAVE_CS2 +mc_cs_rf #(3'h2) u2( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc2 ), + .tms( tms2 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs2 ), + .wp_err( wp_err2 ), + .lmr_req( lmr_req2 ), + .lmr_ack( lmr_ack2 ), + .init_req( init_req2 ), + .init_ack( init_ack2 ) + ); +`else +mc_cs_rf_dummy #(3'h2) u2( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc2 ), + .tms( tms2 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs2 ), + .wp_err( wp_err2 ), + .lmr_req( lmr_req2 ), + .lmr_ack( lmr_ack2 ), + .init_req( init_req2 ), + .init_ack( init_ack2 ) + ); +`endif + +`ifdef MC_HAVE_CS3 +mc_cs_rf #(3'h3) u3( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc3 ), + .tms( tms3 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs3 ), + .wp_err( wp_err3 ), + .lmr_req( lmr_req3 ), + .lmr_ack( lmr_ack3 ), + .init_req( init_req3 ), + .init_ack( init_ack3 ) + ); +`else +mc_cs_rf_dummy #(3'h3) u3( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc3 ), + .tms( tms3 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs3 ), + .wp_err( wp_err3 ), + .lmr_req( lmr_req3 ), + .lmr_ack( lmr_ack3 ), + .init_req( init_req3 ), + .init_ack( init_ack3 ) + ); +`endif + +`ifdef MC_HAVE_CS4 +mc_cs_rf #(3'h4) u4( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc4 ), + .tms( tms4 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs4 ), + .wp_err( wp_err4 ), + .lmr_req( lmr_req4 ), + .lmr_ack( lmr_ack4 ), + .init_req( init_req4 ), + .init_ack( init_ack4 ) + ); +`else +mc_cs_rf_dummy #(3'h4) u4( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc4 ), + .tms( tms4 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs4 ), + .wp_err( wp_err4 ), + .lmr_req( lmr_req4 ), + .lmr_ack( lmr_ack4 ), + .init_req( init_req4 ), + .init_ack( init_ack4 ) + ); +`endif + +`ifdef MC_HAVE_CS5 +mc_cs_rf #(3'h5) u5( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc5 ), + .tms( tms5 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs5 ), + .wp_err( wp_err5 ), + .lmr_req( lmr_req5 ), + .lmr_ack( lmr_ack5 ), + .init_req( init_req5 ), + .init_ack( init_ack5 ) + ); +`else +mc_cs_rf_dummy #(3'h5) u5( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc5 ), + .tms( tms5 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs5 ), + .wp_err( wp_err5 ), + .lmr_req( lmr_req5 ), + .lmr_ack( lmr_ack5 ), + .init_req( init_req5 ), + .init_ack( init_ack5 ) + ); +`endif + +`ifdef MC_HAVE_CS6 +mc_cs_rf #(3'h6) u6( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc6 ), + .tms( tms6 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs6 ), + .wp_err( wp_err6 ), + .lmr_req( lmr_req6 ), + .lmr_ack( lmr_ack6 ), + .init_req( init_req6 ), + .init_ack( init_ack6 ) + ); +`else +mc_cs_rf_dummy #(3'h6) u6( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc6 ), + .tms( tms6 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs6 ), + .wp_err( wp_err6 ), + .lmr_req( lmr_req6 ), + .lmr_ack( lmr_ack6 ), + .init_req( init_req6 ), + .init_ack( init_ack6 ) + ); +`endif + +`ifdef MC_HAVE_CS7 +mc_cs_rf #(3'h7) u7( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc7 ), + .tms( tms7 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs7 ), + .wp_err( wp_err7 ), + .lmr_req( lmr_req7 ), + .lmr_ack( lmr_ack7 ), + .init_req( init_req7 ), + .init_ack( init_ack7 ) + ); +`else +mc_cs_rf_dummy #(3'h7) u7( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc7 ), + .tms( tms7 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs7 ), + .wp_err( wp_err7 ), + .lmr_req( lmr_req7 ), + .lmr_ack( lmr_ack7 ), + .init_req( init_req7 ), + .init_ack( init_ack7 ) + ); +`endif + +endmodule + diff --git a/designs/encrypted_ip/des3_area/mc_timing.v b/designs/encrypted_ip/des3_area/mc_timing.v new file mode 100644 index 000000000..2bbaaa641 --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_timing.v @@ -0,0 +1,1731 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Main Timing Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_timing.v,v 1.8 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.8 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.7 2001/12/21 05:09:30 rudi +// +// - Fixed combinatorial loops in synthesis +// - Fixed byte select bug +// +// Revision 1.6 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.5 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.4 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.3 2001/09/02 02:28:28 rudi +// +// Many fixes for minor bugs that showed up in gate level simulations. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.4 2001/06/14 01:57:37 rudi +// +// +// Fixed a potential bug in a corner case situation where the TMS register +// does not propegate properly during initialisation. +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:44 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_timing(clk, rst, + + // Wishbone Interface + wb_cyc_i, wb_stb_i, wb_we_i, + wb_read_go, wb_write_go, wb_first, wb_wait, mem_ack, + err, + + // Suspend/Resume Interface + susp_req, resume_req, suspended, susp_sel, + + // Memory Interface + mc_clk, data_oe, oe_, we_, cas_, ras_, cke_, + cs_en, wb_cycle, wr_cycle, + mc_br, mc_bg, mc_adsc, mc_adv, + mc_c_oe, mc_ack, + not_mem_cyc, + + // Register File Interface + csc, tms, cs, lmr_req, lmr_ack, cs_le_d, cs_le, + + // Address Select Signals + cmd_a10, row_sel, next_adr, page_size, + + // OBCT Signals + bank_set, bank_clr, bank_clr_all, bank_open, any_bank_open, row_same, + + // Data path Controller Signals + dv, pack_le0, pack_le1, pack_le2, par_err, + + // Refresh Counter Signals + rfr_req, rfr_ack, + + // Initialize Request & Ack + init_req, init_ack + ); + +input clk; +input rst; + +// Wishbone Interface +input wb_cyc_i, wb_stb_i, wb_we_i; +input wb_read_go; +input wb_write_go; +input wb_first; +input wb_wait; +output mem_ack; +output err; + +// Suspend/Resume Interface +input susp_req; +input resume_req; +output suspended; +output susp_sel; + +// Memory Interface +input mc_clk; +output data_oe; +output oe_; +output we_; +output cas_; +output ras_; +output cke_; +output cs_en; +output wb_cycle; +output wr_cycle; +input mc_br; +output mc_bg; +output mc_adsc; +output mc_adv; +output mc_c_oe; +input mc_ack; +input not_mem_cyc; + +// Register File Interface +input [31:0] csc; +input [31:0] tms; +input [7:0] cs; +input lmr_req; +output lmr_ack; +output cs_le; +output cs_le_d; + +// Address Select Signals +input [10:0] page_size; +output cmd_a10; +output row_sel; +output next_adr; + +// OBCT Signals +output bank_set; +output bank_clr; +output bank_clr_all; +input bank_open; +input any_bank_open; +input row_same; + +// Data path Controller Signals +output dv; +output pack_le0, pack_le1, pack_le2; // Pack Latch Enable +input par_err; + +// Refresh Counter Signals +input rfr_req; +output rfr_ack; + +// Initialize Request & Ack +input init_req; +output init_ack; + +//////////////////////////////////////////////////////////////////// +// +// Defines & Parameters +// + +// Number of states: 66 +parameter [65:0] // synopsys enum state +// 6666666555555555544444444443333333333222222222211111111110000000000 +// 6543210987654321098765432109876543210987654321098765432109876543210 +POR = 66'b000000000000000000000000000000000000000000000000000000000000000001, +IDLE = 66'b000000000000000000000000000000000000000000000000000000000000000010, +IDLE_T = 66'b000000000000000000000000000000000000000000000000000000000000000100, +IDLE_T2 = 66'b000000000000000000000000000000000000000000000000000000000000001000, +PRECHARGE = 66'b000000000000000000000000000000000000000000000000000000000000010000, +PRECHARGE_W = 66'b000000000000000000000000000000000000000000000000000000000000100000, +ACTIVATE = 66'b000000000000000000000000000000000000000000000000000000000001000000, +ACTIVATE_W = 66'b000000000000000000000000000000000000000000000000000000000010000000, +SD_RD_WR = 66'b000000000000000000000000000000000000000000000000000000000100000000, +SD_RD = 66'b000000000000000000000000000000000000000000000000000000001000000000, +SD_RD_W = 66'b000000000000000000000000000000000000000000000000000000010000000000, +SD_RD_LOOP = 66'b000000000000000000000000000000000000000000000000000000100000000000, +SD_RD_W2 = 66'b000000000000000000000000000000000000000000000000000001000000000000, +SD_WR = 66'b000000000000000000000000000000000000000000000000000010000000000000, +SD_WR_W = 66'b000000000000000000000000000000000000000000000000000100000000000000, +BT = 66'b000000000000000000000000000000000000000000000000001000000000000000, +BT_W = 66'b000000000000000000000000000000000000000000000000010000000000000000, +REFR = 66'b000000000000000000000000000000000000000000000000100000000000000000, +LMR0 = 66'b000000000000000000000000000000000000000000000001000000000000000000, +LMR1 = 66'b000000000000000000000000000000000000000000000010000000000000000000, +LMR2 = 66'b000000000000000000000000000000000000000000000100000000000000000000, +// 6666666555555555544444444443333333333222222222211111111110000000000 +// 6543210987654321098765432109876543210987654321098765432109876543210 +INIT0 = 66'b000000000000000000000000000000000000000000001000000000000000000000, +INIT = 66'b000000000000000000000000000000000000000000010000000000000000000000, +INIT_W = 66'b000000000000000000000000000000000000000000100000000000000000000000, +INIT_REFR1 = 66'b000000000000000000000000000000000000000001000000000000000000000000, +INIT_REFR1_W = 66'b000000000000000000000000000000000000000010000000000000000000000000, +// 6666666555555555544444444443333333333222222222211111111110000000000 +// 6543210987654321098765432109876543210987654321098765432109876543210 +INIT_LMR = 66'b000000000000000000000000000000000000000100000000000000000000000000, +SUSP1 = 66'b000000000000000000000000000000000000001000000000000000000000000000, +SUSP2 = 66'b000000000000000000000000000000000000010000000000000000000000000000, +SUSP3 = 66'b000000000000000000000000000000000000100000000000000000000000000000, +SUSP4 = 66'b000000000000000000000000000000000001000000000000000000000000000000, +RESUME1 = 66'b000000000000000000000000000000000010000000000000000000000000000000, +RESUME2 = 66'b000000000000000000000000000000000100000000000000000000000000000000, +BG0 = 66'b000000000000000000000000000000001000000000000000000000000000000000, +BG1 = 66'b000000000000000000000000000000010000000000000000000000000000000000, +BG2 = 66'b000000000000000000000000000000100000000000000000000000000000000000, +ACS_RD = 66'b000000000000000000000000000001000000000000000000000000000000000000, +ACS_RD1 = 66'b000000000000000000000000000010000000000000000000000000000000000000, +ACS_RD2A = 66'b000000000000000000000000000100000000000000000000000000000000000000, +ACS_RD2 = 66'b000000000000000000000000001000000000000000000000000000000000000000, +ACS_RD3 = 66'b000000000000000000000000010000000000000000000000000000000000000000, +ACS_RD_8_1 = 66'b000000000000000000000000100000000000000000000000000000000000000000, +ACS_RD_8_2 = 66'b000000000000000000000001000000000000000000000000000000000000000000, +ACS_RD_8_3 = 66'b000000000000000000000010000000000000000000000000000000000000000000, +ACS_RD_8_4 = 66'b000000000000000000000100000000000000000000000000000000000000000000, +ACS_RD_8_5 = 66'b000000000000000000001000000000000000000000000000000000000000000000, +ACS_RD_8_6 = 66'b000000000000000000010000000000000000000000000000000000000000000000, +ACS_WR = 66'b000000000000000000100000000000000000000000000000000000000000000000, +ACS_WR1 = 66'b000000000000000001000000000000000000000000000000000000000000000000, +ACS_WR2 = 66'b000000000000000010000000000000000000000000000000000000000000000000, +ACS_WR3 = 66'b000000000000000100000000000000000000000000000000000000000000000000, +ACS_WR4 = 66'b000000000000001000000000000000000000000000000000000000000000000000, +SRAM_RD = 66'b000000000000010000000000000000000000000000000000000000000000000000, +SRAM_RD0 = 66'b000000000000100000000000000000000000000000000000000000000000000000, +SRAM_RD1 = 66'b000000000001000000000000000000000000000000000000000000000000000000, +SRAM_RD2 = 66'b000000000010000000000000000000000000000000000000000000000000000000, +SRAM_RD3 = 66'b000000000100000000000000000000000000000000000000000000000000000000, +SRAM_RD4 = 66'b000000001000000000000000000000000000000000000000000000000000000000, +SRAM_WR = 66'b000000010000000000000000000000000000000000000000000000000000000000, +SRAM_WR0 = 66'b000000100000000000000000000000000000000000000000000000000000000000, +SCS_RD = 66'b000001000000000000000000000000000000000000000000000000000000000000, +SCS_RD1 = 66'b000010000000000000000000000000000000000000000000000000000000000000, +SCS_RD2 = 66'b000100000000000000000000000000000000000000000000000000000000000000, +SCS_WR = 66'b001000000000000000000000000000000000000000000000000000000000000000, +SCS_WR1 = 66'b010000000000000000000000000000000000000000000000000000000000000000, +SCS_ERR = 66'b100000000000000000000000000000000000000000000000000000000000000000; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg [65:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg mc_bg; + +wire [2:0] mem_type; +wire [1:0] bus_width; +wire kro; + +wire cs_a; +reg [3:0] cmd; + +wire mem_ack; +wire mem_ack_s; +reg mem_ack_d; +reg err_d; +wire err; +reg cmd_a10; +reg lmr_ack; +reg lmr_ack_d; +reg row_sel; +reg oe_; +reg oe_d; +reg data_oe; +reg data_oe_d; +reg cke_d; +reg cke_; +reg init_ack; +reg dv; +reg rfr_ack_d; +reg mc_adsc; +reg mc_adv; + +reg bank_set; +reg bank_clr; +reg bank_clr_all; + +reg wr_set, wr_clr; +reg wr_cycle; + +reg cmd_asserted; +reg cmd_asserted2; + +reg [10:0] burst_val; +reg [10:0] burst_cnt; +wire burst_act; +reg burst_act_rd; +wire single_write; + +reg cs_le_d; +reg cs_le; +reg cs_le_r; + +reg susp_req_r; +reg resume_req_r; +reg suspended; +reg suspended_d; +reg susp_sel_set, susp_sel_clr, susp_sel_r; + +reg [3:0] cmd_del; +reg [3:0] cmd_r; +reg data_oe_r; +reg data_oe_r2; +reg cke_r; +reg cke_rd; +reg cke_o_del; +reg cke_o_r1; +reg cke_o_r2; +reg wb_cycle_set, wb_cycle; +reg [3:0] ack_cnt; +wire ack_cnt_is_0; +reg cnt, cnt_next; +reg [7:0] timer; +reg tmr_ld_trp, tmr_ld_trcd, tmr_ld_tcl, tmr_ld_trfc; +reg tmr_ld_twr, tmr_ld_txsr; +reg tmr2_ld_tscsto; +reg tmr_ld_trdv; +reg tmr_ld_trdz; +reg tmr_ld_twr2; +wire timer_is_zero; +reg tmr_done; +reg tmr2_ld_trdv, tmr2_ld_trdz; +reg tmr2_ld_twpw, tmr2_ld_twd, tmr2_ld_twwd; +reg tmr2_ld_tsrdv; +reg [8:0] timer2; +reg tmr2_done; +wire timer2_is_zero; +reg [3:0] ir_cnt; +reg ir_cnt_ld; +reg ir_cnt_dec; +reg ir_cnt_done; +reg rfr_ack_r; +reg burst_cnt_ld; +reg burst_fp; +reg wb_wait_r, wb_wait_r2; +reg lookup_ready1, lookup_ready2; +reg burst_cnt_ld_4; +reg dv_r; +reg mc_adv_r1, mc_adv_r; + +reg next_adr; +reg pack_le0, pack_le1, pack_le2; +reg pack_le0_d, pack_le1_d, pack_le2_d; +wire bw8, bw16; + +reg mc_c_oe_d; +reg mc_c_oe; + +reg mc_le; +reg mem_ack_r; + +reg rsts, rsts1; +reg no_wb_cycle; + +wire bc_dec; +reg ap_en; // Auto Precharge Enable +reg cmd_a10_r; +reg wb_stb_first; +reg tmr_ld_tavav; + +//////////////////////////////////////////////////////////////////// +// +// Aliases +// +assign mem_type = csc[3:1]; +assign bus_width = csc[5:4]; +assign kro = csc[10]; +assign single_write = tms[9] | (tms[2:0] == 3'h0); + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// +reg cs_le_r1; + +always @(posedge clk) + lmr_ack <= #1 lmr_ack_d; + +assign rfr_ack = rfr_ack_r; + +always @(posedge clk) + cs_le_r <= #1 cs_le_r1; + +always @(posedge clk) + cs_le_r1 <= #1 cs_le; + +always @(posedge clk) + cs_le <= #1 cs_le_d; + +always @(posedge mc_clk or posedge rst) + if(rst) rsts1 <= #1 1'b1; + else rsts1 <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) rsts <= #1 1'b1; + else rsts <= #1 rsts1; + +// Control Signals Output Enable +always @(posedge clk or posedge rst) + if(rst) mc_c_oe <= #1 1'b0; + else mc_c_oe <= #1 mc_c_oe_d; + +always @(posedge clk or posedge rsts) + if(rsts) mc_le <= #1 1'b0; + else mc_le <= #1 ~mc_le; + +always @(posedge clk) + pack_le0 <= #1 pack_le0_d; + +always @(posedge clk) + pack_le1 <= #1 pack_le1_d; + +always @(posedge clk) + pack_le2 <= #1 pack_le2_d; + +always @(posedge clk or posedge rst) + if(rst) mc_adv_r1 <= #1 1'b0; + else + if(!mc_le) mc_adv_r1 <= #1 mc_adv; + +always @(posedge clk or posedge rst) + if(rst) mc_adv_r <= #1 1'b0; + else + if(!mc_le) mc_adv_r <= #1 mc_adv_r1; + +// Bus Width decoder +assign bw8 = (bus_width == `MC_BW_8); +assign bw16 = (bus_width == `MC_BW_16); + +// Any Chip Select +assign cs_a = |cs; + +// Memory to Wishbone Ack +assign mem_ack = (mem_ack_d | mem_ack_s) & (wb_read_go | wb_write_go); + +always @(posedge clk or posedge rst) + if(rst) mem_ack_r <= #1 1'b0; + else mem_ack_r <= #1 mem_ack; + +assign err = err_d; + +// SDRAM Command, either delayed (for writes) or straight through +always @(posedge clk or posedge rst) + if(rst) cmd_r <= #1 `MC_CMD_NOP; + else cmd_r <= #1 cmd; + +always @(posedge clk or posedge rst) + if(rst) cmd_del <= #1 `MC_CMD_NOP; + else cmd_del <= #1 cmd_r; + +assign {cs_en, ras_, cas_, we_} = wr_cycle ? cmd_del : cmd; + +// Track Timing of Asserting a command +always @(posedge clk or posedge rst) + if(rst) cmd_asserted <= #1 1'b0; + else + if(!mc_le) cmd_asserted <= #1 cmd[3]; + +always @(posedge clk or posedge rst) + if(rst) cmd_asserted2 <= #1 1'b0; + else + if(!mc_le) cmd_asserted2 <= #1 cmd_asserted; + +// Output Enable +always @(posedge clk or posedge rst) + if(rst) oe_ <= #1 1'b1; + else oe_ <= #1 ~oe_d; + +// Memory Bus Data lines Output Enable +always @(posedge clk or posedge rst) + if(rst) data_oe_r <= #1 1'b0; + else data_oe_r <= #1 data_oe_d; + +always @(posedge clk or posedge rst) + if(rst) data_oe_r2 <= #1 1'b0; + else data_oe_r2 <= #1 data_oe_r; + +always @(posedge clk or posedge rst) + if(rst) data_oe <= #1 1'b0; + else data_oe <= #1 wr_cycle ? data_oe_r2 : data_oe_d; + +// Clock Enable +always @(posedge clk) + cke_r <= #1 cke_d; + +always @(posedge clk) + cke_ <= #1 cke_r & cke_rd; + +// CKE output delay line to time DV for reads +always @(posedge clk) + cke_o_r1 <= #1 cke_; + +always @(posedge clk) + cke_o_r2 <= #1 cke_o_r1; + +always @(posedge clk) + cke_o_del <= #1 cke_o_r2; + +// Delayed version of the wb_wait input +always @(posedge clk) + wb_wait_r2 <= #1 wb_wait; + +always @(posedge clk) + wb_wait_r <= #1 wb_wait_r2; + +// Indicates when the row_same and bank_open lookups are done +reg lookup_ready1a; + +always @(posedge clk or posedge rst) + if(rst) lookup_ready1 <= #1 1'b0; + else lookup_ready1 <= #1 cs_le & wb_cyc_i & wb_stb_i; + +always @(posedge clk or posedge rst) + if(rst) lookup_ready2 <= #1 1'b0; + else lookup_ready2 <= #1 lookup_ready1 & wb_cyc_i & wb_stb_i; + +// Keep Track if it is a SDRAM write cycle +always @(posedge clk or posedge rst) + if(rst) wr_cycle <= #1 1'b0; + else + if(wr_set) wr_cycle <= #1 1'b1; + else + if(wr_clr) wr_cycle <= #1 1'b0; + +// Track when a cycle is *still* active +always @(posedge clk or posedge rst) + if(rst) wb_cycle <= #1 1'b0; + else + if(wb_cycle_set) wb_cycle <= #1 1'b1; + else + if(!wb_cyc_i | not_mem_cyc) wb_cycle <= #1 1'b0; + +// Thses two signals are used to signal that no wishbone cycle is in +// progress. Need to register them to avoid a very long combinatorial +// path .... +always @(posedge clk or posedge rst) + if(rst) no_wb_cycle <= #1 1'b0; + else no_wb_cycle <= #1 !wb_read_go & !wb_write_go; + +// Track ack's for read cycles +always @(posedge clk or posedge rst) + if(rst) ack_cnt <= #1 4'h0; + else + if(no_wb_cycle) ack_cnt <= #1 4'h0; + else + if(dv & !mem_ack_s) ack_cnt <= #1 ack_cnt + 4'h1; + else + if(!dv & mem_ack_s) ack_cnt <= #1 ack_cnt - 4'h1; + +assign ack_cnt_is_0 = (ack_cnt==4'h0); + +assign mem_ack_s = (ack_cnt != 4'h0) & !wb_wait & !mem_ack_r & wb_read_go & !(wb_we_i & wb_stb_i); + +// Internal Cycle Tracker +always @(posedge clk) + cnt <= #1 cnt_next; + +// Suspend/resume Logic +always @(posedge clk or posedge rst) + if(rst) susp_req_r <= #1 1'b0; + else susp_req_r <= #1 susp_req; + +always @(posedge clk or posedge rst) + if(rst) resume_req_r <= #1 1'b0; + else resume_req_r <= #1 resume_req; + +always @(posedge clk or posedge rst) + if(rst) suspended <= #1 1'b0; + else suspended <= #1 suspended_d; + +always @(posedge clk or posedge rst) + if(rst) rfr_ack_r <= #1 1'b0; + else rfr_ack_r <= #1 rfr_ack_d; + +// Suspend Select Logic +assign susp_sel = susp_sel_r; + +always @(posedge clk or posedge rst) + if(rst) susp_sel_r <= #1 1'b0; + else + if(susp_sel_set) susp_sel_r <= #1 1'b1; + else + if(susp_sel_clr) susp_sel_r <= #1 1'b0; + +//////////////////////////////////////////////////////////////////// +// +// Timing Logic +// +wire [3:0] twrp; +wire twd_is_zero; +wire [31:0] tms_x; + +// FIX_ME +// Hard wire worst case or make it programmable ??? +assign tms_x = (rfr_ack_d | rfr_ack_r | susp_sel | !mc_c_oe) ? 32'hffff_ffff : tms; + +always @(posedge clk) + if(tmr2_ld_tscsto) timer2 <= #1 tms_x[24:16]; + else + if(tmr2_ld_tsrdv) timer2 <= #1 9'd4; // SSRAM RD->1st DATA VALID + else + if(tmr2_ld_twpw) timer2 <= #1 { 5'h0, tms_x[15:12]}; + else + if(tmr2_ld_twd) timer2 <= #1 { 4'h0, tms_x[19:16],1'b0}; + else + if(tmr2_ld_twwd) timer2 <= #1 { 3'h0, tms_x[25:20]}; + else + if(tmr2_ld_trdz) timer2 <= #1 { 4'h0, tms_x[11:8], 1'b1}; + else + if(tmr2_ld_trdv) timer2 <= #1 { tms_x[7:0], 1'b1}; + else + if(!timer2_is_zero) timer2 <= #1 timer2 - 9'b1; + +assign twd_is_zero = (tms_x[19:16] == 4'h0); + +assign timer2_is_zero = (timer2 == 9'h0); + +always @(posedge clk or posedge rst) + if(rst) tmr2_done <= #1 1'b0; + else tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz & + !tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto; + +assign twrp = {2'h0,tms_x[16:15]} + tms_x[23:20]; + +// SDRAM Memories timing tracker +always @(posedge clk or posedge rst) +`ifdef MC_POR_DELAY + if(rst) timer <= #1 `MC_POR_DELAY_VAL ; + else +`endif + if(tmr_ld_twr2) timer <= #1 { 4'h0, tms_x[15:12] }; + else + if(tmr_ld_trdz) timer <= #1 { 4'h0, tms_x[11:8] }; + else + if(tmr_ld_trdv) timer <= #1 tms_x[7:0]; + else + if(tmr_ld_twr) timer <= #1 { 4'h0, twrp}; + else + if(tmr_ld_trp) timer <= #1 { 4'h0, tms_x[23:20]}; + else + if(tmr_ld_trcd) timer <= #1 { 5'h0, tms_x[19:17]}; + else + if(tmr_ld_tcl) timer <= #1 { 6'h0, tms_x[05:04]}; + else + if(tmr_ld_trfc) timer <= #1 { 4'h0, tms_x[27:24]}; + else + if(tmr_ld_tavav) timer <= #1 8'h3; + else + if(tmr_ld_txsr) timer <= #1 8'h7; + else + if(!timer_is_zero & !mc_le) timer <= #1 timer - 8'b1; + +assign timer_is_zero = (timer == 8'h0); + +always @(posedge clk or posedge rst) + if(rst) tmr_done <= #1 1'b0; + else tmr_done <= #1 timer_is_zero; + +// Init Refresh Cycles Counter +always @(posedge clk) + if(ir_cnt_ld) ir_cnt <= #1 `MC_INIT_RFRC_CNT; + else + if(ir_cnt_dec) ir_cnt <= #1 ir_cnt - 4'b1; + +always @(posedge clk) + ir_cnt_done <= #1 (ir_cnt == 4'h0); + +// Burst Counter +always @(tms_x or page_size) + case(tms_x[2:0]) // synopsys full_case parallel_case + 3'h0: burst_val = 11'h1; + 3'h1: burst_val = 11'h2; + 3'h2: burst_val = 11'h4; + 3'h3: burst_val = 11'h8; + 3'h7: burst_val = page_size; + endcase + +assign bc_dec = wr_cycle ? mem_ack_d : dv; + +always @(posedge clk) + if(burst_cnt_ld_4) burst_cnt <= #1 11'h4; // for SSRAM only + else + if(burst_cnt_ld) burst_cnt <= #1 burst_val; + else + if(bc_dec) burst_cnt <= #1 burst_cnt - 11'h1; + +always @(posedge clk or posedge rst) + if(rst) burst_fp <= #1 1'b0; + else + if(burst_cnt_ld) burst_fp <= #1 (tms_x[2:0] == 3'h7); + +// Auto Precharge Enable +always @(posedge clk or posedge rst) + if(rst) ap_en <= #1 1'b0; + else + if(burst_cnt_ld) ap_en <= #1 (tms_x[2:0] == 3'h0) & !kro; + +assign burst_act = |burst_cnt & ( |tms_x[2:0] ); + +always @(posedge clk) + burst_act_rd <= #1 |burst_cnt; + +always @(posedge clk or posedge rst) + if(rst) dv_r <= #1 1'b0; + else dv_r <= #1 dv; + +always @(posedge clk) // Auto Precharge Holding Register + cmd_a10_r <= #1 cmd_a10; + +//////////////////////////////////////////////////////////////////// +// +// Main State Machine +// +reg wb_write_go_r; + +always @(posedge clk) + wb_write_go_r <= #1 wb_write_go; + +always @(posedge clk or posedge rst) + if(rst) wb_stb_first <= #1 1'b0; + else + if(mem_ack) wb_stb_first <= #1 1'b0; + else + if(wb_first & wb_stb_i) wb_stb_first <= #1 1'b1; + +always @(posedge clk or posedge rst) +`ifdef MC_POR_DELAY + if(rst) state <= #1 POR; +`else + if(rst) state <= #1 IDLE; +`endif + else state <= #1 next_state; + +always @(state or cs_a or cs_le or cs_le_r or + twd_is_zero or wb_stb_i or wb_write_go_r or + wb_first or wb_read_go or wb_write_go or wb_wait or mem_ack_r or wb_we_i or + ack_cnt_is_0 or wb_wait_r or cnt or wb_cycle or wr_cycle or + mem_type or kro or lookup_ready2 or row_same or cmd_a10_r or + bank_open or single_write or + cmd_asserted or tmr_done or tmr2_done or ir_cnt_done or cmd_asserted2 or + burst_act or burst_act_rd or burst_fp or cke_ or cke_r or cke_o_del or + rfr_req or lmr_req or init_req or rfr_ack_r or susp_req_r or resume_req_r or + mc_br or bw8 or bw16 or dv_r or mc_adv_r or mc_ack or wb_stb_first or ap_en + ) + begin + next_state = state; // Default keep current state + cnt_next = 1'b0; + + cmd = `MC_CMD_NOP; + cmd_a10 = ap_en; + oe_d = 1'b0; + data_oe_d = 1'b0; + cke_d = 1'b1; + cke_rd = 1'b1; + mc_adsc = 1'b0; + mc_adv = 1'b0; + + bank_set = 1'b0; + bank_clr = 1'b0; + bank_clr_all = 1'b0; + + burst_cnt_ld = 1'b0; + burst_cnt_ld_4 = 1'b0; + tmr_ld_trp = 1'b0; + tmr_ld_trcd = 1'b0; + tmr_ld_tcl = 1'b0; + tmr_ld_trfc = 1'b0; + tmr_ld_twr = 1'b0; + tmr_ld_txsr = 1'b0; + tmr_ld_trdv = 1'b0; + tmr_ld_trdz = 1'b0; + tmr_ld_twr2 = 1'b0; + tmr_ld_tavav = 1'b0; + + tmr2_ld_trdv = 1'b0; + tmr2_ld_trdz = 1'b0; + + tmr2_ld_twpw = 1'b0; + tmr2_ld_twd = 1'b0; + tmr2_ld_twwd = 1'b0; + tmr2_ld_tsrdv = 1'b0; + tmr2_ld_tscsto = 1'b0; + + mem_ack_d = 1'b0; + err_d = 1'b0; + rfr_ack_d = 1'b0; + lmr_ack_d = 1'b0; + init_ack = 1'b0; + + ir_cnt_dec = 1'b0; + ir_cnt_ld = 1'b0; + + row_sel = 1'b0; + cs_le_d = 1'b0; + wr_clr = 1'b0; + wr_set = 1'b0; + wb_cycle_set = 1'b0; + dv = 1'b0; + + suspended_d = 1'b0; + susp_sel_set = 1'b0; + susp_sel_clr = 1'b0; + mc_bg = 1'b0; + + next_adr = 1'b0; + pack_le0_d = 1'b0; + pack_le1_d = 1'b0; + pack_le2_d = 1'b0; + + mc_c_oe_d = 1'b1; + + case(state) // synopsys full_case parallel_case +`ifdef MC_POR_DELAY + POR: + begin + if(tmr_done) next_state = IDLE; + end +`endif + IDLE: + begin + //cs_le_d = wb_stb_first | lmr_req; + cs_le_d = wb_stb_first; + + burst_cnt_ld = 1'b1; + wr_clr = 1'b1; + + if(mem_type == `MC_MEM_TYPE_SCS) tmr2_ld_tscsto = 1'b1; + if(mem_type == `MC_MEM_TYPE_SRAM) tmr2_ld_tsrdv = 1'b1; + + if(rfr_req) + begin + rfr_ack_d = 1'b1; + next_state = PRECHARGE; + end + else + if(init_req) + begin + cs_le_d = 1'b1; + next_state = INIT0; + end + else + if(lmr_req & lookup_ready2) + begin + lmr_ack_d = 1'b1; + cs_le_d = 1'b1; + next_state = LMR0; + end + else + if(susp_req_r & !wb_cycle) + begin + cs_le_d = 1'b1; + susp_sel_set = 1'b1; + next_state = SUSP1; + end + else + if(cs_a & (wb_read_go | wb_write_go) & lookup_ready2) + begin + wb_cycle_set = 1'b1; + case(mem_type) // synopsys full_case parallel_case + `MC_MEM_TYPE_SDRAM: // SDRAM + if((lookup_ready2) & !wb_wait) + begin + if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1; + if(kro & bank_open & row_same) next_state = SD_RD_WR; + else + if(kro & bank_open) next_state = PRECHARGE; + else next_state = ACTIVATE; + end + `MC_MEM_TYPE_ACS: + begin // Async Chip Select + if(!wb_wait) + begin + cs_le_d = 1'b1; + if(wb_write_go) + begin + data_oe_d = 1'b1; + next_state = ACS_WR; + end + else next_state = ACS_RD; + end + end + `MC_MEM_TYPE_SCS: + begin // Sync Chip Select + if(!wb_wait) + begin + cs_le_d = 1'b1; + if(wb_write_go) + begin + cmd = `MC_CMD_XWR; + data_oe_d = 1'b1; + tmr_ld_twr2 = 1'b1; + next_state = SCS_WR; + end + else + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr_ld_trdv = 1'b1; + next_state = SCS_RD; + end + end + end + `MC_MEM_TYPE_SRAM: + begin // SRAM + if(!wb_wait) + begin + cs_le_d = 1'b1; + if(wb_write_go) + begin + data_oe_d = 1'b1; + mem_ack_d = 1'b1; + next_state = SRAM_WR; + end + else + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + mc_adsc = 1'b1; + next_state = SRAM_RD; + end + end + end + endcase + end + else + if(mc_br) + begin + if(!cmd_asserted2) + begin + next_state = BG0; + mc_c_oe_d = 1'b0; + end + end + end + + IDLE_T: + begin + cmd_a10 = cmd_a10_r; // Hold Auto Precharge 'til cycle finishes + if(tmr_done & wb_cycle & !wb_wait) cs_le_d = 1'b1; + if(tmr_done) next_state = IDLE; + end + + IDLE_T2: + begin + if(tmr2_done & (!wb_wait | !wb_cycle) ) + begin + cs_le_d = wb_cycle; + if(cs_le_r | !wb_cycle) next_state = IDLE; + end + end + + ///////////////////////////////////////// + // SCS STATES .... + ///////////////////////////////////////// + SCS_RD: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr_ld_trdv = 1'b1; + if(mc_ack) next_state = SCS_RD1; + else + if(tmr2_done) next_state = SCS_ERR; + end + + SCS_RD1: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + if(tmr_done) + begin + mem_ack_d = 1'b1; + tmr_ld_trdz = 1'b1; + next_state = SCS_RD2; + end + end + + SCS_RD2: + begin + tmr_ld_trdz = 1'b1; + next_state = IDLE_T; + end + + SCS_WR: + begin + tmr_ld_twr2 = 1'b1; + cmd = `MC_CMD_XWR; + data_oe_d = 1'b1; + if(mc_ack) next_state = SCS_WR1; + else + if(tmr2_done) next_state = SCS_ERR; + end + + SCS_WR1: + begin + data_oe_d = 1'b1; + if(tmr_done) + begin + mem_ack_d = 1'b1; + next_state = IDLE_T; + end + else cmd = `MC_CMD_XWR; + end + + SCS_ERR: + begin + mem_ack_d = 1'b1; + err_d = 1'b1; + next_state = IDLE_T2; + end + + ///////////////////////////////////////// + // SSRAM STATES .... + ///////////////////////////////////////// + SRAM_RD: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + mc_adsc = 1'b1; + tmr2_ld_tsrdv = 1'b1; + burst_cnt_ld_4 = 1'b1; + if(cmd_asserted) next_state = SRAM_RD0; + end + + SRAM_RD0: + begin + mc_adv = 1'b1; + oe_d = 1'b1; + if(tmr2_done) + begin + mc_adv = !wb_wait; + next_state = SRAM_RD1; + end + end + + SRAM_RD1: + begin + if(mc_adv_r) dv = ~dv_r; + mc_adv = !wb_wait; + + if(!burst_act | !wb_read_go) next_state = SRAM_RD2; + else oe_d = 1'b1; + end + + SRAM_RD2: + begin + if(ack_cnt_is_0 & wb_read_go) next_state = SRAM_RD3; + else + if(!wb_read_go) + begin + mc_adsc = 1'b1; + next_state = SRAM_RD4; + end + end + + SRAM_RD3: + begin + if(!wb_read_go) + begin + mc_adsc = 1'b1; + next_state = SRAM_RD4; + end + else + if(!wb_wait) + begin + cs_le_d = 1'b1; + next_state = SRAM_RD; + end + end + + SRAM_RD4: // DESELECT + begin + if(wb_cycle) cs_le_d = 1'b1; // For RMW + mc_adsc = 1'b1; + next_state = IDLE; + end + + SRAM_WR: + begin + cmd = `MC_CMD_XWR; + mc_adsc = 1'b1; + data_oe_d = 1'b1; + if(cmd_asserted) + begin + if(wb_wait) next_state = SRAM_WR0; + else + if(!wb_write_go) + begin + mc_adsc = 1'b1; + next_state = SRAM_RD4; + end + else + begin + data_oe_d = 1'b1; + mem_ack_d = ~mem_ack_r; + end + end + end + + SRAM_WR0: + begin + if(wb_wait) next_state = SRAM_WR0; + else + if(!wb_write_go) + begin + mc_adsc = 1'b1; + next_state = SRAM_RD4; + end + else + begin + data_oe_d = 1'b1; + next_state = SRAM_WR; + end + end + + ///////////////////////////////////////// + // Async Devices STATES .... + ///////////////////////////////////////// + ACS_RD: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr2_ld_trdv = 1'b1; + next_state = ACS_RD1; + end + + ACS_RD1: + begin // 32 bit, 8 bit - first; 16 bit - first + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + if(tmr2_done) + begin + if(bw8 | bw16) next_adr = 1'b1; + if(bw8) next_state = ACS_RD_8_1; + else + if(bw16) next_state = ACS_RD_8_5; + else next_state = ACS_RD2A; + end + end + + ACS_RD_8_1: + begin // 8 bit 2nd byte + pack_le0_d = 1'b1; + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr2_ld_trdv = 1'b1; + next_state = ACS_RD_8_2; + end + + ACS_RD_8_2: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + if(tmr2_done) + begin + next_adr = 1'b1; + next_state = ACS_RD_8_3; + end + end + + ACS_RD_8_3: + begin // 8 bit 3rd byte + pack_le1_d = 1'b1; + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr2_ld_trdv = 1'b1; + next_state = ACS_RD_8_4; + end + + ACS_RD_8_4: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + if(tmr2_done) + begin + next_adr = 1'b1; + next_state = ACS_RD_8_5; + end + end + + ACS_RD_8_5: + begin // 8 bit 4th byte; 16 bit 2nd word + if(bw8) pack_le2_d = 1'b1; + if(bw16) pack_le0_d = 1'b1; + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr2_ld_trdv = 1'b1; + next_state = ACS_RD_8_6; + end + + ACS_RD_8_6: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + if(tmr2_done) + begin + next_state = ACS_RD2; + end + end + + ACS_RD2A: + begin + oe_d = 1'b1; + cmd = `MC_CMD_XRD; + next_state = ACS_RD2; + end + + ACS_RD2: + begin + cmd = `MC_CMD_XRD; + next_state = ACS_RD3; + end + + ACS_RD3: + begin + mem_ack_d = 1'b1; + tmr2_ld_trdz = 1'b1; + next_state = IDLE_T2; + end + + ACS_WR: + begin + tmr2_ld_twpw = 1'b1; + cmd = `MC_CMD_XWR; + data_oe_d = 1'b1; + next_state = ACS_WR1; + end + + ACS_WR1: + begin + if(!cmd_asserted) tmr2_ld_twpw = 1'b1; + cmd = `MC_CMD_XWR; + data_oe_d = 1'b1; + if(tmr2_done) + begin + tmr2_ld_twd = 1'b1; + next_state = ACS_WR2; + end + end + + ACS_WR2: + begin + if(twd_is_zero) next_state = ACS_WR3; + else + begin + cmd = `MC_CMD_XRD; + data_oe_d = 1'b1; + next_state = ACS_WR3; + end + end + + ACS_WR3: + begin + if(tmr2_done) next_state = ACS_WR4; + else cmd = `MC_CMD_XRD; + end + + ACS_WR4: + begin + tmr2_ld_twwd = 1'b1; + mem_ack_d = 1'b1; + next_state = IDLE_T2; + end + + ///////////////////////////////////////// + // SDRAM STATES .... + ///////////////////////////////////////// + + PRECHARGE: + begin + cmd = `MC_CMD_PC; + if(rfr_ack_r) + begin + rfr_ack_d = 1'b1; + cmd_a10 = `MC_ALL_BANKS; + bank_clr_all = 1'b1; + end + else + begin + bank_clr = 1'b1; + cmd_a10 = `MC_SINGLE_BANK; + end + tmr_ld_trp = 1'b1; + if(cmd_asserted) next_state = PRECHARGE_W; + end + + PRECHARGE_W: + begin + rfr_ack_d = rfr_ack_r; + if(tmr_done) + begin + if(rfr_ack_r) next_state = REFR; + else next_state = ACTIVATE; + end + end + + ACTIVATE: + begin + if(!wb_wait_r) + begin + row_sel = 1'b1; + tmr_ld_trcd = 1'b1; + cmd = `MC_CMD_ACT; + end + if(cmd_asserted) next_state = ACTIVATE_W; + end + + ACTIVATE_W: + begin + row_sel = 1'b1; + if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1; + + if(kro) bank_set = 1'b1; + + if(tmr_done) + begin + if(wb_write_go) + begin + mem_ack_d = ~mem_ack_r; + cmd_a10 = ap_en | (single_write & !kro); + next_state = SD_WR; + end + else + if(!wb_wait_r) next_state = SD_RD; + end + end + + SD_RD_WR: + begin + if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1; + + if(wb_write_go & !wb_wait) + begin // Write + data_oe_d = 1'b1; + mem_ack_d = ~mem_ack_r; + cmd_a10 = ap_en | (single_write & !kro); + next_state = SD_WR; + end + else + if(!wb_wait) + begin // Read + if(kro) + begin + if(!wb_wait_r) next_state = SD_RD; + end + else next_state = SD_RD; + end + end + + SD_WR: // Write Command + begin // Does the first single write + data_oe_d = 1'b1; + tmr_ld_twr = 1'b1; + cnt_next = ~cnt; + cmd = `MC_CMD_WR; + + cmd_a10 = ap_en | (single_write & !kro); + + if(!cnt & wb_cycle & burst_act) cke_d = ~wb_wait; + else cke_d = cke_r; + + if(cmd_asserted) + begin + mem_ack_d = !mem_ack_r & wb_write_go & !wb_wait & wb_cycle & burst_act; + + if(wb_cycle & !burst_act) next_state = IDLE_T; + else + if(wb_write_go) next_state = SD_WR_W; + else + if(burst_act & !single_write) next_state = BT; + else + if(!ap_en) next_state = BT_W; + else next_state = IDLE_T; + end + + end + + SD_WR_W: + begin // Does additional Writes or Times them + tmr_ld_twr = 1'b1; + cnt_next = ~cnt; + + if(single_write & wb_cycle) + begin + cmd = `MC_CMD_WR; + end + cmd_a10 = ap_en | (single_write & !kro); + + data_oe_d = 1'b1; + mem_ack_d = !mem_ack_r & wb_write_go & !wb_wait & wr_cycle & burst_act; + + if(!cnt) cke_d = ~wb_wait; + else cke_d = cke_r; + + if( (single_write & cke_r) | (!single_write & !cnt & !wb_wait) | (!single_write & cnt & cke_r) ) + begin + if(single_write & !wb_cycle) next_state = IDLE_T; + else + if(burst_act & !single_write & !wb_write_go_r) + begin + cmd = `MC_CMD_BT; + next_state = BT; + end + else + if(!burst_act & !ap_en) next_state = BT_W; + else + if(!burst_act) next_state = IDLE_T; + else + if(!wb_write_go_r & wb_read_go) next_state = IDLE_T; // Added for WMR + end + end + + SD_RD: // Read Command + begin + cmd = `MC_CMD_RD; + cmd_a10 = ap_en; + tmr_ld_tcl = 1'b1; + if(cmd_asserted) next_state = SD_RD_W; + end + + SD_RD_W: + begin + if(tmr_done) next_state = SD_RD_LOOP; + end + + SD_RD_LOOP: + begin + cnt_next = ~cnt; + + if(cnt & !(burst_act & !wb_cycle) & burst_act ) cke_rd = !wb_wait; + else cke_rd = cke_; + + if(wb_cycle & !cnt & burst_act_rd & cke_o_del) dv = 1'b1; + + if(wb_cycle & wb_write_go) next_state = BT; + else + if(burst_act & !wb_cycle) next_state = BT; + else + if(!burst_act) next_state = SD_RD_W2; + end + + SD_RD_W2: + begin + if(wb_write_go | ack_cnt_is_0) + begin + if(!ap_en & !kro) next_state = BT_W; + else + if(!wb_wait & !mem_ack_r) next_state = IDLE_T; + end + end + + BT: + begin + cmd = `MC_CMD_BT; + tmr_ld_trp = 1'b1; + if(cmd_asserted) next_state = BT_W; + end + + BT_W: + begin + cmd_a10 = cmd_a10_r; // Hold Auto Precharge 'til cycle finishes + + if(kro & tmr_done) + begin + if(kro & !wb_wait & (wb_read_go | wb_write_go) ) cs_le_d = 1'b1; + next_state = IDLE; + end + else + if(!kro & tmr_done) // Must do a PRECHARGE after Burst Terminate + begin + bank_clr = 1'b1; + cmd = `MC_CMD_PC; + cmd_a10 = `MC_SINGLE_BANK; + tmr_ld_trp = 1'b1; + if(cmd_asserted) next_state = IDLE_T; + end + end + + REFR: // Refresh Cycle + begin + cs_le_d = 1'b1; + cmd = `MC_CMD_ARFR; + tmr_ld_trfc = 1'b1; + rfr_ack_d = 1'b1; + if(cmd_asserted) + begin + susp_sel_clr = 1'b1; + next_state = IDLE_T; + end + end + + LMR0: + begin + lmr_ack_d = 1'b1; + cmd = `MC_CMD_PC; + cmd_a10 = `MC_ALL_BANKS; + bank_clr_all = 1'b1; + tmr_ld_trp = 1'b1; + if(cmd_asserted) next_state = LMR1; + end + + LMR1: + begin + lmr_ack_d = 1'b1; + if(tmr_done) next_state = LMR2; + end + + LMR2: + begin + bank_clr_all = 1'b1; + cmd = `MC_CMD_LMR; + tmr_ld_trfc = 1'b1; + lmr_ack_d = 1'b1; + if(cmd_asserted) next_state = IDLE_T; + end + + INIT0: + begin + cs_le_d = 1'b1; + next_state = INIT; + end + + INIT: // Initialize SDRAMS + begin // PRECHARGE + init_ack = 1'b1; + cmd = `MC_CMD_PC; + cmd_a10 = `MC_ALL_BANKS; + bank_clr_all = 1'b1; + tmr_ld_trp = 1'b1; + ir_cnt_ld = 1'b1; + if(cmd_asserted) next_state = INIT_W; + end + + INIT_W: + begin + init_ack = 1'b1; + if(tmr_done) next_state = INIT_REFR1; + end + + INIT_REFR1: // Init Refresh Cycle 1 + begin + init_ack = 1'b1; + cmd = `MC_CMD_ARFR; + tmr_ld_trfc = 1'b1; + if(cmd_asserted) + begin + ir_cnt_dec = 1'b1; + next_state = INIT_REFR1_W; + end + end + + INIT_REFR1_W: + begin + init_ack = 1'b1; + if(tmr_done) + begin + if(ir_cnt_done) next_state = INIT_LMR; + else next_state = INIT_REFR1; + end + end + + INIT_LMR: + begin + init_ack = 1'b1; + cmd = `MC_CMD_LMR; + bank_clr_all = 1'b1; + tmr_ld_trfc = 1'b1; + if(cmd_asserted) next_state = IDLE_T; + end + + ///////////////////////////////////////// + // Bus Arbitration STATES .... + ///////////////////////////////////////// + BG0: + begin // Bus Grant + mc_bg = 1'b1; + mc_c_oe_d = 1'b0; + next_state = BG1; + end + BG1: + begin // Bus Grant + mc_bg = 1'b1; + cs_le_d = 1'b1; + mc_c_oe_d = 1'b0; + next_state = BG2; + end + BG2: + begin // Bus Grant + cs_le_d = 1'b1; + mc_bg = !wb_read_go & !wb_write_go & + !rfr_req & !init_req & !lmr_req & + !susp_req_r; + tmr_ld_tavav = 1'b1; + mc_c_oe_d = mc_br; + if(!mc_br) next_state = IDLE_T; + end + + ///////////////////////////////////////// + // SUSPEND/RESUME STATES .... + ///////////////////////////////////////// + SUSP1: + begin // Precharge All + cmd = `MC_CMD_PC; + cmd_a10 = `MC_ALL_BANKS; + bank_clr_all = 1'b1; + tmr_ld_trp = 1'b1; + if(cmd_asserted) next_state = SUSP2; + end + + SUSP2: + begin + if(tmr_done) next_state = SUSP3; + end + + SUSP3: + begin // Enter Self refresh Mode + cke_d = 1'b0; + cmd = `MC_CMD_ARFR; + rfr_ack_d = 1'b1; + if(cmd_asserted) + begin + next_state = SUSP4; + end + end + + SUSP4: + begin // Now we are suspended + cke_rd = 1'b0; + suspended_d = 1'b1; + tmr_ld_txsr = 1'b1; + if(resume_req_r) next_state = RESUME1; + end + + RESUME1: + begin + suspended_d = 1'b1; + tmr_ld_txsr = 1'b1; + next_state = RESUME2; + end + + RESUME2: + begin + suspended_d = 1'b1; + if(tmr_done) next_state = REFR; + end + +// synopsys translate_off + default: + $display("MC_TIMING SM: Entered non existing state ... (%t)",$time); +// synopsys translate_on + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_area/mc_top.v b/designs/encrypted_ip/des3_area/mc_top.v new file mode 100644 index 000000000..9aec51bbf --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_top.v @@ -0,0 +1,545 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_top.v,v 1.7 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.7 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.6 2001/12/21 05:09:30 rudi +// +// - Fixed combinatorial loops in synthesis +// - Fixed byte select bug +// +// Revision 1.5 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.4 2001/09/10 13:44:17 rudi +// *** empty log message *** +// +// Revision 1.3 2001/09/02 02:28:28 rudi +// +// Many fixes for minor bugs that showed up in gate level simulations. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:39 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_top(clk_i, rst_i, + + wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, + + susp_req_i, resume_req_i, suspended_o, poc_o, + + mc_clk_i, mc_br_pad_i, mc_bg_pad_o, mc_ack_pad_i, + mc_addr_pad_o, mc_data_pad_i, mc_data_pad_o, mc_dp_pad_i, + mc_dp_pad_o, mc_doe_pad_doe_o, mc_dqm_pad_o, mc_oe_pad_o_, + mc_we_pad_o_, mc_cas_pad_o_, mc_ras_pad_o_, mc_cke_pad_o_, + mc_cs_pad_o_, mc_sts_pad_i, mc_rp_pad_o_, mc_vpen_pad_o, + mc_adsc_pad_o_, mc_adv_pad_o_, mc_zz_pad_o, mc_coe_pad_coe_o + ); + +input clk_i, rst_i; + +// -------------------------------------- +// WISHBONE SLAVE INTERFACE +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input [31:0] wb_addr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// -------------------------------------- +// Suspend Resume Interface +input susp_req_i; +input resume_req_i; +output suspended_o; + +// POC +output [31:0] poc_o; + +// -------------------------------------- +// Memory Bus Signals +input mc_clk_i; +input mc_br_pad_i; +output mc_bg_pad_o; +input mc_ack_pad_i; +output [23:0] mc_addr_pad_o; +input [31:0] mc_data_pad_i; +output [31:0] mc_data_pad_o; +input [3:0] mc_dp_pad_i; +output [3:0] mc_dp_pad_o; +output mc_doe_pad_doe_o; +output [3:0] mc_dqm_pad_o; +output mc_oe_pad_o_; +output mc_we_pad_o_; +output mc_cas_pad_o_; +output mc_ras_pad_o_; +output mc_cke_pad_o_; +output [7:0] mc_cs_pad_o_; +input mc_sts_pad_i; +output mc_rp_pad_o_; +output mc_vpen_pad_o; +output mc_adsc_pad_o_; +output mc_adv_pad_o_; +output mc_zz_pad_o; +output mc_coe_pad_coe_o; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +// WISHBONE Interface Interconnects +wire wb_read_go; +wire wb_write_go; +wire wb_first; +wire wb_wait; +wire mem_ack; + +// Suspend Resume Interface +wire susp_sel; + +// Register File Interconnects +wire [31:0] rf_dout; +wire [31:0] csc; +wire [31:0] tms; +wire [31:0] sp_csc; +wire [31:0] sp_tms; +wire [7:0] cs; +wire fs; +wire cs_le; +wire [7:0] cs_need_rfr; +wire [2:0] ref_int; +wire [31:0] mem_dout; +wire wp_err; + +// Address Select Signals +wire [12:0] row_adr; +wire [1:0] bank_adr; +wire cmd_a10; +wire row_sel; +wire next_adr; +wire [10:0] page_size; +wire lmr_sel; +wire wr_hold; + +// OBCT Signals +wire bank_set; +wire bank_clr; +wire bank_clr_all; +wire bank_open; +wire row_same; +wire [7:0] obct_cs; +wire any_bank_open; + +// Data path Controller Signals +wire dv; +wire pack_le0, pack_le1, pack_le2; // Pack Latch Enable +wire par_err; +wire [31:0] mc_data_od; +wire [3:0] mc_dp_od; +wire [23:0] mc_addr_d; +wire [35:0] mc_data_ir; + +// Refresh Counter Signals +wire rfr_req; +wire rfr_ack; +wire [7:0] rfr_ps_val; + +// Memory Timing Block Signals +wire data_oe; +wire oe_; +wire we_; +wire cas_; +wire ras_; +wire cke_; +wire lmr_req; +wire lmr_ack; +wire init_req; +wire init_ack; +wire [7:0] spec_req_cs; +wire cs_en; +wire wb_cycle, wr_cycle; +wire [31:0] tms_s; +wire [31:0] csc_s; +wire mc_c_oe_d; +wire mc_br_r; +wire mc_bg_d; +wire mc_adsc_d; +wire mc_adv_d; +wire mc_ack_r; +wire err; +wire mc_sts_i; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign obct_cs = (rfr_ack | susp_sel) ? cs_need_rfr : + (lmr_ack | init_ack) ? spec_req_cs : cs; + +assign lmr_sel = lmr_ack | init_ack; + +assign tms_s = lmr_sel ? sp_tms : tms; +assign csc_s = lmr_sel ? sp_csc : csc; + + +wire not_mem_cyc; + +assign not_mem_cyc = wb_cyc_i & wb_stb_i & !( `MC_MEM_SEL ); + +reg mem_ack_r; + +always @(posedge clk_i) + mem_ack_r <= #1 mem_ack; + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +mc_rf u0( + .clk( clk_i ), + .rst( rst_i ), + .wb_data_i( wb_data_i ), + .rf_dout( rf_dout ), + .wb_addr_i( wb_addr_i ), + .wb_we_i( wb_we_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_ack_o( ), + .wp_err( wp_err ), + .csc( csc ), + .tms( tms ), + .poc( poc_o ), + .sp_csc( sp_csc ), + .sp_tms( sp_tms ), + .cs( cs ), + .mc_data_i( mc_data_ir[31:0]), + .mc_sts( mc_sts_ir ), + .mc_vpen( mc_vpen_pad_o ), + .fs( fs ), + .cs_le( cs_le ), + .cs_le_d( cs_le_d ), + .cs_need_rfr( cs_need_rfr ), + .ref_int( ref_int ), + .rfr_ps_val( rfr_ps_val ), + .spec_req_cs( spec_req_cs ), + .init_req( init_req ), + .init_ack( init_ack ), + .lmr_req( lmr_req ), + .lmr_ack( lmr_ack ) + ); + +mc_adr_sel u1( + .clk( clk_i ), + .csc( csc_s ), + .tms( tms_s ), + .wb_stb_i( wb_stb_i ), + //.wb_ack_o( wb_ack_o ), + .wb_ack_o( mem_ack_r ), + .wb_addr_i( wb_addr_i ), + .wb_we_i( wb_we_i ), + .wb_write_go( wb_write_go ), + .wr_hold( wr_hold ), + .cas_( cas_ ), + .mc_addr( mc_addr_d ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .rfr_ack( rfr_ack ), + .cs_le( cs_le ), + .cmd_a10( cmd_a10 ), + .row_sel( row_sel ), + .lmr_sel( lmr_sel ), + .next_adr( next_adr ), + .wr_cycle( wr_cycle ), + .page_size( page_size ) + ); + +mc_obct_top u2( + .clk( clk_i ), + .rst( rst_i ), + .cs( obct_cs ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set ), + .bank_clr( bank_clr ), + .bank_clr_all( bank_clr_all ), + .bank_open( bank_open ), + .any_bank_open( any_bank_open ), + .row_same( row_same ), + .rfr_ack( rfr_ack ) + ); + +mc_dp u3( + .clk( clk_i ), + .rst( rst_i ), + .csc( csc ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .mem_ack( mem_ack ), + //.wb_ack_o( wb_ack_o ), + .wb_ack_o( mem_ack_r ), + .wb_we_i( wb_we_i ), + .wb_data_i( wb_data_i ), + .wb_data_o( mem_dout ), + .wb_read_go( wb_read_go ), + .mc_clk( mc_clk_i ), + .mc_data_del( mc_data_ir ), + .mc_dp_i( mc_dp_pad_i ), + .mc_data_o( mc_data_od ), + .mc_dp_o( mc_dp_od ), + .dv( dv ), + .pack_le0( pack_le0 ), + .pack_le1( pack_le1 ), + .pack_le2( pack_le2 ), + .byte_en( wb_sel_i ), + .par_err( par_err ) + ); + +mc_refresh u4( + .clk( clk_i ), + .rst( rst_i ), + .cs_need_rfr( cs_need_rfr ), + .ref_int( ref_int ), + .rfr_req( rfr_req ), + .rfr_ack( rfr_ack ), + .rfr_ps_val( rfr_ps_val ) + ); + +mc_timing u5( + .clk( clk_i ), + .mc_clk( mc_clk_i ), + .rst( rst_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_we_i( wb_we_i ), + .wb_read_go( wb_read_go ), + .wb_write_go( wb_write_go ), + .wb_first( wb_first ), + .wb_wait( wb_wait ), + .mem_ack( mem_ack ), + .err( err ), + .susp_req( susp_req_i ), + .resume_req( resume_req_i ), + .suspended( suspended_o ), + .susp_sel( susp_sel ), + .mc_br( mc_br_r ), + .mc_bg( mc_bg_d ), + .mc_ack( mc_ack_r ), + .not_mem_cyc( not_mem_cyc ), + .data_oe( data_oe ), + .oe_( oe_ ), + .we_( we_ ), + .cas_( cas_ ), + .ras_( ras_ ), + .cke_( cke_ ), + .cs_en( cs_en ), + .mc_adsc( mc_adsc_d ), + .mc_adv( mc_adv_d ), + .mc_c_oe( mc_c_oe_d ), + .wb_cycle( wb_cycle ), + .wr_cycle( wr_cycle ), + .csc( csc_s ), + .tms( tms_s ), + .cs( obct_cs ), + .lmr_req( lmr_req ), + .lmr_ack( lmr_ack ), + .cs_le( cs_le ), + .cs_le_d( cs_le_d ), + .cmd_a10( cmd_a10 ), + .row_sel( row_sel ), + .next_adr( next_adr ), + .page_size( page_size ), + .bank_set( bank_set ), + .bank_clr( bank_clr ), + .bank_clr_all( bank_clr_all ), + .bank_open( bank_open ), + .any_bank_open( any_bank_open ), + .row_same( row_same ), + .dv( dv ), + .pack_le0( pack_le0 ), + .pack_le1( pack_le1 ), + .pack_le2( pack_le2 ), + .par_err( par_err ), + .rfr_req( rfr_req ), + .rfr_ack( rfr_ack ), + .init_req( init_req ), + .init_ack( init_ack ) + ); + +mc_wb_if u6( + .clk( clk_i ), + .rst( rst_i ), + .wb_addr_i( wb_addr_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_we_i( wb_we_i ), + .wb_ack_o( wb_ack_o ), + .wb_err( wb_err_o ), + .wb_read_go( wb_read_go ), + .wb_write_go( wb_write_go ), + .wb_first( wb_first ), + .wb_wait( wb_wait ), + .mem_ack( mem_ack ), + .wr_hold( wr_hold ), + .err( err ), + .par_err( par_err ), + .wp_err( wp_err ), + .wb_data_o( wb_data_o ), + .mem_dout( mem_dout ), + .rf_dout( rf_dout ) + ); + +mc_mem_if u7( + .clk( clk_i ), + .rst( rst_i ), + .mc_rp( mc_rp_pad_o_ ), + .mc_clk( mc_clk_i ), + .mc_br( mc_br_pad_i ), + .mc_bg( mc_bg_pad_o ), + .mc_addr( mc_addr_pad_o ), + .mc_data_o( mc_data_pad_o ), + .mc_dp_o( mc_dp_pad_o ), + .mc_data_oe( mc_doe_pad_doe_o), + .mc_dqm( mc_dqm_pad_o ), + .mc_oe_( mc_oe_pad_o_ ), + .mc_we_( mc_we_pad_o_ ), + .mc_cas_( mc_cas_pad_o_ ), + .mc_ras_( mc_ras_pad_o_ ), + .mc_cke_( mc_cke_pad_o_ ), + .mc_cs_( mc_cs_pad_o_ ), + .mc_adsc_( mc_adsc_pad_o_ ), + .mc_adv_( mc_adv_pad_o_ ), + .mc_br_r( mc_br_r ), + .mc_bg_d( mc_bg_d ), + .mc_data_od( mc_data_od ), + .mc_dp_od( mc_dp_od ), + .mc_addr_d( mc_addr_d ), + .mc_ack( mc_ack_pad_i ), + .mc_zz_o( mc_zz_pad_o ), + .we_( we_ ), + .ras_( ras_ ), + .cas_( cas_ ), + .cke_( cke_ ), + .mc_adsc_d( mc_adsc_d ), + .mc_adv_d( mc_adv_d ), + .cs_en( cs_en ), + .rfr_ack( rfr_ack ), + .cs_need_rfr( cs_need_rfr ), + .lmr_sel( lmr_sel ), + .spec_req_cs( spec_req_cs ), + .cs( cs ), + .fs( fs ), + .data_oe( data_oe ), + .susp_sel( susp_sel ), + .suspended_o( suspended_o ), + .mc_c_oe( mc_coe_pad_coe_o), + .mc_c_oe_d( mc_c_oe_d ), + .mc_ack_r( mc_ack_r ), + .oe_( oe_ ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_sel_i( wb_sel_i ), + .wb_cycle( wb_cycle ), + .wr_cycle( wr_cycle ), + .mc_data_i( mc_data_pad_i ), + .mc_dp_i( mc_dp_pad_i ), + .mc_data_ir( mc_data_ir ), + .mc_sts_i( mc_sts_pad_i ), + .mc_sts_ir( mc_sts_ir ) + ); + +endmodule diff --git a/designs/encrypted_ip/des3_area/mc_top_synthed.v b/designs/encrypted_ip/des3_area/mc_top_synthed.v new file mode 100644 index 000000000..45db23245 --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_top_synthed.v @@ -0,0 +1,18190 @@ +// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021 +// Date : Fri May 26 10:15:05 2023 +// Host : goeders1 running 64-bit Ubuntu 20.04.3 LTS +// Command : write_verilog ./mc_top_synthed.v -force +// Design : mc_top +// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an +// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input +// design files. +// Device : xc7a100tcsg324-3 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* STRUCTURAL_NETLIST = "yes" *) +module mc_top + (clk_i, + rst_i, + wb_data_i, + wb_data_o, + wb_addr_i, + wb_sel_i, + wb_we_i, + wb_cyc_i, + wb_stb_i, + wb_ack_o, + wb_err_o, + susp_req_i, + resume_req_i, + suspended_o, + poc_o, + mc_clk_i, + mc_br_pad_i, + mc_bg_pad_o, + mc_ack_pad_i, + mc_addr_pad_o, + mc_data_pad_i, + mc_data_pad_o, + mc_dp_pad_i, + mc_dp_pad_o, + mc_doe_pad_doe_o, + mc_dqm_pad_o, + mc_oe_pad_o_, + mc_we_pad_o_, + mc_cas_pad_o_, + mc_ras_pad_o_, + mc_cke_pad_o_, + mc_cs_pad_o_, + mc_sts_pad_i, + mc_rp_pad_o_, + mc_vpen_pad_o, + mc_adsc_pad_o_, + mc_adv_pad_o_, + mc_zz_pad_o, + mc_coe_pad_coe_o); + input clk_i; + input rst_i; + input [31:0]wb_data_i; + output [31:0]wb_data_o; + input [31:0]wb_addr_i; + input [3:0]wb_sel_i; + input wb_we_i; + input wb_cyc_i; + input wb_stb_i; + output wb_ack_o; + output wb_err_o; + input susp_req_i; + input resume_req_i; + output suspended_o; + output [31:0]poc_o; + input mc_clk_i; + input mc_br_pad_i; + output mc_bg_pad_o; + input mc_ack_pad_i; + output [23:0]mc_addr_pad_o; + input [31:0]mc_data_pad_i; + output [31:0]mc_data_pad_o; + input [3:0]mc_dp_pad_i; + output [3:0]mc_dp_pad_o; + output mc_doe_pad_doe_o; + output [3:0]mc_dqm_pad_o; + output mc_oe_pad_o_; + output mc_we_pad_o_; + output mc_cas_pad_o_; + output mc_ras_pad_o_; + output mc_cke_pad_o_; + output [7:0]mc_cs_pad_o_; + input mc_sts_pad_i; + output mc_rp_pad_o_; + output mc_vpen_pad_o; + output mc_adsc_pad_o_; + output mc_adv_pad_o_; + output mc_zz_pad_o; + output mc_coe_pad_coe_o; + + wire \ ; + wire \ ; + wire \FSM_sequential_state[0]_i_10_n_0 ; + wire \FSM_sequential_state[0]_i_11_n_0 ; + wire \FSM_sequential_state[0]_i_12_n_0 ; + wire \FSM_sequential_state[0]_i_13_n_0 ; + wire \FSM_sequential_state[0]_i_14_n_0 ; + wire \FSM_sequential_state[0]_i_15_n_0 ; + wire \FSM_sequential_state[0]_i_16_n_0 ; + wire \FSM_sequential_state[0]_i_17_n_0 ; + wire \FSM_sequential_state[0]_i_18_n_0 ; + wire \FSM_sequential_state[0]_i_1_n_0 ; + wire \FSM_sequential_state[0]_i_2_n_0 ; + wire \FSM_sequential_state[0]_i_3_n_0 ; + wire \FSM_sequential_state[0]_i_4_n_0 ; + wire \FSM_sequential_state[0]_i_5_n_0 ; + wire \FSM_sequential_state[0]_i_6_n_0 ; + wire \FSM_sequential_state[0]_i_7_n_0 ; + wire \FSM_sequential_state[0]_i_8_n_0 ; + wire \FSM_sequential_state[0]_i_9_n_0 ; + wire \FSM_sequential_state[1]_i_10_n_0 ; + wire \FSM_sequential_state[1]_i_11_n_0 ; + wire \FSM_sequential_state[1]_i_12_n_0 ; + wire \FSM_sequential_state[1]_i_13_n_0 ; + wire \FSM_sequential_state[1]_i_14_n_0 ; + wire \FSM_sequential_state[1]_i_15_n_0 ; + wire \FSM_sequential_state[1]_i_16_n_0 ; + wire \FSM_sequential_state[1]_i_17_n_0 ; + wire \FSM_sequential_state[1]_i_18_n_0 ; + wire \FSM_sequential_state[1]_i_19_n_0 ; + wire \FSM_sequential_state[1]_i_1_n_0 ; + wire \FSM_sequential_state[1]_i_20_n_0 ; + wire \FSM_sequential_state[1]_i_21_n_0 ; + wire \FSM_sequential_state[1]_i_2_n_0 ; + wire \FSM_sequential_state[1]_i_3_n_0 ; + wire \FSM_sequential_state[1]_i_4_n_0 ; + wire \FSM_sequential_state[1]_i_5_n_0 ; + wire \FSM_sequential_state[1]_i_6_n_0 ; + wire \FSM_sequential_state[1]_i_7_n_0 ; + wire \FSM_sequential_state[1]_i_8_n_0 ; + wire \FSM_sequential_state[1]_i_9_n_0 ; + wire \FSM_sequential_state[2]_i_10_n_0 ; + wire \FSM_sequential_state[2]_i_11_n_0 ; + wire \FSM_sequential_state[2]_i_12_n_0 ; + wire \FSM_sequential_state[2]_i_13_n_0 ; + wire \FSM_sequential_state[2]_i_14_n_0 ; + wire \FSM_sequential_state[2]_i_15_n_0 ; + wire \FSM_sequential_state[2]_i_16_n_0 ; + wire \FSM_sequential_state[2]_i_17_n_0 ; + wire \FSM_sequential_state[2]_i_18_n_0 ; + wire \FSM_sequential_state[2]_i_19_n_0 ; + wire \FSM_sequential_state[2]_i_1_n_0 ; + wire \FSM_sequential_state[2]_i_20_n_0 ; + wire \FSM_sequential_state[2]_i_21_n_0 ; + wire \FSM_sequential_state[2]_i_22_n_0 ; + wire \FSM_sequential_state[2]_i_2_n_0 ; + wire \FSM_sequential_state[2]_i_3_n_0 ; + wire \FSM_sequential_state[2]_i_4_n_0 ; + wire \FSM_sequential_state[2]_i_5_n_0 ; + wire \FSM_sequential_state[2]_i_6_n_0 ; + wire \FSM_sequential_state[2]_i_7_n_0 ; + wire \FSM_sequential_state[2]_i_8_n_0 ; + wire \FSM_sequential_state[2]_i_9_n_0 ; + wire \FSM_sequential_state[3]_i_10_n_0 ; + wire \FSM_sequential_state[3]_i_11_n_0 ; + wire \FSM_sequential_state[3]_i_12_n_0 ; + wire \FSM_sequential_state[3]_i_1_n_0 ; + wire \FSM_sequential_state[3]_i_2_n_0 ; + wire \FSM_sequential_state[3]_i_3_n_0 ; + wire \FSM_sequential_state[3]_i_4_n_0 ; + wire \FSM_sequential_state[3]_i_5_n_0 ; + wire \FSM_sequential_state[3]_i_6_n_0 ; + wire \FSM_sequential_state[3]_i_7_n_0 ; + wire \FSM_sequential_state[3]_i_8_n_0 ; + wire \FSM_sequential_state[3]_i_9_n_0 ; + wire \FSM_sequential_state[4]_i_10_n_0 ; + wire \FSM_sequential_state[4]_i_11_n_0 ; + wire \FSM_sequential_state[4]_i_1_n_0 ; + wire \FSM_sequential_state[4]_i_2_n_0 ; + wire \FSM_sequential_state[4]_i_3_n_0 ; + wire \FSM_sequential_state[4]_i_4_n_0 ; + wire \FSM_sequential_state[4]_i_5_n_0 ; + wire \FSM_sequential_state[4]_i_6_n_0 ; + wire \FSM_sequential_state[4]_i_7_n_0 ; + wire \FSM_sequential_state[4]_i_8_n_0 ; + wire \FSM_sequential_state[4]_i_9_n_0 ; + wire \FSM_sequential_state[5]_i_1_n_0 ; + wire \FSM_sequential_state[5]_i_2_n_0 ; + wire \FSM_sequential_state[5]_i_3_n_0 ; + wire \FSM_sequential_state[5]_i_4_n_0 ; + wire \FSM_sequential_state[5]_i_5_n_0 ; + wire \FSM_sequential_state[5]_i_6_n_0 ; + wire \FSM_sequential_state[5]_i_7_n_0 ; + wire \FSM_sequential_state[5]_i_8_n_0 ; + wire \FSM_sequential_state[5]_i_9_n_0 ; + wire \FSM_sequential_state[6]_i_10_n_0 ; + wire \FSM_sequential_state[6]_i_11_n_0 ; + wire \FSM_sequential_state[6]_i_12_n_0 ; + wire \FSM_sequential_state[6]_i_13_n_0 ; + wire \FSM_sequential_state[6]_i_14_n_0 ; + wire \FSM_sequential_state[6]_i_15_n_0 ; + wire \FSM_sequential_state[6]_i_16_n_0 ; + wire \FSM_sequential_state[6]_i_17_n_0 ; + wire \FSM_sequential_state[6]_i_18_n_0 ; + wire \FSM_sequential_state[6]_i_19_n_0 ; + wire \FSM_sequential_state[6]_i_1_n_0 ; + wire \FSM_sequential_state[6]_i_20_n_0 ; + wire \FSM_sequential_state[6]_i_21_n_0 ; + wire \FSM_sequential_state[6]_i_22_n_0 ; + wire \FSM_sequential_state[6]_i_23_n_0 ; + wire \FSM_sequential_state[6]_i_24_n_0 ; + wire \FSM_sequential_state[6]_i_25_n_0 ; + wire \FSM_sequential_state[6]_i_26_n_0 ; + wire \FSM_sequential_state[6]_i_27_n_0 ; + wire \FSM_sequential_state[6]_i_28_n_0 ; + wire \FSM_sequential_state[6]_i_29_n_0 ; + wire \FSM_sequential_state[6]_i_2_n_0 ; + wire \FSM_sequential_state[6]_i_30_n_0 ; + wire \FSM_sequential_state[6]_i_31_n_0 ; + wire \FSM_sequential_state[6]_i_32_n_0 ; + wire \FSM_sequential_state[6]_i_33_n_0 ; + wire \FSM_sequential_state[6]_i_34_n_0 ; + wire \FSM_sequential_state[6]_i_35_n_0 ; + wire \FSM_sequential_state[6]_i_36_n_0 ; + wire \FSM_sequential_state[6]_i_37_n_0 ; + wire \FSM_sequential_state[6]_i_38_n_0 ; + wire \FSM_sequential_state[6]_i_39_n_0 ; + wire \FSM_sequential_state[6]_i_3_n_0 ; + wire \FSM_sequential_state[6]_i_40_n_0 ; + wire \FSM_sequential_state[6]_i_41_n_0 ; + wire \FSM_sequential_state[6]_i_42_n_0 ; + wire \FSM_sequential_state[6]_i_43_n_0 ; + wire \FSM_sequential_state[6]_i_44_n_0 ; + wire \FSM_sequential_state[6]_i_45_n_0 ; + wire \FSM_sequential_state[6]_i_46_n_0 ; + wire \FSM_sequential_state[6]_i_47_n_0 ; + wire \FSM_sequential_state[6]_i_48_n_0 ; + wire \FSM_sequential_state[6]_i_4_n_0 ; + wire \FSM_sequential_state[6]_i_5_n_0 ; + wire \FSM_sequential_state[6]_i_6_n_0 ; + wire \FSM_sequential_state[6]_i_7_n_0 ; + wire \FSM_sequential_state[6]_i_8_n_0 ; + wire \FSM_sequential_state[6]_i_9_n_0 ; + wire \ack_cnt[1]_i_1_n_0 ; + wire \ack_cnt[2]_i_1_n_0 ; + wire \ack_cnt[3]_i_1_n_0 ; + wire \ack_cnt[3]_i_3_n_0 ; + wire [23:0]acs_addr; + wire \acs_addr[0]_i_1_n_0 ; + wire \acs_addr[0]_i_2_n_0 ; + wire \acs_addr[10]_i_1_n_0 ; + wire \acs_addr[10]_i_2_n_0 ; + wire \acs_addr[11]_i_1_n_0 ; + wire \acs_addr[11]_i_2_n_0 ; + wire \acs_addr[12]_i_1_n_0 ; + wire \acs_addr[12]_i_2_n_0 ; + wire \acs_addr[13]_i_1_n_0 ; + wire \acs_addr[13]_i_2_n_0 ; + wire \acs_addr[14]_i_1_n_0 ; + wire \acs_addr[14]_i_2_n_0 ; + wire \acs_addr[15]_i_1_n_0 ; + wire \acs_addr[15]_i_3_n_0 ; + wire \acs_addr[15]_i_4_n_0 ; + wire \acs_addr[16]_i_1_n_0 ; + wire \acs_addr[16]_i_2_n_0 ; + wire \acs_addr[17]_i_1_n_0 ; + wire \acs_addr[17]_i_2_n_0 ; + wire \acs_addr[18]_i_1_n_0 ; + wire \acs_addr[18]_i_2_n_0 ; + wire \acs_addr[19]_i_1_n_0 ; + wire \acs_addr[19]_i_3_n_0 ; + wire \acs_addr[1]_i_1_n_0 ; + wire \acs_addr[1]_i_2_n_0 ; + wire \acs_addr[20]_i_1_n_0 ; + wire \acs_addr[20]_i_2_n_0 ; + wire \acs_addr[21]_i_1_n_0 ; + wire \acs_addr[21]_i_2_n_0 ; + wire \acs_addr[22]_i_1_n_0 ; + wire \acs_addr[22]_i_2_n_0 ; + wire \acs_addr[23]_i_1_n_0 ; + wire \acs_addr[23]_i_2_n_0 ; + wire \acs_addr[23]_i_3_n_0 ; + wire \acs_addr[23]_i_4_n_0 ; + wire \acs_addr[23]_i_6_n_0 ; + wire \acs_addr[2]_i_1_n_0 ; + wire \acs_addr[2]_i_2_n_0 ; + wire \acs_addr[3]_i_1_n_0 ; + wire \acs_addr[3]_i_2_n_0 ; + wire \acs_addr[4]_i_1_n_0 ; + wire \acs_addr[4]_i_2_n_0 ; + wire \acs_addr[5]_i_1_n_0 ; + wire \acs_addr[5]_i_2_n_0 ; + wire \acs_addr[6]_i_1_n_0 ; + wire \acs_addr[6]_i_2_n_0 ; + wire \acs_addr[7]_i_1_n_0 ; + wire \acs_addr[7]_i_2_n_0 ; + wire \acs_addr[8]_i_1_n_0 ; + wire \acs_addr[8]_i_2_n_0 ; + wire \acs_addr[9]_i_1_n_0 ; + wire \acs_addr[9]_i_2_n_0 ; + wire \acs_addr_reg[15]_i_2_n_0 ; + wire \acs_addr_reg[15]_i_2_n_1 ; + wire \acs_addr_reg[15]_i_2_n_2 ; + wire \acs_addr_reg[15]_i_2_n_3 ; + wire \acs_addr_reg[19]_i_2_n_0 ; + wire \acs_addr_reg[19]_i_2_n_1 ; + wire \acs_addr_reg[19]_i_2_n_2 ; + wire \acs_addr_reg[19]_i_2_n_3 ; + wire \acs_addr_reg[23]_i_5_n_1 ; + wire \acs_addr_reg[23]_i_5_n_2 ; + wire \acs_addr_reg[23]_i_5_n_3 ; + wire ap_en_i_1_n_0; + wire ap_en_i_2_n_0; + wire [12:0]b0_last_row; + wire \b0_last_row[12]_i_1_n_0 ; + wire [12:0]b1_last_row; + wire \b1_last_row[12]_i_1_n_0 ; + wire [12:0]b2_last_row; + wire \b2_last_row[12]_i_1_n_0 ; + wire [12:0]b3_last_row; + wire \b3_last_row[12]_i_1_n_0 ; + wire \b3_last_row[12]_i_2__0_n_0 ; + wire \b3_last_row[12]_i_2_n_0 ; + wire \b3_last_row[12]_i_3_n_0 ; + wire \b3_last_row[12]_i_4_n_0 ; + wire bank0_open_i_1__0_n_0; + wire bank0_open_i_1_n_0; + wire bank1_open_i_1__0_n_0; + wire bank1_open_i_1_n_0; + wire bank2_open_i_1__0_n_0; + wire bank2_open_i_1_n_0; + wire bank3_open_i_1__0_n_0; + wire bank3_open_i_1_n_0; + wire bank3_open_i_2__0_n_0; + wire bank3_open_i_2_n_0; + wire bank3_open_i_3__0_n_0; + wire bank3_open_i_3_n_0; + wire bank3_open_i_4_n_0; + wire bank3_open_i_5_n_0; + wire bank3_open_i_6_n_0; + wire bank3_open_i_7_n_0; + wire [1:0]bank_adr; + wire \bank_adr[0]_i_1_n_0 ; + wire \bank_adr[0]_i_2_n_0 ; + wire \bank_adr[0]_i_3_n_0 ; + wire \bank_adr[0]_i_4_n_0 ; + wire \bank_adr[1]_i_1_n_0 ; + wire \bank_adr[1]_i_2_n_0 ; + wire \bank_adr[1]_i_3_n_0 ; + wire \bank_adr[1]_i_4_n_0 ; + wire \bank_adr[1]_i_5_n_0 ; + wire \bank_adr[1]_i_6_n_0 ; + wire bank_open; + wire bank_open_i_2_n_0; + wire bank_open_i_3_n_0; + wire burst_act_rd_i_2_n_0; + wire burst_act_rd_i_3_n_0; + wire \burst_cnt[10]_i_10_n_0 ; + wire \burst_cnt[10]_i_2_n_0 ; + wire \burst_cnt[10]_i_4_n_0 ; + wire \burst_cnt[10]_i_5_n_0 ; + wire \burst_cnt[10]_i_7_n_0 ; + wire \burst_cnt[10]_i_8_n_0 ; + wire \burst_cnt[10]_i_9_n_0 ; + wire \burst_cnt[3]_i_2_n_0 ; + wire \burst_cnt[3]_i_3_n_0 ; + wire \burst_cnt[3]_i_4_n_0 ; + wire \burst_cnt[6]_i_2_n_0 ; + wire \burst_cnt[7]_i_2_n_0 ; + wire \burst_cnt[8]_i_2_n_0 ; + wire \burst_cnt[8]_i_3_n_0 ; + wire \burst_cnt[8]_i_4_n_0 ; + wire \burst_cnt[9]_i_2_n_0 ; + wire [7:0]byte0; + wire [7:0]byte1; + wire \byte1[0]_i_1_n_0 ; + wire \byte1[1]_i_1_n_0 ; + wire \byte1[2]_i_1_n_0 ; + wire \byte1[3]_i_1_n_0 ; + wire \byte1[4]_i_1_n_0 ; + wire \byte1[5]_i_1_n_0 ; + wire \byte1[6]_i_1_n_0 ; + wire \byte1[7]_i_1_n_0 ; + wire \byte1[7]_i_2_n_0 ; + wire [7:0]byte2; + wire cas_; + wire cke__i_2_n_0; + wire cke__i_3_n_0; + wire cke__i_4_n_0; + wire cke__i_5_n_0; + wire cke_r_i_1_n_0; + wire cke_r_i_2_n_0; + wire cke_r_i_3_n_0; + wire cke_r_i_4_n_0; + wire cke_r_i_5_n_0; + wire clk_i; + wire cmd_a10; + wire cmd_a10_r_i_10_n_0; + wire cmd_a10_r_i_11_n_0; + wire cmd_a10_r_i_12_n_0; + wire cmd_a10_r_i_2_n_0; + wire cmd_a10_r_i_3_n_0; + wire cmd_a10_r_i_4_n_0; + wire cmd_a10_r_i_5_n_0; + wire cmd_a10_r_i_6_n_0; + wire cmd_a10_r_i_7_n_0; + wire cmd_a10_r_i_8_n_0; + wire cmd_a10_r_i_9_n_0; + wire cmd_asserted_i_10_n_0; + wire cmd_asserted_i_1_n_0; + wire cmd_asserted_i_2_n_0; + wire cmd_asserted_i_3_n_0; + wire cmd_asserted_i_4_n_0; + wire cmd_asserted_i_5_n_0; + wire cmd_asserted_i_6_n_0; + wire cmd_asserted_i_7_n_0; + wire cmd_asserted_i_8_n_0; + wire cmd_asserted_i_9_n_0; + wire \cmd_r[0]_i_10_n_0 ; + wire \cmd_r[0]_i_11_n_0 ; + wire \cmd_r[0]_i_12_n_0 ; + wire \cmd_r[0]_i_13_n_0 ; + wire \cmd_r[0]_i_2_n_0 ; + wire \cmd_r[0]_i_3_n_0 ; + wire \cmd_r[0]_i_4_n_0 ; + wire \cmd_r[0]_i_5_n_0 ; + wire \cmd_r[0]_i_6_n_0 ; + wire \cmd_r[0]_i_7_n_0 ; + wire \cmd_r[0]_i_8_n_0 ; + wire \cmd_r[0]_i_9_n_0 ; + wire \cmd_r[1]_i_2_n_0 ; + wire \cmd_r[1]_i_3_n_0 ; + wire \cmd_r[1]_i_4_n_0 ; + wire \cmd_r[1]_i_5_n_0 ; + wire \cmd_r[2]_i_2_n_0 ; + wire \cmd_r[2]_i_3_n_0 ; + wire \cmd_r[2]_i_4_n_0 ; + wire cnt_i_2_n_0; + wire [9:0]col_adr; + wire \col_adr[9]_i_1_n_0 ; + wire \col_adr[9]_i_3_n_0 ; + wire [1:0]cs; + wire \cs[0]_i_1_n_0 ; + wire cs_le; + wire cs_le_d; + wire cs_le_i_10_n_0; + wire cs_le_i_11_n_0; + wire cs_le_i_12_n_0; + wire cs_le_i_13_n_0; + wire cs_le_i_14_n_0; + wire cs_le_i_2_n_0; + wire cs_le_i_3_n_0; + wire cs_le_i_4_n_0; + wire cs_le_i_5_n_0; + wire cs_le_i_6_n_0; + wire cs_le_i_7_n_0; + wire cs_le_i_8_n_0; + wire cs_le_i_9_n_0; + wire [11:1]csc; + wire \csc[0]_i_1_n_0 ; + wire \csc[10]_i_1_n_0 ; + wire \csc[11]_i_10_n_0 ; + wire \csc[11]_i_11_n_0 ; + wire \csc[11]_i_12_n_0 ; + wire \csc[11]_i_13_n_0 ; + wire \csc[11]_i_1_n_0 ; + wire \csc[11]_i_2_n_0 ; + wire \csc[11]_i_3_n_0 ; + wire \csc[11]_i_5_n_0 ; + wire \csc[11]_i_6_n_0 ; + wire \csc[11]_i_7_n_0 ; + wire \csc[11]_i_8_n_0 ; + wire \csc[11]_i_9_n_0 ; + wire \csc[1]_i_1__0_n_0 ; + wire \csc[1]_i_1_n_0 ; + wire \csc[2]_i_1__0_n_0 ; + wire \csc[2]_i_1_n_0 ; + wire \csc[31]_i_1_n_0 ; + wire \csc[3]_i_1_n_0 ; + wire \csc[4]_i_1__0_n_0 ; + wire \csc[4]_i_1_n_0 ; + wire \csc[5]_i_1__0_n_0 ; + wire \csc[5]_i_1_n_0 ; + wire \csc[5]_i_2_n_0 ; + wire \csc[6]_i_1_n_0 ; + wire \csc[7]_i_1_n_0 ; + wire \csc[9]_i_1_n_0 ; + wire [10:6]csc__0; + wire data_oe; + wire data_oe_i_1_n_0; + wire data_oe_i_2_n_0; + wire data_oe_i_3_n_0; + wire data_oe_r_i_1_n_0; + wire data_oe_r_i_2_n_0; + wire data_oe_r_i_3_n_0; + wire data_oe_r_i_4_n_0; + wire data_oe_r_i_5_n_0; + wire data_oe_r_i_6_n_0; + wire data_oe_r_i_7_n_0; + wire dv; + wire dv_r_i_2_n_0; + wire dv_r_i_3_n_0; + wire fs; + wire inc_next; + wire [11:0]inc_out0; + wire init_ack; + wire init_req; + wire init_req_i_1__0_n_0; + wire init_req_i_1__1_n_0; + wire init_req_i_2__0_n_0; + wire init_req_i_2_n_0; + wire init_req_we_i_1_n_0; + wire inited_i_1__0_n_0; + wire inited_i_1_n_0; + wire [3:0]ir_cnt0; + wire \ir_cnt[1]_i_1_n_0 ; + wire \ir_cnt[3]_i_4_n_0 ; + wire ir_cnt_done_i_1_n_0; + wire lmr_ack; + wire lmr_ack_i_2_n_0; + wire lmr_ack_i_3_n_0; + wire lmr_req; + wire lmr_req_i_1__0_n_0; + wire lmr_req_i_1__1_n_0; + wire lmr_req_i_2__0_n_0; + wire lmr_req_i_2_n_0; + wire lmr_req_we_i_1__0_n_0; + wire mc_ack_pad_i; + wire mc_ack_r; + wire \mc_addr[0]_i_2_n_0 ; + wire \mc_addr[0]_i_3_n_0 ; + wire \mc_addr[10]_i_2_n_0 ; + wire \mc_addr[10]_i_3_n_0 ; + wire \mc_addr[10]_i_4_n_0 ; + wire \mc_addr[11]_i_2_n_0 ; + wire \mc_addr[11]_i_3_n_0 ; + wire \mc_addr[12]_i_2_n_0 ; + wire \mc_addr[12]_i_3_n_0 ; + wire \mc_addr[12]_i_4_n_0 ; + wire \mc_addr[12]_i_5_n_0 ; + wire \mc_addr[13]_i_2_n_0 ; + wire \mc_addr[14]_i_2_n_0 ; + wire \mc_addr[14]_i_3_n_0 ; + wire \mc_addr[14]_i_4_n_0 ; + wire \mc_addr[1]_i_2_n_0 ; + wire \mc_addr[1]_i_3_n_0 ; + wire \mc_addr[23]_i_2_n_0 ; + wire \mc_addr[23]_i_3_n_0 ; + wire \mc_addr[23]_i_4_n_0 ; + wire \mc_addr[2]_i_2_n_0 ; + wire \mc_addr[2]_i_3_n_0 ; + wire \mc_addr[2]_i_4_n_0 ; + wire \mc_addr[3]_i_2_n_0 ; + wire \mc_addr[3]_i_3_n_0 ; + wire \mc_addr[3]_i_4_n_0 ; + wire \mc_addr[4]_i_2_n_0 ; + wire \mc_addr[4]_i_3_n_0 ; + wire \mc_addr[4]_i_4_n_0 ; + wire \mc_addr[5]_i_2_n_0 ; + wire \mc_addr[5]_i_3_n_0 ; + wire \mc_addr[5]_i_4_n_0 ; + wire \mc_addr[6]_i_2_n_0 ; + wire \mc_addr[6]_i_3_n_0 ; + wire \mc_addr[6]_i_4_n_0 ; + wire \mc_addr[7]_i_2_n_0 ; + wire \mc_addr[7]_i_3_n_0 ; + wire \mc_addr[7]_i_4_n_0 ; + wire \mc_addr[8]_i_2_n_0 ; + wire \mc_addr[8]_i_3_n_0 ; + wire \mc_addr[8]_i_4_n_0 ; + wire \mc_addr[9]_i_2_n_0 ; + wire \mc_addr[9]_i_3_n_0 ; + wire \mc_addr[9]_i_4_n_0 ; + wire [23:0]mc_addr_d; + wire [23:0]mc_addr_pad_o; + wire mc_adsc__i_1_n_0; + wire mc_adsc__i_2_n_0; + wire mc_adsc__i_3_n_0; + wire mc_adsc__i_4_n_0; + wire mc_adsc__i_5_n_0; + wire mc_adsc_pad_o_; + wire mc_adv__i_1_n_0; + wire mc_adv__i_2_n_0; + wire mc_adv__i_3_n_0; + wire mc_adv_d; + wire mc_adv_pad_o_; + wire mc_bg_d; + wire mc_bg_i_2_n_0; + wire mc_bg_i_3_n_0; + wire mc_bg_i_4_n_0; + wire mc_bg_i_5_n_0; + wire mc_bg_pad_o; + wire mc_br_pad_i; + wire mc_br_r; + wire mc_c_oe_d; + wire mc_c_oe_i_2_n_0; + wire mc_c_oe_i_3_n_0; + wire mc_c_oe_i_4_n_0; + wire mc_c_oe_i_5_n_0; + wire mc_cas_pad_o_; + wire mc_cke_pad_o_; + wire mc_clk_i; + wire mc_coe_pad_coe_o; + wire \mc_cs_[0]_i_1_n_0 ; + wire \mc_cs_[0]_i_2_n_0 ; + wire \mc_cs_[1]_i_1_n_0 ; + wire \mc_cs_[1]_i_2_n_0 ; + wire \mc_cs_[1]_i_3_n_0 ; + wire \mc_cs_[1]_i_4_n_0 ; + wire \mc_cs_[1]_i_5_n_0 ; + wire [1:0]\^mc_cs_pad_o_ ; + wire [35:0]mc_data_ir; + wire [31:0]mc_data_o; + wire [31:0]mc_data_pad_i; + wire [31:0]mc_data_pad_o; + wire mc_doe_pad_doe_o; + wire [3:0]mc_dp_o; + wire mc_dp_o0; + wire \mc_dp_o[0]_i_1_n_0 ; + wire \mc_dp_o[0]_i_2_n_0 ; + wire \mc_dp_o[1]_i_1_n_0 ; + wire \mc_dp_o[1]_i_2_n_0 ; + wire \mc_dp_o[2]_i_1_n_0 ; + wire \mc_dp_o[2]_i_2_n_0 ; + wire \mc_dp_o[3]_i_2_n_0 ; + wire [3:0]mc_dp_pad_i; + wire [3:0]mc_dp_pad_o; + wire \mc_dqm[0]_i_1_n_0 ; + wire \mc_dqm[1]_i_1_n_0 ; + wire \mc_dqm[2]_i_1_n_0 ; + wire \mc_dqm[3]_i_1_n_0 ; + wire [3:0]mc_dqm_pad_o; + wire [3:0]mc_dqm_r; + wire [3:0]mc_dqm_r2; + wire mc_le_i_1_n_0; + wire mc_oe_pad_o_; + wire mc_ras_pad_o_; + wire mc_rp_pad_o_; + wire mc_sts_ir; + wire mc_sts_pad_i; + wire mc_vpen_pad_o; + wire mc_we_pad_o_; + wire mc_zz_pad_o; + wire mem_ack; + wire mem_ack_r; + wire mem_ack_r_i_10_n_0; + wire mem_ack_r_i_11_n_0; + wire mem_ack_r_i_12_n_0; + wire mem_ack_r_i_13_n_0; + wire mem_ack_r_i_14_n_0; + wire mem_ack_r_i_2_n_0; + wire mem_ack_r_i_3_n_0; + wire mem_ack_r_i_4_n_0; + wire mem_ack_r_i_5_n_0; + wire mem_ack_r_i_6_n_0; + wire mem_ack_r_i_7_n_0; + wire mem_ack_r_i_8_n_0; + wire mem_ack_r_i_9_n_0; + wire no_wb_cycle_i_2_n_0; + wire oe_; + wire oe__i_1_n_0; + wire oe__i_3_n_0; + wire oe__i_4_n_0; + wire oe__i_5_n_0; + wire oe__reg_i_2_n_0; + wire \out_r[0]_i_1_n_0 ; + wire [10:0]p_0_in; + wire [3:0]p_0_in__0; + wire [7:0]p_0_in__1; + wire [7:0]p_0_in__2; + wire pack_le0; + wire pack_le0_i_2_n_0; + wire pack_le0_i_3_n_0; + wire pack_le1; + wire pack_le2; + wire pack_le2_i_2_n_0; + wire [31:0]poc_o; + wire \ps_cnt[5]_i_2_n_0 ; + wire \ps_cnt[7]_i_1_n_0 ; + wire \ps_cnt[7]_i_3_n_0 ; + wire [35:0]r0; + wire [35:0]r1; + wire [35:0]r2; + wire [35:0]r3; + wire ras_; + wire \rd_adr[0]_i_1_n_0 ; + wire \rd_adr[1]_i_1_n_0 ; + wire \rd_adr[2]_i_1_n_0 ; + wire \rd_adr[3]_i_1_n_0 ; + wire \rd_adr[3]_i_2_n_0 ; + wire resume_req_i; + wire rfr_ack; + wire rfr_ack_r_i_1_n_0; + wire rfr_ack_r_i_2_n_0; + wire rfr_ack_r_i_3_n_0; + wire rfr_ack_r_i_4_n_0; + wire rfr_ack_r_i_5_n_0; + wire rfr_ack_r_i_6_n_0; + wire rfr_ack_r_i_7_n_0; + wire rfr_ce_i_2_n_0; + wire rfr_clr_i_2_n_0; + wire rfr_clr_i_3_n_0; + wire rfr_clr_i_4_n_0; + wire \rfr_cnt[2]_i_1_n_0 ; + wire \rfr_cnt[4]_i_1_n_0 ; + wire \rfr_cnt[6]_i_1_n_0 ; + wire \rfr_cnt[7]_i_1_n_0 ; + wire \rfr_cnt[7]_i_3_n_0 ; + wire rfr_early_i_2_n_0; + wire rfr_early_i_3_n_0; + wire rfr_en_i_1_n_0; + wire rfr_en_i_2_n_0; + wire [7:0]rfr_ps_val; + wire rfr_req; + wire rfr_req_i_1_n_0; + wire rmw_en_i_1_n_0; + wire row0_same_carry__0_i_1__0_n_0; + wire row0_same_carry__0_i_1_n_0; + wire row0_same_carry_i_1__0_n_0; + wire row0_same_carry_i_1_n_0; + wire row0_same_carry_i_2__0_n_0; + wire row0_same_carry_i_2_n_0; + wire row0_same_carry_i_3__0_n_0; + wire row0_same_carry_i_3_n_0; + wire row0_same_carry_i_4__0_n_0; + wire row0_same_carry_i_4_n_0; + wire row1_same_carry__0_i_1__0_n_0; + wire row1_same_carry__0_i_1_n_0; + wire row1_same_carry_i_1__0_n_0; + wire row1_same_carry_i_1_n_0; + wire row1_same_carry_i_2__0_n_0; + wire row1_same_carry_i_2_n_0; + wire row1_same_carry_i_3__0_n_0; + wire row1_same_carry_i_3_n_0; + wire row1_same_carry_i_4__0_n_0; + wire row1_same_carry_i_4_n_0; + wire row2_same_carry__0_i_1__0_n_0; + wire row2_same_carry__0_i_1_n_0; + wire row2_same_carry_i_1__0_n_0; + wire row2_same_carry_i_1_n_0; + wire row2_same_carry_i_2__0_n_0; + wire row2_same_carry_i_2_n_0; + wire row2_same_carry_i_3__0_n_0; + wire row2_same_carry_i_3_n_0; + wire row2_same_carry_i_4__0_n_0; + wire row2_same_carry_i_4_n_0; + wire row3_same_carry__0_i_1__0_n_0; + wire row3_same_carry__0_i_1_n_0; + wire row3_same_carry_i_1__0_n_0; + wire row3_same_carry_i_1_n_0; + wire row3_same_carry_i_2__0_n_0; + wire row3_same_carry_i_2_n_0; + wire row3_same_carry_i_3__0_n_0; + wire row3_same_carry_i_3_n_0; + wire row3_same_carry_i_4__0_n_0; + wire row3_same_carry_i_4_n_0; + wire [12:0]row_adr; + wire \row_adr[0]_i_1_n_0 ; + wire \row_adr[10]_i_1_n_0 ; + wire \row_adr[10]_i_2_n_0 ; + wire \row_adr[10]_i_3_n_0 ; + wire \row_adr[11]_i_2_n_0 ; + wire \row_adr[11]_i_3_n_0 ; + wire \row_adr[12]_i_2_n_0 ; + wire \row_adr[12]_i_3_n_0 ; + wire \row_adr[12]_i_4_n_0 ; + wire \row_adr[12]_i_5_n_0 ; + wire \row_adr[1]_i_1_n_0 ; + wire \row_adr[2]_i_1_n_0 ; + wire \row_adr[2]_i_2_n_0 ; + wire \row_adr[3]_i_1_n_0 ; + wire \row_adr[3]_i_2_n_0 ; + wire \row_adr[4]_i_1_n_0 ; + wire \row_adr[4]_i_2_n_0 ; + wire \row_adr[5]_i_1_n_0 ; + wire \row_adr[5]_i_2_n_0 ; + wire \row_adr[6]_i_1_n_0 ; + wire \row_adr[6]_i_2_n_0 ; + wire \row_adr[7]_i_1_n_0 ; + wire \row_adr[7]_i_2_n_0 ; + wire \row_adr[8]_i_1_n_0 ; + wire \row_adr[8]_i_2_n_0 ; + wire \row_adr[9]_i_1_n_0 ; + wire \row_adr[9]_i_2_n_0 ; + wire \row_adr[9]_i_3_n_0 ; + wire \row_adr_reg[11]_i_1_n_0 ; + wire \row_adr_reg[12]_i_1_n_0 ; + wire row_same; + wire row_same_i_2_n_0; + wire row_same_i_3_n_0; + wire rst_i; + wire rst_r1; + wire rst_r3; + wire [2:0]sel0; + wire [10:1]sp_csc; + wire \sp_csc[10]_i_1_n_0 ; + wire \sp_csc[1]_i_1_n_0 ; + wire \sp_csc[2]_i_1_n_0 ; + wire \sp_csc[3]_i_1_n_0 ; + wire \sp_csc[4]_i_1_n_0 ; + wire \sp_csc[5]_i_1_n_0 ; + wire \sp_csc[6]_i_1_n_0 ; + wire \sp_csc[7]_i_1_n_0 ; + wire \sp_csc[9]_i_1_n_0 ; + wire [27:0]sp_tms; + wire \sp_tms[0]_i_1_n_0 ; + wire \sp_tms[10]_i_1_n_0 ; + wire \sp_tms[11]_i_1_n_0 ; + wire \sp_tms[12]_i_1_n_0 ; + wire \sp_tms[13]_i_1_n_0 ; + wire \sp_tms[14]_i_1_n_0 ; + wire \sp_tms[15]_i_1_n_0 ; + wire \sp_tms[16]_i_1_n_0 ; + wire \sp_tms[17]_i_1_n_0 ; + wire \sp_tms[18]_i_1_n_0 ; + wire \sp_tms[19]_i_1_n_0 ; + wire \sp_tms[1]_i_1_n_0 ; + wire \sp_tms[20]_i_1_n_0 ; + wire \sp_tms[21]_i_1_n_0 ; + wire \sp_tms[22]_i_1_n_0 ; + wire \sp_tms[23]_i_1_n_0 ; + wire \sp_tms[24]_i_1_n_0 ; + wire \sp_tms[25]_i_1_n_0 ; + wire \sp_tms[26]_i_1_n_0 ; + wire \sp_tms[27]_i_1_n_0 ; + wire \sp_tms[2]_i_1_n_0 ; + wire \sp_tms[3]_i_1_n_0 ; + wire \sp_tms[4]_i_1_n_0 ; + wire \sp_tms[5]_i_1_n_0 ; + wire \sp_tms[6]_i_1_n_0 ; + wire \sp_tms[7]_i_1_n_0 ; + wire \sp_tms[8]_i_1_n_0 ; + wire \sp_tms[9]_i_1_n_0 ; + wire [1:0]spec_req_cs; + wire [23:0]sram_addr; + wire sreq_cs_le; + wire susp_req_i; + wire susp_sel; + wire susp_sel_r_i_1_n_0; + wire susp_sel_r_i_2_n_0; + wire suspended_i_2_n_0; + wire suspended_o; + wire \timer2[0]_i_1_n_0 ; + wire \timer2[0]_i_2_n_0 ; + wire \timer2[0]_i_3_n_0 ; + wire \timer2[0]_i_4_n_0 ; + wire \timer2[1]_i_1_n_0 ; + wire \timer2[1]_i_2_n_0 ; + wire \timer2[1]_i_3_n_0 ; + wire \timer2[1]_i_4_n_0 ; + wire \timer2[1]_i_5_n_0 ; + wire \timer2[2]_i_1_n_0 ; + wire \timer2[2]_i_2_n_0 ; + wire \timer2[2]_i_3_n_0 ; + wire \timer2[2]_i_4_n_0 ; + wire \timer2[2]_i_5_n_0 ; + wire \timer2[3]_i_1_n_0 ; + wire \timer2[3]_i_2_n_0 ; + wire \timer2[3]_i_3_n_0 ; + wire \timer2[3]_i_4_n_0 ; + wire \timer2[3]_i_5_n_0 ; + wire \timer2[3]_i_6_n_0 ; + wire \timer2[3]_i_7_n_0 ; + wire \timer2[4]_i_1_n_0 ; + wire \timer2[4]_i_2_n_0 ; + wire \timer2[4]_i_3_n_0 ; + wire \timer2[4]_i_4_n_0 ; + wire \timer2[4]_i_5_n_0 ; + wire \timer2[4]_i_6_n_0 ; + wire \timer2[5]_i_1_n_0 ; + wire \timer2[5]_i_2_n_0 ; + wire \timer2[5]_i_3_n_0 ; + wire \timer2[5]_i_4_n_0 ; + wire \timer2[5]_i_5_n_0 ; + wire \timer2[5]_i_6_n_0 ; + wire \timer2[6]_i_1_n_0 ; + wire \timer2[6]_i_2_n_0 ; + wire \timer2[6]_i_3_n_0 ; + wire \timer2[6]_i_4_n_0 ; + wire \timer2[6]_i_5_n_0 ; + wire \timer2[6]_i_6_n_0 ; + wire \timer2[7]_i_1_n_0 ; + wire \timer2[7]_i_2_n_0 ; + wire \timer2[7]_i_3_n_0 ; + wire \timer2[7]_i_4_n_0 ; + wire \timer2[7]_i_5_n_0 ; + wire \timer2[7]_i_6_n_0 ; + wire \timer2[7]_i_7_n_0 ; + wire \timer2[7]_i_8_n_0 ; + wire \timer2[8]_i_10_n_0 ; + wire \timer2[8]_i_11_n_0 ; + wire \timer2[8]_i_12_n_0 ; + wire \timer2[8]_i_2_n_0 ; + wire \timer2[8]_i_3_n_0 ; + wire \timer2[8]_i_4_n_0 ; + wire \timer2[8]_i_5_n_0 ; + wire \timer2[8]_i_6_n_0 ; + wire \timer2[8]_i_7_n_0 ; + wire \timer2[8]_i_8_n_0 ; + wire \timer2[8]_i_9_n_0 ; + wire \timer[0]_i_1_n_0 ; + wire \timer[0]_i_2_n_0 ; + wire \timer[0]_i_3_n_0 ; + wire \timer[0]_i_4_n_0 ; + wire \timer[0]_i_5_n_0 ; + wire \timer[0]_i_6_n_0 ; + wire \timer[0]_i_7_n_0 ; + wire \timer[0]_i_8_n_0 ; + wire \timer[0]_i_9_n_0 ; + wire \timer[1]_i_1_n_0 ; + wire \timer[1]_i_2_n_0 ; + wire \timer[1]_i_3_n_0 ; + wire \timer[1]_i_4_n_0 ; + wire \timer[1]_i_5_n_0 ; + wire \timer[1]_i_6_n_0 ; + wire \timer[1]_i_7_n_0 ; + wire \timer[1]_i_8_n_0 ; + wire \timer[1]_i_9_n_0 ; + wire \timer[2]_i_10_n_0 ; + wire \timer[2]_i_11_n_0 ; + wire \timer[2]_i_12_n_0 ; + wire \timer[2]_i_13_n_0 ; + wire \timer[2]_i_14_n_0 ; + wire \timer[2]_i_15_n_0 ; + wire \timer[2]_i_16_n_0 ; + wire \timer[2]_i_17_n_0 ; + wire \timer[2]_i_18_n_0 ; + wire \timer[2]_i_19_n_0 ; + wire \timer[2]_i_1_n_0 ; + wire \timer[2]_i_2_n_0 ; + wire \timer[2]_i_3_n_0 ; + wire \timer[2]_i_4_n_0 ; + wire \timer[2]_i_5_n_0 ; + wire \timer[2]_i_6_n_0 ; + wire \timer[2]_i_7_n_0 ; + wire \timer[2]_i_8_n_0 ; + wire \timer[2]_i_9_n_0 ; + wire \timer[3]_i_10_n_0 ; + wire \timer[3]_i_11_n_0 ; + wire \timer[3]_i_12_n_0 ; + wire \timer[3]_i_13_n_0 ; + wire \timer[3]_i_1_n_0 ; + wire \timer[3]_i_2_n_0 ; + wire \timer[3]_i_3_n_0 ; + wire \timer[3]_i_4_n_0 ; + wire \timer[3]_i_5_n_0 ; + wire \timer[3]_i_6_n_0 ; + wire \timer[3]_i_7_n_0 ; + wire \timer[3]_i_8_n_0 ; + wire \timer[3]_i_9_n_0 ; + wire \timer[4]_i_1_n_0 ; + wire \timer[4]_i_2_n_0 ; + wire \timer[4]_i_3_n_0 ; + wire \timer[5]_i_1_n_0 ; + wire \timer[5]_i_2_n_0 ; + wire \timer[5]_i_3_n_0 ; + wire \timer[6]_i_1_n_0 ; + wire \timer[6]_i_2_n_0 ; + wire \timer[7]_i_10_n_0 ; + wire \timer[7]_i_11_n_0 ; + wire \timer[7]_i_12_n_0 ; + wire \timer[7]_i_13_n_0 ; + wire \timer[7]_i_14_n_0 ; + wire \timer[7]_i_15_n_0 ; + wire \timer[7]_i_16_n_0 ; + wire \timer[7]_i_17_n_0 ; + wire \timer[7]_i_18_n_0 ; + wire \timer[7]_i_1_n_0 ; + wire \timer[7]_i_2_n_0 ; + wire \timer[7]_i_3_n_0 ; + wire \timer[7]_i_4_n_0 ; + wire \timer[7]_i_5_n_0 ; + wire \timer[7]_i_6_n_0 ; + wire \timer[7]_i_7_n_0 ; + wire \timer[7]_i_8_n_0 ; + wire \timer[7]_i_9_n_0 ; + wire [31:0]tms; + wire \tms[0]_i_1_n_0 ; + wire \tms[10]_i_1_n_0 ; + wire \tms[11]_i_1_n_0 ; + wire \tms[12]_i_1_n_0 ; + wire \tms[13]_i_1_n_0 ; + wire \tms[14]_i_1_n_0 ; + wire \tms[15]_i_1_n_0 ; + wire \tms[16]_i_1_n_0 ; + wire \tms[17]_i_1_n_0 ; + wire \tms[18]_i_1_n_0 ; + wire \tms[19]_i_1_n_0 ; + wire \tms[1]_i_1_n_0 ; + wire \tms[20]_i_1_n_0 ; + wire \tms[21]_i_1_n_0 ; + wire \tms[22]_i_1_n_0 ; + wire \tms[23]_i_1_n_0 ; + wire \tms[24]_i_1_n_0 ; + wire \tms[25]_i_1_n_0 ; + wire \tms[26]_i_1_n_0 ; + wire \tms[27]_i_1_n_0 ; + wire \tms[27]_i_2_n_0 ; + wire \tms[2]_i_1_n_0 ; + wire \tms[3]_i_1_n_0 ; + wire \tms[4]_i_1_n_0 ; + wire \tms[5]_i_1_n_0 ; + wire \tms[6]_i_1_n_0 ; + wire \tms[7]_i_1_n_0 ; + wire \tms[8]_i_1_n_0 ; + wire \tms[9]_i_1_n_0 ; + wire \u0/cs[1]_i_1_n_0 ; + wire [7:0]\u0/csc_mask ; + wire \u0/csc_mask_r0 ; + wire \u0/csc_mask_r_reg_n_0_[10] ; + wire \u0/csc_mask_r_reg_n_0_[8] ; + wire \u0/csc_mask_r_reg_n_0_[9] ; + wire \u0/csr_r20 ; + wire \u0/csr_r_reg_n_0_[0] ; + wire \u0/csr_r_reg_n_0_[3] ; + wire \u0/csr_r_reg_n_0_[4] ; + wire \u0/csr_r_reg_n_0_[5] ; + wire \u0/csr_r_reg_n_0_[6] ; + wire \u0/csr_r_reg_n_0_[7] ; + wire \u0/init_ack_r ; + wire \u0/init_req01_out ; + wire \u0/init_req_we ; + wire \u0/inited ; + wire \u0/lmr_ack_r ; + wire \u0/lmr_req00_out ; + wire \u0/lmr_req_we ; + wire [3:0]\u0/p_0_in ; + wire \u0/p_0_in1_in ; + wire \u0/rf_we ; + wire \u0/rf_we0 ; + wire \u0/rst_r2 ; + wire [5:5]\u0/sel0 ; + wire \u0/spec_req_cs[0]_i_1_n_0 ; + wire \u0/spec_req_cs[1]_i_1_n_0 ; + wire [0:0]\u0/spec_req_cs_t ; + wire \u0/sreq_cs_le0 ; + wire \u0/tms0 ; + wire \u0/tms_reg_n_0_[0] ; + wire \u0/tms_reg_n_0_[10] ; + wire \u0/tms_reg_n_0_[11] ; + wire \u0/tms_reg_n_0_[12] ; + wire \u0/tms_reg_n_0_[13] ; + wire \u0/tms_reg_n_0_[14] ; + wire \u0/tms_reg_n_0_[15] ; + wire \u0/tms_reg_n_0_[16] ; + wire \u0/tms_reg_n_0_[17] ; + wire \u0/tms_reg_n_0_[18] ; + wire \u0/tms_reg_n_0_[19] ; + wire \u0/tms_reg_n_0_[1] ; + wire \u0/tms_reg_n_0_[20] ; + wire \u0/tms_reg_n_0_[21] ; + wire \u0/tms_reg_n_0_[22] ; + wire \u0/tms_reg_n_0_[23] ; + wire \u0/tms_reg_n_0_[24] ; + wire \u0/tms_reg_n_0_[25] ; + wire \u0/tms_reg_n_0_[26] ; + wire \u0/tms_reg_n_0_[27] ; + wire \u0/tms_reg_n_0_[2] ; + wire \u0/tms_reg_n_0_[3] ; + wire \u0/tms_reg_n_0_[4] ; + wire \u0/tms_reg_n_0_[5] ; + wire \u0/tms_reg_n_0_[6] ; + wire \u0/tms_reg_n_0_[7] ; + wire \u0/tms_reg_n_0_[8] ; + wire \u0/tms_reg_n_0_[9] ; + wire \u0/u0/csc_reg_n_0_[0] ; + wire \u0/u0/csc_reg_n_0_[10] ; + wire \u0/u0/csc_reg_n_0_[11] ; + wire \u0/u0/csc_reg_n_0_[12] ; + wire \u0/u0/csc_reg_n_0_[13] ; + wire \u0/u0/csc_reg_n_0_[14] ; + wire \u0/u0/csc_reg_n_0_[15] ; + wire \u0/u0/csc_reg_n_0_[16] ; + wire \u0/u0/csc_reg_n_0_[17] ; + wire \u0/u0/csc_reg_n_0_[18] ; + wire \u0/u0/csc_reg_n_0_[19] ; + wire \u0/u0/csc_reg_n_0_[1] ; + wire \u0/u0/csc_reg_n_0_[20] ; + wire \u0/u0/csc_reg_n_0_[21] ; + wire \u0/u0/csc_reg_n_0_[22] ; + wire \u0/u0/csc_reg_n_0_[23] ; + wire \u0/u0/csc_reg_n_0_[24] ; + wire \u0/u0/csc_reg_n_0_[25] ; + wire \u0/u0/csc_reg_n_0_[26] ; + wire \u0/u0/csc_reg_n_0_[27] ; + wire \u0/u0/csc_reg_n_0_[28] ; + wire \u0/u0/csc_reg_n_0_[29] ; + wire \u0/u0/csc_reg_n_0_[2] ; + wire \u0/u0/csc_reg_n_0_[30] ; + wire \u0/u0/csc_reg_n_0_[31] ; + wire \u0/u0/csc_reg_n_0_[3] ; + wire \u0/u0/csc_reg_n_0_[4] ; + wire \u0/u0/csc_reg_n_0_[5] ; + wire \u0/u0/csc_reg_n_0_[6] ; + wire \u0/u0/csc_reg_n_0_[7] ; + wire \u0/u0/csc_reg_n_0_[8] ; + wire \u0/u0/csc_reg_n_0_[9] ; + wire \u0/u0/init_req_reg_n_0 ; + wire \u0/u0/lmr_req_reg_n_0 ; + wire \u0/u1/csc_reg_n_0_[0] ; + wire \u0/u1/csc_reg_n_0_[10] ; + wire \u0/u1/csc_reg_n_0_[11] ; + wire \u0/u1/csc_reg_n_0_[12] ; + wire \u0/u1/csc_reg_n_0_[13] ; + wire \u0/u1/csc_reg_n_0_[14] ; + wire \u0/u1/csc_reg_n_0_[15] ; + wire \u0/u1/csc_reg_n_0_[16] ; + wire \u0/u1/csc_reg_n_0_[17] ; + wire \u0/u1/csc_reg_n_0_[18] ; + wire \u0/u1/csc_reg_n_0_[19] ; + wire \u0/u1/csc_reg_n_0_[1] ; + wire \u0/u1/csc_reg_n_0_[20] ; + wire \u0/u1/csc_reg_n_0_[21] ; + wire \u0/u1/csc_reg_n_0_[22] ; + wire \u0/u1/csc_reg_n_0_[23] ; + wire \u0/u1/csc_reg_n_0_[24] ; + wire \u0/u1/csc_reg_n_0_[25] ; + wire \u0/u1/csc_reg_n_0_[26] ; + wire \u0/u1/csc_reg_n_0_[27] ; + wire \u0/u1/csc_reg_n_0_[28] ; + wire \u0/u1/csc_reg_n_0_[29] ; + wire \u0/u1/csc_reg_n_0_[2] ; + wire \u0/u1/csc_reg_n_0_[30] ; + wire \u0/u1/csc_reg_n_0_[31] ; + wire \u0/u1/csc_reg_n_0_[3] ; + wire \u0/u1/csc_reg_n_0_[4] ; + wire \u0/u1/csc_reg_n_0_[5] ; + wire \u0/u1/csc_reg_n_0_[6] ; + wire \u0/u1/csc_reg_n_0_[7] ; + wire \u0/u1/csc_reg_n_0_[8] ; + wire \u0/u1/csc_reg_n_0_[9] ; + wire \u0/u1/init_req_reg_n_0 ; + wire \u0/u1/init_req_we_reg_n_0 ; + wire \u0/u1/inited_reg_n_0 ; + wire \u0/u1/lmr_req_reg_n_0 ; + wire \u0/u1/lmr_req_we_reg_n_0 ; + wire \u0/u1/tms_reg_n_0_[0] ; + wire \u0/u1/tms_reg_n_0_[10] ; + wire \u0/u1/tms_reg_n_0_[11] ; + wire \u0/u1/tms_reg_n_0_[12] ; + wire \u0/u1/tms_reg_n_0_[13] ; + wire \u0/u1/tms_reg_n_0_[14] ; + wire \u0/u1/tms_reg_n_0_[15] ; + wire \u0/u1/tms_reg_n_0_[16] ; + wire \u0/u1/tms_reg_n_0_[17] ; + wire \u0/u1/tms_reg_n_0_[18] ; + wire \u0/u1/tms_reg_n_0_[19] ; + wire \u0/u1/tms_reg_n_0_[1] ; + wire \u0/u1/tms_reg_n_0_[20] ; + wire \u0/u1/tms_reg_n_0_[21] ; + wire \u0/u1/tms_reg_n_0_[22] ; + wire \u0/u1/tms_reg_n_0_[23] ; + wire \u0/u1/tms_reg_n_0_[24] ; + wire \u0/u1/tms_reg_n_0_[25] ; + wire \u0/u1/tms_reg_n_0_[26] ; + wire \u0/u1/tms_reg_n_0_[27] ; + wire \u0/u1/tms_reg_n_0_[28] ; + wire \u0/u1/tms_reg_n_0_[29] ; + wire \u0/u1/tms_reg_n_0_[2] ; + wire \u0/u1/tms_reg_n_0_[30] ; + wire \u0/u1/tms_reg_n_0_[31] ; + wire \u0/u1/tms_reg_n_0_[3] ; + wire \u0/u1/tms_reg_n_0_[4] ; + wire \u0/u1/tms_reg_n_0_[5] ; + wire \u0/u1/tms_reg_n_0_[6] ; + wire \u0/u1/tms_reg_n_0_[7] ; + wire \u0/u1/tms_reg_n_0_[8] ; + wire \u0/u1/tms_reg_n_0_[9] ; + wire [9:8]\u1/col_adr ; + wire \u1/u0/out_r0_carry__0_n_0 ; + wire \u1/u0/out_r0_carry__0_n_1 ; + wire \u1/u0/out_r0_carry__0_n_2 ; + wire \u1/u0/out_r0_carry__0_n_3 ; + wire \u1/u0/out_r0_carry__0_n_4 ; + wire \u1/u0/out_r0_carry__0_n_5 ; + wire \u1/u0/out_r0_carry__0_n_6 ; + wire \u1/u0/out_r0_carry__0_n_7 ; + wire \u1/u0/out_r0_carry__1_n_0 ; + wire \u1/u0/out_r0_carry__1_n_2 ; + wire \u1/u0/out_r0_carry__1_n_3 ; + wire \u1/u0/out_r0_carry__1_n_5 ; + wire \u1/u0/out_r0_carry__1_n_6 ; + wire \u1/u0/out_r0_carry__1_n_7 ; + wire \u1/u0/out_r0_carry_n_0 ; + wire \u1/u0/out_r0_carry_n_1 ; + wire \u1/u0/out_r0_carry_n_2 ; + wire \u1/u0/out_r0_carry_n_3 ; + wire \u1/u0/out_r0_carry_n_4 ; + wire \u1/u0/out_r0_carry_n_5 ; + wire \u1/u0/out_r0_carry_n_6 ; + wire \u1/u0/out_r0_carry_n_7 ; + wire \u1/u0/out_r_reg_n_0_[0] ; + wire \u1/u0/out_r_reg_n_0_[10] ; + wire \u1/u0/out_r_reg_n_0_[11] ; + wire \u1/u0/out_r_reg_n_0_[1] ; + wire \u1/u0/out_r_reg_n_0_[2] ; + wire \u1/u0/out_r_reg_n_0_[3] ; + wire \u1/u0/out_r_reg_n_0_[4] ; + wire \u1/u0/out_r_reg_n_0_[5] ; + wire \u1/u0/out_r_reg_n_0_[6] ; + wire \u1/u0/out_r_reg_n_0_[7] ; + wire \u1/u0/out_r_reg_n_0_[8] ; + wire \u1/u0/out_r_reg_n_0_[9] ; + wire \u2/bank0_open ; + wire \u2/bank0_open0 ; + wire \u2/bank1_open ; + wire \u2/bank1_open0 ; + wire \u2/bank2_open ; + wire \u2/bank2_open0 ; + wire \u2/bank3_open ; + wire \u2/bank3_open0 ; + wire \u2/bank_open0 ; + wire \u2/row0_same ; + wire \u2/row1_same ; + wire \u2/row2_same ; + wire \u2/row3_same ; + wire \u2/row_same0 ; + wire \u2/u0/b0_last_row_reg_n_0_[0] ; + wire \u2/u0/b0_last_row_reg_n_0_[10] ; + wire \u2/u0/b0_last_row_reg_n_0_[11] ; + wire \u2/u0/b0_last_row_reg_n_0_[12] ; + wire \u2/u0/b0_last_row_reg_n_0_[1] ; + wire \u2/u0/b0_last_row_reg_n_0_[2] ; + wire \u2/u0/b0_last_row_reg_n_0_[3] ; + wire \u2/u0/b0_last_row_reg_n_0_[4] ; + wire \u2/u0/b0_last_row_reg_n_0_[5] ; + wire \u2/u0/b0_last_row_reg_n_0_[6] ; + wire \u2/u0/b0_last_row_reg_n_0_[7] ; + wire \u2/u0/b0_last_row_reg_n_0_[8] ; + wire \u2/u0/b0_last_row_reg_n_0_[9] ; + wire \u2/u0/b1_last_row_reg_n_0_[0] ; + wire \u2/u0/b1_last_row_reg_n_0_[10] ; + wire \u2/u0/b1_last_row_reg_n_0_[11] ; + wire \u2/u0/b1_last_row_reg_n_0_[12] ; + wire \u2/u0/b1_last_row_reg_n_0_[1] ; + wire \u2/u0/b1_last_row_reg_n_0_[2] ; + wire \u2/u0/b1_last_row_reg_n_0_[3] ; + wire \u2/u0/b1_last_row_reg_n_0_[4] ; + wire \u2/u0/b1_last_row_reg_n_0_[5] ; + wire \u2/u0/b1_last_row_reg_n_0_[6] ; + wire \u2/u0/b1_last_row_reg_n_0_[7] ; + wire \u2/u0/b1_last_row_reg_n_0_[8] ; + wire \u2/u0/b1_last_row_reg_n_0_[9] ; + wire \u2/u0/b2_last_row_reg_n_0_[0] ; + wire \u2/u0/b2_last_row_reg_n_0_[10] ; + wire \u2/u0/b2_last_row_reg_n_0_[11] ; + wire \u2/u0/b2_last_row_reg_n_0_[12] ; + wire \u2/u0/b2_last_row_reg_n_0_[1] ; + wire \u2/u0/b2_last_row_reg_n_0_[2] ; + wire \u2/u0/b2_last_row_reg_n_0_[3] ; + wire \u2/u0/b2_last_row_reg_n_0_[4] ; + wire \u2/u0/b2_last_row_reg_n_0_[5] ; + wire \u2/u0/b2_last_row_reg_n_0_[6] ; + wire \u2/u0/b2_last_row_reg_n_0_[7] ; + wire \u2/u0/b2_last_row_reg_n_0_[8] ; + wire \u2/u0/b2_last_row_reg_n_0_[9] ; + wire \u2/u0/b3_last_row_reg_n_0_[0] ; + wire \u2/u0/b3_last_row_reg_n_0_[10] ; + wire \u2/u0/b3_last_row_reg_n_0_[11] ; + wire \u2/u0/b3_last_row_reg_n_0_[12] ; + wire \u2/u0/b3_last_row_reg_n_0_[1] ; + wire \u2/u0/b3_last_row_reg_n_0_[2] ; + wire \u2/u0/b3_last_row_reg_n_0_[3] ; + wire \u2/u0/b3_last_row_reg_n_0_[4] ; + wire \u2/u0/b3_last_row_reg_n_0_[5] ; + wire \u2/u0/b3_last_row_reg_n_0_[6] ; + wire \u2/u0/b3_last_row_reg_n_0_[7] ; + wire \u2/u0/b3_last_row_reg_n_0_[8] ; + wire \u2/u0/b3_last_row_reg_n_0_[9] ; + wire \u2/u0/row0_same_carry_n_0 ; + wire \u2/u0/row0_same_carry_n_1 ; + wire \u2/u0/row0_same_carry_n_2 ; + wire \u2/u0/row0_same_carry_n_3 ; + wire \u2/u0/row1_same_carry_n_0 ; + wire \u2/u0/row1_same_carry_n_1 ; + wire \u2/u0/row1_same_carry_n_2 ; + wire \u2/u0/row1_same_carry_n_3 ; + wire \u2/u0/row2_same_carry_n_0 ; + wire \u2/u0/row2_same_carry_n_1 ; + wire \u2/u0/row2_same_carry_n_2 ; + wire \u2/u0/row2_same_carry_n_3 ; + wire \u2/u0/row3_same_carry_n_0 ; + wire \u2/u0/row3_same_carry_n_1 ; + wire \u2/u0/row3_same_carry_n_2 ; + wire \u2/u0/row3_same_carry_n_3 ; + wire \u2/u1/bank0_open_reg_n_0 ; + wire \u2/u1/bank1_open_reg_n_0 ; + wire \u2/u1/bank2_open_reg_n_0 ; + wire \u2/u1/bank3_open_reg_n_0 ; + wire \u2/u1/row0_same_carry__0_n_3 ; + wire \u2/u1/row0_same_carry_n_0 ; + wire \u2/u1/row0_same_carry_n_1 ; + wire \u2/u1/row0_same_carry_n_2 ; + wire \u2/u1/row0_same_carry_n_3 ; + wire \u2/u1/row1_same_carry__0_n_3 ; + wire \u2/u1/row1_same_carry_n_0 ; + wire \u2/u1/row1_same_carry_n_1 ; + wire \u2/u1/row1_same_carry_n_2 ; + wire \u2/u1/row1_same_carry_n_3 ; + wire \u2/u1/row2_same_carry__0_n_3 ; + wire \u2/u1/row2_same_carry_n_0 ; + wire \u2/u1/row2_same_carry_n_1 ; + wire \u2/u1/row2_same_carry_n_2 ; + wire \u2/u1/row2_same_carry_n_3 ; + wire \u2/u1/row3_same_carry__0_n_3 ; + wire \u2/u1/row3_same_carry_n_0 ; + wire \u2/u1/row3_same_carry_n_1 ; + wire \u2/u1/row3_same_carry_n_2 ; + wire \u2/u1/row3_same_carry_n_3 ; + wire \u3/mc_data_o0 ; + wire \u3/u0/p_0_in ; + wire \u3/u0/p_0_in0_in ; + wire \u3/u0/p_0_in1_in ; + wire \u3/u0/r00 ; + wire \u3/u0/r10 ; + wire \u3/u0/r20 ; + wire \u3/u0/r30 ; + wire [3:0]\u3/u0/rd_adr ; + wire \u3/u0/wr_adr_reg_n_0_[0] ; + wire \u4/ps_cnt_clr ; + wire \u4/ps_cnt_clr01_in ; + wire [7:0]\u4/ps_cnt_reg ; + wire \u4/rfr_ce ; + wire \u4/rfr_clr ; + wire \u4/rfr_clr_reg_n_0 ; + wire [0:0]\u4/rfr_cnt_reg ; + wire [7:1]\u4/rfr_cnt_reg__0 ; + wire \u4/rfr_early ; + wire \u4/rfr_en ; + wire [3:0]\u5/ack_cnt_reg ; + wire \u5/ap_en ; + wire \u5/burst_act077_in ; + wire \u5/burst_act_rd ; + wire \u5/burst_cnt_ld ; + wire \u5/burst_cnt_ld_4 ; + wire [10:0]\u5/burst_cnt_reg ; + wire \u5/cke_0 ; + wire \u5/cke_o_del ; + wire \u5/cke_o_r2_reg_srl2_n_0 ; + wire \u5/cke_r ; + wire [2:0]\u5/cmd ; + wire \u5/cmd_a10_r ; + wire \u5/cmd_asserted ; + wire \u5/cmd_asserted2 ; + wire [3:0]\u5/cmd_del ; + wire [3:0]\u5/cmd_r ; + wire \u5/cnt ; + wire \u5/cnt_next ; + wire \u5/cs_le_r ; + wire \u5/cs_le_r1 ; + wire \u5/data_oe_r ; + wire \u5/data_oe_r2 ; + wire \u5/dv_r ; + wire \u5/ir_cnt_dec ; + wire \u5/ir_cnt_done ; + wire \u5/ir_cnt_ld ; + wire [3:0]\u5/ir_cnt_reg ; + wire \u5/lmr_ack_d ; + wire \u5/lookup_ready1 ; + wire \u5/lookup_ready10 ; + wire \u5/lookup_ready2 ; + wire \u5/lookup_ready20 ; + wire \u5/mc_adv_r ; + wire \u5/mc_adv_r1 ; + wire \u5/mc_c_oe_d ; + wire \u5/mc_le ; + wire \u5/mem_ack_r ; + wire \u5/no_wb_cycle ; + wire \u5/p_65_in ; + wire \u5/pack_le0_d ; + wire \u5/pack_le1_d ; + wire \u5/pack_le2_d ; + wire \u5/resume_req_r ; + wire \u5/rsts ; + wire \u5/rsts1 ; + wire [6:0]\u5/state ; + wire \u5/susp_req_r ; + wire \u5/suspended_d ; + wire [7:0]\u5/timer ; + wire [8:0]\u5/timer2 ; + wire \u5/timer20 ; + wire \u5/timer_is_zero ; + wire \u5/tmr2_done ; + wire \u5/tmr2_done0 ; + wire \u5/tmr_done ; + wire \u5/wb_cycle_set ; + wire \u5/wb_stb_first_reg_n_0 ; + wire \u5/wb_wait_r ; + wire \u5/wb_wait_r2 ; + wire \u5/wb_write_go_r ; + wire \u5/wr_set ; + wire \u6/read_go_r ; + wire \u6/read_go_r0 ; + wire \u6/read_go_r1 ; + wire \u6/read_go_r10 ; + wire \u6/rmw_en ; + wire \u6/rmw_r ; + wire \u6/rmw_r0 ; + wire \u6/wb_err0 ; + wire \u6/wb_first_r ; + wire \u6/wb_first_set ; + wire \u6/wr_hold0 ; + wire \u6/write_go_r ; + wire \u6/write_go_r0 ; + wire \u6/write_go_r1 ; + wire \u6/write_go_r10 ; + wire \u7/mc_data_oe0 ; + wire \u7/mc_oe_0 ; + wire \u7/mc_rp0 ; + wire wb_ack_o; + wire wb_ack_o_i_10_n_0; + wire wb_ack_o_i_11_n_0; + wire wb_ack_o_i_12_n_0; + wire wb_ack_o_i_13_n_0; + wire wb_ack_o_i_14_n_0; + wire wb_ack_o_i_15_n_0; + wire wb_ack_o_i_16_n_0; + wire wb_ack_o_i_17_n_0; + wire wb_ack_o_i_18_n_0; + wire wb_ack_o_i_19_n_0; + wire wb_ack_o_i_1_n_0; + wire wb_ack_o_i_20_n_0; + wire wb_ack_o_i_21_n_0; + wire wb_ack_o_i_22_n_0; + wire wb_ack_o_i_23_n_0; + wire wb_ack_o_i_2_n_0; + wire wb_ack_o_i_3_n_0; + wire wb_ack_o_i_4_n_0; + wire wb_ack_o_i_5_n_0; + wire wb_ack_o_i_6_n_0; + wire wb_ack_o_i_7_n_0; + wire wb_ack_o_i_8_n_0; + wire wb_ack_o_i_9_n_0; + wire [31:0]wb_addr_i; + wire wb_cyc_i; + wire wb_cycle; + wire wb_cycle_i_1_n_0; + wire [31:0]wb_data_i; + wire [31:0]wb_data_o; + wire \wb_data_o[0]_i_1_n_0 ; + wire \wb_data_o[0]_i_2_n_0 ; + wire \wb_data_o[0]_i_3_n_0 ; + wire \wb_data_o[0]_i_4_n_0 ; + wire \wb_data_o[0]_i_5_n_0 ; + wire \wb_data_o[0]_i_6_n_0 ; + wire \wb_data_o[10]_i_1_n_0 ; + wire \wb_data_o[10]_i_2_n_0 ; + wire \wb_data_o[10]_i_3_n_0 ; + wire \wb_data_o[10]_i_4_n_0 ; + wire \wb_data_o[10]_i_5_n_0 ; + wire \wb_data_o[10]_i_6_n_0 ; + wire \wb_data_o[10]_i_7_n_0 ; + wire \wb_data_o[10]_i_8_n_0 ; + wire \wb_data_o[11]_i_1_n_0 ; + wire \wb_data_o[11]_i_2_n_0 ; + wire \wb_data_o[11]_i_3_n_0 ; + wire \wb_data_o[11]_i_4_n_0 ; + wire \wb_data_o[11]_i_5_n_0 ; + wire \wb_data_o[12]_i_1_n_0 ; + wire \wb_data_o[12]_i_2_n_0 ; + wire \wb_data_o[12]_i_3_n_0 ; + wire \wb_data_o[12]_i_4_n_0 ; + wire \wb_data_o[12]_i_5_n_0 ; + wire \wb_data_o[13]_i_1_n_0 ; + wire \wb_data_o[13]_i_2_n_0 ; + wire \wb_data_o[13]_i_3_n_0 ; + wire \wb_data_o[13]_i_4_n_0 ; + wire \wb_data_o[13]_i_5_n_0 ; + wire \wb_data_o[14]_i_1_n_0 ; + wire \wb_data_o[14]_i_2_n_0 ; + wire \wb_data_o[14]_i_3_n_0 ; + wire \wb_data_o[14]_i_4_n_0 ; + wire \wb_data_o[14]_i_5_n_0 ; + wire \wb_data_o[15]_i_1_n_0 ; + wire \wb_data_o[15]_i_2_n_0 ; + wire \wb_data_o[15]_i_3_n_0 ; + wire \wb_data_o[15]_i_4_n_0 ; + wire \wb_data_o[15]_i_5_n_0 ; + wire \wb_data_o[15]_i_6_n_0 ; + wire \wb_data_o[16]_i_1_n_0 ; + wire \wb_data_o[16]_i_2_n_0 ; + wire \wb_data_o[16]_i_3_n_0 ; + wire \wb_data_o[16]_i_4_n_0 ; + wire \wb_data_o[16]_i_5_n_0 ; + wire \wb_data_o[16]_i_6_n_0 ; + wire \wb_data_o[17]_i_1_n_0 ; + wire \wb_data_o[17]_i_2_n_0 ; + wire \wb_data_o[17]_i_3_n_0 ; + wire \wb_data_o[17]_i_4_n_0 ; + wire \wb_data_o[17]_i_5_n_0 ; + wire \wb_data_o[17]_i_6_n_0 ; + wire \wb_data_o[18]_i_1_n_0 ; + wire \wb_data_o[18]_i_2_n_0 ; + wire \wb_data_o[18]_i_3_n_0 ; + wire \wb_data_o[18]_i_4_n_0 ; + wire \wb_data_o[18]_i_5_n_0 ; + wire \wb_data_o[18]_i_6_n_0 ; + wire \wb_data_o[19]_i_1_n_0 ; + wire \wb_data_o[19]_i_2_n_0 ; + wire \wb_data_o[19]_i_3_n_0 ; + wire \wb_data_o[19]_i_4_n_0 ; + wire \wb_data_o[19]_i_5_n_0 ; + wire \wb_data_o[19]_i_6_n_0 ; + wire \wb_data_o[1]_i_1_n_0 ; + wire \wb_data_o[1]_i_2_n_0 ; + wire \wb_data_o[1]_i_3_n_0 ; + wire \wb_data_o[1]_i_4_n_0 ; + wire \wb_data_o[1]_i_5_n_0 ; + wire \wb_data_o[1]_i_6_n_0 ; + wire \wb_data_o[20]_i_1_n_0 ; + wire \wb_data_o[20]_i_2_n_0 ; + wire \wb_data_o[20]_i_3_n_0 ; + wire \wb_data_o[20]_i_4_n_0 ; + wire \wb_data_o[20]_i_5_n_0 ; + wire \wb_data_o[20]_i_6_n_0 ; + wire \wb_data_o[21]_i_1_n_0 ; + wire \wb_data_o[21]_i_2_n_0 ; + wire \wb_data_o[21]_i_3_n_0 ; + wire \wb_data_o[21]_i_4_n_0 ; + wire \wb_data_o[21]_i_5_n_0 ; + wire \wb_data_o[21]_i_6_n_0 ; + wire \wb_data_o[22]_i_1_n_0 ; + wire \wb_data_o[22]_i_2_n_0 ; + wire \wb_data_o[22]_i_3_n_0 ; + wire \wb_data_o[22]_i_4_n_0 ; + wire \wb_data_o[22]_i_5_n_0 ; + wire \wb_data_o[22]_i_6_n_0 ; + wire \wb_data_o[23]_i_1_n_0 ; + wire \wb_data_o[23]_i_2_n_0 ; + wire \wb_data_o[23]_i_3_n_0 ; + wire \wb_data_o[23]_i_4_n_0 ; + wire \wb_data_o[23]_i_5_n_0 ; + wire \wb_data_o[23]_i_6_n_0 ; + wire \wb_data_o[24]_i_1_n_0 ; + wire \wb_data_o[24]_i_2_n_0 ; + wire \wb_data_o[24]_i_3_n_0 ; + wire \wb_data_o[24]_i_4_n_0 ; + wire \wb_data_o[24]_i_5_n_0 ; + wire \wb_data_o[24]_i_6_n_0 ; + wire \wb_data_o[25]_i_1_n_0 ; + wire \wb_data_o[25]_i_2_n_0 ; + wire \wb_data_o[25]_i_3_n_0 ; + wire \wb_data_o[25]_i_4_n_0 ; + wire \wb_data_o[25]_i_5_n_0 ; + wire \wb_data_o[25]_i_6_n_0 ; + wire \wb_data_o[26]_i_1_n_0 ; + wire \wb_data_o[26]_i_2_n_0 ; + wire \wb_data_o[26]_i_3_n_0 ; + wire \wb_data_o[26]_i_4_n_0 ; + wire \wb_data_o[26]_i_5_n_0 ; + wire \wb_data_o[26]_i_6_n_0 ; + wire \wb_data_o[27]_i_1_n_0 ; + wire \wb_data_o[27]_i_2_n_0 ; + wire \wb_data_o[27]_i_3_n_0 ; + wire \wb_data_o[27]_i_4_n_0 ; + wire \wb_data_o[27]_i_5_n_0 ; + wire \wb_data_o[27]_i_6_n_0 ; + wire \wb_data_o[28]_i_1_n_0 ; + wire \wb_data_o[28]_i_2_n_0 ; + wire \wb_data_o[28]_i_3_n_0 ; + wire \wb_data_o[28]_i_4_n_0 ; + wire \wb_data_o[28]_i_5_n_0 ; + wire \wb_data_o[28]_i_6_n_0 ; + wire \wb_data_o[29]_i_1_n_0 ; + wire \wb_data_o[29]_i_2_n_0 ; + wire \wb_data_o[29]_i_3_n_0 ; + wire \wb_data_o[29]_i_4_n_0 ; + wire \wb_data_o[29]_i_5_n_0 ; + wire \wb_data_o[29]_i_6_n_0 ; + wire \wb_data_o[2]_i_1_n_0 ; + wire \wb_data_o[2]_i_2_n_0 ; + wire \wb_data_o[2]_i_3_n_0 ; + wire \wb_data_o[2]_i_4_n_0 ; + wire \wb_data_o[2]_i_5_n_0 ; + wire \wb_data_o[2]_i_6_n_0 ; + wire \wb_data_o[30]_i_1_n_0 ; + wire \wb_data_o[30]_i_2_n_0 ; + wire \wb_data_o[30]_i_3_n_0 ; + wire \wb_data_o[30]_i_4_n_0 ; + wire \wb_data_o[30]_i_5_n_0 ; + wire \wb_data_o[30]_i_6_n_0 ; + wire \wb_data_o[31]_i_1_n_0 ; + wire \wb_data_o[31]_i_2_n_0 ; + wire \wb_data_o[31]_i_3_n_0 ; + wire \wb_data_o[31]_i_4_n_0 ; + wire \wb_data_o[31]_i_5_n_0 ; + wire \wb_data_o[31]_i_6_n_0 ; + wire \wb_data_o[31]_i_7_n_0 ; + wire \wb_data_o[31]_i_8_n_0 ; + wire \wb_data_o[31]_i_9_n_0 ; + wire \wb_data_o[3]_i_1_n_0 ; + wire \wb_data_o[3]_i_2_n_0 ; + wire \wb_data_o[3]_i_3_n_0 ; + wire \wb_data_o[3]_i_4_n_0 ; + wire \wb_data_o[3]_i_5_n_0 ; + wire \wb_data_o[3]_i_6_n_0 ; + wire \wb_data_o[4]_i_1_n_0 ; + wire \wb_data_o[4]_i_2_n_0 ; + wire \wb_data_o[4]_i_3_n_0 ; + wire \wb_data_o[4]_i_4_n_0 ; + wire \wb_data_o[4]_i_5_n_0 ; + wire \wb_data_o[4]_i_6_n_0 ; + wire \wb_data_o[5]_i_1_n_0 ; + wire \wb_data_o[5]_i_2_n_0 ; + wire \wb_data_o[5]_i_3_n_0 ; + wire \wb_data_o[5]_i_4_n_0 ; + wire \wb_data_o[5]_i_5_n_0 ; + wire \wb_data_o[5]_i_6_n_0 ; + wire \wb_data_o[6]_i_1_n_0 ; + wire \wb_data_o[6]_i_2_n_0 ; + wire \wb_data_o[6]_i_3_n_0 ; + wire \wb_data_o[6]_i_4_n_0 ; + wire \wb_data_o[6]_i_5_n_0 ; + wire \wb_data_o[6]_i_6_n_0 ; + wire \wb_data_o[7]_i_1_n_0 ; + wire \wb_data_o[7]_i_2_n_0 ; + wire \wb_data_o[7]_i_3_n_0 ; + wire \wb_data_o[7]_i_4_n_0 ; + wire \wb_data_o[7]_i_5_n_0 ; + wire \wb_data_o[7]_i_6_n_0 ; + wire \wb_data_o[8]_i_1_n_0 ; + wire \wb_data_o[8]_i_2_n_0 ; + wire \wb_data_o[8]_i_3_n_0 ; + wire \wb_data_o[8]_i_4_n_0 ; + wire \wb_data_o[8]_i_5_n_0 ; + wire \wb_data_o[8]_i_6_n_0 ; + wire \wb_data_o[9]_i_1_n_0 ; + wire \wb_data_o[9]_i_2_n_0 ; + wire \wb_data_o[9]_i_3_n_0 ; + wire \wb_data_o[9]_i_4_n_0 ; + wire \wb_data_o[9]_i_5_n_0 ; + wire \wb_data_o[9]_i_6_n_0 ; + wire wb_err_o; + wire wb_first_r_i_1_n_0; + wire [3:0]wb_sel_i; + wire wb_stb_first_i_1_n_0; + wire wb_stb_first_i_2_n_0; + wire wb_stb_i; + wire wb_wait; + wire wb_we_i; + wire wb_write_go; + wire wb_write_go_r_i_2_n_0; + wire we_; + wire wp_err; + wire wp_err_i_1_n_0; + wire wp_err_i_2_n_0; + wire \wr_adr[0]_i_1_n_0 ; + wire \wr_adr[1]_i_1_n_0 ; + wire \wr_adr[2]_i_1_n_0 ; + wire \wr_adr[3]_i_1_n_0 ; + wire \wr_adr[3]_i_2_n_0 ; + wire wr_cycle; + wire wr_cycle_i_1_n_0; + wire wr_cycle_i_3_n_0; + wire wr_cycle_i_4_n_0; + wire wr_hold; + wire wr_hold_i_1_n_0; + wire [3:0]\NLW_u1/u0/out_r0_carry__1_CO_UNCONNECTED ; + + assign mc_cs_pad_o_[7] = \ ; + assign mc_cs_pad_o_[6] = \ ; + assign mc_cs_pad_o_[5] = \ ; + assign mc_cs_pad_o_[4] = \ ; + assign mc_cs_pad_o_[3] = \ ; + assign mc_cs_pad_o_[2] = \ ; + assign mc_cs_pad_o_[1:0] = \^mc_cs_pad_o_ [1:0]; + LUT6 #( + .INIT(64'h00000000FFFFFFF4)) + \FSM_sequential_state[0]_i_1 + (.I0(\FSM_sequential_state[0]_i_2_n_0 ), + .I1(\FSM_sequential_state[0]_i_3_n_0 ), + .I2(\FSM_sequential_state[0]_i_4_n_0 ), + .I3(\FSM_sequential_state[0]_i_5_n_0 ), + .I4(\FSM_sequential_state[0]_i_6_n_0 ), + .I5(\FSM_sequential_state[0]_i_7_n_0 ), + .O(\FSM_sequential_state[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000F000D000F)) + \FSM_sequential_state[0]_i_10 + (.I0(\FSM_sequential_state[0]_i_14_n_0 ), + .I1(\FSM_sequential_state[5]_i_9_n_0 ), + .I2(\u5/state [3]), + .I3(\u5/state [1]), + .I4(\FSM_sequential_state[0]_i_15_n_0 ), + .I5(\FSM_sequential_state[0]_i_16_n_0 ), + .O(\FSM_sequential_state[0]_i_10_n_0 )); + LUT6 #( + .INIT(64'h0000000000008088)) + \FSM_sequential_state[0]_i_11 + (.I0(ap_en_i_2_n_0), + .I1(bank_open), + .I2(wb_cycle), + .I3(\u5/susp_req_r ), + .I4(\FSM_sequential_state[0]_i_17_n_0 ), + .I5(\mc_addr[23]_i_3_n_0 ), + .O(\FSM_sequential_state[0]_i_11_n_0 )); + LUT6 #( + .INIT(64'h0FFFFFFF0FFDFFFF)) + \FSM_sequential_state[0]_i_12 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(\FSM_sequential_state[0]_i_16_n_0 ), + .I2(wb_write_go), + .I3(\u5/state [1]), + .I4(\FSM_sequential_state[0]_i_18_n_0 ), + .I5(\mc_addr[14]_i_4_n_0 ), + .O(\FSM_sequential_state[0]_i_12_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT4 #( + .INIT(16'h0C44)) + \FSM_sequential_state[0]_i_13 + (.I0(cke__i_5_n_0), + .I1(\u5/state [4]), + .I2(wb_write_go), + .I3(wb_cycle), + .O(\FSM_sequential_state[0]_i_13_n_0 )); + LUT5 #( + .INIT(32'hAAAABFFF)) + \FSM_sequential_state[0]_i_14 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(row_same), + .I2(ap_en_i_2_n_0), + .I3(bank_open), + .I4(\mc_addr[14]_i_4_n_0 ), + .O(\FSM_sequential_state[0]_i_14_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT4 #( + .INIT(16'h0007)) + \FSM_sequential_state[0]_i_15 + (.I0(lmr_req), + .I1(\u5/lookup_ready2 ), + .I2(init_req), + .I3(rfr_req), + .O(\FSM_sequential_state[0]_i_15_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_state[0]_i_16 + (.I0(\u5/susp_req_r ), + .I1(wb_cycle), + .O(\FSM_sequential_state[0]_i_16_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT5 #( + .INIT(32'hFFFFFFFD)) + \FSM_sequential_state[0]_i_17 + (.I0(\u5/state [0]), + .I1(\u5/state [1]), + .I2(\u5/state [3]), + .I3(\u5/state [2]), + .I4(\u5/state [6]), + .O(\FSM_sequential_state[0]_i_17_n_0 )); + LUT6 #( + .INIT(64'h0404000400000004)) + \FSM_sequential_state[0]_i_18 + (.I0(\u5/state [6]), + .I1(\u5/state [0]), + .I2(\u5/state [3]), + .I3(\u5/state [5]), + .I4(\u5/state [1]), + .I5(\u5/state [2]), + .O(\FSM_sequential_state[0]_i_18_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_state[0]_i_2 + (.I0(\FSM_sequential_state[6]_i_22_n_0 ), + .I1(\u5/state [5]), + .O(\FSM_sequential_state[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT2 #( + .INIT(4'h1)) + \FSM_sequential_state[0]_i_3 + (.I0(\u5/state [2]), + .I1(\u5/state [0]), + .O(\FSM_sequential_state[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF00800000)) + \FSM_sequential_state[0]_i_4 + (.I0(\u5/state [4]), + .I1(\u5/state [2]), + .I2(\u5/state [0]), + .I3(\u5/state [1]), + .I4(\FSM_sequential_state[2]_i_11_n_0 ), + .I5(\FSM_sequential_state[0]_i_8_n_0 ), + .O(\FSM_sequential_state[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0000FF00D000FF00)) + \FSM_sequential_state[0]_i_5 + (.I0(\FSM_sequential_state[2]_i_13_n_0 ), + .I1(\u5/state [5]), + .I2(\u5/state [4]), + .I3(\u5/state [1]), + .I4(\u5/state [0]), + .I5(\u5/state [3]), + .O(\FSM_sequential_state[0]_i_5_n_0 )); + LUT6 #( + .INIT(64'h0000000000A000A2)) + \FSM_sequential_state[0]_i_6 + (.I0(\FSM_sequential_state[0]_i_9_n_0 ), + .I1(\u5/state [5]), + .I2(\u5/state [1]), + .I3(\u5/state [2]), + .I4(\u5/state [4]), + .I5(\FSM_sequential_state[0]_i_10_n_0 ), + .O(\FSM_sequential_state[0]_i_6_n_0 )); + LUT6 #( + .INIT(64'hBBBAAABABBBBBBBB)) + \FSM_sequential_state[0]_i_7 + (.I0(\FSM_sequential_state[0]_i_11_n_0 ), + .I1(\FSM_sequential_state[0]_i_12_n_0 ), + .I2(\FSM_sequential_state[1]_i_9_n_0 ), + .I3(\u5/state [5]), + .I4(mc_adv__i_3_n_0), + .I5(\u5/state [1]), + .O(\FSM_sequential_state[0]_i_7_n_0 )); + LUT6 #( + .INIT(64'hCCCCFFDFCCCCDFDF)) + \FSM_sequential_state[0]_i_8 + (.I0(\u5/state [4]), + .I1(\u5/state [6]), + .I2(\u5/state [3]), + .I3(no_wb_cycle_i_2_n_0), + .I4(\u5/state [0]), + .I5(\u5/state [5]), + .O(\FSM_sequential_state[0]_i_8_n_0 )); + LUT6 #( + .INIT(64'hEE2EEEEEFFFFFFFF)) + \FSM_sequential_state[0]_i_9 + (.I0(\FSM_sequential_state[0]_i_13_n_0 ), + .I1(\u5/state [5]), + .I2(\u5/state [4]), + .I3(no_wb_cycle_i_2_n_0), + .I4(mem_ack_r_i_7_n_0), + .I5(rfr_ack_r_i_2_n_0), + .O(\FSM_sequential_state[0]_i_9_n_0 )); + LUT6 #( + .INIT(64'h8AAA8A00AAAAAAAA)) + \FSM_sequential_state[1]_i_1 + (.I0(\FSM_sequential_state[1]_i_2_n_0 ), + .I1(\FSM_sequential_state[1]_i_3_n_0 ), + .I2(\FSM_sequential_state[1]_i_4_n_0 ), + .I3(\u5/state [0]), + .I4(\FSM_sequential_state[1]_i_5_n_0 ), + .I5(\FSM_sequential_state[1]_i_6_n_0 ), + .O(\FSM_sequential_state[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h1010101010001010)) + \FSM_sequential_state[1]_i_10 + (.I0(\u5/state [2]), + .I1(\u5/state [1]), + .I2(\u5/state [5]), + .I3(mc_ack_r), + .I4(\u5/state [4]), + .I5(\u5/state [3]), + .O(\FSM_sequential_state[1]_i_10_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBB0BBB0BBB0)) + \FSM_sequential_state[1]_i_11 + (.I0(wb_cycle), + .I1(\u5/susp_req_r ), + .I2(\FSM_sequential_state[5]_i_9_n_0 ), + .I3(\FSM_sequential_state[2]_i_18_n_0 ), + .I4(cs_le_i_7_n_0), + .I5(wb_write_go), + .O(\FSM_sequential_state[1]_i_11_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT3 #( + .INIT(8'hEA)) + \FSM_sequential_state[1]_i_12 + (.I0(rfr_req), + .I1(lmr_req), + .I2(\u5/lookup_ready2 ), + .O(\FSM_sequential_state[1]_i_12_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h1)) + \FSM_sequential_state[1]_i_13 + (.I0(\u5/state [2]), + .I1(\u5/state [4]), + .O(\FSM_sequential_state[1]_i_13_n_0 )); + LUT6 #( + .INIT(64'h4F4FCFCF4F4FFFCF)) + \FSM_sequential_state[1]_i_14 + (.I0(\FSM_sequential_state[6]_i_25_n_0 ), + .I1(\u5/state [3]), + .I2(rfr_ack_r_i_7_n_0), + .I3(\FSM_sequential_state[1]_i_19_n_0 ), + .I4(\u5/state [4]), + .I5(\u5/state [2]), + .O(\FSM_sequential_state[1]_i_14_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT4 #( + .INIT(16'hC3FB)) + \FSM_sequential_state[1]_i_15 + (.I0(pack_le0_i_3_n_0), + .I1(\u5/state [2]), + .I2(\u5/state [4]), + .I3(\u5/state [3]), + .O(\FSM_sequential_state[1]_i_15_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF01000000)) + \FSM_sequential_state[1]_i_16 + (.I0(data_oe_r_i_7_n_0), + .I1(\u5/state [1]), + .I2(\u5/state [5]), + .I3(\u5/state [4]), + .I4(\u5/state [2]), + .I5(\FSM_sequential_state[1]_i_20_n_0 ), + .O(\FSM_sequential_state[1]_i_16_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT5 #( + .INIT(32'h5A5A5A58)) + \FSM_sequential_state[1]_i_17 + (.I0(\u5/state [4]), + .I1(\FSM_sequential_state[1]_i_21_n_0 ), + .I2(\u5/state [2]), + .I3(cke__i_5_n_0), + .I4(\u5/ap_en ), + .O(\FSM_sequential_state[1]_i_17_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_state[1]_i_18 + (.I0(\u5/state [1]), + .I1(\u5/state [3]), + .O(\FSM_sequential_state[1]_i_18_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_state[1]_i_19 + (.I0(init_req), + .I1(rfr_req), + .O(\FSM_sequential_state[1]_i_19_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT5 #( + .INIT(32'hFFFFFFFB)) + \FSM_sequential_state[1]_i_2 + (.I0(\u5/state [1]), + .I1(\u5/ir_cnt_done ), + .I2(\u5/state [4]), + .I3(\u5/state [2]), + .I4(\u5/state [0]), + .O(\FSM_sequential_state[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h054FFFFF00000000)) + \FSM_sequential_state[1]_i_20 + (.I0(\u5/state [3]), + .I1(wb_write_go), + .I2(\u5/state [4]), + .I3(\u5/state [5]), + .I4(\u5/state [2]), + .I5(\u5/state [1]), + .O(\FSM_sequential_state[1]_i_20_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT4 #( + .INIT(16'h0535)) + \FSM_sequential_state[1]_i_21 + (.I0(wb_cycle), + .I1(\u5/wb_write_go_r ), + .I2(\cmd_r[0]_i_5_n_0 ), + .I3(burst_act_rd_i_2_n_0), + .O(\FSM_sequential_state[1]_i_21_n_0 )); + LUT6 #( + .INIT(64'hFFFFFF10FF10FF10)) + \FSM_sequential_state[1]_i_3 + (.I0(\FSM_sequential_state[1]_i_7_n_0 ), + .I1(\FSM_sequential_state[1]_i_8_n_0 ), + .I2(\FSM_sequential_state[1]_i_9_n_0 ), + .I3(\FSM_sequential_state[1]_i_10_n_0 ), + .I4(wb_write_go), + .I5(\FSM_sequential_state[2]_i_9_n_0 ), + .O(\FSM_sequential_state[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFABAAAAAAAAAA)) + \FSM_sequential_state[1]_i_4 + (.I0(\u5/state [1]), + .I1(\FSM_sequential_state[1]_i_11_n_0 ), + .I2(\FSM_sequential_state[1]_i_12_n_0 ), + .I3(\FSM_sequential_state[1]_i_13_n_0 ), + .I4(\FSM_sequential_state[1]_i_14_n_0 ), + .I5(\FSM_sequential_state[1]_i_15_n_0 ), + .O(\FSM_sequential_state[1]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'hAAAAEAAE)) + \FSM_sequential_state[1]_i_5 + (.I0(\FSM_sequential_state[1]_i_16_n_0 ), + .I1(\u5/state [3]), + .I2(\u5/state [1]), + .I3(\u5/state [5]), + .I4(\FSM_sequential_state[1]_i_17_n_0 ), + .O(\FSM_sequential_state[1]_i_5_n_0 )); + LUT6 #( + .INIT(64'hBBFFFFFFFFFFFF3F)) + \FSM_sequential_state[1]_i_6 + (.I0(mc_adv__i_3_n_0), + .I1(\FSM_sequential_state[1]_i_18_n_0 ), + .I2(rfr_ack), + .I3(\u5/state [2]), + .I4(\u5/state [4]), + .I5(\u5/state [5]), + .O(\FSM_sequential_state[1]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_state[1]_i_7 + (.I0(\cmd_r[0]_i_5_n_0 ), + .I1(burst_act_rd_i_2_n_0), + .O(\FSM_sequential_state[1]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFEFFFFF)) + \FSM_sequential_state[1]_i_8 + (.I0(wb_write_go), + .I1(\u5/state [5]), + .I2(\u5/state [2]), + .I3(\u5/state [3]), + .I4(\u5/state [4]), + .I5(\u5/ap_en ), + .O(\FSM_sequential_state[1]_i_8_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT2 #( + .INIT(4'hB)) + \FSM_sequential_state[1]_i_9 + (.I0(cke__i_5_n_0), + .I1(wb_cycle), + .O(\FSM_sequential_state[1]_i_9_n_0 )); + LUT6 #( + .INIT(64'h8A8A8A888A8A8A8A)) + \FSM_sequential_state[2]_i_1 + (.I0(\FSM_sequential_state[2]_i_2_n_0 ), + .I1(\FSM_sequential_state[2]_i_3_n_0 ), + .I2(\FSM_sequential_state[2]_i_4_n_0 ), + .I3(\FSM_sequential_state[2]_i_5_n_0 ), + .I4(\FSM_sequential_state[2]_i_6_n_0 ), + .I5(\FSM_sequential_state[2]_i_7_n_0 ), + .O(\FSM_sequential_state[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFEEEEAEEE)) + \FSM_sequential_state[2]_i_10 + (.I0(\FSM_sequential_state[2]_i_20_n_0 ), + .I1(\FSM_sequential_state[2]_i_21_n_0 ), + .I2(\u5/state [4]), + .I3(\u5/state [3]), + .I4(\u5/state [5]), + .I5(\u5/state [0]), + .O(\FSM_sequential_state[2]_i_10_n_0 )); + LUT6 #( + .INIT(64'hEEEEEEECECECEEEC)) + \FSM_sequential_state[2]_i_11 + (.I0(\u5/state [3]), + .I1(\u5/state [5]), + .I2(\u5/ap_en ), + .I3(sp_csc[10]), + .I4(\timer2[6]_i_4_n_0 ), + .I5(csc__0[10]), + .O(\FSM_sequential_state[2]_i_11_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT2 #( + .INIT(4'hB)) + \FSM_sequential_state[2]_i_12 + (.I0(\u5/state [5]), + .I1(rfr_ack), + .O(\FSM_sequential_state[2]_i_12_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT3 #( + .INIT(8'h8A)) + \FSM_sequential_state[2]_i_13 + (.I0(\FSM_sequential_state[1]_i_9_n_0 ), + .I1(\FSM_sequential_state[1]_i_7_n_0 ), + .I2(\u5/ap_en ), + .O(\FSM_sequential_state[2]_i_13_n_0 )); + LUT2 #( + .INIT(4'h9)) + \FSM_sequential_state[2]_i_14 + (.I0(\u5/state [2]), + .I1(\u5/state [1]), + .O(\FSM_sequential_state[2]_i_14_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT4 #( + .INIT(16'hF1FF)) + \FSM_sequential_state[2]_i_15 + (.I0(\u5/state [5]), + .I1(\u5/state [2]), + .I2(\u5/state [3]), + .I3(\u5/state [4]), + .O(\FSM_sequential_state[2]_i_15_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT3 #( + .INIT(8'hFE)) + \FSM_sequential_state[2]_i_16 + (.I0(\u5/state [1]), + .I1(\u5/state [4]), + .I2(\u5/state [5]), + .O(\FSM_sequential_state[2]_i_16_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT5 #( + .INIT(32'h04050505)) + \FSM_sequential_state[2]_i_17 + (.I0(\u5/state [3]), + .I1(init_req), + .I2(rfr_req), + .I3(lmr_req), + .I4(\u5/lookup_ready2 ), + .O(\FSM_sequential_state[2]_i_17_n_0 )); + LUT6 #( + .INIT(64'h000000000000B800)) + \FSM_sequential_state[2]_i_18 + (.I0(csc__0[10]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_csc[10]), + .I3(bank_open), + .I4(cs_le_i_7_n_0), + .I5(row_same), + .O(\FSM_sequential_state[2]_i_18_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT4 #( + .INIT(16'h000D)) + \FSM_sequential_state[2]_i_19 + (.I0(\u5/susp_req_r ), + .I1(wb_cycle), + .I2(init_req), + .I3(\FSM_sequential_state[5]_i_9_n_0 ), + .O(\FSM_sequential_state[2]_i_19_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT4 #( + .INIT(16'hFEFF)) + \FSM_sequential_state[2]_i_2 + (.I0(\u5/state [0]), + .I1(\u5/state [2]), + .I2(\u5/state [4]), + .I3(\u5/ir_cnt_done ), + .O(\FSM_sequential_state[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFBFF0000FAFFFAFF)) + \FSM_sequential_state[2]_i_20 + (.I0(\u5/state [1]), + .I1(\u5/state [4]), + .I2(\u5/state [5]), + .I3(\u5/state [3]), + .I4(\FSM_sequential_state[2]_i_22_n_0 ), + .I5(\u5/state [2]), + .O(\FSM_sequential_state[2]_i_20_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT4 #( + .INIT(16'h0400)) + \FSM_sequential_state[2]_i_21 + (.I0(\u5/state [1]), + .I1(\u5/state [2]), + .I2(no_wb_cycle_i_2_n_0), + .I3(\u5/state [3]), + .O(\FSM_sequential_state[2]_i_21_n_0 )); + LUT6 #( + .INIT(64'h4444555500445055)) + \FSM_sequential_state[2]_i_22 + (.I0(\u5/state [5]), + .I1(\u5/state [4]), + .I2(\FSM_sequential_state[6]_i_40_n_0 ), + .I3(wb_write_go), + .I4(\u5/state [1]), + .I5(\u5/state [3]), + .O(\FSM_sequential_state[2]_i_22_n_0 )); + LUT6 #( + .INIT(64'hCFCFCFCCEFEFCFCF)) + \FSM_sequential_state[2]_i_3 + (.I0(\FSM_sequential_state[2]_i_8_n_0 ), + .I1(\FSM_sequential_state[2]_i_9_n_0 ), + .I2(\FSM_sequential_state[2]_i_10_n_0 ), + .I3(\FSM_sequential_state[6]_i_22_n_0 ), + .I4(\u5/state [2]), + .I5(\u5/state [4]), + .O(\FSM_sequential_state[2]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT2 #( + .INIT(4'hB)) + \FSM_sequential_state[2]_i_4 + (.I0(\u5/state [6]), + .I1(\u5/state [0]), + .O(\FSM_sequential_state[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'h05F005F0050005C0)) + \FSM_sequential_state[2]_i_5 + (.I0(\FSM_sequential_state[2]_i_11_n_0 ), + .I1(\FSM_sequential_state[2]_i_12_n_0 ), + .I2(\u5/state [1]), + .I3(\u5/state [2]), + .I4(\u5/state [4]), + .I5(\u5/state [3]), + .O(\FSM_sequential_state[2]_i_5_n_0 )); + LUT6 #( + .INIT(64'h0000000022720000)) + \FSM_sequential_state[2]_i_6 + (.I0(\u5/state [5]), + .I1(mc_ack_r), + .I2(\FSM_sequential_state[2]_i_13_n_0 ), + .I3(wb_write_go), + .I4(\FSM_sequential_state[2]_i_14_n_0 ), + .I5(\FSM_sequential_state[2]_i_15_n_0 ), + .O(\FSM_sequential_state[2]_i_6_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAAFFFBBBBB)) + \FSM_sequential_state[2]_i_7 + (.I0(\FSM_sequential_state[2]_i_16_n_0 ), + .I1(\FSM_sequential_state[2]_i_17_n_0 ), + .I2(mc_adsc__i_5_n_0), + .I3(\FSM_sequential_state[2]_i_18_n_0 ), + .I4(\FSM_sequential_state[2]_i_19_n_0 ), + .I5(\u5/state [2]), + .O(\FSM_sequential_state[2]_i_7_n_0 )); + LUT6 #( + .INIT(64'h7033700370337033)) + \FSM_sequential_state[2]_i_8 + (.I0(mc_ack_r), + .I1(\u5/state [1]), + .I2(\u5/state [5]), + .I3(\u5/state [3]), + .I4(pack_le0_i_3_n_0), + .I5(pack_le0_i_2_n_0), + .O(\FSM_sequential_state[2]_i_8_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT5 #( + .INIT(32'h00800000)) + \FSM_sequential_state[2]_i_9 + (.I0(\u5/state [2]), + .I1(\u5/state [4]), + .I2(\u5/state [5]), + .I3(\u5/state [3]), + .I4(\u5/state [1]), + .O(\FSM_sequential_state[2]_i_9_n_0 )); + LUT6 #( + .INIT(64'h00000000F4F4F4F7)) + \FSM_sequential_state[3]_i_1 + (.I0(\FSM_sequential_state[3]_i_2_n_0 ), + .I1(\u5/state [2]), + .I2(\FSM_sequential_state[3]_i_3_n_0 ), + .I3(\u5/state [6]), + .I4(\FSM_sequential_state[3]_i_4_n_0 ), + .I5(\FSM_sequential_state[3]_i_5_n_0 ), + .O(\FSM_sequential_state[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFF4F)) + \FSM_sequential_state[3]_i_10 + (.I0(\FSM_sequential_state[5]_i_9_n_0 ), + .I1(\FSM_sequential_state[3]_i_12_n_0 ), + .I2(\u5/state [0]), + .I3(\u5/state [3]), + .I4(rfr_req), + .I5(init_req), + .O(\FSM_sequential_state[3]_i_10_n_0 )); + LUT6 #( + .INIT(64'h11F111F111F11111)) + \FSM_sequential_state[3]_i_11 + (.I0(\burst_cnt[8]_i_3_n_0 ), + .I1(\u5/state [4]), + .I2(\u5/state [1]), + .I3(wb_write_go), + .I4(no_wb_cycle_i_2_n_0), + .I5(wb_stb_i), + .O(\FSM_sequential_state[3]_i_11_n_0 )); + LUT6 #( + .INIT(64'h0000303330331011)) + \FSM_sequential_state[3]_i_12 + (.I0(\mc_addr[14]_i_4_n_0 ), + .I1(lmr_req), + .I2(wb_cycle), + .I3(\u5/susp_req_r ), + .I4(wb_write_go), + .I5(\mc_addr[23]_i_3_n_0 ), + .O(\FSM_sequential_state[3]_i_12_n_0 )); + LUT6 #( + .INIT(64'h0000707777777077)) + \FSM_sequential_state[3]_i_2 + (.I0(\FSM_sequential_state[3]_i_6_n_0 ), + .I1(\FSM_sequential_state[6]_i_24_n_0 ), + .I2(\FSM_sequential_state[3]_i_7_n_0 ), + .I3(\u5/state [4]), + .I4(\u5/state [0]), + .I5(\FSM_sequential_state[3]_i_8_n_0 ), + .O(\FSM_sequential_state[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT5 #( + .INIT(32'h40400440)) + \FSM_sequential_state[3]_i_3 + (.I0(\u5/state [0]), + .I1(\u5/state [3]), + .I2(\u5/state [5]), + .I3(\u5/state [1]), + .I4(\u5/state [4]), + .O(\FSM_sequential_state[3]_i_3_n_0 )); + LUT6 #( + .INIT(64'h5D7D555551415555)) + \FSM_sequential_state[3]_i_4 + (.I0(\u5/state [3]), + .I1(\u5/state [0]), + .I2(\u5/state [4]), + .I3(\FSM_sequential_state[6]_i_22_n_0 ), + .I4(\FSM_sequential_state[3]_i_9_n_0 ), + .I5(\FSM_sequential_state[3]_i_10_n_0 ), + .O(\FSM_sequential_state[3]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \FSM_sequential_state[3]_i_5 + (.I0(\u5/state [2]), + .I1(\u5/state [4]), + .I2(\u5/state [5]), + .I3(\u5/state [1]), + .I4(\u5/ir_cnt_done ), + .I5(\u5/state [0]), + .O(\FSM_sequential_state[3]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h0400)) + \FSM_sequential_state[3]_i_6 + (.I0(\u5/state [3]), + .I1(\u5/state [0]), + .I2(\u5/state [5]), + .I3(\u5/state [1]), + .O(\FSM_sequential_state[3]_i_6_n_0 )); + LUT6 #( + .INIT(64'hFF30CCDDFFFCCCDD)) + \FSM_sequential_state[3]_i_7 + (.I0(data_oe_r_i_7_n_0), + .I1(\u5/state [5]), + .I2(wb_write_go), + .I3(\u5/state [3]), + .I4(\u5/state [1]), + .I5(mc_adv__i_3_n_0), + .O(\FSM_sequential_state[3]_i_7_n_0 )); + LUT6 #( + .INIT(64'h03032323FF0C0C0C)) + \FSM_sequential_state[3]_i_8 + (.I0(\FSM_sequential_state[6]_i_25_n_0 ), + .I1(\u5/state [1]), + .I2(\u5/state [4]), + .I3(\FSM_sequential_state[3]_i_11_n_0 ), + .I4(\u5/state [5]), + .I5(\u5/state [3]), + .O(\FSM_sequential_state[3]_i_8_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT2 #( + .INIT(4'h1)) + \FSM_sequential_state[3]_i_9 + (.I0(\u5/state [5]), + .I1(\u5/state [1]), + .O(\FSM_sequential_state[3]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFAEAAAAAAAAAA)) + \FSM_sequential_state[4]_i_1 + (.I0(\FSM_sequential_state[4]_i_2_n_0 ), + .I1(suspended_i_2_n_0), + .I2(\FSM_sequential_state[4]_i_3_n_0 ), + .I3(\FSM_sequential_state[4]_i_4_n_0 ), + .I4(\FSM_sequential_state[4]_i_5_n_0 ), + .I5(\FSM_sequential_state[4]_i_6_n_0 ), + .O(\FSM_sequential_state[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h888A8A8A8A8A888A)) + \FSM_sequential_state[4]_i_10 + (.I0(\FSM_sequential_state[4]_i_11_n_0 ), + .I1(\FSM_sequential_state[5]_i_9_n_0 ), + .I2(\FSM_sequential_state[2]_i_18_n_0 ), + .I3(\mc_addr[23]_i_3_n_0 ), + .I4(wb_write_go), + .I5(\mc_addr[14]_i_4_n_0 ), + .O(\FSM_sequential_state[4]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT3 #( + .INIT(8'h02)) + \FSM_sequential_state[4]_i_11 + (.I0(\FSM_sequential_state[5]_i_8_n_0 ), + .I1(\u5/state [1]), + .I2(\u5/state [5]), + .O(\FSM_sequential_state[4]_i_11_n_0 )); + LUT6 #( + .INIT(64'h4040400055555555)) + \FSM_sequential_state[4]_i_2 + (.I0(\u5/state [6]), + .I1(\FSM_sequential_state[4]_i_7_n_0 ), + .I2(\u5/state [3]), + .I3(\u5/state [4]), + .I4(\FSM_sequential_state[4]_i_8_n_0 ), + .I5(\FSM_sequential_state[4]_i_9_n_0 ), + .O(\FSM_sequential_state[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT2 #( + .INIT(4'h7)) + \FSM_sequential_state[4]_i_3 + (.I0(\u5/state [2]), + .I1(\u5/state [4]), + .O(\FSM_sequential_state[4]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT2 #( + .INIT(4'hE)) + \FSM_sequential_state[4]_i_4 + (.I0(\u5/state [5]), + .I1(\FSM_sequential_state[6]_i_24_n_0 ), + .O(\FSM_sequential_state[4]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0404C4C4FF3CC4C4)) + \FSM_sequential_state[4]_i_5 + (.I0(\u5/state [5]), + .I1(\u5/state [4]), + .I2(\u5/state [1]), + .I3(\FSM_sequential_state[4]_i_10_n_0 ), + .I4(\u5/state [0]), + .I5(\u5/state [2]), + .O(\FSM_sequential_state[4]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT2 #( + .INIT(4'h1)) + \FSM_sequential_state[4]_i_6 + (.I0(\u5/state [3]), + .I1(\u5/state [6]), + .O(\FSM_sequential_state[4]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT5 #( + .INIT(32'h0CFCFEFE)) + \FSM_sequential_state[4]_i_7 + (.I0(\FSM_sequential_state[6]_i_22_n_0 ), + .I1(\u5/state [5]), + .I2(\u5/state [0]), + .I3(\u5/state [4]), + .I4(\u5/state [2]), + .O(\FSM_sequential_state[4]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT2 #( + .INIT(4'h8)) + \FSM_sequential_state[4]_i_8 + (.I0(\u5/state [2]), + .I1(\u5/state [1]), + .O(\FSM_sequential_state[4]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFDF0FFFFFF0FFFFF)) + \FSM_sequential_state[4]_i_9 + (.I0(\FSM_sequential_state[6]_i_25_n_0 ), + .I1(\u5/state [5]), + .I2(\u5/state [1]), + .I3(\u5/state [0]), + .I4(\u5/state [4]), + .I5(\u5/state [2]), + .O(\FSM_sequential_state[4]_i_9_n_0 )); + LUT6 #( + .INIT(64'h4544444445454545)) + \FSM_sequential_state[5]_i_1 + (.I0(\u5/state [6]), + .I1(\FSM_sequential_state[5]_i_2_n_0 ), + .I2(\FSM_sequential_state[5]_i_3_n_0 ), + .I3(\FSM_sequential_state[5]_i_4_n_0 ), + .I4(\FSM_sequential_state[5]_i_5_n_0 ), + .I5(\FSM_sequential_state[5]_i_6_n_0 ), + .O(\FSM_sequential_state[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h4AFE0000FFFF0000)) + \FSM_sequential_state[5]_i_2 + (.I0(\u5/state [3]), + .I1(\u5/state [1]), + .I2(\u5/state [2]), + .I3(\u5/state [0]), + .I4(\u5/state [5]), + .I5(\u5/state [4]), + .O(\FSM_sequential_state[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT4 #( + .INIT(16'h7EFF)) + \FSM_sequential_state[5]_i_3 + (.I0(\u5/state [2]), + .I1(\u5/state [3]), + .I2(\u5/state [1]), + .I3(\u5/state [0]), + .O(\FSM_sequential_state[5]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT2 #( + .INIT(4'hE)) + \FSM_sequential_state[5]_i_4 + (.I0(\u5/state [5]), + .I1(\u5/state [4]), + .O(\FSM_sequential_state[5]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT2 #( + .INIT(4'h6)) + \FSM_sequential_state[5]_i_5 + (.I0(\u5/state [5]), + .I1(\u5/state [3]), + .O(\FSM_sequential_state[5]_i_5_n_0 )); + LUT6 #( + .INIT(64'h777F7777777F777F)) + \FSM_sequential_state[5]_i_6 + (.I0(\FSM_sequential_state[5]_i_7_n_0 ), + .I1(\FSM_sequential_state[5]_i_8_n_0 ), + .I2(\FSM_sequential_state[5]_i_9_n_0 ), + .I3(\mc_addr[14]_i_4_n_0 ), + .I4(wb_write_go), + .I5(\mc_addr[23]_i_3_n_0 ), + .O(\FSM_sequential_state[5]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT2 #( + .INIT(4'h1)) + \FSM_sequential_state[5]_i_7 + (.I0(\u5/state [3]), + .I1(\u5/state [4]), + .O(\FSM_sequential_state[5]_i_7_n_0 )); + LUT6 #( + .INIT(64'h0111000001110111)) + \FSM_sequential_state[5]_i_8 + (.I0(rfr_req), + .I1(init_req), + .I2(\u5/lookup_ready2 ), + .I3(lmr_req), + .I4(wb_cycle), + .I5(\u5/susp_req_r ), + .O(\FSM_sequential_state[5]_i_8_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h4F4FFF4F)) + \FSM_sequential_state[5]_i_9 + (.I0(wb_write_go), + .I1(no_wb_cycle_i_2_n_0), + .I2(\u5/lookup_ready2 ), + .I3(\mc_cs_[1]_i_2_n_0 ), + .I4(\mc_cs_[0]_i_2_n_0 ), + .O(\FSM_sequential_state[5]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF1311)) + \FSM_sequential_state[6]_i_1 + (.I0(\FSM_sequential_state[6]_i_3_n_0 ), + .I1(\u5/state [6]), + .I2(\FSM_sequential_state[6]_i_4_n_0 ), + .I3(\FSM_sequential_state[6]_i_5_n_0 ), + .I4(\FSM_sequential_state[6]_i_6_n_0 ), + .I5(\FSM_sequential_state[6]_i_7_n_0 ), + .O(\FSM_sequential_state[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT4 #( + .INIT(16'hFFFD)) + \FSM_sequential_state[6]_i_10 + (.I0(\u5/state [3]), + .I1(\u5/state [1]), + .I2(\u5/state [5]), + .I3(\u5/state [2]), + .O(\FSM_sequential_state[6]_i_10_n_0 )); + LUT6 #( + .INIT(64'h3FCFFF8F3FCFF38F)) + \FSM_sequential_state[6]_i_11 + (.I0(\FSM_sequential_state[6]_i_24_n_0 ), + .I1(\u5/state [2]), + .I2(\u5/state [1]), + .I3(\u5/state [3]), + .I4(\u5/state [5]), + .I5(\FSM_sequential_state[6]_i_25_n_0 ), + .O(\FSM_sequential_state[6]_i_11_n_0 )); + LUT6 #( + .INIT(64'h0D0D0F0F0D0D0F00)) + \FSM_sequential_state[6]_i_12 + (.I0(\u5/tmr2_done ), + .I1(\u5/state [4]), + .I2(\FSM_sequential_state[6]_i_26_n_0 ), + .I3(\u5/state [1]), + .I4(\u5/state [0]), + .I5(\FSM_sequential_state[6]_i_27_n_0 ), + .O(\FSM_sequential_state[6]_i_12_n_0 )); + LUT6 #( + .INIT(64'h000000000000AA02)) + \FSM_sequential_state[6]_i_13 + (.I0(\FSM_sequential_state[6]_i_28_n_0 ), + .I1(wb_stb_i), + .I2(no_wb_cycle_i_2_n_0), + .I3(\FSM_sequential_state[6]_i_29_n_0 ), + .I4(\FSM_sequential_state[6]_i_30_n_0 ), + .I5(\FSM_sequential_state[6]_i_31_n_0 ), + .O(\FSM_sequential_state[6]_i_13_n_0 )); + LUT6 #( + .INIT(64'hFEFEFEFE0E0EFE0E)) + \FSM_sequential_state[6]_i_14 + (.I0(\FSM_sequential_state[6]_i_32_n_0 ), + .I1(\cmd_r[0]_i_2_n_0 ), + .I2(\u5/state [4]), + .I3(\b3_last_row[12]_i_3_n_0 ), + .I4(\FSM_sequential_state[6]_i_33_n_0 ), + .I5(\FSM_sequential_state[6]_i_34_n_0 ), + .O(\FSM_sequential_state[6]_i_14_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFF00FE)) + \FSM_sequential_state[6]_i_15 + (.I0(\cmd_r[0]_i_6_n_0 ), + .I1(\FSM_sequential_state[6]_i_35_n_0 ), + .I2(\FSM_sequential_state[6]_i_36_n_0 ), + .I3(\FSM_sequential_state[6]_i_37_n_0 ), + .I4(\u5/state [1]), + .I5(\FSM_sequential_state[6]_i_38_n_0 ), + .O(\FSM_sequential_state[6]_i_15_n_0 )); + LUT6 #( + .INIT(64'hE000000000000000)) + \FSM_sequential_state[6]_i_16 + (.I0(ap_en_i_2_n_0), + .I1(\u5/cmd_asserted ), + .I2(\u5/tmr_done ), + .I3(\u5/state [4]), + .I4(\u5/state [3]), + .I5(\u5/state [1]), + .O(\FSM_sequential_state[6]_i_16_n_0 )); + LUT6 #( + .INIT(64'h0002000233030003)) + \FSM_sequential_state[6]_i_17 + (.I0(\FSM_sequential_state[6]_i_39_n_0 ), + .I1(\u5/state [0]), + .I2(\u5/state [3]), + .I3(\u5/state [1]), + .I4(\u5/tmr_done ), + .I5(\u5/state [4]), + .O(\FSM_sequential_state[6]_i_17_n_0 )); + LUT6 #( + .INIT(64'hFEFEFEFEAAFEAAAA)) + \FSM_sequential_state[6]_i_18 + (.I0(\u5/state [1]), + .I1(mem_ack_r_i_7_n_0), + .I2(wb_write_go), + .I3(\u5/mem_ack_r ), + .I4(mc_adv__i_3_n_0), + .I5(\FSM_sequential_state[6]_i_25_n_0 ), + .O(\FSM_sequential_state[6]_i_18_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT2 #( + .INIT(4'h8)) + \FSM_sequential_state[6]_i_19 + (.I0(\u5/state [0]), + .I1(\u5/state [4]), + .O(\FSM_sequential_state[6]_i_19_n_0 )); + LUT6 #( + .INIT(64'h020202A2A2A202A2)) + \FSM_sequential_state[6]_i_2 + (.I0(\FSM_sequential_state[6]_i_8_n_0 ), + .I1(\FSM_sequential_state[6]_i_9_n_0 ), + .I2(\u5/state [0]), + .I3(\FSM_sequential_state[6]_i_10_n_0 ), + .I4(\u5/state [4]), + .I5(\FSM_sequential_state[6]_i_11_n_0 ), + .O(\FSM_sequential_state[6]_i_2_n_0 )); + LUT5 #( + .INIT(32'hA808A8A8)) + \FSM_sequential_state[6]_i_20 + (.I0(\FSM_sequential_state[5]_i_8_n_0 ), + .I1(\FSM_sequential_state[6]_i_40_n_0 ), + .I2(\FSM_sequential_state[5]_i_9_n_0 ), + .I3(\u5/cmd_asserted2 ), + .I4(mc_br_r), + .O(\FSM_sequential_state[6]_i_20_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT2 #( + .INIT(4'hB)) + \FSM_sequential_state[6]_i_21 + (.I0(\u5/state [4]), + .I1(\u5/state [0]), + .O(\FSM_sequential_state[6]_i_21_n_0 )); + LUT6 #( + .INIT(64'h003000300030FAFA)) + \FSM_sequential_state[6]_i_22 + (.I0(wb_cycle), + .I1(burst_act_rd_i_2_n_0), + .I2(\cmd_r[0]_i_5_n_0 ), + .I3(\u5/wb_write_go_r ), + .I4(\u5/ap_en ), + .I5(cke__i_5_n_0), + .O(\FSM_sequential_state[6]_i_22_n_0 )); + LUT6 #( + .INIT(64'hBAAAAAAAAAAABAAA)) + \FSM_sequential_state[6]_i_23 + (.I0(\u5/state [6]), + .I1(\u5/state [5]), + .I2(\u5/state [3]), + .I3(\u5/state [2]), + .I4(\u5/state [1]), + .I5(\u5/state [4]), + .O(\FSM_sequential_state[6]_i_23_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT4 #( + .INIT(16'hF0D0)) + \FSM_sequential_state[6]_i_24 + (.I0(\u5/ap_en ), + .I1(\FSM_sequential_state[1]_i_7_n_0 ), + .I2(\FSM_sequential_state[1]_i_9_n_0 ), + .I3(wb_write_go), + .O(\FSM_sequential_state[6]_i_24_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \FSM_sequential_state[6]_i_25 + (.I0(\u5/ap_en ), + .I1(sp_csc[10]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(csc__0[10]), + .O(\FSM_sequential_state[6]_i_25_n_0 )); + LUT6 #( + .INIT(64'h5454541450505010)) + \FSM_sequential_state[6]_i_26 + (.I0(\u5/state [3]), + .I1(\u5/state [4]), + .I2(\u5/state [0]), + .I3(mc_ack_r), + .I4(\u5/tmr2_done ), + .I5(\u5/tmr_done ), + .O(\FSM_sequential_state[6]_i_26_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT2 #( + .INIT(4'h7)) + \FSM_sequential_state[6]_i_27 + (.I0(\u5/cmd_asserted ), + .I1(\u5/state [3]), + .O(\FSM_sequential_state[6]_i_27_n_0 )); + LUT6 #( + .INIT(64'h7F33FFFFFFFFFFFF)) + \FSM_sequential_state[6]_i_28 + (.I0(mc_adv__i_3_n_0), + .I1(\u5/tmr2_done ), + .I2(\u5/cs_le_r ), + .I3(wb_cycle), + .I4(\u5/state [0]), + .I5(\u5/state [4]), + .O(\FSM_sequential_state[6]_i_28_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'hB)) + \FSM_sequential_state[6]_i_29 + (.I0(\u5/state [1]), + .I1(\u5/state [3]), + .O(\FSM_sequential_state[6]_i_29_n_0 )); + LUT6 #( + .INIT(64'h00E2FFFF00E20000)) + \FSM_sequential_state[6]_i_3 + (.I0(\FSM_sequential_state[6]_i_12_n_0 ), + .I1(\u5/state [2]), + .I2(\FSM_sequential_state[6]_i_13_n_0 ), + .I3(\FSM_sequential_state[6]_i_14_n_0 ), + .I4(\u5/state [5]), + .I5(\FSM_sequential_state[6]_i_15_n_0 ), + .O(\FSM_sequential_state[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hEE00F000EF0FFF0F)) + \FSM_sequential_state[6]_i_30 + (.I0(\u5/tmr2_done ), + .I1(mc_ack_r), + .I2(\u5/state [0]), + .I3(\u5/state [3]), + .I4(\u5/state [1]), + .I5(\u5/state [4]), + .O(\FSM_sequential_state[6]_i_30_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT5 #( + .INIT(32'h55400055)) + \FSM_sequential_state[6]_i_31 + (.I0(\u5/state [0]), + .I1(data_oe_r_i_7_n_0), + .I2(\u5/cmd_asserted ), + .I3(\u5/state [3]), + .I4(\u5/state [1]), + .O(\FSM_sequential_state[6]_i_31_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_state[6]_i_32 + (.I0(\u5/tmr2_done ), + .I1(\u5/state [3]), + .O(\FSM_sequential_state[6]_i_32_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT3 #( + .INIT(8'h4F)) + \FSM_sequential_state[6]_i_33 + (.I0(no_wb_cycle_i_2_n_0), + .I1(cke__i_5_n_0), + .I2(\u5/state [3]), + .O(\FSM_sequential_state[6]_i_33_n_0 )); + LUT6 #( + .INIT(64'hEE00FF00F0000000)) + \FSM_sequential_state[6]_i_34 + (.I0(no_wb_cycle_i_2_n_0), + .I1(mem_ack_r_i_7_n_0), + .I2(\u5/tmr2_done ), + .I3(\u5/state [0]), + .I4(\u5/state [3]), + .I5(\u5/state [1]), + .O(\FSM_sequential_state[6]_i_34_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT4 #( + .INIT(16'hFBFF)) + \FSM_sequential_state[6]_i_35 + (.I0(\u5/state [2]), + .I1(\u5/state [3]), + .I2(\u5/state [0]), + .I3(\u5/state [4]), + .O(\FSM_sequential_state[6]_i_35_n_0 )); + LUT6 #( + .INIT(64'hCCCC8088CC008000)) + \FSM_sequential_state[6]_i_36 + (.I0(no_wb_cycle_i_2_n_0), + .I1(cke__i_5_n_0), + .I2(burst_act_rd_i_2_n_0), + .I3(\cmd_r[0]_i_5_n_0 ), + .I4(\u5/wb_write_go_r ), + .I5(wb_cycle), + .O(\FSM_sequential_state[6]_i_36_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT5 #( + .INIT(32'hFFFF0880)) + \FSM_sequential_state[6]_i_37 + (.I0(\u5/cmd_asserted ), + .I1(\u5/state [3]), + .I2(\u5/state [2]), + .I3(\u5/state [0]), + .I4(\FSM_sequential_state[6]_i_41_n_0 ), + .O(\FSM_sequential_state[6]_i_37_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFA820A8A8)) + \FSM_sequential_state[6]_i_38 + (.I0(\FSM_sequential_state[6]_i_42_n_0 ), + .I1(\u5/state [4]), + .I2(\u5/tmr_done ), + .I3(wb_write_go), + .I4(\FSM_sequential_state[6]_i_43_n_0 ), + .I5(\FSM_sequential_state[6]_i_44_n_0 ), + .O(\FSM_sequential_state[6]_i_38_n_0 )); + LUT6 #( + .INIT(64'h8AAA8A8A8AAAAAAA)) + \FSM_sequential_state[6]_i_39 + (.I0(mc_adv__i_3_n_0), + .I1(wb_write_go), + .I2(\u5/wb_wait_r ), + .I3(csc__0[10]), + .I4(\timer2[6]_i_4_n_0 ), + .I5(sp_csc[10]), + .O(\FSM_sequential_state[6]_i_39_n_0 )); + LUT6 #( + .INIT(64'h0002020202020202)) + \FSM_sequential_state[6]_i_4 + (.I0(\u5/state [2]), + .I1(\FSM_sequential_state[6]_i_16_n_0 ), + .I2(\FSM_sequential_state[6]_i_17_n_0 ), + .I3(\FSM_sequential_state[6]_i_18_n_0 ), + .I4(\FSM_sequential_state[6]_i_19_n_0 ), + .I5(\u5/state [3]), + .O(\FSM_sequential_state[6]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_state[6]_i_40 + (.I0(wb_cyc_i), + .I1(wb_stb_i), + .O(\FSM_sequential_state[6]_i_40_n_0 )); + LUT6 #( + .INIT(64'h1010150510101000)) + \FSM_sequential_state[6]_i_41 + (.I0(\u5/state [2]), + .I1(\u5/state [3]), + .I2(\u5/state [4]), + .I3(\u5/resume_req_r ), + .I4(\u5/state [0]), + .I5(\u5/tmr_done ), + .O(\FSM_sequential_state[6]_i_41_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT4 #( + .INIT(16'h4000)) + \FSM_sequential_state[6]_i_42 + (.I0(\u5/state [2]), + .I1(\u5/state [0]), + .I2(\u5/state [1]), + .I3(\u5/state [3]), + .O(\FSM_sequential_state[6]_i_42_n_0 )); + LUT6 #( + .INIT(64'h0000FFFD00000000)) + \FSM_sequential_state[6]_i_43 + (.I0(\burst_cnt[3]_i_2_n_0 ), + .I1(\mc_addr[2]_i_4_n_0 ), + .I2(\timer2[6]_i_3_n_0 ), + .I3(\burst_cnt[3]_i_3_n_0 ), + .I4(burst_act_rd_i_2_n_0), + .I5(wb_cycle), + .O(\FSM_sequential_state[6]_i_43_n_0 )); + LUT6 #( + .INIT(64'hAEAAAAAAAEAAAEAA)) + \FSM_sequential_state[6]_i_44 + (.I0(\FSM_sequential_state[6]_i_45_n_0 ), + .I1(\FSM_sequential_state[6]_i_46_n_0 ), + .I2(\b3_last_row[12]_i_4_n_0 ), + .I3(\b3_last_row[12]_i_3_n_0 ), + .I4(wb_write_go), + .I5(\u5/wb_wait_r ), + .O(\FSM_sequential_state[6]_i_44_n_0 )); + LUT6 #( + .INIT(64'hFFF080F080808080)) + \FSM_sequential_state[6]_i_45 + (.I0(\u5/state [0]), + .I1(\FSM_sequential_state[6]_i_47_n_0 ), + .I2(\u5/cmd_asserted ), + .I3(\u5/state [4]), + .I4(\u5/tmr_done ), + .I5(\FSM_sequential_state[6]_i_48_n_0 ), + .O(\FSM_sequential_state[6]_i_45_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT2 #( + .INIT(4'h8)) + \FSM_sequential_state[6]_i_46 + (.I0(\u5/tmr_done ), + .I1(\u5/state [4]), + .O(\FSM_sequential_state[6]_i_46_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'h2A)) + \FSM_sequential_state[6]_i_47 + (.I0(\u5/state [2]), + .I1(\u5/state [4]), + .I2(\u5/state [3]), + .O(\FSM_sequential_state[6]_i_47_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'h04)) + \FSM_sequential_state[6]_i_48 + (.I0(\u5/state [0]), + .I1(\u5/state [1]), + .I2(\u5/state [2]), + .O(\FSM_sequential_state[6]_i_48_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAEAEF)) + \FSM_sequential_state[6]_i_5 + (.I0(\u5/state [2]), + .I1(\u5/tmr_done ), + .I2(\u5/state [1]), + .I3(\FSM_sequential_state[6]_i_20_n_0 ), + .I4(\u5/state [3]), + .I5(\FSM_sequential_state[6]_i_21_n_0 ), + .O(\FSM_sequential_state[6]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT5 #( + .INIT(32'h80008088)) + \FSM_sequential_state[6]_i_6 + (.I0(\u5/state [6]), + .I1(cke__i_2_n_0), + .I2(\u5/tmr_done ), + .I3(\u5/state [0]), + .I4(mc_br_r), + .O(\FSM_sequential_state[6]_i_6_n_0 )); + LUT6 #( + .INIT(64'h1000000000000000)) + \FSM_sequential_state[6]_i_7 + (.I0(\u5/state [6]), + .I1(\u5/state [3]), + .I2(\u5/state [1]), + .I3(\u5/state [4]), + .I4(\u5/cmd_asserted ), + .I5(\u5/state [0]), + .O(\FSM_sequential_state[6]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFF757FFFFFFFFF)) + \FSM_sequential_state[6]_i_8 + (.I0(\u5/tmr_done ), + .I1(csc__0[10]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[10]), + .I4(\u5/state [0]), + .I5(\u5/state [1]), + .O(\FSM_sequential_state[6]_i_8_n_0 )); + LUT6 #( + .INIT(64'h00000000FFE3FFFF)) + \FSM_sequential_state[6]_i_9 + (.I0(\FSM_sequential_state[6]_i_22_n_0 ), + .I1(\u5/state [5]), + .I2(\u5/state [3]), + .I3(\u5/state [1]), + .I4(\burst_cnt[10]_i_4_n_0 ), + .I5(\FSM_sequential_state[6]_i_23_n_0 ), + .O(\FSM_sequential_state[6]_i_9_n_0 )); + GND GND + (.G(\ )); + VCC VCC + (.P(\ )); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT2 #( + .INIT(4'h1)) + \ack_cnt[0]_i_1 + (.I0(\u5/ack_cnt_reg [0]), + .I1(\u5/no_wb_cycle ), + .O(p_0_in__0[0])); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT4 #( + .INIT(16'h1441)) + \ack_cnt[1]_i_1 + (.I0(\u5/no_wb_cycle ), + .I1(\u5/ack_cnt_reg [1]), + .I2(\ack_cnt[3]_i_3_n_0 ), + .I3(\u5/ack_cnt_reg [0]), + .O(\ack_cnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT5 #( + .INIT(32'h14505041)) + \ack_cnt[2]_i_1 + (.I0(\u5/no_wb_cycle ), + .I1(\u5/ack_cnt_reg [1]), + .I2(\u5/ack_cnt_reg [2]), + .I3(\ack_cnt[3]_i_3_n_0 ), + .I4(\u5/ack_cnt_reg [0]), + .O(\ack_cnt[2]_i_1_n_0 )); + LUT3 #( + .INIT(8'hBE)) + \ack_cnt[3]_i_1 + (.I0(\u5/no_wb_cycle ), + .I1(mem_ack_r_i_2_n_0), + .I2(dv), + .O(\ack_cnt[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'h000000007FFE8001)) + \ack_cnt[3]_i_2 + (.I0(\u5/ack_cnt_reg [2]), + .I1(\u5/ack_cnt_reg [1]), + .I2(\ack_cnt[3]_i_3_n_0 ), + .I3(\u5/ack_cnt_reg [0]), + .I4(\u5/ack_cnt_reg [3]), + .I5(\u5/no_wb_cycle ), + .O(p_0_in__0[3])); + LUT2 #( + .INIT(4'h2)) + \ack_cnt[3]_i_3 + (.I0(dv), + .I1(mem_ack_r_i_2_n_0), + .O(\ack_cnt[3]_i_3_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[0]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[0] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[0]_i_2_n_0 ), + .O(\acs_addr[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[0]_i_2 + (.I0(wb_addr_i[2]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[1]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[0]), + .O(\acs_addr[0]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[10]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[10] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[10]_i_2_n_0 ), + .O(\acs_addr[10]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[10]_i_2 + (.I0(wb_addr_i[12]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[11]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[10]), + .O(\acs_addr[10]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[11]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[11] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[11]_i_2_n_0 ), + .O(\acs_addr[11]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[11]_i_2 + (.I0(wb_addr_i[13]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[12]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[11]), + .O(\acs_addr[11]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[12]_i_1 + (.I0(inc_out0[0]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[12]_i_2_n_0 ), + .O(\acs_addr[12]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[12]_i_2 + (.I0(wb_addr_i[14]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[13]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[12]), + .O(\acs_addr[12]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[13]_i_1 + (.I0(inc_out0[1]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[13]_i_2_n_0 ), + .O(\acs_addr[13]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[13]_i_2 + (.I0(wb_addr_i[15]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[14]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[13]), + .O(\acs_addr[13]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[14]_i_1 + (.I0(inc_out0[2]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[14]_i_2_n_0 ), + .O(\acs_addr[14]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[14]_i_2 + (.I0(wb_addr_i[16]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[15]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[14]), + .O(\acs_addr[14]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[15]_i_1 + (.I0(inc_out0[3]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[15]_i_3_n_0 ), + .O(\acs_addr[15]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[15]_i_3 + (.I0(wb_addr_i[17]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[16]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[15]), + .O(\acs_addr[15]_i_3_n_0 )); + LUT2 #( + .INIT(4'h6)) + \acs_addr[15]_i_4 + (.I0(acs_addr[12]), + .I1(inc_next), + .O(\acs_addr[15]_i_4_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[16]_i_1 + (.I0(inc_out0[4]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[16]_i_2_n_0 ), + .O(\acs_addr[16]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[16]_i_2 + (.I0(wb_addr_i[18]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[17]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[16]), + .O(\acs_addr[16]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[17]_i_1 + (.I0(inc_out0[5]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[17]_i_2_n_0 ), + .O(\acs_addr[17]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[17]_i_2 + (.I0(wb_addr_i[19]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[18]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[17]), + .O(\acs_addr[17]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[18]_i_1 + (.I0(inc_out0[6]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[18]_i_2_n_0 ), + .O(\acs_addr[18]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[18]_i_2 + (.I0(wb_addr_i[20]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[19]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[18]), + .O(\acs_addr[18]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[19]_i_1 + (.I0(inc_out0[7]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[19]_i_3_n_0 ), + .O(\acs_addr[19]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[19]_i_3 + (.I0(wb_addr_i[21]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[20]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[19]), + .O(\acs_addr[19]_i_3_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[1]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[1] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[1]_i_2_n_0 ), + .O(\acs_addr[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[1]_i_2 + (.I0(wb_addr_i[3]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[2]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[1]), + .O(\acs_addr[1]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[20]_i_1 + (.I0(inc_out0[8]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[20]_i_2_n_0 ), + .O(\acs_addr[20]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[20]_i_2 + (.I0(wb_addr_i[22]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[21]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[20]), + .O(\acs_addr[20]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[21]_i_1 + (.I0(inc_out0[9]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[21]_i_2_n_0 ), + .O(\acs_addr[21]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[21]_i_2 + (.I0(wb_addr_i[23]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[22]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[21]), + .O(\acs_addr[21]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[22]_i_1 + (.I0(inc_out0[10]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[22]_i_2_n_0 ), + .O(\acs_addr[22]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[22]_i_2 + (.I0(wb_addr_i[24]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[23]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[22]), + .O(\acs_addr[22]_i_2_n_0 )); + LUT6 #( + .INIT(64'h555555D555555555)) + \acs_addr[23]_i_1 + (.I0(\acs_addr[23]_i_3_n_0 ), + .I1(\acs_addr[23]_i_4_n_0 ), + .I2(\u5/state [0]), + .I3(\u5/state [6]), + .I4(\u5/state [4]), + .I5(\u5/state [5]), + .O(\acs_addr[23]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[23]_i_2 + (.I0(inc_out0[11]), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[23]_i_6_n_0 ), + .O(\acs_addr[23]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT2 #( + .INIT(4'h1)) + \acs_addr[23]_i_3 + (.I0(cs_le), + .I1(wb_we_i), + .O(\acs_addr[23]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT5 #( + .INIT(32'h0D003000)) + \acs_addr[23]_i_4 + (.I0(pack_le0_i_3_n_0), + .I1(\u5/state [1]), + .I2(\u5/state [3]), + .I3(\u5/tmr2_done ), + .I4(\u5/state [2]), + .O(\acs_addr[23]_i_4_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[23]_i_6 + (.I0(wb_addr_i[25]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[24]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[23]), + .O(\acs_addr[23]_i_6_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[2]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[2] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[2]_i_2_n_0 ), + .O(\acs_addr[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[2]_i_2 + (.I0(wb_addr_i[4]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[3]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[2]), + .O(\acs_addr[2]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[3]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[3] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[3]_i_2_n_0 ), + .O(\acs_addr[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[3]_i_2 + (.I0(wb_addr_i[5]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[4]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[3]), + .O(\acs_addr[3]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[4]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[4] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[4]_i_2_n_0 ), + .O(\acs_addr[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[4]_i_2 + (.I0(wb_addr_i[6]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[5]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[4]), + .O(\acs_addr[4]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[5]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[5] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[5]_i_2_n_0 ), + .O(\acs_addr[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[5]_i_2 + (.I0(wb_addr_i[7]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[6]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[5]), + .O(\acs_addr[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[6]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[6] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[6]_i_2_n_0 ), + .O(\acs_addr[6]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[6]_i_2 + (.I0(wb_addr_i[8]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[7]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[6]), + .O(\acs_addr[6]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[7]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[7] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[7]_i_2_n_0 ), + .O(\acs_addr[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[7]_i_2 + (.I0(wb_addr_i[9]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[8]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[7]), + .O(\acs_addr[7]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[8]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[8] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[8]_i_2_n_0 ), + .O(\acs_addr[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[8]_i_2 + (.I0(wb_addr_i[10]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[9]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[8]), + .O(\acs_addr[8]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFE02)) + \acs_addr[9]_i_1 + (.I0(\u1/u0/out_r_reg_n_0_[9] ), + .I1(cs_le), + .I2(wb_we_i), + .I3(\acs_addr[9]_i_2_n_0 ), + .O(\acs_addr[9]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \acs_addr[9]_i_2 + (.I0(wb_addr_i[11]), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[10]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[9]), + .O(\acs_addr[9]_i_2_n_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \acs_addr_reg[15]_i_2 + (.CI(\ ), + .CO({\acs_addr_reg[15]_i_2_n_0 ,\acs_addr_reg[15]_i_2_n_1 ,\acs_addr_reg[15]_i_2_n_2 ,\acs_addr_reg[15]_i_2_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,acs_addr[12]}), + .O(inc_out0[3:0]), + .S({acs_addr[15:13],\acs_addr[15]_i_4_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \acs_addr_reg[19]_i_2 + (.CI(\acs_addr_reg[15]_i_2_n_0 ), + .CO({\acs_addr_reg[19]_i_2_n_0 ,\acs_addr_reg[19]_i_2_n_1 ,\acs_addr_reg[19]_i_2_n_2 ,\acs_addr_reg[19]_i_2_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(inc_out0[7:4]), + .S(acs_addr[19:16])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \acs_addr_reg[23]_i_5 + (.CI(\acs_addr_reg[19]_i_2_n_0 ), + .CO({\acs_addr_reg[23]_i_5_n_1 ,\acs_addr_reg[23]_i_5_n_2 ,\acs_addr_reg[23]_i_5_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(inc_out0[11:8]), + .S(acs_addr[23:20])); + LUT6 #( + .INIT(64'h0001FFFF00010000)) + ap_en_i_1 + (.I0(\timer[1]_i_2_n_0 ), + .I1(\timer[2]_i_2_n_0 ), + .I2(\timer[0]_i_3_n_0 ), + .I3(ap_en_i_2_n_0), + .I4(\u5/burst_cnt_ld ), + .I5(\u5/ap_en ), + .O(ap_en_i_1_n_0)); + LUT6 #( + .INIT(64'hEEEFEEEE22202222)) + ap_en_i_2 + (.I0(csc__0[10]), + .I1(lmr_ack), + .I2(\u5/state [6]), + .I3(\FSM_sequential_state[5]_i_4_n_0 ), + .I4(\burst_cnt[3]_i_4_n_0 ), + .I5(sp_csc[10]), + .O(ap_en_i_2_n_0)); + LUT3 #( + .INIT(8'h02)) + \b0_last_row[12]_i_1 + (.I0(\b3_last_row[12]_i_2_n_0 ), + .I1(bank_adr[1]), + .I2(bank_adr[0]), + .O(\b0_last_row[12]_i_1_n_0 )); + LUT3 #( + .INIT(8'h01)) + \b0_last_row[12]_i_1__0 + (.I0(bank_adr[1]), + .I1(bank_adr[0]), + .I2(\b3_last_row[12]_i_2__0_n_0 ), + .O(\u2/bank0_open0 )); + LUT3 #( + .INIT(8'h20)) + \b1_last_row[12]_i_1 + (.I0(\b3_last_row[12]_i_2_n_0 ), + .I1(bank_adr[1]), + .I2(bank_adr[0]), + .O(\b1_last_row[12]_i_1_n_0 )); + LUT3 #( + .INIT(8'h04)) + \b1_last_row[12]_i_1__0 + (.I0(bank_adr[1]), + .I1(bank_adr[0]), + .I2(\b3_last_row[12]_i_2__0_n_0 ), + .O(\u2/bank1_open0 )); + LUT3 #( + .INIT(8'h20)) + \b2_last_row[12]_i_1 + (.I0(\b3_last_row[12]_i_2_n_0 ), + .I1(bank_adr[0]), + .I2(bank_adr[1]), + .O(\b2_last_row[12]_i_1_n_0 )); + LUT3 #( + .INIT(8'h04)) + \b2_last_row[12]_i_1__0 + (.I0(bank_adr[0]), + .I1(bank_adr[1]), + .I2(\b3_last_row[12]_i_2__0_n_0 ), + .O(\u2/bank2_open0 )); + LUT3 #( + .INIT(8'h80)) + \b3_last_row[12]_i_1 + (.I0(\b3_last_row[12]_i_2_n_0 ), + .I1(bank_adr[1]), + .I2(bank_adr[0]), + .O(\b3_last_row[12]_i_1_n_0 )); + LUT3 #( + .INIT(8'h08)) + \b3_last_row[12]_i_1__0 + (.I0(bank_adr[1]), + .I1(bank_adr[0]), + .I2(\b3_last_row[12]_i_2__0_n_0 ), + .O(\u2/bank3_open0 )); + LUT6 #( + .INIT(64'h0040000000000000)) + \b3_last_row[12]_i_2 + (.I0(\mc_cs_[1]_i_2_n_0 ), + .I1(\b3_last_row[12]_i_3_n_0 ), + .I2(rfr_ack_r_i_7_n_0), + .I3(\b3_last_row[12]_i_4_n_0 ), + .I4(\u5/state [4]), + .I5(ap_en_i_2_n_0), + .O(\b3_last_row[12]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF7FFFFFFFFFFFFFF)) + \b3_last_row[12]_i_2__0 + (.I0(\b3_last_row[12]_i_3_n_0 ), + .I1(rfr_ack_r_i_7_n_0), + .I2(\b3_last_row[12]_i_4_n_0 ), + .I3(\u5/state [4]), + .I4(ap_en_i_2_n_0), + .I5(\mc_cs_[0]_i_2_n_0 ), + .O(\b3_last_row[12]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT2 #( + .INIT(4'h2)) + \b3_last_row[12]_i_3 + (.I0(\u5/state [1]), + .I1(\u5/state [0]), + .O(\b3_last_row[12]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT2 #( + .INIT(4'hB)) + \b3_last_row[12]_i_4 + (.I0(\u5/state [3]), + .I1(\u5/state [2]), + .O(\b3_last_row[12]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0202FFFE02020202)) + bank0_open_i_1 + (.I0(\b3_last_row[12]_i_2_n_0 ), + .I1(bank_adr[1]), + .I2(bank_adr[0]), + .I3(bank3_open_i_2__0_n_0), + .I4(bank3_open_i_3__0_n_0), + .I5(\u2/u1/bank0_open_reg_n_0 ), + .O(bank0_open_i_1_n_0)); + LUT6 #( + .INIT(64'h0101FFEF01010101)) + bank0_open_i_1__0 + (.I0(bank_adr[1]), + .I1(bank_adr[0]), + .I2(\b3_last_row[12]_i_2__0_n_0 ), + .I3(bank3_open_i_2_n_0), + .I4(bank3_open_i_3_n_0), + .I5(\u2/bank0_open ), + .O(bank0_open_i_1__0_n_0)); + LUT6 #( + .INIT(64'h2020FFEF20202020)) + bank1_open_i_1 + (.I0(\b3_last_row[12]_i_2_n_0 ), + .I1(bank_adr[1]), + .I2(bank_adr[0]), + .I3(bank3_open_i_2__0_n_0), + .I4(bank3_open_i_3__0_n_0), + .I5(\u2/u1/bank1_open_reg_n_0 ), + .O(bank1_open_i_1_n_0)); + LUT6 #( + .INIT(64'h0404FFBF04040404)) + bank1_open_i_1__0 + (.I0(bank_adr[1]), + .I1(bank_adr[0]), + .I2(\b3_last_row[12]_i_2__0_n_0 ), + .I3(bank3_open_i_2_n_0), + .I4(bank3_open_i_3_n_0), + .I5(\u2/bank1_open ), + .O(bank1_open_i_1__0_n_0)); + LUT6 #( + .INIT(64'h2020FFEF20202020)) + bank2_open_i_1 + (.I0(\b3_last_row[12]_i_2_n_0 ), + .I1(bank_adr[0]), + .I2(bank_adr[1]), + .I3(bank3_open_i_2__0_n_0), + .I4(bank3_open_i_3__0_n_0), + .I5(\u2/u1/bank2_open_reg_n_0 ), + .O(bank2_open_i_1_n_0)); + LUT6 #( + .INIT(64'h0404FFBF04040404)) + bank2_open_i_1__0 + (.I0(bank_adr[0]), + .I1(bank_adr[1]), + .I2(\b3_last_row[12]_i_2__0_n_0 ), + .I3(bank3_open_i_2_n_0), + .I4(bank3_open_i_3_n_0), + .I5(\u2/bank2_open ), + .O(bank2_open_i_1__0_n_0)); + LUT6 #( + .INIT(64'h8080FFBF80808080)) + bank3_open_i_1 + (.I0(\b3_last_row[12]_i_2_n_0 ), + .I1(bank_adr[1]), + .I2(bank_adr[0]), + .I3(bank3_open_i_2__0_n_0), + .I4(bank3_open_i_3__0_n_0), + .I5(\u2/u1/bank3_open_reg_n_0 ), + .O(bank3_open_i_1_n_0)); + LUT6 #( + .INIT(64'h0808FF7F08080808)) + bank3_open_i_1__0 + (.I0(bank_adr[1]), + .I1(bank_adr[0]), + .I2(\b3_last_row[12]_i_2__0_n_0 ), + .I3(bank3_open_i_2_n_0), + .I4(bank3_open_i_3_n_0), + .I5(\u2/bank3_open ), + .O(bank3_open_i_1__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT2 #( + .INIT(4'hB)) + bank3_open_i_2 + (.I0(bank3_open_i_4_n_0), + .I1(\mc_cs_[0]_i_2_n_0 ), + .O(bank3_open_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT2 #( + .INIT(4'hE)) + bank3_open_i_2__0 + (.I0(\mc_cs_[1]_i_2_n_0 ), + .I1(bank3_open_i_4_n_0), + .O(bank3_open_i_2__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'hBA)) + bank3_open_i_3 + (.I0(rfr_ack), + .I1(bank3_open_i_5_n_0), + .I2(\mc_cs_[0]_i_2_n_0 ), + .O(bank3_open_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'hAB)) + bank3_open_i_3__0 + (.I0(rfr_ack), + .I1(bank3_open_i_5_n_0), + .I2(\mc_cs_[1]_i_2_n_0 ), + .O(bank3_open_i_3__0_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFF2EFFFFFF)) + bank3_open_i_4 + (.I0(rfr_ack), + .I1(\u5/state [4]), + .I2(bank3_open_i_6_n_0), + .I3(cs_le_i_12_n_0), + .I4(bank3_open_i_7_n_0), + .I5(mc_bg_i_4_n_0), + .O(bank3_open_i_4_n_0)); + LUT6 #( + .INIT(64'hFEFEABBFFEFFABBF)) + bank3_open_i_5 + (.I0(lmr_ack_i_3_n_0), + .I1(\u5/state [0]), + .I2(\u5/state [2]), + .I3(\u5/state [3]), + .I4(\u5/state [1]), + .I5(rfr_ack), + .O(bank3_open_i_5_n_0)); + LUT6 #( + .INIT(64'h222200202222AA2A)) + bank3_open_i_6 + (.I0(\u5/tmr_done ), + .I1(sp_csc[10]), + .I2(\burst_cnt[3]_i_4_n_0 ), + .I3(lmr_ack_i_3_n_0), + .I4(lmr_ack), + .I5(csc__0[10]), + .O(bank3_open_i_6_n_0)); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT2 #( + .INIT(4'h2)) + bank3_open_i_7 + (.I0(\u5/state [1]), + .I1(\u5/state [5]), + .O(bank3_open_i_7_n_0)); + LUT5 #( + .INIT(32'hBABF8A80)) + \bank_adr[0]_i_1 + (.I0(\bank_adr[0]_i_2_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\bank_adr[0]_i_3_n_0 ), + .O(\bank_adr[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAACCAACCF000F0FF)) + \bank_adr[0]_i_2 + (.I0(wb_addr_i[22]), + .I1(wb_addr_i[21]), + .I2(wb_addr_i[23]), + .I3(\bank_adr[1]_i_5_n_0 ), + .I4(\bank_adr[0]_i_4_n_0 ), + .I5(\bank_adr[1]_i_4_n_0 ), + .O(\bank_adr[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFF03FE32FC00CE02)) + \bank_adr[0]_i_3 + (.I0(wb_addr_i[12]), + .I1(pack_le0_i_3_n_0), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[10]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[11]), + .O(\bank_adr[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'h01515404FD5D57F7)) + \bank_adr[0]_i_4 + (.I0(wb_addr_i[24]), + .I1(sp_csc[6]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(csc__0[6]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[25]), + .O(\bank_adr[0]_i_4_n_0 )); + LUT5 #( + .INIT(32'hBABF8A80)) + \bank_adr[1]_i_1 + (.I0(\bank_adr[1]_i_2_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\bank_adr[1]_i_3_n_0 ), + .O(\bank_adr[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \bank_adr[1]_i_2 + (.I0(wb_addr_i[23]), + .I1(wb_addr_i[22]), + .I2(\bank_adr[1]_i_4_n_0 ), + .I3(wb_addr_i[24]), + .I4(\bank_adr[1]_i_5_n_0 ), + .I5(\bank_adr[1]_i_6_n_0 ), + .O(\bank_adr[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFCFECE03003202)) + \bank_adr[1]_i_3 + (.I0(wb_addr_i[13]), + .I1(pack_le0_i_3_n_0), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[12]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[11]), + .O(\bank_adr[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h5555555500044404)) + \bank_adr[1]_i_4 + (.I0(\row_adr[12]_i_5_n_0 ), + .I1(pack_le0_i_2_n_0), + .I2(sp_csc[6]), + .I3(\timer2[6]_i_4_n_0 ), + .I4(csc__0[6]), + .I5(pack_le0_i_3_n_0), + .O(\bank_adr[1]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFF1DE20000FF1D)) + \bank_adr[1]_i_5 + (.I0(sp_csc[6]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(csc__0[6]), + .I3(pack_le0_i_2_n_0), + .I4(\row_adr[12]_i_5_n_0 ), + .I5(pack_le0_i_3_n_0), + .O(\bank_adr[1]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFEAEABFB02A2A808)) + \bank_adr[1]_i_6 + (.I0(wb_addr_i[25]), + .I1(sp_csc[6]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(csc__0[6]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[26]), + .O(\bank_adr[1]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT4 #( + .INIT(16'h4F44)) + bank_open_i_1 + (.I0(\mc_cs_[1]_i_2_n_0 ), + .I1(bank_open_i_2_n_0), + .I2(bank_open_i_3_n_0), + .I3(\mc_cs_[0]_i_2_n_0 ), + .O(\u2/bank_open0 )); + LUT6 #( + .INIT(64'hCCF0FFAACCF000AA)) + bank_open_i_2 + (.I0(\u2/u1/bank0_open_reg_n_0 ), + .I1(\u2/u1/bank3_open_reg_n_0 ), + .I2(\u2/u1/bank1_open_reg_n_0 ), + .I3(bank_adr[1]), + .I4(bank_adr[0]), + .I5(\u2/u1/bank2_open_reg_n_0 ), + .O(bank_open_i_2_n_0)); + LUT6 #( + .INIT(64'h3355000F3355FF0F)) + bank_open_i_3 + (.I0(\u2/bank1_open ), + .I1(\u2/bank3_open ), + .I2(\u2/bank0_open ), + .I3(bank_adr[1]), + .I4(bank_adr[0]), + .I5(\u2/bank2_open ), + .O(bank_open_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT1 #( + .INIT(2'h1)) + burst_act_rd_i_1 + (.I0(burst_act_rd_i_2_n_0), + .O(\u5/burst_act077_in )); + LUT6 #( + .INIT(64'h0000000000000004)) + burst_act_rd_i_2 + (.I0(\u5/burst_cnt_reg [4]), + .I1(\burst_cnt[6]_i_2_n_0 ), + .I2(\u5/burst_cnt_reg [3]), + .I3(\u5/burst_cnt_reg [9]), + .I4(\u5/burst_cnt_reg [6]), + .I5(burst_act_rd_i_3_n_0), + .O(burst_act_rd_i_2_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + burst_act_rd_i_3 + (.I0(\u5/burst_cnt_reg [10]), + .I1(\u5/burst_cnt_reg [8]), + .I2(\u5/burst_cnt_reg [7]), + .I3(\u5/burst_cnt_reg [5]), + .O(burst_act_rd_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h101F)) + \burst_cnt[0]_i_1 + (.I0(\timer[0]_i_3_n_0 ), + .I1(\timer[1]_i_2_n_0 ), + .I2(\u5/burst_cnt_ld ), + .I3(\u5/burst_cnt_reg [0]), + .O(p_0_in[0])); + LUT6 #( + .INIT(64'h0000000000004000)) + \burst_cnt[10]_i_1 + (.I0(\u5/state [6]), + .I1(\burst_cnt[10]_i_4_n_0 ), + .I2(\u5/state [5]), + .I3(\u5/state [3]), + .I4(\u5/state [0]), + .I5(\u5/state [1]), + .O(\u5/burst_cnt_ld_4 )); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT2 #( + .INIT(4'h2)) + \burst_cnt[10]_i_10 + (.I0(\u5/state [4]), + .I1(\u5/state [3]), + .O(\burst_cnt[10]_i_10_n_0 )); + LUT4 #( + .INIT(16'hFF5C)) + \burst_cnt[10]_i_2 + (.I0(\burst_cnt[10]_i_5_n_0 ), + .I1(dv), + .I2(wr_cycle), + .I3(\u5/burst_cnt_ld ), + .O(\burst_cnt[10]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0002FFFF00020000)) + \burst_cnt[10]_i_3 + (.I0(\timer[2]_i_2_n_0 ), + .I1(\col_adr[9]_i_3_n_0 ), + .I2(pack_le0_i_3_n_0), + .I3(pack_le0_i_2_n_0), + .I4(\u5/burst_cnt_ld ), + .I5(\burst_cnt[10]_i_7_n_0 ), + .O(p_0_in[10])); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT2 #( + .INIT(4'h2)) + \burst_cnt[10]_i_4 + (.I0(\u5/state [4]), + .I1(\u5/state [2]), + .O(\burst_cnt[10]_i_4_n_0 )); + LUT6 #( + .INIT(64'h00FE000000FE00FE)) + \burst_cnt[10]_i_5 + (.I0(\u5/state [6]), + .I1(\u5/state [0]), + .I2(\burst_cnt[10]_i_8_n_0 ), + .I3(mem_ack_r_i_4_n_0), + .I4(mem_ack_r_i_5_n_0), + .I5(mem_ack_r_i_6_n_0), + .O(\burst_cnt[10]_i_5_n_0 )); + LUT6 #( + .INIT(64'h0000000000010000)) + \burst_cnt[10]_i_6 + (.I0(\burst_cnt[10]_i_9_n_0 ), + .I1(\u5/state [3]), + .I2(\u5/state [4]), + .I3(\u5/state [6]), + .I4(\u5/state [0]), + .I5(\u5/state [5]), + .O(\u5/burst_cnt_ld )); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAA9AA)) + \burst_cnt[10]_i_7 + (.I0(\u5/burst_cnt_reg [10]), + .I1(\u5/burst_cnt_reg [9]), + .I2(\u5/burst_cnt_reg [7]), + .I3(\burst_cnt[7]_i_2_n_0 ), + .I4(\u5/burst_cnt_reg [6]), + .I5(\u5/burst_cnt_reg [8]), + .O(\burst_cnt[10]_i_7_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFF373F)) + \burst_cnt[10]_i_8 + (.I0(\u5/tmr_done ), + .I1(\burst_cnt[10]_i_10_n_0 ), + .I2(\u5/state [2]), + .I3(\u5/state [5]), + .I4(mem_ack_r_i_9_n_0), + .I5(mem_ack_r_i_8_n_0), + .O(\burst_cnt[10]_i_8_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT2 #( + .INIT(4'hE)) + \burst_cnt[10]_i_9 + (.I0(\u5/state [2]), + .I1(\u5/state [1]), + .O(\burst_cnt[10]_i_9_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT5 #( + .INIT(32'h2F20202F)) + \burst_cnt[1]_i_1 + (.I0(\timer[0]_i_3_n_0 ), + .I1(\timer[1]_i_2_n_0 ), + .I2(\u5/burst_cnt_ld ), + .I3(\u5/burst_cnt_reg [0]), + .I4(\u5/burst_cnt_reg [1]), + .O(p_0_in[1])); + LUT6 #( + .INIT(64'h0000A9A9FF00A9A9)) + \burst_cnt[2]_i_1 + (.I0(\u5/burst_cnt_reg [2]), + .I1(\u5/burst_cnt_reg [1]), + .I2(\u5/burst_cnt_reg [0]), + .I3(\burst_cnt[3]_i_3_n_0 ), + .I4(\u5/burst_cnt_ld ), + .I5(\timer[0]_i_3_n_0 ), + .O(p_0_in[2])); + LUT6 #( + .INIT(64'h000F666600006666)) + \burst_cnt[3]_i_1 + (.I0(\u5/burst_cnt_reg [3]), + .I1(\burst_cnt[6]_i_2_n_0 ), + .I2(\timer[2]_i_2_n_0 ), + .I3(\burst_cnt[3]_i_2_n_0 ), + .I4(\u5/burst_cnt_ld ), + .I5(\burst_cnt[3]_i_3_n_0 ), + .O(p_0_in[3])); + LUT6 #( + .INIT(64'h11101111DDDFDDDD)) + \burst_cnt[3]_i_2 + (.I0(\u0/tms_reg_n_0_[0] ), + .I1(lmr_ack), + .I2(\u5/state [6]), + .I3(\FSM_sequential_state[5]_i_4_n_0 ), + .I4(\burst_cnt[3]_i_4_n_0 ), + .I5(sp_tms[0]), + .O(\burst_cnt[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hEEEFEEEE22202222)) + \burst_cnt[3]_i_3 + (.I0(\u0/tms_reg_n_0_[1] ), + .I1(lmr_ack), + .I2(\u5/state [6]), + .I3(\FSM_sequential_state[5]_i_4_n_0 ), + .I4(\burst_cnt[3]_i_4_n_0 ), + .I5(sp_tms[1]), + .O(\burst_cnt[3]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT4 #( + .INIT(16'h0E30)) + \burst_cnt[3]_i_4 + (.I0(\u5/state [0]), + .I1(\u5/state [1]), + .I2(\u5/state [3]), + .I3(\u5/state [2]), + .O(\burst_cnt[3]_i_4_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFE0001)) + \burst_cnt[4]_i_1 + (.I0(\u5/burst_cnt_reg [2]), + .I1(\u5/burst_cnt_reg [0]), + .I2(\u5/burst_cnt_reg [1]), + .I3(\u5/burst_cnt_reg [3]), + .I4(\u5/burst_cnt_reg [4]), + .I5(\u5/burst_cnt_ld ), + .O(p_0_in[4])); + LUT5 #( + .INIT(32'h0000FB04)) + \burst_cnt[5]_i_1 + (.I0(\u5/burst_cnt_reg [3]), + .I1(\burst_cnt[6]_i_2_n_0 ), + .I2(\u5/burst_cnt_reg [4]), + .I3(\u5/burst_cnt_reg [5]), + .I4(\u5/burst_cnt_ld ), + .O(p_0_in[5])); + LUT6 #( + .INIT(64'h00000000FFFB0004)) + \burst_cnt[6]_i_1 + (.I0(\u5/burst_cnt_reg [4]), + .I1(\burst_cnt[6]_i_2_n_0 ), + .I2(\u5/burst_cnt_reg [3]), + .I3(\u5/burst_cnt_reg [5]), + .I4(\u5/burst_cnt_reg [6]), + .I5(\u5/burst_cnt_ld ), + .O(p_0_in[6])); + LUT3 #( + .INIT(8'h01)) + \burst_cnt[6]_i_2 + (.I0(\u5/burst_cnt_reg [1]), + .I1(\u5/burst_cnt_reg [0]), + .I2(\u5/burst_cnt_reg [2]), + .O(\burst_cnt[6]_i_2_n_0 )); + LUT4 #( + .INIT(16'h00D2)) + \burst_cnt[7]_i_1 + (.I0(\burst_cnt[7]_i_2_n_0 ), + .I1(\u5/burst_cnt_reg [6]), + .I2(\u5/burst_cnt_reg [7]), + .I3(\u5/burst_cnt_ld ), + .O(p_0_in[7])); + LUT6 #( + .INIT(64'h0000000000000001)) + \burst_cnt[7]_i_2 + (.I0(\u5/burst_cnt_reg [4]), + .I1(\u5/burst_cnt_reg [2]), + .I2(\u5/burst_cnt_reg [0]), + .I3(\u5/burst_cnt_reg [1]), + .I4(\u5/burst_cnt_reg [3]), + .I5(\u5/burst_cnt_reg [5]), + .O(\burst_cnt[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h020002FF02FF0200)) + \burst_cnt[8]_i_1 + (.I0(\timer[2]_i_2_n_0 ), + .I1(\burst_cnt[8]_i_2_n_0 ), + .I2(\burst_cnt[8]_i_3_n_0 ), + .I3(\u5/burst_cnt_ld ), + .I4(\u5/burst_cnt_reg [8]), + .I5(\burst_cnt[8]_i_4_n_0 ), + .O(p_0_in[8])); + LUT6 #( + .INIT(64'h5555454555504540)) + \burst_cnt[8]_i_2 + (.I0(pack_le0_i_3_n_0), + .I1(csc__0[7]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[7]), + .I4(csc__0[6]), + .I5(sp_csc[6]), + .O(\burst_cnt[8]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00053305)) + \burst_cnt[8]_i_3 + (.I0(sp_csc[5]), + .I1(csc[5]), + .I2(sp_csc[4]), + .I3(\timer2[6]_i_4_n_0 ), + .I4(csc[4]), + .O(\burst_cnt[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000010)) + \burst_cnt[8]_i_4 + (.I0(\u5/burst_cnt_reg [6]), + .I1(\u5/burst_cnt_reg [4]), + .I2(\burst_cnt[6]_i_2_n_0 ), + .I3(\u5/burst_cnt_reg [3]), + .I4(\u5/burst_cnt_reg [5]), + .I5(\u5/burst_cnt_reg [7]), + .O(\burst_cnt[8]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0828FFFF08280000)) + \burst_cnt[9]_i_1 + (.I0(\timer[2]_i_2_n_0 ), + .I1(pack_le0_i_2_n_0), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(pack_le0_i_3_n_0), + .I4(\u5/burst_cnt_ld ), + .I5(\burst_cnt[9]_i_2_n_0 ), + .O(p_0_in[9])); + LUT5 #( + .INIT(32'hAAAAA9AA)) + \burst_cnt[9]_i_2 + (.I0(\u5/burst_cnt_reg [9]), + .I1(\u5/burst_cnt_reg [8]), + .I2(\u5/burst_cnt_reg [6]), + .I3(\burst_cnt[7]_i_2_n_0 ), + .I4(\u5/burst_cnt_reg [7]), + .O(\burst_cnt[9]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \byte1[0]_i_1 + (.I0(mc_data_ir[0]), + .I1(pack_le1), + .I2(csc[4]), + .I3(mc_data_ir[8]), + .O(\byte1[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \byte1[1]_i_1 + (.I0(mc_data_ir[1]), + .I1(pack_le1), + .I2(csc[4]), + .I3(mc_data_ir[9]), + .O(\byte1[1]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \byte1[2]_i_1 + (.I0(mc_data_ir[2]), + .I1(pack_le1), + .I2(csc[4]), + .I3(mc_data_ir[10]), + .O(\byte1[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \byte1[3]_i_1 + (.I0(mc_data_ir[3]), + .I1(pack_le1), + .I2(csc[4]), + .I3(mc_data_ir[11]), + .O(\byte1[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \byte1[4]_i_1 + (.I0(mc_data_ir[4]), + .I1(pack_le1), + .I2(csc[4]), + .I3(mc_data_ir[12]), + .O(\byte1[4]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \byte1[5]_i_1 + (.I0(mc_data_ir[5]), + .I1(pack_le1), + .I2(csc[4]), + .I3(mc_data_ir[13]), + .O(\byte1[5]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \byte1[6]_i_1 + (.I0(mc_data_ir[6]), + .I1(pack_le1), + .I2(csc[4]), + .I3(mc_data_ir[14]), + .O(\byte1[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'h2320)) + \byte1[7]_i_1 + (.I0(pack_le0), + .I1(csc[5]), + .I2(csc[4]), + .I3(pack_le1), + .O(\byte1[7]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \byte1[7]_i_2 + (.I0(mc_data_ir[7]), + .I1(pack_le1), + .I2(csc[4]), + .I3(mc_data_ir[15]), + .O(\byte1[7]_i_2_n_0 )); + LUT5 #( + .INIT(32'h8A888A8A)) + cke__i_1 + (.I0(\u5/cke_r ), + .I1(cke__i_2_n_0), + .I2(\u5/state [6]), + .I3(cke__i_3_n_0), + .I4(cke__i_4_n_0), + .O(\u5/cke_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT5 #( + .INIT(32'h00000001)) + cke__i_2 + (.I0(\u5/state [1]), + .I1(\u5/state [5]), + .I2(\u5/state [2]), + .I3(\u5/state [4]), + .I4(\u5/state [3]), + .O(cke__i_2_n_0)); + LUT6 #( + .INIT(64'hFBFFFFFFFFFFFFFB)) + cke__i_3 + (.I0(\u5/state [5]), + .I1(\u5/state [4]), + .I2(\u5/state [2]), + .I3(\u5/state [3]), + .I4(\u5/state [1]), + .I5(\u5/state [0]), + .O(cke__i_3_n_0)); + LUT6 #( + .INIT(64'h755555557FFFFFFF)) + cke__i_4 + (.I0(\u5/state [3]), + .I1(mc_adv__i_3_n_0), + .I2(cke__i_5_n_0), + .I3(wb_cycle), + .I4(\u5/cnt ), + .I5(mc_cke_pad_o_), + .O(cke__i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT5 #( + .INIT(32'h55545555)) + cke__i_5 + (.I0(burst_act_rd_i_2_n_0), + .I1(\burst_cnt[3]_i_3_n_0 ), + .I2(\timer2[6]_i_3_n_0 ), + .I3(\mc_addr[2]_i_4_n_0 ), + .I4(\burst_cnt[3]_i_2_n_0 ), + .O(cke__i_5_n_0)); + LUT6 #( + .INIT(64'hFFFF3735FFFF0405)) + cke_r_i_1 + (.I0(cke_r_i_2_n_0), + .I1(cke_r_i_3_n_0), + .I2(\u5/state [6]), + .I3(cke_r_i_4_n_0), + .I4(cke__i_2_n_0), + .I5(\u5/cke_r ), + .O(cke_r_i_1_n_0)); + LUT6 #( + .INIT(64'h0000000003101000)) + cke_r_i_2 + (.I0(mc_adv__i_3_n_0), + .I1(\u5/state [5]), + .I2(\u5/state [4]), + .I3(\u5/state [2]), + .I4(\u5/state [3]), + .I5(cke_r_i_5_n_0), + .O(cke_r_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT5 #( + .INIT(32'h11111000)) + cke_r_i_3 + (.I0(\u5/state [6]), + .I1(\u5/cnt ), + .I2(cke__i_5_n_0), + .I3(wb_cycle), + .I4(\u5/state [3]), + .O(cke_r_i_3_n_0)); + LUT6 #( + .INIT(64'h0400000000000008)) + cke_r_i_4 + (.I0(\u5/state [3]), + .I1(\u5/state [4]), + .I2(\u5/state [5]), + .I3(\u5/state [2]), + .I4(\u5/state [1]), + .I5(\u5/state [0]), + .O(cke_r_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT3 #( + .INIT(8'h7E)) + cke_r_i_5 + (.I0(\u5/state [0]), + .I1(\u5/state [1]), + .I2(\u5/state [2]), + .O(cke_r_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT1 #( + .INIT(2'h1)) + cmd_a10_r_i_1 + (.I0(cmd_a10_r_i_2_n_0), + .O(cmd_a10)); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAA8AA)) + cmd_a10_r_i_10 + (.I0(\u5/state [6]), + .I1(\u5/state [1]), + .I2(\u5/state [5]), + .I3(\FSM_sequential_state[1]_i_13_n_0 ), + .I4(\u5/state [3]), + .I5(\u5/state [0]), + .O(cmd_a10_r_i_10_n_0)); + LUT6 #( + .INIT(64'h000000000000000D)) + cmd_a10_r_i_11 + (.I0(\u5/ap_en ), + .I1(\b3_last_row[12]_i_3_n_0 ), + .I2(rfr_ack), + .I3(\u5/state [3]), + .I4(\u5/state [2]), + .I5(\u5/state [5]), + .O(cmd_a10_r_i_11_n_0)); + LUT6 #( + .INIT(64'h0A0A0B0A0A0B0A0A)) + cmd_a10_r_i_12 + (.I0(\u5/ap_en ), + .I1(\u5/state [5]), + .I2(\u5/state [4]), + .I3(\u5/state [2]), + .I4(\u5/state [1]), + .I5(\u5/state [0]), + .O(cmd_a10_r_i_12_n_0)); + LUT6 #( + .INIT(64'h00000000DDDDFFFD)) + cmd_a10_r_i_2 + (.I0(\u5/state [4]), + .I1(\u5/state [6]), + .I2(cmd_a10_r_i_3_n_0), + .I3(cmd_a10_r_i_4_n_0), + .I4(cmd_a10_r_i_5_n_0), + .I5(cmd_a10_r_i_6_n_0), + .O(cmd_a10_r_i_2_n_0)); + LUT6 #( + .INIT(64'h5555555555555455)) + cmd_a10_r_i_3 + (.I0(\u5/ap_en ), + .I1(\b3_last_row[12]_i_4_n_0 ), + .I2(\u5/state [5]), + .I3(\u5/state [1]), + .I4(ap_en_i_2_n_0), + .I5(\cmd_r[0]_i_5_n_0 ), + .O(cmd_a10_r_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT5 #( + .INIT(32'h10110100)) + cmd_a10_r_i_4 + (.I0(\u5/state [0]), + .I1(\u5/state [5]), + .I2(\u5/state [1]), + .I3(\u5/state [3]), + .I4(\u5/state [2]), + .O(cmd_a10_r_i_4_n_0)); + LUT6 #( + .INIT(64'h00000000EEEEEEEF)) + cmd_a10_r_i_5 + (.I0(\u5/ap_en ), + .I1(cmd_a10_r_i_7_n_0), + .I2(\cmd_r[0]_i_5_n_0 ), + .I3(ap_en_i_2_n_0), + .I4(cmd_a10_r_i_8_n_0), + .I5(cmd_a10_r_i_9_n_0), + .O(cmd_a10_r_i_5_n_0)); + LUT6 #( + .INIT(64'h040004FF04000400)) + cmd_a10_r_i_6 + (.I0(\FSM_sequential_state[2]_i_16_n_0 ), + .I1(\u5/cmd_a10_r ), + .I2(rfr_ack_r_i_5_n_0), + .I3(cmd_a10_r_i_10_n_0), + .I4(cmd_a10_r_i_11_n_0), + .I5(cmd_a10_r_i_12_n_0), + .O(cmd_a10_r_i_6_n_0)); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT2 #( + .INIT(4'h8)) + cmd_a10_r_i_7 + (.I0(\u5/state [2]), + .I1(\u5/state [3]), + .O(cmd_a10_r_i_7_n_0)); + LUT6 #( + .INIT(64'h000000000F2FFF2F)) + cmd_a10_r_i_8 + (.I0(wb_cyc_i), + .I1(wb_stb_i), + .I2(wb_write_go), + .I3(\u5/state [1]), + .I4(\u5/tmr_done ), + .I5(mc_adv__i_2_n_0), + .O(cmd_a10_r_i_8_n_0)); + LUT6 #( + .INIT(64'hF7FFBBBB3333FFFF)) + cmd_a10_r_i_9 + (.I0(\u5/state [1]), + .I1(\timer[2]_i_17_n_0 ), + .I2(bank3_open_i_6_n_0), + .I3(\u5/cmd_a10_r ), + .I4(\u5/state [2]), + .I5(\u5/state [3]), + .O(cmd_a10_r_i_9_n_0)); + LUT6 #( + .INIT(64'h5555005155555555)) + cmd_asserted_i_1 + (.I0(\u5/state [6]), + .I1(cmd_asserted_i_2_n_0), + .I2(cmd_asserted_i_3_n_0), + .I3(\u5/state [5]), + .I4(cmd_asserted_i_4_n_0), + .I5(\mc_cs_[1]_i_3_n_0 ), + .O(cmd_asserted_i_1_n_0)); + LUT5 #( + .INIT(32'hFFFACCFA)) + cmd_asserted_i_10 + (.I0(sp_tms[16]), + .I1(\u0/tms_reg_n_0_[16] ), + .I2(sp_tms[17]), + .I3(\timer2[6]_i_4_n_0 ), + .I4(\u0/tms_reg_n_0_[17] ), + .O(cmd_asserted_i_10_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFDD0D)) + cmd_asserted_i_2 + (.I0(oe__i_3_n_0), + .I1(cmd_asserted_i_5_n_0), + .I2(\u5/state [1]), + .I3(\u5/state [0]), + .I4(\u5/state [4]), + .I5(\u5/state [2]), + .O(cmd_asserted_i_2_n_0)); + LUT6 #( + .INIT(64'hFAFAAFBAAAAAFAAA)) + cmd_asserted_i_3 + (.I0(cmd_asserted_i_6_n_0), + .I1(\u5/wb_wait_r ), + .I2(\u5/state [2]), + .I3(\u5/state [3]), + .I4(\u5/state [1]), + .I5(\u5/state [0]), + .O(cmd_asserted_i_3_n_0)); + LUT6 #( + .INIT(64'hDDDDDDDD5555555D)) + cmd_asserted_i_4 + (.I0(rfr_ack_r_i_3_n_0), + .I1(\u5/state [5]), + .I2(cmd_asserted_i_7_n_0), + .I3(\u5/state [1]), + .I4(\u5/state [4]), + .I5(cmd_asserted_i_8_n_0), + .O(cmd_asserted_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'hFF4FFFFF)) + cmd_asserted_i_5 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(wb_write_go), + .I2(\mc_addr[14]_i_4_n_0 ), + .I3(\u5/state [1]), + .I4(\u5/state [0]), + .O(cmd_asserted_i_5_n_0)); + LUT6 #( + .INIT(64'h22F0000000F00000)) + cmd_asserted_i_6 + (.I0(\u5/tmr_done ), + .I1(ap_en_i_2_n_0), + .I2(\u5/state [0]), + .I3(\u5/state [3]), + .I4(cmd_asserted_i_9_n_0), + .I5(\u5/state [2]), + .O(cmd_asserted_i_6_n_0)); + LUT6 #( + .INIT(64'h0002220200000000)) + cmd_asserted_i_7 + (.I0(\timer2[3]_i_4_n_0 ), + .I1(cmd_asserted_i_10_n_0), + .I2(sp_tms[18]), + .I3(\timer2[6]_i_4_n_0 ), + .I4(\u0/tms_reg_n_0_[18] ), + .I5(\u5/state [0]), + .O(cmd_asserted_i_7_n_0)); + LUT6 #( + .INIT(64'h000FF00A0551FAA2)) + cmd_asserted_i_8 + (.I0(\u5/state [2]), + .I1(\u5/tmr_done ), + .I2(\u5/state [3]), + .I3(\u5/state [0]), + .I4(\u5/state [4]), + .I5(\u5/state [1]), + .O(cmd_asserted_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h8)) + cmd_asserted_i_9 + (.I0(\u5/state [1]), + .I1(\u5/state [4]), + .O(cmd_asserted_i_9_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFF01000000)) + \cmd_r[0]_i_1 + (.I0(\u5/state [2]), + .I1(\u5/state [1]), + .I2(\u5/state [6]), + .I3(\cmd_r[0]_i_2_n_0 ), + .I4(\cmd_r[0]_i_3_n_0 ), + .I5(\cmd_r[0]_i_4_n_0 ), + .O(\u5/cmd [0])); + LUT6 #( + .INIT(64'h00FFFFFFFFFF08FF)) + \cmd_r[0]_i_10 + (.I0(\u5/state [3]), + .I1(\u5/tmr_done ), + .I2(ap_en_i_2_n_0), + .I3(cmd_asserted_i_9_n_0), + .I4(\u5/state [5]), + .I5(\u5/state [0]), + .O(\cmd_r[0]_i_10_n_0 )); + LUT6 #( + .INIT(64'h00CC00CC330F0008)) + \cmd_r[0]_i_11 + (.I0(\u5/tmr_done ), + .I1(\u5/state [4]), + .I2(\u5/state [3]), + .I3(\u5/state [1]), + .I4(\u5/state [2]), + .I5(\u5/state [0]), + .O(\cmd_r[0]_i_11_n_0 )); + LUT6 #( + .INIT(64'h007A0000FFFA0000)) + \cmd_r[0]_i_12 + (.I0(\u5/state [5]), + .I1(\u5/state [3]), + .I2(\u5/state [0]), + .I3(\u5/state [4]), + .I4(\u5/state [1]), + .I5(\u5/state [2]), + .O(\cmd_r[0]_i_12_n_0 )); + LUT6 #( + .INIT(64'h003F003000002203)) + \cmd_r[0]_i_13 + (.I0(\FSM_sequential_state[1]_i_13_n_0 ), + .I1(\u5/state [1]), + .I2(\u5/state [0]), + .I3(\u5/state [6]), + .I4(\u5/state [3]), + .I5(\u5/state [5]), + .O(\cmd_r[0]_i_13_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT2 #( + .INIT(4'h2)) + \cmd_r[0]_i_2 + (.I0(\u5/state [3]), + .I1(\u5/state [0]), + .O(\cmd_r[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hCCC8FFFBFFFFFFFF)) + \cmd_r[0]_i_3 + (.I0(\u5/wb_write_go_r ), + .I1(\cmd_r[0]_i_5_n_0 ), + .I2(burst_act_rd_i_2_n_0), + .I3(\cmd_r[0]_i_6_n_0 ), + .I4(wb_cycle), + .I5(\u5/state [4]), + .O(\cmd_r[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFDF0000)) + \cmd_r[0]_i_4 + (.I0(\FSM_sequential_state[5]_i_8_n_0 ), + .I1(data_oe_r_i_7_n_0), + .I2(\cmd_r[0]_i_7_n_0 ), + .I3(\cmd_r[0]_i_8_n_0 ), + .I4(cke__i_2_n_0), + .I5(\cmd_r[0]_i_9_n_0 ), + .O(\cmd_r[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFDDDFD)) + \cmd_r[0]_i_5 + (.I0(\burst_cnt[3]_i_2_n_0 ), + .I1(\burst_cnt[3]_i_3_n_0 ), + .I2(sp_tms[2]), + .I3(\timer2[6]_i_4_n_0 ), + .I4(\u0/tms_reg_n_0_[2] ), + .I5(\mc_addr[9]_i_4_n_0 ), + .O(\cmd_r[0]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT4 #( + .INIT(16'h3533)) + \cmd_r[0]_i_6 + (.I0(mc_adv__i_3_n_0), + .I1(\u5/cke_r ), + .I2(\u5/cnt ), + .I3(\cmd_r[0]_i_5_n_0 ), + .O(\cmd_r[0]_i_6_n_0 )); + LUT6 #( + .INIT(64'h000080800A008A80)) + \cmd_r[0]_i_7 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(csc[1]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[1]), + .I4(csc[3]), + .I5(sp_csc[3]), + .O(\cmd_r[0]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h4F)) + \cmd_r[0]_i_8 + (.I0(\mc_cs_[0]_i_2_n_0 ), + .I1(\mc_cs_[1]_i_2_n_0 ), + .I2(\u5/lookup_ready2 ), + .O(\cmd_r[0]_i_8_n_0 )); + LUT5 #( + .INIT(32'hFFFF00FD)) + \cmd_r[0]_i_9 + (.I0(\cmd_r[0]_i_10_n_0 ), + .I1(\cmd_r[0]_i_11_n_0 ), + .I2(\cmd_r[0]_i_12_n_0 ), + .I3(\u5/state [6]), + .I4(\cmd_r[0]_i_13_n_0 ), + .O(\cmd_r[0]_i_9_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAAFFFFBBAB)) + \cmd_r[1]_i_1 + (.I0(cke__i_2_n_0), + .I1(\cmd_r[1]_i_2_n_0 ), + .I2(\cmd_r[1]_i_3_n_0 ), + .I3(\cmd_r[1]_i_4_n_0 ), + .I4(\cmd_r[1]_i_5_n_0 ), + .I5(\u5/state [6]), + .O(\u5/cmd [1])); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'hBA)) + \cmd_r[1]_i_2 + (.I0(\u5/state [0]), + .I1(\u5/state [1]), + .I2(\u5/state [2]), + .O(\cmd_r[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h2)) + \cmd_r[1]_i_3 + (.I0(\u5/state [4]), + .I1(\u5/state [1]), + .O(\cmd_r[1]_i_3_n_0 )); + LUT5 #( + .INIT(32'h5455FFFF)) + \cmd_r[1]_i_4 + (.I0(\mc_addr[9]_i_4_n_0 ), + .I1(\mc_addr[2]_i_4_n_0 ), + .I2(\burst_cnt[3]_i_3_n_0 ), + .I3(\burst_cnt[3]_i_2_n_0 ), + .I4(wb_cycle), + .O(\cmd_r[1]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFF3FCF3F2F3FCFF)) + \cmd_r[1]_i_5 + (.I0(\u5/state [0]), + .I1(\u5/state [1]), + .I2(\u5/state [5]), + .I3(\u5/state [3]), + .I4(\u5/state [2]), + .I5(\u5/state [4]), + .O(\cmd_r[1]_i_5_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAAFFFFAAAE)) + \cmd_r[2]_i_1 + (.I0(cke__i_2_n_0), + .I1(\u5/state [3]), + .I2(\u5/state [0]), + .I3(\cmd_r[2]_i_2_n_0 ), + .I4(\cmd_r[2]_i_3_n_0 ), + .I5(\u5/state [6]), + .O(\u5/cmd [2])); + LUT6 #( + .INIT(64'h02A2FFFFFFFF0000)) + \cmd_r[2]_i_2 + (.I0(\u5/tmr_done ), + .I1(sp_csc[10]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(csc__0[10]), + .I4(\u5/state [2]), + .I5(\u5/state [1]), + .O(\cmd_r[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4022)) + \cmd_r[2]_i_3 + (.I0(\u5/state [2]), + .I1(\u5/state [0]), + .I2(\u5/state [1]), + .I3(\u5/state [3]), + .I4(\cmd_r[2]_i_4_n_0 ), + .I5(\u5/state [5]), + .O(\cmd_r[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'h9F609F609F609360)) + \cmd_r[2]_i_4 + (.I0(\u5/state [0]), + .I1(\u5/state [2]), + .I2(\u5/state [1]), + .I3(\u5/state [4]), + .I4(\u5/wb_wait_r ), + .I5(\u5/state [3]), + .O(\cmd_r[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0000008800000002)) + cnt_i_1 + (.I0(cnt_i_2_n_0), + .I1(\u5/state [0]), + .I2(\u5/state [2]), + .I3(\u5/state [6]), + .I4(\u5/cnt ), + .I5(\u5/state [1]), + .O(\u5/cnt_next )); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT4 #( + .INIT(16'h0440)) + cnt_i_2 + (.I0(\u5/state [5]), + .I1(\u5/state [4]), + .I2(\u5/state [3]), + .I3(\u5/state [2]), + .O(cnt_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT4 #( + .INIT(16'h0222)) + \col_adr[8]_i_1 + (.I0(wb_addr_i[10]), + .I1(pack_le0_i_3_n_0), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(pack_le0_i_2_n_0), + .O(\u1/col_adr [8])); + LUT3 #( + .INIT(8'hB8)) + \col_adr[9]_i_1 + (.I0(mem_ack_r), + .I1(wr_cycle), + .I2(wb_stb_i), + .O(\col_adr[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT4 #( + .INIT(16'h0010)) + \col_adr[9]_i_2 + (.I0(\col_adr[9]_i_3_n_0 ), + .I1(pack_le0_i_3_n_0), + .I2(wb_addr_i[11]), + .I3(pack_le0_i_2_n_0), + .O(\u1/col_adr [9])); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT5 #( + .INIT(32'h00053305)) + \col_adr[9]_i_3 + (.I0(sp_csc[6]), + .I1(csc__0[6]), + .I2(sp_csc[7]), + .I3(\timer2[6]_i_4_n_0 ), + .I4(csc__0[7]), + .O(\col_adr[9]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT5 #( + .INIT(32'h07FF0700)) + \cs[0]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(cs_le), + .I4(cs[0]), + .O(\cs[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF0000FF51)) + cs_le_i_1 + (.I0(cs_le_i_2_n_0), + .I1(cs_le_i_3_n_0), + .I2(cs_le_i_4_n_0), + .I3(cs_le_i_5_n_0), + .I4(\FSM_sequential_state[2]_i_4_n_0 ), + .I5(cs_le_i_6_n_0), + .O(cs_le_d)); + LUT6 #( + .INIT(64'h55CF55FF55FF55FF)) + cs_le_i_10 + (.I0(\FSM_sequential_state[2]_i_21_n_0 ), + .I1(\u5/p_65_in ), + .I2(cs_le_i_14_n_0), + .I3(\u5/state [5]), + .I4(ap_en_i_2_n_0), + .I5(\u5/tmr_done ), + .O(cs_le_i_10_n_0)); + LUT2 #( + .INIT(4'h8)) + cs_le_i_11 + (.I0(mc_adv__i_3_n_0), + .I1(\u5/state [4]), + .O(cs_le_i_11_n_0)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h1)) + cs_le_i_12 + (.I0(\u5/state [0]), + .I1(\u5/state [6]), + .O(cs_le_i_12_n_0)); + LUT6 #( + .INIT(64'h8000000088888888)) + cs_le_i_13 + (.I0(\u5/state [6]), + .I1(cke__i_2_n_0), + .I2(mc_adv__i_3_n_0), + .I3(wb_cycle), + .I4(\u5/tmr_done ), + .I5(\u5/state [0]), + .O(cs_le_i_13_n_0)); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'h80)) + cs_le_i_14 + (.I0(\u5/state [1]), + .I1(\u5/state [2]), + .I2(\u5/state [3]), + .O(cs_le_i_14_n_0)); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT5 #( + .INIT(32'hFEFFFFFE)) + cs_le_i_2 + (.I0(\u5/state [3]), + .I1(\u5/state [2]), + .I2(\u5/state [5]), + .I3(\u5/state [4]), + .I4(\u5/state [1]), + .O(cs_le_i_2_n_0)); + LUT6 #( + .INIT(64'hEAEEEAEEEEEEEAEE)) + cs_le_i_3 + (.I0(rfr_req), + .I1(\FSM_sequential_state[5]_i_8_n_0 ), + .I2(\FSM_sequential_state[5]_i_9_n_0 ), + .I3(cs_le_i_7_n_0), + .I4(wb_cyc_i), + .I5(wb_stb_i), + .O(cs_le_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT2 #( + .INIT(4'hE)) + cs_le_i_4 + (.I0(\u5/state [1]), + .I1(\u5/wb_stb_first_reg_n_0 ), + .O(cs_le_i_4_n_0)); + LUT6 #( + .INIT(64'hF000F080F0000000)) + cs_le_i_5 + (.I0(\u5/tmr2_done ), + .I1(mc_adv__i_3_n_0), + .I2(wb_ack_o_i_9_n_0), + .I3(\u5/state [3]), + .I4(\u5/state [1]), + .I5(wb_cycle), + .O(cs_le_i_5_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFF8F880000)) + cs_le_i_6 + (.I0(cs_le_i_8_n_0), + .I1(cs_le_i_9_n_0), + .I2(cs_le_i_10_n_0), + .I3(cs_le_i_11_n_0), + .I4(cs_le_i_12_n_0), + .I5(cs_le_i_13_n_0), + .O(cs_le_i_6_n_0)); + LUT5 #( + .INIT(32'hFFFACCFA)) + cs_le_i_7 + (.I0(sp_csc[2]), + .I1(csc[2]), + .I2(sp_csc[1]), + .I3(\timer2[6]_i_4_n_0 ), + .I4(csc[1]), + .O(cs_le_i_7_n_0)); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT2 #( + .INIT(4'h2)) + cs_le_i_8 + (.I0(\u5/state [2]), + .I1(\u5/state [1]), + .O(cs_le_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT3 #( + .INIT(8'h01)) + cs_le_i_9 + (.I0(\u5/state [3]), + .I1(\u5/state [4]), + .I2(\u5/state [5]), + .O(cs_le_i_9_n_0)); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT4 #( + .INIT(16'hEFE0)) + \csc[0]_i_1 + (.I0(poc_o[3]), + .I1(poc_o[2]), + .I2(\u0/rst_r2 ), + .I3(wb_data_i[0]), + .O(\csc[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \csc[10]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(\u0/u0/csc_reg_n_0_[10] ), + .I4(\u0/u1/csc_reg_n_0_[10] ), + .I5(\u0/sel0 ), + .O(\csc[10]_i_1_n_0 )); + LUT3 #( + .INIT(8'h80)) + \csc[11]_i_1 + (.I0(cs_le_d), + .I1(wb_cyc_i), + .I2(wb_stb_i), + .O(\csc[11]_i_1_n_0 )); + LUT6 #( + .INIT(64'h48FF4848FF484848)) + \csc[11]_i_10 + (.I0(wb_addr_i[21]), + .I1(\u0/csc_mask [0]), + .I2(\u0/u1/csc_reg_n_0_[16] ), + .I3(wb_addr_i[22]), + .I4(\u0/csc_mask [1]), + .I5(\u0/u1/csc_reg_n_0_[17] ), + .O(\csc[11]_i_10_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF60FF)) + \csc[11]_i_11 + (.I0(\u0/u1/csc_reg_n_0_[23] ), + .I1(wb_addr_i[28]), + .I2(\u0/csc_mask [7]), + .I3(\u0/u1/csc_reg_n_0_[0] ), + .I4(\csc[11]_i_12_n_0 ), + .I5(\csc[11]_i_13_n_0 ), + .O(\csc[11]_i_11_n_0 )); + LUT6 #( + .INIT(64'h4848FF48FF484848)) + \csc[11]_i_12 + (.I0(wb_addr_i[24]), + .I1(\u0/csc_mask [3]), + .I2(\u0/u1/csc_reg_n_0_[19] ), + .I3(\u0/csc_mask [4]), + .I4(wb_addr_i[25]), + .I5(\u0/u1/csc_reg_n_0_[20] ), + .O(\csc[11]_i_12_n_0 )); + LUT6 #( + .INIT(64'h4848FF48FF484848)) + \csc[11]_i_13 + (.I0(wb_addr_i[23]), + .I1(\u0/csc_mask [2]), + .I2(\u0/u1/csc_reg_n_0_[18] ), + .I3(\u0/csc_mask [6]), + .I4(wb_addr_i[27]), + .I5(\u0/u1/csc_reg_n_0_[22] ), + .O(\csc[11]_i_13_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \csc[11]_i_2 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(\u0/u0/csc_reg_n_0_[11] ), + .I4(\u0/u1/csc_reg_n_0_[11] ), + .I5(\u0/sel0 ), + .O(\csc[11]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFFBEAA)) + \csc[11]_i_3 + (.I0(\csc[11]_i_5_n_0 ), + .I1(wb_addr_i[24]), + .I2(\u0/u0/csc_reg_n_0_[19] ), + .I3(\u0/csc_mask [3]), + .I4(\csc[11]_i_6_n_0 ), + .O(\csc[11]_i_3_n_0 )); + LUT3 #( + .INIT(8'h07)) + \csc[11]_i_4 + (.I0(wb_we_i), + .I1(\u0/u1/csc_reg_n_0_[8] ), + .I2(\csc[11]_i_7_n_0 ), + .O(\u0/sel0 )); + LUT6 #( + .INIT(64'h2828FF28FF282828)) + \csc[11]_i_5 + (.I0(\u0/csc_mask [0]), + .I1(\u0/u0/csc_reg_n_0_[16] ), + .I2(wb_addr_i[21]), + .I3(\u0/csc_mask [1]), + .I4(\u0/u0/csc_reg_n_0_[17] ), + .I5(wb_addr_i[22]), + .O(\csc[11]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF7D55)) + \csc[11]_i_6 + (.I0(\u0/u0/csc_reg_n_0_[0] ), + .I1(wb_addr_i[28]), + .I2(\u0/u0/csc_reg_n_0_[23] ), + .I3(\u0/csc_mask [7]), + .I4(\csc[11]_i_8_n_0 ), + .I5(\csc[11]_i_9_n_0 ), + .O(\csc[11]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFFFFBEAA)) + \csc[11]_i_7 + (.I0(\csc[11]_i_10_n_0 ), + .I1(\u0/u1/csc_reg_n_0_[21] ), + .I2(wb_addr_i[26]), + .I3(\u0/csc_mask [5]), + .I4(\csc[11]_i_11_n_0 ), + .O(\csc[11]_i_7_n_0 )); + LUT6 #( + .INIT(64'h2828FF28FF282828)) + \csc[11]_i_8 + (.I0(\u0/csc_mask [2]), + .I1(\u0/u0/csc_reg_n_0_[18] ), + .I2(wb_addr_i[23]), + .I3(\u0/csc_mask [6]), + .I4(\u0/u0/csc_reg_n_0_[22] ), + .I5(wb_addr_i[27]), + .O(\csc[11]_i_8_n_0 )); + LUT6 #( + .INIT(64'h2828FF28FF282828)) + \csc[11]_i_9 + (.I0(\u0/csc_mask [4]), + .I1(\u0/u0/csc_reg_n_0_[20] ), + .I2(wb_addr_i[25]), + .I3(\u0/csc_mask [5]), + .I4(\u0/u0/csc_reg_n_0_[21] ), + .I5(wb_addr_i[26]), + .O(\csc[11]_i_9_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \csc[1]_i_1 + (.I0(poc_o[2]), + .I1(\u0/rst_r2 ), + .I2(wb_data_i[1]), + .O(\csc[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \csc[1]_i_1__0 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(\u0/u0/csc_reg_n_0_[1] ), + .I4(\u0/u1/csc_reg_n_0_[1] ), + .I5(\u0/sel0 ), + .O(\csc[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT3 #( + .INIT(8'hB8)) + \csc[2]_i_1 + (.I0(poc_o[3]), + .I1(\u0/rst_r2 ), + .I2(wb_data_i[2]), + .O(\csc[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \csc[2]_i_1__0 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(\u0/u0/csc_reg_n_0_[2] ), + .I4(\u0/u1/csc_reg_n_0_[2] ), + .I5(\u0/sel0 ), + .O(\csc[2]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'h0000004000000000)) + \csc[31]_i_1 + (.I0(\u0/p_0_in1_in ), + .I1(\u0/rf_we ), + .I2(\u0/p_0_in [0]), + .I3(\u0/p_0_in [2]), + .I4(\u0/p_0_in [3]), + .I5(\u0/p_0_in [1]), + .O(\csc[31]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \csc[3]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(\u0/u0/csc_reg_n_0_[3] ), + .I4(\u0/u1/csc_reg_n_0_[3] ), + .I5(\u0/sel0 ), + .O(\csc[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hB8)) + \csc[4]_i_1 + (.I0(poc_o[0]), + .I1(\u0/rst_r2 ), + .I2(wb_data_i[4]), + .O(\csc[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \csc[4]_i_1__0 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(\u0/u0/csc_reg_n_0_[4] ), + .I4(\u0/u1/csc_reg_n_0_[4] ), + .I5(\u0/sel0 ), + .O(\csc[4]_i_1__0_n_0 )); + LUT2 #( + .INIT(4'hE)) + \csc[5]_i_1 + (.I0(\u0/rst_r2 ), + .I1(init_req_we_i_1_n_0), + .O(\csc[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \csc[5]_i_1__0 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(\u0/u0/csc_reg_n_0_[5] ), + .I4(\u0/u1/csc_reg_n_0_[5] ), + .I5(\u0/sel0 ), + .O(\csc[5]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hB8)) + \csc[5]_i_2 + (.I0(poc_o[1]), + .I1(\u0/rst_r2 ), + .I2(wb_data_i[5]), + .O(\csc[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \csc[6]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(\u0/u0/csc_reg_n_0_[6] ), + .I4(\u0/u1/csc_reg_n_0_[6] ), + .I5(\u0/sel0 ), + .O(\csc[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \csc[7]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(\u0/u0/csc_reg_n_0_[7] ), + .I4(\u0/u1/csc_reg_n_0_[7] ), + .I5(\u0/sel0 ), + .O(\csc[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \csc[9]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(\u0/u0/csc_reg_n_0_[9] ), + .I4(\u0/u1/csc_reg_n_0_[9] ), + .I5(\u0/sel0 ), + .O(\csc[9]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000008)) + \csc_mask_r[10]_i_1 + (.I0(\u0/p_0_in [0]), + .I1(\u0/rf_we ), + .I2(\u0/p_0_in1_in ), + .I3(\u0/p_0_in [1]), + .I4(\u0/p_0_in [3]), + .I5(\u0/p_0_in [2]), + .O(\u0/csc_mask_r0 )); + LUT6 #( + .INIT(64'h0000000000000004)) + \csr_r[1]_i_1 + (.I0(\u0/p_0_in [0]), + .I1(\u0/rf_we ), + .I2(\u0/p_0_in1_in ), + .I3(\u0/p_0_in [1]), + .I4(\u0/p_0_in [3]), + .I5(\u0/p_0_in [2]), + .O(\u0/csr_r20 )); + LUT6 #( + .INIT(64'h8888888B8B8B888B)) + data_oe_i_1 + (.I0(\u5/data_oe_r2 ), + .I1(wr_cycle), + .I2(\u5/state [6]), + .I3(data_oe_i_2_n_0), + .I4(\u5/state [1]), + .I5(data_oe_r_i_4_n_0), + .O(data_oe_i_1_n_0)); + LUT6 #( + .INIT(64'hBBB8BBB8B8B8BBB8)) + data_oe_i_2 + (.I0(data_oe_r_i_3_n_0), + .I1(\u5/state [3]), + .I2(data_oe_r_i_5_n_0), + .I3(mc_c_oe_i_5_n_0), + .I4(data_oe_i_3_n_0), + .I5(data_oe_r_i_6_n_0), + .O(data_oe_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT4 #( + .INIT(16'h0800)) + data_oe_i_3 + (.I0(wb_write_go), + .I1(\FSM_sequential_state[5]_i_8_n_0 ), + .I2(\u5/state [4]), + .I3(\u5/state [0]), + .O(data_oe_i_3_n_0)); + LUT6 #( + .INIT(64'h0000015155550151)) + data_oe_r_i_1 + (.I0(\u5/state [6]), + .I1(data_oe_r_i_2_n_0), + .I2(\u5/state [3]), + .I3(data_oe_r_i_3_n_0), + .I4(\u5/state [1]), + .I5(data_oe_r_i_4_n_0), + .O(data_oe_r_i_1_n_0)); + LUT6 #( + .INIT(64'hEEEEEEEEEAEEEEEE)) + data_oe_r_i_2 + (.I0(data_oe_r_i_5_n_0), + .I1(mc_c_oe_i_5_n_0), + .I2(\FSM_sequential_state[6]_i_21_n_0 ), + .I3(\FSM_sequential_state[5]_i_8_n_0 ), + .I4(wb_write_go), + .I5(data_oe_r_i_6_n_0), + .O(data_oe_r_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT4 #( + .INIT(16'hFEFF)) + data_oe_r_i_3 + (.I0(\u5/state [0]), + .I1(\u5/state [5]), + .I2(\u5/state [2]), + .I3(\u5/state [4]), + .O(data_oe_r_i_3_n_0)); + LUT6 #( + .INIT(64'hFD7F77FFF57F77FF)) + data_oe_r_i_4 + (.I0(\u5/state [2]), + .I1(\u5/state [0]), + .I2(\u5/state [3]), + .I3(\u5/state [4]), + .I4(\u5/state [5]), + .I5(data_oe_r_i_7_n_0), + .O(data_oe_r_i_4_n_0)); + LUT6 #( + .INIT(64'hFCFCF8FCFCCCC8CC)) + data_oe_r_i_5 + (.I0(data_oe_r_i_7_n_0), + .I1(\u5/state [2]), + .I2(\u5/state [5]), + .I3(\u5/state [4]), + .I4(\u5/state [0]), + .I5(cmd_asserted_i_7_n_0), + .O(data_oe_r_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'hABABFFAB)) + data_oe_r_i_6 + (.I0(\FSM_sequential_state[5]_i_9_n_0 ), + .I1(\mc_addr[23]_i_3_n_0 ), + .I2(\mc_addr[14]_i_4_n_0 ), + .I3(wb_cyc_i), + .I4(wb_stb_i), + .O(data_oe_r_i_6_n_0)); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT3 #( + .INIT(8'h4F)) + data_oe_r_i_7 + (.I0(wb_stb_i), + .I1(wb_cyc_i), + .I2(wb_write_go), + .O(data_oe_r_i_7_n_0)); + LUT6 #( + .INIT(64'h00000000FFFF0040)) + dv_r_i_1 + (.I0(\u5/state [0]), + .I1(\u5/state [5]), + .I2(\u5/mc_adv_r ), + .I3(\u5/dv_r ), + .I4(dv_r_i_2_n_0), + .I5(dv_r_i_3_n_0), + .O(dv)); + LUT6 #( + .INIT(64'h0000400000000000)) + dv_r_i_2 + (.I0(\u5/state [5]), + .I1(\u5/state [0]), + .I2(wb_cycle), + .I3(\u5/cke_o_del ), + .I4(\u5/cnt ), + .I5(\u5/burst_act_rd ), + .O(dv_r_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT5 #( + .INIT(32'hFFFFF7FF)) + dv_r_i_3 + (.I0(\u5/state [1]), + .I1(\u5/state [3]), + .I2(\u5/state [6]), + .I3(\u5/state [4]), + .I4(\u5/state [2]), + .O(dv_r_i_3_n_0)); + LUT6 #( + .INIT(64'h0000000000002624)) + init_ack_r_i_1 + (.I0(\u5/state [2]), + .I1(\u5/state [3]), + .I2(\u5/state [1]), + .I3(\u5/state [0]), + .I4(\FSM_sequential_state[5]_i_4_n_0 ), + .I5(\u5/state [6]), + .O(init_ack)); + LUT2 #( + .INIT(4'hE)) + init_req_i_1 + (.I0(\u0/u1/init_req_reg_n_0 ), + .I1(\u0/u0/init_req_reg_n_0 ), + .O(\u0/init_req01_out )); + LUT6 #( + .INIT(64'hBFBBBBBB0F000000)) + init_req_i_1__0 + (.I0(init_req_i_2_n_0), + .I1(spec_req_cs[0]), + .I2(\u0/inited ), + .I3(\u0/init_req_we ), + .I4(rfr_en_i_2_n_0), + .I5(\u0/u0/init_req_reg_n_0 ), + .O(init_req_i_1__0_n_0)); + LUT6 #( + .INIT(64'hBFBBBBBB0F000000)) + init_req_i_1__1 + (.I0(init_req_i_2_n_0), + .I1(spec_req_cs[1]), + .I2(\u0/u1/inited_reg_n_0 ), + .I3(\u0/u1/init_req_we_reg_n_0 ), + .I4(init_req_i_2__0_n_0), + .I5(\u0/u1/init_req_reg_n_0 ), + .O(init_req_i_1__1_n_0)); + LUT6 #( + .INIT(64'h00540500FFFFFFFF)) + init_req_i_2 + (.I0(lmr_ack_i_3_n_0), + .I1(\u5/state [0]), + .I2(\u5/state [1]), + .I3(\u5/state [3]), + .I4(\u5/state [2]), + .I5(\u0/init_ack_r ), + .O(init_req_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT4 #( + .INIT(16'h0002)) + init_req_i_2__0 + (.I0(\u0/u1/csc_reg_n_0_[0] ), + .I1(\u0/u1/csc_reg_n_0_[1] ), + .I2(\u0/u1/csc_reg_n_0_[3] ), + .I3(\u0/u1/csc_reg_n_0_[2] ), + .O(init_req_i_2__0_n_0)); + LUT6 #( + .INIT(64'h0000000400000000)) + init_req_we_i_1 + (.I0(\u0/p_0_in1_in ), + .I1(\u0/rf_we ), + .I2(\u0/p_0_in [0]), + .I3(\u0/p_0_in [2]), + .I4(\u0/p_0_in [3]), + .I5(\u0/p_0_in [1]), + .O(init_req_we_i_1_n_0)); + LUT4 #( + .INIT(16'hFF40)) + inited_i_1 + (.I0(init_ack), + .I1(\u0/init_ack_r ), + .I2(spec_req_cs[1]), + .I3(\u0/u1/inited_reg_n_0 ), + .O(inited_i_1_n_0)); + LUT4 #( + .INIT(16'hFF40)) + inited_i_1__0 + (.I0(init_ack), + .I1(\u0/init_ack_r ), + .I2(spec_req_cs[0]), + .I3(\u0/inited ), + .O(inited_i_1__0_n_0)); + LUT1 #( + .INIT(2'h1)) + \ir_cnt[0]_i_1 + (.I0(\u5/ir_cnt_reg [0]), + .O(ir_cnt0[0])); + LUT2 #( + .INIT(4'h9)) + \ir_cnt[1]_i_1 + (.I0(\u5/ir_cnt_reg [0]), + .I1(\u5/ir_cnt_reg [1]), + .O(\ir_cnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT3 #( + .INIT(8'hA9)) + \ir_cnt[2]_i_1 + (.I0(\u5/ir_cnt_reg [2]), + .I1(\u5/ir_cnt_reg [1]), + .I2(\u5/ir_cnt_reg [0]), + .O(ir_cnt0[2])); + LUT6 #( + .INIT(64'h0000000000080000)) + \ir_cnt[3]_i_1 + (.I0(\FSM_sequential_state[4]_i_6_n_0 ), + .I1(\u5/state [0]), + .I2(\u5/state [5]), + .I3(\u5/state [4]), + .I4(\u5/state [2]), + .I5(\u5/state [1]), + .O(\u5/ir_cnt_ld )); + LUT5 #( + .INIT(32'h00800000)) + \ir_cnt[3]_i_2 + (.I0(\ir_cnt[3]_i_4_n_0 ), + .I1(\u5/state [2]), + .I2(\u5/state [1]), + .I3(\u5/state [4]), + .I4(\u5/cmd_asserted ), + .O(\u5/ir_cnt_dec )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT4 #( + .INIT(16'hAAA9)) + \ir_cnt[3]_i_3 + (.I0(\u5/ir_cnt_reg [3]), + .I1(\u5/ir_cnt_reg [2]), + .I2(\u5/ir_cnt_reg [0]), + .I3(\u5/ir_cnt_reg [1]), + .O(ir_cnt0[3])); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT4 #( + .INIT(16'h0004)) + \ir_cnt[3]_i_4 + (.I0(\u5/state [5]), + .I1(\u5/state [0]), + .I2(\u5/state [6]), + .I3(\u5/state [3]), + .O(\ir_cnt[3]_i_4_n_0 )); + LUT4 #( + .INIT(16'h0001)) + ir_cnt_done_i_1 + (.I0(\u5/ir_cnt_reg [2]), + .I1(\u5/ir_cnt_reg [0]), + .I2(\u5/ir_cnt_reg [1]), + .I3(\u5/ir_cnt_reg [3]), + .O(ir_cnt_done_i_1_n_0)); + LUT6 #( + .INIT(64'h0000000000004148)) + lmr_ack_i_1 + (.I0(\u5/state [2]), + .I1(\u5/state [3]), + .I2(\u5/state [1]), + .I3(\u5/state [0]), + .I4(lmr_ack_i_2_n_0), + .I5(lmr_ack_i_3_n_0), + .O(\u5/lmr_ack_d )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT5 #( + .INIT(32'h54555555)) + lmr_ack_i_2 + (.I0(\u5/state [3]), + .I1(rfr_req), + .I2(init_req), + .I3(\u5/lookup_ready2 ), + .I4(lmr_req), + .O(lmr_ack_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hFE)) + lmr_ack_i_3 + (.I0(\u5/state [6]), + .I1(\u5/state [4]), + .I2(\u5/state [5]), + .O(lmr_ack_i_3_n_0)); + LUT2 #( + .INIT(4'hE)) + lmr_req_i_1 + (.I0(\u0/u1/lmr_req_reg_n_0 ), + .I1(\u0/u0/lmr_req_reg_n_0 ), + .O(\u0/lmr_req00_out )); + LUT6 #( + .INIT(64'hBBBB8BBB88888888)) + lmr_req_i_1__0 + (.I0(\u0/u1/inited_reg_n_0 ), + .I1(lmr_req_i_2__0_n_0), + .I2(spec_req_cs[1]), + .I3(\u0/lmr_ack_r ), + .I4(lmr_ack), + .I5(\u0/u1/lmr_req_reg_n_0 ), + .O(lmr_req_i_1__0_n_0)); + LUT6 #( + .INIT(64'hBB8BBBBB88888888)) + lmr_req_i_1__1 + (.I0(\u0/inited ), + .I1(lmr_req_i_2_n_0), + .I2(\u0/lmr_ack_r ), + .I3(lmr_ack), + .I4(spec_req_cs[0]), + .I5(\u0/u0/lmr_req_reg_n_0 ), + .O(lmr_req_i_1__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT4 #( + .INIT(16'h0002)) + lmr_req_i_2 + (.I0(\u0/lmr_req_we ), + .I1(\u0/u0/csc_reg_n_0_[1] ), + .I2(\u0/u0/csc_reg_n_0_[3] ), + .I3(\u0/u0/csc_reg_n_0_[2] ), + .O(lmr_req_i_2_n_0)); + LUT4 #( + .INIT(16'h0002)) + lmr_req_i_2__0 + (.I0(\u0/u1/lmr_req_we_reg_n_0 ), + .I1(\u0/u1/csc_reg_n_0_[1] ), + .I2(\u0/u1/csc_reg_n_0_[3] ), + .I3(\u0/u1/csc_reg_n_0_[2] ), + .O(lmr_req_i_2__0_n_0)); + LUT6 #( + .INIT(64'h0000000800000000)) + lmr_req_we_i_1 + (.I0(\u0/p_0_in1_in ), + .I1(\u0/rf_we ), + .I2(\u0/p_0_in [0]), + .I3(\u0/p_0_in [2]), + .I4(\u0/p_0_in [3]), + .I5(\u0/p_0_in [1]), + .O(\u0/tms0 )); + LUT6 #( + .INIT(64'h0000008000000000)) + lmr_req_we_i_1__0 + (.I0(\u0/p_0_in1_in ), + .I1(\u0/rf_we ), + .I2(\u0/p_0_in [0]), + .I3(\u0/p_0_in [2]), + .I4(\u0/p_0_in [3]), + .I5(\u0/p_0_in [1]), + .O(lmr_req_we_i_1__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT3 #( + .INIT(8'h80)) + lookup_ready1_i_1 + (.I0(cs_le), + .I1(wb_cyc_i), + .I2(wb_stb_i), + .O(\u5/lookup_ready10 )); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT3 #( + .INIT(8'h80)) + lookup_ready2_i_1 + (.I0(\u5/lookup_ready1 ), + .I1(wb_cyc_i), + .I2(wb_stb_i), + .O(\u5/lookup_ready20 )); + LUT5 #( + .INIT(32'h8D8DFF00)) + \mc_addr[0]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[0]), + .I2(\mc_addr[0]_i_2_n_0 ), + .I3(\mc_addr[0]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[0])); + LUT5 #( + .INIT(32'h8B888BBB)) + \mc_addr[0]_i_2 + (.I0(\burst_cnt[3]_i_2_n_0 ), + .I1(\mc_addr[12]_i_4_n_0 ), + .I2(row_adr[0]), + .I3(\mc_addr[12]_i_5_n_0 ), + .I4(col_adr[0]), + .O(\mc_addr[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[0]_i_3 + (.I0(sram_addr[0]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[2]), + .O(\mc_addr[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFEFEBABABAFEBAFE)) + \mc_addr[10]_i_1 + (.I0(rfr_ack), + .I1(\mc_addr[23]_i_4_n_0 ), + .I2(\mc_addr[10]_i_2_n_0 ), + .I3(\mc_addr[10]_i_3_n_0 ), + .I4(acs_addr[10]), + .I5(\mc_addr[23]_i_3_n_0 ), + .O(mc_addr_d[10])); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[10]_i_2 + (.I0(sram_addr[10]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[12]), + .O(\mc_addr[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'h47774744)) + \mc_addr[10]_i_3 + (.I0(\mc_addr[10]_i_4_n_0 ), + .I1(\mc_addr[12]_i_4_n_0 ), + .I2(row_adr[10]), + .I3(\mc_addr[12]_i_5_n_0 ), + .I4(cmd_a10_r_i_2_n_0), + .O(\mc_addr[10]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[10]_i_4 + (.I0(\u0/tms_reg_n_0_[10] ), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_tms[10]), + .O(\mc_addr[10]_i_4_n_0 )); + LUT5 #( + .INIT(32'h0000D5F7)) + \mc_addr[11]_i_1 + (.I0(\mc_addr[23]_i_4_n_0 ), + .I1(\mc_addr[23]_i_3_n_0 ), + .I2(acs_addr[11]), + .I3(\mc_addr[11]_i_2_n_0 ), + .I4(\mc_addr[11]_i_3_n_0 ), + .O(mc_addr_d[11])); + LUT6 #( + .INIT(64'h1D001DFF1DFF1DFF)) + \mc_addr[11]_i_2 + (.I0(sp_tms[11]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(\u0/tms_reg_n_0_[11] ), + .I3(\mc_addr[12]_i_4_n_0 ), + .I4(row_adr[11]), + .I5(\mc_addr[12]_i_5_n_0 ), + .O(\mc_addr[11]_i_2_n_0 )); + LUT4 #( + .INIT(16'h0053)) + \mc_addr[11]_i_3 + (.I0(sram_addr[11]), + .I1(wb_addr_i[13]), + .I2(\mc_addr[23]_i_2_n_0 ), + .I3(\mc_addr[23]_i_4_n_0 ), + .O(\mc_addr[11]_i_3_n_0 )); + LUT5 #( + .INIT(32'h0000D5F7)) + \mc_addr[12]_i_1 + (.I0(\mc_addr[23]_i_4_n_0 ), + .I1(\mc_addr[23]_i_3_n_0 ), + .I2(acs_addr[12]), + .I3(\mc_addr[12]_i_2_n_0 ), + .I4(\mc_addr[12]_i_3_n_0 ), + .O(mc_addr_d[12])); + LUT6 #( + .INIT(64'h1D001DFF1DFF1DFF)) + \mc_addr[12]_i_2 + (.I0(sp_tms[12]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(\u0/tms_reg_n_0_[12] ), + .I3(\mc_addr[12]_i_4_n_0 ), + .I4(row_adr[12]), + .I5(\mc_addr[12]_i_5_n_0 ), + .O(\mc_addr[12]_i_2_n_0 )); + LUT4 #( + .INIT(16'h0053)) + \mc_addr[12]_i_3 + (.I0(sram_addr[12]), + .I1(wb_addr_i[14]), + .I2(\mc_addr[23]_i_2_n_0 ), + .I3(\mc_addr[23]_i_4_n_0 ), + .O(\mc_addr[12]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT4 #( + .INIT(16'h0151)) + \mc_addr[12]_i_4 + (.I0(\timer2[6]_i_4_n_0 ), + .I1(\u5/cmd [1]), + .I2(wr_cycle), + .I3(\u5/cmd_del [1]), + .O(\mc_addr[12]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0000340000000000)) + \mc_addr[12]_i_5 + (.I0(\u5/wb_wait_r ), + .I1(\u5/state [0]), + .I2(\u5/state [1]), + .I3(rfr_ack_r_i_7_n_0), + .I4(\b3_last_row[12]_i_4_n_0 ), + .I5(\u5/state [4]), + .O(\mc_addr[12]_i_5_n_0 )); + LUT6 #( + .INIT(64'hCDC8CDCDCDC8C8C8)) + \mc_addr[13]_i_1 + (.I0(\mc_addr[14]_i_2_n_0 ), + .I1(\mc_addr[13]_i_2_n_0 ), + .I2(\mc_addr[14]_i_4_n_0 ), + .I3(acs_addr[13]), + .I4(\mc_addr[23]_i_3_n_0 ), + .I5(bank_adr[0]), + .O(mc_addr_d[13])); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[13]_i_2 + (.I0(sram_addr[13]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[15]), + .O(\mc_addr[13]_i_2_n_0 )); + LUT6 #( + .INIT(64'hCDC8CDCDCDC8C8C8)) + \mc_addr[14]_i_1 + (.I0(\mc_addr[14]_i_2_n_0 ), + .I1(\mc_addr[14]_i_3_n_0 ), + .I2(\mc_addr[14]_i_4_n_0 ), + .I3(acs_addr[14]), + .I4(\mc_addr[23]_i_3_n_0 ), + .I5(bank_adr[1]), + .O(mc_addr_d[14])); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[14]_i_2 + (.I0(csc[3]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_csc[3]), + .O(\mc_addr[14]_i_2_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \mc_addr[14]_i_3 + (.I0(sram_addr[14]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[16]), + .O(\mc_addr[14]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[14]_i_4 + (.I0(csc[1]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_csc[1]), + .O(\mc_addr[14]_i_4_n_0 )); + LUT6 #( + .INIT(64'h8F808F8F8F808080)) + \mc_addr[15]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[15]), + .I2(\mc_addr[23]_i_4_n_0 ), + .I3(sram_addr[15]), + .I4(\mc_addr[23]_i_2_n_0 ), + .I5(wb_addr_i[17]), + .O(mc_addr_d[15])); + LUT6 #( + .INIT(64'h8F808F8F8F808080)) + \mc_addr[16]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[16]), + .I2(\mc_addr[23]_i_4_n_0 ), + .I3(sram_addr[16]), + .I4(\mc_addr[23]_i_2_n_0 ), + .I5(wb_addr_i[18]), + .O(mc_addr_d[16])); + LUT6 #( + .INIT(64'h8F808F8F8F808080)) + \mc_addr[17]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[17]), + .I2(\mc_addr[23]_i_4_n_0 ), + .I3(sram_addr[17]), + .I4(\mc_addr[23]_i_2_n_0 ), + .I5(wb_addr_i[19]), + .O(mc_addr_d[17])); + LUT6 #( + .INIT(64'h8F808F8F8F808080)) + \mc_addr[18]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[18]), + .I2(\mc_addr[23]_i_4_n_0 ), + .I3(sram_addr[18]), + .I4(\mc_addr[23]_i_2_n_0 ), + .I5(wb_addr_i[20]), + .O(mc_addr_d[18])); + LUT6 #( + .INIT(64'h8F808F8F8F808080)) + \mc_addr[19]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[19]), + .I2(\mc_addr[23]_i_4_n_0 ), + .I3(sram_addr[19]), + .I4(\mc_addr[23]_i_2_n_0 ), + .I5(wb_addr_i[21]), + .O(mc_addr_d[19])); + LUT5 #( + .INIT(32'h8D8DFF00)) + \mc_addr[1]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[1]), + .I2(\mc_addr[1]_i_2_n_0 ), + .I3(\mc_addr[1]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[1])); + LUT5 #( + .INIT(32'h5555303F)) + \mc_addr[1]_i_2 + (.I0(\burst_cnt[3]_i_3_n_0 ), + .I1(row_adr[1]), + .I2(\mc_addr[12]_i_5_n_0 ), + .I3(col_adr[1]), + .I4(\mc_addr[12]_i_4_n_0 ), + .O(\mc_addr[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[1]_i_3 + (.I0(sram_addr[1]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[3]), + .O(\mc_addr[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h8F808F8F8F808080)) + \mc_addr[20]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[20]), + .I2(\mc_addr[23]_i_4_n_0 ), + .I3(sram_addr[20]), + .I4(\mc_addr[23]_i_2_n_0 ), + .I5(wb_addr_i[22]), + .O(mc_addr_d[20])); + LUT6 #( + .INIT(64'h8F808F8F8F808080)) + \mc_addr[21]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[21]), + .I2(\mc_addr[23]_i_4_n_0 ), + .I3(sram_addr[21]), + .I4(\mc_addr[23]_i_2_n_0 ), + .I5(wb_addr_i[23]), + .O(mc_addr_d[21])); + LUT6 #( + .INIT(64'hFF00B8B80000B8B8)) + \mc_addr[22]_i_1 + (.I0(sram_addr[22]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[24]), + .I3(\mc_addr[23]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .I5(acs_addr[22]), + .O(mc_addr_d[22])); + LUT6 #( + .INIT(64'hFF000000B8B8B8B8)) + \mc_addr[23]_i_1 + (.I0(sram_addr[23]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[25]), + .I3(acs_addr[23]), + .I4(\mc_addr[23]_i_3_n_0 ), + .I5(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[23])); + LUT6 #( + .INIT(64'h0000000002A20000)) + \mc_addr[23]_i_2 + (.I0(wr_hold), + .I1(sp_csc[3]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(csc[3]), + .I4(\mc_addr[14]_i_4_n_0 ), + .I5(\mc_addr[23]_i_3_n_0 ), + .O(\mc_addr[23]_i_2_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \mc_addr[23]_i_3 + (.I0(csc[2]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_csc[2]), + .O(\mc_addr[23]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT5 #( + .INIT(32'h00053305)) + \mc_addr[23]_i_4 + (.I0(sp_csc[1]), + .I1(csc[1]), + .I2(sp_csc[3]), + .I3(\timer2[6]_i_4_n_0 ), + .I4(csc[3]), + .O(\mc_addr[23]_i_4_n_0 )); + LUT5 #( + .INIT(32'h8D8DFF00)) + \mc_addr[2]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[2]), + .I2(\mc_addr[2]_i_2_n_0 ), + .I3(\mc_addr[2]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[2])); + LUT5 #( + .INIT(32'h00FF4747)) + \mc_addr[2]_i_2 + (.I0(row_adr[2]), + .I1(\mc_addr[12]_i_5_n_0 ), + .I2(col_adr[2]), + .I3(\mc_addr[2]_i_4_n_0 ), + .I4(\mc_addr[12]_i_4_n_0 ), + .O(\mc_addr[2]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[2]_i_3 + (.I0(sram_addr[2]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[4]), + .O(\mc_addr[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hEEEFEEEE22202222)) + \mc_addr[2]_i_4 + (.I0(\u0/tms_reg_n_0_[2] ), + .I1(lmr_ack), + .I2(\u5/state [6]), + .I3(\FSM_sequential_state[5]_i_4_n_0 ), + .I4(\burst_cnt[3]_i_4_n_0 ), + .I5(sp_tms[2]), + .O(\mc_addr[2]_i_4_n_0 )); + LUT5 #( + .INIT(32'hD8D8FF00)) + \mc_addr[3]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[3]), + .I2(\mc_addr[3]_i_2_n_0 ), + .I3(\mc_addr[3]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[3])); + LUT5 #( + .INIT(32'hB8BBB888)) + \mc_addr[3]_i_2 + (.I0(\mc_addr[3]_i_4_n_0 ), + .I1(\mc_addr[12]_i_4_n_0 ), + .I2(row_adr[3]), + .I3(\mc_addr[12]_i_5_n_0 ), + .I4(col_adr[3]), + .O(\mc_addr[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[3]_i_3 + (.I0(sram_addr[3]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[5]), + .O(\mc_addr[3]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[3]_i_4 + (.I0(\u0/tms_reg_n_0_[3] ), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_tms[3]), + .O(\mc_addr[3]_i_4_n_0 )); + LUT5 #( + .INIT(32'h8D8DFF00)) + \mc_addr[4]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[4]), + .I2(\mc_addr[4]_i_2_n_0 ), + .I3(\mc_addr[4]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[4])); + LUT5 #( + .INIT(32'h47444777)) + \mc_addr[4]_i_2 + (.I0(\mc_addr[4]_i_4_n_0 ), + .I1(\mc_addr[12]_i_4_n_0 ), + .I2(row_adr[4]), + .I3(\mc_addr[12]_i_5_n_0 ), + .I4(col_adr[4]), + .O(\mc_addr[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[4]_i_3 + (.I0(sram_addr[4]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[6]), + .O(\mc_addr[4]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[4]_i_4 + (.I0(\u0/tms_reg_n_0_[4] ), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_tms[4]), + .O(\mc_addr[4]_i_4_n_0 )); + LUT5 #( + .INIT(32'hD8D8FF00)) + \mc_addr[5]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[5]), + .I2(\mc_addr[5]_i_2_n_0 ), + .I3(\mc_addr[5]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[5])); + LUT5 #( + .INIT(32'hB8BBB888)) + \mc_addr[5]_i_2 + (.I0(\mc_addr[5]_i_4_n_0 ), + .I1(\mc_addr[12]_i_4_n_0 ), + .I2(row_adr[5]), + .I3(\mc_addr[12]_i_5_n_0 ), + .I4(col_adr[5]), + .O(\mc_addr[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[5]_i_3 + (.I0(sram_addr[5]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[7]), + .O(\mc_addr[5]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[5]_i_4 + (.I0(\u0/tms_reg_n_0_[5] ), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_tms[5]), + .O(\mc_addr[5]_i_4_n_0 )); + LUT5 #( + .INIT(32'hD8D8FF00)) + \mc_addr[6]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[6]), + .I2(\mc_addr[6]_i_2_n_0 ), + .I3(\mc_addr[6]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[6])); + LUT5 #( + .INIT(32'hB8BBB888)) + \mc_addr[6]_i_2 + (.I0(\mc_addr[6]_i_4_n_0 ), + .I1(\mc_addr[12]_i_4_n_0 ), + .I2(row_adr[6]), + .I3(\mc_addr[12]_i_5_n_0 ), + .I4(col_adr[6]), + .O(\mc_addr[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[6]_i_3 + (.I0(sram_addr[6]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[8]), + .O(\mc_addr[6]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[6]_i_4 + (.I0(\u0/tms_reg_n_0_[6] ), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_tms[6]), + .O(\mc_addr[6]_i_4_n_0 )); + LUT5 #( + .INIT(32'h8D8DFF00)) + \mc_addr[7]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[7]), + .I2(\mc_addr[7]_i_2_n_0 ), + .I3(\mc_addr[7]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[7])); + LUT5 #( + .INIT(32'h47444777)) + \mc_addr[7]_i_2 + (.I0(\mc_addr[7]_i_4_n_0 ), + .I1(\mc_addr[12]_i_4_n_0 ), + .I2(row_adr[7]), + .I3(\mc_addr[12]_i_5_n_0 ), + .I4(col_adr[7]), + .O(\mc_addr[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[7]_i_3 + (.I0(sram_addr[7]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[9]), + .O(\mc_addr[7]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[7]_i_4 + (.I0(\u0/tms_reg_n_0_[7] ), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_tms[7]), + .O(\mc_addr[7]_i_4_n_0 )); + LUT5 #( + .INIT(32'hD8D8FF00)) + \mc_addr[8]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[8]), + .I2(\mc_addr[8]_i_2_n_0 ), + .I3(\mc_addr[8]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[8])); + LUT5 #( + .INIT(32'hB8BBB888)) + \mc_addr[8]_i_2 + (.I0(\mc_addr[8]_i_4_n_0 ), + .I1(\mc_addr[12]_i_4_n_0 ), + .I2(row_adr[8]), + .I3(\mc_addr[12]_i_5_n_0 ), + .I4(col_adr[8]), + .O(\mc_addr[8]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[8]_i_3 + (.I0(sram_addr[8]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[10]), + .O(\mc_addr[8]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[8]_i_4 + (.I0(\u0/tms_reg_n_0_[8] ), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_tms[8]), + .O(\mc_addr[8]_i_4_n_0 )); + LUT5 #( + .INIT(32'hD8D8FF00)) + \mc_addr[9]_i_1 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(acs_addr[9]), + .I2(\mc_addr[9]_i_2_n_0 ), + .I3(\mc_addr[9]_i_3_n_0 ), + .I4(\mc_addr[23]_i_4_n_0 ), + .O(mc_addr_d[9])); + LUT5 #( + .INIT(32'hB8BBB888)) + \mc_addr[9]_i_2 + (.I0(\mc_addr[9]_i_4_n_0 ), + .I1(\mc_addr[12]_i_4_n_0 ), + .I2(row_adr[9]), + .I3(\mc_addr[12]_i_5_n_0 ), + .I4(col_adr[9]), + .O(\mc_addr[9]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'hB8)) + \mc_addr[9]_i_3 + (.I0(sram_addr[9]), + .I1(\mc_addr[23]_i_2_n_0 ), + .I2(wb_addr_i[11]), + .O(\mc_addr[9]_i_3_n_0 )); + LUT6 #( + .INIT(64'hEEEFEEEE22202222)) + \mc_addr[9]_i_4 + (.I0(\u0/tms_reg_n_0_[9] ), + .I1(lmr_ack), + .I2(\u5/state [6]), + .I3(\FSM_sequential_state[5]_i_4_n_0 ), + .I4(\burst_cnt[3]_i_4_n_0 ), + .I5(sp_tms[9]), + .O(\mc_addr[9]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'hFFFF1555)) + mc_adsc__i_1 + (.I0(mc_adsc__i_2_n_0), + .I1(\u5/state [4]), + .I2(\u5/state [1]), + .I3(mc_adsc__i_3_n_0), + .I4(mc_adsc__i_4_n_0), + .O(mc_adsc__i_1_n_0)); + LUT6 #( + .INIT(64'h00C80000000C0030)) + mc_adsc__i_2 + (.I0(no_wb_cycle_i_2_n_0), + .I1(\u5/state [4]), + .I2(\u5/state [0]), + .I3(\u5/state [1]), + .I4(\u5/state [3]), + .I5(\u5/state [2]), + .O(mc_adsc__i_2_n_0)); + LUT6 #( + .INIT(64'h00000EFFCC000000)) + mc_adsc__i_3 + (.I0(wb_stb_i), + .I1(no_wb_cycle_i_2_n_0), + .I2(wb_write_go), + .I3(\u5/state [0]), + .I4(\u5/state [3]), + .I5(\u5/state [2]), + .O(mc_adsc__i_3_n_0)); + LUT6 #( + .INIT(64'hFF00FFFFFFFFFFDF)) + mc_adsc__i_4 + (.I0(oe__i_3_n_0), + .I1(\mc_addr[23]_i_3_n_0 ), + .I2(mc_adsc__i_5_n_0), + .I3(\u5/state [6]), + .I4(\u5/state [5]), + .I5(\u5/state [4]), + .O(mc_adsc__i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT4 #( + .INIT(16'h00E2)) + mc_adsc__i_5 + (.I0(sp_csc[1]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(csc[1]), + .I3(wb_write_go), + .O(mc_adsc__i_5_n_0)); + LUT6 #( + .INIT(64'hD7FFFFFFD7FFF7FF)) + mc_adv__i_1 + (.I0(mc_bg_i_3_n_0), + .I1(\u5/state [0]), + .I2(\u5/state [1]), + .I3(mc_adv__i_2_n_0), + .I4(mc_adv__i_3_n_0), + .I5(\u5/tmr2_done ), + .O(mc_adv__i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT2 #( + .INIT(4'h2)) + mc_adv__i_2 + (.I0(\u5/state [3]), + .I1(\u5/state [2]), + .O(mc_adv__i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT3 #( + .INIT(8'hBA)) + mc_adv__i_3 + (.I0(wb_stb_i), + .I1(wb_write_go), + .I2(no_wb_cycle_i_2_n_0), + .O(mc_adv__i_3_n_0)); + LUT6 #( + .INIT(64'h00D0C00000000000)) + mc_adv_r1_i_1 + (.I0(\u5/tmr2_done ), + .I1(mc_adv__i_3_n_0), + .I2(mc_adv__i_2_n_0), + .I3(\u5/state [1]), + .I4(\u5/state [0]), + .I5(mc_bg_i_3_n_0), + .O(mc_adv_d)); + LUT6 #( + .INIT(64'h00000000EE00000E)) + mc_bg_i_1 + (.I0(mc_bg_i_2_n_0), + .I1(mc_bg_i_3_n_0), + .I2(\u5/state [0]), + .I3(\u5/state [1]), + .I4(\u5/state [2]), + .I5(mc_bg_i_4_n_0), + .O(mc_bg_d)); + LUT6 #( + .INIT(64'h0000000000020000)) + mc_bg_i_2 + (.I0(\u5/p_65_in ), + .I1(\FSM_sequential_state[5]_i_4_n_0 ), + .I2(mc_bg_i_5_n_0), + .I3(\u5/susp_req_r ), + .I4(\u5/state [6]), + .I5(lmr_req), + .O(mc_bg_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'h08)) + mc_bg_i_3 + (.I0(\u5/state [4]), + .I1(\u5/state [5]), + .I2(\u5/state [6]), + .O(mc_bg_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT3 #( + .INIT(8'h7E)) + mc_bg_i_4 + (.I0(\u5/state [4]), + .I1(\u5/state [2]), + .I2(\u5/state [3]), + .O(mc_bg_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT2 #( + .INIT(4'hE)) + mc_bg_i_5 + (.I0(rfr_req), + .I1(init_req), + .O(mc_bg_i_5_n_0)); + LUT6 #( + .INIT(64'hABBBBBBBAAAAAAAA)) + mc_c_oe_i_1 + (.I0(mc_c_oe_i_2_n_0), + .I1(\u5/state [6]), + .I2(\u5/state [4]), + .I3(\u5/state [2]), + .I4(\u5/state [3]), + .I5(mc_c_oe_i_3_n_0), + .O(\u5/mc_c_oe_d )); + LUT6 #( + .INIT(64'h0000000C00010F0C)) + mc_c_oe_i_2 + (.I0(\u5/state [4]), + .I1(\u5/state [3]), + .I2(mc_c_oe_i_4_n_0), + .I3(\u5/state [1]), + .I4(\u5/state [6]), + .I5(\u5/state [5]), + .O(mc_c_oe_i_2_n_0)); + LUT6 #( + .INIT(64'hFFDFFFFFFFFFFFFF)) + mc_c_oe_i_3 + (.I0(mc_br_r), + .I1(\u5/cmd_asserted2 ), + .I2(\FSM_sequential_state[5]_i_9_n_0 ), + .I3(\FSM_sequential_state[6]_i_21_n_0 ), + .I4(\FSM_sequential_state[5]_i_8_n_0 ), + .I5(mc_c_oe_i_5_n_0), + .O(mc_c_oe_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT4 #( + .INIT(16'h01F1)) + mc_c_oe_i_4 + (.I0(mc_br_r), + .I1(\u5/state [0]), + .I2(\u5/state [2]), + .I3(\u5/state [3]), + .O(mc_c_oe_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT2 #( + .INIT(4'h1)) + mc_c_oe_i_5 + (.I0(\u5/state [2]), + .I1(\u5/state [5]), + .O(mc_c_oe_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT3 #( + .INIT(8'hB8)) + mc_cas__i_1 + (.I0(\u5/cmd_del [1]), + .I1(wr_cycle), + .I2(\u5/cmd [1]), + .O(cas_)); + LUT6 #( + .INIT(64'h77772272FFFFFFFF)) + \mc_cs_[0]_i_1 + (.I0(wr_cycle), + .I1(\u5/cmd_del [3]), + .I2(\mc_cs_[1]_i_3_n_0 ), + .I3(\mc_cs_[1]_i_4_n_0 ), + .I4(\u5/state [6]), + .I5(\mc_cs_[0]_i_2_n_0 ), + .O(\mc_cs_[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hABA8ABABABA8A8A8)) + \mc_cs_[0]_i_2 + (.I0(rfr_en_i_2_n_0), + .I1(rfr_ack), + .I2(susp_sel), + .I3(cs[0]), + .I4(\timer2[6]_i_4_n_0 ), + .I5(spec_req_cs[0]), + .O(\mc_cs_[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBFBFBFBFAEAEBFAE)) + \mc_cs_[1]_i_1 + (.I0(\mc_cs_[1]_i_2_n_0 ), + .I1(wr_cycle), + .I2(\u5/cmd_del [3]), + .I3(\mc_cs_[1]_i_3_n_0 ), + .I4(\mc_cs_[1]_i_4_n_0 ), + .I5(\u5/state [6]), + .O(\mc_cs_[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00FF00FF00FF1D1D)) + \mc_cs_[1]_i_2 + (.I0(spec_req_cs[1]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(cs[1]), + .I3(init_req_i_2__0_n_0), + .I4(rfr_ack), + .I5(susp_sel), + .O(\mc_cs_[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFF75FFFFFF757777)) + \mc_cs_[1]_i_3 + (.I0(\FSM_sequential_state[0]_i_3_n_0 ), + .I1(\u5/state [3]), + .I2(\u5/tmr2_done ), + .I3(\u5/state [4]), + .I4(\u5/state [1]), + .I5(\cmd_r[0]_i_3_n_0 ), + .O(\mc_cs_[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF0000FF01)) + \mc_cs_[1]_i_4 + (.I0(\u5/state [2]), + .I1(\u5/state [4]), + .I2(\mc_cs_[1]_i_5_n_0 ), + .I3(cmd_asserted_i_3_n_0), + .I4(\u5/state [5]), + .I5(cmd_asserted_i_4_n_0), + .O(\mc_cs_[1]_i_4_n_0 )); + LUT6 #( + .INIT(64'h5545554555555545)) + \mc_cs_[1]_i_5 + (.I0(\b3_last_row[12]_i_3_n_0 ), + .I1(cmd_asserted_i_5_n_0), + .I2(\FSM_sequential_state[5]_i_8_n_0 ), + .I3(\FSM_sequential_state[5]_i_9_n_0 ), + .I4(wb_cyc_i), + .I5(wb_stb_i), + .O(\mc_cs_[1]_i_5_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \mc_data_o[31]_i_1 + (.I0(csc[2]), + .I1(csc[3]), + .I2(csc[1]), + .I3(mem_ack_r), + .O(\u3/mc_data_o0 )); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'h08)) + mc_data_oe_i_1 + (.I0(data_oe), + .I1(mc_c_oe_d), + .I2(susp_sel), + .O(\u7/mc_data_oe0 )); + LUT5 #( + .INIT(32'h96696996)) + \mc_dp_o[0]_i_1 + (.I0(wb_data_i[4]), + .I1(wb_data_i[5]), + .I2(wb_data_i[0]), + .I3(wb_data_i[1]), + .I4(\mc_dp_o[0]_i_2_n_0 ), + .O(\mc_dp_o[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'h6996)) + \mc_dp_o[0]_i_2 + (.I0(wb_data_i[3]), + .I1(wb_data_i[2]), + .I2(wb_data_i[6]), + .I3(wb_data_i[7]), + .O(\mc_dp_o[0]_i_2_n_0 )); + LUT5 #( + .INIT(32'h96696996)) + \mc_dp_o[1]_i_1 + (.I0(wb_data_i[13]), + .I1(wb_data_i[12]), + .I2(wb_data_i[11]), + .I3(wb_data_i[10]), + .I4(\mc_dp_o[1]_i_2_n_0 ), + .O(\mc_dp_o[1]_i_1_n_0 )); + LUT4 #( + .INIT(16'h6996)) + \mc_dp_o[1]_i_2 + (.I0(wb_data_i[14]), + .I1(wb_data_i[15]), + .I2(wb_data_i[8]), + .I3(wb_data_i[9]), + .O(\mc_dp_o[1]_i_2_n_0 )); + LUT5 #( + .INIT(32'h96696996)) + \mc_dp_o[2]_i_1 + (.I0(wb_data_i[21]), + .I1(wb_data_i[20]), + .I2(wb_data_i[19]), + .I3(wb_data_i[18]), + .I4(\mc_dp_o[2]_i_2_n_0 ), + .O(\mc_dp_o[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'h6996)) + \mc_dp_o[2]_i_2 + (.I0(wb_data_i[22]), + .I1(wb_data_i[23]), + .I2(wb_data_i[16]), + .I3(wb_data_i[17]), + .O(\mc_dp_o[2]_i_2_n_0 )); + LUT5 #( + .INIT(32'h96696996)) + \mc_dp_o[3]_i_1 + (.I0(wb_data_i[29]), + .I1(wb_data_i[28]), + .I2(wb_data_i[27]), + .I3(wb_data_i[26]), + .I4(\mc_dp_o[3]_i_2_n_0 ), + .O(mc_dp_o0)); + LUT4 #( + .INIT(16'h6996)) + \mc_dp_o[3]_i_2 + (.I0(wb_data_i[30]), + .I1(wb_data_i[31]), + .I2(wb_data_i[24]), + .I3(wb_data_i[25]), + .O(\mc_dp_o[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT4 #( + .INIT(16'h0FBB)) + \mc_dqm[0]_i_1 + (.I0(wr_cycle), + .I1(wb_cycle), + .I2(mc_dqm_r2[0]), + .I3(data_oe), + .O(\mc_dqm[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT4 #( + .INIT(16'h0FBB)) + \mc_dqm[1]_i_1 + (.I0(wr_cycle), + .I1(wb_cycle), + .I2(mc_dqm_r2[1]), + .I3(data_oe), + .O(\mc_dqm[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT4 #( + .INIT(16'h0FBB)) + \mc_dqm[2]_i_1 + (.I0(wr_cycle), + .I1(wb_cycle), + .I2(mc_dqm_r2[2]), + .I3(data_oe), + .O(\mc_dqm[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT4 #( + .INIT(16'h0FBB)) + \mc_dqm[3]_i_1 + (.I0(wr_cycle), + .I1(wb_cycle), + .I2(mc_dqm_r2[3]), + .I3(data_oe), + .O(\mc_dqm[3]_i_1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \mc_dqm_r[3]_i_1 + (.I0(wb_cyc_i), + .I1(wb_stb_i), + .O(\u6/wr_hold0 )); + LUT1 #( + .INIT(2'h1)) + mc_le_i_1 + (.I0(\u5/mc_le ), + .O(mc_le_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + mc_oe__i_1 + (.I0(susp_sel), + .I1(oe_), + .O(\u7/mc_oe_0 )); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT3 #( + .INIT(8'hB8)) + mc_ras__i_1 + (.I0(\u5/cmd_del [2]), + .I1(wr_cycle), + .I2(\u5/cmd [2]), + .O(ras_)); + LUT2 #( + .INIT(4'h1)) + mc_rp_i_1 + (.I0(fs), + .I1(suspended_o), + .O(\u7/mc_rp0 )); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT3 #( + .INIT(8'hB8)) + mc_we__i_1 + (.I0(\u5/cmd_del [0]), + .I1(wr_cycle), + .I2(\u5/cmd [0]), + .O(we_)); + LUT6 #( + .INIT(64'h5554555555545554)) + mem_ack_r_i_1 + (.I0(\u5/p_65_in ), + .I1(mem_ack_r_i_2_n_0), + .I2(mem_ack_r_i_3_n_0), + .I3(mem_ack_r_i_4_n_0), + .I4(mem_ack_r_i_5_n_0), + .I5(mem_ack_r_i_6_n_0), + .O(mem_ack)); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT2 #( + .INIT(4'h1)) + mem_ack_r_i_10 + (.I0(\u5/state [0]), + .I1(\u5/state [4]), + .O(mem_ack_r_i_10_n_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'hFF4FFFFF)) + mem_ack_r_i_11 + (.I0(wb_stb_i), + .I1(wb_cyc_i), + .I2(wb_write_go), + .I3(\u5/mem_ack_r ), + .I4(\u5/cmd_asserted ), + .O(mem_ack_r_i_11_n_0)); + LUT6 #( + .INIT(64'h0000000020000000)) + mem_ack_r_i_12 + (.I0(\mc_addr[14]_i_4_n_0 ), + .I1(data_oe_r_i_7_n_0), + .I2(\FSM_sequential_state[1]_i_13_n_0 ), + .I3(\FSM_sequential_state[3]_i_9_n_0 ), + .I4(\FSM_sequential_state[5]_i_8_n_0 ), + .I5(\mc_addr[23]_i_3_n_0 ), + .O(mem_ack_r_i_12_n_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'hBBFB)) + mem_ack_r_i_13 + (.I0(\u5/mem_ack_r ), + .I1(wb_write_go), + .I2(wb_cyc_i), + .I3(wb_stb_i), + .O(mem_ack_r_i_13_n_0)); + LUT6 #( + .INIT(64'h00FF40FFFFFF00FF)) + mem_ack_r_i_14 + (.I0(\u5/mem_ack_r ), + .I1(wb_write_go), + .I2(\u5/tmr_done ), + .I3(\u5/state [2]), + .I4(\u5/state [5]), + .I5(\u5/state [1]), + .O(mem_ack_r_i_14_n_0)); + LUT5 #( + .INIT(32'h00000004)) + mem_ack_r_i_2 + (.I0(\u5/mem_ack_r ), + .I1(wb_stb_i), + .I2(wb_we_i), + .I3(mem_ack_r_i_7_n_0), + .I4(no_wb_cycle_i_2_n_0), + .O(mem_ack_r_i_2_n_0)); + LUT6 #( + .INIT(64'h888A888A888A8888)) + mem_ack_r_i_3 + (.I0(cs_le_i_12_n_0), + .I1(mem_ack_r_i_8_n_0), + .I2(mem_ack_r_i_9_n_0), + .I3(\FSM_sequential_state[2]_i_15_n_0 ), + .I4(\u5/tmr_done ), + .I5(\u5/state [2]), + .O(mem_ack_r_i_3_n_0)); + LUT6 #( + .INIT(64'h0080000000000000)) + mem_ack_r_i_4 + (.I0(\u5/state [3]), + .I1(\u5/state [2]), + .I2(\u5/state [1]), + .I3(\u5/state [6]), + .I4(\u5/state [5]), + .I5(mem_ack_r_i_10_n_0), + .O(mem_ack_r_i_4_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF700)) + mem_ack_r_i_5 + (.I0(wb_cycle), + .I1(cke__i_5_n_0), + .I2(mem_ack_r_i_11_n_0), + .I3(\u5/state [4]), + .I4(\FSM_sequential_state[2]_i_4_n_0 ), + .I5(\u5/state [3]), + .O(mem_ack_r_i_5_n_0)); + LUT6 #( + .INIT(64'h0820FFFF08200820)) + mem_ack_r_i_6 + (.I0(\u5/state [1]), + .I1(\u5/state [2]), + .I2(\u5/state [5]), + .I3(\u5/state [4]), + .I4(\FSM_sequential_state[5]_i_9_n_0 ), + .I5(mem_ack_r_i_12_n_0), + .O(mem_ack_r_i_6_n_0)); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT4 #( + .INIT(16'h0001)) + mem_ack_r_i_7 + (.I0(\u5/ack_cnt_reg [0]), + .I1(\u5/ack_cnt_reg [1]), + .I2(\u5/ack_cnt_reg [3]), + .I3(\u5/ack_cnt_reg [2]), + .O(mem_ack_r_i_7_n_0)); + LUT6 #( + .INIT(64'h0000000000200000)) + mem_ack_r_i_8 + (.I0(cke__i_5_n_0), + .I1(\u5/state [5]), + .I2(\burst_cnt[10]_i_4_n_0 ), + .I3(\FSM_sequential_state[6]_i_29_n_0 ), + .I4(wr_cycle), + .I5(mem_ack_r_i_13_n_0), + .O(mem_ack_r_i_8_n_0)); + LUT6 #( + .INIT(64'h0F0F0F0F0F0F0700)) + mem_ack_r_i_9 + (.I0(\u5/state [5]), + .I1(\u5/cmd_asserted ), + .I2(mem_ack_r_i_14_n_0), + .I3(\u5/state [1]), + .I4(data_oe_r_i_7_n_0), + .I5(\u5/mem_ack_r ), + .O(mem_ack_r_i_9_n_0)); + FDRE mem_ack_r_reg + (.C(clk_i), + .CE(\ ), + .D(mem_ack), + .Q(mem_ack_r), + .R(\ )); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT2 #( + .INIT(4'h2)) + no_wb_cycle_i_1 + (.I0(no_wb_cycle_i_2_n_0), + .I1(wb_write_go), + .O(\u5/p_65_in )); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT3 #( + .INIT(8'hBF)) + no_wb_cycle_i_2 + (.I0(wb_write_go_r_i_2_n_0), + .I1(\u6/read_go_r1 ), + .I2(wb_cyc_i), + .O(no_wb_cycle_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFAAAAFFBF)) + oe__i_1 + (.I0(oe__reg_i_2_n_0), + .I1(oe__i_3_n_0), + .I2(\mc_addr[14]_i_4_n_0 ), + .I3(wb_write_go), + .I4(\u5/state [5]), + .I5(\u5/state [6]), + .O(oe__i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT4 #( + .INIT(16'h2202)) + oe__i_3 + (.I0(\FSM_sequential_state[5]_i_8_n_0 ), + .I1(\FSM_sequential_state[5]_i_9_n_0 ), + .I2(wb_cyc_i), + .I3(wb_stb_i), + .O(oe__i_3_n_0)); + LUT6 #( + .INIT(64'hF3F3737F33FC33FF)) + oe__i_4 + (.I0(\FSM_sequential_state[6]_i_33_n_0 ), + .I1(\u5/state [5]), + .I2(\u5/state [1]), + .I3(\u5/state [3]), + .I4(\u5/state [0]), + .I5(\u5/state [4]), + .O(oe__i_4_n_0)); + LUT5 #( + .INIT(32'hFFFBBBBB)) + oe__i_5 + (.I0(\u5/state [4]), + .I1(\u5/state [5]), + .I2(\u5/state [1]), + .I3(\u5/state [0]), + .I4(\u5/state [3]), + .O(oe__i_5_n_0)); + MUXF7 oe__reg_i_2 + (.I0(oe__i_4_n_0), + .I1(oe__i_5_n_0), + .O(oe__reg_i_2_n_0), + .S(\u5/state [2])); + LUT1 #( + .INIT(2'h1)) + \out_r[0]_i_1 + (.I0(acs_addr[0]), + .O(\out_r[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h44F4000000000000)) + pack_le0_i_1 + (.I0(\u5/state [3]), + .I1(\u5/state [2]), + .I2(pack_le0_i_2_n_0), + .I3(pack_le0_i_3_n_0), + .I4(\timer2[8]_i_5_n_0 ), + .I5(\u5/state [1]), + .O(\u5/pack_le0_d )); + LUT3 #( + .INIT(8'hB8)) + pack_le0_i_2 + (.I0(csc[4]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_csc[4]), + .O(pack_le0_i_2_n_0)); + LUT3 #( + .INIT(8'hB8)) + pack_le0_i_3 + (.I0(csc[5]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_csc[5]), + .O(pack_le0_i_3_n_0)); + LUT6 #( + .INIT(64'h0000000000002000)) + pack_le1_i_1 + (.I0(\u5/state [3]), + .I1(\u5/state [4]), + .I2(\u5/state [5]), + .I3(\FSM_sequential_state[0]_i_3_n_0 ), + .I4(\u5/state [6]), + .I5(\u5/state [1]), + .O(\u5/pack_le1_d )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT5 #( + .INIT(32'h00000010)) + pack_le2_i_1 + (.I0(pack_le0_i_2_n_0), + .I1(pack_le0_i_3_n_0), + .I2(\u5/state [3]), + .I3(\u5/state [0]), + .I4(pack_le2_i_2_n_0), + .O(\u5/pack_le2_d )); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT5 #( + .INIT(32'hFFFBFFFF)) + pack_le2_i_2 + (.I0(\u5/state [6]), + .I1(\u5/state [5]), + .I2(\u5/state [4]), + .I3(\u5/state [2]), + .I4(\u5/state [1]), + .O(pack_le2_i_2_n_0)); + LUT2 #( + .INIT(4'h1)) + \ps_cnt[0]_i_1 + (.I0(\u4/ps_cnt_reg [0]), + .I1(\u4/ps_cnt_clr ), + .O(p_0_in__1[0])); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'h06)) + \ps_cnt[1]_i_1 + (.I0(\u4/ps_cnt_reg [1]), + .I1(\u4/ps_cnt_reg [0]), + .I2(\u4/ps_cnt_clr ), + .O(p_0_in__1[1])); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT4 #( + .INIT(16'h0078)) + \ps_cnt[2]_i_1 + (.I0(\u4/ps_cnt_reg [0]), + .I1(\u4/ps_cnt_reg [1]), + .I2(\u4/ps_cnt_reg [2]), + .I3(\u4/ps_cnt_clr ), + .O(p_0_in__1[2])); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT5 #( + .INIT(32'h00007F80)) + \ps_cnt[3]_i_1 + (.I0(\u4/ps_cnt_reg [2]), + .I1(\u4/ps_cnt_reg [1]), + .I2(\u4/ps_cnt_reg [0]), + .I3(\u4/ps_cnt_reg [3]), + .I4(\u4/ps_cnt_clr ), + .O(p_0_in__1[3])); + LUT6 #( + .INIT(64'h000000007FFF8000)) + \ps_cnt[4]_i_1 + (.I0(\u4/ps_cnt_reg [3]), + .I1(\u4/ps_cnt_reg [0]), + .I2(\u4/ps_cnt_reg [1]), + .I3(\u4/ps_cnt_reg [2]), + .I4(\u4/ps_cnt_reg [4]), + .I5(\u4/ps_cnt_clr ), + .O(p_0_in__1[4])); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'h06)) + \ps_cnt[5]_i_1 + (.I0(\ps_cnt[5]_i_2_n_0 ), + .I1(\u4/ps_cnt_reg [5]), + .I2(\u4/ps_cnt_clr ), + .O(p_0_in__1[5])); + LUT5 #( + .INIT(32'h80000000)) + \ps_cnt[5]_i_2 + (.I0(\u4/ps_cnt_reg [4]), + .I1(\u4/ps_cnt_reg [2]), + .I2(\u4/ps_cnt_reg [1]), + .I3(\u4/ps_cnt_reg [0]), + .I4(\u4/ps_cnt_reg [3]), + .O(\ps_cnt[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT3 #( + .INIT(8'h06)) + \ps_cnt[6]_i_1 + (.I0(\ps_cnt[7]_i_3_n_0 ), + .I1(\u4/ps_cnt_reg [6]), + .I2(\u4/ps_cnt_clr ), + .O(p_0_in__1[6])); + LUT2 #( + .INIT(4'hE)) + \ps_cnt[7]_i_1 + (.I0(\u4/rfr_en ), + .I1(\u4/ps_cnt_clr ), + .O(\ps_cnt[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT4 #( + .INIT(16'h0078)) + \ps_cnt[7]_i_2 + (.I0(\u4/ps_cnt_reg [6]), + .I1(\ps_cnt[7]_i_3_n_0 ), + .I2(\u4/ps_cnt_reg [7]), + .I3(\u4/ps_cnt_clr ), + .O(p_0_in__1[7])); + LUT6 #( + .INIT(64'h8000000000000000)) + \ps_cnt[7]_i_3 + (.I0(\u4/ps_cnt_reg [5]), + .I1(\u4/ps_cnt_reg [3]), + .I2(\u4/ps_cnt_reg [0]), + .I3(\u4/ps_cnt_reg [1]), + .I4(\u4/ps_cnt_reg [2]), + .I5(\u4/ps_cnt_reg [4]), + .O(\ps_cnt[7]_i_3_n_0 )); + LUT2 #( + .INIT(4'h8)) + \r0[35]_i_1 + (.I0(\u3/u0/wr_adr_reg_n_0_[0] ), + .I1(dv), + .O(\u3/u0/r00 )); + LUT2 #( + .INIT(4'h8)) + \r1[35]_i_1 + (.I0(\u3/u0/p_0_in1_in ), + .I1(dv), + .O(\u3/u0/r10 )); + LUT2 #( + .INIT(4'h8)) + \r2[35]_i_1 + (.I0(\u3/u0/p_0_in0_in ), + .I1(dv), + .O(\u3/u0/r20 )); + LUT2 #( + .INIT(4'h8)) + \r3[35]_i_1 + (.I0(\u3/u0/p_0_in ), + .I1(dv), + .O(\u3/u0/r30 )); + LUT4 #( + .INIT(16'hFBBB)) + \rd_adr[0]_i_1 + (.I0(\u3/u0/rd_adr [3]), + .I1(wb_cyc_i), + .I2(wb_we_i), + .I3(wb_stb_i), + .O(\rd_adr[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'h0888)) + \rd_adr[1]_i_1 + (.I0(\u3/u0/rd_adr [0]), + .I1(wb_cyc_i), + .I2(wb_we_i), + .I3(wb_stb_i), + .O(\rd_adr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT4 #( + .INIT(16'h0888)) + \rd_adr[2]_i_1 + (.I0(\u3/u0/rd_adr [1]), + .I1(wb_cyc_i), + .I2(wb_we_i), + .I3(wb_stb_i), + .O(\rd_adr[2]_i_1_n_0 )); + LUT5 #( + .INIT(32'hD5FFD5D5)) + \rd_adr[3]_i_1 + (.I0(wb_cyc_i), + .I1(wb_we_i), + .I2(wb_stb_i), + .I3(no_wb_cycle_i_2_n_0), + .I4(mem_ack_r), + .O(\rd_adr[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT4 #( + .INIT(16'h0888)) + \rd_adr[3]_i_2 + (.I0(\u3/u0/rd_adr [2]), + .I1(wb_cyc_i), + .I2(wb_we_i), + .I3(wb_stb_i), + .O(\rd_adr[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h00000000FF400000)) + read_go_r1_i_1 + (.I0(wb_we_i), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(wb_stb_i), + .I3(\u6/read_go_r ), + .I4(wb_cyc_i), + .I5(wb_write_go_r_i_2_n_0), + .O(\u6/read_go_r10 )); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT2 #( + .INIT(4'h8)) + read_go_r_i_1 + (.I0(\u6/read_go_r1 ), + .I1(wb_cyc_i), + .O(\u6/read_go_r0 )); + LUT6 #( + .INIT(64'h0000000004000000)) + rf_we_i_1 + (.I0(wb_ack_o_i_3_n_0), + .I1(wb_we_i), + .I2(wb_addr_i[31]), + .I3(wb_addr_i[29]), + .I4(wb_addr_i[30]), + .I5(\u0/rf_we ), + .O(\u0/rf_we0 )); + LUT6 #( + .INIT(64'h222222F200000000)) + rfr_ack_r_i_1 + (.I0(rfr_ack_r_i_2_n_0), + .I1(rfr_ack_r_i_3_n_0), + .I2(rfr_ack_r_i_4_n_0), + .I3(rfr_ack_r_i_5_n_0), + .I4(rfr_ack_r_i_6_n_0), + .I5(rfr_ack_r_i_7_n_0), + .O(rfr_ack_r_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT2 #( + .INIT(4'h8)) + rfr_ack_r_i_2 + (.I0(\u5/state [3]), + .I1(\u5/state [1]), + .O(rfr_ack_r_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT3 #( + .INIT(8'hDF)) + rfr_ack_r_i_3 + (.I0(\u5/state [2]), + .I1(\u5/state [4]), + .I2(\u5/state [0]), + .O(rfr_ack_r_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h8F)) + rfr_ack_r_i_4 + (.I0(\u5/state [1]), + .I1(\u5/state [0]), + .I2(\u5/state [4]), + .O(rfr_ack_r_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT2 #( + .INIT(4'hE)) + rfr_ack_r_i_5 + (.I0(\u5/state [2]), + .I1(\u5/state [3]), + .O(rfr_ack_r_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT5 #( + .INIT(32'h000F0077)) + rfr_ack_r_i_6 + (.I0(rfr_req), + .I1(\u5/state [0]), + .I2(rfr_ack), + .I3(\u5/state [4]), + .I4(\u5/state [1]), + .O(rfr_ack_r_i_6_n_0)); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT2 #( + .INIT(4'h1)) + rfr_ack_r_i_7 + (.I0(\u5/state [5]), + .I1(\u5/state [6]), + .O(rfr_ack_r_i_7_n_0)); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAAAA8)) + rfr_ce_i_1 + (.I0(\u4/ps_cnt_clr01_in ), + .I1(rfr_ce_i_2_n_0), + .I2(rfr_ps_val[6]), + .I3(rfr_ps_val[5]), + .I4(rfr_ps_val[3]), + .I5(rfr_ps_val[1]), + .O(\u4/ps_cnt_clr )); + LUT4 #( + .INIT(16'hFFFE)) + rfr_ce_i_2 + (.I0(rfr_ps_val[7]), + .I1(rfr_ps_val[4]), + .I2(rfr_ps_val[2]), + .I3(rfr_ps_val[0]), + .O(rfr_ce_i_2_n_0)); + LUT4 #( + .INIT(16'h7000)) + rfr_clr_i_1 + (.I0(rfr_clr_i_2_n_0), + .I1(sel0[2]), + .I2(rfr_clr_i_3_n_0), + .I3(\u4/rfr_early ), + .O(\u4/rfr_clr )); + LUT6 #( + .INIT(64'h7050FFFFFFF0FFFF)) + rfr_clr_i_2 + (.I0(\u4/rfr_cnt_reg__0 [6]), + .I1(\u4/rfr_cnt_reg__0 [7]), + .I2(sel0[1]), + .I3(sel0[0]), + .I4(\rfr_cnt[7]_i_3_n_0 ), + .I5(\u4/rfr_cnt_reg__0 [5]), + .O(rfr_clr_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFF4044FFFFFFFF)) + rfr_clr_i_3 + (.I0(sel0[1]), + .I1(\u4/rfr_cnt_reg ), + .I2(\u4/rfr_cnt_reg__0 [1]), + .I3(sel0[0]), + .I4(sel0[2]), + .I5(rfr_clr_i_4_n_0), + .O(rfr_clr_i_3_n_0)); + LUT6 #( + .INIT(64'h7F7FFF7FFFFFFFFF)) + rfr_clr_i_4 + (.I0(\u4/rfr_cnt_reg__0 [2]), + .I1(\u4/rfr_cnt_reg ), + .I2(\u4/rfr_cnt_reg__0 [1]), + .I3(sel0[0]), + .I4(\u4/rfr_cnt_reg__0 [3]), + .I5(sel0[1]), + .O(rfr_clr_i_4_n_0)); + LUT2 #( + .INIT(4'h1)) + \rfr_cnt[0]_i_1 + (.I0(rfr_ack), + .I1(\u4/rfr_cnt_reg ), + .O(p_0_in__2[0])); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'h06)) + \rfr_cnt[1]_i_1 + (.I0(\u4/rfr_cnt_reg__0 [1]), + .I1(\u4/rfr_cnt_reg ), + .I2(rfr_ack), + .O(p_0_in__2[1])); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT4 #( + .INIT(16'h1540)) + \rfr_cnt[2]_i_1 + (.I0(rfr_ack), + .I1(\u4/rfr_cnt_reg ), + .I2(\u4/rfr_cnt_reg__0 [1]), + .I3(\u4/rfr_cnt_reg__0 [2]), + .O(\rfr_cnt[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT5 #( + .INIT(32'h00007F80)) + \rfr_cnt[3]_i_1 + (.I0(\u4/rfr_cnt_reg__0 [1]), + .I1(\u4/rfr_cnt_reg ), + .I2(\u4/rfr_cnt_reg__0 [2]), + .I3(\u4/rfr_cnt_reg__0 [3]), + .I4(rfr_ack), + .O(p_0_in__2[3])); + LUT6 #( + .INIT(64'h1555555540000000)) + \rfr_cnt[4]_i_1 + (.I0(rfr_ack), + .I1(\u4/rfr_cnt_reg__0 [3]), + .I2(\u4/rfr_cnt_reg__0 [2]), + .I3(\u4/rfr_cnt_reg ), + .I4(\u4/rfr_cnt_reg__0 [1]), + .I5(\u4/rfr_cnt_reg__0 [4]), + .O(\rfr_cnt[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'h06)) + \rfr_cnt[5]_i_1 + (.I0(\rfr_cnt[7]_i_3_n_0 ), + .I1(\u4/rfr_cnt_reg__0 [5]), + .I2(rfr_ack), + .O(p_0_in__2[5])); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT4 #( + .INIT(16'h1540)) + \rfr_cnt[6]_i_1 + (.I0(rfr_ack), + .I1(\u4/rfr_cnt_reg__0 [5]), + .I2(\rfr_cnt[7]_i_3_n_0 ), + .I3(\u4/rfr_cnt_reg__0 [6]), + .O(\rfr_cnt[6]_i_1_n_0 )); + LUT2 #( + .INIT(4'hE)) + \rfr_cnt[7]_i_1 + (.I0(\u4/rfr_ce ), + .I1(rfr_ack), + .O(\rfr_cnt[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT5 #( + .INIT(32'h00007F80)) + \rfr_cnt[7]_i_2 + (.I0(\rfr_cnt[7]_i_3_n_0 ), + .I1(\u4/rfr_cnt_reg__0 [6]), + .I2(\u4/rfr_cnt_reg__0 [5]), + .I3(\u4/rfr_cnt_reg__0 [7]), + .I4(rfr_ack), + .O(p_0_in__2[7])); + LUT5 #( + .INIT(32'h80000000)) + \rfr_cnt[7]_i_3 + (.I0(\u4/rfr_cnt_reg__0 [4]), + .I1(\u4/rfr_cnt_reg__0 [1]), + .I2(\u4/rfr_cnt_reg ), + .I3(\u4/rfr_cnt_reg__0 [2]), + .I4(\u4/rfr_cnt_reg__0 [3]), + .O(\rfr_cnt[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000009009)) + rfr_early_i_1 + (.I0(\u4/ps_cnt_reg [7]), + .I1(rfr_ps_val[7]), + .I2(\u4/ps_cnt_reg [6]), + .I3(rfr_ps_val[6]), + .I4(rfr_early_i_2_n_0), + .I5(rfr_early_i_3_n_0), + .O(\u4/ps_cnt_clr01_in )); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + rfr_early_i_2 + (.I0(rfr_ps_val[0]), + .I1(\u4/ps_cnt_reg [0]), + .I2(\u4/ps_cnt_reg [2]), + .I3(rfr_ps_val[2]), + .I4(\u4/ps_cnt_reg [1]), + .I5(rfr_ps_val[1]), + .O(rfr_early_i_2_n_0)); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + rfr_early_i_3 + (.I0(rfr_ps_val[3]), + .I1(\u4/ps_cnt_reg [3]), + .I2(\u4/ps_cnt_reg [4]), + .I3(rfr_ps_val[4]), + .I4(\u4/ps_cnt_reg [5]), + .I5(rfr_ps_val[5]), + .O(rfr_early_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT5 #( + .INIT(32'hFFFF0100)) + rfr_en_i_1 + (.I0(\u0/u1/csc_reg_n_0_[2] ), + .I1(\u0/u1/csc_reg_n_0_[3] ), + .I2(\u0/u1/csc_reg_n_0_[1] ), + .I3(\u0/u1/csc_reg_n_0_[0] ), + .I4(rfr_en_i_2_n_0), + .O(rfr_en_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT4 #( + .INIT(16'h0002)) + rfr_en_i_2 + (.I0(\u0/u0/csc_reg_n_0_[0] ), + .I1(\u0/u0/csc_reg_n_0_[1] ), + .I2(\u0/u0/csc_reg_n_0_[3] ), + .I3(\u0/u0/csc_reg_n_0_[2] ), + .O(rfr_en_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'h54)) + rfr_req_i_1 + (.I0(rfr_ack), + .I1(\u4/rfr_clr_reg_n_0 ), + .I2(rfr_req), + .O(rfr_req_i_1_n_0)); + LUT3 #( + .INIT(8'hEA)) + rmw_en_i_1 + (.I0(wb_ack_o), + .I1(wb_cyc_i), + .I2(\u6/rmw_en ), + .O(rmw_en_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT5 #( + .INIT(32'h00008000)) + rmw_r_i_1 + (.I0(wb_stb_i), + .I1(wb_cyc_i), + .I2(wb_we_i), + .I3(\u6/rmw_en ), + .I4(wr_hold), + .O(\u6/rmw_r0 )); + LUT2 #( + .INIT(4'h9)) + row0_same_carry__0_i_1 + (.I0(row_adr[12]), + .I1(\u2/u0/b0_last_row_reg_n_0_[12] ), + .O(row0_same_carry__0_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + row0_same_carry__0_i_1__0 + (.I0(row_adr[12]), + .I1(b0_last_row[12]), + .O(row0_same_carry__0_i_1__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row0_same_carry_i_1 + (.I0(b0_last_row[11]), + .I1(row_adr[11]), + .I2(b0_last_row[10]), + .I3(row_adr[10]), + .I4(row_adr[9]), + .I5(b0_last_row[9]), + .O(row0_same_carry_i_1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row0_same_carry_i_1__0 + (.I0(row_adr[10]), + .I1(\u2/u0/b0_last_row_reg_n_0_[10] ), + .I2(\u2/u0/b0_last_row_reg_n_0_[11] ), + .I3(row_adr[11]), + .I4(\u2/u0/b0_last_row_reg_n_0_[9] ), + .I5(row_adr[9]), + .O(row0_same_carry_i_1__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row0_same_carry_i_2 + (.I0(row_adr[7]), + .I1(b0_last_row[7]), + .I2(b0_last_row[8]), + .I3(row_adr[8]), + .I4(b0_last_row[6]), + .I5(row_adr[6]), + .O(row0_same_carry_i_2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row0_same_carry_i_2__0 + (.I0(row_adr[7]), + .I1(\u2/u0/b0_last_row_reg_n_0_[7] ), + .I2(\u2/u0/b0_last_row_reg_n_0_[8] ), + .I3(row_adr[8]), + .I4(\u2/u0/b0_last_row_reg_n_0_[6] ), + .I5(row_adr[6]), + .O(row0_same_carry_i_2__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row0_same_carry_i_3 + (.I0(row_adr[4]), + .I1(b0_last_row[4]), + .I2(b0_last_row[5]), + .I3(row_adr[5]), + .I4(b0_last_row[3]), + .I5(row_adr[3]), + .O(row0_same_carry_i_3_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row0_same_carry_i_3__0 + (.I0(\u2/u0/b0_last_row_reg_n_0_[5] ), + .I1(row_adr[5]), + .I2(\u2/u0/b0_last_row_reg_n_0_[4] ), + .I3(row_adr[4]), + .I4(row_adr[3]), + .I5(\u2/u0/b0_last_row_reg_n_0_[3] ), + .O(row0_same_carry_i_3__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row0_same_carry_i_4 + (.I0(b0_last_row[2]), + .I1(row_adr[2]), + .I2(b0_last_row[1]), + .I3(row_adr[1]), + .I4(row_adr[0]), + .I5(b0_last_row[0]), + .O(row0_same_carry_i_4_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row0_same_carry_i_4__0 + (.I0(\u2/u0/b0_last_row_reg_n_0_[2] ), + .I1(row_adr[2]), + .I2(\u2/u0/b0_last_row_reg_n_0_[0] ), + .I3(row_adr[0]), + .I4(row_adr[1]), + .I5(\u2/u0/b0_last_row_reg_n_0_[1] ), + .O(row0_same_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'h9)) + row1_same_carry__0_i_1 + (.I0(row_adr[12]), + .I1(b1_last_row[12]), + .O(row1_same_carry__0_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + row1_same_carry__0_i_1__0 + (.I0(row_adr[12]), + .I1(\u2/u0/b1_last_row_reg_n_0_[12] ), + .O(row1_same_carry__0_i_1__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row1_same_carry_i_1 + (.I0(b1_last_row[11]), + .I1(row_adr[11]), + .I2(b1_last_row[10]), + .I3(row_adr[10]), + .I4(row_adr[9]), + .I5(b1_last_row[9]), + .O(row1_same_carry_i_1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row1_same_carry_i_1__0 + (.I0(\u2/u0/b1_last_row_reg_n_0_[11] ), + .I1(row_adr[11]), + .I2(\u2/u0/b1_last_row_reg_n_0_[10] ), + .I3(row_adr[10]), + .I4(row_adr[9]), + .I5(\u2/u0/b1_last_row_reg_n_0_[9] ), + .O(row1_same_carry_i_1__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row1_same_carry_i_2 + (.I0(row_adr[7]), + .I1(b1_last_row[7]), + .I2(b1_last_row[8]), + .I3(row_adr[8]), + .I4(b1_last_row[6]), + .I5(row_adr[6]), + .O(row1_same_carry_i_2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row1_same_carry_i_2__0 + (.I0(row_adr[7]), + .I1(\u2/u0/b1_last_row_reg_n_0_[7] ), + .I2(\u2/u0/b1_last_row_reg_n_0_[8] ), + .I3(row_adr[8]), + .I4(\u2/u0/b1_last_row_reg_n_0_[6] ), + .I5(row_adr[6]), + .O(row1_same_carry_i_2__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row1_same_carry_i_3 + (.I0(b1_last_row[5]), + .I1(row_adr[5]), + .I2(b1_last_row[4]), + .I3(row_adr[4]), + .I4(row_adr[3]), + .I5(b1_last_row[3]), + .O(row1_same_carry_i_3_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row1_same_carry_i_3__0 + (.I0(row_adr[4]), + .I1(\u2/u0/b1_last_row_reg_n_0_[4] ), + .I2(\u2/u0/b1_last_row_reg_n_0_[5] ), + .I3(row_adr[5]), + .I4(\u2/u0/b1_last_row_reg_n_0_[3] ), + .I5(row_adr[3]), + .O(row1_same_carry_i_3__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row1_same_carry_i_4 + (.I0(b1_last_row[2]), + .I1(row_adr[2]), + .I2(b1_last_row[0]), + .I3(row_adr[0]), + .I4(row_adr[1]), + .I5(b1_last_row[1]), + .O(row1_same_carry_i_4_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row1_same_carry_i_4__0 + (.I0(\u2/u0/b1_last_row_reg_n_0_[2] ), + .I1(row_adr[2]), + .I2(\u2/u0/b1_last_row_reg_n_0_[0] ), + .I3(row_adr[0]), + .I4(row_adr[1]), + .I5(\u2/u0/b1_last_row_reg_n_0_[1] ), + .O(row1_same_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'h9)) + row2_same_carry__0_i_1 + (.I0(row_adr[12]), + .I1(b2_last_row[12]), + .O(row2_same_carry__0_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + row2_same_carry__0_i_1__0 + (.I0(row_adr[12]), + .I1(\u2/u0/b2_last_row_reg_n_0_[12] ), + .O(row2_same_carry__0_i_1__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row2_same_carry_i_1 + (.I0(b2_last_row[11]), + .I1(row_adr[11]), + .I2(b2_last_row[10]), + .I3(row_adr[10]), + .I4(row_adr[9]), + .I5(b2_last_row[9]), + .O(row2_same_carry_i_1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row2_same_carry_i_1__0 + (.I0(row_adr[10]), + .I1(\u2/u0/b2_last_row_reg_n_0_[10] ), + .I2(\u2/u0/b2_last_row_reg_n_0_[11] ), + .I3(row_adr[11]), + .I4(\u2/u0/b2_last_row_reg_n_0_[9] ), + .I5(row_adr[9]), + .O(row2_same_carry_i_1__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row2_same_carry_i_2 + (.I0(b2_last_row[8]), + .I1(row_adr[8]), + .I2(b2_last_row[7]), + .I3(row_adr[7]), + .I4(row_adr[6]), + .I5(b2_last_row[6]), + .O(row2_same_carry_i_2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row2_same_carry_i_2__0 + (.I0(row_adr[7]), + .I1(\u2/u0/b2_last_row_reg_n_0_[7] ), + .I2(\u2/u0/b2_last_row_reg_n_0_[8] ), + .I3(row_adr[8]), + .I4(\u2/u0/b2_last_row_reg_n_0_[6] ), + .I5(row_adr[6]), + .O(row2_same_carry_i_2__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row2_same_carry_i_3 + (.I0(b2_last_row[5]), + .I1(row_adr[5]), + .I2(b2_last_row[4]), + .I3(row_adr[4]), + .I4(row_adr[3]), + .I5(b2_last_row[3]), + .O(row2_same_carry_i_3_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row2_same_carry_i_3__0 + (.I0(row_adr[4]), + .I1(\u2/u0/b2_last_row_reg_n_0_[4] ), + .I2(\u2/u0/b2_last_row_reg_n_0_[5] ), + .I3(row_adr[5]), + .I4(\u2/u0/b2_last_row_reg_n_0_[3] ), + .I5(row_adr[3]), + .O(row2_same_carry_i_3__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row2_same_carry_i_4 + (.I0(b2_last_row[2]), + .I1(row_adr[2]), + .I2(b2_last_row[1]), + .I3(row_adr[1]), + .I4(row_adr[0]), + .I5(b2_last_row[0]), + .O(row2_same_carry_i_4_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row2_same_carry_i_4__0 + (.I0(\u2/u0/b2_last_row_reg_n_0_[2] ), + .I1(row_adr[2]), + .I2(\u2/u0/b2_last_row_reg_n_0_[1] ), + .I3(row_adr[1]), + .I4(row_adr[0]), + .I5(\u2/u0/b2_last_row_reg_n_0_[0] ), + .O(row2_same_carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'h9)) + row3_same_carry__0_i_1 + (.I0(row_adr[12]), + .I1(b3_last_row[12]), + .O(row3_same_carry__0_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + row3_same_carry__0_i_1__0 + (.I0(row_adr[12]), + .I1(\u2/u0/b3_last_row_reg_n_0_[12] ), + .O(row3_same_carry__0_i_1__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row3_same_carry_i_1 + (.I0(row_adr[10]), + .I1(b3_last_row[10]), + .I2(b3_last_row[11]), + .I3(row_adr[11]), + .I4(b3_last_row[9]), + .I5(row_adr[9]), + .O(row3_same_carry_i_1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row3_same_carry_i_1__0 + (.I0(\u2/u0/b3_last_row_reg_n_0_[11] ), + .I1(row_adr[11]), + .I2(\u2/u0/b3_last_row_reg_n_0_[10] ), + .I3(row_adr[10]), + .I4(row_adr[9]), + .I5(\u2/u0/b3_last_row_reg_n_0_[9] ), + .O(row3_same_carry_i_1__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row3_same_carry_i_2 + (.I0(row_adr[7]), + .I1(b3_last_row[7]), + .I2(b3_last_row[8]), + .I3(row_adr[8]), + .I4(b3_last_row[6]), + .I5(row_adr[6]), + .O(row3_same_carry_i_2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row3_same_carry_i_2__0 + (.I0(\u2/u0/b3_last_row_reg_n_0_[8] ), + .I1(row_adr[8]), + .I2(\u2/u0/b3_last_row_reg_n_0_[7] ), + .I3(row_adr[7]), + .I4(row_adr[6]), + .I5(\u2/u0/b3_last_row_reg_n_0_[6] ), + .O(row3_same_carry_i_2__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row3_same_carry_i_3 + (.I0(b3_last_row[5]), + .I1(row_adr[5]), + .I2(b3_last_row[4]), + .I3(row_adr[4]), + .I4(row_adr[3]), + .I5(b3_last_row[3]), + .O(row3_same_carry_i_3_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row3_same_carry_i_3__0 + (.I0(row_adr[4]), + .I1(\u2/u0/b3_last_row_reg_n_0_[4] ), + .I2(\u2/u0/b3_last_row_reg_n_0_[5] ), + .I3(row_adr[5]), + .I4(\u2/u0/b3_last_row_reg_n_0_[3] ), + .I5(row_adr[3]), + .O(row3_same_carry_i_3__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row3_same_carry_i_4 + (.I0(b3_last_row[2]), + .I1(row_adr[2]), + .I2(b3_last_row[0]), + .I3(row_adr[0]), + .I4(row_adr[1]), + .I5(b3_last_row[1]), + .O(row3_same_carry_i_4_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + row3_same_carry_i_4__0 + (.I0(\u2/u0/b3_last_row_reg_n_0_[2] ), + .I1(row_adr[2]), + .I2(\u2/u0/b3_last_row_reg_n_0_[1] ), + .I3(row_adr[1]), + .I4(row_adr[0]), + .I5(\u2/u0/b3_last_row_reg_n_0_[0] ), + .O(row3_same_carry_i_4__0_n_0)); + LUT5 #( + .INIT(32'hBABF8A80)) + \row_adr[0]_i_1 + (.I0(\bank_adr[0]_i_3_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\row_adr[2]_i_2_n_0 ), + .O(\row_adr[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hBABF8A80)) + \row_adr[10]_i_1 + (.I0(\row_adr[10]_i_2_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\row_adr[10]_i_3_n_0 ), + .O(\row_adr[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFCFECE03003202)) + \row_adr[10]_i_2 + (.I0(wb_addr_i[22]), + .I1(pack_le0_i_3_n_0), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[21]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[20]), + .O(\row_adr[10]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFEFB1051FEEA1040)) + \row_adr[10]_i_3 + (.I0(pack_le0_i_3_n_0), + .I1(\col_adr[9]_i_3_n_0 ), + .I2(wb_addr_i[23]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[22]), + .I5(wb_addr_i[24]), + .O(\row_adr[10]_i_3_n_0 )); + LUT6 #( + .INIT(64'h00FFEEB8000022B8)) + \row_adr[11]_i_2 + (.I0(wb_addr_i[24]), + .I1(pack_le0_i_2_n_0), + .I2(wb_addr_i[25]), + .I3(\col_adr[9]_i_3_n_0 ), + .I4(pack_le0_i_3_n_0), + .I5(wb_addr_i[23]), + .O(\row_adr[11]_i_2_n_0 )); + LUT6 #( + .INIT(64'h22222222B8F3B8C0)) + \row_adr[11]_i_3 + (.I0(wb_addr_i[21]), + .I1(\col_adr[9]_i_3_n_0 ), + .I2(wb_addr_i[22]), + .I3(pack_le0_i_2_n_0), + .I4(wb_addr_i[23]), + .I5(pack_le0_i_3_n_0), + .O(\row_adr[11]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \row_adr[12]_i_2 + (.I0(csc__0[9]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_csc[9]), + .O(\row_adr[12]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAAAAA8080000A808)) + \row_adr[12]_i_3 + (.I0(\row_adr[12]_i_5_n_0 ), + .I1(wb_addr_i[26]), + .I2(pack_le0_i_2_n_0), + .I3(wb_addr_i[25]), + .I4(pack_le0_i_3_n_0), + .I5(wb_addr_i[24]), + .O(\row_adr[12]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAA8080000A808)) + \row_adr[12]_i_4 + (.I0(\row_adr[12]_i_5_n_0 ), + .I1(wb_addr_i[24]), + .I2(pack_le0_i_2_n_0), + .I3(wb_addr_i[23]), + .I4(pack_le0_i_3_n_0), + .I5(wb_addr_i[22]), + .O(\row_adr[12]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'hB8)) + \row_adr[12]_i_5 + (.I0(csc__0[7]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_csc[7]), + .O(\row_adr[12]_i_5_n_0 )); + LUT5 #( + .INIT(32'hBABF8A80)) + \row_adr[1]_i_1 + (.I0(\bank_adr[1]_i_3_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\row_adr[3]_i_2_n_0 ), + .O(\row_adr[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hBABF8A80)) + \row_adr[2]_i_1 + (.I0(\row_adr[2]_i_2_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\row_adr[4]_i_2_n_0 ), + .O(\row_adr[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFCFECE03003202)) + \row_adr[2]_i_2 + (.I0(wb_addr_i[14]), + .I1(pack_le0_i_3_n_0), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[13]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[12]), + .O(\row_adr[2]_i_2_n_0 )); + LUT5 #( + .INIT(32'hBABF8A80)) + \row_adr[3]_i_1 + (.I0(\row_adr[3]_i_2_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\row_adr[5]_i_2_n_0 ), + .O(\row_adr[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \row_adr[3]_i_2 + (.I0(pack_le0_i_3_n_0), + .I1(wb_addr_i[13]), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[14]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[15]), + .O(\row_adr[3]_i_2_n_0 )); + LUT5 #( + .INIT(32'hBABF8A80)) + \row_adr[4]_i_1 + (.I0(\row_adr[4]_i_2_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\row_adr[6]_i_2_n_0 ), + .O(\row_adr[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \row_adr[4]_i_2 + (.I0(pack_le0_i_3_n_0), + .I1(wb_addr_i[14]), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[15]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[16]), + .O(\row_adr[4]_i_2_n_0 )); + LUT5 #( + .INIT(32'hBABF8A80)) + \row_adr[5]_i_1 + (.I0(\row_adr[5]_i_2_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\row_adr[7]_i_2_n_0 ), + .O(\row_adr[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \row_adr[5]_i_2 + (.I0(pack_le0_i_3_n_0), + .I1(wb_addr_i[15]), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[16]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[17]), + .O(\row_adr[5]_i_2_n_0 )); + LUT5 #( + .INIT(32'hBABF8A80)) + \row_adr[6]_i_1 + (.I0(\row_adr[6]_i_2_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\row_adr[8]_i_2_n_0 ), + .O(\row_adr[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \row_adr[6]_i_2 + (.I0(pack_le0_i_3_n_0), + .I1(wb_addr_i[16]), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[17]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[18]), + .O(\row_adr[6]_i_2_n_0 )); + LUT5 #( + .INIT(32'hBABF8A80)) + \row_adr[7]_i_1 + (.I0(\row_adr[7]_i_2_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\row_adr[9]_i_2_n_0 ), + .O(\row_adr[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \row_adr[7]_i_2 + (.I0(pack_le0_i_3_n_0), + .I1(wb_addr_i[17]), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[18]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[19]), + .O(\row_adr[7]_i_2_n_0 )); + LUT5 #( + .INIT(32'hBABF8A80)) + \row_adr[8]_i_1 + (.I0(\row_adr[8]_i_2_n_0 ), + .I1(csc__0[9]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_csc[9]), + .I4(\row_adr[10]_i_2_n_0 ), + .O(\row_adr[8]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \row_adr[8]_i_2 + (.I0(pack_le0_i_3_n_0), + .I1(wb_addr_i[18]), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[19]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[20]), + .O(\row_adr[8]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB888BBBB)) + \row_adr[9]_i_1 + (.I0(\row_adr[9]_i_2_n_0 ), + .I1(\row_adr[12]_i_2_n_0 ), + .I2(wb_addr_i[21]), + .I3(pack_le0_i_3_n_0), + .I4(\row_adr[9]_i_3_n_0 ), + .O(\row_adr[9]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCDC8DD8DCDC8D888)) + \row_adr[9]_i_2 + (.I0(pack_le0_i_3_n_0), + .I1(wb_addr_i[19]), + .I2(\col_adr[9]_i_3_n_0 ), + .I3(wb_addr_i[20]), + .I4(pack_le0_i_2_n_0), + .I5(wb_addr_i[21]), + .O(\row_adr[9]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAAAFABFBFAFFABFB)) + \row_adr[9]_i_3 + (.I0(pack_le0_i_3_n_0), + .I1(wb_addr_i[23]), + .I2(pack_le0_i_2_n_0), + .I3(wb_addr_i[22]), + .I4(\col_adr[9]_i_3_n_0 ), + .I5(wb_addr_i[21]), + .O(\row_adr[9]_i_3_n_0 )); + MUXF7 \row_adr_reg[11]_i_1 + (.I0(\row_adr[11]_i_2_n_0 ), + .I1(\row_adr[11]_i_3_n_0 ), + .O(\row_adr_reg[11]_i_1_n_0 ), + .S(\row_adr[12]_i_2_n_0 )); + MUXF7 \row_adr_reg[12]_i_1 + (.I0(\row_adr[12]_i_3_n_0 ), + .I1(\row_adr[12]_i_4_n_0 ), + .O(\row_adr_reg[12]_i_1_n_0 ), + .S(\row_adr[12]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT4 #( + .INIT(16'h4F44)) + row_same_i_1 + (.I0(\mc_cs_[1]_i_2_n_0 ), + .I1(row_same_i_2_n_0), + .I2(row_same_i_3_n_0), + .I3(\mc_cs_[0]_i_2_n_0 ), + .O(\u2/row_same0 )); + LUT6 #( + .INIT(64'hCCF0FFAACCF000AA)) + row_same_i_2 + (.I0(\u2/u1/row0_same_carry__0_n_3 ), + .I1(\u2/u1/row3_same_carry__0_n_3 ), + .I2(\u2/u1/row1_same_carry__0_n_3 ), + .I3(bank_adr[1]), + .I4(bank_adr[0]), + .I5(\u2/u1/row2_same_carry__0_n_3 ), + .O(row_same_i_2_n_0)); + LUT6 #( + .INIT(64'h000F3355FF0F3355)) + row_same_i_3 + (.I0(\u2/row0_same ), + .I1(\u2/row1_same ), + .I2(\u2/row2_same ), + .I3(bank_adr[0]), + .I4(bank_adr[1]), + .I5(\u2/row3_same ), + .O(row_same_i_3_n_0)); + LUT4 #( + .INIT(16'hB888)) + \sp_csc[10]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[10] ), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/csc_reg_n_0_[10] ), + .O(\sp_csc[10]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_csc[1]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[1] ), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/csc_reg_n_0_[1] ), + .O(\sp_csc[1]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_csc[2]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[2] ), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/csc_reg_n_0_[2] ), + .O(\sp_csc[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_csc[3]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[3] ), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/csc_reg_n_0_[3] ), + .O(\sp_csc[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_csc[4]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[4] ), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/csc_reg_n_0_[4] ), + .O(\sp_csc[4]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_csc[5]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[5] ), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/csc_reg_n_0_[5] ), + .O(\sp_csc[5]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_csc[6]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[6] ), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/csc_reg_n_0_[6] ), + .O(\sp_csc[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_csc[7]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[7] ), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/csc_reg_n_0_[7] ), + .O(\sp_csc[7]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_csc[9]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[9] ), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/csc_reg_n_0_[9] ), + .O(\sp_csc[9]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[0]_i_1 + (.I0(tms[0]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[0] ), + .O(\sp_tms[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[10]_i_1 + (.I0(tms[10]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[10] ), + .O(\sp_tms[10]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[11]_i_1 + (.I0(tms[11]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[11] ), + .O(\sp_tms[11]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[12]_i_1 + (.I0(tms[12]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[12] ), + .O(\sp_tms[12]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[13]_i_1 + (.I0(tms[13]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[13] ), + .O(\sp_tms[13]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[14]_i_1 + (.I0(tms[14]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[14] ), + .O(\sp_tms[14]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[15]_i_1 + (.I0(tms[15]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[15] ), + .O(\sp_tms[15]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[16]_i_1 + (.I0(tms[16]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[16] ), + .O(\sp_tms[16]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[17]_i_1 + (.I0(tms[17]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[17] ), + .O(\sp_tms[17]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[18]_i_1 + (.I0(tms[18]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[18] ), + .O(\sp_tms[18]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[19]_i_1 + (.I0(tms[19]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[19] ), + .O(\sp_tms[19]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[1]_i_1 + (.I0(tms[1]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[1] ), + .O(\sp_tms[1]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[20]_i_1 + (.I0(tms[20]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[20] ), + .O(\sp_tms[20]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[21]_i_1 + (.I0(tms[21]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[21] ), + .O(\sp_tms[21]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[22]_i_1 + (.I0(tms[22]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[22] ), + .O(\sp_tms[22]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[23]_i_1 + (.I0(tms[23]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[23] ), + .O(\sp_tms[23]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[24]_i_1 + (.I0(tms[24]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[24] ), + .O(\sp_tms[24]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[25]_i_1 + (.I0(tms[25]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[25] ), + .O(\sp_tms[25]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[26]_i_1 + (.I0(tms[26]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[26] ), + .O(\sp_tms[26]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[27]_i_1 + (.I0(tms[27]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[27] ), + .O(\sp_tms[27]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[2]_i_1 + (.I0(tms[2]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[2] ), + .O(\sp_tms[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[3]_i_1 + (.I0(tms[3]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[3] ), + .O(\sp_tms[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[4]_i_1 + (.I0(tms[4]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[4] ), + .O(\sp_tms[4]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[5]_i_1 + (.I0(tms[5]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[5] ), + .O(\sp_tms[5]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[6]_i_1 + (.I0(tms[6]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[6] ), + .O(\sp_tms[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[7]_i_1 + (.I0(tms[7]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[7] ), + .O(\sp_tms[7]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[8]_i_1 + (.I0(tms[8]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[8] ), + .O(\sp_tms[8]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sp_tms[9]_i_1 + (.I0(tms[9]), + .I1(spec_req_cs[0]), + .I2(spec_req_cs[1]), + .I3(\u0/u1/tms_reg_n_0_[9] ), + .O(\sp_tms[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT3 #( + .INIT(8'hB8)) + \spec_req_cs[1]_i_2 + (.I0(\u0/u0/init_req_reg_n_0 ), + .I1(init_req), + .I2(\u0/u0/lmr_req_reg_n_0 ), + .O(\u0/spec_req_cs_t )); + LUT6 #( + .INIT(64'h11F111F1FFFF11F1)) + sreq_cs_le_i_1 + (.I0(lmr_req), + .I1(init_req), + .I2(\u0/lmr_ack_r ), + .I3(lmr_ack), + .I4(\u0/init_ack_r ), + .I5(init_ack), + .O(\u0/sreq_cs_le0 )); + LUT6 #( + .INIT(64'hFFEFEFEFFF000000)) + susp_sel_r_i_1 + (.I0(\u5/state [2]), + .I1(\u5/state [5]), + .I2(\FSM_sequential_state[6]_i_7_n_0 ), + .I3(\u5/burst_cnt_ld ), + .I4(susp_sel_r_i_2_n_0), + .I5(susp_sel), + .O(susp_sel_r_i_1_n_0)); + LUT6 #( + .INIT(64'h0000011100000000)) + susp_sel_r_i_2 + (.I0(rfr_req), + .I1(init_req), + .I2(\u5/lookup_ready2 ), + .I3(lmr_req), + .I4(wb_cycle), + .I5(\u5/susp_req_r ), + .O(susp_sel_r_i_2_n_0)); + LUT6 #( + .INIT(64'h0000000000000100)) + suspended_i_1 + (.I0(\u5/state [3]), + .I1(\u5/state [2]), + .I2(\u5/state [6]), + .I3(\u5/state [4]), + .I4(\u5/state [5]), + .I5(suspended_i_2_n_0), + .O(\u5/suspended_d )); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT2 #( + .INIT(4'h8)) + suspended_i_2 + (.I0(\u5/state [0]), + .I1(\u5/state [1]), + .O(suspended_i_2_n_0)); + LUT6 #( + .INIT(64'h0B00FFFF0B000B00)) + \timer2[0]_i_1 + (.I0(\timer2[0]_i_2_n_0 ), + .I1(\u5/timer2 [0]), + .I2(\timer2[0]_i_3_n_0 ), + .I3(\timer2[8]_i_4_n_0 ), + .I4(\timer2[0]_i_4_n_0 ), + .I5(\timer2[8]_i_9_n_0 ), + .O(\timer2[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h7)) + \timer2[0]_i_2 + (.I0(\timer2[8]_i_11_n_0 ), + .I1(\timer2[7]_i_3_n_0 ), + .O(\timer2[0]_i_2_n_0 )); + LUT5 #( + .INIT(32'h51510051)) + \timer2[0]_i_3 + (.I0(\timer2[7]_i_3_n_0 ), + .I1(\timer2[5]_i_3_n_0 ), + .I2(\timer2[4]_i_4_n_0 ), + .I3(\timer2[3]_i_6_n_0 ), + .I4(\timer[0]_i_8_n_0 ), + .O(\timer2[0]_i_3_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer2[0]_i_4 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[16]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[16] ), + .O(\timer2[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0B00FFFF0B000B00)) + \timer2[1]_i_1 + (.I0(\timer2[1]_i_2_n_0 ), + .I1(\timer2[1]_i_3_n_0 ), + .I2(\timer2[1]_i_4_n_0 ), + .I3(\timer2[8]_i_4_n_0 ), + .I4(\timer2[1]_i_5_n_0 ), + .I5(\timer2[8]_i_9_n_0 ), + .O(\timer2[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF88888F8FFFFFFFF)) + \timer2[1]_i_2 + (.I0(\timer2[8]_i_5_n_0 ), + .I1(\timer[0]_i_3_n_0 ), + .I2(\timer2[8]_i_11_n_0 ), + .I3(\u5/timer2 [0]), + .I4(\u5/timer2 [1]), + .I5(\timer2[7]_i_3_n_0 ), + .O(\timer2[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT5 #( + .INIT(32'h0047FFFF)) + \timer2[1]_i_3 + (.I0(\u0/tms_reg_n_0_[8] ), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_tms[8]), + .I3(\timer2[6]_i_3_n_0 ), + .I4(mem_ack_r_i_4_n_0), + .O(\timer2[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h2323202323202020)) + \timer2[1]_i_4 + (.I0(\timer[1]_i_8_n_0 ), + .I1(\timer2[7]_i_3_n_0 ), + .I2(\timer2[3]_i_6_n_0 ), + .I3(\timer2[3]_i_7_n_0 ), + .I4(\timer2[5]_i_5_n_0 ), + .I5(\timer2[0]_i_4_n_0 ), + .O(\timer2[1]_i_4_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer2[1]_i_5 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[17]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[17] ), + .O(\timer2[1]_i_5_n_0 )); + LUT6 #( + .INIT(64'hD0DDD000DDDDDDDD)) + \timer2[2]_i_1 + (.I0(\timer2[8]_i_9_n_0 ), + .I1(\timer2[2]_i_2_n_0 ), + .I2(\timer2[2]_i_3_n_0 ), + .I3(\timer2[7]_i_3_n_0 ), + .I4(\timer2[2]_i_4_n_0 ), + .I5(\timer2[8]_i_4_n_0 ), + .O(\timer2[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFEAE)) + \timer2[2]_i_2 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[18]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[18] ), + .O(\timer2[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h88888BB8FFFF8BB8)) + \timer2[2]_i_3 + (.I0(\timer[1]_i_2_n_0 ), + .I1(\timer2[8]_i_5_n_0 ), + .I2(\timer2[2]_i_5_n_0 ), + .I3(\u5/timer2 [2]), + .I4(mem_ack_r_i_4_n_0), + .I5(\timer[1]_i_7_n_0 ), + .O(\timer2[2]_i_3_n_0 )); + LUT5 #( + .INIT(32'h3530353F)) + \timer2[2]_i_4 + (.I0(\timer[2]_i_8_n_0 ), + .I1(\timer[2]_i_15_n_0 ), + .I2(\timer2[3]_i_6_n_0 ), + .I3(\timer2[3]_i_7_n_0 ), + .I4(\timer2[1]_i_5_n_0 ), + .O(\timer2[2]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT2 #( + .INIT(4'h1)) + \timer2[2]_i_5 + (.I0(\u5/timer2 [1]), + .I1(\u5/timer2 [0]), + .O(\timer2[2]_i_5_n_0 )); + LUT5 #( + .INIT(32'h10FF1010)) + \timer2[3]_i_1 + (.I0(\timer2[3]_i_2_n_0 ), + .I1(\timer2[3]_i_3_n_0 ), + .I2(\timer2[8]_i_4_n_0 ), + .I3(\timer2[3]_i_4_n_0 ), + .I4(\timer2[8]_i_9_n_0 ), + .O(\timer2[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000880C88CC880C)) + \timer2[3]_i_2 + (.I0(\timer[2]_i_14_n_0 ), + .I1(\timer2[7]_i_3_n_0 ), + .I2(\timer2[3]_i_5_n_0 ), + .I3(mem_ack_r_i_4_n_0), + .I4(\timer2[8]_i_5_n_0 ), + .I5(\timer[2]_i_2_n_0 ), + .O(\timer2[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h3331303103010001)) + \timer2[3]_i_3 + (.I0(\timer2[2]_i_2_n_0 ), + .I1(\timer2[7]_i_3_n_0 ), + .I2(\timer2[3]_i_6_n_0 ), + .I3(\timer2[3]_i_7_n_0 ), + .I4(\timer2[7]_i_4_n_0 ), + .I5(\timer[3]_i_10_n_0 ), + .O(\timer2[3]_i_3_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer2[3]_i_4 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[19]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[19] ), + .O(\timer2[3]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT4 #( + .INIT(16'hAAA9)) + \timer2[3]_i_5 + (.I0(\u5/timer2 [3]), + .I1(\u5/timer2 [2]), + .I2(\u5/timer2 [1]), + .I3(\u5/timer2 [0]), + .O(\timer2[3]_i_5_n_0 )); + LUT6 #( + .INIT(64'h0000000000001014)) + \timer2[3]_i_6 + (.I0(cke_r_i_5_n_0), + .I1(\u5/state [5]), + .I2(\u5/state [4]), + .I3(\u5/cmd_asserted ), + .I4(\u5/state [6]), + .I5(mc_bg_i_4_n_0), + .O(\timer2[3]_i_6_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBFFFFFFFFF)) + \timer2[3]_i_7 + (.I0(\u5/state [4]), + .I1(\u5/state [5]), + .I2(\FSM_sequential_state[0]_i_3_n_0 ), + .I3(\u5/state [6]), + .I4(\u5/state [1]), + .I5(\FSM_sequential_state[6]_i_32_n_0 ), + .O(\timer2[3]_i_7_n_0 )); + LUT5 #( + .INIT(32'h10FF1010)) + \timer2[4]_i_1 + (.I0(\timer2[4]_i_2_n_0 ), + .I1(\timer2[4]_i_3_n_0 ), + .I2(\timer2[8]_i_4_n_0 ), + .I3(\timer2[4]_i_4_n_0 ), + .I4(\timer2[8]_i_9_n_0 ), + .O(\timer2[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0000DDD0)) + \timer2[4]_i_2 + (.I0(\timer2[7]_i_5_n_0 ), + .I1(\timer2[8]_i_8_n_0 ), + .I2(\timer2[3]_i_4_n_0 ), + .I3(\timer2[4]_i_5_n_0 ), + .I4(\timer2[7]_i_3_n_0 ), + .O(\timer2[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'h8C8C8C80008C0080)) + \timer2[4]_i_3 + (.I0(\timer[3]_i_9_n_0 ), + .I1(\timer2[7]_i_3_n_0 ), + .I2(mem_ack_r_i_4_n_0), + .I3(\timer2[8]_i_5_n_0 ), + .I4(\timer2[4]_i_6_n_0 ), + .I5(\timer[3]_i_7_n_0 ), + .O(\timer2[4]_i_3_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer2[4]_i_4 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[20]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[20] ), + .O(\timer2[4]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT4 #( + .INIT(16'hFFFB)) + \timer2[4]_i_5 + (.I0(\timer2[3]_i_6_n_0 ), + .I1(\u5/tmr2_done ), + .I2(\u5/state [3]), + .I3(\timer2[7]_i_8_n_0 ), + .O(\timer2[4]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT5 #( + .INIT(32'h55555556)) + \timer2[4]_i_6 + (.I0(\u5/timer2 [4]), + .I1(\u5/timer2 [3]), + .I2(\u5/timer2 [0]), + .I3(\u5/timer2 [1]), + .I4(\u5/timer2 [2]), + .O(\timer2[4]_i_6_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) + \timer2[5]_i_1 + (.I0(\timer2[8]_i_4_n_0 ), + .I1(\timer2[5]_i_2_n_0 ), + .I2(\timer2[5]_i_3_n_0 ), + .I3(\timer2[5]_i_4_n_0 ), + .I4(\timer2[5]_i_5_n_0 ), + .I5(\timer2[8]_i_9_n_0 ), + .O(\timer2[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h7D007D7DFFFFFFFF)) + \timer2[5]_i_2 + (.I0(\timer2[8]_i_11_n_0 ), + .I1(\timer2[5]_i_6_n_0 ), + .I2(\u5/timer2 [5]), + .I3(\timer[4]_i_3_n_0 ), + .I4(\timer2[8]_i_5_n_0 ), + .I5(\timer2[7]_i_3_n_0 ), + .O(\timer2[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000008000000000)) + \timer2[5]_i_3 + (.I0(\u5/state [5]), + .I1(\u5/state [1]), + .I2(\FSM_sequential_state[5]_i_7_n_0 ), + .I3(\u5/state [2]), + .I4(\u5/state [6]), + .I5(\u5/state [0]), + .O(\timer2[5]_i_3_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer2[5]_i_4 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[25]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[25] ), + .O(\timer2[5]_i_4_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer2[5]_i_5 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[21]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[21] ), + .O(\timer2[5]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT5 #( + .INIT(32'hFFFFFFFE)) + \timer2[5]_i_6 + (.I0(\u5/timer2 [4]), + .I1(\u5/timer2 [3]), + .I2(\u5/timer2 [0]), + .I3(\u5/timer2 [1]), + .I4(\u5/timer2 [2]), + .O(\timer2[5]_i_6_n_0 )); + LUT6 #( + .INIT(64'hFFFEEEFEAAAAAAAA)) + \timer2[6]_i_1 + (.I0(\timer2[6]_i_2_n_0 ), + .I1(\timer2[6]_i_3_n_0 ), + .I2(sp_tms[22]), + .I3(\timer2[6]_i_4_n_0 ), + .I4(\u0/tms_reg_n_0_[22] ), + .I5(\timer2[8]_i_9_n_0 ), + .O(\timer2[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0880AAAA08800880)) + \timer2[6]_i_2 + (.I0(\timer2[8]_i_7_n_0 ), + .I1(\timer2[8]_i_11_n_0 ), + .I2(\timer2[8]_i_10_n_0 ), + .I3(\u5/timer2 [6]), + .I4(\timer[5]_i_3_n_0 ), + .I5(\timer2[8]_i_5_n_0 ), + .O(\timer2[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFAAAA0200)) + \timer2[6]_i_3 + (.I0(rfr_ack_r_i_7_n_0), + .I1(rfr_ack_r_i_6_n_0), + .I2(rfr_ack_r_i_5_n_0), + .I3(rfr_ack_r_i_4_n_0), + .I4(\timer2[6]_i_5_n_0 ), + .I5(\timer2[6]_i_6_n_0 ), + .O(\timer2[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'h5555444555445555)) + \timer2[6]_i_4 + (.I0(lmr_ack), + .I1(lmr_ack_i_3_n_0), + .I2(\u5/state [0]), + .I3(\u5/state [1]), + .I4(\u5/state [3]), + .I5(\u5/state [2]), + .O(\timer2[6]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT5 #( + .INIT(32'h00800000)) + \timer2[6]_i_5 + (.I0(\u5/state [1]), + .I1(\u5/state [3]), + .I2(\u5/state [0]), + .I3(\u5/state [4]), + .I4(\u5/state [2]), + .O(\timer2[6]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'hEF)) + \timer2[6]_i_6 + (.I0(susp_sel), + .I1(rfr_ack), + .I2(mc_c_oe_d), + .O(\timer2[6]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT5 #( + .INIT(32'h40FF4040)) + \timer2[7]_i_1 + (.I0(\timer2[7]_i_2_n_0 ), + .I1(\timer2[8]_i_4_n_0 ), + .I2(\timer2[7]_i_3_n_0 ), + .I3(\timer2[7]_i_4_n_0 ), + .I4(\timer2[8]_i_9_n_0 ), + .O(\timer2[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0DD00D0DDDDDDDDD)) + \timer2[7]_i_2 + (.I0(\timer2[8]_i_5_n_0 ), + .I1(\timer[6]_i_2_n_0 ), + .I2(\u5/timer2 [7]), + .I3(\u5/timer2 [6]), + .I4(\timer2[8]_i_10_n_0 ), + .I5(\timer2[8]_i_11_n_0 ), + .O(\timer2[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAA8AAAAAAAAAAAAA)) + \timer2[7]_i_3 + (.I0(\timer2[7]_i_5_n_0 ), + .I1(\u5/state [6]), + .I2(\u5/state [5]), + .I3(\u5/state [4]), + .I4(\timer2[7]_i_6_n_0 ), + .I5(\timer2[7]_i_7_n_0 ), + .O(\timer2[7]_i_3_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer2[7]_i_4 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[23]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[23] ), + .O(\timer2[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT4 #( + .INIT(16'h00FD)) + \timer2[7]_i_5 + (.I0(\u5/tmr2_done ), + .I1(\u5/state [3]), + .I2(\timer2[7]_i_8_n_0 ), + .I3(\timer2[3]_i_6_n_0 ), + .O(\timer2[7]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT2 #( + .INIT(4'h2)) + \timer2[7]_i_6 + (.I0(\u5/state [1]), + .I1(\u5/state [2]), + .O(\timer2[7]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT2 #( + .INIT(4'h2)) + \timer2[7]_i_7 + (.I0(\u5/state [0]), + .I1(\u5/state [3]), + .O(\timer2[7]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFFFF)) + \timer2[7]_i_8 + (.I0(\u5/state [1]), + .I1(\u5/state [6]), + .I2(\u5/state [2]), + .I3(\u5/state [0]), + .I4(\u5/state [5]), + .I5(\u5/state [4]), + .O(\timer2[7]_i_8_n_0 )); + LUT2 #( + .INIT(4'hB)) + \timer2[8]_i_1 + (.I0(\timer2[8]_i_3_n_0 ), + .I1(\timer2[8]_i_4_n_0 ), + .O(\u5/timer20 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \timer2[8]_i_10 + (.I0(\u5/timer2 [5]), + .I1(\u5/timer2 [2]), + .I2(\u5/timer2 [1]), + .I3(\u5/timer2 [0]), + .I4(\u5/timer2 [3]), + .I5(\u5/timer2 [4]), + .O(\timer2[8]_i_10_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF43FFFFFF)) + \timer2[8]_i_11 + (.I0(\u5/state [1]), + .I1(\u5/state [2]), + .I2(\u5/state [3]), + .I3(mem_ack_r_i_10_n_0), + .I4(\u5/state [5]), + .I5(\u5/state [6]), + .O(\timer2[8]_i_11_n_0 )); + LUT6 #( + .INIT(64'hFEFFFFFFFFFFFFEF)) + \timer2[8]_i_12 + (.I0(\u5/state [6]), + .I1(\burst_cnt[10]_i_9_n_0 ), + .I2(\u5/state [0]), + .I3(\u5/state [3]), + .I4(\u5/state [4]), + .I5(\u5/state [5]), + .O(\timer2[8]_i_12_n_0 )); + LUT6 #( + .INIT(64'hF200FFFFF200F200)) + \timer2[8]_i_2 + (.I0(\timer2[8]_i_5_n_0 ), + .I1(\timer[7]_i_8_n_0 ), + .I2(\timer2[8]_i_6_n_0 ), + .I3(\timer2[8]_i_7_n_0 ), + .I4(\timer2[8]_i_8_n_0 ), + .I5(\timer2[8]_i_9_n_0 ), + .O(\timer2[8]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFBFFFFFFFFFFFF)) + \timer2[8]_i_3 + (.I0(\u5/timer2 [6]), + .I1(\timer2[8]_i_10_n_0 ), + .I2(\u5/timer2 [7]), + .I3(\u5/timer2 [8]), + .I4(\timer2[7]_i_3_n_0 ), + .I5(\timer2[8]_i_11_n_0 ), + .O(\timer2[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hDDDDDDDD0DCCDDDD)) + \timer2[8]_i_4 + (.I0(\u5/state [4]), + .I1(\timer2[8]_i_12_n_0 ), + .I2(\u5/burst_cnt_ld ), + .I3(\mc_addr[23]_i_3_n_0 ), + .I4(\mc_addr[14]_i_4_n_0 ), + .I5(\mc_addr[14]_i_2_n_0 ), + .O(\timer2[8]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0000000400040000)) + \timer2[8]_i_5 + (.I0(\u5/state [6]), + .I1(\u5/state [5]), + .I2(\u5/state [0]), + .I3(\u5/state [4]), + .I4(\u5/state [3]), + .I5(\u5/state [2]), + .O(\timer2[8]_i_5_n_0 )); + LUT5 #( + .INIT(32'hAA8A0020)) + \timer2[8]_i_6 + (.I0(\timer2[8]_i_11_n_0 ), + .I1(\u5/timer2 [6]), + .I2(\timer2[8]_i_10_n_0 ), + .I3(\u5/timer2 [7]), + .I4(\u5/timer2 [8]), + .O(\timer2[8]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT2 #( + .INIT(4'h8)) + \timer2[8]_i_7 + (.I0(\timer2[8]_i_4_n_0 ), + .I1(\timer2[7]_i_3_n_0 ), + .O(\timer2[8]_i_7_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer2[8]_i_8 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[24]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[24] ), + .O(\timer2[8]_i_8_n_0 )); + LUT6 #( + .INIT(64'h1D00000000000000)) + \timer2[8]_i_9 + (.I0(sp_csc[3]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(csc[3]), + .I3(\mc_addr[14]_i_4_n_0 ), + .I4(\mc_addr[23]_i_3_n_0 ), + .I5(\u5/burst_cnt_ld ), + .O(\timer2[8]_i_9_n_0 )); + LUT5 #( + .INIT(32'hFFFFB080)) + \timer[0]_i_1 + (.I0(\timer[0]_i_2_n_0 ), + .I1(\timer[7]_i_7_n_0 ), + .I2(\timer[7]_i_5_n_0 ), + .I3(\timer[0]_i_3_n_0 ), + .I4(\timer[0]_i_4_n_0 ), + .O(\timer[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h07FF0700)) + \timer[0]_i_2 + (.I0(\timer[7]_i_11_n_0 ), + .I1(\u5/timer [0]), + .I2(\timer[0]_i_5_n_0 ), + .I3(\timer[2]_i_4_n_0 ), + .I4(\timer[0]_i_6_n_0 ), + .O(\timer[0]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFEAE)) + \timer[0]_i_3 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[0]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[0] ), + .O(\timer[0]_i_3_n_0 )); + LUT4 #( + .INIT(16'h4F44)) + \timer[0]_i_4 + (.I0(\timer[0]_i_7_n_0 ), + .I1(\timer[7]_i_12_n_0 ), + .I2(\timer[0]_i_8_n_0 ), + .I3(\timer[3]_i_11_n_0 ), + .O(\timer[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'hDDD088D0000088D0)) + \timer[0]_i_5 + (.I0(\timer[0]_i_9_n_0 ), + .I1(\timer[4]_i_3_n_0 ), + .I2(\timer2[1]_i_5_n_0 ), + .I3(\timer[2]_i_18_n_0 ), + .I4(\timer[3]_i_8_n_0 ), + .I5(\timer2[8]_i_8_n_0 ), + .O(\timer[0]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFB800000047FFFF)) + \timer[0]_i_6 + (.I0(\u0/tms_reg_n_0_[15] ), + .I1(\timer2[6]_i_4_n_0 ), + .I2(sp_tms[15]), + .I3(\timer2[6]_i_3_n_0 ), + .I4(\timer[2]_i_10_n_0 ), + .I5(\timer2[4]_i_4_n_0 ), + .O(\timer[0]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT4 #( + .INIT(16'h0151)) + \timer[0]_i_7 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[8]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[8] ), + .O(\timer[0]_i_7_n_0 )); + LUT4 #( + .INIT(16'h001D)) + \timer[0]_i_8 + (.I0(sp_tms[12]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(\u0/tms_reg_n_0_[12] ), + .I3(\timer2[6]_i_3_n_0 ), + .O(\timer[0]_i_8_n_0 )); + LUT6 #( + .INIT(64'h0000000004000000)) + \timer[0]_i_9 + (.I0(\u5/state [6]), + .I1(\u5/state [0]), + .I2(\u5/state [5]), + .I3(\u5/state [3]), + .I4(\u5/state [4]), + .I5(\burst_cnt[10]_i_9_n_0 ), + .O(\timer[0]_i_9_n_0 )); + LUT5 #( + .INIT(32'hFFFFA820)) + \timer[1]_i_1 + (.I0(\timer[7]_i_5_n_0 ), + .I1(\timer[7]_i_7_n_0 ), + .I2(\timer[1]_i_2_n_0 ), + .I3(\timer[1]_i_3_n_0 ), + .I4(\timer[1]_i_4_n_0 ), + .O(\timer[1]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFFE2)) + \timer[1]_i_2 + (.I0(sp_tms[1]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(\u0/tms_reg_n_0_[1] ), + .I3(\timer2[6]_i_3_n_0 ), + .O(\timer[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h9999F0006666FF0F)) + \timer[1]_i_3 + (.I0(\timer[1]_i_5_n_0 ), + .I1(\timer2[0]_i_4_n_0 ), + .I2(\timer[2]_i_9_n_0 ), + .I3(\timer[1]_i_6_n_0 ), + .I4(\timer[2]_i_10_n_0 ), + .I5(\timer2[5]_i_5_n_0 ), + .O(\timer[1]_i_3_n_0 )); + LUT4 #( + .INIT(16'h4F44)) + \timer[1]_i_4 + (.I0(\timer[1]_i_7_n_0 ), + .I1(\timer[7]_i_12_n_0 ), + .I2(\timer[1]_i_8_n_0 ), + .I3(\timer[3]_i_11_n_0 ), + .O(\timer[1]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFA0CCA000)) + \timer[1]_i_5 + (.I0(\u0/tms_reg_n_0_[15] ), + .I1(sp_tms[15]), + .I2(\u0/tms_reg_n_0_[20] ), + .I3(\timer2[6]_i_4_n_0 ), + .I4(sp_tms[20]), + .I5(\timer2[6]_i_3_n_0 ), + .O(\timer[1]_i_5_n_0 )); + LUT4 #( + .INIT(16'h82AA)) + \timer[1]_i_6 + (.I0(\timer[1]_i_9_n_0 ), + .I1(\u5/timer [1]), + .I2(\u5/timer [0]), + .I3(\timer[7]_i_11_n_0 ), + .O(\timer[1]_i_6_n_0 )); + LUT4 #( + .INIT(16'h001D)) + \timer[1]_i_7 + (.I0(sp_tms[9]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(\u0/tms_reg_n_0_[9] ), + .I3(\timer2[6]_i_3_n_0 ), + .O(\timer[1]_i_7_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer[1]_i_8 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[13]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[13] ), + .O(\timer[1]_i_8_n_0 )); + LUT6 #( + .INIT(64'h27F727F7FFFF22F2)) + \timer[1]_i_9 + (.I0(\timer[0]_i_9_n_0 ), + .I1(\timer[5]_i_3_n_0 ), + .I2(\timer[3]_i_8_n_0 ), + .I3(\timer2[5]_i_4_n_0 ), + .I4(\timer2[2]_i_2_n_0 ), + .I5(\timer[2]_i_18_n_0 ), + .O(\timer[1]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF040E0E0E)) + \timer[2]_i_1 + (.I0(\timer[7]_i_7_n_0 ), + .I1(\timer[2]_i_2_n_0 ), + .I2(\timer[2]_i_3_n_0 ), + .I3(\timer[2]_i_4_n_0 ), + .I4(\timer[2]_i_5_n_0 ), + .I5(\timer[2]_i_6_n_0 ), + .O(\timer[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000101000)) + \timer[2]_i_10 + (.I0(cke_r_i_5_n_0), + .I1(\u5/state [5]), + .I2(\u5/state [4]), + .I3(\u5/state [3]), + .I4(\u5/state [2]), + .I5(\u5/state [6]), + .O(\timer[2]_i_10_n_0 )); + LUT6 #( + .INIT(64'h0000000000000004)) + \timer[2]_i_11 + (.I0(\u5/state [2]), + .I1(\u5/state [4]), + .I2(\u5/state [3]), + .I3(\u5/state [6]), + .I4(\u5/state [5]), + .I5(\u5/state [1]), + .O(\timer[2]_i_11_n_0 )); + LUT6 #( + .INIT(64'h01000000FFFFFFFF)) + \timer[2]_i_12 + (.I0(\u5/state [4]), + .I1(\u5/state [3]), + .I2(\burst_cnt[10]_i_9_n_0 ), + .I3(\u5/state [6]), + .I4(\timer[2]_i_17_n_0 ), + .I5(\timer[7]_i_17_n_0 ), + .O(\timer[2]_i_12_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF55544454)) + \timer[2]_i_13 + (.I0(\timer[2]_i_18_n_0 ), + .I1(\timer2[6]_i_3_n_0 ), + .I2(sp_tms[19]), + .I3(\timer2[6]_i_4_n_0 ), + .I4(\u0/tms_reg_n_0_[19] ), + .I5(\timer[2]_i_19_n_0 ), + .O(\timer[2]_i_13_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT4 #( + .INIT(16'h001D)) + \timer[2]_i_14 + (.I0(sp_tms[10]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(\u0/tms_reg_n_0_[10] ), + .I3(\timer2[6]_i_3_n_0 ), + .O(\timer[2]_i_14_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer[2]_i_15 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[14]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[14] ), + .O(\timer[2]_i_15_n_0 )); + LUT6 #( + .INIT(64'hF7AF77AFF7AFF7AF)) + \timer[2]_i_16 + (.I0(\u5/state [4]), + .I1(\u5/state [3]), + .I2(\u5/state [1]), + .I3(\u5/state [2]), + .I4(ap_en_i_2_n_0), + .I5(\u5/tmr_done ), + .O(\timer[2]_i_16_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT2 #( + .INIT(4'h1)) + \timer[2]_i_17 + (.I0(\u5/state [5]), + .I1(\u5/state [0]), + .O(\timer[2]_i_17_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT5 #( + .INIT(32'hFDFFFFFF)) + \timer[2]_i_18 + (.I0(\u5/state [4]), + .I1(\u5/state [1]), + .I2(\u5/wb_wait_r ), + .I3(\u5/state [2]), + .I4(\ir_cnt[3]_i_4_n_0 ), + .O(\timer[2]_i_18_n_0 )); + LUT5 #( + .INIT(32'hAAAA8A80)) + \timer[2]_i_19 + (.I0(\timer[3]_i_8_n_0 ), + .I1(\u0/tms_reg_n_0_[26] ), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_tms[26]), + .I4(\timer2[6]_i_3_n_0 ), + .O(\timer[2]_i_19_n_0 )); + LUT4 #( + .INIT(16'hFFE2)) + \timer[2]_i_2 + (.I0(sp_tms[2]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(\u0/tms_reg_n_0_[2] ), + .I3(\timer2[6]_i_3_n_0 ), + .O(\timer[2]_i_2_n_0 )); + LUT4 #( + .INIT(16'h5D7D)) + \timer[2]_i_3 + (.I0(\timer[7]_i_5_n_0 ), + .I1(\timer[2]_i_7_n_0 ), + .I2(\timer[2]_i_8_n_0 ), + .I3(\timer[2]_i_4_n_0 ), + .O(\timer[2]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'h2)) + \timer[2]_i_4 + (.I0(\timer[2]_i_9_n_0 ), + .I1(\timer[2]_i_10_n_0 ), + .O(\timer[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFF0154)) + \timer[2]_i_5 + (.I0(\timer[2]_i_11_n_0 ), + .I1(\u5/timer [1]), + .I2(\u5/timer [0]), + .I3(\u5/timer [2]), + .I4(\timer[2]_i_12_n_0 ), + .I5(\timer[2]_i_13_n_0 ), + .O(\timer[2]_i_5_n_0 )); + LUT4 #( + .INIT(16'h4F44)) + \timer[2]_i_6 + (.I0(\timer[2]_i_14_n_0 ), + .I1(\timer[7]_i_12_n_0 ), + .I2(\timer[2]_i_15_n_0 ), + .I3(\timer[3]_i_11_n_0 ), + .O(\timer[2]_i_6_n_0 )); + LUT4 #( + .INIT(16'h088A)) + \timer[2]_i_7 + (.I0(\timer[2]_i_10_n_0 ), + .I1(\timer[1]_i_5_n_0 ), + .I2(\timer2[0]_i_4_n_0 ), + .I3(\timer2[5]_i_5_n_0 ), + .O(\timer[2]_i_7_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer[2]_i_8 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[22]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[22] ), + .O(\timer[2]_i_8_n_0 )); + LUT6 #( + .INIT(64'hEEEEE2EEFFFFFFFF)) + \timer[2]_i_9 + (.I0(\timer[2]_i_16_n_0 ), + .I1(\u5/state [0]), + .I2(\u5/state [4]), + .I3(\u5/state [2]), + .I4(\u5/state [1]), + .I5(rfr_ack_r_i_7_n_0), + .O(\timer[2]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFD50000)) + \timer[3]_i_1 + (.I0(\timer[3]_i_2_n_0 ), + .I1(\timer[7]_i_3_n_0 ), + .I2(\timer[3]_i_3_n_0 ), + .I3(\timer[3]_i_4_n_0 ), + .I4(\timer[7]_i_5_n_0 ), + .I5(\timer[3]_i_5_n_0 ), + .O(\timer[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'h0151)) + \timer[3]_i_10 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[15]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[15] ), + .O(\timer[3]_i_10_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFF0008)) + \timer[3]_i_11 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(\FSM_sequential_state[5]_i_8_n_0 ), + .I2(\timer[3]_i_12_n_0 ), + .I3(\FSM_sequential_state[5]_i_9_n_0 ), + .I4(\timer[3]_i_13_n_0 ), + .I5(\timer[7]_i_13_n_0 ), + .O(\timer[3]_i_11_n_0 )); + LUT6 #( + .INIT(64'h5D5D5DFFFFFF5DFF)) + \timer[3]_i_12 + (.I0(wb_write_go), + .I1(wb_cyc_i), + .I2(wb_stb_i), + .I3(sp_csc[1]), + .I4(\timer2[6]_i_4_n_0 ), + .I5(csc[1]), + .O(\timer[3]_i_12_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT2 #( + .INIT(4'h8)) + \timer[3]_i_13 + (.I0(\u5/state [5]), + .I1(\u5/state [3]), + .O(\timer[3]_i_13_n_0 )); + LUT6 #( + .INIT(64'hBBBBAABA8888AA8A)) + \timer[3]_i_2 + (.I0(\timer[3]_i_6_n_0 ), + .I1(\timer[7]_i_9_n_0 ), + .I2(\mc_addr[23]_i_3_n_0 ), + .I3(\timer[7]_i_10_n_0 ), + .I4(\u5/state [4]), + .I5(\timer[3]_i_7_n_0 ), + .O(\timer[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT4 #( + .INIT(16'hAAA9)) + \timer[3]_i_3 + (.I0(\u5/timer [3]), + .I1(\u5/timer [2]), + .I2(\u5/timer [1]), + .I3(\u5/timer [0]), + .O(\timer[3]_i_3_n_0 )); + LUT5 #( + .INIT(32'hAAAA8A80)) + \timer[3]_i_4 + (.I0(\timer[3]_i_8_n_0 ), + .I1(\u0/tms_reg_n_0_[27] ), + .I2(\timer2[6]_i_4_n_0 ), + .I3(sp_tms[27]), + .I4(\timer2[6]_i_3_n_0 ), + .O(\timer[3]_i_4_n_0 )); + LUT4 #( + .INIT(16'h4F44)) + \timer[3]_i_5 + (.I0(\timer[3]_i_9_n_0 ), + .I1(\timer[7]_i_12_n_0 ), + .I2(\timer[3]_i_10_n_0 ), + .I3(\timer[3]_i_11_n_0 ), + .O(\timer[3]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT5 #( + .INIT(32'hF4F40FF4)) + \timer[3]_i_6 + (.I0(\timer[2]_i_10_n_0 ), + .I1(\timer[2]_i_9_n_0 ), + .I2(\timer2[7]_i_4_n_0 ), + .I3(\timer[2]_i_7_n_0 ), + .I4(\timer[2]_i_8_n_0 ), + .O(\timer[3]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT4 #( + .INIT(16'h0151)) + \timer[3]_i_7 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[3]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[3] ), + .O(\timer[3]_i_7_n_0 )); + LUT6 #( + .INIT(64'h0000080012008000)) + \timer[3]_i_8 + (.I0(\u5/state [0]), + .I1(\u5/state [1]), + .I2(\u5/state [2]), + .I3(rfr_ack_r_i_7_n_0), + .I4(\u5/state [3]), + .I5(\u5/state [4]), + .O(\timer[3]_i_8_n_0 )); + LUT4 #( + .INIT(16'h001D)) + \timer[3]_i_9 + (.I0(sp_tms[11]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(\u0/tms_reg_n_0_[11] ), + .I3(\timer2[6]_i_3_n_0 ), + .O(\timer[3]_i_9_n_0 )); + LUT6 #( + .INIT(64'h088008800880AAAA)) + \timer[4]_i_1 + (.I0(\timer[7]_i_5_n_0 ), + .I1(\timer[7]_i_3_n_0 ), + .I2(\timer[4]_i_2_n_0 ), + .I3(\u5/timer [4]), + .I4(\timer[7]_i_7_n_0 ), + .I5(\timer[4]_i_3_n_0 ), + .O(\timer[4]_i_1_n_0 )); + LUT4 #( + .INIT(16'h0001)) + \timer[4]_i_2 + (.I0(\u5/timer [2]), + .I1(\u5/timer [1]), + .I2(\u5/timer [0]), + .I3(\u5/timer [3]), + .O(\timer[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT4 #( + .INIT(16'h001D)) + \timer[4]_i_3 + (.I0(sp_tms[4]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(\u0/tms_reg_n_0_[4] ), + .I3(\timer2[6]_i_3_n_0 ), + .O(\timer[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'h088008800880AAAA)) + \timer[5]_i_1 + (.I0(\timer[7]_i_5_n_0 ), + .I1(\timer[7]_i_3_n_0 ), + .I2(\timer[5]_i_2_n_0 ), + .I3(\u5/timer [5]), + .I4(\timer[7]_i_7_n_0 ), + .I5(\timer[5]_i_3_n_0 ), + .O(\timer[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT5 #( + .INIT(32'h00000001)) + \timer[5]_i_2 + (.I0(\u5/timer [3]), + .I1(\u5/timer [0]), + .I2(\u5/timer [1]), + .I3(\u5/timer [2]), + .I4(\u5/timer [4]), + .O(\timer[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT4 #( + .INIT(16'h0151)) + \timer[5]_i_3 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[5]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[5] ), + .O(\timer[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'h088008800880AAAA)) + \timer[6]_i_1 + (.I0(\timer[7]_i_5_n_0 ), + .I1(\timer[7]_i_3_n_0 ), + .I2(\timer[7]_i_4_n_0 ), + .I3(\u5/timer [6]), + .I4(\timer[7]_i_7_n_0 ), + .I5(\timer[6]_i_2_n_0 ), + .O(\timer[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT4 #( + .INIT(16'h0151)) + \timer[6]_i_2 + (.I0(\timer2[6]_i_3_n_0 ), + .I1(sp_tms[6]), + .I2(\timer2[6]_i_4_n_0 ), + .I3(\u0/tms_reg_n_0_[6] ), + .O(\timer[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'h77777577FFFFFFFF)) + \timer[7]_i_1 + (.I0(\timer[7]_i_3_n_0 ), + .I1(\u5/mc_le ), + .I2(\u5/timer [7]), + .I3(\timer[7]_i_4_n_0 ), + .I4(\u5/timer [6]), + .I5(\timer[7]_i_5_n_0 ), + .O(\timer[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFBFBBFFFFFFFF)) + \timer[7]_i_10 + (.I0(wb_write_go), + .I1(\mc_addr[14]_i_4_n_0 ), + .I2(wb_stb_i), + .I3(wb_cyc_i), + .I4(\FSM_sequential_state[5]_i_9_n_0 ), + .I5(\FSM_sequential_state[5]_i_8_n_0 ), + .O(\timer[7]_i_10_n_0 )); + LUT6 #( + .INIT(64'h4440444444444444)) + \timer[7]_i_11 + (.I0(\timer[2]_i_11_n_0 ), + .I1(\timer[7]_i_17_n_0 ), + .I2(\u5/state [5]), + .I3(\u5/state [0]), + .I4(\u5/state [6]), + .I5(\timer[7]_i_18_n_0 ), + .O(\timer[7]_i_11_n_0 )); + LUT6 #( + .INIT(64'h8000800080000000)) + \timer[7]_i_12 + (.I0(\timer[7]_i_16_n_0 ), + .I1(\u5/state [5]), + .I2(\u5/state [4]), + .I3(\u5/state [1]), + .I4(\u5/tmr_done ), + .I5(\u5/state [0]), + .O(\timer[7]_i_12_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT5 #( + .INIT(32'hFFFFFFBE)) + \timer[7]_i_13 + (.I0(\FSM_sequential_state[5]_i_3_n_0 ), + .I1(\u5/state [5]), + .I2(\u5/state [3]), + .I3(\u5/state [6]), + .I4(\u5/state [4]), + .O(\timer[7]_i_13_n_0 )); + LUT6 #( + .INIT(64'h8A00000000000000)) + \timer[7]_i_14 + (.I0(\mc_addr[14]_i_4_n_0 ), + .I1(wb_stb_i), + .I2(wb_cyc_i), + .I3(wb_write_go), + .I4(\FSM_sequential_state[5]_i_8_n_0 ), + .I5(\mc_addr[23]_i_3_n_0 ), + .O(\timer[7]_i_14_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'hB)) + \timer[7]_i_15 + (.I0(\u5/state [1]), + .I1(\u5/state [0]), + .O(\timer[7]_i_15_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'h01)) + \timer[7]_i_16 + (.I0(\u5/state [6]), + .I1(\u5/state [2]), + .I2(\u5/state [3]), + .O(\timer[7]_i_16_n_0 )); + LUT3 #( + .INIT(8'h04)) + \timer[7]_i_17 + (.I0(\timer[0]_i_9_n_0 ), + .I1(\timer[2]_i_18_n_0 ), + .I2(\timer[3]_i_8_n_0 ), + .O(\timer[7]_i_17_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT4 #( + .INIT(16'h0001)) + \timer[7]_i_18 + (.I0(\u5/state [4]), + .I1(\u5/state [3]), + .I2(\u5/state [1]), + .I3(\u5/state [2]), + .O(\timer[7]_i_18_n_0 )); + LUT6 #( + .INIT(64'h088008800880AAAA)) + \timer[7]_i_2 + (.I0(\timer[7]_i_5_n_0 ), + .I1(\timer[7]_i_3_n_0 ), + .I2(\timer[7]_i_6_n_0 ), + .I3(\u5/timer [7]), + .I4(\timer[7]_i_7_n_0 ), + .I5(\timer[7]_i_8_n_0 ), + .O(\timer[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h8888AA8A00000000)) + \timer[7]_i_3 + (.I0(\timer[2]_i_4_n_0 ), + .I1(\timer[7]_i_9_n_0 ), + .I2(\mc_addr[23]_i_3_n_0 ), + .I3(\timer[7]_i_10_n_0 ), + .I4(\u5/state [4]), + .I5(\timer[7]_i_11_n_0 ), + .O(\timer[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \timer[7]_i_4 + (.I0(\u5/timer [4]), + .I1(\u5/timer [2]), + .I2(\u5/timer [1]), + .I3(\u5/timer [0]), + .I4(\u5/timer [3]), + .I5(\u5/timer [5]), + .O(\timer[7]_i_4_n_0 )); + LUT6 #( + .INIT(64'h4555444445554555)) + \timer[7]_i_5 + (.I0(\timer[7]_i_12_n_0 ), + .I1(\timer[7]_i_13_n_0 ), + .I2(\u5/state [3]), + .I3(\u5/state [5]), + .I4(\FSM_sequential_state[5]_i_9_n_0 ), + .I5(\timer[7]_i_14_n_0 ), + .O(\timer[7]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT2 #( + .INIT(4'h2)) + \timer[7]_i_6 + (.I0(\timer[7]_i_4_n_0 ), + .I1(\u5/timer [6]), + .O(\timer[7]_i_6_n_0 )); + LUT6 #( + .INIT(64'hDFDFDFDFFFFFEFFF)) + \timer[7]_i_7 + (.I0(\u5/state [5]), + .I1(\timer[7]_i_15_n_0 ), + .I2(\timer[7]_i_16_n_0 ), + .I3(\mc_addr[23]_i_3_n_0 ), + .I4(\timer[7]_i_10_n_0 ), + .I5(\u5/state [4]), + .O(\timer[7]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT4 #( + .INIT(16'h001D)) + \timer[7]_i_8 + (.I0(sp_tms[7]), + .I1(\timer2[6]_i_4_n_0 ), + .I2(\u0/tms_reg_n_0_[7] ), + .I3(\timer2[6]_i_3_n_0 ), + .O(\timer[7]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFFFFFFFFFE)) + \timer[7]_i_9 + (.I0(\u5/state [6]), + .I1(\u5/state [2]), + .I2(\u5/state [3]), + .I3(\timer[7]_i_15_n_0 ), + .I4(\u5/state [4]), + .I5(\u5/state [5]), + .O(\timer[7]_i_9_n_0 )); + LUT2 #( + .INIT(4'h1)) + tmr2_done_i_1 + (.I0(\timer2[8]_i_9_n_0 ), + .I1(\timer2[8]_i_3_n_0 ), + .O(\u5/tmr2_done0 )); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT3 #( + .INIT(8'h04)) + tmr_done_i_1 + (.I0(\u5/timer [6]), + .I1(\timer[7]_i_4_n_0 ), + .I2(\u5/timer [7]), + .O(\u5/timer_is_zero )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[0]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[0]), + .I4(\u0/u1/tms_reg_n_0_[0] ), + .I5(\u0/sel0 ), + .O(\tms[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[10]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[10]), + .I4(\u0/u1/tms_reg_n_0_[10] ), + .I5(\u0/sel0 ), + .O(\tms[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[11]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[11]), + .I4(\u0/u1/tms_reg_n_0_[11] ), + .I5(\u0/sel0 ), + .O(\tms[11]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[12]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[12]), + .I4(\u0/u1/tms_reg_n_0_[12] ), + .I5(\u0/sel0 ), + .O(\tms[12]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[13]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[13]), + .I4(\u0/u1/tms_reg_n_0_[13] ), + .I5(\u0/sel0 ), + .O(\tms[13]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[14]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[14]), + .I4(\u0/u1/tms_reg_n_0_[14] ), + .I5(\u0/sel0 ), + .O(\tms[14]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[15]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[15]), + .I4(\u0/u1/tms_reg_n_0_[15] ), + .I5(\u0/sel0 ), + .O(\tms[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[16]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[16]), + .I4(\u0/u1/tms_reg_n_0_[16] ), + .I5(\u0/sel0 ), + .O(\tms[16]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[17]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[17]), + .I4(\u0/u1/tms_reg_n_0_[17] ), + .I5(\u0/sel0 ), + .O(\tms[17]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[18]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[18]), + .I4(\u0/u1/tms_reg_n_0_[18] ), + .I5(\u0/sel0 ), + .O(\tms[18]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[19]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[19]), + .I4(\u0/u1/tms_reg_n_0_[19] ), + .I5(\u0/sel0 ), + .O(\tms[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[1]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[1]), + .I4(\u0/u1/tms_reg_n_0_[1] ), + .I5(\u0/sel0 ), + .O(\tms[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[20]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[20]), + .I4(\u0/u1/tms_reg_n_0_[20] ), + .I5(\u0/sel0 ), + .O(\tms[20]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[21]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[21]), + .I4(\u0/u1/tms_reg_n_0_[21] ), + .I5(\u0/sel0 ), + .O(\tms[21]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[22]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[22]), + .I4(\u0/u1/tms_reg_n_0_[22] ), + .I5(\u0/sel0 ), + .O(\tms[22]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[23]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[23]), + .I4(\u0/u1/tms_reg_n_0_[23] ), + .I5(\u0/sel0 ), + .O(\tms[23]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[24]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[24]), + .I4(\u0/u1/tms_reg_n_0_[24] ), + .I5(\u0/sel0 ), + .O(\tms[24]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[25]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[25]), + .I4(\u0/u1/tms_reg_n_0_[25] ), + .I5(\u0/sel0 ), + .O(\tms[25]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[26]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[26]), + .I4(\u0/u1/tms_reg_n_0_[26] ), + .I5(\u0/sel0 ), + .O(\tms[26]_i_1_n_0 )); + LUT4 #( + .INIT(16'h8880)) + \tms[27]_i_1 + (.I0(wb_cyc_i), + .I1(wb_stb_i), + .I2(cs_le_d), + .I3(\u0/rf_we ), + .O(\tms[27]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[27]_i_2 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[27]), + .I4(\u0/u1/tms_reg_n_0_[27] ), + .I5(\u0/sel0 ), + .O(\tms[27]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[2]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[2]), + .I4(\u0/u1/tms_reg_n_0_[2] ), + .I5(\u0/sel0 ), + .O(\tms[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[3]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[3]), + .I4(\u0/u1/tms_reg_n_0_[3] ), + .I5(\u0/sel0 ), + .O(\tms[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[4]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[4]), + .I4(\u0/u1/tms_reg_n_0_[4] ), + .I5(\u0/sel0 ), + .O(\tms[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[5]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[5]), + .I4(\u0/u1/tms_reg_n_0_[5] ), + .I5(\u0/sel0 ), + .O(\tms[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[6]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[6]), + .I4(\u0/u1/tms_reg_n_0_[6] ), + .I5(\u0/sel0 ), + .O(\tms[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[7]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[7]), + .I4(\u0/u1/tms_reg_n_0_[7] ), + .I5(\u0/sel0 ), + .O(\tms[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[8]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[8]), + .I4(\u0/u1/tms_reg_n_0_[8] ), + .I5(\u0/sel0 ), + .O(\tms[8]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFF8070007000700)) + \tms[9]_i_1 + (.I0(\u0/u0/csc_reg_n_0_[8] ), + .I1(wb_we_i), + .I2(\csc[11]_i_3_n_0 ), + .I3(tms[9]), + .I4(\u0/u1/tms_reg_n_0_[9] ), + .I5(\u0/sel0 ), + .O(\tms[9]_i_1_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \u0/cs[1]_i_1 + (.I0(\u0/sel0 ), + .I1(cs_le), + .I2(cs[1]), + .O(\u0/cs[1]_i_1_n_0 )); + FDCE \u0/cs_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\cs[0]_i_1_n_0 ), + .Q(cs[0])); + FDCE \u0/cs_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u0/cs[1]_i_1_n_0 ), + .Q(cs[1])); + FDPE \u0/csc_mask_r_reg[0] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[0]), + .PRE(rst_i), + .Q(\u0/csc_mask [0])); + FDPE \u0/csc_mask_r_reg[10] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[10]), + .PRE(rst_i), + .Q(\u0/csc_mask_r_reg_n_0_[10] )); + FDPE \u0/csc_mask_r_reg[1] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[1]), + .PRE(rst_i), + .Q(\u0/csc_mask [1])); + FDPE \u0/csc_mask_r_reg[2] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[2]), + .PRE(rst_i), + .Q(\u0/csc_mask [2])); + FDPE \u0/csc_mask_r_reg[3] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[3]), + .PRE(rst_i), + .Q(\u0/csc_mask [3])); + FDPE \u0/csc_mask_r_reg[4] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[4]), + .PRE(rst_i), + .Q(\u0/csc_mask [4])); + FDPE \u0/csc_mask_r_reg[5] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[5]), + .PRE(rst_i), + .Q(\u0/csc_mask [5])); + FDPE \u0/csc_mask_r_reg[6] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[6]), + .PRE(rst_i), + .Q(\u0/csc_mask [6])); + FDPE \u0/csc_mask_r_reg[7] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[7]), + .PRE(rst_i), + .Q(\u0/csc_mask [7])); + FDPE \u0/csc_mask_r_reg[8] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[8]), + .PRE(rst_i), + .Q(\u0/csc_mask_r_reg_n_0_[8] )); + FDPE \u0/csc_mask_r_reg[9] + (.C(clk_i), + .CE(\u0/csc_mask_r0 ), + .D(wb_data_i[9]), + .PRE(rst_i), + .Q(\u0/csc_mask_r_reg_n_0_[9] )); + FDCE \u0/csc_reg[10] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\csc[10]_i_1_n_0 ), + .Q(csc__0[10])); + FDCE \u0/csc_reg[11] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\csc[11]_i_2_n_0 ), + .Q(csc[11])); + FDCE \u0/csc_reg[1] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\csc[1]_i_1__0_n_0 ), + .Q(csc[1])); + FDCE \u0/csc_reg[2] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\csc[2]_i_1__0_n_0 ), + .Q(csc[2])); + FDCE \u0/csc_reg[3] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\csc[3]_i_1_n_0 ), + .Q(csc[3])); + FDCE \u0/csc_reg[4] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\csc[4]_i_1__0_n_0 ), + .Q(csc[4])); + FDCE \u0/csc_reg[5] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\csc[5]_i_1__0_n_0 ), + .Q(csc[5])); + FDCE \u0/csc_reg[6] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\csc[6]_i_1_n_0 ), + .Q(csc__0[6])); + FDCE \u0/csc_reg[7] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\csc[7]_i_1_n_0 ), + .Q(csc__0[7])); + FDCE \u0/csc_reg[9] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\csc[9]_i_1_n_0 ), + .Q(csc__0[9])); + FDCE \u0/csr_r2_reg[0] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[24]), + .Q(rfr_ps_val[0])); + FDCE \u0/csr_r2_reg[1] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[25]), + .Q(rfr_ps_val[1])); + FDCE \u0/csr_r2_reg[2] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[26]), + .Q(rfr_ps_val[2])); + FDCE \u0/csr_r2_reg[3] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[27]), + .Q(rfr_ps_val[3])); + FDCE \u0/csr_r2_reg[4] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[28]), + .Q(rfr_ps_val[4])); + FDCE \u0/csr_r2_reg[5] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[29]), + .Q(rfr_ps_val[5])); + FDCE \u0/csr_r2_reg[6] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[30]), + .Q(rfr_ps_val[6])); + FDCE \u0/csr_r2_reg[7] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[31]), + .Q(rfr_ps_val[7])); + FDRE \u0/csr_r_reg[0] + (.C(clk_i), + .CE(\ ), + .D(mc_sts_ir), + .Q(\u0/csr_r_reg_n_0_[0] ), + .R(\ )); + FDCE \u0/csr_r_reg[10] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[10]), + .Q(sel0[2])); + FDCE \u0/csr_r_reg[1] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[1]), + .Q(mc_vpen_pad_o)); + FDCE \u0/csr_r_reg[2] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[2]), + .Q(fs)); + FDCE \u0/csr_r_reg[3] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[3]), + .Q(\u0/csr_r_reg_n_0_[3] )); + FDCE \u0/csr_r_reg[4] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[4]), + .Q(\u0/csr_r_reg_n_0_[4] )); + FDCE \u0/csr_r_reg[5] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[5]), + .Q(\u0/csr_r_reg_n_0_[5] )); + FDCE \u0/csr_r_reg[6] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[6]), + .Q(\u0/csr_r_reg_n_0_[6] )); + FDCE \u0/csr_r_reg[7] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[7]), + .Q(\u0/csr_r_reg_n_0_[7] )); + FDCE \u0/csr_r_reg[8] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[8]), + .Q(sel0[0])); + FDCE \u0/csr_r_reg[9] + (.C(clk_i), + .CE(\u0/csr_r20 ), + .CLR(rst_i), + .D(wb_data_i[9]), + .Q(sel0[1])); + FDRE \u0/init_ack_r_reg + (.C(clk_i), + .CE(\ ), + .D(init_ack), + .Q(\u0/init_ack_r ), + .R(\ )); + FDCE \u0/init_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u0/init_req01_out ), + .Q(init_req)); + FDRE \u0/lmr_ack_r_reg + (.C(clk_i), + .CE(\ ), + .D(lmr_ack), + .Q(\u0/lmr_ack_r ), + .R(\ )); + FDCE \u0/lmr_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u0/lmr_req00_out ), + .Q(lmr_req)); + FDRE \u0/poc_reg[0] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[0]), + .Q(poc_o[0]), + .R(\ )); + FDRE \u0/poc_reg[10] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[10]), + .Q(poc_o[10]), + .R(\ )); + FDRE \u0/poc_reg[11] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[11]), + .Q(poc_o[11]), + .R(\ )); + FDRE \u0/poc_reg[12] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[12]), + .Q(poc_o[12]), + .R(\ )); + FDRE \u0/poc_reg[13] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[13]), + .Q(poc_o[13]), + .R(\ )); + FDRE \u0/poc_reg[14] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[14]), + .Q(poc_o[14]), + .R(\ )); + FDRE \u0/poc_reg[15] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[15]), + .Q(poc_o[15]), + .R(\ )); + FDRE \u0/poc_reg[16] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[16]), + .Q(poc_o[16]), + .R(\ )); + FDRE \u0/poc_reg[17] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[17]), + .Q(poc_o[17]), + .R(\ )); + FDRE \u0/poc_reg[18] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[18]), + .Q(poc_o[18]), + .R(\ )); + FDRE \u0/poc_reg[19] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[19]), + .Q(poc_o[19]), + .R(\ )); + FDRE \u0/poc_reg[1] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[1]), + .Q(poc_o[1]), + .R(\ )); + FDRE \u0/poc_reg[20] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[20]), + .Q(poc_o[20]), + .R(\ )); + FDRE \u0/poc_reg[21] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[21]), + .Q(poc_o[21]), + .R(\ )); + FDRE \u0/poc_reg[22] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[22]), + .Q(poc_o[22]), + .R(\ )); + FDRE \u0/poc_reg[23] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[23]), + .Q(poc_o[23]), + .R(\ )); + FDRE \u0/poc_reg[24] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[24]), + .Q(poc_o[24]), + .R(\ )); + FDRE \u0/poc_reg[25] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[25]), + .Q(poc_o[25]), + .R(\ )); + FDRE \u0/poc_reg[26] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[26]), + .Q(poc_o[26]), + .R(\ )); + FDRE \u0/poc_reg[27] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[27]), + .Q(poc_o[27]), + .R(\ )); + FDRE \u0/poc_reg[28] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[28]), + .Q(poc_o[28]), + .R(\ )); + FDRE \u0/poc_reg[29] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[29]), + .Q(poc_o[29]), + .R(\ )); + FDRE \u0/poc_reg[2] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[2]), + .Q(poc_o[2]), + .R(\ )); + FDRE \u0/poc_reg[30] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[30]), + .Q(poc_o[30]), + .R(\ )); + FDRE \u0/poc_reg[31] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[31]), + .Q(poc_o[31]), + .R(\ )); + FDRE \u0/poc_reg[3] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[3]), + .Q(poc_o[3]), + .R(\ )); + FDRE \u0/poc_reg[4] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[4]), + .Q(poc_o[4]), + .R(\ )); + FDRE \u0/poc_reg[5] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[5]), + .Q(poc_o[5]), + .R(\ )); + FDRE \u0/poc_reg[6] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[6]), + .Q(poc_o[6]), + .R(\ )); + FDRE \u0/poc_reg[7] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[7]), + .Q(poc_o[7]), + .R(\ )); + FDRE \u0/poc_reg[8] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[8]), + .Q(poc_o[8]), + .R(\ )); + FDRE \u0/poc_reg[9] + (.C(clk_i), + .CE(rst_r3), + .D(mc_data_ir[9]), + .Q(poc_o[9]), + .R(\ )); + FDCE \u0/rf_we_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u0/rf_we0 ), + .Q(\u0/rf_we )); + FDPE \u0/rst_r3_reg + (.C(clk_i), + .CE(\ ), + .D(\u0/rst_r2 ), + .PRE(rst_i), + .Q(rst_r3)); + FDCE \u0/sp_csc_reg[10] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\sp_csc[10]_i_1_n_0 ), + .Q(sp_csc[10])); + FDCE \u0/sp_csc_reg[1] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\sp_csc[1]_i_1_n_0 ), + .Q(sp_csc[1])); + FDCE \u0/sp_csc_reg[2] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\sp_csc[2]_i_1_n_0 ), + .Q(sp_csc[2])); + FDCE \u0/sp_csc_reg[3] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\sp_csc[3]_i_1_n_0 ), + .Q(sp_csc[3])); + FDCE \u0/sp_csc_reg[4] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\sp_csc[4]_i_1_n_0 ), + .Q(sp_csc[4])); + FDCE \u0/sp_csc_reg[5] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\sp_csc[5]_i_1_n_0 ), + .Q(sp_csc[5])); + FDCE \u0/sp_csc_reg[6] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\sp_csc[6]_i_1_n_0 ), + .Q(sp_csc[6])); + FDCE \u0/sp_csc_reg[7] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\sp_csc[7]_i_1_n_0 ), + .Q(sp_csc[7])); + FDCE \u0/sp_csc_reg[9] + (.C(clk_i), + .CE(\csc[11]_i_1_n_0 ), + .CLR(rst_i), + .D(\sp_csc[9]_i_1_n_0 ), + .Q(sp_csc[9])); + FDPE \u0/sp_tms_reg[0] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[0]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[0])); + FDPE \u0/sp_tms_reg[10] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[10]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[10])); + FDPE \u0/sp_tms_reg[11] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[11]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[11])); + FDPE \u0/sp_tms_reg[12] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[12]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[12])); + FDPE \u0/sp_tms_reg[13] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[13]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[13])); + FDPE \u0/sp_tms_reg[14] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[14]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[14])); + FDPE \u0/sp_tms_reg[15] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[15]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[15])); + FDPE \u0/sp_tms_reg[16] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[16]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[16])); + FDPE \u0/sp_tms_reg[17] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[17]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[17])); + FDPE \u0/sp_tms_reg[18] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[18]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[18])); + FDPE \u0/sp_tms_reg[19] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[19]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[19])); + FDPE \u0/sp_tms_reg[1] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[1]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[1])); + FDPE \u0/sp_tms_reg[20] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[20]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[20])); + FDPE \u0/sp_tms_reg[21] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[21]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[21])); + FDPE \u0/sp_tms_reg[22] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[22]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[22])); + FDPE \u0/sp_tms_reg[23] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[23]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[23])); + FDPE \u0/sp_tms_reg[24] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[24]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[24])); + FDPE \u0/sp_tms_reg[25] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[25]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[25])); + FDPE \u0/sp_tms_reg[26] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[26]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[26])); + FDPE \u0/sp_tms_reg[27] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[27]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[27])); + FDPE \u0/sp_tms_reg[2] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[2]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[2])); + FDPE \u0/sp_tms_reg[3] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[3]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[3])); + FDPE \u0/sp_tms_reg[4] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[4]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[4])); + FDPE \u0/sp_tms_reg[5] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[5]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[5])); + FDPE \u0/sp_tms_reg[6] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[6]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[6])); + FDPE \u0/sp_tms_reg[7] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[7]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[7])); + FDPE \u0/sp_tms_reg[8] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[8]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[8])); + FDPE \u0/sp_tms_reg[9] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\sp_tms[9]_i_1_n_0 ), + .PRE(rst_i), + .Q(sp_tms[9])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hB8FFB800)) + \u0/spec_req_cs[0]_i_1 + (.I0(\u0/u0/init_req_reg_n_0 ), + .I1(init_req), + .I2(\u0/u0/lmr_req_reg_n_0 ), + .I3(sreq_cs_le), + .I4(spec_req_cs[0]), + .O(\u0/spec_req_cs[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00E2FFFF00E20000)) + \u0/spec_req_cs[1]_i_1 + (.I0(\u0/u1/lmr_req_reg_n_0 ), + .I1(init_req), + .I2(\u0/u1/init_req_reg_n_0 ), + .I3(\u0/spec_req_cs_t ), + .I4(sreq_cs_le), + .I5(spec_req_cs[1]), + .O(\u0/spec_req_cs[1]_i_1_n_0 )); + FDCE \u0/spec_req_cs_reg[0] + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u0/spec_req_cs[0]_i_1_n_0 ), + .Q(spec_req_cs[0])); + FDCE \u0/spec_req_cs_reg[1] + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u0/spec_req_cs[1]_i_1_n_0 ), + .Q(spec_req_cs[1])); + FDCE \u0/sreq_cs_le_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u0/sreq_cs_le0 ), + .Q(sreq_cs_le)); + FDPE \u0/tms_reg[0] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[0]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[0] )); + FDPE \u0/tms_reg[10] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[10]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[10] )); + FDPE \u0/tms_reg[11] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[11]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[11] )); + FDPE \u0/tms_reg[12] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[12]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[12] )); + FDPE \u0/tms_reg[13] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[13]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[13] )); + FDPE \u0/tms_reg[14] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[14]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[14] )); + FDPE \u0/tms_reg[15] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[15]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[15] )); + FDPE \u0/tms_reg[16] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[16]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[16] )); + FDPE \u0/tms_reg[17] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[17]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[17] )); + FDPE \u0/tms_reg[18] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[18]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[18] )); + FDPE \u0/tms_reg[19] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[19]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[19] )); + FDPE \u0/tms_reg[1] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[1]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[1] )); + FDPE \u0/tms_reg[20] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[20]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[20] )); + FDPE \u0/tms_reg[21] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[21]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[21] )); + FDPE \u0/tms_reg[22] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[22]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[22] )); + FDPE \u0/tms_reg[23] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[23]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[23] )); + FDPE \u0/tms_reg[24] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[24]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[24] )); + FDPE \u0/tms_reg[25] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[25]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[25] )); + FDPE \u0/tms_reg[26] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[26]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[26] )); + FDPE \u0/tms_reg[27] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[27]_i_2_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[27] )); + FDPE \u0/tms_reg[2] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[2]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[2] )); + FDPE \u0/tms_reg[3] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[3]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[3] )); + FDPE \u0/tms_reg[4] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[4]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[4] )); + FDPE \u0/tms_reg[5] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[5]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[5] )); + FDPE \u0/tms_reg[6] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[6]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[6] )); + FDPE \u0/tms_reg[7] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[7]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[7] )); + FDPE \u0/tms_reg[8] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[8]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[8] )); + FDPE \u0/tms_reg[9] + (.C(clk_i), + .CE(\tms[27]_i_1_n_0 ), + .D(\tms[9]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u0/tms_reg_n_0_[9] )); + FDRE \u0/u0/addr_r_reg[2] + (.C(clk_i), + .CE(\ ), + .D(wb_addr_i[2]), + .Q(\u0/p_0_in1_in ), + .R(\ )); + FDRE \u0/u0/addr_r_reg[3] + (.C(clk_i), + .CE(\ ), + .D(wb_addr_i[3]), + .Q(\u0/p_0_in [0]), + .R(\ )); + FDRE \u0/u0/addr_r_reg[4] + (.C(clk_i), + .CE(\ ), + .D(wb_addr_i[4]), + .Q(\u0/p_0_in [1]), + .R(\ )); + FDRE \u0/u0/addr_r_reg[5] + (.C(clk_i), + .CE(\ ), + .D(wb_addr_i[5]), + .Q(\u0/p_0_in [2]), + .R(\ )); + FDRE \u0/u0/addr_r_reg[6] + (.C(clk_i), + .CE(\ ), + .D(wb_addr_i[6]), + .Q(\u0/p_0_in [3]), + .R(\ )); + FDRE \u0/u0/csc_reg[0] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(\csc[0]_i_1_n_0 ), + .Q(\u0/u0/csc_reg_n_0_[0] ), + .R(\ )); + FDRE \u0/u0/csc_reg[10] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[10]), + .Q(\u0/u0/csc_reg_n_0_[10] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[11] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[11]), + .Q(\u0/u0/csc_reg_n_0_[11] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[12] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[12]), + .Q(\u0/u0/csc_reg_n_0_[12] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[13] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[13]), + .Q(\u0/u0/csc_reg_n_0_[13] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[14] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[14]), + .Q(\u0/u0/csc_reg_n_0_[14] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[15] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[15]), + .Q(\u0/u0/csc_reg_n_0_[15] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[16] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[16]), + .Q(\u0/u0/csc_reg_n_0_[16] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[17] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[17]), + .Q(\u0/u0/csc_reg_n_0_[17] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[18] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[18]), + .Q(\u0/u0/csc_reg_n_0_[18] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[19] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[19]), + .Q(\u0/u0/csc_reg_n_0_[19] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[1] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(\csc[1]_i_1_n_0 ), + .Q(\u0/u0/csc_reg_n_0_[1] ), + .R(\ )); + FDRE \u0/u0/csc_reg[20] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[20]), + .Q(\u0/u0/csc_reg_n_0_[20] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[21] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[21]), + .Q(\u0/u0/csc_reg_n_0_[21] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[22] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[22]), + .Q(\u0/u0/csc_reg_n_0_[22] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[23] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[23]), + .Q(\u0/u0/csc_reg_n_0_[23] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[24] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[24]), + .Q(\u0/u0/csc_reg_n_0_[24] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[25] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[25]), + .Q(\u0/u0/csc_reg_n_0_[25] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[26] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[26]), + .Q(\u0/u0/csc_reg_n_0_[26] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[27] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[27]), + .Q(\u0/u0/csc_reg_n_0_[27] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[28] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[28]), + .Q(\u0/u0/csc_reg_n_0_[28] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[29] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[29]), + .Q(\u0/u0/csc_reg_n_0_[29] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[2] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(\csc[2]_i_1_n_0 ), + .Q(\u0/u0/csc_reg_n_0_[2] ), + .R(\ )); + FDRE \u0/u0/csc_reg[30] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[30]), + .Q(\u0/u0/csc_reg_n_0_[30] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[31] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[31]), + .Q(\u0/u0/csc_reg_n_0_[31] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[3] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[3]), + .Q(\u0/u0/csc_reg_n_0_[3] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[4] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(\csc[4]_i_1_n_0 ), + .Q(\u0/u0/csc_reg_n_0_[4] ), + .R(\ )); + FDRE \u0/u0/csc_reg[5] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(\csc[5]_i_2_n_0 ), + .Q(\u0/u0/csc_reg_n_0_[5] ), + .R(\ )); + FDRE \u0/u0/csc_reg[6] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[6]), + .Q(\u0/u0/csc_reg_n_0_[6] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[7] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[7]), + .Q(\u0/u0/csc_reg_n_0_[7] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[8] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[8]), + .Q(\u0/u0/csc_reg_n_0_[8] ), + .R(\u0/rst_r2 )); + FDRE \u0/u0/csc_reg[9] + (.C(clk_i), + .CE(\csc[5]_i_1_n_0 ), + .D(wb_data_i[9]), + .Q(\u0/u0/csc_reg_n_0_[9] ), + .R(\u0/rst_r2 )); + FDCE \u0/u0/init_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(init_req_i_1__0_n_0), + .Q(\u0/u0/init_req_reg_n_0 )); + FDCE \u0/u0/init_req_we_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(init_req_we_i_1_n_0), + .Q(\u0/init_req_we )); + FDCE \u0/u0/inited_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(inited_i_1__0_n_0), + .Q(\u0/inited )); + FDCE \u0/u0/lmr_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(lmr_req_i_1__1_n_0), + .Q(\u0/u0/lmr_req_reg_n_0 )); + FDCE \u0/u0/lmr_req_we_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u0/tms0 ), + .Q(\u0/lmr_req_we )); + FDPE \u0/u0/rst_r1_reg + (.C(clk_i), + .CE(\ ), + .D(\ ), + .PRE(rst_i), + .Q(rst_r1)); + FDPE \u0/u0/rst_r2_reg + (.C(clk_i), + .CE(\ ), + .D(rst_r1), + .PRE(rst_i), + .Q(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[0] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[0]), + .Q(tms[0]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[10] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[10]), + .Q(tms[10]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[11] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[11]), + .Q(tms[11]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[12] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[12]), + .Q(tms[12]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[13] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[13]), + .Q(tms[13]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[14] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[14]), + .Q(tms[14]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[15] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[15]), + .Q(tms[15]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[16] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[16]), + .Q(tms[16]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[17] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[17]), + .Q(tms[17]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[18] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[18]), + .Q(tms[18]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[19] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[19]), + .Q(tms[19]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[1] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[1]), + .Q(tms[1]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[20] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[20]), + .Q(tms[20]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[21] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[21]), + .Q(tms[21]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[22] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[22]), + .Q(tms[22]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[23] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[23]), + .Q(tms[23]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[24] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[24]), + .Q(tms[24]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[25] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[25]), + .Q(tms[25]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[26] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[26]), + .Q(tms[26]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[27] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[27]), + .Q(tms[27]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[28] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[28]), + .Q(tms[28]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[29] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[29]), + .Q(tms[29]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[2] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[2]), + .Q(tms[2]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[30] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[30]), + .Q(tms[30]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[31] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[31]), + .Q(tms[31]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[3] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[3]), + .Q(tms[3]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[4] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[4]), + .Q(tms[4]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[5] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[5]), + .Q(tms[5]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[6] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[6]), + .Q(tms[6]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[7] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[7]), + .Q(tms[7]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[8] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[8]), + .Q(tms[8]), + .S(\u0/rst_r2 )); + FDSE \u0/u0/tms_reg[9] + (.C(clk_i), + .CE(\u0/tms0 ), + .D(wb_data_i[9]), + .Q(tms[9]), + .S(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[0] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[0]), + .Q(\u0/u1/csc_reg_n_0_[0] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[10] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[10]), + .Q(\u0/u1/csc_reg_n_0_[10] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[11] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[11]), + .Q(\u0/u1/csc_reg_n_0_[11] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[12] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[12]), + .Q(\u0/u1/csc_reg_n_0_[12] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[13] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[13]), + .Q(\u0/u1/csc_reg_n_0_[13] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[14] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[14]), + .Q(\u0/u1/csc_reg_n_0_[14] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[15] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[15]), + .Q(\u0/u1/csc_reg_n_0_[15] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[16] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[16]), + .Q(\u0/u1/csc_reg_n_0_[16] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[17] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[17]), + .Q(\u0/u1/csc_reg_n_0_[17] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[18] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[18]), + .Q(\u0/u1/csc_reg_n_0_[18] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[19] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[19]), + .Q(\u0/u1/csc_reg_n_0_[19] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[1] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[1]), + .Q(\u0/u1/csc_reg_n_0_[1] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[20] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[20]), + .Q(\u0/u1/csc_reg_n_0_[20] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[21] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[21]), + .Q(\u0/u1/csc_reg_n_0_[21] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[22] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[22]), + .Q(\u0/u1/csc_reg_n_0_[22] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[23] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[23]), + .Q(\u0/u1/csc_reg_n_0_[23] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[24] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[24]), + .Q(\u0/u1/csc_reg_n_0_[24] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[25] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[25]), + .Q(\u0/u1/csc_reg_n_0_[25] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[26] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[26]), + .Q(\u0/u1/csc_reg_n_0_[26] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[27] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[27]), + .Q(\u0/u1/csc_reg_n_0_[27] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[28] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[28]), + .Q(\u0/u1/csc_reg_n_0_[28] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[29] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[29]), + .Q(\u0/u1/csc_reg_n_0_[29] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[2] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[2]), + .Q(\u0/u1/csc_reg_n_0_[2] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[30] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[30]), + .Q(\u0/u1/csc_reg_n_0_[30] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[31] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[31]), + .Q(\u0/u1/csc_reg_n_0_[31] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[3] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[3]), + .Q(\u0/u1/csc_reg_n_0_[3] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[4] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[4]), + .Q(\u0/u1/csc_reg_n_0_[4] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[5] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[5]), + .Q(\u0/u1/csc_reg_n_0_[5] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[6] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[6]), + .Q(\u0/u1/csc_reg_n_0_[6] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[7] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[7]), + .Q(\u0/u1/csc_reg_n_0_[7] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[8] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[8]), + .Q(\u0/u1/csc_reg_n_0_[8] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/csc_reg[9] + (.C(clk_i), + .CE(\csc[31]_i_1_n_0 ), + .D(wb_data_i[9]), + .Q(\u0/u1/csc_reg_n_0_[9] ), + .R(\u0/rst_r2 )); + FDCE \u0/u1/init_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(init_req_i_1__1_n_0), + .Q(\u0/u1/init_req_reg_n_0 )); + FDCE \u0/u1/init_req_we_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\csc[31]_i_1_n_0 ), + .Q(\u0/u1/init_req_we_reg_n_0 )); + FDCE \u0/u1/inited_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(inited_i_1_n_0), + .Q(\u0/u1/inited_reg_n_0 )); + FDCE \u0/u1/lmr_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(lmr_req_i_1__0_n_0), + .Q(\u0/u1/lmr_req_reg_n_0 )); + FDCE \u0/u1/lmr_req_we_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(lmr_req_we_i_1__0_n_0), + .Q(\u0/u1/lmr_req_we_reg_n_0 )); + FDRE \u0/u1/tms_reg[0] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[0]), + .Q(\u0/u1/tms_reg_n_0_[0] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[10] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[10]), + .Q(\u0/u1/tms_reg_n_0_[10] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[11] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[11]), + .Q(\u0/u1/tms_reg_n_0_[11] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[12] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[12]), + .Q(\u0/u1/tms_reg_n_0_[12] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[13] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[13]), + .Q(\u0/u1/tms_reg_n_0_[13] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[14] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[14]), + .Q(\u0/u1/tms_reg_n_0_[14] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[15] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[15]), + .Q(\u0/u1/tms_reg_n_0_[15] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[16] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[16]), + .Q(\u0/u1/tms_reg_n_0_[16] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[17] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[17]), + .Q(\u0/u1/tms_reg_n_0_[17] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[18] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[18]), + .Q(\u0/u1/tms_reg_n_0_[18] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[19] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[19]), + .Q(\u0/u1/tms_reg_n_0_[19] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[1] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[1]), + .Q(\u0/u1/tms_reg_n_0_[1] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[20] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[20]), + .Q(\u0/u1/tms_reg_n_0_[20] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[21] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[21]), + .Q(\u0/u1/tms_reg_n_0_[21] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[22] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[22]), + .Q(\u0/u1/tms_reg_n_0_[22] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[23] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[23]), + .Q(\u0/u1/tms_reg_n_0_[23] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[24] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[24]), + .Q(\u0/u1/tms_reg_n_0_[24] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[25] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[25]), + .Q(\u0/u1/tms_reg_n_0_[25] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[26] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[26]), + .Q(\u0/u1/tms_reg_n_0_[26] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[27] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[27]), + .Q(\u0/u1/tms_reg_n_0_[27] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[28] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[28]), + .Q(\u0/u1/tms_reg_n_0_[28] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[29] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[29]), + .Q(\u0/u1/tms_reg_n_0_[29] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[2] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[2]), + .Q(\u0/u1/tms_reg_n_0_[2] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[30] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[30]), + .Q(\u0/u1/tms_reg_n_0_[30] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[31] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[31]), + .Q(\u0/u1/tms_reg_n_0_[31] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[3] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[3]), + .Q(\u0/u1/tms_reg_n_0_[3] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[4] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[4]), + .Q(\u0/u1/tms_reg_n_0_[4] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[5] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[5]), + .Q(\u0/u1/tms_reg_n_0_[5] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[6] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[6]), + .Q(\u0/u1/tms_reg_n_0_[6] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[7] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[7]), + .Q(\u0/u1/tms_reg_n_0_[7] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[8] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[8]), + .Q(\u0/u1/tms_reg_n_0_[8] ), + .R(\u0/rst_r2 )); + FDRE \u0/u1/tms_reg[9] + (.C(clk_i), + .CE(lmr_req_we_i_1__0_n_0), + .D(wb_data_i[9]), + .Q(\u0/u1/tms_reg_n_0_[9] ), + .R(\u0/rst_r2 )); + FDCE \u0/wp_err_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(wp_err_i_1_n_0), + .Q(wp_err)); + FDRE \u1/acs_addr_reg[0] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[0]_i_1_n_0 ), + .Q(acs_addr[0]), + .R(\ )); + FDRE \u1/acs_addr_reg[10] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[10]_i_1_n_0 ), + .Q(acs_addr[10]), + .R(\ )); + FDRE \u1/acs_addr_reg[11] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[11]_i_1_n_0 ), + .Q(acs_addr[11]), + .R(\ )); + FDRE \u1/acs_addr_reg[12] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[12]_i_1_n_0 ), + .Q(acs_addr[12]), + .R(\ )); + FDRE \u1/acs_addr_reg[13] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[13]_i_1_n_0 ), + .Q(acs_addr[13]), + .R(\ )); + FDRE \u1/acs_addr_reg[14] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[14]_i_1_n_0 ), + .Q(acs_addr[14]), + .R(\ )); + FDRE \u1/acs_addr_reg[15] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[15]_i_1_n_0 ), + .Q(acs_addr[15]), + .R(\ )); + FDRE \u1/acs_addr_reg[16] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[16]_i_1_n_0 ), + .Q(acs_addr[16]), + .R(\ )); + FDRE \u1/acs_addr_reg[17] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[17]_i_1_n_0 ), + .Q(acs_addr[17]), + .R(\ )); + FDRE \u1/acs_addr_reg[18] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[18]_i_1_n_0 ), + .Q(acs_addr[18]), + .R(\ )); + FDRE \u1/acs_addr_reg[19] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[19]_i_1_n_0 ), + .Q(acs_addr[19]), + .R(\ )); + FDRE \u1/acs_addr_reg[1] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[1]_i_1_n_0 ), + .Q(acs_addr[1]), + .R(\ )); + FDRE \u1/acs_addr_reg[20] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[20]_i_1_n_0 ), + .Q(acs_addr[20]), + .R(\ )); + FDRE \u1/acs_addr_reg[21] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[21]_i_1_n_0 ), + .Q(acs_addr[21]), + .R(\ )); + FDRE \u1/acs_addr_reg[22] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[22]_i_1_n_0 ), + .Q(acs_addr[22]), + .R(\ )); + FDRE \u1/acs_addr_reg[23] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[23]_i_2_n_0 ), + .Q(acs_addr[23]), + .R(\ )); + FDRE \u1/acs_addr_reg[2] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[2]_i_1_n_0 ), + .Q(acs_addr[2]), + .R(\ )); + FDRE \u1/acs_addr_reg[3] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[3]_i_1_n_0 ), + .Q(acs_addr[3]), + .R(\ )); + FDRE \u1/acs_addr_reg[4] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[4]_i_1_n_0 ), + .Q(acs_addr[4]), + .R(\ )); + FDRE \u1/acs_addr_reg[5] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[5]_i_1_n_0 ), + .Q(acs_addr[5]), + .R(\ )); + FDRE \u1/acs_addr_reg[6] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[6]_i_1_n_0 ), + .Q(acs_addr[6]), + .R(\ )); + FDRE \u1/acs_addr_reg[7] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[7]_i_1_n_0 ), + .Q(acs_addr[7]), + .R(\ )); + FDRE \u1/acs_addr_reg[8] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[8]_i_1_n_0 ), + .Q(acs_addr[8]), + .R(\ )); + FDRE \u1/acs_addr_reg[9] + (.C(clk_i), + .CE(\acs_addr[23]_i_1_n_0 ), + .D(\acs_addr[9]_i_1_n_0 ), + .Q(acs_addr[9]), + .R(\ )); + FDRE \u1/bank_adr_reg[0] + (.C(clk_i), + .CE(cs_le), + .D(\bank_adr[0]_i_1_n_0 ), + .Q(bank_adr[0]), + .R(\ )); + FDRE \u1/bank_adr_reg[1] + (.C(clk_i), + .CE(cs_le), + .D(\bank_adr[1]_i_1_n_0 ), + .Q(bank_adr[1]), + .R(\ )); + FDRE \u1/col_adr_reg[0] + (.C(clk_i), + .CE(\col_adr[9]_i_1_n_0 ), + .D(wb_addr_i[2]), + .Q(col_adr[0]), + .R(\ )); + FDRE \u1/col_adr_reg[1] + (.C(clk_i), + .CE(\col_adr[9]_i_1_n_0 ), + .D(wb_addr_i[3]), + .Q(col_adr[1]), + .R(\ )); + FDRE \u1/col_adr_reg[2] + (.C(clk_i), + .CE(\col_adr[9]_i_1_n_0 ), + .D(wb_addr_i[4]), + .Q(col_adr[2]), + .R(\ )); + FDRE \u1/col_adr_reg[3] + (.C(clk_i), + .CE(\col_adr[9]_i_1_n_0 ), + .D(wb_addr_i[5]), + .Q(col_adr[3]), + .R(\ )); + FDRE \u1/col_adr_reg[4] + (.C(clk_i), + .CE(\col_adr[9]_i_1_n_0 ), + .D(wb_addr_i[6]), + .Q(col_adr[4]), + .R(\ )); + FDRE \u1/col_adr_reg[5] + (.C(clk_i), + .CE(\col_adr[9]_i_1_n_0 ), + .D(wb_addr_i[7]), + .Q(col_adr[5]), + .R(\ )); + FDRE \u1/col_adr_reg[6] + (.C(clk_i), + .CE(\col_adr[9]_i_1_n_0 ), + .D(wb_addr_i[8]), + .Q(col_adr[6]), + .R(\ )); + FDRE \u1/col_adr_reg[7] + (.C(clk_i), + .CE(\col_adr[9]_i_1_n_0 ), + .D(wb_addr_i[9]), + .Q(col_adr[7]), + .R(\ )); + FDRE \u1/col_adr_reg[8] + (.C(clk_i), + .CE(\col_adr[9]_i_1_n_0 ), + .D(\u1/col_adr [8]), + .Q(col_adr[8]), + .R(\ )); + FDRE \u1/col_adr_reg[9] + (.C(clk_i), + .CE(\col_adr[9]_i_1_n_0 ), + .D(\u1/col_adr [9]), + .Q(col_adr[9]), + .R(\ )); + FDRE \u1/row_adr_reg[0] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[0]_i_1_n_0 ), + .Q(row_adr[0]), + .R(\ )); + FDRE \u1/row_adr_reg[10] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[10]_i_1_n_0 ), + .Q(row_adr[10]), + .R(\ )); + FDRE \u1/row_adr_reg[11] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr_reg[11]_i_1_n_0 ), + .Q(row_adr[11]), + .R(\ )); + FDRE \u1/row_adr_reg[12] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr_reg[12]_i_1_n_0 ), + .Q(row_adr[12]), + .R(\ )); + FDRE \u1/row_adr_reg[1] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[1]_i_1_n_0 ), + .Q(row_adr[1]), + .R(\ )); + FDRE \u1/row_adr_reg[2] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[2]_i_1_n_0 ), + .Q(row_adr[2]), + .R(\ )); + FDRE \u1/row_adr_reg[3] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[3]_i_1_n_0 ), + .Q(row_adr[3]), + .R(\ )); + FDRE \u1/row_adr_reg[4] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[4]_i_1_n_0 ), + .Q(row_adr[4]), + .R(\ )); + FDRE \u1/row_adr_reg[5] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[5]_i_1_n_0 ), + .Q(row_adr[5]), + .R(\ )); + FDRE \u1/row_adr_reg[6] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[6]_i_1_n_0 ), + .Q(row_adr[6]), + .R(\ )); + FDRE \u1/row_adr_reg[7] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[7]_i_1_n_0 ), + .Q(row_adr[7]), + .R(\ )); + FDRE \u1/row_adr_reg[8] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[8]_i_1_n_0 ), + .Q(row_adr[8]), + .R(\ )); + FDRE \u1/row_adr_reg[9] + (.C(clk_i), + .CE(cs_le), + .D(\row_adr[9]_i_1_n_0 ), + .Q(row_adr[9]), + .R(\ )); + FDRE \u1/sram_addr_reg[0] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[2]), + .Q(sram_addr[0]), + .R(\ )); + FDRE \u1/sram_addr_reg[10] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[12]), + .Q(sram_addr[10]), + .R(\ )); + FDRE \u1/sram_addr_reg[11] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[13]), + .Q(sram_addr[11]), + .R(\ )); + FDRE \u1/sram_addr_reg[12] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[14]), + .Q(sram_addr[12]), + .R(\ )); + FDRE \u1/sram_addr_reg[13] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[15]), + .Q(sram_addr[13]), + .R(\ )); + FDRE \u1/sram_addr_reg[14] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[16]), + .Q(sram_addr[14]), + .R(\ )); + FDRE \u1/sram_addr_reg[15] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[17]), + .Q(sram_addr[15]), + .R(\ )); + FDRE \u1/sram_addr_reg[16] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[18]), + .Q(sram_addr[16]), + .R(\ )); + FDRE \u1/sram_addr_reg[17] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[19]), + .Q(sram_addr[17]), + .R(\ )); + FDRE \u1/sram_addr_reg[18] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[20]), + .Q(sram_addr[18]), + .R(\ )); + FDRE \u1/sram_addr_reg[19] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[21]), + .Q(sram_addr[19]), + .R(\ )); + FDRE \u1/sram_addr_reg[1] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[3]), + .Q(sram_addr[1]), + .R(\ )); + FDRE \u1/sram_addr_reg[20] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[22]), + .Q(sram_addr[20]), + .R(\ )); + FDRE \u1/sram_addr_reg[21] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[23]), + .Q(sram_addr[21]), + .R(\ )); + FDRE \u1/sram_addr_reg[22] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[24]), + .Q(sram_addr[22]), + .R(\ )); + FDRE \u1/sram_addr_reg[23] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[25]), + .Q(sram_addr[23]), + .R(\ )); + FDRE \u1/sram_addr_reg[2] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[4]), + .Q(sram_addr[2]), + .R(\ )); + FDRE \u1/sram_addr_reg[3] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[5]), + .Q(sram_addr[3]), + .R(\ )); + FDRE \u1/sram_addr_reg[4] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[6]), + .Q(sram_addr[4]), + .R(\ )); + FDRE \u1/sram_addr_reg[5] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[7]), + .Q(sram_addr[5]), + .R(\ )); + FDRE \u1/sram_addr_reg[6] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[8]), + .Q(sram_addr[6]), + .R(\ )); + FDRE \u1/sram_addr_reg[7] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[9]), + .Q(sram_addr[7]), + .R(\ )); + FDRE \u1/sram_addr_reg[8] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[10]), + .Q(sram_addr[8]), + .R(\ )); + FDRE \u1/sram_addr_reg[9] + (.C(clk_i), + .CE(wb_stb_i), + .D(wb_addr_i[11]), + .Q(sram_addr[9]), + .R(\ )); + CARRY4 \u1/u0/out_r0_carry + (.CI(\ ), + .CO({\u1/u0/out_r0_carry_n_0 ,\u1/u0/out_r0_carry_n_1 ,\u1/u0/out_r0_carry_n_2 ,\u1/u0/out_r0_carry_n_3 }), + .CYINIT(acs_addr[0]), + .DI({\ ,\ ,\ ,\ }), + .O({\u1/u0/out_r0_carry_n_4 ,\u1/u0/out_r0_carry_n_5 ,\u1/u0/out_r0_carry_n_6 ,\u1/u0/out_r0_carry_n_7 }), + .S(acs_addr[4:1])); + CARRY4 \u1/u0/out_r0_carry__0 + (.CI(\u1/u0/out_r0_carry_n_0 ), + .CO({\u1/u0/out_r0_carry__0_n_0 ,\u1/u0/out_r0_carry__0_n_1 ,\u1/u0/out_r0_carry__0_n_2 ,\u1/u0/out_r0_carry__0_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\u1/u0/out_r0_carry__0_n_4 ,\u1/u0/out_r0_carry__0_n_5 ,\u1/u0/out_r0_carry__0_n_6 ,\u1/u0/out_r0_carry__0_n_7 }), + .S(acs_addr[8:5])); + CARRY4 \u1/u0/out_r0_carry__1 + (.CI(\u1/u0/out_r0_carry__0_n_0 ), + .CO({\u1/u0/out_r0_carry__1_n_0 ,\NLW_u1/u0/out_r0_carry__1_CO_UNCONNECTED [2],\u1/u0/out_r0_carry__1_n_2 ,\u1/u0/out_r0_carry__1_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\u1/u0/out_r0_carry__1_n_5 ,\u1/u0/out_r0_carry__1_n_6 ,\u1/u0/out_r0_carry__1_n_7 }), + .S({\ ,acs_addr[11:9]})); + FDRE \u1/u0/out_r_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\out_r[0]_i_1_n_0 ), + .Q(\u1/u0/out_r_reg_n_0_[0] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[10] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry__1_n_6 ), + .Q(\u1/u0/out_r_reg_n_0_[10] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[11] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry__1_n_5 ), + .Q(\u1/u0/out_r_reg_n_0_[11] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[12] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry__1_n_0 ), + .Q(inc_next), + .R(\ )); + FDRE \u1/u0/out_r_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry_n_7 ), + .Q(\u1/u0/out_r_reg_n_0_[1] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry_n_6 ), + .Q(\u1/u0/out_r_reg_n_0_[2] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[3] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry_n_5 ), + .Q(\u1/u0/out_r_reg_n_0_[3] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[4] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry_n_4 ), + .Q(\u1/u0/out_r_reg_n_0_[4] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[5] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry__0_n_7 ), + .Q(\u1/u0/out_r_reg_n_0_[5] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[6] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry__0_n_6 ), + .Q(\u1/u0/out_r_reg_n_0_[6] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[7] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry__0_n_5 ), + .Q(\u1/u0/out_r_reg_n_0_[7] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[8] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry__0_n_4 ), + .Q(\u1/u0/out_r_reg_n_0_[8] ), + .R(\ )); + FDRE \u1/u0/out_r_reg[9] + (.C(clk_i), + .CE(\ ), + .D(\u1/u0/out_r0_carry__1_n_7 ), + .Q(\u1/u0/out_r_reg_n_0_[9] ), + .R(\ )); + FDRE \u2/bank_open_reg + (.C(clk_i), + .CE(\ ), + .D(\u2/bank_open0 ), + .Q(bank_open), + .R(\ )); + FDRE \u2/row_same_reg + (.C(clk_i), + .CE(\ ), + .D(\u2/row_same0 ), + .Q(row_same), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[0] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[0]), + .Q(\u2/u0/b0_last_row_reg_n_0_[0] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[10] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[10]), + .Q(\u2/u0/b0_last_row_reg_n_0_[10] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[11] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[11]), + .Q(\u2/u0/b0_last_row_reg_n_0_[11] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[12] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[12]), + .Q(\u2/u0/b0_last_row_reg_n_0_[12] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[1] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[1]), + .Q(\u2/u0/b0_last_row_reg_n_0_[1] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[2] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[2]), + .Q(\u2/u0/b0_last_row_reg_n_0_[2] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[3] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[3]), + .Q(\u2/u0/b0_last_row_reg_n_0_[3] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[4] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[4]), + .Q(\u2/u0/b0_last_row_reg_n_0_[4] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[5] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[5]), + .Q(\u2/u0/b0_last_row_reg_n_0_[5] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[6] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[6]), + .Q(\u2/u0/b0_last_row_reg_n_0_[6] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[7] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[7]), + .Q(\u2/u0/b0_last_row_reg_n_0_[7] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[8] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[8]), + .Q(\u2/u0/b0_last_row_reg_n_0_[8] ), + .R(\ )); + FDRE \u2/u0/b0_last_row_reg[9] + (.C(clk_i), + .CE(\u2/bank0_open0 ), + .D(row_adr[9]), + .Q(\u2/u0/b0_last_row_reg_n_0_[9] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[0] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[0]), + .Q(\u2/u0/b1_last_row_reg_n_0_[0] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[10] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[10]), + .Q(\u2/u0/b1_last_row_reg_n_0_[10] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[11] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[11]), + .Q(\u2/u0/b1_last_row_reg_n_0_[11] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[12] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[12]), + .Q(\u2/u0/b1_last_row_reg_n_0_[12] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[1] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[1]), + .Q(\u2/u0/b1_last_row_reg_n_0_[1] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[2] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[2]), + .Q(\u2/u0/b1_last_row_reg_n_0_[2] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[3] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[3]), + .Q(\u2/u0/b1_last_row_reg_n_0_[3] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[4] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[4]), + .Q(\u2/u0/b1_last_row_reg_n_0_[4] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[5] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[5]), + .Q(\u2/u0/b1_last_row_reg_n_0_[5] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[6] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[6]), + .Q(\u2/u0/b1_last_row_reg_n_0_[6] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[7] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[7]), + .Q(\u2/u0/b1_last_row_reg_n_0_[7] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[8] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[8]), + .Q(\u2/u0/b1_last_row_reg_n_0_[8] ), + .R(\ )); + FDRE \u2/u0/b1_last_row_reg[9] + (.C(clk_i), + .CE(\u2/bank1_open0 ), + .D(row_adr[9]), + .Q(\u2/u0/b1_last_row_reg_n_0_[9] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[0] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[0]), + .Q(\u2/u0/b2_last_row_reg_n_0_[0] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[10] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[10]), + .Q(\u2/u0/b2_last_row_reg_n_0_[10] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[11] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[11]), + .Q(\u2/u0/b2_last_row_reg_n_0_[11] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[12] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[12]), + .Q(\u2/u0/b2_last_row_reg_n_0_[12] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[1] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[1]), + .Q(\u2/u0/b2_last_row_reg_n_0_[1] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[2] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[2]), + .Q(\u2/u0/b2_last_row_reg_n_0_[2] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[3] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[3]), + .Q(\u2/u0/b2_last_row_reg_n_0_[3] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[4] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[4]), + .Q(\u2/u0/b2_last_row_reg_n_0_[4] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[5] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[5]), + .Q(\u2/u0/b2_last_row_reg_n_0_[5] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[6] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[6]), + .Q(\u2/u0/b2_last_row_reg_n_0_[6] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[7] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[7]), + .Q(\u2/u0/b2_last_row_reg_n_0_[7] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[8] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[8]), + .Q(\u2/u0/b2_last_row_reg_n_0_[8] ), + .R(\ )); + FDRE \u2/u0/b2_last_row_reg[9] + (.C(clk_i), + .CE(\u2/bank2_open0 ), + .D(row_adr[9]), + .Q(\u2/u0/b2_last_row_reg_n_0_[9] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[0] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[0]), + .Q(\u2/u0/b3_last_row_reg_n_0_[0] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[10] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[10]), + .Q(\u2/u0/b3_last_row_reg_n_0_[10] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[11] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[11]), + .Q(\u2/u0/b3_last_row_reg_n_0_[11] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[12] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[12]), + .Q(\u2/u0/b3_last_row_reg_n_0_[12] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[1] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[1]), + .Q(\u2/u0/b3_last_row_reg_n_0_[1] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[2] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[2]), + .Q(\u2/u0/b3_last_row_reg_n_0_[2] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[3] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[3]), + .Q(\u2/u0/b3_last_row_reg_n_0_[3] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[4] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[4]), + .Q(\u2/u0/b3_last_row_reg_n_0_[4] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[5] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[5]), + .Q(\u2/u0/b3_last_row_reg_n_0_[5] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[6] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[6]), + .Q(\u2/u0/b3_last_row_reg_n_0_[6] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[7] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[7]), + .Q(\u2/u0/b3_last_row_reg_n_0_[7] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[8] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[8]), + .Q(\u2/u0/b3_last_row_reg_n_0_[8] ), + .R(\ )); + FDRE \u2/u0/b3_last_row_reg[9] + (.C(clk_i), + .CE(\u2/bank3_open0 ), + .D(row_adr[9]), + .Q(\u2/u0/b3_last_row_reg_n_0_[9] ), + .R(\ )); + FDCE \u2/u0/bank0_open_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(bank0_open_i_1__0_n_0), + .Q(\u2/bank0_open )); + FDCE \u2/u0/bank1_open_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(bank1_open_i_1__0_n_0), + .Q(\u2/bank1_open )); + FDCE \u2/u0/bank2_open_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(bank2_open_i_1__0_n_0), + .Q(\u2/bank2_open )); + FDCE \u2/u0/bank3_open_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(bank3_open_i_1__0_n_0), + .Q(\u2/bank3_open )); + CARRY4 \u2/u0/row0_same_carry + (.CI(\ ), + .CO({\u2/u0/row0_same_carry_n_0 ,\u2/u0/row0_same_carry_n_1 ,\u2/u0/row0_same_carry_n_2 ,\u2/u0/row0_same_carry_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({row0_same_carry_i_1__0_n_0,row0_same_carry_i_2__0_n_0,row0_same_carry_i_3__0_n_0,row0_same_carry_i_4__0_n_0})); + CARRY4 \u2/u0/row0_same_carry__0 + (.CI(\u2/u0/row0_same_carry_n_0 ), + .CO(\u2/row0_same ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({\ ,\ ,\ ,row0_same_carry__0_i_1_n_0})); + CARRY4 \u2/u0/row1_same_carry + (.CI(\ ), + .CO({\u2/u0/row1_same_carry_n_0 ,\u2/u0/row1_same_carry_n_1 ,\u2/u0/row1_same_carry_n_2 ,\u2/u0/row1_same_carry_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({row1_same_carry_i_1__0_n_0,row1_same_carry_i_2__0_n_0,row1_same_carry_i_3__0_n_0,row1_same_carry_i_4__0_n_0})); + CARRY4 \u2/u0/row1_same_carry__0 + (.CI(\u2/u0/row1_same_carry_n_0 ), + .CO(\u2/row1_same ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({\ ,\ ,\ ,row1_same_carry__0_i_1__0_n_0})); + CARRY4 \u2/u0/row2_same_carry + (.CI(\ ), + .CO({\u2/u0/row2_same_carry_n_0 ,\u2/u0/row2_same_carry_n_1 ,\u2/u0/row2_same_carry_n_2 ,\u2/u0/row2_same_carry_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({row2_same_carry_i_1__0_n_0,row2_same_carry_i_2__0_n_0,row2_same_carry_i_3__0_n_0,row2_same_carry_i_4__0_n_0})); + CARRY4 \u2/u0/row2_same_carry__0 + (.CI(\u2/u0/row2_same_carry_n_0 ), + .CO(\u2/row2_same ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({\ ,\ ,\ ,row2_same_carry__0_i_1__0_n_0})); + CARRY4 \u2/u0/row3_same_carry + (.CI(\ ), + .CO({\u2/u0/row3_same_carry_n_0 ,\u2/u0/row3_same_carry_n_1 ,\u2/u0/row3_same_carry_n_2 ,\u2/u0/row3_same_carry_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({row3_same_carry_i_1__0_n_0,row3_same_carry_i_2__0_n_0,row3_same_carry_i_3__0_n_0,row3_same_carry_i_4__0_n_0})); + CARRY4 \u2/u0/row3_same_carry__0 + (.CI(\u2/u0/row3_same_carry_n_0 ), + .CO(\u2/row3_same ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({\ ,\ ,\ ,row3_same_carry__0_i_1__0_n_0})); + FDRE \u2/u1/b0_last_row_reg[0] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[0]), + .Q(b0_last_row[0]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[10] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[10]), + .Q(b0_last_row[10]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[11] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[11]), + .Q(b0_last_row[11]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[12] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[12]), + .Q(b0_last_row[12]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[1] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[1]), + .Q(b0_last_row[1]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[2] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[2]), + .Q(b0_last_row[2]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[3] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[3]), + .Q(b0_last_row[3]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[4] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[4]), + .Q(b0_last_row[4]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[5] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[5]), + .Q(b0_last_row[5]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[6] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[6]), + .Q(b0_last_row[6]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[7] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[7]), + .Q(b0_last_row[7]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[8] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[8]), + .Q(b0_last_row[8]), + .R(\ )); + FDRE \u2/u1/b0_last_row_reg[9] + (.C(clk_i), + .CE(\b0_last_row[12]_i_1_n_0 ), + .D(row_adr[9]), + .Q(b0_last_row[9]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[0] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[0]), + .Q(b1_last_row[0]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[10] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[10]), + .Q(b1_last_row[10]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[11] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[11]), + .Q(b1_last_row[11]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[12] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[12]), + .Q(b1_last_row[12]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[1] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[1]), + .Q(b1_last_row[1]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[2] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[2]), + .Q(b1_last_row[2]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[3] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[3]), + .Q(b1_last_row[3]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[4] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[4]), + .Q(b1_last_row[4]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[5] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[5]), + .Q(b1_last_row[5]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[6] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[6]), + .Q(b1_last_row[6]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[7] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[7]), + .Q(b1_last_row[7]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[8] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[8]), + .Q(b1_last_row[8]), + .R(\ )); + FDRE \u2/u1/b1_last_row_reg[9] + (.C(clk_i), + .CE(\b1_last_row[12]_i_1_n_0 ), + .D(row_adr[9]), + .Q(b1_last_row[9]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[0] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[0]), + .Q(b2_last_row[0]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[10] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[10]), + .Q(b2_last_row[10]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[11] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[11]), + .Q(b2_last_row[11]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[12] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[12]), + .Q(b2_last_row[12]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[1] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[1]), + .Q(b2_last_row[1]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[2] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[2]), + .Q(b2_last_row[2]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[3] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[3]), + .Q(b2_last_row[3]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[4] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[4]), + .Q(b2_last_row[4]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[5] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[5]), + .Q(b2_last_row[5]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[6] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[6]), + .Q(b2_last_row[6]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[7] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[7]), + .Q(b2_last_row[7]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[8] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[8]), + .Q(b2_last_row[8]), + .R(\ )); + FDRE \u2/u1/b2_last_row_reg[9] + (.C(clk_i), + .CE(\b2_last_row[12]_i_1_n_0 ), + .D(row_adr[9]), + .Q(b2_last_row[9]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[0] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[0]), + .Q(b3_last_row[0]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[10] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[10]), + .Q(b3_last_row[10]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[11] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[11]), + .Q(b3_last_row[11]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[12] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[12]), + .Q(b3_last_row[12]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[1] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[1]), + .Q(b3_last_row[1]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[2] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[2]), + .Q(b3_last_row[2]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[3] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[3]), + .Q(b3_last_row[3]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[4] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[4]), + .Q(b3_last_row[4]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[5] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[5]), + .Q(b3_last_row[5]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[6] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[6]), + .Q(b3_last_row[6]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[7] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[7]), + .Q(b3_last_row[7]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[8] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[8]), + .Q(b3_last_row[8]), + .R(\ )); + FDRE \u2/u1/b3_last_row_reg[9] + (.C(clk_i), + .CE(\b3_last_row[12]_i_1_n_0 ), + .D(row_adr[9]), + .Q(b3_last_row[9]), + .R(\ )); + FDCE \u2/u1/bank0_open_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(bank0_open_i_1_n_0), + .Q(\u2/u1/bank0_open_reg_n_0 )); + FDCE \u2/u1/bank1_open_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(bank1_open_i_1_n_0), + .Q(\u2/u1/bank1_open_reg_n_0 )); + FDCE \u2/u1/bank2_open_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(bank2_open_i_1_n_0), + .Q(\u2/u1/bank2_open_reg_n_0 )); + FDCE \u2/u1/bank3_open_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(bank3_open_i_1_n_0), + .Q(\u2/u1/bank3_open_reg_n_0 )); + CARRY4 \u2/u1/row0_same_carry + (.CI(\ ), + .CO({\u2/u1/row0_same_carry_n_0 ,\u2/u1/row0_same_carry_n_1 ,\u2/u1/row0_same_carry_n_2 ,\u2/u1/row0_same_carry_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({row0_same_carry_i_1_n_0,row0_same_carry_i_2_n_0,row0_same_carry_i_3_n_0,row0_same_carry_i_4_n_0})); + CARRY4 \u2/u1/row0_same_carry__0 + (.CI(\u2/u1/row0_same_carry_n_0 ), + .CO(\u2/u1/row0_same_carry__0_n_3 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({\ ,\ ,\ ,row0_same_carry__0_i_1__0_n_0})); + CARRY4 \u2/u1/row1_same_carry + (.CI(\ ), + .CO({\u2/u1/row1_same_carry_n_0 ,\u2/u1/row1_same_carry_n_1 ,\u2/u1/row1_same_carry_n_2 ,\u2/u1/row1_same_carry_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({row1_same_carry_i_1_n_0,row1_same_carry_i_2_n_0,row1_same_carry_i_3_n_0,row1_same_carry_i_4_n_0})); + CARRY4 \u2/u1/row1_same_carry__0 + (.CI(\u2/u1/row1_same_carry_n_0 ), + .CO(\u2/u1/row1_same_carry__0_n_3 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({\ ,\ ,\ ,row1_same_carry__0_i_1_n_0})); + CARRY4 \u2/u1/row2_same_carry + (.CI(\ ), + .CO({\u2/u1/row2_same_carry_n_0 ,\u2/u1/row2_same_carry_n_1 ,\u2/u1/row2_same_carry_n_2 ,\u2/u1/row2_same_carry_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({row2_same_carry_i_1_n_0,row2_same_carry_i_2_n_0,row2_same_carry_i_3_n_0,row2_same_carry_i_4_n_0})); + CARRY4 \u2/u1/row2_same_carry__0 + (.CI(\u2/u1/row2_same_carry_n_0 ), + .CO(\u2/u1/row2_same_carry__0_n_3 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({\ ,\ ,\ ,row2_same_carry__0_i_1_n_0})); + CARRY4 \u2/u1/row3_same_carry + (.CI(\ ), + .CO({\u2/u1/row3_same_carry_n_0 ,\u2/u1/row3_same_carry_n_1 ,\u2/u1/row3_same_carry_n_2 ,\u2/u1/row3_same_carry_n_3 }), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({row3_same_carry_i_1_n_0,row3_same_carry_i_2_n_0,row3_same_carry_i_3_n_0,row3_same_carry_i_4_n_0})); + CARRY4 \u2/u1/row3_same_carry__0 + (.CI(\u2/u1/row3_same_carry_n_0 ), + .CO(\u2/u1/row3_same_carry__0_n_3 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .S({\ ,\ ,\ ,row3_same_carry__0_i_1_n_0})); + FDRE \u3/byte0_reg[0] + (.C(clk_i), + .CE(pack_le0), + .D(mc_data_ir[0]), + .Q(byte0[0]), + .R(\ )); + FDRE \u3/byte0_reg[1] + (.C(clk_i), + .CE(pack_le0), + .D(mc_data_ir[1]), + .Q(byte0[1]), + .R(\ )); + FDRE \u3/byte0_reg[2] + (.C(clk_i), + .CE(pack_le0), + .D(mc_data_ir[2]), + .Q(byte0[2]), + .R(\ )); + FDRE \u3/byte0_reg[3] + (.C(clk_i), + .CE(pack_le0), + .D(mc_data_ir[3]), + .Q(byte0[3]), + .R(\ )); + FDRE \u3/byte0_reg[4] + (.C(clk_i), + .CE(pack_le0), + .D(mc_data_ir[4]), + .Q(byte0[4]), + .R(\ )); + FDRE \u3/byte0_reg[5] + (.C(clk_i), + .CE(pack_le0), + .D(mc_data_ir[5]), + .Q(byte0[5]), + .R(\ )); + FDRE \u3/byte0_reg[6] + (.C(clk_i), + .CE(pack_le0), + .D(mc_data_ir[6]), + .Q(byte0[6]), + .R(\ )); + FDRE \u3/byte0_reg[7] + (.C(clk_i), + .CE(pack_le0), + .D(mc_data_ir[7]), + .Q(byte0[7]), + .R(\ )); + FDRE \u3/byte1_reg[0] + (.C(clk_i), + .CE(\byte1[7]_i_1_n_0 ), + .D(\byte1[0]_i_1_n_0 ), + .Q(byte1[0]), + .R(\ )); + FDRE \u3/byte1_reg[1] + (.C(clk_i), + .CE(\byte1[7]_i_1_n_0 ), + .D(\byte1[1]_i_1_n_0 ), + .Q(byte1[1]), + .R(\ )); + FDRE \u3/byte1_reg[2] + (.C(clk_i), + .CE(\byte1[7]_i_1_n_0 ), + .D(\byte1[2]_i_1_n_0 ), + .Q(byte1[2]), + .R(\ )); + FDRE \u3/byte1_reg[3] + (.C(clk_i), + .CE(\byte1[7]_i_1_n_0 ), + .D(\byte1[3]_i_1_n_0 ), + .Q(byte1[3]), + .R(\ )); + FDRE \u3/byte1_reg[4] + (.C(clk_i), + .CE(\byte1[7]_i_1_n_0 ), + .D(\byte1[4]_i_1_n_0 ), + .Q(byte1[4]), + .R(\ )); + FDRE \u3/byte1_reg[5] + (.C(clk_i), + .CE(\byte1[7]_i_1_n_0 ), + .D(\byte1[5]_i_1_n_0 ), + .Q(byte1[5]), + .R(\ )); + FDRE \u3/byte1_reg[6] + (.C(clk_i), + .CE(\byte1[7]_i_1_n_0 ), + .D(\byte1[6]_i_1_n_0 ), + .Q(byte1[6]), + .R(\ )); + FDRE \u3/byte1_reg[7] + (.C(clk_i), + .CE(\byte1[7]_i_1_n_0 ), + .D(\byte1[7]_i_2_n_0 ), + .Q(byte1[7]), + .R(\ )); + FDRE \u3/byte2_reg[0] + (.C(clk_i), + .CE(pack_le2), + .D(mc_data_ir[0]), + .Q(byte2[0]), + .R(\ )); + FDRE \u3/byte2_reg[1] + (.C(clk_i), + .CE(pack_le2), + .D(mc_data_ir[1]), + .Q(byte2[1]), + .R(\ )); + FDRE \u3/byte2_reg[2] + (.C(clk_i), + .CE(pack_le2), + .D(mc_data_ir[2]), + .Q(byte2[2]), + .R(\ )); + FDRE \u3/byte2_reg[3] + (.C(clk_i), + .CE(pack_le2), + .D(mc_data_ir[3]), + .Q(byte2[3]), + .R(\ )); + FDRE \u3/byte2_reg[4] + (.C(clk_i), + .CE(pack_le2), + .D(mc_data_ir[4]), + .Q(byte2[4]), + .R(\ )); + FDRE \u3/byte2_reg[5] + (.C(clk_i), + .CE(pack_le2), + .D(mc_data_ir[5]), + .Q(byte2[5]), + .R(\ )); + FDRE \u3/byte2_reg[6] + (.C(clk_i), + .CE(pack_le2), + .D(mc_data_ir[6]), + .Q(byte2[6]), + .R(\ )); + FDRE \u3/byte2_reg[7] + (.C(clk_i), + .CE(pack_le2), + .D(mc_data_ir[7]), + .Q(byte2[7]), + .R(\ )); + FDRE \u3/mc_data_o_reg[0] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[0]), + .Q(mc_data_o[0]), + .R(\ )); + FDRE \u3/mc_data_o_reg[10] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[10]), + .Q(mc_data_o[10]), + .R(\ )); + FDRE \u3/mc_data_o_reg[11] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[11]), + .Q(mc_data_o[11]), + .R(\ )); + FDRE \u3/mc_data_o_reg[12] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[12]), + .Q(mc_data_o[12]), + .R(\ )); + FDRE \u3/mc_data_o_reg[13] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[13]), + .Q(mc_data_o[13]), + .R(\ )); + FDRE \u3/mc_data_o_reg[14] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[14]), + .Q(mc_data_o[14]), + .R(\ )); + FDRE \u3/mc_data_o_reg[15] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[15]), + .Q(mc_data_o[15]), + .R(\ )); + FDRE \u3/mc_data_o_reg[16] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[16]), + .Q(mc_data_o[16]), + .R(\ )); + FDRE \u3/mc_data_o_reg[17] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[17]), + .Q(mc_data_o[17]), + .R(\ )); + FDRE \u3/mc_data_o_reg[18] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[18]), + .Q(mc_data_o[18]), + .R(\ )); + FDRE \u3/mc_data_o_reg[19] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[19]), + .Q(mc_data_o[19]), + .R(\ )); + FDRE \u3/mc_data_o_reg[1] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[1]), + .Q(mc_data_o[1]), + .R(\ )); + FDRE \u3/mc_data_o_reg[20] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[20]), + .Q(mc_data_o[20]), + .R(\ )); + FDRE \u3/mc_data_o_reg[21] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[21]), + .Q(mc_data_o[21]), + .R(\ )); + FDRE \u3/mc_data_o_reg[22] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[22]), + .Q(mc_data_o[22]), + .R(\ )); + FDRE \u3/mc_data_o_reg[23] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[23]), + .Q(mc_data_o[23]), + .R(\ )); + FDRE \u3/mc_data_o_reg[24] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[24]), + .Q(mc_data_o[24]), + .R(\ )); + FDRE \u3/mc_data_o_reg[25] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[25]), + .Q(mc_data_o[25]), + .R(\ )); + FDRE \u3/mc_data_o_reg[26] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[26]), + .Q(mc_data_o[26]), + .R(\ )); + FDRE \u3/mc_data_o_reg[27] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[27]), + .Q(mc_data_o[27]), + .R(\ )); + FDRE \u3/mc_data_o_reg[28] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[28]), + .Q(mc_data_o[28]), + .R(\ )); + FDRE \u3/mc_data_o_reg[29] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[29]), + .Q(mc_data_o[29]), + .R(\ )); + FDRE \u3/mc_data_o_reg[2] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[2]), + .Q(mc_data_o[2]), + .R(\ )); + FDRE \u3/mc_data_o_reg[30] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[30]), + .Q(mc_data_o[30]), + .R(\ )); + FDRE \u3/mc_data_o_reg[31] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[31]), + .Q(mc_data_o[31]), + .R(\ )); + FDRE \u3/mc_data_o_reg[3] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[3]), + .Q(mc_data_o[3]), + .R(\ )); + FDRE \u3/mc_data_o_reg[4] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[4]), + .Q(mc_data_o[4]), + .R(\ )); + FDRE \u3/mc_data_o_reg[5] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[5]), + .Q(mc_data_o[5]), + .R(\ )); + FDRE \u3/mc_data_o_reg[6] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[6]), + .Q(mc_data_o[6]), + .R(\ )); + FDRE \u3/mc_data_o_reg[7] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[7]), + .Q(mc_data_o[7]), + .R(\ )); + FDRE \u3/mc_data_o_reg[8] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[8]), + .Q(mc_data_o[8]), + .R(\ )); + FDRE \u3/mc_data_o_reg[9] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(wb_data_i[9]), + .Q(mc_data_o[9]), + .R(\ )); + FDRE \u3/mc_dp_o_reg[0] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(\mc_dp_o[0]_i_1_n_0 ), + .Q(mc_dp_o[0]), + .R(\ )); + FDRE \u3/mc_dp_o_reg[1] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(\mc_dp_o[1]_i_1_n_0 ), + .Q(mc_dp_o[1]), + .R(\ )); + FDRE \u3/mc_dp_o_reg[2] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(\mc_dp_o[2]_i_1_n_0 ), + .Q(mc_dp_o[2]), + .R(\ )); + FDRE \u3/mc_dp_o_reg[3] + (.C(clk_i), + .CE(\u3/mc_data_o0 ), + .D(mc_dp_o0), + .Q(mc_dp_o[3]), + .R(\ )); + FDRE \u3/u0/r0_reg[0] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[0]), + .Q(r0[0]), + .R(\ )); + FDRE \u3/u0/r0_reg[10] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[10]), + .Q(r0[10]), + .R(\ )); + FDRE \u3/u0/r0_reg[11] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[11]), + .Q(r0[11]), + .R(\ )); + FDRE \u3/u0/r0_reg[12] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[12]), + .Q(r0[12]), + .R(\ )); + FDRE \u3/u0/r0_reg[13] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[13]), + .Q(r0[13]), + .R(\ )); + FDRE \u3/u0/r0_reg[14] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[14]), + .Q(r0[14]), + .R(\ )); + FDRE \u3/u0/r0_reg[15] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[15]), + .Q(r0[15]), + .R(\ )); + FDRE \u3/u0/r0_reg[16] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[16]), + .Q(r0[16]), + .R(\ )); + FDRE \u3/u0/r0_reg[17] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[17]), + .Q(r0[17]), + .R(\ )); + FDRE \u3/u0/r0_reg[18] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[18]), + .Q(r0[18]), + .R(\ )); + FDRE \u3/u0/r0_reg[19] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[19]), + .Q(r0[19]), + .R(\ )); + FDRE \u3/u0/r0_reg[1] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[1]), + .Q(r0[1]), + .R(\ )); + FDRE \u3/u0/r0_reg[20] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[20]), + .Q(r0[20]), + .R(\ )); + FDRE \u3/u0/r0_reg[21] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[21]), + .Q(r0[21]), + .R(\ )); + FDRE \u3/u0/r0_reg[22] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[22]), + .Q(r0[22]), + .R(\ )); + FDRE \u3/u0/r0_reg[23] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[23]), + .Q(r0[23]), + .R(\ )); + FDRE \u3/u0/r0_reg[24] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[24]), + .Q(r0[24]), + .R(\ )); + FDRE \u3/u0/r0_reg[25] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[25]), + .Q(r0[25]), + .R(\ )); + FDRE \u3/u0/r0_reg[26] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[26]), + .Q(r0[26]), + .R(\ )); + FDRE \u3/u0/r0_reg[27] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[27]), + .Q(r0[27]), + .R(\ )); + FDRE \u3/u0/r0_reg[28] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[28]), + .Q(r0[28]), + .R(\ )); + FDRE \u3/u0/r0_reg[29] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[29]), + .Q(r0[29]), + .R(\ )); + FDRE \u3/u0/r0_reg[2] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[2]), + .Q(r0[2]), + .R(\ )); + FDRE \u3/u0/r0_reg[30] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[30]), + .Q(r0[30]), + .R(\ )); + FDRE \u3/u0/r0_reg[31] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[31]), + .Q(r0[31]), + .R(\ )); + FDRE \u3/u0/r0_reg[32] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[32]), + .Q(r0[32]), + .R(\ )); + FDRE \u3/u0/r0_reg[33] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[33]), + .Q(r0[33]), + .R(\ )); + FDRE \u3/u0/r0_reg[34] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[34]), + .Q(r0[34]), + .R(\ )); + FDRE \u3/u0/r0_reg[35] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[35]), + .Q(r0[35]), + .R(\ )); + FDRE \u3/u0/r0_reg[3] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[3]), + .Q(r0[3]), + .R(\ )); + FDRE \u3/u0/r0_reg[4] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[4]), + .Q(r0[4]), + .R(\ )); + FDRE \u3/u0/r0_reg[5] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[5]), + .Q(r0[5]), + .R(\ )); + FDRE \u3/u0/r0_reg[6] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[6]), + .Q(r0[6]), + .R(\ )); + FDRE \u3/u0/r0_reg[7] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[7]), + .Q(r0[7]), + .R(\ )); + FDRE \u3/u0/r0_reg[8] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[8]), + .Q(r0[8]), + .R(\ )); + FDRE \u3/u0/r0_reg[9] + (.C(clk_i), + .CE(\u3/u0/r00 ), + .D(mc_data_ir[9]), + .Q(r0[9]), + .R(\ )); + FDRE \u3/u0/r1_reg[0] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[0]), + .Q(r1[0]), + .R(\ )); + FDRE \u3/u0/r1_reg[10] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[10]), + .Q(r1[10]), + .R(\ )); + FDRE \u3/u0/r1_reg[11] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[11]), + .Q(r1[11]), + .R(\ )); + FDRE \u3/u0/r1_reg[12] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[12]), + .Q(r1[12]), + .R(\ )); + FDRE \u3/u0/r1_reg[13] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[13]), + .Q(r1[13]), + .R(\ )); + FDRE \u3/u0/r1_reg[14] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[14]), + .Q(r1[14]), + .R(\ )); + FDRE \u3/u0/r1_reg[15] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[15]), + .Q(r1[15]), + .R(\ )); + FDRE \u3/u0/r1_reg[16] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[16]), + .Q(r1[16]), + .R(\ )); + FDRE \u3/u0/r1_reg[17] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[17]), + .Q(r1[17]), + .R(\ )); + FDRE \u3/u0/r1_reg[18] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[18]), + .Q(r1[18]), + .R(\ )); + FDRE \u3/u0/r1_reg[19] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[19]), + .Q(r1[19]), + .R(\ )); + FDRE \u3/u0/r1_reg[1] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[1]), + .Q(r1[1]), + .R(\ )); + FDRE \u3/u0/r1_reg[20] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[20]), + .Q(r1[20]), + .R(\ )); + FDRE \u3/u0/r1_reg[21] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[21]), + .Q(r1[21]), + .R(\ )); + FDRE \u3/u0/r1_reg[22] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[22]), + .Q(r1[22]), + .R(\ )); + FDRE \u3/u0/r1_reg[23] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[23]), + .Q(r1[23]), + .R(\ )); + FDRE \u3/u0/r1_reg[24] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[24]), + .Q(r1[24]), + .R(\ )); + FDRE \u3/u0/r1_reg[25] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[25]), + .Q(r1[25]), + .R(\ )); + FDRE \u3/u0/r1_reg[26] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[26]), + .Q(r1[26]), + .R(\ )); + FDRE \u3/u0/r1_reg[27] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[27]), + .Q(r1[27]), + .R(\ )); + FDRE \u3/u0/r1_reg[28] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[28]), + .Q(r1[28]), + .R(\ )); + FDRE \u3/u0/r1_reg[29] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[29]), + .Q(r1[29]), + .R(\ )); + FDRE \u3/u0/r1_reg[2] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[2]), + .Q(r1[2]), + .R(\ )); + FDRE \u3/u0/r1_reg[30] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[30]), + .Q(r1[30]), + .R(\ )); + FDRE \u3/u0/r1_reg[31] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[31]), + .Q(r1[31]), + .R(\ )); + FDRE \u3/u0/r1_reg[32] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[32]), + .Q(r1[32]), + .R(\ )); + FDRE \u3/u0/r1_reg[33] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[33]), + .Q(r1[33]), + .R(\ )); + FDRE \u3/u0/r1_reg[34] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[34]), + .Q(r1[34]), + .R(\ )); + FDRE \u3/u0/r1_reg[35] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[35]), + .Q(r1[35]), + .R(\ )); + FDRE \u3/u0/r1_reg[3] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[3]), + .Q(r1[3]), + .R(\ )); + FDRE \u3/u0/r1_reg[4] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[4]), + .Q(r1[4]), + .R(\ )); + FDRE \u3/u0/r1_reg[5] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[5]), + .Q(r1[5]), + .R(\ )); + FDRE \u3/u0/r1_reg[6] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[6]), + .Q(r1[6]), + .R(\ )); + FDRE \u3/u0/r1_reg[7] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[7]), + .Q(r1[7]), + .R(\ )); + FDRE \u3/u0/r1_reg[8] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[8]), + .Q(r1[8]), + .R(\ )); + FDRE \u3/u0/r1_reg[9] + (.C(clk_i), + .CE(\u3/u0/r10 ), + .D(mc_data_ir[9]), + .Q(r1[9]), + .R(\ )); + FDRE \u3/u0/r2_reg[0] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[0]), + .Q(r2[0]), + .R(\ )); + FDRE \u3/u0/r2_reg[10] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[10]), + .Q(r2[10]), + .R(\ )); + FDRE \u3/u0/r2_reg[11] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[11]), + .Q(r2[11]), + .R(\ )); + FDRE \u3/u0/r2_reg[12] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[12]), + .Q(r2[12]), + .R(\ )); + FDRE \u3/u0/r2_reg[13] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[13]), + .Q(r2[13]), + .R(\ )); + FDRE \u3/u0/r2_reg[14] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[14]), + .Q(r2[14]), + .R(\ )); + FDRE \u3/u0/r2_reg[15] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[15]), + .Q(r2[15]), + .R(\ )); + FDRE \u3/u0/r2_reg[16] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[16]), + .Q(r2[16]), + .R(\ )); + FDRE \u3/u0/r2_reg[17] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[17]), + .Q(r2[17]), + .R(\ )); + FDRE \u3/u0/r2_reg[18] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[18]), + .Q(r2[18]), + .R(\ )); + FDRE \u3/u0/r2_reg[19] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[19]), + .Q(r2[19]), + .R(\ )); + FDRE \u3/u0/r2_reg[1] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[1]), + .Q(r2[1]), + .R(\ )); + FDRE \u3/u0/r2_reg[20] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[20]), + .Q(r2[20]), + .R(\ )); + FDRE \u3/u0/r2_reg[21] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[21]), + .Q(r2[21]), + .R(\ )); + FDRE \u3/u0/r2_reg[22] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[22]), + .Q(r2[22]), + .R(\ )); + FDRE \u3/u0/r2_reg[23] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[23]), + .Q(r2[23]), + .R(\ )); + FDRE \u3/u0/r2_reg[24] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[24]), + .Q(r2[24]), + .R(\ )); + FDRE \u3/u0/r2_reg[25] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[25]), + .Q(r2[25]), + .R(\ )); + FDRE \u3/u0/r2_reg[26] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[26]), + .Q(r2[26]), + .R(\ )); + FDRE \u3/u0/r2_reg[27] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[27]), + .Q(r2[27]), + .R(\ )); + FDRE \u3/u0/r2_reg[28] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[28]), + .Q(r2[28]), + .R(\ )); + FDRE \u3/u0/r2_reg[29] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[29]), + .Q(r2[29]), + .R(\ )); + FDRE \u3/u0/r2_reg[2] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[2]), + .Q(r2[2]), + .R(\ )); + FDRE \u3/u0/r2_reg[30] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[30]), + .Q(r2[30]), + .R(\ )); + FDRE \u3/u0/r2_reg[31] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[31]), + .Q(r2[31]), + .R(\ )); + FDRE \u3/u0/r2_reg[32] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[32]), + .Q(r2[32]), + .R(\ )); + FDRE \u3/u0/r2_reg[33] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[33]), + .Q(r2[33]), + .R(\ )); + FDRE \u3/u0/r2_reg[34] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[34]), + .Q(r2[34]), + .R(\ )); + FDRE \u3/u0/r2_reg[35] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[35]), + .Q(r2[35]), + .R(\ )); + FDRE \u3/u0/r2_reg[3] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[3]), + .Q(r2[3]), + .R(\ )); + FDRE \u3/u0/r2_reg[4] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[4]), + .Q(r2[4]), + .R(\ )); + FDRE \u3/u0/r2_reg[5] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[5]), + .Q(r2[5]), + .R(\ )); + FDRE \u3/u0/r2_reg[6] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[6]), + .Q(r2[6]), + .R(\ )); + FDRE \u3/u0/r2_reg[7] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[7]), + .Q(r2[7]), + .R(\ )); + FDRE \u3/u0/r2_reg[8] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[8]), + .Q(r2[8]), + .R(\ )); + FDRE \u3/u0/r2_reg[9] + (.C(clk_i), + .CE(\u3/u0/r20 ), + .D(mc_data_ir[9]), + .Q(r2[9]), + .R(\ )); + FDRE \u3/u0/r3_reg[0] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[0]), + .Q(r3[0]), + .R(\ )); + FDRE \u3/u0/r3_reg[10] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[10]), + .Q(r3[10]), + .R(\ )); + FDRE \u3/u0/r3_reg[11] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[11]), + .Q(r3[11]), + .R(\ )); + FDRE \u3/u0/r3_reg[12] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[12]), + .Q(r3[12]), + .R(\ )); + FDRE \u3/u0/r3_reg[13] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[13]), + .Q(r3[13]), + .R(\ )); + FDRE \u3/u0/r3_reg[14] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[14]), + .Q(r3[14]), + .R(\ )); + FDRE \u3/u0/r3_reg[15] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[15]), + .Q(r3[15]), + .R(\ )); + FDRE \u3/u0/r3_reg[16] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[16]), + .Q(r3[16]), + .R(\ )); + FDRE \u3/u0/r3_reg[17] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[17]), + .Q(r3[17]), + .R(\ )); + FDRE \u3/u0/r3_reg[18] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[18]), + .Q(r3[18]), + .R(\ )); + FDRE \u3/u0/r3_reg[19] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[19]), + .Q(r3[19]), + .R(\ )); + FDRE \u3/u0/r3_reg[1] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[1]), + .Q(r3[1]), + .R(\ )); + FDRE \u3/u0/r3_reg[20] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[20]), + .Q(r3[20]), + .R(\ )); + FDRE \u3/u0/r3_reg[21] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[21]), + .Q(r3[21]), + .R(\ )); + FDRE \u3/u0/r3_reg[22] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[22]), + .Q(r3[22]), + .R(\ )); + FDRE \u3/u0/r3_reg[23] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[23]), + .Q(r3[23]), + .R(\ )); + FDRE \u3/u0/r3_reg[24] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[24]), + .Q(r3[24]), + .R(\ )); + FDRE \u3/u0/r3_reg[25] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[25]), + .Q(r3[25]), + .R(\ )); + FDRE \u3/u0/r3_reg[26] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[26]), + .Q(r3[26]), + .R(\ )); + FDRE \u3/u0/r3_reg[27] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[27]), + .Q(r3[27]), + .R(\ )); + FDRE \u3/u0/r3_reg[28] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[28]), + .Q(r3[28]), + .R(\ )); + FDRE \u3/u0/r3_reg[29] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[29]), + .Q(r3[29]), + .R(\ )); + FDRE \u3/u0/r3_reg[2] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[2]), + .Q(r3[2]), + .R(\ )); + FDRE \u3/u0/r3_reg[30] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[30]), + .Q(r3[30]), + .R(\ )); + FDRE \u3/u0/r3_reg[31] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[31]), + .Q(r3[31]), + .R(\ )); + FDRE \u3/u0/r3_reg[32] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[32]), + .Q(r3[32]), + .R(\ )); + FDRE \u3/u0/r3_reg[33] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[33]), + .Q(r3[33]), + .R(\ )); + FDRE \u3/u0/r3_reg[34] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[34]), + .Q(r3[34]), + .R(\ )); + FDRE \u3/u0/r3_reg[35] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[35]), + .Q(r3[35]), + .R(\ )); + FDRE \u3/u0/r3_reg[3] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[3]), + .Q(r3[3]), + .R(\ )); + FDRE \u3/u0/r3_reg[4] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[4]), + .Q(r3[4]), + .R(\ )); + FDRE \u3/u0/r3_reg[5] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[5]), + .Q(r3[5]), + .R(\ )); + FDRE \u3/u0/r3_reg[6] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[6]), + .Q(r3[6]), + .R(\ )); + FDRE \u3/u0/r3_reg[7] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[7]), + .Q(r3[7]), + .R(\ )); + FDRE \u3/u0/r3_reg[8] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[8]), + .Q(r3[8]), + .R(\ )); + FDRE \u3/u0/r3_reg[9] + (.C(clk_i), + .CE(\u3/u0/r30 ), + .D(mc_data_ir[9]), + .Q(r3[9]), + .R(\ )); + FDPE \u3/u0/rd_adr_reg[0] + (.C(clk_i), + .CE(\rd_adr[3]_i_1_n_0 ), + .D(\rd_adr[0]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u3/u0/rd_adr [0])); + FDCE \u3/u0/rd_adr_reg[1] + (.C(clk_i), + .CE(\rd_adr[3]_i_1_n_0 ), + .CLR(rst_i), + .D(\rd_adr[1]_i_1_n_0 ), + .Q(\u3/u0/rd_adr [1])); + FDCE \u3/u0/rd_adr_reg[2] + (.C(clk_i), + .CE(\rd_adr[3]_i_1_n_0 ), + .CLR(rst_i), + .D(\rd_adr[2]_i_1_n_0 ), + .Q(\u3/u0/rd_adr [2])); + FDCE \u3/u0/rd_adr_reg[3] + (.C(clk_i), + .CE(\rd_adr[3]_i_1_n_0 ), + .CLR(rst_i), + .D(\rd_adr[3]_i_2_n_0 ), + .Q(\u3/u0/rd_adr [3])); + FDPE \u3/u0/wr_adr_reg[0] + (.C(clk_i), + .CE(\wr_adr[3]_i_1_n_0 ), + .D(\wr_adr[0]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u3/u0/wr_adr_reg_n_0_[0] )); + FDCE \u3/u0/wr_adr_reg[1] + (.C(clk_i), + .CE(\wr_adr[3]_i_1_n_0 ), + .CLR(rst_i), + .D(\wr_adr[1]_i_1_n_0 ), + .Q(\u3/u0/p_0_in1_in )); + FDCE \u3/u0/wr_adr_reg[2] + (.C(clk_i), + .CE(\wr_adr[3]_i_1_n_0 ), + .CLR(rst_i), + .D(\wr_adr[2]_i_1_n_0 ), + .Q(\u3/u0/p_0_in0_in )); + FDCE \u3/u0/wr_adr_reg[3] + (.C(clk_i), + .CE(\wr_adr[3]_i_1_n_0 ), + .CLR(rst_i), + .D(\wr_adr[3]_i_2_n_0 ), + .Q(\u3/u0/p_0_in )); + FDCE \u4/ps_cnt_reg[0] + (.C(clk_i), + .CE(\ps_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__1[0]), + .Q(\u4/ps_cnt_reg [0])); + FDCE \u4/ps_cnt_reg[1] + (.C(clk_i), + .CE(\ps_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__1[1]), + .Q(\u4/ps_cnt_reg [1])); + FDCE \u4/ps_cnt_reg[2] + (.C(clk_i), + .CE(\ps_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__1[2]), + .Q(\u4/ps_cnt_reg [2])); + FDCE \u4/ps_cnt_reg[3] + (.C(clk_i), + .CE(\ps_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__1[3]), + .Q(\u4/ps_cnt_reg [3])); + FDCE \u4/ps_cnt_reg[4] + (.C(clk_i), + .CE(\ps_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__1[4]), + .Q(\u4/ps_cnt_reg [4])); + FDCE \u4/ps_cnt_reg[5] + (.C(clk_i), + .CE(\ps_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__1[5]), + .Q(\u4/ps_cnt_reg [5])); + FDCE \u4/ps_cnt_reg[6] + (.C(clk_i), + .CE(\ps_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__1[6]), + .Q(\u4/ps_cnt_reg [6])); + FDCE \u4/ps_cnt_reg[7] + (.C(clk_i), + .CE(\ps_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__1[7]), + .Q(\u4/ps_cnt_reg [7])); + FDCE \u4/rfr_ce_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u4/ps_cnt_clr ), + .Q(\u4/rfr_ce )); + FDRE \u4/rfr_clr_reg + (.C(clk_i), + .CE(\ ), + .D(\u4/rfr_clr ), + .Q(\u4/rfr_clr_reg_n_0 ), + .R(\ )); + FDCE \u4/rfr_cnt_reg[0] + (.C(clk_i), + .CE(\rfr_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__2[0]), + .Q(\u4/rfr_cnt_reg )); + FDCE \u4/rfr_cnt_reg[1] + (.C(clk_i), + .CE(\rfr_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__2[1]), + .Q(\u4/rfr_cnt_reg__0 [1])); + FDCE \u4/rfr_cnt_reg[2] + (.C(clk_i), + .CE(\rfr_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(\rfr_cnt[2]_i_1_n_0 ), + .Q(\u4/rfr_cnt_reg__0 [2])); + FDCE \u4/rfr_cnt_reg[3] + (.C(clk_i), + .CE(\rfr_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__2[3]), + .Q(\u4/rfr_cnt_reg__0 [3])); + FDCE \u4/rfr_cnt_reg[4] + (.C(clk_i), + .CE(\rfr_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(\rfr_cnt[4]_i_1_n_0 ), + .Q(\u4/rfr_cnt_reg__0 [4])); + FDCE \u4/rfr_cnt_reg[5] + (.C(clk_i), + .CE(\rfr_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__2[5]), + .Q(\u4/rfr_cnt_reg__0 [5])); + FDCE \u4/rfr_cnt_reg[6] + (.C(clk_i), + .CE(\rfr_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(\rfr_cnt[6]_i_1_n_0 ), + .Q(\u4/rfr_cnt_reg__0 [6])); + FDCE \u4/rfr_cnt_reg[7] + (.C(clk_i), + .CE(\rfr_cnt[7]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__2[7]), + .Q(\u4/rfr_cnt_reg__0 [7])); + FDCE \u4/rfr_early_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u4/ps_cnt_clr01_in ), + .Q(\u4/rfr_early )); + FDCE \u4/rfr_en_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(rfr_en_i_1_n_0), + .Q(\u4/rfr_en )); + FDCE \u4/rfr_req_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(rfr_req_i_1_n_0), + .Q(rfr_req)); + (* FSM_ENCODED_STATES = "ACTIVATE_W:0010110,ACS_RD2:0101101,SUSP4:0010000,SCS_RD2:0110011,ACS_WR3:0100010,LMR0:0001010,SCS_ERR:0110100,BG0:0111110,IDLE:0000001,RESUME2:0010010,SCS_WR1:0110000,POR:0000000,BG1:0111111,INIT_REFR1_W:0001000,SRAM_RD4:0111101,IDLE_T:1000001,ACS_RD_8_6:0101011,SD_WR_W:0011000,SRAM_RD2:0111011,INIT_W:0000110,BG2:1000000,IDLE_T2:0110101,SRAM_WR:0110110,INIT_LMR:0001001,ACS_RD_8_4:0101001,SD_RD_W2:0011101,ACS_RD3:0101110,RESUME1:0010001,SD_RD_WR:0010100,SCS_WR:0101111,ACS_WR:0011111,BT:0011100,SRAM_RD0:0111001,INIT0:0000100,INIT_REFR1:0000111,SRAM_RD3:0111100,LMR2:0001100,SRAM_RD:0111000,ACS_RD:0100100,PRECHARGE:0000010,SUSP1:0001101,SRAM_WR0:0110111,PRECHARGE_W:0000011,ACS_RD1:0100101,SUSP2:0001110,SCS_RD:0110001,SD_RD_W:0011010,ACS_RD_8_2:0100111,SUSP3:0001111,ACTIVATE:0010101,ACS_RD2A:0101100,SCS_RD1:0110010,ACS_RD_8_5:0101010,SD_WR:0010111,SD_RD_LOOP:0011011,ACS_RD_8_3:0101000,ACS_WR4:0100011,LMR1:0001011,ACS_RD_8_1:0100110,SD_RD:0011001,ACS_WR1:0100000,BT_W:0011110,ACS_WR2:0100001,REFR:0010011,SRAM_RD1:0111010,INIT:0000101" *) + FDCE \u5/FSM_sequential_state_reg[0] + (.C(clk_i), + .CE(\FSM_sequential_state[6]_i_1_n_0 ), + .CLR(rst_i), + .D(\FSM_sequential_state[0]_i_1_n_0 ), + .Q(\u5/state [0])); + (* FSM_ENCODED_STATES = "ACTIVATE_W:0010110,ACS_RD2:0101101,SUSP4:0010000,SCS_RD2:0110011,ACS_WR3:0100010,LMR0:0001010,SCS_ERR:0110100,BG0:0111110,IDLE:0000001,RESUME2:0010010,SCS_WR1:0110000,POR:0000000,BG1:0111111,INIT_REFR1_W:0001000,SRAM_RD4:0111101,IDLE_T:1000001,ACS_RD_8_6:0101011,SD_WR_W:0011000,SRAM_RD2:0111011,INIT_W:0000110,BG2:1000000,IDLE_T2:0110101,SRAM_WR:0110110,INIT_LMR:0001001,ACS_RD_8_4:0101001,SD_RD_W2:0011101,ACS_RD3:0101110,RESUME1:0010001,SD_RD_WR:0010100,SCS_WR:0101111,ACS_WR:0011111,BT:0011100,SRAM_RD0:0111001,INIT0:0000100,INIT_REFR1:0000111,SRAM_RD3:0111100,LMR2:0001100,SRAM_RD:0111000,ACS_RD:0100100,PRECHARGE:0000010,SUSP1:0001101,SRAM_WR0:0110111,PRECHARGE_W:0000011,ACS_RD1:0100101,SUSP2:0001110,SCS_RD:0110001,SD_RD_W:0011010,ACS_RD_8_2:0100111,SUSP3:0001111,ACTIVATE:0010101,ACS_RD2A:0101100,SCS_RD1:0110010,ACS_RD_8_5:0101010,SD_WR:0010111,SD_RD_LOOP:0011011,ACS_RD_8_3:0101000,ACS_WR4:0100011,LMR1:0001011,ACS_RD_8_1:0100110,SD_RD:0011001,ACS_WR1:0100000,BT_W:0011110,ACS_WR2:0100001,REFR:0010011,SRAM_RD1:0111010,INIT:0000101" *) + FDCE \u5/FSM_sequential_state_reg[1] + (.C(clk_i), + .CE(\FSM_sequential_state[6]_i_1_n_0 ), + .CLR(rst_i), + .D(\FSM_sequential_state[1]_i_1_n_0 ), + .Q(\u5/state [1])); + (* FSM_ENCODED_STATES = "ACTIVATE_W:0010110,ACS_RD2:0101101,SUSP4:0010000,SCS_RD2:0110011,ACS_WR3:0100010,LMR0:0001010,SCS_ERR:0110100,BG0:0111110,IDLE:0000001,RESUME2:0010010,SCS_WR1:0110000,POR:0000000,BG1:0111111,INIT_REFR1_W:0001000,SRAM_RD4:0111101,IDLE_T:1000001,ACS_RD_8_6:0101011,SD_WR_W:0011000,SRAM_RD2:0111011,INIT_W:0000110,BG2:1000000,IDLE_T2:0110101,SRAM_WR:0110110,INIT_LMR:0001001,ACS_RD_8_4:0101001,SD_RD_W2:0011101,ACS_RD3:0101110,RESUME1:0010001,SD_RD_WR:0010100,SCS_WR:0101111,ACS_WR:0011111,BT:0011100,SRAM_RD0:0111001,INIT0:0000100,INIT_REFR1:0000111,SRAM_RD3:0111100,LMR2:0001100,SRAM_RD:0111000,ACS_RD:0100100,PRECHARGE:0000010,SUSP1:0001101,SRAM_WR0:0110111,PRECHARGE_W:0000011,ACS_RD1:0100101,SUSP2:0001110,SCS_RD:0110001,SD_RD_W:0011010,ACS_RD_8_2:0100111,SUSP3:0001111,ACTIVATE:0010101,ACS_RD2A:0101100,SCS_RD1:0110010,ACS_RD_8_5:0101010,SD_WR:0010111,SD_RD_LOOP:0011011,ACS_RD_8_3:0101000,ACS_WR4:0100011,LMR1:0001011,ACS_RD_8_1:0100110,SD_RD:0011001,ACS_WR1:0100000,BT_W:0011110,ACS_WR2:0100001,REFR:0010011,SRAM_RD1:0111010,INIT:0000101" *) + FDCE \u5/FSM_sequential_state_reg[2] + (.C(clk_i), + .CE(\FSM_sequential_state[6]_i_1_n_0 ), + .CLR(rst_i), + .D(\FSM_sequential_state[2]_i_1_n_0 ), + .Q(\u5/state [2])); + (* FSM_ENCODED_STATES = "ACTIVATE_W:0010110,ACS_RD2:0101101,SUSP4:0010000,SCS_RD2:0110011,ACS_WR3:0100010,LMR0:0001010,SCS_ERR:0110100,BG0:0111110,IDLE:0000001,RESUME2:0010010,SCS_WR1:0110000,POR:0000000,BG1:0111111,INIT_REFR1_W:0001000,SRAM_RD4:0111101,IDLE_T:1000001,ACS_RD_8_6:0101011,SD_WR_W:0011000,SRAM_RD2:0111011,INIT_W:0000110,BG2:1000000,IDLE_T2:0110101,SRAM_WR:0110110,INIT_LMR:0001001,ACS_RD_8_4:0101001,SD_RD_W2:0011101,ACS_RD3:0101110,RESUME1:0010001,SD_RD_WR:0010100,SCS_WR:0101111,ACS_WR:0011111,BT:0011100,SRAM_RD0:0111001,INIT0:0000100,INIT_REFR1:0000111,SRAM_RD3:0111100,LMR2:0001100,SRAM_RD:0111000,ACS_RD:0100100,PRECHARGE:0000010,SUSP1:0001101,SRAM_WR0:0110111,PRECHARGE_W:0000011,ACS_RD1:0100101,SUSP2:0001110,SCS_RD:0110001,SD_RD_W:0011010,ACS_RD_8_2:0100111,SUSP3:0001111,ACTIVATE:0010101,ACS_RD2A:0101100,SCS_RD1:0110010,ACS_RD_8_5:0101010,SD_WR:0010111,SD_RD_LOOP:0011011,ACS_RD_8_3:0101000,ACS_WR4:0100011,LMR1:0001011,ACS_RD_8_1:0100110,SD_RD:0011001,ACS_WR1:0100000,BT_W:0011110,ACS_WR2:0100001,REFR:0010011,SRAM_RD1:0111010,INIT:0000101" *) + FDCE \u5/FSM_sequential_state_reg[3] + (.C(clk_i), + .CE(\FSM_sequential_state[6]_i_1_n_0 ), + .CLR(rst_i), + .D(\FSM_sequential_state[3]_i_1_n_0 ), + .Q(\u5/state [3])); + (* FSM_ENCODED_STATES = "ACTIVATE_W:0010110,ACS_RD2:0101101,SUSP4:0010000,SCS_RD2:0110011,ACS_WR3:0100010,LMR0:0001010,SCS_ERR:0110100,BG0:0111110,IDLE:0000001,RESUME2:0010010,SCS_WR1:0110000,POR:0000000,BG1:0111111,INIT_REFR1_W:0001000,SRAM_RD4:0111101,IDLE_T:1000001,ACS_RD_8_6:0101011,SD_WR_W:0011000,SRAM_RD2:0111011,INIT_W:0000110,BG2:1000000,IDLE_T2:0110101,SRAM_WR:0110110,INIT_LMR:0001001,ACS_RD_8_4:0101001,SD_RD_W2:0011101,ACS_RD3:0101110,RESUME1:0010001,SD_RD_WR:0010100,SCS_WR:0101111,ACS_WR:0011111,BT:0011100,SRAM_RD0:0111001,INIT0:0000100,INIT_REFR1:0000111,SRAM_RD3:0111100,LMR2:0001100,SRAM_RD:0111000,ACS_RD:0100100,PRECHARGE:0000010,SUSP1:0001101,SRAM_WR0:0110111,PRECHARGE_W:0000011,ACS_RD1:0100101,SUSP2:0001110,SCS_RD:0110001,SD_RD_W:0011010,ACS_RD_8_2:0100111,SUSP3:0001111,ACTIVATE:0010101,ACS_RD2A:0101100,SCS_RD1:0110010,ACS_RD_8_5:0101010,SD_WR:0010111,SD_RD_LOOP:0011011,ACS_RD_8_3:0101000,ACS_WR4:0100011,LMR1:0001011,ACS_RD_8_1:0100110,SD_RD:0011001,ACS_WR1:0100000,BT_W:0011110,ACS_WR2:0100001,REFR:0010011,SRAM_RD1:0111010,INIT:0000101" *) + FDCE \u5/FSM_sequential_state_reg[4] + (.C(clk_i), + .CE(\FSM_sequential_state[6]_i_1_n_0 ), + .CLR(rst_i), + .D(\FSM_sequential_state[4]_i_1_n_0 ), + .Q(\u5/state [4])); + (* FSM_ENCODED_STATES = "ACTIVATE_W:0010110,ACS_RD2:0101101,SUSP4:0010000,SCS_RD2:0110011,ACS_WR3:0100010,LMR0:0001010,SCS_ERR:0110100,BG0:0111110,IDLE:0000001,RESUME2:0010010,SCS_WR1:0110000,POR:0000000,BG1:0111111,INIT_REFR1_W:0001000,SRAM_RD4:0111101,IDLE_T:1000001,ACS_RD_8_6:0101011,SD_WR_W:0011000,SRAM_RD2:0111011,INIT_W:0000110,BG2:1000000,IDLE_T2:0110101,SRAM_WR:0110110,INIT_LMR:0001001,ACS_RD_8_4:0101001,SD_RD_W2:0011101,ACS_RD3:0101110,RESUME1:0010001,SD_RD_WR:0010100,SCS_WR:0101111,ACS_WR:0011111,BT:0011100,SRAM_RD0:0111001,INIT0:0000100,INIT_REFR1:0000111,SRAM_RD3:0111100,LMR2:0001100,SRAM_RD:0111000,ACS_RD:0100100,PRECHARGE:0000010,SUSP1:0001101,SRAM_WR0:0110111,PRECHARGE_W:0000011,ACS_RD1:0100101,SUSP2:0001110,SCS_RD:0110001,SD_RD_W:0011010,ACS_RD_8_2:0100111,SUSP3:0001111,ACTIVATE:0010101,ACS_RD2A:0101100,SCS_RD1:0110010,ACS_RD_8_5:0101010,SD_WR:0010111,SD_RD_LOOP:0011011,ACS_RD_8_3:0101000,ACS_WR4:0100011,LMR1:0001011,ACS_RD_8_1:0100110,SD_RD:0011001,ACS_WR1:0100000,BT_W:0011110,ACS_WR2:0100001,REFR:0010011,SRAM_RD1:0111010,INIT:0000101" *) + FDCE \u5/FSM_sequential_state_reg[5] + (.C(clk_i), + .CE(\FSM_sequential_state[6]_i_1_n_0 ), + .CLR(rst_i), + .D(\FSM_sequential_state[5]_i_1_n_0 ), + .Q(\u5/state [5])); + (* FSM_ENCODED_STATES = "ACTIVATE_W:0010110,ACS_RD2:0101101,SUSP4:0010000,SCS_RD2:0110011,ACS_WR3:0100010,LMR0:0001010,SCS_ERR:0110100,BG0:0111110,IDLE:0000001,RESUME2:0010010,SCS_WR1:0110000,POR:0000000,BG1:0111111,INIT_REFR1_W:0001000,SRAM_RD4:0111101,IDLE_T:1000001,ACS_RD_8_6:0101011,SD_WR_W:0011000,SRAM_RD2:0111011,INIT_W:0000110,BG2:1000000,IDLE_T2:0110101,SRAM_WR:0110110,INIT_LMR:0001001,ACS_RD_8_4:0101001,SD_RD_W2:0011101,ACS_RD3:0101110,RESUME1:0010001,SD_RD_WR:0010100,SCS_WR:0101111,ACS_WR:0011111,BT:0011100,SRAM_RD0:0111001,INIT0:0000100,INIT_REFR1:0000111,SRAM_RD3:0111100,LMR2:0001100,SRAM_RD:0111000,ACS_RD:0100100,PRECHARGE:0000010,SUSP1:0001101,SRAM_WR0:0110111,PRECHARGE_W:0000011,ACS_RD1:0100101,SUSP2:0001110,SCS_RD:0110001,SD_RD_W:0011010,ACS_RD_8_2:0100111,SUSP3:0001111,ACTIVATE:0010101,ACS_RD2A:0101100,SCS_RD1:0110010,ACS_RD_8_5:0101010,SD_WR:0010111,SD_RD_LOOP:0011011,ACS_RD_8_3:0101000,ACS_WR4:0100011,LMR1:0001011,ACS_RD_8_1:0100110,SD_RD:0011001,ACS_WR1:0100000,BT_W:0011110,ACS_WR2:0100001,REFR:0010011,SRAM_RD1:0111010,INIT:0000101" *) + FDCE \u5/FSM_sequential_state_reg[6] + (.C(clk_i), + .CE(\FSM_sequential_state[6]_i_1_n_0 ), + .CLR(rst_i), + .D(\FSM_sequential_state[6]_i_2_n_0 ), + .Q(\u5/state [6])); + FDCE \u5/ack_cnt_reg[0] + (.C(clk_i), + .CE(\ack_cnt[3]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__0[0]), + .Q(\u5/ack_cnt_reg [0])); + FDCE \u5/ack_cnt_reg[1] + (.C(clk_i), + .CE(\ack_cnt[3]_i_1_n_0 ), + .CLR(rst_i), + .D(\ack_cnt[1]_i_1_n_0 ), + .Q(\u5/ack_cnt_reg [1])); + FDCE \u5/ack_cnt_reg[2] + (.C(clk_i), + .CE(\ack_cnt[3]_i_1_n_0 ), + .CLR(rst_i), + .D(\ack_cnt[2]_i_1_n_0 ), + .Q(\u5/ack_cnt_reg [2])); + FDCE \u5/ack_cnt_reg[3] + (.C(clk_i), + .CE(\ack_cnt[3]_i_1_n_0 ), + .CLR(rst_i), + .D(p_0_in__0[3]), + .Q(\u5/ack_cnt_reg [3])); + FDCE \u5/ap_en_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(ap_en_i_1_n_0), + .Q(\u5/ap_en )); + FDRE \u5/burst_act_rd_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/burst_act077_in ), + .Q(\u5/burst_act_rd ), + .R(\ )); + FDRE \u5/burst_cnt_reg[0] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[0]), + .Q(\u5/burst_cnt_reg [0]), + .R(\u5/burst_cnt_ld_4 )); + FDRE \u5/burst_cnt_reg[10] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[10]), + .Q(\u5/burst_cnt_reg [10]), + .R(\u5/burst_cnt_ld_4 )); + FDRE \u5/burst_cnt_reg[1] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[1]), + .Q(\u5/burst_cnt_reg [1]), + .R(\u5/burst_cnt_ld_4 )); + FDSE \u5/burst_cnt_reg[2] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[2]), + .Q(\u5/burst_cnt_reg [2]), + .S(\u5/burst_cnt_ld_4 )); + FDRE \u5/burst_cnt_reg[3] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[3]), + .Q(\u5/burst_cnt_reg [3]), + .R(\u5/burst_cnt_ld_4 )); + FDRE \u5/burst_cnt_reg[4] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[4]), + .Q(\u5/burst_cnt_reg [4]), + .R(\u5/burst_cnt_ld_4 )); + FDRE \u5/burst_cnt_reg[5] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[5]), + .Q(\u5/burst_cnt_reg [5]), + .R(\u5/burst_cnt_ld_4 )); + FDRE \u5/burst_cnt_reg[6] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[6]), + .Q(\u5/burst_cnt_reg [6]), + .R(\u5/burst_cnt_ld_4 )); + FDRE \u5/burst_cnt_reg[7] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[7]), + .Q(\u5/burst_cnt_reg [7]), + .R(\u5/burst_cnt_ld_4 )); + FDRE \u5/burst_cnt_reg[8] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[8]), + .Q(\u5/burst_cnt_reg [8]), + .R(\u5/burst_cnt_ld_4 )); + FDRE \u5/burst_cnt_reg[9] + (.C(clk_i), + .CE(\burst_cnt[10]_i_2_n_0 ), + .D(p_0_in[9]), + .Q(\u5/burst_cnt_reg [9]), + .R(\u5/burst_cnt_ld_4 )); + FDRE \u5/cke__reg + (.C(clk_i), + .CE(\ ), + .D(\u5/cke_0 ), + .Q(mc_cke_pad_o_), + .R(\ )); + FDRE \u5/cke_o_del_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/cke_o_r2_reg_srl2_n_0 ), + .Q(\u5/cke_o_del ), + .R(\ )); + (* srl_name = "\u5/cke_o_r2_reg_srl2 " *) + SRL16E \u5/cke_o_r2_reg_srl2 + (.A0(\ ), + .A1(\ ), + .A2(\ ), + .A3(\ ), + .CE(\ ), + .CLK(clk_i), + .D(mc_cke_pad_o_), + .Q(\u5/cke_o_r2_reg_srl2_n_0 )); + FDRE \u5/cke_r_reg + (.C(clk_i), + .CE(\ ), + .D(cke_r_i_1_n_0), + .Q(\u5/cke_r ), + .R(\ )); + FDRE \u5/cmd_a10_r_reg + (.C(clk_i), + .CE(\ ), + .D(cmd_a10), + .Q(\u5/cmd_a10_r ), + .R(\ )); + FDCE \u5/cmd_asserted2_reg + (.C(clk_i), + .CE(mc_le_i_1_n_0), + .CLR(rst_i), + .D(\u5/cmd_asserted ), + .Q(\u5/cmd_asserted2 )); + FDCE \u5/cmd_asserted_reg + (.C(clk_i), + .CE(mc_le_i_1_n_0), + .CLR(rst_i), + .D(cmd_asserted_i_1_n_0), + .Q(\u5/cmd_asserted )); + FDPE \u5/cmd_del_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\u5/cmd_r [0]), + .PRE(rst_i), + .Q(\u5/cmd_del [0])); + FDPE \u5/cmd_del_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u5/cmd_r [1]), + .PRE(rst_i), + .Q(\u5/cmd_del [1])); + FDPE \u5/cmd_del_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\u5/cmd_r [2]), + .PRE(rst_i), + .Q(\u5/cmd_del [2])); + FDCE \u5/cmd_del_reg[3] + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u5/cmd_r [3]), + .Q(\u5/cmd_del [3])); + FDPE \u5/cmd_r_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\u5/cmd [0]), + .PRE(rst_i), + .Q(\u5/cmd_r [0])); + FDPE \u5/cmd_r_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\u5/cmd [1]), + .PRE(rst_i), + .Q(\u5/cmd_r [1])); + FDPE \u5/cmd_r_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\u5/cmd [2]), + .PRE(rst_i), + .Q(\u5/cmd_r [2])); + FDCE \u5/cmd_r_reg[3] + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(cmd_asserted_i_1_n_0), + .Q(\u5/cmd_r [3])); + FDRE \u5/cnt_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/cnt_next ), + .Q(\u5/cnt ), + .R(\ )); + FDRE \u5/cs_le_r1_reg + (.C(clk_i), + .CE(\ ), + .D(cs_le), + .Q(\u5/cs_le_r1 ), + .R(\ )); + FDRE \u5/cs_le_r_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/cs_le_r1 ), + .Q(\u5/cs_le_r ), + .R(\ )); + FDRE \u5/cs_le_reg + (.C(clk_i), + .CE(\ ), + .D(cs_le_d), + .Q(cs_le), + .R(\ )); + FDCE \u5/data_oe_r2_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u5/data_oe_r ), + .Q(\u5/data_oe_r2 )); + FDCE \u5/data_oe_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(data_oe_r_i_1_n_0), + .Q(\u5/data_oe_r )); + FDCE \u5/data_oe_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(data_oe_i_1_n_0), + .Q(data_oe)); + FDCE \u5/dv_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(dv), + .Q(\u5/dv_r )); + FDRE \u5/ir_cnt_done_reg + (.C(clk_i), + .CE(\ ), + .D(ir_cnt_done_i_1_n_0), + .Q(\u5/ir_cnt_done ), + .R(\ )); + FDRE \u5/ir_cnt_reg[0] + (.C(clk_i), + .CE(\u5/ir_cnt_dec ), + .D(ir_cnt0[0]), + .Q(\u5/ir_cnt_reg [0]), + .R(\u5/ir_cnt_ld )); + FDSE \u5/ir_cnt_reg[1] + (.C(clk_i), + .CE(\u5/ir_cnt_dec ), + .D(\ir_cnt[1]_i_1_n_0 ), + .Q(\u5/ir_cnt_reg [1]), + .S(\u5/ir_cnt_ld )); + FDRE \u5/ir_cnt_reg[2] + (.C(clk_i), + .CE(\u5/ir_cnt_dec ), + .D(ir_cnt0[2]), + .Q(\u5/ir_cnt_reg [2]), + .R(\u5/ir_cnt_ld )); + FDRE \u5/ir_cnt_reg[3] + (.C(clk_i), + .CE(\u5/ir_cnt_dec ), + .D(ir_cnt0[3]), + .Q(\u5/ir_cnt_reg [3]), + .R(\u5/ir_cnt_ld )); + FDRE \u5/lmr_ack_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/lmr_ack_d ), + .Q(lmr_ack), + .R(\ )); + FDCE \u5/lookup_ready1_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u5/lookup_ready10 ), + .Q(\u5/lookup_ready1 )); + FDCE \u5/lookup_ready2_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u5/lookup_ready20 ), + .Q(\u5/lookup_ready2 )); + FDCE \u5/mc_adv_r1_reg + (.C(clk_i), + .CE(mc_le_i_1_n_0), + .CLR(rst_i), + .D(mc_adv_d), + .Q(\u5/mc_adv_r1 )); + FDCE \u5/mc_adv_r_reg + (.C(clk_i), + .CE(mc_le_i_1_n_0), + .CLR(rst_i), + .D(\u5/mc_adv_r1 ), + .Q(\u5/mc_adv_r )); + FDCE \u5/mc_c_oe_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u5/mc_c_oe_d ), + .Q(mc_c_oe_d)); + FDCE \u5/mc_le_reg + (.C(clk_i), + .CE(\ ), + .CLR(\u5/rsts ), + .D(mc_le_i_1_n_0), + .Q(\u5/mc_le )); + FDCE \u5/mem_ack_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(mem_ack), + .Q(\u5/mem_ack_r )); + FDCE \u5/no_wb_cycle_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u5/p_65_in ), + .Q(\u5/no_wb_cycle )); + FDPE \u5/oe__reg + (.C(clk_i), + .CE(\ ), + .D(oe__i_1_n_0), + .PRE(rst_i), + .Q(oe_)); + FDRE \u5/pack_le0_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/pack_le0_d ), + .Q(pack_le0), + .R(\ )); + FDRE \u5/pack_le1_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/pack_le1_d ), + .Q(pack_le1), + .R(\ )); + FDRE \u5/pack_le2_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/pack_le2_d ), + .Q(pack_le2), + .R(\ )); + FDCE \u5/resume_req_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(resume_req_i), + .Q(\u5/resume_req_r )); + FDCE \u5/rfr_ack_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(rfr_ack_r_i_1_n_0), + .Q(rfr_ack)); + FDPE \u5/rsts1_reg + (.C(mc_clk_i), + .CE(\ ), + .D(\ ), + .PRE(rst_i), + .Q(\u5/rsts1 )); + FDPE \u5/rsts_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/rsts1 ), + .PRE(rst_i), + .Q(\u5/rsts )); + FDCE \u5/susp_req_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(susp_req_i), + .Q(\u5/susp_req_r )); + FDCE \u5/susp_sel_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(susp_sel_r_i_1_n_0), + .Q(susp_sel)); + FDCE \u5/suspended_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u5/suspended_d ), + .Q(suspended_o)); + FDRE \u5/timer2_reg[0] + (.C(clk_i), + .CE(\u5/timer20 ), + .D(\timer2[0]_i_1_n_0 ), + .Q(\u5/timer2 [0]), + .R(\ )); + FDRE \u5/timer2_reg[1] + (.C(clk_i), + .CE(\u5/timer20 ), + .D(\timer2[1]_i_1_n_0 ), + .Q(\u5/timer2 [1]), + .R(\ )); + FDRE \u5/timer2_reg[2] + (.C(clk_i), + .CE(\u5/timer20 ), + .D(\timer2[2]_i_1_n_0 ), + .Q(\u5/timer2 [2]), + .R(\ )); + FDRE \u5/timer2_reg[3] + (.C(clk_i), + .CE(\u5/timer20 ), + .D(\timer2[3]_i_1_n_0 ), + .Q(\u5/timer2 [3]), + .R(\ )); + FDRE \u5/timer2_reg[4] + (.C(clk_i), + .CE(\u5/timer20 ), + .D(\timer2[4]_i_1_n_0 ), + .Q(\u5/timer2 [4]), + .R(\ )); + FDRE \u5/timer2_reg[5] + (.C(clk_i), + .CE(\u5/timer20 ), + .D(\timer2[5]_i_1_n_0 ), + .Q(\u5/timer2 [5]), + .R(\ )); + FDRE \u5/timer2_reg[6] + (.C(clk_i), + .CE(\u5/timer20 ), + .D(\timer2[6]_i_1_n_0 ), + .Q(\u5/timer2 [6]), + .R(\ )); + FDRE \u5/timer2_reg[7] + (.C(clk_i), + .CE(\u5/timer20 ), + .D(\timer2[7]_i_1_n_0 ), + .Q(\u5/timer2 [7]), + .R(\ )); + FDRE \u5/timer2_reg[8] + (.C(clk_i), + .CE(\u5/timer20 ), + .D(\timer2[8]_i_2_n_0 ), + .Q(\u5/timer2 [8]), + .R(\ )); + FDCE \u5/timer_reg[0] + (.C(clk_i), + .CE(\timer[7]_i_1_n_0 ), + .CLR(rst_i), + .D(\timer[0]_i_1_n_0 ), + .Q(\u5/timer [0])); + FDPE \u5/timer_reg[1] + (.C(clk_i), + .CE(\timer[7]_i_1_n_0 ), + .D(\timer[1]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u5/timer [1])); + FDCE \u5/timer_reg[2] + (.C(clk_i), + .CE(\timer[7]_i_1_n_0 ), + .CLR(rst_i), + .D(\timer[2]_i_1_n_0 ), + .Q(\u5/timer [2])); + FDPE \u5/timer_reg[3] + (.C(clk_i), + .CE(\timer[7]_i_1_n_0 ), + .D(\timer[3]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u5/timer [3])); + FDPE \u5/timer_reg[4] + (.C(clk_i), + .CE(\timer[7]_i_1_n_0 ), + .D(\timer[4]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u5/timer [4])); + FDPE \u5/timer_reg[5] + (.C(clk_i), + .CE(\timer[7]_i_1_n_0 ), + .D(\timer[5]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u5/timer [5])); + FDPE \u5/timer_reg[6] + (.C(clk_i), + .CE(\timer[7]_i_1_n_0 ), + .D(\timer[6]_i_1_n_0 ), + .PRE(rst_i), + .Q(\u5/timer [6])); + FDPE \u5/timer_reg[7] + (.C(clk_i), + .CE(\timer[7]_i_1_n_0 ), + .D(\timer[7]_i_2_n_0 ), + .PRE(rst_i), + .Q(\u5/timer [7])); + FDCE \u5/tmr2_done_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u5/tmr2_done0 ), + .Q(\u5/tmr2_done )); + FDCE \u5/tmr_done_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u5/timer_is_zero ), + .Q(\u5/tmr_done )); + FDCE \u5/wb_cycle_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(wb_cycle_i_1_n_0), + .Q(wb_cycle)); + FDCE \u5/wb_stb_first_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(wb_stb_first_i_1_n_0), + .Q(\u5/wb_stb_first_reg_n_0 )); + FDRE \u5/wb_wait_r2_reg + (.C(clk_i), + .CE(\ ), + .D(wb_wait), + .Q(\u5/wb_wait_r2 ), + .R(\ )); + FDRE \u5/wb_wait_r_reg + (.C(clk_i), + .CE(\ ), + .D(\u5/wb_wait_r2 ), + .Q(\u5/wb_wait_r ), + .R(\ )); + FDRE \u5/wb_write_go_r_reg + (.C(clk_i), + .CE(\ ), + .D(wb_write_go), + .Q(\u5/wb_write_go_r ), + .R(\ )); + FDCE \u5/wr_cycle_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(wr_cycle_i_1_n_0), + .Q(wr_cycle)); + FDCE \u6/read_go_r1_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u6/read_go_r10 ), + .Q(\u6/read_go_r1 )); + FDCE \u6/read_go_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u6/read_go_r0 ), + .Q(\u6/read_go_r )); + FDCE \u6/rmw_en_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(rmw_en_i_1_n_0), + .Q(\u6/rmw_en )); + FDCE \u6/rmw_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u6/rmw_r0 ), + .Q(\u6/rmw_r )); + FDCE \u6/wb_ack_o_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(wb_ack_o_i_1_n_0), + .Q(wb_ack_o)); + FDRE \u6/wb_data_o_reg[0] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[0]_i_1_n_0 ), + .Q(wb_data_o[0]), + .R(\ )); + FDRE \u6/wb_data_o_reg[10] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[10]_i_1_n_0 ), + .Q(wb_data_o[10]), + .R(\ )); + FDRE \u6/wb_data_o_reg[11] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[11]_i_1_n_0 ), + .Q(wb_data_o[11]), + .R(\ )); + FDRE \u6/wb_data_o_reg[12] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[12]_i_1_n_0 ), + .Q(wb_data_o[12]), + .R(\ )); + FDRE \u6/wb_data_o_reg[13] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[13]_i_1_n_0 ), + .Q(wb_data_o[13]), + .R(\ )); + FDRE \u6/wb_data_o_reg[14] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[14]_i_1_n_0 ), + .Q(wb_data_o[14]), + .R(\ )); + FDRE \u6/wb_data_o_reg[15] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[15]_i_1_n_0 ), + .Q(wb_data_o[15]), + .R(\ )); + FDRE \u6/wb_data_o_reg[16] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[16]_i_1_n_0 ), + .Q(wb_data_o[16]), + .R(\ )); + FDRE \u6/wb_data_o_reg[17] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[17]_i_1_n_0 ), + .Q(wb_data_o[17]), + .R(\ )); + FDRE \u6/wb_data_o_reg[18] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[18]_i_1_n_0 ), + .Q(wb_data_o[18]), + .R(\ )); + FDRE \u6/wb_data_o_reg[19] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[19]_i_1_n_0 ), + .Q(wb_data_o[19]), + .R(\ )); + FDRE \u6/wb_data_o_reg[1] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[1]_i_1_n_0 ), + .Q(wb_data_o[1]), + .R(\ )); + FDRE \u6/wb_data_o_reg[20] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[20]_i_1_n_0 ), + .Q(wb_data_o[20]), + .R(\ )); + FDRE \u6/wb_data_o_reg[21] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[21]_i_1_n_0 ), + .Q(wb_data_o[21]), + .R(\ )); + FDRE \u6/wb_data_o_reg[22] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[22]_i_1_n_0 ), + .Q(wb_data_o[22]), + .R(\ )); + FDRE \u6/wb_data_o_reg[23] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[23]_i_1_n_0 ), + .Q(wb_data_o[23]), + .R(\ )); + FDRE \u6/wb_data_o_reg[24] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[24]_i_1_n_0 ), + .Q(wb_data_o[24]), + .R(\ )); + FDRE \u6/wb_data_o_reg[25] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[25]_i_1_n_0 ), + .Q(wb_data_o[25]), + .R(\ )); + FDRE \u6/wb_data_o_reg[26] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[26]_i_1_n_0 ), + .Q(wb_data_o[26]), + .R(\ )); + FDRE \u6/wb_data_o_reg[27] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[27]_i_1_n_0 ), + .Q(wb_data_o[27]), + .R(\ )); + FDRE \u6/wb_data_o_reg[28] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[28]_i_1_n_0 ), + .Q(wb_data_o[28]), + .R(\ )); + FDRE \u6/wb_data_o_reg[29] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[29]_i_1_n_0 ), + .Q(wb_data_o[29]), + .R(\ )); + FDRE \u6/wb_data_o_reg[2] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[2]_i_1_n_0 ), + .Q(wb_data_o[2]), + .R(\ )); + FDRE \u6/wb_data_o_reg[30] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[30]_i_1_n_0 ), + .Q(wb_data_o[30]), + .R(\ )); + FDRE \u6/wb_data_o_reg[31] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[31]_i_1_n_0 ), + .Q(wb_data_o[31]), + .R(\ )); + FDRE \u6/wb_data_o_reg[3] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[3]_i_1_n_0 ), + .Q(wb_data_o[3]), + .R(\ )); + FDRE \u6/wb_data_o_reg[4] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[4]_i_1_n_0 ), + .Q(wb_data_o[4]), + .R(\ )); + FDRE \u6/wb_data_o_reg[5] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[5]_i_1_n_0 ), + .Q(wb_data_o[5]), + .R(\ )); + FDRE \u6/wb_data_o_reg[6] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[6]_i_1_n_0 ), + .Q(wb_data_o[6]), + .R(\ )); + FDRE \u6/wb_data_o_reg[7] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[7]_i_1_n_0 ), + .Q(wb_data_o[7]), + .R(\ )); + FDRE \u6/wb_data_o_reg[8] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[8]_i_1_n_0 ), + .Q(wb_data_o[8]), + .R(\ )); + FDRE \u6/wb_data_o_reg[9] + (.C(clk_i), + .CE(\ ), + .D(\wb_data_o[9]_i_1_n_0 ), + .Q(wb_data_o[9]), + .R(\ )); + FDCE \u6/wb_err_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u6/wb_err0 ), + .Q(wb_err_o)); + FDCE \u6/wb_first_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(wb_first_r_i_1_n_0), + .Q(\u6/wb_first_r )); + FDCE \u6/wr_hold_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(wr_hold_i_1_n_0), + .Q(wr_hold)); + FDCE \u6/write_go_r1_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u6/write_go_r10 ), + .Q(\u6/write_go_r1 )); + FDCE \u6/write_go_r_reg + (.C(clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u6/write_go_r0 ), + .Q(\u6/write_go_r )); + FDRE \u7/mc_ack_r_reg + (.C(mc_clk_i), + .CE(\ ), + .D(mc_ack_pad_i), + .Q(mc_ack_r), + .R(\ )); + FDRE \u7/mc_addr_reg[0] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[0]), + .Q(mc_addr_pad_o[0]), + .R(\ )); + FDRE \u7/mc_addr_reg[10] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[10]), + .Q(mc_addr_pad_o[10]), + .R(\ )); + FDRE \u7/mc_addr_reg[11] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[11]), + .Q(mc_addr_pad_o[11]), + .R(\ )); + FDRE \u7/mc_addr_reg[12] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[12]), + .Q(mc_addr_pad_o[12]), + .R(\ )); + FDRE \u7/mc_addr_reg[13] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[13]), + .Q(mc_addr_pad_o[13]), + .R(\ )); + FDRE \u7/mc_addr_reg[14] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[14]), + .Q(mc_addr_pad_o[14]), + .R(\ )); + FDRE \u7/mc_addr_reg[15] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[15]), + .Q(mc_addr_pad_o[15]), + .R(\ )); + FDRE \u7/mc_addr_reg[16] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[16]), + .Q(mc_addr_pad_o[16]), + .R(\ )); + FDRE \u7/mc_addr_reg[17] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[17]), + .Q(mc_addr_pad_o[17]), + .R(\ )); + FDRE \u7/mc_addr_reg[18] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[18]), + .Q(mc_addr_pad_o[18]), + .R(\ )); + FDRE \u7/mc_addr_reg[19] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[19]), + .Q(mc_addr_pad_o[19]), + .R(\ )); + FDRE \u7/mc_addr_reg[1] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[1]), + .Q(mc_addr_pad_o[1]), + .R(\ )); + FDRE \u7/mc_addr_reg[20] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[20]), + .Q(mc_addr_pad_o[20]), + .R(\ )); + FDRE \u7/mc_addr_reg[21] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[21]), + .Q(mc_addr_pad_o[21]), + .R(\ )); + FDRE \u7/mc_addr_reg[22] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[22]), + .Q(mc_addr_pad_o[22]), + .R(\ )); + FDRE \u7/mc_addr_reg[23] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[23]), + .Q(mc_addr_pad_o[23]), + .R(\ )); + FDRE \u7/mc_addr_reg[2] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[2]), + .Q(mc_addr_pad_o[2]), + .R(\ )); + FDRE \u7/mc_addr_reg[3] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[3]), + .Q(mc_addr_pad_o[3]), + .R(\ )); + FDRE \u7/mc_addr_reg[4] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[4]), + .Q(mc_addr_pad_o[4]), + .R(\ )); + FDRE \u7/mc_addr_reg[5] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[5]), + .Q(mc_addr_pad_o[5]), + .R(\ )); + FDRE \u7/mc_addr_reg[6] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[6]), + .Q(mc_addr_pad_o[6]), + .R(\ )); + FDRE \u7/mc_addr_reg[7] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[7]), + .Q(mc_addr_pad_o[7]), + .R(\ )); + FDRE \u7/mc_addr_reg[8] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[8]), + .Q(mc_addr_pad_o[8]), + .R(\ )); + FDRE \u7/mc_addr_reg[9] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_addr_d[9]), + .Q(mc_addr_pad_o[9]), + .R(\ )); + FDRE \u7/mc_adsc__reg + (.C(mc_clk_i), + .CE(\ ), + .D(mc_adsc__i_1_n_0), + .Q(mc_adsc_pad_o_), + .R(\ )); + FDRE \u7/mc_adv__reg + (.C(mc_clk_i), + .CE(\ ), + .D(mc_adv__i_1_n_0), + .Q(mc_adv_pad_o_), + .R(\ )); + FDRE \u7/mc_bg_reg + (.C(mc_clk_i), + .CE(\ ), + .D(mc_bg_d), + .Q(mc_bg_pad_o), + .R(\ )); + FDRE \u7/mc_br_r_reg + (.C(mc_clk_i), + .CE(\ ), + .D(mc_br_pad_i), + .Q(mc_br_r), + .R(\ )); + FDRE \u7/mc_c_oe_reg + (.C(mc_clk_i), + .CE(\ ), + .D(mc_c_oe_d), + .Q(mc_coe_pad_coe_o), + .R(\ )); + FDRE \u7/mc_cas__reg + (.C(mc_clk_i), + .CE(\ ), + .D(cas_), + .Q(mc_cas_pad_o_), + .R(\ )); + FDPE \u7/mc_cs__reg[0] + (.C(mc_clk_i), + .CE(\ ), + .D(\mc_cs_[0]_i_1_n_0 ), + .PRE(rst_i), + .Q(\^mc_cs_pad_o_ [0])); + FDPE \u7/mc_cs__reg[1] + (.C(mc_clk_i), + .CE(\ ), + .D(\mc_cs_[1]_i_1_n_0 ), + .PRE(rst_i), + .Q(\^mc_cs_pad_o_ [1])); + FDRE \u7/mc_data_ir_reg[0] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[0]), + .Q(mc_data_ir[0]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[10] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[10]), + .Q(mc_data_ir[10]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[11] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[11]), + .Q(mc_data_ir[11]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[12] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[12]), + .Q(mc_data_ir[12]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[13] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[13]), + .Q(mc_data_ir[13]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[14] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[14]), + .Q(mc_data_ir[14]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[15] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[15]), + .Q(mc_data_ir[15]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[16] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[16]), + .Q(mc_data_ir[16]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[17] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[17]), + .Q(mc_data_ir[17]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[18] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[18]), + .Q(mc_data_ir[18]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[19] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[19]), + .Q(mc_data_ir[19]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[1] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[1]), + .Q(mc_data_ir[1]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[20] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[20]), + .Q(mc_data_ir[20]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[21] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[21]), + .Q(mc_data_ir[21]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[22] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[22]), + .Q(mc_data_ir[22]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[23] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[23]), + .Q(mc_data_ir[23]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[24] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[24]), + .Q(mc_data_ir[24]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[25] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[25]), + .Q(mc_data_ir[25]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[26] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[26]), + .Q(mc_data_ir[26]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[27] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[27]), + .Q(mc_data_ir[27]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[28] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[28]), + .Q(mc_data_ir[28]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[29] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[29]), + .Q(mc_data_ir[29]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[2] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[2]), + .Q(mc_data_ir[2]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[30] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[30]), + .Q(mc_data_ir[30]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[31] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[31]), + .Q(mc_data_ir[31]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[32] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_dp_pad_i[0]), + .Q(mc_data_ir[32]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[33] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_dp_pad_i[1]), + .Q(mc_data_ir[33]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[34] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_dp_pad_i[2]), + .Q(mc_data_ir[34]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[35] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_dp_pad_i[3]), + .Q(mc_data_ir[35]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[3] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[3]), + .Q(mc_data_ir[3]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[4] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[4]), + .Q(mc_data_ir[4]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[5] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[5]), + .Q(mc_data_ir[5]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[6] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[6]), + .Q(mc_data_ir[6]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[7] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[7]), + .Q(mc_data_ir[7]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[8] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[8]), + .Q(mc_data_ir[8]), + .R(\ )); + FDRE \u7/mc_data_ir_reg[9] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_pad_i[9]), + .Q(mc_data_ir[9]), + .R(\ )); + FDRE \u7/mc_data_o_reg[0] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[0]), + .Q(mc_data_pad_o[0]), + .R(\ )); + FDRE \u7/mc_data_o_reg[10] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[10]), + .Q(mc_data_pad_o[10]), + .R(\ )); + FDRE \u7/mc_data_o_reg[11] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[11]), + .Q(mc_data_pad_o[11]), + .R(\ )); + FDRE \u7/mc_data_o_reg[12] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[12]), + .Q(mc_data_pad_o[12]), + .R(\ )); + FDRE \u7/mc_data_o_reg[13] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[13]), + .Q(mc_data_pad_o[13]), + .R(\ )); + FDRE \u7/mc_data_o_reg[14] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[14]), + .Q(mc_data_pad_o[14]), + .R(\ )); + FDRE \u7/mc_data_o_reg[15] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[15]), + .Q(mc_data_pad_o[15]), + .R(\ )); + FDRE \u7/mc_data_o_reg[16] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[16]), + .Q(mc_data_pad_o[16]), + .R(\ )); + FDRE \u7/mc_data_o_reg[17] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[17]), + .Q(mc_data_pad_o[17]), + .R(\ )); + FDRE \u7/mc_data_o_reg[18] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[18]), + .Q(mc_data_pad_o[18]), + .R(\ )); + FDRE \u7/mc_data_o_reg[19] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[19]), + .Q(mc_data_pad_o[19]), + .R(\ )); + FDRE \u7/mc_data_o_reg[1] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[1]), + .Q(mc_data_pad_o[1]), + .R(\ )); + FDRE \u7/mc_data_o_reg[20] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[20]), + .Q(mc_data_pad_o[20]), + .R(\ )); + FDRE \u7/mc_data_o_reg[21] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[21]), + .Q(mc_data_pad_o[21]), + .R(\ )); + FDRE \u7/mc_data_o_reg[22] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[22]), + .Q(mc_data_pad_o[22]), + .R(\ )); + FDRE \u7/mc_data_o_reg[23] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[23]), + .Q(mc_data_pad_o[23]), + .R(\ )); + FDRE \u7/mc_data_o_reg[24] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[24]), + .Q(mc_data_pad_o[24]), + .R(\ )); + FDRE \u7/mc_data_o_reg[25] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[25]), + .Q(mc_data_pad_o[25]), + .R(\ )); + FDRE \u7/mc_data_o_reg[26] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[26]), + .Q(mc_data_pad_o[26]), + .R(\ )); + FDRE \u7/mc_data_o_reg[27] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[27]), + .Q(mc_data_pad_o[27]), + .R(\ )); + FDRE \u7/mc_data_o_reg[28] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[28]), + .Q(mc_data_pad_o[28]), + .R(\ )); + FDRE \u7/mc_data_o_reg[29] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[29]), + .Q(mc_data_pad_o[29]), + .R(\ )); + FDRE \u7/mc_data_o_reg[2] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[2]), + .Q(mc_data_pad_o[2]), + .R(\ )); + FDRE \u7/mc_data_o_reg[30] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[30]), + .Q(mc_data_pad_o[30]), + .R(\ )); + FDRE \u7/mc_data_o_reg[31] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[31]), + .Q(mc_data_pad_o[31]), + .R(\ )); + FDRE \u7/mc_data_o_reg[3] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[3]), + .Q(mc_data_pad_o[3]), + .R(\ )); + FDRE \u7/mc_data_o_reg[4] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[4]), + .Q(mc_data_pad_o[4]), + .R(\ )); + FDRE \u7/mc_data_o_reg[5] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[5]), + .Q(mc_data_pad_o[5]), + .R(\ )); + FDRE \u7/mc_data_o_reg[6] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[6]), + .Q(mc_data_pad_o[6]), + .R(\ )); + FDRE \u7/mc_data_o_reg[7] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[7]), + .Q(mc_data_pad_o[7]), + .R(\ )); + FDRE \u7/mc_data_o_reg[8] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[8]), + .Q(mc_data_pad_o[8]), + .R(\ )); + FDRE \u7/mc_data_o_reg[9] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_data_o[9]), + .Q(mc_data_pad_o[9]), + .R(\ )); + FDCE \u7/mc_data_oe_reg + (.C(mc_clk_i), + .CE(\ ), + .CLR(rst_i), + .D(\u7/mc_data_oe0 ), + .Q(mc_doe_pad_doe_o)); + FDRE \u7/mc_dp_o_reg[0] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_dp_o[0]), + .Q(mc_dp_pad_o[0]), + .R(\ )); + FDRE \u7/mc_dp_o_reg[1] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_dp_o[1]), + .Q(mc_dp_pad_o[1]), + .R(\ )); + FDRE \u7/mc_dp_o_reg[2] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_dp_o[2]), + .Q(mc_dp_pad_o[2]), + .R(\ )); + FDRE \u7/mc_dp_o_reg[3] + (.C(mc_clk_i), + .CE(\ ), + .D(mc_dp_o[3]), + .Q(mc_dp_pad_o[3]), + .R(\ )); + FDRE \u7/mc_dqm_r2_reg[0] + (.C(clk_i), + .CE(\ ), + .D(mc_dqm_r[0]), + .Q(mc_dqm_r2[0]), + .R(\ )); + FDRE \u7/mc_dqm_r2_reg[1] + (.C(clk_i), + .CE(\ ), + .D(mc_dqm_r[1]), + .Q(mc_dqm_r2[1]), + .R(\ )); + FDRE \u7/mc_dqm_r2_reg[2] + (.C(clk_i), + .CE(\ ), + .D(mc_dqm_r[2]), + .Q(mc_dqm_r2[2]), + .R(\ )); + FDRE \u7/mc_dqm_r2_reg[3] + (.C(clk_i), + .CE(\ ), + .D(mc_dqm_r[3]), + .Q(mc_dqm_r2[3]), + .R(\ )); + FDRE \u7/mc_dqm_r_reg[0] + (.C(clk_i), + .CE(\u6/wr_hold0 ), + .D(wb_sel_i[0]), + .Q(mc_dqm_r[0]), + .R(\ )); + FDRE \u7/mc_dqm_r_reg[1] + (.C(clk_i), + .CE(\u6/wr_hold0 ), + .D(wb_sel_i[1]), + .Q(mc_dqm_r[1]), + .R(\ )); + FDRE \u7/mc_dqm_r_reg[2] + (.C(clk_i), + .CE(\u6/wr_hold0 ), + .D(wb_sel_i[2]), + .Q(mc_dqm_r[2]), + .R(\ )); + FDRE \u7/mc_dqm_r_reg[3] + (.C(clk_i), + .CE(\u6/wr_hold0 ), + .D(wb_sel_i[3]), + .Q(mc_dqm_r[3]), + .R(\ )); + FDSE \u7/mc_dqm_reg[0] + (.C(mc_clk_i), + .CE(\ ), + .D(\mc_dqm[0]_i_1_n_0 ), + .Q(mc_dqm_pad_o[0]), + .S(susp_sel)); + FDSE \u7/mc_dqm_reg[1] + (.C(mc_clk_i), + .CE(\ ), + .D(\mc_dqm[1]_i_1_n_0 ), + .Q(mc_dqm_pad_o[1]), + .S(susp_sel)); + FDSE \u7/mc_dqm_reg[2] + (.C(mc_clk_i), + .CE(\ ), + .D(\mc_dqm[2]_i_1_n_0 ), + .Q(mc_dqm_pad_o[2]), + .S(susp_sel)); + FDSE \u7/mc_dqm_reg[3] + (.C(mc_clk_i), + .CE(\ ), + .D(\mc_dqm[3]_i_1_n_0 ), + .Q(mc_dqm_pad_o[3]), + .S(susp_sel)); + FDPE \u7/mc_oe__reg + (.C(mc_clk_i), + .CE(\ ), + .D(\u7/mc_oe_0 ), + .PRE(rst_i), + .Q(mc_oe_pad_o_)); + FDRE \u7/mc_ras__reg + (.C(mc_clk_i), + .CE(\ ), + .D(ras_), + .Q(mc_ras_pad_o_), + .R(\ )); + FDRE \u7/mc_rp_reg + (.C(mc_clk_i), + .CE(\ ), + .D(\u7/mc_rp0 ), + .Q(mc_rp_pad_o_), + .R(\ )); + FDRE \u7/mc_sts_ir_reg + (.C(mc_clk_i), + .CE(\ ), + .D(mc_sts_pad_i), + .Q(mc_sts_ir), + .R(\ )); + FDRE \u7/mc_we__reg + (.C(mc_clk_i), + .CE(\ ), + .D(we_), + .Q(mc_we_pad_o_), + .R(\ )); + FDRE \u7/mc_zz_o_reg + (.C(mc_clk_i), + .CE(\ ), + .D(suspended_o), + .Q(mc_zz_pad_o), + .R(\ )); + LUT6 #( + .INIT(64'hEAEAEAAAEAAAEAAA)) + wb_ack_o_i_1 + (.I0(wb_ack_o_i_2_n_0), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(mem_ack), + .I3(wb_ack_o_i_3_n_0), + .I4(wb_ack_o_i_4_n_0), + .I5(wb_ack_o_i_5_n_0), + .O(wb_ack_o_i_1_n_0)); + LUT6 #( + .INIT(64'h6996966996696996)) + wb_ack_o_i_10 + (.I0(wb_ack_o_i_15_n_0), + .I1(wb_ack_o_i_16_n_0), + .I2(\wb_data_o[9]_i_5_n_0 ), + .I3(\wb_data_o[8]_i_5_n_0 ), + .I4(\wb_data_o[11]_i_4_n_0 ), + .I5(\wb_data_o[10]_i_7_n_0 ), + .O(wb_ack_o_i_10_n_0)); + LUT6 #( + .INIT(64'h6996966996696996)) + wb_ack_o_i_11 + (.I0(wb_ack_o_i_17_n_0), + .I1(wb_ack_o_i_18_n_0), + .I2(\wb_data_o[19]_i_4_n_0 ), + .I3(\wb_data_o[18]_i_4_n_0 ), + .I4(\wb_data_o[17]_i_4_n_0 ), + .I5(\wb_data_o[16]_i_3_n_0 ), + .O(wb_ack_o_i_11_n_0)); + LUT5 #( + .INIT(32'h96696996)) + wb_ack_o_i_12 + (.I0(wb_ack_o_i_19_n_0), + .I1(\wb_data_o[27]_i_3_n_0 ), + .I2(\wb_data_o[26]_i_4_n_0 ), + .I3(\wb_data_o[25]_i_3_n_0 ), + .I4(\wb_data_o[24]_i_4_n_0 ), + .O(wb_ack_o_i_12_n_0)); + LUT5 #( + .INIT(32'hFFFFF888)) + wb_ack_o_i_13 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[32]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[32]), + .I4(wb_ack_o_i_20_n_0), + .O(wb_ack_o_i_13_n_0)); + LUT4 #( + .INIT(16'h6996)) + wb_ack_o_i_14 + (.I0(\wb_data_o[3]_i_5_n_0 ), + .I1(\wb_data_o[2]_i_5_n_0 ), + .I2(\wb_data_o[1]_i_5_n_0 ), + .I3(\wb_data_o[0]_i_5_n_0 ), + .O(wb_ack_o_i_14_n_0)); + LUT5 #( + .INIT(32'h00000777)) + wb_ack_o_i_15 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[33]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[33]), + .I4(wb_ack_o_i_21_n_0), + .O(wb_ack_o_i_15_n_0)); + LUT4 #( + .INIT(16'h6996)) + wb_ack_o_i_16 + (.I0(\wb_data_o[15]_i_5_n_0 ), + .I1(\wb_data_o[14]_i_4_n_0 ), + .I2(\wb_data_o[13]_i_4_n_0 ), + .I3(\wb_data_o[12]_i_4_n_0 ), + .O(wb_ack_o_i_16_n_0)); + LUT5 #( + .INIT(32'h00000777)) + wb_ack_o_i_17 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[34]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[34]), + .I4(wb_ack_o_i_22_n_0), + .O(wb_ack_o_i_17_n_0)); + LUT4 #( + .INIT(16'h6996)) + wb_ack_o_i_18 + (.I0(\wb_data_o[21]_i_4_n_0 ), + .I1(\wb_data_o[20]_i_3_n_0 ), + .I2(\wb_data_o[22]_i_4_n_0 ), + .I3(\wb_data_o[23]_i_4_n_0 ), + .O(wb_ack_o_i_18_n_0)); + LUT5 #( + .INIT(32'h00000777)) + wb_ack_o_i_19 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[35]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[35]), + .I4(wb_ack_o_i_23_n_0), + .O(wb_ack_o_i_19_n_0)); + LUT6 #( + .INIT(64'h0000000008000000)) + wb_ack_o_i_2 + (.I0(wb_cyc_i), + .I1(wb_stb_i), + .I2(wb_addr_i[31]), + .I3(wb_addr_i[29]), + .I4(wb_addr_i[30]), + .I5(wb_ack_o), + .O(wb_ack_o_i_2_n_0)); + LUT4 #( + .INIT(16'hF888)) + wb_ack_o_i_20 + (.I0(r3[32]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[32]), + .I3(\u3/u0/rd_adr [2]), + .O(wb_ack_o_i_20_n_0)); + LUT4 #( + .INIT(16'hF888)) + wb_ack_o_i_21 + (.I0(r2[33]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[33]), + .I3(\u3/u0/rd_adr [3]), + .O(wb_ack_o_i_21_n_0)); + LUT4 #( + .INIT(16'hF888)) + wb_ack_o_i_22 + (.I0(r3[34]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[34]), + .I3(\u3/u0/rd_adr [2]), + .O(wb_ack_o_i_22_n_0)); + LUT4 #( + .INIT(16'hF888)) + wb_ack_o_i_23 + (.I0(r3[35]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[35]), + .I3(\u3/u0/rd_adr [2]), + .O(wb_ack_o_i_23_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h7)) + wb_ack_o_i_3 + (.I0(wb_stb_i), + .I1(wb_cyc_i), + .O(wb_ack_o_i_3_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFF4044FFFF)) + wb_ack_o_i_4 + (.I0(wb_ack_o_i_6_n_0), + .I1(wb_ack_o_i_7_n_0), + .I2(wb_ack_o_i_8_n_0), + .I3(wb_sel_i[0]), + .I4(csc[11]), + .I5(wb_we_i), + .O(wb_ack_o_i_4_n_0)); + LUT6 #( + .INIT(64'h00000000FFFFFFFD)) + wb_ack_o_i_5 + (.I0(wb_ack_o_i_9_n_0), + .I1(\u5/state [1]), + .I2(\u5/state [6]), + .I3(\u5/state [0]), + .I4(\u5/state [3]), + .I5(wp_err), + .O(wb_ack_o_i_5_n_0)); + LUT4 #( + .INIT(16'h4F44)) + wb_ack_o_i_6 + (.I0(wb_ack_o_i_10_n_0), + .I1(wb_sel_i[1]), + .I2(wb_ack_o_i_11_n_0), + .I3(wb_sel_i[2]), + .O(wb_ack_o_i_6_n_0)); + LUT6 #( + .INIT(64'hD77D7DD77DD7D77D)) + wb_ack_o_i_7 + (.I0(wb_sel_i[3]), + .I1(wb_ack_o_i_12_n_0), + .I2(\wb_data_o[31]_i_5_n_0 ), + .I3(\wb_data_o[30]_i_3_n_0 ), + .I4(\wb_data_o[29]_i_4_n_0 ), + .I5(\wb_data_o[28]_i_3_n_0 ), + .O(wb_ack_o_i_7_n_0)); + LUT6 #( + .INIT(64'h6996966996696996)) + wb_ack_o_i_8 + (.I0(wb_ack_o_i_13_n_0), + .I1(wb_ack_o_i_14_n_0), + .I2(\wb_data_o[7]_i_5_n_0 ), + .I3(\wb_data_o[6]_i_5_n_0 ), + .I4(\wb_data_o[5]_i_5_n_0 ), + .I5(\wb_data_o[4]_i_5_n_0 ), + .O(wb_ack_o_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT3 #( + .INIT(8'h80)) + wb_ack_o_i_9 + (.I0(\u5/state [5]), + .I1(\u5/state [4]), + .I2(\u5/state [2]), + .O(wb_ack_o_i_9_n_0)); + LUT5 #( + .INIT(32'hFFA2FF00)) + wb_cycle_i_1 + (.I0(wb_cyc_i), + .I1(wb_stb_i), + .I2(\wb_data_o[31]_i_4_n_0 ), + .I3(\u5/wb_cycle_set ), + .I4(wb_cycle), + .O(wb_cycle_i_1_n_0)); + LUT6 #( + .INIT(64'h0000000010110000)) + wb_cycle_i_2 + (.I0(\FSM_sequential_state[5]_i_9_n_0 ), + .I1(init_req), + .I2(wb_cycle), + .I3(\u5/susp_req_r ), + .I4(\u5/burst_cnt_ld ), + .I5(\FSM_sequential_state[1]_i_12_n_0 ), + .O(\u5/wb_cycle_set )); + LUT5 #( + .INIT(32'hFF100010)) + \wb_data_o[0]_i_1 + (.I0(wb_addr_i[6]), + .I1(wb_addr_i[5]), + .I2(\wb_data_o[0]_i_2_n_0 ), + .I3(\wb_data_o[31]_i_4_n_0 ), + .I4(\wb_data_o[0]_i_3_n_0 ), + .O(\wb_data_o[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[0]_i_2 + (.I0(\u0/csr_r_reg_n_0_[0] ), + .I1(poc_o[0]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask [0]), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[0]_i_4_n_0 ), + .O(\wb_data_o[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFE02FEFEFE020202)) + \wb_data_o[0]_i_3 + (.I0(\wb_data_o[0]_i_5_n_0 ), + .I1(csc[3]), + .I2(csc[2]), + .I3(mc_data_ir[0]), + .I4(csc[5]), + .I5(byte0[0]), + .O(\wb_data_o[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[0]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[0] ), + .I1(\u0/u1/csc_reg_n_0_[0] ), + .I2(wb_addr_i[3]), + .I3(tms[0]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[0] ), + .O(\wb_data_o[0]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[0]_i_5 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[0]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[0]), + .I4(\wb_data_o[0]_i_6_n_0 ), + .O(\wb_data_o[0]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[0]_i_6 + (.I0(r2[0]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[0]), + .I3(\u3/u0/rd_adr [3]), + .O(\wb_data_o[0]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFF100010)) + \wb_data_o[10]_i_1 + (.I0(wb_addr_i[6]), + .I1(wb_addr_i[5]), + .I2(\wb_data_o[10]_i_2_n_0 ), + .I3(\wb_data_o[31]_i_4_n_0 ), + .I4(\wb_data_o[10]_i_3_n_0 ), + .O(\wb_data_o[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[10]_i_2 + (.I0(sel0[2]), + .I1(poc_o[10]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask_r_reg_n_0_[10] ), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[10]_i_6_n_0 ), + .O(\wb_data_o[10]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFE02FEFEFE020202)) + \wb_data_o[10]_i_3 + (.I0(\wb_data_o[10]_i_7_n_0 ), + .I1(csc[3]), + .I2(csc[2]), + .I3(mc_data_ir[10]), + .I4(csc[5]), + .I5(byte1[2]), + .O(\wb_data_o[10]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'h1)) + \wb_data_o[10]_i_4 + (.I0(wb_addr_i[3]), + .I1(wb_addr_i[4]), + .O(\wb_data_o[10]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'h45)) + \wb_data_o[10]_i_5 + (.I0(wb_addr_i[4]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[2]), + .O(\wb_data_o[10]_i_5_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[10]_i_6 + (.I0(\u0/u1/tms_reg_n_0_[10] ), + .I1(\u0/u1/csc_reg_n_0_[10] ), + .I2(wb_addr_i[3]), + .I3(tms[10]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[10] ), + .O(\wb_data_o[10]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[10]_i_7 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[10]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[10]), + .I4(\wb_data_o[10]_i_8_n_0 ), + .O(\wb_data_o[10]_i_7_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[10]_i_8 + (.I0(r3[10]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[10]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[10]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF54540004)) + \wb_data_o[11]_i_1 + (.I0(\wb_data_o[15]_i_3_n_0 ), + .I1(poc_o[11]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[3]), + .I4(\wb_data_o[11]_i_2_n_0 ), + .I5(\wb_data_o[11]_i_3_n_0 ), + .O(\wb_data_o[11]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[11]_i_2 + (.I0(\u0/u1/tms_reg_n_0_[11] ), + .I1(\u0/u1/csc_reg_n_0_[11] ), + .I2(wb_addr_i[3]), + .I3(tms[11]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[11] ), + .O(\wb_data_o[11]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[11]_i_3 + (.I0(\wb_data_o[11]_i_4_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte1[3]), + .I3(csc[5]), + .I4(mc_data_ir[11]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[11]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[11]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[11]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[11]), + .I4(\wb_data_o[11]_i_5_n_0 ), + .O(\wb_data_o[11]_i_4_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[11]_i_5 + (.I0(r3[11]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[11]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[11]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF54540004)) + \wb_data_o[12]_i_1 + (.I0(\wb_data_o[15]_i_3_n_0 ), + .I1(poc_o[12]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[3]), + .I4(\wb_data_o[12]_i_2_n_0 ), + .I5(\wb_data_o[12]_i_3_n_0 ), + .O(\wb_data_o[12]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[12]_i_2 + (.I0(\u0/u1/tms_reg_n_0_[12] ), + .I1(\u0/u1/csc_reg_n_0_[12] ), + .I2(wb_addr_i[3]), + .I3(tms[12]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[12] ), + .O(\wb_data_o[12]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[12]_i_3 + (.I0(\wb_data_o[12]_i_4_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte1[4]), + .I3(csc[5]), + .I4(mc_data_ir[12]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[12]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[12]_i_4 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[12]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[12]), + .I4(\wb_data_o[12]_i_5_n_0 ), + .O(\wb_data_o[12]_i_4_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[12]_i_5 + (.I0(r2[12]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[12]), + .I3(\u3/u0/rd_adr [3]), + .O(\wb_data_o[12]_i_5_n_0 )); + LUT6 #( + .INIT(64'hBBBABBBAAAAAAABA)) + \wb_data_o[13]_i_1 + (.I0(\wb_data_o[13]_i_2_n_0 ), + .I1(\wb_data_o[15]_i_3_n_0 ), + .I2(poc_o[13]), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(\wb_data_o[13]_i_3_n_0 ), + .O(\wb_data_o[13]_i_1_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[13]_i_2 + (.I0(\wb_data_o[13]_i_4_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte1[5]), + .I3(csc[5]), + .I4(mc_data_ir[13]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[13]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[13]_i_3 + (.I0(\u0/u1/tms_reg_n_0_[13] ), + .I1(\u0/u1/csc_reg_n_0_[13] ), + .I2(wb_addr_i[3]), + .I3(tms[13]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[13] ), + .O(\wb_data_o[13]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[13]_i_4 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[13]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[13]), + .I4(\wb_data_o[13]_i_5_n_0 ), + .O(\wb_data_o[13]_i_4_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[13]_i_5 + (.I0(r2[13]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[13]), + .I3(\u3/u0/rd_adr [3]), + .O(\wb_data_o[13]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF54540004)) + \wb_data_o[14]_i_1 + (.I0(\wb_data_o[15]_i_3_n_0 ), + .I1(poc_o[14]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[3]), + .I4(\wb_data_o[14]_i_2_n_0 ), + .I5(\wb_data_o[14]_i_3_n_0 ), + .O(\wb_data_o[14]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[14]_i_2 + (.I0(\u0/u1/tms_reg_n_0_[14] ), + .I1(\u0/u1/csc_reg_n_0_[14] ), + .I2(wb_addr_i[3]), + .I3(tms[14]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[14] ), + .O(\wb_data_o[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[14]_i_3 + (.I0(\wb_data_o[14]_i_4_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte1[6]), + .I3(csc[5]), + .I4(mc_data_ir[14]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[14]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[14]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[14]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[14]), + .I4(\wb_data_o[14]_i_5_n_0 ), + .O(\wb_data_o[14]_i_4_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[14]_i_5 + (.I0(r3[14]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[14]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[14]_i_5_n_0 )); + LUT6 #( + .INIT(64'hBBBABBBAAAAAAABA)) + \wb_data_o[15]_i_1 + (.I0(\wb_data_o[15]_i_2_n_0 ), + .I1(\wb_data_o[15]_i_3_n_0 ), + .I2(poc_o[15]), + .I3(wb_addr_i[4]), + .I4(wb_addr_i[3]), + .I5(\wb_data_o[15]_i_4_n_0 ), + .O(\wb_data_o[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[15]_i_2 + (.I0(\wb_data_o[15]_i_5_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte1[7]), + .I3(csc[5]), + .I4(mc_data_ir[15]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[15]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFF0D)) + \wb_data_o[15]_i_3 + (.I0(wb_addr_i[2]), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(wb_addr_i[5]), + .I4(wb_addr_i[6]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[15]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[15]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[15] ), + .I1(\u0/u1/csc_reg_n_0_[15] ), + .I2(wb_addr_i[3]), + .I3(tms[15]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[15] ), + .O(\wb_data_o[15]_i_4_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[15]_i_5 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[15]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[15]), + .I4(\wb_data_o[15]_i_6_n_0 ), + .O(\wb_data_o[15]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[15]_i_6 + (.I0(r3[15]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[15]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[15]_i_6_n_0 )); + LUT6 #( + .INIT(64'hEEEEEEEAAAAAAAEA)) + \wb_data_o[16]_i_1 + (.I0(\wb_data_o[16]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(\wb_data_o[16]_i_3_n_0 ), + .I3(csc[3]), + .I4(csc[2]), + .I5(\wb_data_o[16]_i_4_n_0 ), + .O(\wb_data_o[16]_i_1_n_0 )); + LUT6 #( + .INIT(64'h4444744400000000)) + \wb_data_o[16]_i_2 + (.I0(\wb_data_o[16]_i_5_n_0 ), + .I1(wb_addr_i[4]), + .I2(poc_o[16]), + .I3(wb_addr_i[2]), + .I4(wb_addr_i[3]), + .I5(\wb_data_o[31]_i_2_n_0 ), + .O(\wb_data_o[16]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[16]_i_3 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[16]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[16]), + .I4(\wb_data_o[16]_i_6_n_0 ), + .O(\wb_data_o[16]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[16]_i_4 + (.I0(mc_data_ir[16]), + .I1(csc[5]), + .I2(mc_data_ir[0]), + .I3(csc[4]), + .I4(byte2[0]), + .O(\wb_data_o[16]_i_4_n_0 )); + LUT6 #( + .INIT(64'h505F3030505F3F3F)) + \wb_data_o[16]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[16] ), + .I1(\u0/u1/csc_reg_n_0_[16] ), + .I2(wb_addr_i[3]), + .I3(tms[16]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[16] ), + .O(\wb_data_o[16]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[16]_i_6 + (.I0(r2[16]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[16]), + .I3(\u3/u0/rd_adr [3]), + .O(\wb_data_o[16]_i_6_n_0 )); + LUT6 #( + .INIT(64'hEAEAEAEAEAEAAAEE)) + \wb_data_o[17]_i_1 + (.I0(\wb_data_o[17]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(\wb_data_o[17]_i_3_n_0 ), + .I3(\wb_data_o[17]_i_4_n_0 ), + .I4(csc[3]), + .I5(csc[2]), + .O(\wb_data_o[17]_i_1_n_0 )); + LUT6 #( + .INIT(64'h8888B88800000000)) + \wb_data_o[17]_i_2 + (.I0(\wb_data_o[17]_i_5_n_0 ), + .I1(wb_addr_i[4]), + .I2(poc_o[17]), + .I3(wb_addr_i[2]), + .I4(wb_addr_i[3]), + .I5(\wb_data_o[31]_i_2_n_0 ), + .O(\wb_data_o[17]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[17]_i_3 + (.I0(mc_data_ir[17]), + .I1(csc[5]), + .I2(mc_data_ir[1]), + .I3(csc[4]), + .I4(byte2[1]), + .O(\wb_data_o[17]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[17]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[17]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[17]), + .I4(\wb_data_o[17]_i_6_n_0 ), + .O(\wb_data_o[17]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[17]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[17] ), + .I1(\u0/u1/csc_reg_n_0_[17] ), + .I2(wb_addr_i[3]), + .I3(tms[17]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[17] ), + .O(\wb_data_o[17]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[17]_i_6 + (.I0(r3[17]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[17]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[17]_i_6_n_0 )); + LUT6 #( + .INIT(64'hEAEAEAEAEAEAAAEE)) + \wb_data_o[18]_i_1 + (.I0(\wb_data_o[18]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(\wb_data_o[18]_i_3_n_0 ), + .I3(\wb_data_o[18]_i_4_n_0 ), + .I4(csc[3]), + .I5(csc[2]), + .O(\wb_data_o[18]_i_1_n_0 )); + LUT6 #( + .INIT(64'h8888B88800000000)) + \wb_data_o[18]_i_2 + (.I0(\wb_data_o[18]_i_5_n_0 ), + .I1(wb_addr_i[4]), + .I2(poc_o[18]), + .I3(wb_addr_i[2]), + .I4(wb_addr_i[3]), + .I5(\wb_data_o[31]_i_2_n_0 ), + .O(\wb_data_o[18]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[18]_i_3 + (.I0(mc_data_ir[18]), + .I1(csc[5]), + .I2(mc_data_ir[2]), + .I3(csc[4]), + .I4(byte2[2]), + .O(\wb_data_o[18]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[18]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[18]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[18]), + .I4(\wb_data_o[18]_i_6_n_0 ), + .O(\wb_data_o[18]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[18]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[18] ), + .I1(\u0/u1/csc_reg_n_0_[18] ), + .I2(wb_addr_i[3]), + .I3(tms[18]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[18] ), + .O(\wb_data_o[18]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[18]_i_6 + (.I0(r3[18]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[18]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[18]_i_6_n_0 )); + LUT6 #( + .INIT(64'hEAEAEAEAEAEAAAEE)) + \wb_data_o[19]_i_1 + (.I0(\wb_data_o[19]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(\wb_data_o[19]_i_3_n_0 ), + .I3(\wb_data_o[19]_i_4_n_0 ), + .I4(csc[3]), + .I5(csc[2]), + .O(\wb_data_o[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h4444744400000000)) + \wb_data_o[19]_i_2 + (.I0(\wb_data_o[19]_i_5_n_0 ), + .I1(wb_addr_i[4]), + .I2(poc_o[19]), + .I3(wb_addr_i[2]), + .I4(wb_addr_i[3]), + .I5(\wb_data_o[31]_i_2_n_0 ), + .O(\wb_data_o[19]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[19]_i_3 + (.I0(mc_data_ir[19]), + .I1(csc[5]), + .I2(mc_data_ir[3]), + .I3(csc[4]), + .I4(byte2[3]), + .O(\wb_data_o[19]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[19]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[19]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[19]), + .I4(\wb_data_o[19]_i_6_n_0 ), + .O(\wb_data_o[19]_i_4_n_0 )); + LUT6 #( + .INIT(64'h505F3030505F3F3F)) + \wb_data_o[19]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[19] ), + .I1(\u0/u1/csc_reg_n_0_[19] ), + .I2(wb_addr_i[3]), + .I3(tms[19]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[19] ), + .O(\wb_data_o[19]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[19]_i_6 + (.I0(r3[19]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[19]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[19]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFFFF0100)) + \wb_data_o[1]_i_1 + (.I0(\wb_data_o[31]_i_4_n_0 ), + .I1(wb_addr_i[6]), + .I2(wb_addr_i[5]), + .I3(\wb_data_o[1]_i_2_n_0 ), + .I4(\wb_data_o[1]_i_3_n_0 ), + .O(\wb_data_o[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[1]_i_2 + (.I0(mc_vpen_pad_o), + .I1(poc_o[1]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask [1]), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[1]_i_4_n_0 ), + .O(\wb_data_o[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[1]_i_3 + (.I0(\wb_data_o[1]_i_5_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte0[1]), + .I3(csc[5]), + .I4(mc_data_ir[1]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[1]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[1] ), + .I1(\u0/u1/csc_reg_n_0_[1] ), + .I2(wb_addr_i[3]), + .I3(tms[1]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[1] ), + .O(\wb_data_o[1]_i_4_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[1]_i_5 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[1]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[1]), + .I4(\wb_data_o[1]_i_6_n_0 ), + .O(\wb_data_o[1]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[1]_i_6 + (.I0(r3[1]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[1]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[1]_i_6_n_0 )); + LUT6 #( + .INIT(64'hEEEEEEEAAAAAAAEA)) + \wb_data_o[20]_i_1 + (.I0(\wb_data_o[20]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(\wb_data_o[20]_i_3_n_0 ), + .I3(csc[3]), + .I4(csc[2]), + .I5(\wb_data_o[20]_i_4_n_0 ), + .O(\wb_data_o[20]_i_1_n_0 )); + LUT6 #( + .INIT(64'h4444744400000000)) + \wb_data_o[20]_i_2 + (.I0(\wb_data_o[20]_i_5_n_0 ), + .I1(wb_addr_i[4]), + .I2(poc_o[20]), + .I3(wb_addr_i[2]), + .I4(wb_addr_i[3]), + .I5(\wb_data_o[31]_i_2_n_0 ), + .O(\wb_data_o[20]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[20]_i_3 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[20]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[20]), + .I4(\wb_data_o[20]_i_6_n_0 ), + .O(\wb_data_o[20]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[20]_i_4 + (.I0(mc_data_ir[20]), + .I1(csc[5]), + .I2(mc_data_ir[4]), + .I3(csc[4]), + .I4(byte2[4]), + .O(\wb_data_o[20]_i_4_n_0 )); + LUT6 #( + .INIT(64'h505F3030505F3F3F)) + \wb_data_o[20]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[20] ), + .I1(\u0/u1/csc_reg_n_0_[20] ), + .I2(wb_addr_i[3]), + .I3(tms[20]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[20] ), + .O(\wb_data_o[20]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[20]_i_6 + (.I0(r2[20]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[20]), + .I3(\u3/u0/rd_adr [3]), + .O(\wb_data_o[20]_i_6_n_0 )); + LUT6 #( + .INIT(64'hEAEAEAEAEAEAAAEE)) + \wb_data_o[21]_i_1 + (.I0(\wb_data_o[21]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(\wb_data_o[21]_i_3_n_0 ), + .I3(\wb_data_o[21]_i_4_n_0 ), + .I4(csc[3]), + .I5(csc[2]), + .O(\wb_data_o[21]_i_1_n_0 )); + LUT6 #( + .INIT(64'h8888B88800000000)) + \wb_data_o[21]_i_2 + (.I0(\wb_data_o[21]_i_5_n_0 ), + .I1(wb_addr_i[4]), + .I2(poc_o[21]), + .I3(wb_addr_i[2]), + .I4(wb_addr_i[3]), + .I5(\wb_data_o[31]_i_2_n_0 ), + .O(\wb_data_o[21]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[21]_i_3 + (.I0(mc_data_ir[21]), + .I1(csc[5]), + .I2(mc_data_ir[5]), + .I3(csc[4]), + .I4(byte2[5]), + .O(\wb_data_o[21]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[21]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[21]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[21]), + .I4(\wb_data_o[21]_i_6_n_0 ), + .O(\wb_data_o[21]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[21]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[21] ), + .I1(\u0/u1/csc_reg_n_0_[21] ), + .I2(wb_addr_i[3]), + .I3(tms[21]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[21] ), + .O(\wb_data_o[21]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[21]_i_6 + (.I0(r3[21]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[21]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[21]_i_6_n_0 )); + LUT6 #( + .INIT(64'hEAEAEAEAEAEAAAEE)) + \wb_data_o[22]_i_1 + (.I0(\wb_data_o[22]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(\wb_data_o[22]_i_3_n_0 ), + .I3(\wb_data_o[22]_i_4_n_0 ), + .I4(csc[3]), + .I5(csc[2]), + .O(\wb_data_o[22]_i_1_n_0 )); + LUT6 #( + .INIT(64'h8888B88800000000)) + \wb_data_o[22]_i_2 + (.I0(\wb_data_o[22]_i_5_n_0 ), + .I1(wb_addr_i[4]), + .I2(poc_o[22]), + .I3(wb_addr_i[2]), + .I4(wb_addr_i[3]), + .I5(\wb_data_o[31]_i_2_n_0 ), + .O(\wb_data_o[22]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[22]_i_3 + (.I0(mc_data_ir[22]), + .I1(csc[5]), + .I2(mc_data_ir[6]), + .I3(csc[4]), + .I4(byte2[6]), + .O(\wb_data_o[22]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[22]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[22]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[22]), + .I4(\wb_data_o[22]_i_6_n_0 ), + .O(\wb_data_o[22]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[22]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[22] ), + .I1(\u0/u1/csc_reg_n_0_[22] ), + .I2(wb_addr_i[3]), + .I3(tms[22]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[22] ), + .O(\wb_data_o[22]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[22]_i_6 + (.I0(r3[22]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[22]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[22]_i_6_n_0 )); + LUT6 #( + .INIT(64'hEAEAEAEAEAEAAAEE)) + \wb_data_o[23]_i_1 + (.I0(\wb_data_o[23]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(\wb_data_o[23]_i_3_n_0 ), + .I3(\wb_data_o[23]_i_4_n_0 ), + .I4(csc[3]), + .I5(csc[2]), + .O(\wb_data_o[23]_i_1_n_0 )); + LUT6 #( + .INIT(64'h550C000055000000)) + \wb_data_o[23]_i_2 + (.I0(\wb_data_o[23]_i_5_n_0 ), + .I1(wb_addr_i[2]), + .I2(wb_addr_i[3]), + .I3(wb_addr_i[4]), + .I4(\wb_data_o[31]_i_2_n_0 ), + .I5(poc_o[23]), + .O(\wb_data_o[23]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[23]_i_3 + (.I0(mc_data_ir[23]), + .I1(csc[5]), + .I2(mc_data_ir[7]), + .I3(csc[4]), + .I4(byte2[7]), + .O(\wb_data_o[23]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[23]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[23]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[23]), + .I4(\wb_data_o[23]_i_6_n_0 ), + .O(\wb_data_o[23]_i_4_n_0 )); + LUT6 #( + .INIT(64'h505F3030505F3F3F)) + \wb_data_o[23]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[23] ), + .I1(\u0/u1/csc_reg_n_0_[23] ), + .I2(wb_addr_i[3]), + .I3(tms[23]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[23] ), + .O(\wb_data_o[23]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[23]_i_6 + (.I0(r3[23]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[23]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[23]_i_6_n_0 )); + LUT6 #( + .INIT(64'h4444F4F4F444F444)) + \wb_data_o[24]_i_1 + (.I0(\wb_data_o[24]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_2_n_0 ), + .I2(\wb_data_o[31]_i_4_n_0 ), + .I3(\wb_data_o[24]_i_3_n_0 ), + .I4(\wb_data_o[24]_i_4_n_0 ), + .I5(\wb_data_o[31]_i_6_n_0 ), + .O(\wb_data_o[24]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5C5C5C5F5F5F5C5F)) + \wb_data_o[24]_i_2 + (.I0(\wb_data_o[24]_i_5_n_0 ), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rfr_ps_val[0]), + .I4(wb_addr_i[2]), + .I5(poc_o[24]), + .O(\wb_data_o[24]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[24]_i_3 + (.I0(mc_data_ir[24]), + .I1(csc[5]), + .I2(mc_data_ir[8]), + .I3(csc[4]), + .I4(mc_data_ir[0]), + .O(\wb_data_o[24]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[24]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[24]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[24]), + .I4(\wb_data_o[24]_i_6_n_0 ), + .O(\wb_data_o[24]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[24]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[24] ), + .I1(\u0/u1/csc_reg_n_0_[24] ), + .I2(wb_addr_i[3]), + .I3(tms[24]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[24] ), + .O(\wb_data_o[24]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[24]_i_6 + (.I0(r3[24]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[24]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[24]_i_6_n_0 )); + LUT6 #( + .INIT(64'hF444F4F4F4444444)) + \wb_data_o[25]_i_1 + (.I0(\wb_data_o[25]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_2_n_0 ), + .I2(\wb_data_o[31]_i_4_n_0 ), + .I3(\wb_data_o[25]_i_3_n_0 ), + .I4(\wb_data_o[31]_i_6_n_0 ), + .I5(\wb_data_o[25]_i_4_n_0 ), + .O(\wb_data_o[25]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5C5C5C5F5F5F5C5F)) + \wb_data_o[25]_i_2 + (.I0(\wb_data_o[25]_i_5_n_0 ), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rfr_ps_val[1]), + .I4(wb_addr_i[2]), + .I5(poc_o[25]), + .O(\wb_data_o[25]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[25]_i_3 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[25]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[25]), + .I4(\wb_data_o[25]_i_6_n_0 ), + .O(\wb_data_o[25]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[25]_i_4 + (.I0(mc_data_ir[25]), + .I1(csc[5]), + .I2(mc_data_ir[9]), + .I3(csc[4]), + .I4(mc_data_ir[1]), + .O(\wb_data_o[25]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[25]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[25] ), + .I1(\u0/u1/csc_reg_n_0_[25] ), + .I2(wb_addr_i[3]), + .I3(tms[25]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[25] ), + .O(\wb_data_o[25]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[25]_i_6 + (.I0(r3[25]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[25]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[25]_i_6_n_0 )); + LUT6 #( + .INIT(64'h4444F4F4F444F444)) + \wb_data_o[26]_i_1 + (.I0(\wb_data_o[26]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_2_n_0 ), + .I2(\wb_data_o[31]_i_4_n_0 ), + .I3(\wb_data_o[26]_i_3_n_0 ), + .I4(\wb_data_o[26]_i_4_n_0 ), + .I5(\wb_data_o[31]_i_6_n_0 ), + .O(\wb_data_o[26]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5C5C5C5F5F5F5C5F)) + \wb_data_o[26]_i_2 + (.I0(\wb_data_o[26]_i_5_n_0 ), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rfr_ps_val[2]), + .I4(wb_addr_i[2]), + .I5(poc_o[26]), + .O(\wb_data_o[26]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[26]_i_3 + (.I0(mc_data_ir[26]), + .I1(csc[5]), + .I2(mc_data_ir[10]), + .I3(csc[4]), + .I4(mc_data_ir[2]), + .O(\wb_data_o[26]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[26]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[26]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[26]), + .I4(\wb_data_o[26]_i_6_n_0 ), + .O(\wb_data_o[26]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[26]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[26] ), + .I1(\u0/u1/csc_reg_n_0_[26] ), + .I2(wb_addr_i[3]), + .I3(tms[26]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[26] ), + .O(\wb_data_o[26]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[26]_i_6 + (.I0(r3[26]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[26]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[26]_i_6_n_0 )); + LUT6 #( + .INIT(64'hF444F4F4F4444444)) + \wb_data_o[27]_i_1 + (.I0(\wb_data_o[27]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_2_n_0 ), + .I2(\wb_data_o[31]_i_4_n_0 ), + .I3(\wb_data_o[27]_i_3_n_0 ), + .I4(\wb_data_o[31]_i_6_n_0 ), + .I5(\wb_data_o[27]_i_4_n_0 ), + .O(\wb_data_o[27]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5C5C5C5F5F5F5C5F)) + \wb_data_o[27]_i_2 + (.I0(\wb_data_o[27]_i_5_n_0 ), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rfr_ps_val[3]), + .I4(wb_addr_i[2]), + .I5(poc_o[27]), + .O(\wb_data_o[27]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[27]_i_3 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[27]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[27]), + .I4(\wb_data_o[27]_i_6_n_0 ), + .O(\wb_data_o[27]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[27]_i_4 + (.I0(mc_data_ir[27]), + .I1(csc[5]), + .I2(mc_data_ir[11]), + .I3(csc[4]), + .I4(mc_data_ir[3]), + .O(\wb_data_o[27]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[27]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[27] ), + .I1(\u0/u1/csc_reg_n_0_[27] ), + .I2(wb_addr_i[3]), + .I3(tms[27]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[27] ), + .O(\wb_data_o[27]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[27]_i_6 + (.I0(r2[27]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[27]), + .I3(\u3/u0/rd_adr [3]), + .O(\wb_data_o[27]_i_6_n_0 )); + LUT6 #( + .INIT(64'hF444F4F4F4444444)) + \wb_data_o[28]_i_1 + (.I0(\wb_data_o[28]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_2_n_0 ), + .I2(\wb_data_o[31]_i_4_n_0 ), + .I3(\wb_data_o[28]_i_3_n_0 ), + .I4(\wb_data_o[31]_i_6_n_0 ), + .I5(\wb_data_o[28]_i_4_n_0 ), + .O(\wb_data_o[28]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5C5C5C5F5F5F5C5F)) + \wb_data_o[28]_i_2 + (.I0(\wb_data_o[28]_i_5_n_0 ), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rfr_ps_val[4]), + .I4(wb_addr_i[2]), + .I5(poc_o[28]), + .O(\wb_data_o[28]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[28]_i_3 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[28]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[28]), + .I4(\wb_data_o[28]_i_6_n_0 ), + .O(\wb_data_o[28]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[28]_i_4 + (.I0(mc_data_ir[28]), + .I1(csc[5]), + .I2(mc_data_ir[12]), + .I3(csc[4]), + .I4(mc_data_ir[4]), + .O(\wb_data_o[28]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[28]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[28] ), + .I1(\u0/u1/csc_reg_n_0_[28] ), + .I2(wb_addr_i[3]), + .I3(tms[28]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[28] ), + .O(\wb_data_o[28]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[28]_i_6 + (.I0(r2[28]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[28]), + .I3(\u3/u0/rd_adr [3]), + .O(\wb_data_o[28]_i_6_n_0 )); + LUT6 #( + .INIT(64'h4444F4F4F444F444)) + \wb_data_o[29]_i_1 + (.I0(\wb_data_o[29]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_2_n_0 ), + .I2(\wb_data_o[31]_i_4_n_0 ), + .I3(\wb_data_o[29]_i_3_n_0 ), + .I4(\wb_data_o[29]_i_4_n_0 ), + .I5(\wb_data_o[31]_i_6_n_0 ), + .O(\wb_data_o[29]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5C5C5C5F5F5F5C5F)) + \wb_data_o[29]_i_2 + (.I0(\wb_data_o[29]_i_5_n_0 ), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rfr_ps_val[5]), + .I4(wb_addr_i[2]), + .I5(poc_o[29]), + .O(\wb_data_o[29]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[29]_i_3 + (.I0(mc_data_ir[29]), + .I1(csc[5]), + .I2(mc_data_ir[13]), + .I3(csc[4]), + .I4(mc_data_ir[5]), + .O(\wb_data_o[29]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[29]_i_4 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[29]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[29]), + .I4(\wb_data_o[29]_i_6_n_0 ), + .O(\wb_data_o[29]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[29]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[29] ), + .I1(\u0/u1/csc_reg_n_0_[29] ), + .I2(wb_addr_i[3]), + .I3(tms[29]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[29] ), + .O(\wb_data_o[29]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[29]_i_6 + (.I0(r3[29]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[29]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[29]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFF100010)) + \wb_data_o[2]_i_1 + (.I0(wb_addr_i[6]), + .I1(wb_addr_i[5]), + .I2(\wb_data_o[2]_i_2_n_0 ), + .I3(\wb_data_o[31]_i_4_n_0 ), + .I4(\wb_data_o[2]_i_3_n_0 ), + .O(\wb_data_o[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[2]_i_2 + (.I0(fs), + .I1(poc_o[2]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask [2]), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[2]_i_4_n_0 ), + .O(\wb_data_o[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFE02FEFEFE020202)) + \wb_data_o[2]_i_3 + (.I0(\wb_data_o[2]_i_5_n_0 ), + .I1(csc[3]), + .I2(csc[2]), + .I3(mc_data_ir[2]), + .I4(csc[5]), + .I5(byte0[2]), + .O(\wb_data_o[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[2]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[2] ), + .I1(\u0/u1/csc_reg_n_0_[2] ), + .I2(wb_addr_i[3]), + .I3(tms[2]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[2] ), + .O(\wb_data_o[2]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[2]_i_5 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[2]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[2]), + .I4(\wb_data_o[2]_i_6_n_0 ), + .O(\wb_data_o[2]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[2]_i_6 + (.I0(r2[2]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[2]), + .I3(\u3/u0/rd_adr [3]), + .O(\wb_data_o[2]_i_6_n_0 )); + LUT6 #( + .INIT(64'hF444F4F4F4444444)) + \wb_data_o[30]_i_1 + (.I0(\wb_data_o[30]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_2_n_0 ), + .I2(\wb_data_o[31]_i_4_n_0 ), + .I3(\wb_data_o[30]_i_3_n_0 ), + .I4(\wb_data_o[31]_i_6_n_0 ), + .I5(\wb_data_o[30]_i_4_n_0 ), + .O(\wb_data_o[30]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5C5C5C5F5F5F5C5F)) + \wb_data_o[30]_i_2 + (.I0(\wb_data_o[30]_i_5_n_0 ), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rfr_ps_val[6]), + .I4(wb_addr_i[2]), + .I5(poc_o[30]), + .O(\wb_data_o[30]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[30]_i_3 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[30]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[30]), + .I4(\wb_data_o[30]_i_6_n_0 ), + .O(\wb_data_o[30]_i_3_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[30]_i_4 + (.I0(mc_data_ir[30]), + .I1(csc[5]), + .I2(mc_data_ir[14]), + .I3(csc[4]), + .I4(mc_data_ir[6]), + .O(\wb_data_o[30]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[30]_i_5 + (.I0(\u0/u1/tms_reg_n_0_[30] ), + .I1(\u0/u1/csc_reg_n_0_[30] ), + .I2(wb_addr_i[3]), + .I3(tms[30]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[30] ), + .O(\wb_data_o[30]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[30]_i_6 + (.I0(r3[30]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[30]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[30]_i_6_n_0 )); + LUT6 #( + .INIT(64'h88F8F8F888F88888)) + \wb_data_o[31]_i_1 + (.I0(\wb_data_o[31]_i_2_n_0 ), + .I1(\wb_data_o[31]_i_3_n_0 ), + .I2(\wb_data_o[31]_i_4_n_0 ), + .I3(\wb_data_o[31]_i_5_n_0 ), + .I4(\wb_data_o[31]_i_6_n_0 ), + .I5(\wb_data_o[31]_i_7_n_0 ), + .O(\wb_data_o[31]_i_1_n_0 )); + LUT5 #( + .INIT(32'h000000FE)) + \wb_data_o[31]_i_2 + (.I0(wb_addr_i[31]), + .I1(wb_addr_i[30]), + .I2(wb_addr_i[29]), + .I3(wb_addr_i[6]), + .I4(wb_addr_i[5]), + .O(\wb_data_o[31]_i_2_n_0 )); + LUT6 #( + .INIT(64'hA3A3A3A0A0A0A3A0)) + \wb_data_o[31]_i_3 + (.I0(\wb_data_o[31]_i_8_n_0 ), + .I1(wb_addr_i[3]), + .I2(wb_addr_i[4]), + .I3(rfr_ps_val[7]), + .I4(wb_addr_i[2]), + .I5(poc_o[31]), + .O(\wb_data_o[31]_i_3_n_0 )); + LUT3 #( + .INIT(8'h01)) + \wb_data_o[31]_i_4 + (.I0(wb_addr_i[29]), + .I1(wb_addr_i[30]), + .I2(wb_addr_i[31]), + .O(\wb_data_o[31]_i_4_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[31]_i_5 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[31]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[31]), + .I4(\wb_data_o[31]_i_9_n_0 ), + .O(\wb_data_o[31]_i_5_n_0 )); + LUT2 #( + .INIT(4'h1)) + \wb_data_o[31]_i_6 + (.I0(csc[3]), + .I1(csc[2]), + .O(\wb_data_o[31]_i_6_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \wb_data_o[31]_i_7 + (.I0(mc_data_ir[31]), + .I1(csc[5]), + .I2(mc_data_ir[15]), + .I3(csc[4]), + .I4(mc_data_ir[7]), + .O(\wb_data_o[31]_i_7_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[31]_i_8 + (.I0(\u0/u1/tms_reg_n_0_[31] ), + .I1(\u0/u1/csc_reg_n_0_[31] ), + .I2(wb_addr_i[3]), + .I3(tms[31]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[31] ), + .O(\wb_data_o[31]_i_8_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[31]_i_9 + (.I0(r2[31]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[31]), + .I3(\u3/u0/rd_adr [3]), + .O(\wb_data_o[31]_i_9_n_0 )); + LUT5 #( + .INIT(32'hFFFF0100)) + \wb_data_o[3]_i_1 + (.I0(\wb_data_o[31]_i_4_n_0 ), + .I1(wb_addr_i[6]), + .I2(wb_addr_i[5]), + .I3(\wb_data_o[3]_i_2_n_0 ), + .I4(\wb_data_o[3]_i_3_n_0 ), + .O(\wb_data_o[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[3]_i_2 + (.I0(\u0/csr_r_reg_n_0_[3] ), + .I1(poc_o[3]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask [3]), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[3]_i_4_n_0 ), + .O(\wb_data_o[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[3]_i_3 + (.I0(\wb_data_o[3]_i_5_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte0[3]), + .I3(csc[5]), + .I4(mc_data_ir[3]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[3]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[3]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[3] ), + .I1(\u0/u1/csc_reg_n_0_[3] ), + .I2(wb_addr_i[3]), + .I3(tms[3]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[3] ), + .O(\wb_data_o[3]_i_4_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[3]_i_5 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[3]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[3]), + .I4(\wb_data_o[3]_i_6_n_0 ), + .O(\wb_data_o[3]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[3]_i_6 + (.I0(r3[3]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[3]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[3]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFF100010)) + \wb_data_o[4]_i_1 + (.I0(wb_addr_i[6]), + .I1(wb_addr_i[5]), + .I2(\wb_data_o[4]_i_2_n_0 ), + .I3(\wb_data_o[31]_i_4_n_0 ), + .I4(\wb_data_o[4]_i_3_n_0 ), + .O(\wb_data_o[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[4]_i_2 + (.I0(\u0/csr_r_reg_n_0_[4] ), + .I1(poc_o[4]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask [4]), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[4]_i_4_n_0 ), + .O(\wb_data_o[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFE02FEFEFE020202)) + \wb_data_o[4]_i_3 + (.I0(\wb_data_o[4]_i_5_n_0 ), + .I1(csc[3]), + .I2(csc[2]), + .I3(mc_data_ir[4]), + .I4(csc[5]), + .I5(byte0[4]), + .O(\wb_data_o[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[4]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[4] ), + .I1(\u0/u1/csc_reg_n_0_[4] ), + .I2(wb_addr_i[3]), + .I3(tms[4]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[4] ), + .O(\wb_data_o[4]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[4]_i_5 + (.I0(\u3/u0/rd_adr [0]), + .I1(r0[4]), + .I2(\u3/u0/rd_adr [1]), + .I3(r1[4]), + .I4(\wb_data_o[4]_i_6_n_0 ), + .O(\wb_data_o[4]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[4]_i_6 + (.I0(r2[4]), + .I1(\u3/u0/rd_adr [2]), + .I2(r3[4]), + .I3(\u3/u0/rd_adr [3]), + .O(\wb_data_o[4]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFFFF0100)) + \wb_data_o[5]_i_1 + (.I0(\wb_data_o[31]_i_4_n_0 ), + .I1(wb_addr_i[6]), + .I2(wb_addr_i[5]), + .I3(\wb_data_o[5]_i_2_n_0 ), + .I4(\wb_data_o[5]_i_3_n_0 ), + .O(\wb_data_o[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[5]_i_2 + (.I0(\u0/csr_r_reg_n_0_[5] ), + .I1(poc_o[5]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask [5]), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[5]_i_4_n_0 ), + .O(\wb_data_o[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[5]_i_3 + (.I0(\wb_data_o[5]_i_5_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte0[5]), + .I3(csc[5]), + .I4(mc_data_ir[5]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[5]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[5] ), + .I1(\u0/u1/csc_reg_n_0_[5] ), + .I2(wb_addr_i[3]), + .I3(tms[5]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[5] ), + .O(\wb_data_o[5]_i_4_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[5]_i_5 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[5]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[5]), + .I4(\wb_data_o[5]_i_6_n_0 ), + .O(\wb_data_o[5]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[5]_i_6 + (.I0(r3[5]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[5]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[5]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFFFF0100)) + \wb_data_o[6]_i_1 + (.I0(\wb_data_o[31]_i_4_n_0 ), + .I1(wb_addr_i[6]), + .I2(wb_addr_i[5]), + .I3(\wb_data_o[6]_i_2_n_0 ), + .I4(\wb_data_o[6]_i_3_n_0 ), + .O(\wb_data_o[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[6]_i_2 + (.I0(\u0/csr_r_reg_n_0_[6] ), + .I1(poc_o[6]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask [6]), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[6]_i_4_n_0 ), + .O(\wb_data_o[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[6]_i_3 + (.I0(\wb_data_o[6]_i_5_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte0[6]), + .I3(csc[5]), + .I4(mc_data_ir[6]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[6]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[6] ), + .I1(\u0/u1/csc_reg_n_0_[6] ), + .I2(wb_addr_i[3]), + .I3(tms[6]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[6] ), + .O(\wb_data_o[6]_i_4_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[6]_i_5 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[6]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[6]), + .I4(\wb_data_o[6]_i_6_n_0 ), + .O(\wb_data_o[6]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[6]_i_6 + (.I0(r3[6]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[6]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[6]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFFFF0100)) + \wb_data_o[7]_i_1 + (.I0(\wb_data_o[31]_i_4_n_0 ), + .I1(wb_addr_i[6]), + .I2(wb_addr_i[5]), + .I3(\wb_data_o[7]_i_2_n_0 ), + .I4(\wb_data_o[7]_i_3_n_0 ), + .O(\wb_data_o[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[7]_i_2 + (.I0(\u0/csr_r_reg_n_0_[7] ), + .I1(poc_o[7]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask [7]), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[7]_i_4_n_0 ), + .O(\wb_data_o[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[7]_i_3 + (.I0(\wb_data_o[7]_i_5_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte0[7]), + .I3(csc[5]), + .I4(mc_data_ir[7]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[7]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[7] ), + .I1(\u0/u1/csc_reg_n_0_[7] ), + .I2(wb_addr_i[3]), + .I3(tms[7]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[7] ), + .O(\wb_data_o[7]_i_4_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[7]_i_5 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[7]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[7]), + .I4(\wb_data_o[7]_i_6_n_0 ), + .O(\wb_data_o[7]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[7]_i_6 + (.I0(r3[7]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[7]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[7]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFF100010)) + \wb_data_o[8]_i_1 + (.I0(wb_addr_i[6]), + .I1(wb_addr_i[5]), + .I2(\wb_data_o[8]_i_2_n_0 ), + .I3(\wb_data_o[31]_i_4_n_0 ), + .I4(\wb_data_o[8]_i_3_n_0 ), + .O(\wb_data_o[8]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[8]_i_2 + (.I0(sel0[0]), + .I1(poc_o[8]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask_r_reg_n_0_[8] ), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[8]_i_4_n_0 ), + .O(\wb_data_o[8]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFE02FEFEFE020202)) + \wb_data_o[8]_i_3 + (.I0(\wb_data_o[8]_i_5_n_0 ), + .I1(csc[3]), + .I2(csc[2]), + .I3(mc_data_ir[8]), + .I4(csc[5]), + .I5(byte1[0]), + .O(\wb_data_o[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[8]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[8] ), + .I1(\u0/u1/csc_reg_n_0_[8] ), + .I2(wb_addr_i[3]), + .I3(tms[8]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[8] ), + .O(\wb_data_o[8]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFF888)) + \wb_data_o[8]_i_5 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[8]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[8]), + .I4(\wb_data_o[8]_i_6_n_0 ), + .O(\wb_data_o[8]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[8]_i_6 + (.I0(r3[8]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[8]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[8]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFFFF0100)) + \wb_data_o[9]_i_1 + (.I0(\wb_data_o[31]_i_4_n_0 ), + .I1(wb_addr_i[6]), + .I2(wb_addr_i[5]), + .I3(\wb_data_o[9]_i_2_n_0 ), + .I4(\wb_data_o[9]_i_3_n_0 ), + .O(\wb_data_o[9]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[9]_i_2 + (.I0(sel0[1]), + .I1(poc_o[9]), + .I2(\wb_data_o[10]_i_4_n_0 ), + .I3(\u0/csc_mask_r_reg_n_0_[9] ), + .I4(\wb_data_o[10]_i_5_n_0 ), + .I5(\wb_data_o[9]_i_4_n_0 ), + .O(\wb_data_o[9]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7774447400000000)) + \wb_data_o[9]_i_3 + (.I0(\wb_data_o[9]_i_5_n_0 ), + .I1(\wb_data_o[31]_i_6_n_0 ), + .I2(byte1[1]), + .I3(csc[5]), + .I4(mc_data_ir[9]), + .I5(\wb_data_o[31]_i_4_n_0 ), + .O(\wb_data_o[9]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \wb_data_o[9]_i_4 + (.I0(\u0/u1/tms_reg_n_0_[9] ), + .I1(\u0/u1/csc_reg_n_0_[9] ), + .I2(wb_addr_i[3]), + .I3(tms[9]), + .I4(wb_addr_i[2]), + .I5(\u0/u0/csc_reg_n_0_[9] ), + .O(\wb_data_o[9]_i_4_n_0 )); + LUT5 #( + .INIT(32'h00000777)) + \wb_data_o[9]_i_5 + (.I0(\u3/u0/rd_adr [1]), + .I1(r1[9]), + .I2(\u3/u0/rd_adr [0]), + .I3(r0[9]), + .I4(\wb_data_o[9]_i_6_n_0 ), + .O(\wb_data_o[9]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \wb_data_o[9]_i_6 + (.I0(r3[9]), + .I1(\u3/u0/rd_adr [3]), + .I2(r2[9]), + .I3(\u3/u0/rd_adr [2]), + .O(\wb_data_o[9]_i_6_n_0 )); + LUT6 #( + .INIT(64'h0000000004440404)) + wb_err_i_1 + (.I0(wb_err_o), + .I1(\wb_data_o[31]_i_4_n_0 ), + .I2(wb_ack_o_i_5_n_0), + .I3(wb_ack_o_i_4_n_0), + .I4(mem_ack), + .I5(wb_ack_o_i_3_n_0), + .O(\u6/wb_err0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'hF1F0)) + wb_first_r_i_1 + (.I0(wb_err_o), + .I1(wb_ack_o), + .I2(\u6/wb_first_set ), + .I3(\u6/wb_first_r ), + .O(wb_first_r_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h02000000)) + wb_first_r_i_2 + (.I0(\wb_data_o[31]_i_4_n_0 ), + .I1(\u6/read_go_r ), + .I2(\u6/write_go_r ), + .I3(wb_stb_i), + .I4(wb_cyc_i), + .O(\u6/wb_first_set )); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'h32)) + wb_stb_first_i_1 + (.I0(wb_stb_first_i_2_n_0), + .I1(mem_ack), + .I2(\u5/wb_stb_first_reg_n_0 ), + .O(wb_stb_first_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h888A8888)) + wb_stb_first_i_2 + (.I0(wb_stb_i), + .I1(\u6/wb_first_set ), + .I2(wb_err_o), + .I3(wb_ack_o), + .I4(\u6/wb_first_r ), + .O(wb_stb_first_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT1 #( + .INIT(2'h1)) + wb_wait_r2_i_1 + (.I0(mc_adv__i_3_n_0), + .O(wb_wait)); + LUT5 #( + .INIT(32'h44000400)) + wb_write_go_r_i_1 + (.I0(wb_write_go_r_i_2_n_0), + .I1(\u6/write_go_r1 ), + .I2(wb_stb_i), + .I3(wb_cyc_i), + .I4(wb_we_i), + .O(wb_write_go)); + LUT6 #( + .INIT(64'hBAAAAAAAAAAAAAAA)) + wb_write_go_r_i_2 + (.I0(\u6/rmw_r ), + .I1(wr_hold), + .I2(\u6/rmw_en ), + .I3(wb_we_i), + .I4(wb_cyc_i), + .I5(wb_stb_i), + .O(wb_write_go_r_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT5 #( + .INIT(32'hBF008000)) + wp_err_i_1 + (.I0(wp_err_i_2_n_0), + .I1(wb_stb_i), + .I2(cs_le), + .I3(wb_cyc_i), + .I4(wp_err), + .O(wp_err_i_1_n_0)); + LUT5 #( + .INIT(32'h4F004400)) + wp_err_i_2 + (.I0(\csc[11]_i_7_n_0 ), + .I1(\u0/u1/csc_reg_n_0_[8] ), + .I2(\csc[11]_i_3_n_0 ), + .I3(wb_we_i), + .I4(\u0/u0/csc_reg_n_0_[8] ), + .O(wp_err_i_2_n_0)); + LUT4 #( + .INIT(16'hFBBB)) + \wr_adr[0]_i_1 + (.I0(\u3/u0/p_0_in ), + .I1(wb_cyc_i), + .I2(wb_we_i), + .I3(wb_stb_i), + .O(\wr_adr[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'h0888)) + \wr_adr[1]_i_1 + (.I0(\u3/u0/wr_adr_reg_n_0_[0] ), + .I1(wb_cyc_i), + .I2(wb_we_i), + .I3(wb_stb_i), + .O(\wr_adr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT4 #( + .INIT(16'h0888)) + \wr_adr[2]_i_1 + (.I0(\u3/u0/p_0_in1_in ), + .I1(wb_cyc_i), + .I2(wb_we_i), + .I3(wb_stb_i), + .O(\wr_adr[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFBBB)) + \wr_adr[3]_i_1 + (.I0(dv), + .I1(wb_cyc_i), + .I2(wb_we_i), + .I3(wb_stb_i), + .O(\wr_adr[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT4 #( + .INIT(16'h0888)) + \wr_adr[3]_i_2 + (.I0(\u3/u0/p_0_in0_in ), + .I1(wb_cyc_i), + .I2(wb_we_i), + .I3(wb_stb_i), + .O(\wr_adr[3]_i_2_n_0 )); + LUT3 #( + .INIT(8'hBA)) + wr_cycle_i_1 + (.I0(\u5/wr_set ), + .I1(\u5/burst_cnt_ld ), + .I2(wr_cycle), + .O(wr_cycle_i_1_n_0)); + LUT6 #( + .INIT(64'h0E0E0E0E0E000000)) + wr_cycle_i_2 + (.I0(wr_cycle_i_3_n_0), + .I1(\u5/state [4]), + .I2(wr_cycle_i_4_n_0), + .I3(wb_stb_i), + .I4(wb_we_i), + .I5(wb_write_go), + .O(\u5/wr_set )); + LUT6 #( + .INIT(64'h0100000000000000)) + wr_cycle_i_3 + (.I0(\mc_addr[23]_i_3_n_0 ), + .I1(\mc_addr[14]_i_4_n_0 ), + .I2(\FSM_sequential_state[5]_i_9_n_0 ), + .I3(\FSM_sequential_state[5]_i_8_n_0 ), + .I4(\u5/lookup_ready2 ), + .I5(mc_adv__i_3_n_0), + .O(wr_cycle_i_3_n_0)); + LUT6 #( + .INIT(64'hFFFFFF5FFFEFFFFF)) + wr_cycle_i_4 + (.I0(\u5/state [4]), + .I1(\u5/state [1]), + .I2(rfr_ack_r_i_7_n_0), + .I3(\u5/state [3]), + .I4(\u5/state [0]), + .I5(\u5/state [2]), + .O(wr_cycle_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'hBF80)) + wr_hold_i_1 + (.I0(wb_we_i), + .I1(wb_cyc_i), + .I2(wb_stb_i), + .I3(wr_hold), + .O(wr_hold_i_1_n_0)); + LUT5 #( + .INIT(32'hA8888888)) + write_go_r1_i_1 + (.I0(wb_cyc_i), + .I1(\u6/write_go_r ), + .I2(\wb_data_o[31]_i_4_n_0 ), + .I3(wb_stb_i), + .I4(wb_we_i), + .O(\u6/write_go_r10 )); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT4 #( + .INIT(16'hA020)) + write_go_r_i_1 + (.I0(\u6/write_go_r1 ), + .I1(wb_stb_i), + .I2(wb_cyc_i), + .I3(wb_we_i), + .O(\u6/write_go_r0 )); +endmodule diff --git a/designs/encrypted_ip/des3_area/mc_wb_if.v b/designs/encrypted_ip/des3_area/mc_wb_if.v new file mode 100644 index 000000000..af7beb36f --- /dev/null +++ b/designs/encrypted_ip/des3_area/mc_wb_if.v @@ -0,0 +1,248 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// WISHBONE Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_wb_if.v,v 1.6 2002-01-21 13:08:52 rudi Exp $ +// +// $Date: 2002-01-21 13:08:52 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.5 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.4 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.3 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug +// fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:47 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_wb_if(clk, rst, + wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o, + wb_read_go, wb_write_go, + wb_first, wb_wait, mem_ack, wr_hold, + err, par_err, wp_err, + wb_data_o, mem_dout, rf_dout); + +input clk, rst; +input [31:0] wb_addr_i; +input wb_cyc_i; +input wb_stb_i; +input wb_we_i; +output wb_err; +output wb_ack_o; +output wb_read_go; +output wb_write_go; +output wb_first; +output wb_wait; +input mem_ack; +output wr_hold; +input err, par_err, wp_err; +output [31:0] wb_data_o; +input [31:0] mem_dout, rf_dout; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +wire mem_sel; +reg read_go_r; +reg read_go_r1; +reg write_go_r; +reg write_go_r1; +reg wb_first_r; +wire wb_first_set; +reg wr_hold; +wire rmw; +reg rmw_r; +reg rmw_en; +reg wb_ack_o; +reg wb_err; +reg [31:0] wb_data_o; + +//////////////////////////////////////////////////////////////////// +// +// Memory Go Logic +// + +assign mem_sel = `MC_MEM_SEL; + +always @(posedge clk or posedge rst) + if(rst) rmw_en <= #1 1'b0; + else + if(wb_ack_o) rmw_en <= #1 1'b1; + else + if(!wb_cyc_i) rmw_en <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) rmw_r <= #1 1'b0; + else rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en; + +assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en); + +always @(posedge clk or posedge rst) + if(rst) read_go_r1 <= #1 1'b0; + else read_go_r1 <= #1 !rmw & wb_cyc_i & + ((wb_stb_i & mem_sel & !wb_we_i) | read_go_r); + +always @(posedge clk or posedge rst) + if(rst) read_go_r <= #1 1'b0; + else read_go_r <= #1 read_go_r1 & wb_cyc_i; + +assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i; + +always @(posedge clk or posedge rst) + if(rst) write_go_r1 <= #1 1'b0; + else write_go_r1 <= #1 wb_cyc_i & + ((wb_stb_i & mem_sel & wb_we_i) | write_go_r); + +always @(posedge clk or posedge rst) + if(rst) write_go_r <= #1 1'b0; + else write_go_r <= #1 write_go_r1 & wb_cyc_i & + ((wb_we_i & wb_stb_i) | !wb_stb_i); + +assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i & + ((wb_we_i & wb_stb_i) | !wb_stb_i); + +assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r); +assign wb_first = wb_first_set | (wb_first_r & !wb_ack_o & !wb_err); + +always @(posedge clk or posedge rst) + if(rst) wb_first_r <= #1 1'b0; + else + if(wb_first_set) wb_first_r <= #1 1'b1; + else + if(wb_ack_o | wb_err) wb_first_r <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) wr_hold <= #1 1'b0; + else + if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i; + +//////////////////////////////////////////////////////////////////// +// +// WB Ack +// + +wire wb_err_d; + +// Ack no longer asserted when wb_err is asserted +always @(posedge clk or posedge rst) + if(rst) wb_ack_o <= #1 1'b0; + else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack & !wb_err_d : + `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o; + +assign wb_err_d = wb_cyc_i & wb_stb_i & (par_err | err | wp_err); + +always @(posedge clk or posedge rst) + if(rst) wb_err <= #1 1'b0; + else wb_err <= #1 `MC_MEM_SEL & wb_err_d & !wb_err; + +//////////////////////////////////////////////////////////////////// +// +// Memory Wait Logic +// + +assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go); + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Data Output +// + +always @(posedge clk) + wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout; + +endmodule diff --git a/designs/encrypted_ip/des3_area/sbox1.v b/designs/encrypted_ip/des3_area/sbox1.v new file mode 100644 index 000000000..76d5e22f6 --- /dev/null +++ b/designs/encrypted_ip/des3_area/sbox1.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox1(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 14; + 1: dout = 4; + 2: dout = 13; + 3: dout = 1; + 4: dout = 2; + 5: dout = 15; + 6: dout = 11; + 7: dout = 8; + 8: dout = 3; + 9: dout = 10; + 10: dout = 6; + 11: dout = 12; + 12: dout = 5; + 13: dout = 9; + 14: dout = 0; + 15: dout = 7; + + 16: dout = 0; + 17: dout = 15; + 18: dout = 7; + 19: dout = 4; + 20: dout = 14; + 21: dout = 2; + 22: dout = 13; + 23: dout = 1; + 24: dout = 10; + 25: dout = 6; + 26: dout = 12; + 27: dout = 11; + 28: dout = 9; + 29: dout = 5; + 30: dout = 3; + 31: dout = 8; + + 32: dout = 4; + 33: dout = 1; + 34: dout = 14; + 35: dout = 8; + 36: dout = 13; + 37: dout = 6; + 38: dout = 2; + 39: dout = 11; + 40: dout = 15; + 41: dout = 12; + 42: dout = 9; + 43: dout = 7; + 44: dout = 3; + 45: dout = 10; + 46: dout = 5; + 47: dout = 0; + + 48: dout = 15; + 49: dout = 12; + 50: dout = 8; + 51: dout = 2; + 52: dout = 4; + 53: dout = 9; + 54: dout = 1; + 55: dout = 7; + 56: dout = 5; + 57: dout = 11; + 58: dout = 3; + 59: dout = 14; + 60: dout = 10; + 61: dout = 0; + 62: dout = 6; + 63: dout = 13; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_area/sbox2.v b/designs/encrypted_ip/des3_area/sbox2.v new file mode 100644 index 000000000..aa505f3a2 --- /dev/null +++ b/designs/encrypted_ip/des3_area/sbox2.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox2(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 15; + 1: dout = 1; + 2: dout = 8; + 3: dout = 14; + 4: dout = 6; + 5: dout = 11; + 6: dout = 3; + 7: dout = 4; + 8: dout = 9; + 9: dout = 7; + 10: dout = 2; + 11: dout = 13; + 12: dout = 12; + 13: dout = 0; + 14: dout = 5; + 15: dout = 10; + + 16: dout = 3; + 17: dout = 13; + 18: dout = 4; + 19: dout = 7; + 20: dout = 15; + 21: dout = 2; + 22: dout = 8; + 23: dout = 14; + 24: dout = 12; + 25: dout = 0; + 26: dout = 1; + 27: dout = 10; + 28: dout = 6; + 29: dout = 9; + 30: dout = 11; + 31: dout = 5; + + 32: dout = 0; + 33: dout = 14; + 34: dout = 7; + 35: dout = 11; + 36: dout = 10; + 37: dout = 4; + 38: dout = 13; + 39: dout = 1; + 40: dout = 5; + 41: dout = 8; + 42: dout = 12; + 43: dout = 6; + 44: dout = 9; + 45: dout = 3; + 46: dout = 2; + 47: dout = 15; + + 48: dout = 13; + 49: dout = 8; + 50: dout = 10; + 51: dout = 1; + 52: dout = 3; + 53: dout = 15; + 54: dout = 4; + 55: dout = 2; + 56: dout = 11; + 57: dout = 6; + 58: dout = 7; + 59: dout = 12; + 60: dout = 0; + 61: dout = 5; + 62: dout = 14; + 63: dout = 9; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_area/sbox3.v b/designs/encrypted_ip/des3_area/sbox3.v new file mode 100644 index 000000000..0c6cddf03 --- /dev/null +++ b/designs/encrypted_ip/des3_area/sbox3.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox3(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 10; + 1: dout = 0; + 2: dout = 9; + 3: dout = 14; + 4: dout = 6; + 5: dout = 3; + 6: dout = 15; + 7: dout = 5; + 8: dout = 1; + 9: dout = 13; + 10: dout = 12; + 11: dout = 7; + 12: dout = 11; + 13: dout = 4; + 14: dout = 2; + 15: dout = 8; + + 16: dout = 13; + 17: dout = 7; + 18: dout = 0; + 19: dout = 9; + 20: dout = 3; + 21: dout = 4; + 22: dout = 6; + 23: dout = 10; + 24: dout = 2; + 25: dout = 8; + 26: dout = 5; + 27: dout = 14; + 28: dout = 12; + 29: dout = 11; + 30: dout = 15; + 31: dout = 1; + + 32: dout = 13; + 33: dout = 6; + 34: dout = 4; + 35: dout = 9; + 36: dout = 8; + 37: dout = 15; + 38: dout = 3; + 39: dout = 0; + 40: dout = 11; + 41: dout = 1; + 42: dout = 2; + 43: dout = 12; + 44: dout = 5; + 45: dout = 10; + 46: dout = 14; + 47: dout = 7; + + 48: dout = 1; + 49: dout = 10; + 50: dout = 13; + 51: dout = 0; + 52: dout = 6; + 53: dout = 9; + 54: dout = 8; + 55: dout = 7; + 56: dout = 4; + 57: dout = 15; + 58: dout = 14; + 59: dout = 3; + 60: dout = 11; + 61: dout = 5; + 62: dout = 2; + 63: dout = 12; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_area/sbox4.v b/designs/encrypted_ip/des3_area/sbox4.v new file mode 100644 index 000000000..ec531c1e8 --- /dev/null +++ b/designs/encrypted_ip/des3_area/sbox4.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox4(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 7; + 1: dout = 13; + 2: dout = 14; + 3: dout = 3; + 4: dout = 0; + 5: dout = 6; + 6: dout = 9; + 7: dout = 10; + 8: dout = 1; + 9: dout = 2; + 10: dout = 8; + 11: dout = 5; + 12: dout = 11; + 13: dout = 12; + 14: dout = 4; + 15: dout = 15; + + 16: dout = 13; + 17: dout = 8; + 18: dout = 11; + 19: dout = 5; + 20: dout = 6; + 21: dout = 15; + 22: dout = 0; + 23: dout = 3; + 24: dout = 4; + 25: dout = 7; + 26: dout = 2; + 27: dout = 12; + 28: dout = 1; + 29: dout = 10; + 30: dout = 14; + 31: dout = 9; + + 32: dout = 10; + 33: dout = 6; + 34: dout = 9; + 35: dout = 0; + 36: dout = 12; + 37: dout = 11; + 38: dout = 7; + 39: dout = 13; + 40: dout = 15; + 41: dout = 1; + 42: dout = 3; + 43: dout = 14; + 44: dout = 5; + 45: dout = 2; + 46: dout = 8; + 47: dout = 4; + + 48: dout = 3; + 49: dout = 15; + 50: dout = 0; + 51: dout = 6; + 52: dout = 10; + 53: dout = 1; + 54: dout = 13; + 55: dout = 8; + 56: dout = 9; + 57: dout = 4; + 58: dout = 5; + 59: dout = 11; + 60: dout = 12; + 61: dout = 7; + 62: dout = 2; + 63: dout = 14; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_area/sbox5.v b/designs/encrypted_ip/des3_area/sbox5.v new file mode 100644 index 000000000..f874c25cc --- /dev/null +++ b/designs/encrypted_ip/des3_area/sbox5.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox5(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 2; + 1: dout = 12; + 2: dout = 4; + 3: dout = 1; + 4: dout = 7; + 5: dout = 10; + 6: dout = 11; + 7: dout = 6; + 8: dout = 8; + 9: dout = 5; + 10: dout = 3; + 11: dout = 15; + 12: dout = 13; + 13: dout = 0; + 14: dout = 14; + 15: dout = 9; + + 16: dout = 14; + 17: dout = 11; + 18: dout = 2; + 19: dout = 12; + 20: dout = 4; + 21: dout = 7; + 22: dout = 13; + 23: dout = 1; + 24: dout = 5; + 25: dout = 0; + 26: dout = 15; + 27: dout = 10; + 28: dout = 3; + 29: dout = 9; + 30: dout = 8; + 31: dout = 6; + + 32: dout = 4; + 33: dout = 2; + 34: dout = 1; + 35: dout = 11; + 36: dout = 10; + 37: dout = 13; + 38: dout = 7; + 39: dout = 8; + 40: dout = 15; + 41: dout = 9; + 42: dout = 12; + 43: dout = 5; + 44: dout = 6; + 45: dout = 3; + 46: dout = 0; + 47: dout = 14; + + 48: dout = 11; + 49: dout = 8; + 50: dout = 12; + 51: dout = 7; + 52: dout = 1; + 53: dout = 14; + 54: dout = 2; + 55: dout = 13; + 56: dout = 6; + 57: dout = 15; + 58: dout = 0; + 59: dout = 9; + 60: dout = 10; + 61: dout = 4; + 62: dout = 5; + 63: dout = 3; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_area/sbox6.v b/designs/encrypted_ip/des3_area/sbox6.v new file mode 100644 index 000000000..58fc86af0 --- /dev/null +++ b/designs/encrypted_ip/des3_area/sbox6.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox6(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 12; + 1: dout = 1; + 2: dout = 10; + 3: dout = 15; + 4: dout = 9; + 5: dout = 2; + 6: dout = 6; + 7: dout = 8; + 8: dout = 0; + 9: dout = 13; + 10: dout = 3; + 11: dout = 4; + 12: dout = 14; + 13: dout = 7; + 14: dout = 5; + 15: dout = 11; + + 16: dout = 10; + 17: dout = 15; + 18: dout = 4; + 19: dout = 2; + 20: dout = 7; + 21: dout = 12; + 22: dout = 9; + 23: dout = 5; + 24: dout = 6; + 25: dout = 1; + 26: dout = 13; + 27: dout = 14; + 28: dout = 0; + 29: dout = 11; + 30: dout = 3; + 31: dout = 8; + + 32: dout = 9; + 33: dout = 14; + 34: dout = 15; + 35: dout = 5; + 36: dout = 2; + 37: dout = 8; + 38: dout = 12; + 39: dout = 3; + 40: dout = 7; + 41: dout = 0; + 42: dout = 4; + 43: dout = 10; + 44: dout = 1; + 45: dout = 13; + 46: dout = 11; + 47: dout = 6; + + 48: dout = 4; + 49: dout = 3; + 50: dout = 2; + 51: dout = 12; + 52: dout = 9; + 53: dout = 5; + 54: dout = 15; + 55: dout = 10; + 56: dout = 11; + 57: dout = 14; + 58: dout = 1; + 59: dout = 7; + 60: dout = 6; + 61: dout = 0; + 62: dout = 8; + 63: dout = 13; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_area/sbox7.v b/designs/encrypted_ip/des3_area/sbox7.v new file mode 100644 index 000000000..f27957e2f --- /dev/null +++ b/designs/encrypted_ip/des3_area/sbox7.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox7(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 4; + 1: dout = 11; + 2: dout = 2; + 3: dout = 14; + 4: dout = 15; + 5: dout = 0; + 6: dout = 8; + 7: dout = 13; + 8: dout = 3; + 9: dout = 12; + 10: dout = 9; + 11: dout = 7; + 12: dout = 5; + 13: dout = 10; + 14: dout = 6; + 15: dout = 1; + + 16: dout = 13; + 17: dout = 0; + 18: dout = 11; + 19: dout = 7; + 20: dout = 4; + 21: dout = 9; + 22: dout = 1; + 23: dout = 10; + 24: dout = 14; + 25: dout = 3; + 26: dout = 5; + 27: dout = 12; + 28: dout = 2; + 29: dout = 15; + 30: dout = 8; + 31: dout = 6; + + 32: dout = 1; + 33: dout = 4; + 34: dout = 11; + 35: dout = 13; + 36: dout = 12; + 37: dout = 3; + 38: dout = 7; + 39: dout = 14; + 40: dout = 10; + 41: dout = 15; + 42: dout = 6; + 43: dout = 8; + 44: dout = 0; + 45: dout = 5; + 46: dout = 9; + 47: dout = 2; + + 48: dout = 6; + 49: dout = 11; + 50: dout = 13; + 51: dout = 8; + 52: dout = 1; + 53: dout = 4; + 54: dout = 10; + 55: dout = 7; + 56: dout = 9; + 57: dout = 5; + 58: dout = 0; + 59: dout = 15; + 60: dout = 14; + 61: dout = 2; + 62: dout = 3; + 63: dout = 12; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_area/sbox8.v b/designs/encrypted_ip/des3_area/sbox8.v new file mode 100644 index 000000000..5ebad6388 --- /dev/null +++ b/designs/encrypted_ip/des3_area/sbox8.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox8(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 13; + 1: dout = 2; + 2: dout = 8; + 3: dout = 4; + 4: dout = 6; + 5: dout = 15; + 6: dout = 11; + 7: dout = 1; + 8: dout = 10; + 9: dout = 9; + 10: dout = 3; + 11: dout = 14; + 12: dout = 5; + 13: dout = 0; + 14: dout = 12; + 15: dout = 7; + + 16: dout = 1; + 17: dout = 15; + 18: dout = 13; + 19: dout = 8; + 20: dout = 10; + 21: dout = 3; + 22: dout = 7; + 23: dout = 4; + 24: dout = 12; + 25: dout = 5; + 26: dout = 6; + 27: dout = 11; + 28: dout = 0; + 29: dout = 14; + 30: dout = 9; + 31: dout = 2; + + 32: dout = 7; + 33: dout = 11; + 34: dout = 4; + 35: dout = 1; + 36: dout = 9; + 37: dout = 12; + 38: dout = 14; + 39: dout = 2; + 40: dout = 0; + 41: dout = 6; + 42: dout = 10; + 43: dout = 13; + 44: dout = 15; + 45: dout = 3; + 46: dout = 5; + 47: dout = 8; + + 48: dout = 2; + 49: dout = 1; + 50: dout = 14; + 51: dout = 7; + 52: dout = 4; + 53: dout = 10; + 54: dout = 8; + 55: dout = 13; + 56: dout = 15; + 57: dout = 12; + 58: dout = 9; + 59: dout = 0; + 60: dout = 3; + 61: dout = 5; + 62: dout = 6; + 63: dout = 11; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_area/top.v b/designs/encrypted_ip/des3_area/top.v new file mode 100644 index 000000000..8b86d93ea --- /dev/null +++ b/designs/encrypted_ip/des3_area/top.v @@ -0,0 +1,200 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 07/17/2017 01:29:40 PM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +// +//module top( +// input clk, +// input reset, +// input [15:0] sw, +// input [4:0] btn, // Not used +// output [15:0] led, +// output [6:0] seg, // Not used +// output dp, // Not used +// output [7:0] an // Not used +// ); +////////////////////////////////////////////////////////////////////////////////// + + +module top( + input clk, + input reset, + input [15:0] sw, + input [4:0] btn, // Not used + output [15:0] led, + output [6:0] seg, // Not used + output dp, // Not used + output [7:0] an // Not used + ); + + assign seg = {btn, 2'b00}; + assign dp = 1'b0; + assign an = 8'b00000000; + + + wire [112:0] mem_ctrl_i; + wire [151:0] mem_ctrl_o; + + // des3_area added here + wire [63:0] des3_area_i; + wire [63:0] des3_area_o; + wire [55:0] key1, key2, key3; + wire decrypt; + wire [5:0] roundSel; + // end added code + + wire [70:0] wb_lcd_i; + wire [39:0] wb_lcd_o; + wire [80:0] ac97_0_i; + wire [47:0] ac97_0_o; + wire [80:0] ac97_1_i; + wire [47:0] ac97_1_o; + + // 113 bits + assign mem_ctrl_i = {des3_area_o, des3_area_o[49:0]}; + + wire [64:0] four_inputs; + assign four_inputs = {4{sw}}; + + // 64 bits + assign des3_area_i = four_inputs; + + // new des3_area assignments + assign key1 = four_inputs[55:0]; + assign key2 = four_inputs[59:4]; + assign key3 = four_inputs[63:8]; + assign decrypt = clk ^ reset; + assign roundSel = {mem_ctrl_o[99], mem_ctrl_o[89], mem_ctrl_o[79], mem_ctrl_o[69], mem_ctrl_o[59]}; + + // 81 bits + assign ac97_0_i = {sw[4:0], mem_ctrl_o[75:0]}; + + // 81 bits + assign ac97_1_i = {sw[9:5], mem_ctrl_o[151:76]}; + + + // 16 bits + assign led = {&ac97_0_o[5:0], + &ac97_0_o[11:6], + &ac97_0_o[17:12], + &ac97_0_o[23:18], + &ac97_0_o[29:24], + &ac97_0_o[35:30], + &ac97_0_o[41:36], + &ac97_0_o[47:42], + &ac97_1_o[5:0], + &ac97_1_o[11:6], + &ac97_1_o[17:12], + &ac97_1_o[23:18], + &ac97_1_o[29:24], + &ac97_1_o[35:30], + &ac97_1_o[41:36], + &ac97_1_o[47:42]}; + + /////////////////////////////////////////////////////////////////// + // + // Module Instantiations + // + mc_top mem_ctrl_0( + .clk_i(clk), + .rst_i(reset), + + // -------------------------------------- + // WISHBONE SLAVE INTERFACE + .wb_data_i(mem_ctrl_i[31:0]), + .wb_data_o(mem_ctrl_o[31:0]), + .wb_addr_i(mem_ctrl_i[63:32]), + .wb_sel_i(mem_ctrl_i[67:64]), + .wb_we_i(mem_ctrl_i[68]), + .wb_cyc_i(mem_ctrl_i[69]), + .wb_stb_i(mem_ctrl_i[70]), + .wb_ack_o(mem_ctrl_o[32]), + .wb_err_o(mem_ctrl_o[33]), + + // -------------------------------------- + // Suspend Resume Interface + .susp_req_i(mem_ctrl_i[71]), + .resume_req_i(mem_ctrl_i[72]), + .suspended_o(mem_ctrl_o[34]), + + // POC + .poc_o(mem_ctrl_o[66:35]), + + // -------------------------------------- + // Memory Bus Signals + .mc_clk_i(mem_ctrl_i[73]), + .mc_br_pad_i(mem_ctrl_i[74]), + .mc_bg_pad_o(mem_ctrl_o[67]), + .mc_ack_pad_i(mem_ctrl_i[75]), + .mc_addr_pad_o(mem_ctrl_o[91:68]), + .mc_data_pad_i(mem_ctrl_i[107:76]), + .mc_data_pad_o(mem_ctrl_o[123:92]), + .mc_dp_pad_i(mem_ctrl_i[111:108]), + .mc_dp_pad_o(mem_ctrl_o[127:124]), + .mc_doe_pad_doe_o(mem_ctrl_o[128]), + .mc_dqm_pad_o(mem_ctrl_o[132:129]), + .mc_oe_pad_o_(mem_ctrl_o[133]), + .mc_we_pad_o_(mem_ctrl_o[134]), + .mc_cas_pad_o_(mem_ctrl_o[135]), + .mc_ras_pad_o_(mem_ctrl_o[136]), + .mc_cke_pad_o_(mem_ctrl_o[137]), + .mc_cs_pad_o_(mem_ctrl_o[145:138]), + .mc_sts_pad_i(mem_ctrl_i[112]), + .mc_rp_pad_o_(mem_ctrl_o[146]), + .mc_vpen_pad_o(mem_ctrl_o[147]), + .mc_adsc_pad_o_(mem_ctrl_o[148]), + .mc_adv_pad_o_(mem_ctrl_o[149]), + .mc_zz_pad_o(mem_ctrl_o[150]), + .mc_coe_pad_coe_o(mem_ctrl_o[151])); + + ac97_top ac97_0(.clk_i(clk), .rst_i(reset), + + .wb_data_i(ac97_0_i[31:0]), .wb_data_o(ac97_0_o[31:0]), .wb_addr_i(ac97_0_i[63:32]), + .wb_sel_i(ac97_0_i[67:64]), .wb_we_i(ac97_0_i[68]), .wb_cyc_i(ac97_0_i[69]), + .wb_stb_i(ac97_0_i[70]), .wb_ack_o(ac97_0_o[32]), .wb_err_o(ac97_0_o[33]), + + .int_o(ac97_0_o[34]), .dma_req_o(ac97_0_o[43:35]), .dma_ack_i(ac97_0_i[79:71]), + .suspended_o(ac97_0_o[44]), + + .bit_clk_pad_i(clk), .sync_pad_o(ac97_0_o[45]), .sdata_pad_o(ac97_0_o[46]), + .sdata_pad_i(ac97_0_i[80]), .ac97_reset_pad_o_(ac97_0_o[47])); + + ac97_top ac97_1(.clk_i(clk), .rst_i(reset), + + .wb_data_i(ac97_1_i[31:0]), .wb_data_o(ac97_1_o[31:0]), .wb_addr_i(ac97_1_i[63:32]), + .wb_sel_i(ac97_1_i[67:64]), .wb_we_i(ac97_1_i[68]), .wb_cyc_i(ac97_1_i[69]), + .wb_stb_i(ac97_1_i[70]), .wb_ack_o(ac97_1_o[32]), .wb_err_o(ac97_1_o[33]), + + .int_o(ac97_1_o[34]), .dma_req_o(ac97_1_o[43:35]), .dma_ack_i(ac97_1_i[79:71]), + .suspended_o(ac97_1_o[44]), + + .bit_clk_pad_i(clk), .sync_pad_o(ac97_1_o[45]), .sdata_pad_o(ac97_1_o[46]), + .sdata_pad_i(ac97_1_i[80]), .ac97_reset_pad_o_(ac97_1_o[47])); + + des3_area des3_area_0( + .desOut(des3_area_o), + .desIn(des3_area_i), + .key1(key1), + .key2(key2), + .key3(key3), + .decrypt(decrypt), + .roundSel(roundSel), + .clk(clk) + ); + +endmodule From 7f637a3d97053f2a8539690722d9b1693132145b Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Wed, 13 Dec 2023 01:58:37 -0700 Subject: [PATCH 14/25] gathering utilization --- bfasst/flows/encrypted_ip.py | 45 ++++++++++++---- bfasst/tools/impl/vivado_impl.tcl.mustache | 2 +- bfasst/tools/ip/loader.py | 18 +++++-- bfasst/tools/ip/loader_vivado.tcl.mustache | 1 + bfasst/tools/synth/vivado_synth.py | 1 + bfasst/tools/synth/vivado_synth.tcl.mustache | 1 + bfasst/utils/vivado.py | 55 ++++++++++++++++++++ 7 files changed, 109 insertions(+), 14 deletions(-) create mode 100644 bfasst/utils/vivado.py diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py index 89716d3d7..381fdc1e8 100644 --- a/bfasst/flows/encrypted_ip.py +++ b/bfasst/flows/encrypted_ip.py @@ -1,12 +1,15 @@ """Flow to create Vivado synthesis and implementation ninja snippets.""" import pathlib +import re import yaml from bfasst.flows.flow import Flow +from bfasst.tools.impl.vivado_impl import VivadoImpl from bfasst.tools.ip.ipencrypter import IpEncrypter from bfasst.tools.ip.loader import EncryptedIpLoader from bfasst.tools.synth.vivado_synth import VivadoSynth +from bfasst.utils.vivado import parse_hierarchical_utilization class EncryptedIP(Flow): @@ -20,6 +23,10 @@ def __init__(self, design): # ip_definitions = [ip["definition"] for ip in self.design_props.encrypted_ip["ip"]] + # Perform the regular vivado CAD flow + self.synth_regular = VivadoSynth(self, design) + VivadoImpl(self, design) + # Synthesize and encrypt each encrypte IP for ip in self.design_props.encrypted_ip["ip"]: ip_definition = ip["definition"] @@ -46,24 +53,42 @@ def __init__(self, design): ip["ciphertext_path"] = str(ip_encrypter_tool.outputs["lut_ciphertext"]) # Synthesize the top module - synth_tool = VivadoSynth(self, design, ooc=True, synth_options="-flatten_hierarchy rebuilt") - synth_tool.verilog = [ + self.top_synth_tool = VivadoSynth( + self, design, ooc=True, synth_options="-flatten_hierarchy rebuilt" + ) + self.top_synth_tool.verilog = [ self.design_path / v for v in self.design_props.encrypted_ip["user_files"] ] - synth_tool.verilog.extend(encrypted_ip_paths) - - encrypted_ip_yaml_path = self.design_build_path / "encrypted_ip.yaml" - encrypted_ip_yaml_path.parent.mkdir(exist_ok=True, parents=True) - with open(encrypted_ip_yaml_path, "w") as f: - yaml.dump(self.design_props.encrypted_ip["ip"], f) + self.top_synth_tool.verilog.extend(encrypted_ip_paths) # Encrypted IP Shell EncryptedIpLoader( self, design, - user_synth_dcp_path=synth_tool.outputs["synth_dcp"], - encrypted_ip_yaml_path=encrypted_ip_yaml_path, + user_synth_dcp_path=self.top_synth_tool.outputs["synth_dcp"], + encrypted_ip_data=self.design_props.encrypted_ip["ip"], ) def get_top_level_flow_path(self): return pathlib.Path(__file__) + + def post_execute(self): + out_csv_path = self.design_build_path / "area_results.txt" + + # Get regular synthesis results + reg_utilization_file = self.synth_regular.outputs["utilization"] + encrypted_utilization_file = self.top_synth_tool.outputs["utilization"] + + regular_data = parse_hierarchical_utilization(reg_utilization_file) + encrypted_data = parse_hierarchical_utilization(encrypted_utilization_file) + + instances = ["top_0"] + [ + f"top_0/{definition}" + for ip in self.design_props.encrypted_ip["ip"] + for definition in ip["instances"] + ] + + for instance in instances: + if + assert instance in regular_data, f"Instance {instance} not found in regular data" + assert instance in encrypted_data, f"Instance {instance} not found in encrypted data" diff --git a/bfasst/tools/impl/vivado_impl.tcl.mustache b/bfasst/tools/impl/vivado_impl.tcl.mustache index ee094eed1..1fe2e842e 100644 --- a/bfasst/tools/impl/vivado_impl.tcl.mustache +++ b/bfasst/tools/impl/vivado_impl.tcl.mustache @@ -13,7 +13,7 @@ route_design write_checkpoint -force -file {{ impl_output }}/impl.dcp write_edif -force -file {{ impl_output }}/viv_impl.edf write_verilog -force -file {{ impl_output }}/viv_impl.v -report_utilization -file {{ impl_output }}/utilization.txt +report_utilization -file {{ impl_output }}/utilization.txt -hierarchical {{#bit}} write_bitstream -force {{ . }} diff --git a/bfasst/tools/ip/loader.py b/bfasst/tools/ip/loader.py index 59fd52247..436336e68 100644 --- a/bfasst/tools/ip/loader.py +++ b/bfasst/tools/ip/loader.py @@ -1,5 +1,7 @@ import json import pathlib + +import yaml from bfasst import config from bfasst.paths import BFASST_UTILS_PATH, COMMON_TOOLS_PATH, ENCRYPTED_IP_PATH from bfasst.tools.tool import Tool @@ -7,12 +9,13 @@ class EncryptedIpLoader(Tool): - def __init__(self, flow, design_path, user_synth_dcp_path, encrypted_ip_yaml_path) -> None: + def __init__(self, flow, design_path, user_synth_dcp_path, encrypted_ip_data) -> None: super().__init__(flow, design_path) self.build_path = self.design_build_path / "loader" self._my_dir_path = pathlib.Path(__file__).parent self.user_synth_dcp_path = user_synth_dcp_path - self.encrypted_ip_yaml_path = encrypted_ip_yaml_path + # self.encrypted_ip_yaml_path = encrypted_ip_yaml_path + self.encrypted_ip_data = encrypted_ip_data self._init_outputs() def create_rule_snippets(self): @@ -35,10 +38,19 @@ def create_build_snippets(self): "user_partial_bitstream": str(self.build_path / "user_partial.bit"), "final": str(self.build_path / "final"), "key_files": str(ENCRYPTED_IP_PATH / "Project" / "key_files"), + "utilization_cells": " ".join( + f"static_top_i/top_0/{instance}" + for ip in self.encrypted_ip_data + for instance in ip["instances"] + ), } vivado_tcl_json = json.dumps(vivado_tcl_dict, indent=4) json_write_if_changed(self.build_path / "vivado.json", vivado_tcl_json) + encrypted_ip_yaml_path = self.build_path / "encrypted_ip.yaml" + with open(encrypted_ip_yaml_path, "w") as f: + yaml.dump(self.encrypted_ip_data, f) + self._append_build_snippets_default( __file__, { @@ -47,7 +59,7 @@ def create_build_snippets(self): "top_dcp": str(self.user_synth_dcp_path), "final": str(self.build_path / "final"), "user_partial_bitstream": str(self.build_path / "user_partial.bit"), - "encrypted_ip_yaml_path": self.encrypted_ip_yaml_path, + "encrypted_ip_yaml_path": encrypted_ip_yaml_path, }, ) diff --git a/bfasst/tools/ip/loader_vivado.tcl.mustache b/bfasst/tools/ip/loader_vivado.tcl.mustache index e48bbddb4..0f9963930 100644 --- a/bfasst/tools/ip/loader_vivado.tcl.mustache +++ b/bfasst/tools/ip/loader_vivado.tcl.mustache @@ -16,6 +16,7 @@ puts [exec date] # Step 4: Write out implemented checkpoints write_checkpoint {{ final }}.dcp -force write_edif {{ final }}.edif -force +report_utilization -file {{ final }}_utilization_report.txt -hierarchical puts "Time starting writing bitstream DTIMING" puts [exec date] diff --git a/bfasst/tools/synth/vivado_synth.py b/bfasst/tools/synth/vivado_synth.py index 45eda4940..eb89464f4 100644 --- a/bfasst/tools/synth/vivado_synth.py +++ b/bfasst/tools/synth/vivado_synth.py @@ -70,6 +70,7 @@ def _init_outputs(self): self.outputs["synth_dcp"] = self.build_path / "synth.dcp" self.outputs["synth_journal"] = self.build_path / "vivado.jou" self.outputs["synth_log"] = self.build_path / "vivado.log" + self.outputs["utilization"] = self.build_path / "utilization.txt" if not self.ooc: self.outputs["io_report"] = self.build_path / "report_io.txt" diff --git a/bfasst/tools/synth/vivado_synth.tcl.mustache b/bfasst/tools/synth/vivado_synth.tcl.mustache index fd6d2ccf2..579c285df 100644 --- a/bfasst/tools/synth/vivado_synth.tcl.mustache +++ b/bfasst/tools/synth/vivado_synth.tcl.mustache @@ -25,6 +25,7 @@ place_ports write_edif -force {{ synth_output }}/viv_synth.edf write_checkpoint -force -file {{ synth_output }}/synth.dcp write_verilog -force -file {{ synth_output }}/viv_synth.v +report_utilization -file {{ synth_output }}/utilization.txt -hierarchical {{#io}} report_io -force -file {{ . }} diff --git a/bfasst/utils/vivado.py b/bfasst/utils/vivado.py new file mode 100644 index 000000000..1c4d92c3f --- /dev/null +++ b/bfasst/utils/vivado.py @@ -0,0 +1,55 @@ +import pathlib +import re + + +def parse_hierarchical_utilization(path): + assert path.is_file() + with open(path) as f: + lines = f.readlines() + + # Find where in the file the utilization data starts + start_line = None + for i, line in enumerate(lines): + if re.match("\d+\. Utilization by Hierarchy", line): + start_line = i + 4 + assert start_line + lines = lines[start_line:] + + # Get the column names, excluding the first two which are the + # instance and module name + columns = [c.strip() for c in lines[0].strip()[1:-1].split("|")[2:]] + + # Skip the empty lines + lines = lines[2:] + + utilization_data = {} + + # Iterate through lines of data + current_path = None + prev_spaces = None + for line in lines: + if line.startswith("+"): + break + cols = line.strip()[1:-1].split("|") + + # Determine the hierarchy level by counting spaces + spaces = len(cols[0]) - len(cols[0].lstrip()) + if current_path is None: + assert prev_spaces is None + current_path = pathlib.Path(cols[0].strip()) + else: + if spaces > prev_spaces: + current_path /= cols[0].strip() + elif spaces == prev_spaces: + current_path = current_path.parent / cols[0].strip() + else: + current_path = current_path.parent.parent / cols[0].strip() + prev_spaces = spaces + + # Save each column of utilization data + instance_data = {} + utilization_data[str(current_path)] = instance_data + for col, val in zip(columns, cols[2:]): + instance_data[col] = int(val.strip()) + + return utilization_data From ff599ccbd2c8dcf51cb8273d09ee68eae75fce9f Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Wed, 13 Dec 2023 09:15:51 -0700 Subject: [PATCH 15/25] add more benchmarks --- bfasst/flows/encrypted_ip.py | 27 +- bfasst/yaml_parser.py | 2 +- .../16x16bit_multiplier_pipelined.v | 0 .../{pid_test => pid}/CLA_fixed.v | 0 designs/encrypted_ip/{pid_test => pid}/PID.v | 0 .../{pid_test => pid}/PID_defines.v | 0 .../encrypted_ip/{pid_test => pid}/booth.v | 0 designs/encrypted_ip/pid/design.yaml | 14 + .../{pid_test => pid}/divider_dshift.v | 0 .../encrypted_ip/{pid_test => pid}/shifter.v | 0 designs/encrypted_ip/{pid_test => pid}/top.v | 0 designs/encrypted_ip/pid_test/design.yaml | 4 - designs/encrypted_ip/uart2spi/clk_ctl.v | 124 ++++++ designs/encrypted_ip/uart2spi/design.yaml | 12 + designs/encrypted_ip/uart2spi/gng.v | 107 +++++ designs/encrypted_ip/uart2spi/gng_coef.v | 318 +++++++++++++++ designs/encrypted_ip/uart2spi/gng_ctg.v | 96 +++++ designs/encrypted_ip/uart2spi/gng_interp.v | 223 ++++++++++ designs/encrypted_ip/uart2spi/gng_lzd.v | 199 +++++++++ .../encrypted_ip/uart2spi/gng_smul_16_18.v | 66 +++ .../uart2spi/gng_smul_16_18_sadd_37.v | 78 ++++ designs/encrypted_ip/uart2spi/registers.v | 276 +++++++++++++ designs/encrypted_ip/uart2spi/spi_cfg.v | 362 +++++++++++++++++ designs/encrypted_ip/uart2spi/spi_core.v | 198 +++++++++ designs/encrypted_ip/uart2spi/spi_ctl.v | 310 ++++++++++++++ designs/encrypted_ip/uart2spi/spi_if.v | 137 +++++++ designs/encrypted_ip/uart2spi/top.v | 82 ++++ designs/encrypted_ip/uart2spi/uart2spi.v | 228 +++++++++++ designs/encrypted_ip/uart2spi/uart_core.v | 190 +++++++++ .../encrypted_ip/uart2spi/uart_msg_handler.v | 384 ++++++++++++++++++ designs/encrypted_ip/uart2spi/uart_rxfsm.v | 207 ++++++++++ designs/encrypted_ip/uart2spi/uart_txfsm.v | 168 ++++++++ requirements.txt | 1 + 33 files changed, 3804 insertions(+), 9 deletions(-) rename designs/encrypted_ip/{pid_test => pid}/16x16bit_multiplier_pipelined.v (100%) rename designs/encrypted_ip/{pid_test => pid}/CLA_fixed.v (100%) rename designs/encrypted_ip/{pid_test => pid}/PID.v (100%) rename designs/encrypted_ip/{pid_test => pid}/PID_defines.v (100%) rename designs/encrypted_ip/{pid_test => pid}/booth.v (100%) create mode 100644 designs/encrypted_ip/pid/design.yaml rename designs/encrypted_ip/{pid_test => pid}/divider_dshift.v (100%) rename designs/encrypted_ip/{pid_test => pid}/shifter.v (100%) rename designs/encrypted_ip/{pid_test => pid}/top.v (100%) delete mode 100644 designs/encrypted_ip/pid_test/design.yaml create mode 100644 designs/encrypted_ip/uart2spi/clk_ctl.v create mode 100644 designs/encrypted_ip/uart2spi/design.yaml create mode 100644 designs/encrypted_ip/uart2spi/gng.v create mode 100644 designs/encrypted_ip/uart2spi/gng_coef.v create mode 100644 designs/encrypted_ip/uart2spi/gng_ctg.v create mode 100644 designs/encrypted_ip/uart2spi/gng_interp.v create mode 100644 designs/encrypted_ip/uart2spi/gng_lzd.v create mode 100644 designs/encrypted_ip/uart2spi/gng_smul_16_18.v create mode 100644 designs/encrypted_ip/uart2spi/gng_smul_16_18_sadd_37.v create mode 100644 designs/encrypted_ip/uart2spi/registers.v create mode 100644 designs/encrypted_ip/uart2spi/spi_cfg.v create mode 100644 designs/encrypted_ip/uart2spi/spi_core.v create mode 100644 designs/encrypted_ip/uart2spi/spi_ctl.v create mode 100644 designs/encrypted_ip/uart2spi/spi_if.v create mode 100644 designs/encrypted_ip/uart2spi/top.v create mode 100644 designs/encrypted_ip/uart2spi/uart2spi.v create mode 100644 designs/encrypted_ip/uart2spi/uart_core.v create mode 100644 designs/encrypted_ip/uart2spi/uart_msg_handler.v create mode 100644 designs/encrypted_ip/uart2spi/uart_rxfsm.v create mode 100644 designs/encrypted_ip/uart2spi/uart_txfsm.v diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py index 381fdc1e8..7b84ba9d0 100644 --- a/bfasst/flows/encrypted_ip.py +++ b/bfasst/flows/encrypted_ip.py @@ -1,6 +1,7 @@ """Flow to create Vivado synthesis and implementation ninja snippets.""" import pathlib import re +import pandas as pd import yaml from bfasst.flows.flow import Flow @@ -73,7 +74,8 @@ def get_top_level_flow_path(self): return pathlib.Path(__file__) def post_execute(self): - out_csv_path = self.design_build_path / "area_results.txt" + print("Running post_execute for EncryptedIP flow") + out_csv_path = self.design_build_path / "area_results.csv" # Get regular synthesis results reg_utilization_file = self.synth_regular.outputs["utilization"] @@ -82,13 +84,30 @@ def post_execute(self): regular_data = parse_hierarchical_utilization(reg_utilization_file) encrypted_data = parse_hierarchical_utilization(encrypted_utilization_file) - instances = ["top_0"] + [ - f"top_0/{definition}" + instances = ["top"] + [ + f"top/{definition}" for ip in self.design_props.encrypted_ip["ip"] for definition in ip["instances"] ] + df = pd.DataFrame( + columns=["Instance", "LUTs-Regular", "FFs-Regular", "LUTs-Encrypted", "FFs-Encrypted"] + ) for instance in instances: - if assert instance in regular_data, f"Instance {instance} not found in regular data" assert instance in encrypted_data, f"Instance {instance} not found in encrypted data" + + row = pd.Series( + { + "Instance": instance, + "LUTs-Regular": regular_data[instance]["Total LUTs"], + "FFs-Regular": regular_data[instance]["FFs"], + "LUTs-Encrypted": encrypted_data[instance]["Total LUTs"], + "FFs-Encrypted": encrypted_data[instance]["FFs"], + } + ) + df = pd.concat( + [df, row.to_frame().T], + ) + + df.to_csv(out_csv_path, index=False) diff --git a/bfasst/yaml_parser.py b/bfasst/yaml_parser.py index f6d701398..cfd68cbec 100644 --- a/bfasst/yaml_parser.py +++ b/bfasst/yaml_parser.py @@ -86,7 +86,7 @@ def _collect_design_paths(self): for dir_item in design_dir_path.iterdir(): item_path = design_dir_path / dir_item if item_path.is_dir(): - self.design_paths.append(dir_item.name) + self.design_paths.append(item_path) def _uniquify_design_paths(self): self.design_paths = list(set(self.design_paths)) diff --git a/designs/encrypted_ip/pid_test/16x16bit_multiplier_pipelined.v b/designs/encrypted_ip/pid/16x16bit_multiplier_pipelined.v similarity index 100% rename from designs/encrypted_ip/pid_test/16x16bit_multiplier_pipelined.v rename to designs/encrypted_ip/pid/16x16bit_multiplier_pipelined.v diff --git a/designs/encrypted_ip/pid_test/CLA_fixed.v b/designs/encrypted_ip/pid/CLA_fixed.v similarity index 100% rename from designs/encrypted_ip/pid_test/CLA_fixed.v rename to designs/encrypted_ip/pid/CLA_fixed.v diff --git a/designs/encrypted_ip/pid_test/PID.v b/designs/encrypted_ip/pid/PID.v similarity index 100% rename from designs/encrypted_ip/pid_test/PID.v rename to designs/encrypted_ip/pid/PID.v diff --git a/designs/encrypted_ip/pid_test/PID_defines.v b/designs/encrypted_ip/pid/PID_defines.v similarity index 100% rename from designs/encrypted_ip/pid_test/PID_defines.v rename to designs/encrypted_ip/pid/PID_defines.v diff --git a/designs/encrypted_ip/pid_test/booth.v b/designs/encrypted_ip/pid/booth.v similarity index 100% rename from designs/encrypted_ip/pid_test/booth.v rename to designs/encrypted_ip/pid/booth.v diff --git a/designs/encrypted_ip/pid/design.yaml b/designs/encrypted_ip/pid/design.yaml new file mode 100644 index 000000000..9a74b9137 --- /dev/null +++ b/designs/encrypted_ip/pid/design.yaml @@ -0,0 +1,14 @@ +top: top + +encrypted_ip: + ip: + - definition: "pid" + instances: + - "pid_0" + - definition: "divider_dshift" + instances: + - "divider_dshift_1" + - "divider_dshift_2" + - "divider_dshift_3" + + user_files: ["top.v"] \ No newline at end of file diff --git a/designs/encrypted_ip/pid_test/divider_dshift.v b/designs/encrypted_ip/pid/divider_dshift.v similarity index 100% rename from designs/encrypted_ip/pid_test/divider_dshift.v rename to designs/encrypted_ip/pid/divider_dshift.v diff --git a/designs/encrypted_ip/pid_test/shifter.v b/designs/encrypted_ip/pid/shifter.v similarity index 100% rename from designs/encrypted_ip/pid_test/shifter.v rename to designs/encrypted_ip/pid/shifter.v diff --git a/designs/encrypted_ip/pid_test/top.v b/designs/encrypted_ip/pid/top.v similarity index 100% rename from designs/encrypted_ip/pid_test/top.v rename to designs/encrypted_ip/pid/top.v diff --git a/designs/encrypted_ip/pid_test/design.yaml b/designs/encrypted_ip/pid_test/design.yaml deleted file mode 100644 index 0f7e762de..000000000 --- a/designs/encrypted_ip/pid_test/design.yaml +++ /dev/null @@ -1,4 +0,0 @@ -top: top - -encrypted_ip: ["pid", "divider_dshift"] -encrypted_ip_user_files: ["top.v"] \ No newline at end of file diff --git a/designs/encrypted_ip/uart2spi/clk_ctl.v b/designs/encrypted_ip/uart2spi/clk_ctl.v new file mode 100644 index 000000000..8a81e8ef3 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/clk_ctl.v @@ -0,0 +1,124 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// ################################################################# +// Module: clk_ctl +// +// Description: Generic clock control logic , clk-out = mclk/(2+clk_div_ratio) +// +// +// ################################################################# + + +module clk_ctl ( + // Outputs + clk_o, + // Inputs + mclk, + reset_n, + clk_div_ratio + ); + +//--------------------------------- +// CLOCK Default Divider value. +// This value will be change from outside +//--------------------------------- +parameter WD = 'h1; + +//--------------------------------------------- +// All the input to this block are declared here +// -------------------------------------------- + input mclk ;// + input reset_n ;// primary reset signal + input [WD:0] clk_div_ratio ;// primary clock divide ratio + // output clock = selected clock / (div_ratio+1) + +//--------------------------------------------- +// All the output to this block are declared here +// -------------------------------------------- + output clk_o ; // clock out + + + +//------------------------------------ +// Clock Divide func is done here +//------------------------------------ +reg [WD-1:0] high_count ; // high level counter +reg [WD-1:0] low_count ; // low level counter +reg mclk_div ; // divided clock + + +assign clk_o = mclk_div; + +always @ (posedge mclk or negedge reset_n) +begin // { + if(reset_n == 1'b0) + begin + high_count <= 'h0; + low_count <= 'h0; + mclk_div <= 'b0; + end + else + begin + if(high_count != 0) + begin // { + high_count <= high_count - 1; + mclk_div <= 1'b1; + end // } + else if(low_count != 0) + begin // { + low_count <= low_count - 1; + mclk_div <= 1'b0; + end // } + else + begin // { + high_count <= clk_div_ratio[WD:1] + clk_div_ratio[0]; + low_count <= clk_div_ratio[WD:1] + 1; + mclk_div <= ~mclk_div; + end // } + end // } +end // } + + +endmodule + diff --git a/designs/encrypted_ip/uart2spi/design.yaml b/designs/encrypted_ip/uart2spi/design.yaml new file mode 100644 index 000000000..4153cd211 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/design.yaml @@ -0,0 +1,12 @@ +top: top + +encrypted_ip: + ip: + - definition: "gng" + instances: + - "gng_0" + - definition: "uart2spi" + instances: + - "uart2spi_0" + + user_files: ["top.v"] \ No newline at end of file diff --git a/designs/encrypted_ip/uart2spi/gng.v b/designs/encrypted_ip/uart2spi/gng.v new file mode 100644 index 000000000..04701aa65 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/gng.v @@ -0,0 +1,107 @@ +//------------------------------------------------------------------------------ +// +// gng.v +// +// This file is part of the Gaussian Noise Generator IP Core +// +// Description +// Top module of Gaussian noise generator. +// +//------------------------------------------------------------------------------ +// +// Copyright (C) 2014, Guangxi Liu +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as published by +// the Free Software Foundation; either version 2.1 of the License, +// or (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, download it from +// http://www.opencores.org/lgpl.shtml +// +//------------------------------------------------------------------------------ + + +`timescale 1 ns / 1 ps + + +module gng +( + input [63:0] INIT_Z1, + input [63:0] INIT_Z2, + input [63:0] INIT_Z3, + // System signals + input clk, // system clock + input rstn, // system synchronous reset, active low + + // Data interface + input ce, // clock enable + output valid_out, // output data valid + output [15:0] data_out // output data, s<16,11> +); + +// Local variables +wire valid_out_ctg; +wire [63:0] data_out_ctg; + +wire valid_out_placeholder; + +// Instances +gng_ctg u_gng_ctg ( + .INIT_Z1(INIT_Z1), + .INIT_Z2(INIT_Z2), + .INIT_Z3(INIT_Z3), + .clk(clk), + .rstn(rstn), + .ce(ce), + .valid_out(valid_out_ctg), + .data_out(data_out_ctg) +); + +gng_interp u_gng_interp ( + .clk(clk), + .rstn(rstn), + .valid_in(valid_out_ctg), + .data_in(data_out_ctg), + .valid_out(valid_out_placeholder), + .data_out(data_out) +); + +wire frm_error, par_error, baud_clk_16x; +wire txd, sck, so; +wire [3:0] cs_n; + +uart2spi uart2spi_0 ( + rstn, + clk, + INIT_Z1[0], + INIT_Z1[1], + INIT_Z1[2], + INIT_Z1[4:3], + INIT_Z1[16:5], + frm_error, + par_error, + baud_clk_16x, + INIT_Z1[16], + txd, + sck, + so, + INIT_Z1[17], + cs_n +); + +assign valid_out = valid_out_placeholder ^ frm_error ^ par_error ^ baud_clk_16x ^ txd ^ sck ^ so ^ (^cs_n); + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/gng_coef.v b/designs/encrypted_ip/uart2spi/gng_coef.v new file mode 100644 index 000000000..8a5b844e8 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/gng_coef.v @@ -0,0 +1,318 @@ +//------------------------------------------------------------------------------ +// +// gng_coef.v +// +// This file is part of the Gaussian Noise Generator IP Core +// +// Description +// Coefficients ROM table for polynomial interpolation. +// +//------------------------------------------------------------------------------ +// +// Copyright (C) 2014, Guangxi Liu +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as published by +// the Free Software Foundation; either version 2.1 of the License, +// or (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, download it from +// http://www.opencores.org/lgpl.shtml +// +//------------------------------------------------------------------------------ + + +`timescale 1 ns / 1 ps + + +module gng_coef ( + // System signals + input clk, // system clock + + // Data interface + input [7:0] addr, // read address + output reg [17:0] c0, // coefficient c0, u<18,14> + output reg [17:0] c1, // coefficient c1, s<18,19> + output reg [16:0] c2 // coefficient c2, u<17,23> +); + +// Local variables +reg [52:0] d; // {c0, c1, c2} + + +// Table +always @ (*) begin + case (addr) + 8'd0 : d = 53'b000010101100101001_100110111110001110_10100011110000000; + 8'd1 : d = 53'b000001111101000111_101001011111011001_01011111011110011; + 8'd2 : d = 53'b000001010001100100_101010111101101110_00110010101000000; + 8'd3 : d = 53'b000000101000010001_101011101111111001_00001111111010011; + 8'd4 : d = 53'b000100100110011110_101100101100100010_10101101110011100; + 8'd5 : d = 53'b000100000010100011_101111010111110111_01110101000001100; + 8'd6 : d = 53'b000011100011000111_110001001011101011_01010011011010011; + 8'd7 : d = 53'b000011000110110001_110010011110011100_00111101101011001; + 8'd8 : d = 53'b000110001000101110_101111110110101010_10100011001000110; + 8'd9 : d = 53'b000101101010111101_110010010111100001_01101111010111011; + 8'd10 : d = 53'b000101010001011010_110100000101110001_01010000111111000; + 8'd11 : d = 53'b000100111010110110_110101010110001001_00111101100100011; + 8'd12 : d = 53'b000111011100110110_110001111001100101_10010111001100011; + 8'd13 : d = 53'b000111000010111111_110100001110101001_01100111010010101; + 8'd14 : d = 53'b000110101101000010_110101110100111010_01001011010000101; + 8'd15 : d = 53'b000110011001110111_110110111111100110_00111001011001010; + 8'd16 : d = 53'b001000100111011000_110011010110100101_10001100100110110; + 8'd17 : d = 53'b001000010000010000_110101100001001100_01011111111010010; + 8'd18 : d = 53'b000111111100110010_110111000000001000_01000101110011111; + 8'd19 : d = 53'b000111101011110111_111000000101011011_00110101001101001; + 8'd20 : d = 53'b001001101010111000_110100011100101111_10000011100100011; + 8'd21 : d = 53'b001001010101110100_110110011110011100_01011001100101001; + 8'd22 : d = 53'b001001000100001010_110111110111000110_01000001000110100; + 8'd23 : d = 53'b001000110100111000_111000110111101101_00110001100011100; + 8'd24 : d = 53'b001010101000111110_110101010011111110_01111011110111110; + 8'd25 : d = 53'b001010010101100000_110111001110000100_01010100001100011; + 8'd26 : d = 53'b001010000101010000_111000100001011001_00111101000110010; + 8'd27 : d = 53'b001001110111001111_111001011110000001_00101110011100100; + 8'd28 : d = 53'b001011100010101101_110110000000110101_01110101010001000; + 8'd29 : d = 53'b001011010000100011_110111110100011001_01001111100101010; + 8'd30 : d = 53'b001011000001011011_111001000011001010_00111001101011010; + 8'd31 : d = 53'b001010110100011010_111001111100011001_00101011110010110; + 8'd32 : d = 53'b001100011000111001_110110100110001001_01101111100010101; + 8'd33 : d = 53'b001100000111110011_111000010100000101_01001011100110010; + 8'd34 : d = 53'b001011111001100110_111001011110111001_00110110101110100; + 8'd35 : d = 53'b001011101101011011_111010010101001100_00101001100000110; + 8'd36 : d = 53'b001101001100000100_110111000101110100_01101010100010001; + 8'd37 : d = 53'b001100111011111001_111000101110110010_01001000000111110; + 8'd38 : d = 53'b001100101110011110_111001110110001010_00110100001010001; + 8'd39 : d = 53'b001100100010111110_111010101001111011_00100111100001111; + 8'd40 : d = 53'b001101111100101100_110111100001000101_01100110000110111; + 8'd41 : d = 53'b001101101101010011_111001000101101101_01000101000011110; + 8'd42 : d = 53'b001101100000100011_111010001010000011_00110001111001101; + 8'd43 : d = 53'b001101010101101000_111010111011100011_00100101110010101; + 8'd44 : d = 53'b001110101011000101_110111111000111001_01100010001010110; + 8'd45 : d = 53'b001110011100011000_111001011001101000_01000010010101101; + 8'd46 : d = 53'b001110010000001101_111010011011010001_00101111111001101; + 8'd47 : d = 53'b001110000101110011_111011001010110011_00100100010000001; + 8'd48 : d = 53'b001111010111100001_111000001101111010_01011110101000100; + 8'd49 : d = 53'b001111001001011011_111001101011001001_00111111111001110; + 8'd50 : d = 53'b001110111101110000_111010101010011000_00101110000111001; + 8'd51 : d = 53'b001110110011110011_111011011000001000_00100010111000010; + 8'd52 : d = 53'b010000000010001111_111000100000100111_01011011011100010; + 8'd53 : d = 53'b001111110100101011_111001111010101101_00111101101101001; + 8'd54 : d = 53'b001111101001011101_111010110111110001_00101100100000001; + 8'd55 : d = 53'b001111011111111001_111011100011111010_00100001101001010; + 8'd56 : d = 53'b010000101011011010_111000110001011010_01011000100010101; + 8'd57 : d = 53'b010000011110010100_111010001000101001_00111011101101101; + 8'd58 : d = 53'b010000010011100000_111011000011101110_00101011000010110; + 8'd59 : d = 53'b010000001010010010_111011101110011011_00100000100001110; + 8'd60 : d = 53'b010001010011001011_111001000000100110_01010101111001000; + 8'd61 : d = 53'b010001000110100001_111010010101001110_00111001111001011; + 8'd62 : d = 53'b010000111100000101_111011001110100000_00101001101101110; + 8'd63 : d = 53'b010000110011001011_111011110111111001_00011111100000110; + 8'd64 : d = 53'b010001111001101011_111001001110011010_01010011011101011; + 8'd65 : d = 53'b010001101101011010_111010100000101000_00111000001110110; + 8'd66 : d = 53'b010001100011010011_111011011000010001_00101000011111111; + 8'd67 : d = 53'b010001011010101100_111100000000011100_00011110100101010; + 8'd68 : d = 53'b010010011111000010_111001011011000010_01010001001101111; + 8'd69 : d = 53'b010010010011001000_111010101011000011_00110110101100101; + 8'd70 : d = 53'b010010001001010100_111011100001001011_00100111011000011; + 8'd71 : d = 53'b010010000000111110_111100001000001111_00011101101110101; + 8'd72 : d = 53'b010011000011010100_111001100110101010_01001111001001001; + 8'd73 : d = 53'b010010110111110000_111010110100101000_00110101010001111; + 8'd74 : d = 53'b010010101110001110_111011101001010101_00100110010110010; + 8'd75 : d = 53'b010010100110000111_111100001111011000_00011100111100001; + 8'd76 : d = 53'b010011100110101001_111001110001011000_01001101001101110; + 8'd77 : d = 53'b010011011011011000_111010111101011100_00110011111101110; + 8'd78 : d = 53'b010011010010000110_111011110000110110_00100101011000111; + 8'd79 : d = 53'b010011001010001101_111100010101111100_00011100001101100; + 8'd80 : d = 53'b010100001001000100_111001111011010100_01001011011010110; + 8'd81 : d = 53'b010011111110000101_111011000101100111_00110010101111010; + 8'd82 : d = 53'b010011110101000010_111011110111110011_00100100011111111; + 8'd83 : d = 53'b010011101101010110_111100011100000001_00011011100010000; + 8'd84 : d = 53'b010100101010101001_111010000100100011_01001001101111010; + 8'd85 : d = 53'b010100011111111011_111011001101001100_00110001100110000; + 8'd86 : d = 53'b010100010111000110_111011111110010000_00100011101010101; + 8'd87 : d = 53'b010100001111100110_111100100001101001_00011010111001100; + 8'd88 : d = 53'b010101001011011100_111010001101001011_01001000001010100; + 8'd89 : d = 53'b010101000000111110_111011010100010000_00110000100001100; + 8'd90 : d = 53'b010100111000010110_111100000100010001_00100010111000110; + 8'd91 : d = 53'b010100110001000001_111100100110111000_00011010010011100; + 8'd92 : d = 53'b010101101011100000_111010010101001111_01000110101011110; + 8'd93 : d = 53'b010101100001010001_111011011010111000_00101111100001000; + 8'd94 : d = 53'b010101011000110110_111100001001111000_00100010001010000; + 8'd95 : d = 53'b010101010001101011_111100101011110001_00011001110000000; + 8'd96 : d = 53'b010110001010111001_111010011100110100_01000101010010101; + 8'd97 : d = 53'b010110000000110111_111011100001000100_00101110100100011; + 8'd98 : d = 53'b010101111000101000_111100001111001001_00100001011110000; + 8'd99 : d = 53'b010101110001100111_111100110000010110_00011001001110100; + 8'd100: d = 53'b010110101001101001_111010100011111100_01000011111110011; + 8'd101: d = 53'b010110011111110100_111011100110111001_00101101101011001; + 8'd102: d = 53'b010110010111101111_111100010100000101_00100000110100100; + 8'd103: d = 53'b010110010000111000_111100110100101001_00011000101111000; + 8'd104: d = 53'b010111000111110010_111010101010101010_01000010101110101; + 8'd105: d = 53'b010110111110001010_111011101100011001_00101100110101000; + 8'd106: d = 53'b010110110110001111_111100011000101111_00100000001101010; + 8'd107: d = 53'b010110101111100000_111100111000101100_00011000010001010; + 8'd108: d = 53'b010111100101010111_111010110001000000_01000001100011001; + 8'd109: d = 53'b010111011011111010_111011110001100101_00101100000001110; + 8'd110: d = 53'b010111010100001000_111100011101001000_00011111101000001; + 8'd111: d = 53'b010111001101100010_111100111100100000_00010111110101000; + 8'd112: d = 53'b011000000010011001_111010110111000001_01000000011011011; + 8'd113: d = 53'b010111111001000111_111011110110011111_00101011010001001; + 8'd114: d = 53'b010111110001011110_111100100001010011_00011111000100111; + 8'd115: d = 53'b010111101011000000_111101000000000111_00010111011010010; + 8'd116: d = 53'b011000011110111010_111010111100101110_00111111010111001; + 8'd117: d = 53'b011000010101110010_111011111011001001_00101010100010111; + 8'd118: d = 53'b011000001110010011_111100100101001111_00011110100011011; + 8'd119: d = 53'b011000000111111011_111101000011100010_00010111000000111; + 8'd120: d = 53'b011000111010111100_111011000010001010_00111110010110001; + 8'd121: d = 53'b011000110001111110_111011111111100100_00101001110110111; + 8'd122: d = 53'b011000101010100111_111100101000111110_00011110000011100; + 8'd123: d = 53'b011000100100010110_111101000110110010_00010110101000110; + 8'd124: d = 53'b011001010110100001_111011000111010100_00111101011000001; + 8'd125: d = 53'b011001001101101100_111100000011110001_00101001001100110; + 8'd126: d = 53'b011001000110011100_111100101100100010_00011101100101001; + 8'd127: d = 53'b011001000000010011_111101001001111000_00010110010001110; + 8'd128: d = 53'b011001110001101001_111011001100001111_00111100011100111; + 8'd129: d = 53'b011001101000111101_111100000111110010_00101000100100101; + 8'd130: d = 53'b011001100001110101_111100101111111011_00011101001000001; + 8'd131: d = 53'b011001011011110010_111101001100110100_00010101111011110; + 8'd132: d = 53'b011010001100010110_111011010000111100_00111011100100001; + 8'd133: d = 53'b011010000011110011_111100001011100111_00100111111110010; + 8'd134: d = 53'b011001111100110010_111100110011001001_00011100101100011; + 8'd135: d = 53'b011001110110110101_111101001111100111_00010101100110101; + 8'd136: d = 53'b011010100110101010_111011010101011011_00111010101101111; + 8'd137: d = 53'b011010011110001111_111100001111010001_00100111011001101; + 8'd138: d = 53'b011010010111010101_111100110110001111_00011100010001111; + 8'd139: d = 53'b011010010001011101_111101010010010010_00010101010010101; + 8'd140: d = 53'b011011000000100101_111011011001101110_00111001111001110; + 8'd141: d = 53'b011010111000010010_111100010010110001_00100110110110011; + 8'd142: d = 53'b011010110001011110_111100111001001100_00011011111000011; + 8'd143: d = 53'b011010101011101100_111101010100110110_00010100111111010; + 8'd144: d = 53'b011011011010001001_111011011101110110_00111001000111110; + 8'd145: d = 53'b011011010001111101_111100010110000111_00100110010100100; + 8'd146: d = 53'b011011001011001111_111100111100000001_00011011100000000; + 8'd147: d = 53'b011011000101100010_111101010111010011_00010100101100111; + 8'd148: d = 53'b011011110011010110_111011100001110011_00111000010111101; + 8'd149: d = 53'b011011101011010001_111100011001010101_00100101110100000; + 8'd150: d = 53'b011011100100101001_111100111110101111_00011011001000100; + 8'd151: d = 53'b011011011111000010_111101011001101010_00010100011011000; + 8'd152: d = 53'b011100001100001101_111011100101100111_00110111101001100; + 8'd153: d = 53'b011100000100001111_111100011100011011_00100101010100110; + 8'd154: d = 53'b011011111101101101_111101000001010110_00011010110001111; + 8'd155: d = 53'b011011111000001010_111101011011111010_00010100001010000; + 8'd156: d = 53'b011100100100110000_111011101001010001_00110110111100111; + 8'd157: d = 53'b011100011100111000_111100011111011001_00100100110110110; + 8'd158: d = 53'b011100010110011100_111101000011110110_00011010011100010; + 8'd159: d = 53'b011100010000111110_111101011110000101_00010011111001101; + 8'd160: d = 53'b011100111100111110_111011101100110010_00110110010010000; + 8'd161: d = 53'b011100110101001101_111100100010001111_00100100011001110; + 8'd162: d = 53'b011100101110110110_111101000110010000_00011010000111010; + 8'd163: d = 53'b011100101001011100_111101100000001010_00010011101001110; + 8'd164: d = 53'b011101010100111001_111011110000001011_00110101101000101; + 8'd165: d = 53'b011101001101001110_111100100101000000_00100011111101110; + 8'd166: d = 53'b011101000110111100_111101001000100101_00011001110011001; + 8'd167: d = 53'b011101000001100111_111101100010001010_00010011011010100; + 8'd168: d = 53'b011101101100100001_111011110011011100_00110101000000101; + 8'd169: d = 53'b011101100100111101_111100100111101001_00100011100010111; + 8'd170: d = 53'b011101011110101111_111101001010110100_00011001011111101; + 8'd171: d = 53'b011101011001011110_111101100100000110_00010011001011110; + 8'd172: d = 53'b011110000011111000_111011110110100110_00110100011010000; + 8'd173: d = 53'b011101111100011001_111100101010001101_00100011001000110; + 8'd174: d = 53'b011101110110010000_111101001100111110_00011001001100111; + 8'd175: d = 53'b011101110001000011_111101100101111110_00010010111101101; + 8'd176: d = 53'b011110011010111101_111011111001101001_00110011110100110; + 8'd177: d = 53'b011110010011100100_111100101100101011_00100010101111100; + 8'd178: d = 53'b011110001101011111_111101001111000011_00011000111010110; + 8'd179: d = 53'b011110001000010110_111101100111110001_00010010101111111; + 8'd180: d = 53'b011110110001110001_111011111100100101_00110011010000101; + 8'd181: d = 53'b011110101010011101_111100101111000100_00100010010111001; + 8'd182: d = 53'b011110100100011101_111101010001000100_00011000101001001; + 8'd183: d = 53'b011110011111011000_111101101001100000_00010010100010100; + 8'd184: d = 53'b011111001000010110_111011111111011011_00110010101101101; + 8'd185: d = 53'b011111000001000111_111100110001011000_00100001111111101; + 8'd186: d = 53'b011110111011001011_111101010011000000_00011000011000001; + 8'd187: d = 53'b011110110110001001_111101101011001100_00010010010101110; + 8'd188: d = 53'b011111011110101010_111100000010001100_00110010001011110; + 8'd189: d = 53'b011111010111100000_111100110011100111_00100001101000110; + 8'd190: d = 53'b011111010001101001_111101010100111001_00011000000111101; + 8'd191: d = 53'b011111001100101010_111101101100110100_00010010001001010; + 8'd192: d = 53'b011111110100101111_111100000100110111_00110001101011000; + 8'd193: d = 53'b011111101101101010_111100110101110010_00100001010010101; + 8'd194: d = 53'b011111100111110111_111101010110101101_00010111110111110; + 8'd195: d = 53'b011111100010111100_111101101110011001_00010001111101010; + 8'd196: d = 53'b100000001010100110_111100000111011101_00110001001011010; + 8'd197: d = 53'b100000000011100101_111100110111111000_00100000111101010; + 8'd198: d = 53'b011111111101110110_111101011000011110_00010111101000010; + 8'd199: d = 53'b011111111000111110_111101101111111010_00010001110001100; + 8'd200: d = 53'b100000100000001110_111100001001111101_00110000101100101; + 8'd201: d = 53'b100000011001010010_111100111001111010_00100000101000100; + 8'd202: d = 53'b100000010011100110_111101011010001100_00010111011001011; + 8'd203: d = 53'b100000001110110010_111101110001011001_00010001100110010; + 8'd204: d = 53'b100000110101101001_111100001100011001_00110000001111001; + 8'd205: d = 53'b100000101110110001_111100111011111000_00100000010100101; + 8'd206: d = 53'b100000101001001001_111101011011110110_00010111001011000; + 8'd207: d = 53'b100000100100011000_111101110010110101_00010001011011011; + 8'd208: d = 53'b100001001010110110_111100001110110000_00101111110011010; + 8'd209: d = 53'b100001000100000010_111100111101110011_00100000000001101; + 8'd210: d = 53'b100000111110011110_111101011101011101_00010110111101010; + 8'd211: d = 53'b100000111001101111_111101110100001110_00010001010001000; + 8'd212: d = 53'b100001011111110110_111100010001000010_00101111011001100; + 8'd213: d = 53'b100001011001000111_111100111111101001_00011111101111111; + 8'd214: d = 53'b100001010011100101_111101011111000001_00010110110000010; + 8'd215: d = 53'b100001001110111010_111101110101100100_00010001000111001; + 8'd216: d = 53'b100001110100101001_111100010011001110_00101111000011000; + 8'd217: d = 53'b100001101101111110_111101000001011100_00011111100000001; + 8'd218: d = 53'b100001101000100000_111101100000100010_00010110100100101; + 8'd219: d = 53'b100001100011110111_111101110110111000_00010000111110001; + 8'd220: d = 53'b100010001001010000_111100010101010100_00101110110010010; + 8'd221: d = 53'b100010000010101001_111101000011001010_00011111010011101; + 8'd222: d = 53'b100001111101001110_111101100001111111_00010110011011000; + 8'd223: d = 53'b100001111000101000_111101111000001001_00010000110110100; + 8'd224: d = 53'b100010011101101011_111100010111010010_00101110101100100; + 8'd225: d = 53'b100010010111000111_111101000100110010_00011111001101001; + 8'd226: d = 53'b100010010001110000_111101100011011000_00010110010101000; + 8'd227: d = 53'b100010001101001101_111101111001010110_00010000110001010; + 8'd228: d = 53'b100010110001111010_111100011001000101_00101110111011101; + 8'd229: d = 53'b100010101011011010_111101000110010011_00011111010010001; + 8'd230: d = 53'b100010100110000110_111101100100101100_00010110010110000; + 8'd231: d = 53'b100010100001100101_111101111010100000_00010000110000101; + 8'd232: d = 53'b100011000101111110_111100011010100111_00101111110100001; + 8'd233: d = 53'b100010111111100010_111101000111101011_00011111101101110; + 8'd234: d = 53'b100010111010010000_111101100101111001_00010110100100111; + 8'd235: d = 53'b100010110101110010_111101111011100101_00010000111001000; + 8'd236: d = 53'b100011011001110111_111100101000100000_00000000000000000; + 8'd237: d = 53'b100011010011011110_111101010001001010_00000000000000000; + 8'd238: d = 53'b100011001110010000_111101101100110110_00000000000000000; + 8'd239: d = 53'b100011001001110100_111110000000111011_00000000000000000; + 8'd240: d = 53'b100011101101100101_000000000000000000_00000000000000000; + 8'd241: d = 53'b100011100111010000_000000000000000000_00000000000000000; + 8'd242: d = 53'b100011100010000100_000000000000000000_00000000000000000; + 8'd243: d = 53'b100011011101101011_000000000000000000_00000000000000000; + 8'd244: d = 53'b100100100111110000_000000000000000000_00000000000000000; + 8'd245: d = 53'b100100010100100001_000000000000000000_00000000000000000; + 8'd246: d = 53'b100100000001001000_000000000000000000_00000000000000000; + 8'd247: d = 53'b100011110101101101_000000000000000000_00000000000000000; + default: d = 53'd0; + endcase +end + + +// Output data +always @ (posedge clk) begin + c0 <= d[52:35]; + c1 <= d[34:17]; + c2 <= d[16:0]; +end + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/gng_ctg.v b/designs/encrypted_ip/uart2spi/gng_ctg.v new file mode 100644 index 000000000..1ff61ff0a --- /dev/null +++ b/designs/encrypted_ip/uart2spi/gng_ctg.v @@ -0,0 +1,96 @@ +//------------------------------------------------------------------------------ +// +// gng_ctg.v +// +// This file is part of the Gaussian Noise Generator IP Core +// +// Description +// Maximally equidistributed combined Tausworthe generator with +// (k1,k2,k3) = (63,58,55); (q1,q2,q3) = (5,19,24); (s1,s2,s3) = (24,13,7). +// Period is approximately 2^176. +// +//------------------------------------------------------------------------------ +// +// Copyright (C) 2014, Guangxi Liu +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as published by +// the Free Software Foundation; either version 2.1 of the License, +// or (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, download it from +// http://www.opencores.org/lgpl.shtml +// +//------------------------------------------------------------------------------ + + +`timescale 1 ns / 1 ps + + +module gng_ctg +( + input [63:0] INIT_Z1, + input [63:0] INIT_Z2, + input [63:0] INIT_Z3, + // System signals + input clk, // system clock + input rstn, // system synchronous reset, active low + + // Data interface + input ce, // clock enable + output reg valid_out, // output data valid + output reg [63:0] data_out // output data +); + +// Local variables +reg [63:0] z1, z2, z3; +wire [63:0] z1_next, z2_next, z3_next; + + +// Update state +assign z1_next = {z1[39:1], z1[58:34] ^ z1[63:39]}; +assign z2_next = {z2[50:6], z2[44:26] ^ z2[63:45]}; +assign z3_next = {z3[56:9], z3[39:24] ^ z3[63:48]}; + +always @ (posedge clk) begin + if (!rstn) begin + z1 <= INIT_Z1; + z2 <= INIT_Z2; + z3 <= INIT_Z3; + end + else if (ce) begin + z1 <= z1_next; + z2 <= z2_next; + z3 <= z3_next; + end +end + + +// Output data +always @ (posedge clk) begin + if (!rstn) + valid_out <= 1'b0; + else + valid_out <= ce; +end + +always @ (posedge clk) begin + if (!rstn) + data_out <= 64'd0; + else + data_out <= z1_next ^ z2_next ^ z3_next; +end + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/gng_interp.v b/designs/encrypted_ip/uart2spi/gng_interp.v new file mode 100644 index 000000000..4405c5be3 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/gng_interp.v @@ -0,0 +1,223 @@ +//------------------------------------------------------------------------------ +// +// gng_interp.v +// +// This file is part of the Gaussian Noise Generator IP Core +// +// Description +// Polynomial interpolation. +// +//------------------------------------------------------------------------------ +// +// Copyright (C) 2014, Guangxi Liu +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as published by +// the Free Software Foundation; either version 2.1 of the License, +// or (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, download it from +// http://www.opencores.org/lgpl.shtml +// +//------------------------------------------------------------------------------ + + +`timescale 1 ns / 1 ps + + +module gng_interp ( + // System signals + input clk, // system clock + input rstn, // system synchronous reset, active low + + // Data interface + input valid_in, // input data valid + input [63:0] data_in, // input data + output reg valid_out, // output data valid + output reg [15:0] data_out // output data, s<16,11> +); + +// Local variables +wire [5:0] num_lzd; +reg [5:0] num_lzd_r; +reg [14:0] mask; +reg [1:0] offset; +wire [7:0] addr; +wire [17:0] c0; // u<18,14> +wire [17:0] c1; // s<18,19> +wire [16:0] c2; // u<17,23> +reg [14:0] x; // u<15,15> +reg [14:0] x_r1, x_r2, x_r3, x_r4; // u<15,15> +reg [17:0] c1_r1; // s<18,19> +wire [37:0] sum1; // s<38,38> +wire [17:0] sum1_new; // s<18,18> +wire [33:0] mul1; // s<34,33> +wire signed [13:0] mul1_new; // s<14,14> +reg [17:0] c0_r1, c0_r2, c0_r3, c0_r4, c0_r5; // u<18,14> +reg signed [18:0] sum2; // s<19,14> +reg [14:0] sum2_rnd; // u<15,11> +reg [8:0] sign_r; +reg [8:0] valid_in_r; + + +// Leading zero detector +gng_lzd u_gng_lzd ( + .data_in(data_in[63:3]), + .data_out(num_lzd) +); + +always @ (posedge clk) begin + if (!rstn) + num_lzd_r <= 6'd0; + else + num_lzd_r <= num_lzd; +end + + +// Get mask for value x +always @ (posedge clk) begin + if (!rstn) + mask <= 15'b111111111111111; + else begin + case (num_lzd_r) + 6'd61: mask <= 15'b111111111111111; + 6'd60: mask <= 15'b011111111111111; + 6'd59: mask <= 15'b101111111111111; + 6'd58: mask <= 15'b110111111111111; + 6'd57: mask <= 15'b111011111111111; + 6'd56: mask <= 15'b111101111111111; + 6'd55: mask <= 15'b111110111111111; + 6'd54: mask <= 15'b111111011111111; + 6'd53: mask <= 15'b111111101111111; + 6'd52: mask <= 15'b111111110111111; + 6'd51: mask <= 15'b111111111011111; + 6'd50: mask <= 15'b111111111101111; + 6'd49: mask <= 15'b111111111110111; + 6'd48: mask <= 15'b111111111111011; + 6'd47: mask <= 15'b111111111111101; + 6'd46: mask <= 15'b111111111111110; + default: mask <= 15'b111111111111111; + endcase + end +end + + +// Generate table address and coefficients +always @ (posedge clk) begin + if (!rstn) + offset <= 2'd0; + else + offset <= {data_in[1], data_in[2]}; +end + +assign addr = {num_lzd_r, offset}; + +gng_coef u_gng_coef ( + .clk(clk), + .addr(addr), + .c0(c0), + .c1(c1), + .c2(c2) +); + + +// Data delay +always @ (posedge clk) begin + if (!rstn) + x <= 15'd0; + else + x <= {data_in[3], data_in[4], data_in[5], data_in[6], data_in[7], + data_in[8], data_in[9], data_in[10], data_in[11], data_in[12], + data_in[13], data_in[14], data_in[15], data_in[16], data_in[17]}; +end + +always @ (posedge clk) begin + x_r1 <= x & mask; + x_r2 <= x_r1; + x_r3 <= x_r2; + x_r4 <= x_r3; +end + +always @ (posedge clk) begin + c1_r1 <= c1; +end + +always @ (posedge clk) begin + c0_r1 <= c0; + c0_r2 <= c0_r1; + c0_r3 <= c0_r2; + c0_r4 <= c0_r3; + c0_r5 <= c0_r4; +end + +always @ (posedge clk) begin + sign_r <= {sign_r[7:0], data_in[0]}; +end + +always @ (posedge clk) begin + if (!rstn) + valid_in_r <= 9'd0; + else + valid_in_r <= {valid_in_r[7:0], valid_in}; +end + + +// Polynomial interpolation of order 2 +gng_smul_16_18_sadd_37 u_gng_smul_16_18_sadd_37 ( + .clk(clk), + .a({1'b0, x_r1}), + .b({1'b0, c2}), + .c({c1_r1, 19'd0}), + .p(sum1) +); + +assign sum1_new = sum1[37:20]; + +gng_smul_16_18 u_gng_smul_16_18 ( + .clk(clk), + .a({1'b0, x_r4}), + .b(sum1_new), + .p(mul1) +); + +assign mul1_new = mul1[32:19]; + +always @ (posedge clk) begin + sum2 <= $signed({1'b0, c0_r5}) + mul1_new; +end + +always @ (posedge clk) begin + sum2_rnd <= sum2[17:3] + sum2[2]; +end + + +// Output data +always @ (posedge clk) begin + if (!rstn) + valid_out <= 1'b0; + else + valid_out <= valid_in_r[8]; +end + +always @ (posedge clk) begin + if (!rstn) + data_out <= 16'd0; + else if (sign_r[8]) + data_out <= {1'b1, ~sum2_rnd} + 1'b1; + else + data_out <= {1'b0, sum2_rnd}; +end + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/gng_lzd.v b/designs/encrypted_ip/uart2spi/gng_lzd.v new file mode 100644 index 000000000..01014f4e9 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/gng_lzd.v @@ -0,0 +1,199 @@ +//------------------------------------------------------------------------------ +// +// gng_lzd.v +// +// This file is part of the Gaussian Noise Generator IP Core +// +// Description +// Leading zero detector of 61-bit number. +// +//------------------------------------------------------------------------------ +// +// Copyright (C) 2014, Guangxi Liu +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as published by +// the Free Software Foundation; either version 2.1 of the License, +// or (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, download it from +// http://www.opencores.org/lgpl.shtml +// +//------------------------------------------------------------------------------ + + +`timescale 1 ns / 1 ps + + +module gng_lzd ( + // Data interface + input [60:0] data_in, // input data + output [5:0] data_out // output number of leading zeros +); + +// Local variables +wire [63:0] d; +wire p1 [31:0]; +wire [31:0] v1; +wire [1:0] p2 [15:0]; +wire [15:0] v2; +wire [2:0] p3 [7:0]; +wire [7:0] v3; +wire [3:0] p4 [3:0]; +wire [3:0] v4; +wire [4:0] p5 [1:0]; +wire [1:0] v5; +wire [5:0] p6; + + +// Parallel structure +assign d = {data_in, 3'b111}; // fill last 3 bits with '1' + +assign p1[0 ] = ~d[1 ]; +assign p1[1 ] = ~d[3 ]; +assign p1[2 ] = ~d[5 ]; +assign p1[3 ] = ~d[7 ]; +assign p1[4 ] = ~d[9 ]; +assign p1[5 ] = ~d[11]; +assign p1[6 ] = ~d[13]; +assign p1[7 ] = ~d[15]; +assign p1[8 ] = ~d[17]; +assign p1[9 ] = ~d[19]; +assign p1[10] = ~d[21]; +assign p1[11] = ~d[23]; +assign p1[12] = ~d[25]; +assign p1[13] = ~d[27]; +assign p1[14] = ~d[29]; +assign p1[15] = ~d[31]; +assign p1[16] = ~d[33]; +assign p1[17] = ~d[35]; +assign p1[18] = ~d[37]; +assign p1[19] = ~d[39]; +assign p1[20] = ~d[41]; +assign p1[21] = ~d[43]; +assign p1[22] = ~d[45]; +assign p1[23] = ~d[47]; +assign p1[24] = ~d[49]; +assign p1[25] = ~d[51]; +assign p1[26] = ~d[53]; +assign p1[27] = ~d[55]; +assign p1[28] = ~d[57]; +assign p1[29] = ~d[59]; +assign p1[30] = ~d[61]; +assign p1[31] = ~d[63]; +assign v1[0 ] = d[0 ] | d[1 ]; +assign v1[1 ] = d[2 ] | d[3 ]; +assign v1[2 ] = d[4 ] | d[5 ]; +assign v1[3 ] = d[6 ] | d[7 ]; +assign v1[4 ] = d[8 ] | d[9 ]; +assign v1[5 ] = d[10] | d[11]; +assign v1[6 ] = d[12] | d[13]; +assign v1[7 ] = d[14] | d[15]; +assign v1[8 ] = d[16] | d[17]; +assign v1[9 ] = d[18] | d[19]; +assign v1[10] = d[20] | d[21]; +assign v1[11] = d[22] | d[23]; +assign v1[12] = d[24] | d[25]; +assign v1[13] = d[26] | d[27]; +assign v1[14] = d[28] | d[29]; +assign v1[15] = d[30] | d[31]; +assign v1[16] = d[32] | d[33]; +assign v1[17] = d[34] | d[35]; +assign v1[18] = d[36] | d[37]; +assign v1[19] = d[38] | d[39]; +assign v1[20] = d[40] | d[41]; +assign v1[21] = d[42] | d[43]; +assign v1[22] = d[44] | d[45]; +assign v1[23] = d[46] | d[47]; +assign v1[24] = d[48] | d[49]; +assign v1[25] = d[50] | d[51]; +assign v1[26] = d[52] | d[53]; +assign v1[27] = d[54] | d[55]; +assign v1[28] = d[56] | d[57]; +assign v1[29] = d[58] | d[59]; +assign v1[30] = d[60] | d[61]; +assign v1[31] = d[62] | d[63]; + +assign p2[0 ] = {~v1[1 ], (v1[1 ] ? p1[1 ] : p1[0 ])}; +assign p2[1 ] = {~v1[3 ], (v1[3 ] ? p1[3 ] : p1[2 ])}; +assign p2[2 ] = {~v1[5 ], (v1[5 ] ? p1[5 ] : p1[4 ])}; +assign p2[3 ] = {~v1[7 ], (v1[7 ] ? p1[7 ] : p1[6 ])}; +assign p2[4 ] = {~v1[9 ], (v1[9 ] ? p1[9 ] : p1[8 ])}; +assign p2[5 ] = {~v1[11], (v1[11] ? p1[11] : p1[10])}; +assign p2[6 ] = {~v1[13], (v1[13] ? p1[13] : p1[12])}; +assign p2[7 ] = {~v1[15], (v1[15] ? p1[15] : p1[14])}; +assign p2[8 ] = {~v1[17], (v1[17] ? p1[17] : p1[16])}; +assign p2[9 ] = {~v1[19], (v1[19] ? p1[19] : p1[18])}; +assign p2[10] = {~v1[21], (v1[21] ? p1[21] : p1[20])}; +assign p2[11] = {~v1[23], (v1[23] ? p1[23] : p1[22])}; +assign p2[12] = {~v1[25], (v1[25] ? p1[25] : p1[24])}; +assign p2[13] = {~v1[27], (v1[27] ? p1[27] : p1[26])}; +assign p2[14] = {~v1[29], (v1[29] ? p1[29] : p1[28])}; +assign p2[15] = {~v1[31], (v1[31] ? p1[31] : p1[30])}; +assign v2[0 ] = v1[1 ] | v1[0 ]; +assign v2[1 ] = v1[3 ] | v1[2 ]; +assign v2[2 ] = v1[5 ] | v1[4 ]; +assign v2[3 ] = v1[7 ] | v1[6 ]; +assign v2[4 ] = v1[9 ] | v1[8 ]; +assign v2[5 ] = v1[11] | v1[10]; +assign v2[6 ] = v1[13] | v1[12]; +assign v2[7 ] = v1[15] | v1[14]; +assign v2[8 ] = v1[17] | v1[16]; +assign v2[9 ] = v1[19] | v1[18]; +assign v2[10] = v1[21] | v1[20]; +assign v2[11] = v1[23] | v1[22]; +assign v2[12] = v1[25] | v1[24]; +assign v2[13] = v1[27] | v1[26]; +assign v2[14] = v1[29] | v1[28]; +assign v2[15] = v1[31] | v1[30]; + +assign p3[0] = {~v2[1 ], (v2[1 ] ? p2[1 ] : p2[0 ])}; +assign p3[1] = {~v2[3 ], (v2[3 ] ? p2[3 ] : p2[2 ])}; +assign p3[2] = {~v2[5 ], (v2[5 ] ? p2[5 ] : p2[4 ])}; +assign p3[3] = {~v2[7 ], (v2[7 ] ? p2[7 ] : p2[6 ])}; +assign p3[4] = {~v2[9 ], (v2[9 ] ? p2[9 ] : p2[8 ])}; +assign p3[5] = {~v2[11], (v2[11] ? p2[11] : p2[10])}; +assign p3[6] = {~v2[13], (v2[13] ? p2[13] : p2[12])}; +assign p3[7] = {~v2[15], (v2[15] ? p2[15] : p2[14])}; +assign v3[0] = v2[1 ] | v2[0 ]; +assign v3[1] = v2[3 ] | v2[2 ]; +assign v3[2] = v2[5 ] | v2[4 ]; +assign v3[3] = v2[7 ] | v2[6 ]; +assign v3[4] = v2[9 ] | v2[8 ]; +assign v3[5] = v2[11] | v2[10]; +assign v3[6] = v2[13] | v2[12]; +assign v3[7] = v2[15] | v2[14]; + +assign p4[0] = {~v3[1], (v3[1] ? p3[1] : p3[0])}; +assign p4[1] = {~v3[3], (v3[3] ? p3[3] : p3[2])}; +assign p4[2] = {~v3[5], (v3[5] ? p3[5] : p3[4])}; +assign p4[3] = {~v3[7], (v3[7] ? p3[7] : p3[6])}; +assign v4[0] = v3[1] | v3[0]; +assign v4[1] = v3[3] | v3[2]; +assign v4[2] = v3[5] | v3[4]; +assign v4[3] = v3[7] | v3[6]; + +assign p5[0] = {~v4[1], (v4[1] ? p4[1] : p4[0])}; +assign p5[1] = {~v4[3], (v4[3] ? p4[3] : p4[2])}; +assign v5[0] = v4[1] | v4[0]; +assign v5[1] = v4[3] | v4[2]; + +assign p6 = {~v5[1], (v5[1] ? p5[1] : p5[0])}; + + +// Output data +assign data_out = p6; + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/gng_smul_16_18.v b/designs/encrypted_ip/uart2spi/gng_smul_16_18.v new file mode 100644 index 000000000..96b707e4d --- /dev/null +++ b/designs/encrypted_ip/uart2spi/gng_smul_16_18.v @@ -0,0 +1,66 @@ +//------------------------------------------------------------------------------ +// +// gng_smul_16_18.v +// +// This file is part of the Gaussian Noise Generator IP Core +// +// Description +// Signed multiplier 16-bit x 18-bit, delay 2 cycles. +// +//------------------------------------------------------------------------------ +// +// Copyright (C) 2014, Guangxi Liu +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as published by +// the Free Software Foundation; either version 2.1 of the License, +// or (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, download it from +// http://www.opencores.org/lgpl.shtml +// +//------------------------------------------------------------------------------ + + +`timescale 1 ns / 1 ps + + +module gng_smul_16_18 ( + // System signals + input clk, // system clock + + // Data interface + input [15:0] a, // multiplicand + input [17:0] b, // multiplicator + output [33:0] p // result +); + +// Behavioral model +reg signed [15:0] a_reg; +reg signed [17:0] b_reg; +reg signed [33:0] prod; + +always @ (posedge clk) begin + a_reg <= a; + b_reg <= b; +end + +always @ (posedge clk) begin + prod <= a_reg * b_reg; +end + +assign p = prod; + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/gng_smul_16_18_sadd_37.v b/designs/encrypted_ip/uart2spi/gng_smul_16_18_sadd_37.v new file mode 100644 index 000000000..1004314c5 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/gng_smul_16_18_sadd_37.v @@ -0,0 +1,78 @@ +//------------------------------------------------------------------------------ +// +// gng_smul_16_18_sadd_37.v +// +// This file is part of the Gaussian Noise Generator IP Core +// +// Description +// Signed multiplier 16-bit x 18-bit follows signed adder 37-bit, +// delay 3 cycles¡£ +// +//------------------------------------------------------------------------------ +// +// Copyright (C) 2014, Guangxi Liu +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as published by +// the Free Software Foundation; either version 2.1 of the License, +// or (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, download it from +// http://www.opencores.org/lgpl.shtml +// +//------------------------------------------------------------------------------ + + +`timescale 1 ns / 1 ps + + +module gng_smul_16_18_sadd_37 ( + // System signals + input clk, // system clock + + // Data interface + input [15:0] a, // multiplicand + input [17:0] b, // multiplicator + input [36:0] c, // adder + output [37:0] p // result +); + +// Behavioral model +reg signed [15:0] a_reg; +reg signed [17:0] b_reg; +reg signed [36:0] c_reg; +reg signed [33:0] prod; +wire signed [37:0] sum; +reg [37:0] result; + +always @ (posedge clk) begin + a_reg <= a; + b_reg <= b; + c_reg <= c; +end + +always @ (posedge clk) begin + prod <= a_reg * b_reg; +end + +assign sum = c_reg + prod; + +always @ (posedge clk) begin + result <= sum; +end + +assign p = result; + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/registers.v b/designs/encrypted_ip/uart2spi/registers.v new file mode 100644 index 000000000..4685609de --- /dev/null +++ b/designs/encrypted_ip/uart2spi/registers.v @@ -0,0 +1,276 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +//`timescale 1ns/100ps + +/********************************************************************* +** module: bit register + +** description: infers a register, make it modular + ***********************************************************************/ +module bit_register ( + //inputs + we, + clk, + reset_n, + data_in, + + //outputs + data_out + ); + +//--------------------------------- +// Reset Default value +//--------------------------------- +parameter RESET_DEFAULT = 1'h0; + + input we; + input clk; + input reset_n; + input data_in; + output data_out; + + reg data_out; + + //infer the register + always @(posedge clk or negedge reset_n) + begin + if (!reset_n) + data_out <= RESET_DEFAULT; + else if (we) + data_out <= data_in; + end // always @ (posedge clk or negedge reset_n) +endmodule // register + + +/********************************************************************* +** module: req register. + +** description: This register is set by cpu writting 1 and reset by + harward req = 1 + + Note: When there is a clash between cpu and hardware, cpu is given higher + priority + + ***********************************************************************/ +module req_register ( + //inputs + clk, + reset_n, + cpu_we, + cpu_req, + hware_ack, + + //outputs + data_out + ); + +//--------------------------------- +// Reset Default value +//--------------------------------- +parameter RESET_DEFAULT = 1'h0; + + input clk ; + input reset_n ; + input cpu_we ; // cpu write enable + input cpu_req ; // CPU Request + input hware_ack; // Hardware Ack + output data_out ; + + reg data_out; + + //infer the register + always @(posedge clk or negedge reset_n) + begin + if (!reset_n) + data_out <= RESET_DEFAULT; + else if (cpu_we & cpu_req) // Set on CPU Request + data_out <= 1'b1; + else if (hware_ack) // Reset the flag on Hardware ack + data_out <= 1'b0; + end // always @ (posedge clk or negedge reset_n) +endmodule // register + + +/********************************************************************* +** module: req register. + +** description: This register is cleared by cpu writting 1 and set by + harward req = 1 + + Note: When there is a clash between cpu and hardware, + hardware is given higher priority + + ***********************************************************************/ +module stat_register ( + //inputs + clk, + reset_n, + cpu_we, + cpu_ack, + hware_req, + + //outputs + data_out + ); + +//--------------------------------- +// Reset Default value +//--------------------------------- +parameter RESET_DEFAULT = 1'h0; + + input clk ; + input reset_n ; + input cpu_we ; // cpu write enable + input cpu_ack ; // CPU Ack + input hware_req; // Hardware Req + output data_out ; + + reg data_out; + + //infer the register + always @(posedge clk or negedge reset_n) + begin + if (!reset_n) + data_out <= RESET_DEFAULT; + else if (hware_req) // Set the flag on Hardware Req + data_out <= 1'b1; + else if (cpu_we & cpu_ack) // Clear on CPU Ack + data_out <= 1'b0; + end // always @ (posedge clk or negedge reset_n) +endmodule // register + + + + + +/********************************************************************* +** copyright message here. + +** module: generic register + +***********************************************************************/ +module generic_register ( + //List of Inputs + we, + data_in, + reset_n, + clk, + + //List of Outs + data_out + ); + + parameter WD = 1; + parameter RESET_DEFAULT = 0; + input [WD-1:0] we; + input [WD-1:0] data_in; + input reset_n; + input clk; + output [WD-1:0] data_out; + + +generate + genvar i; + for (i = 0; i < WD; i = i + 1) begin : gen_bit_reg + bit_register #(RESET_DEFAULT[i]) u_bit_reg ( + .we (we[i]), + .clk (clk), + .reset_n (reset_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end +endgenerate + + +endmodule + + +/********************************************************************* +** copyright message here. + +** module: generic register + +***********************************************************************/ +module generic_intr_stat_reg ( + //inputs + clk, + reset_n, + reg_we, + reg_din, + hware_req, + + //outputs + data_out + ); + + parameter WD = 1; + parameter RESET_DEFAULT = 0; + input [WD-1:0] reg_we; + input [WD-1:0] reg_din; + input [WD-1:0] hware_req; + input reset_n; + input clk; + output [WD-1:0] data_out; + + +generate + genvar i; + for (i = 0; i < WD; i = i + 1) begin : gen_bit_reg + stat_register #(RESET_DEFAULT[i]) u_bit_reg ( + //inputs + . clk (clk ), + . reset_n (reset_n ), + . cpu_we (reg_we[i] ), + . cpu_ack (reg_din[i] ), + . hware_req (hware_req[i] ), + + //outputs + . data_out (data_out[i] ) + ); + + end +endgenerate + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/spi_cfg.v b/designs/encrypted_ip/uart2spi/spi_cfg.v new file mode 100644 index 000000000..a2104e176 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/spi_cfg.v @@ -0,0 +1,362 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores SPI Interface Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + + +module spi_cfg ( + + mclk, + reset_n, + + // Reg Bus Interface Signal + reg_cs, + reg_wr, + reg_addr, + reg_wdata, + reg_be, + + // Outputs + reg_rdata, + reg_ack, + + + // configuration signal + cfg_tgt_sel , + cfg_op_req , // SPI operation request + cfg_op_type , // SPI operation type + cfg_transfer_size , // SPI transfer size + cfg_sck_period , // sck clock period + cfg_sck_cs_period , // cs setup/hold period + cfg_cs_byte , // cs bit information + cfg_datain , // data for transfer + cfg_dataout , // data for received + hware_op_done // operation done + + ); + + + +input mclk; +input reset_n; + +output [1:0] cfg_tgt_sel ; + +output cfg_op_req ; // SPI operation request +output [1:0] cfg_op_type ; // SPI operation type +output [1:0] cfg_transfer_size ; // SPI transfer size +output [5:0] cfg_sck_period ; // sck clock period +output [4:0] cfg_sck_cs_period ; // cs setup/hold period +output [7:0] cfg_cs_byte ; // cs bit information +output [31:0] cfg_datain ; // data for transfer +input [31:0] cfg_dataout ; // data for received +input hware_op_done ; // operation done + +//--------------------------------- +// Reg Bus Interface Signal +//--------------------------------- +input reg_cs ; +input reg_wr ; +input [3:0] reg_addr ; +input [31:0] reg_wdata ; +input [3:0] reg_be ; + +// Outputs +output [31:0] reg_rdata ; +output reg_ack ; + + + +//----------------------------------------------------------------------- +// Internal Wire Declarations +//----------------------------------------------------------------------- + +wire sw_rd_en; +wire sw_wr_en; +wire [3:0] sw_addr ; // addressing 16 registers +wire [3:0] wr_be ; + +reg [31:0] reg_rdata ; +reg reg_ack ; + +wire [31:0] reg_0; // Software_Reg_0 +wire [31:0] reg_1; // Software-Reg_1 +wire [31:0] reg_2; // Software-Reg_2 +wire [31:0] reg_3 = 0; // Software-Reg_3 +wire [31:0] reg_4 = 0; // Software-Reg_4 +wire [31:0] reg_5 = 0; // Software-Reg_5 +wire [31:0] reg_6 = 0; // Software-Reg_6 +wire [31:0] reg_7 = 0; // Software-Reg_7 +wire [31:0] reg_8 = 0; // Software-Reg_8 +wire [31:0] reg_9 = 0; // Software-Reg_9 +wire [31:0] reg_10 = 0; // Software-Reg_10 +wire [31:0] reg_11 = 0; // Software-Reg_11 +wire [31:0] reg_12 = 0; // Software-Reg_12 +wire [31:0] reg_13 = 0; // Software-Reg_13 +wire [31:0] reg_14 = 0; // Software-Reg_14 +wire [31:0] reg_15 = 0; // Software-Reg_15 +reg [31:0] reg_out; + +//----------------------------------------------------------------------- +// Main code starts here +//----------------------------------------------------------------------- + +//----------------------------------------------------------------------- +// Internal Logic Starts here +//----------------------------------------------------------------------- + assign sw_addr = reg_addr [3:0]; + assign sw_rd_en = reg_cs & !reg_wr; + assign sw_wr_en = reg_cs & reg_wr; + assign wr_be = reg_be; + + +//----------------------------------------------------------------------- +// Read path mux +//----------------------------------------------------------------------- + +always @ (posedge mclk or negedge reset_n) +begin : preg_out_Seq + if (reset_n == 1'b0) + begin + reg_rdata [31:0] <= 32'h0000_0000; + reg_ack <= 1'b0; + end + else if (sw_rd_en && !reg_ack) + begin + reg_rdata [31:0] <= reg_out [31:0]; + reg_ack <= 1'b1; + end + else if (sw_wr_en && !reg_ack) + reg_ack <= 1'b1; + else + begin + reg_ack <= 1'b0; + end +end + + +//----------------------------------------------------------------------- +// register read enable and write enable decoding logic +//----------------------------------------------------------------------- +wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0); +wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0); +wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1); +wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1); +wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2); +wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2); +wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3); +wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3); +wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4); +wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4); +wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5); +wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5); +wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6); +wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6); +wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7); +wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7); +wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8); +wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8); +wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9); +wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9); +wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA); +wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA); +wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB); +wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB); +wire sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC); +wire sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC); +wire sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD); +wire sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD); +wire sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE); +wire sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE); +wire sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF); +wire sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF); + + +always @( *) +begin : preg_sel_Com + + reg_out [31:0] = 32'd0; + + case (sw_addr [3:0]) + 4'b0000 : reg_out [31:0] = reg_0 [31:0]; + 4'b0001 : reg_out [31:0] = reg_1 [31:0]; + 4'b0010 : reg_out [31:0] = reg_2 [31:0]; + 4'b0011 : reg_out [31:0] = reg_3 [31:0]; + 4'b0100 : reg_out [31:0] = reg_4 [31:0]; + 4'b0101 : reg_out [31:0] = reg_5 [31:0]; + 4'b0110 : reg_out [31:0] = reg_6 [31:0]; + 4'b0111 : reg_out [31:0] = reg_7 [31:0]; + 4'b1000 : reg_out [31:0] = reg_8 [31:0]; + 4'b1001 : reg_out [31:0] = reg_9 [31:0]; + 4'b1010 : reg_out [31:0] = reg_10 [31:0]; + 4'b1011 : reg_out [31:0] = reg_11 [31:0]; + 4'b1100 : reg_out [31:0] = reg_12 [31:0]; + 4'b1101 : reg_out [31:0] = reg_13 [31:0]; + 4'b1110 : reg_out [31:0] = reg_14 [31:0]; + 4'b1111 : reg_out [31:0] = reg_15 [31:0]; + endcase +end + + + +//----------------------------------------------------------------------- +// Individual register assignments +//----------------------------------------------------------------------- +// Logic for Register 0 : SPI Control Register +//----------------------------------------------------------------------- +wire cfg_op_req = reg_0[31]; // cpu request +wire [1:0] cfg_tgt_sel = reg_0[24:23]; // target chip select +wire [1:0] cfg_op_type = reg_0[22:21]; // SPI operation type +wire [1:0] cfg_transfer_size = reg_0[20:19]; // SPI transfer size +wire [5:0] cfg_sck_period = reg_0[18:13]; // sck clock period +wire [4:0] cfg_sck_cs_period = reg_0[12:8]; // cs setup/hold period +wire [7:0] cfg_cs_byte = reg_0[7:0]; // cs bit information + +generic_register #(8,0 ) u_spi_ctrl_be0 ( + .we ({8{sw_wr_en_0 & + wr_be[0] }} ), + .data_in (reg_wdata[7:0] ), + .reset_n (reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_0[7:0] ) + ); + +generic_register #(8,0 ) u_spi_ctrl_be1 ( + .we ({8{sw_wr_en_0 & + wr_be[1] }} ), + .data_in (reg_wdata[15:8] ), + .reset_n (reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_0[15:8] ) + ); + +generic_register #(8,0 ) u_spi_ctrl_be2 ( + .we ({8{sw_wr_en_0 & + wr_be[2] }} ), + .data_in (reg_wdata[23:16] ), + .reset_n (reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_0[23:16] ) + ); + +assign reg_0[30:24] = 7'h0; + +req_register #(0 ) u_spi_ctrl_req ( + .cpu_we ({sw_wr_en_0 & + wr_be[3] } ), + .cpu_req (reg_wdata[31] ), + .hware_ack (hware_op_done ), + .reset_n (reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_0[31] ) + ); + + + + +//----------------------------------------------------------------------- +// Logic for Register 1 : SPI Data In Register +//----------------------------------------------------------------------- +wire [31:0] cfg_datain = reg_1[31:0]; + +generic_register #(8,0 ) u_spi_din_be0 ( + .we ({8{sw_wr_en_1 & + wr_be[0] }} ), + .data_in (reg_wdata[7:0] ), + .reset_n (reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_1[7:0] ) + ); + +generic_register #(8,0 ) u_spi_din_be1 ( + .we ({8{sw_wr_en_1 & + wr_be[1] }} ), + .data_in (reg_wdata[15:8] ), + .reset_n (reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_1[15:8] ) + ); + +generic_register #(8,0 ) u_spi_din_be2 ( + .we ({8{sw_wr_en_1 & + wr_be[2] }} ), + .data_in (reg_wdata[23:16] ), + .reset_n (reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_1[23:16] ) + ); + + +generic_register #(8,0 ) u_spi_din_be3 ( + .we ({8{sw_wr_en_1 & + wr_be[3] }} ), + .data_in (reg_wdata[31:24] ), + .reset_n (reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_1[31:24] ) + ); + + +//----------------------------------------------------------------------- +// Logic for Register 2 : SPI Data output Register +//----------------------------------------------------------------------- +assign reg_2 = cfg_dataout; + + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/spi_core.v b/designs/encrypted_ip/uart2spi/spi_core.v new file mode 100644 index 000000000..1bc4d2d60 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/spi_core.v @@ -0,0 +1,198 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores SPI Interface Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +module spi_core ( + + clk, + reset_n, + + // Reg Bus Interface Signal + reg_cs, + reg_wr, + reg_addr, + reg_wdata, + reg_be, + + // Outputs + reg_rdata, + reg_ack, + + // line interface + sck , + so , + si , + cs_n + + ); + +input clk ; +input reset_n ; + + +//--------------------------------- +// Reg Bus Interface Signal +//--------------------------------- +input reg_cs ; +input reg_wr ; +input [3:0] reg_addr ; +input [31:0] reg_wdata ; +input [3:0] reg_be ; + +// Outputs +output [31:0] reg_rdata ; +output reg_ack ; + +//------------------------------------------- +// Line Interface +//------------------------------------------- + +output sck ; // clock out +output so ; // serial data out +input si ; // serial data in +output [3:0] cs_n ; // cs_n + +//------------------------------------ +// Wires +//------------------------------------ + +wire [7:0] byte_in ; +wire [7:0] byte_out ; + + +wire [1:0] cfg_tgt_sel ; + +wire cfg_op_req ; // SPI operation request +wire [1:0] cfg_op_type ; // SPI operation type +wire [1:0] cfg_transfer_size ; // SPI transfer size +wire [5:0] cfg_sck_period ; // sck clock period +wire [4:0] cfg_sck_cs_period ; // cs setup/hold period +wire [7:0] cfg_cs_byte ; // cs bit information +wire [31:0] cfg_datain ; // data for transfer +wire [31:0] cfg_dataout ; // data for received +wire hware_op_done ; // operation done + +spi_if u_spi_if + ( + . clk (clk ), + . reset_n (reset_n ), + + // towards ctrl i/f + . sck_pe (sck_pe ), + . sck_int (sck_int ), + . cs_int_n (cs_int_n ), + . byte_in (byte_in ), + . load_byte (load_byte ), + . byte_out (byte_out ), + . shift_out (shift_out ), + . shift_in (shift_in ), + + . cfg_tgt_sel (cfg_tgt_sel ), + + . sck (sck ), + . so (so ), + . si (si ), + . cs_n (cs_n ) + ); + + +spi_ctl u_spi_ctrl + ( + . clk (clk ), + . reset_n (reset_n ), + + . cfg_op_req (cfg_op_req ), + . cfg_op_type (cfg_op_type ), + . cfg_transfer_size (cfg_transfer_size ), + . cfg_sck_period (cfg_sck_period ), + . cfg_sck_cs_period (cfg_sck_cs_period ), + . cfg_cs_byte (cfg_cs_byte ), + . cfg_datain (cfg_datain ), + . cfg_dataout (cfg_dataout ), + . op_done (hware_op_done ), + + . sck_int (sck_int ), + . cs_int_n (cs_int_n ), + . sck_pe (sck_pe ), + . sck_ne (sck_ne ), + . shift_out (shift_out ), + . shift_in (shift_in ), + . load_byte (load_byte ), + . byte_out (byte_out ), + . byte_in (byte_in ) + + ); + + + + +spi_cfg u_cfg ( + + . mclk (clk ), + . reset_n (reset_n ), + + // Reg Bus Interface Signal + . reg_cs (reg_cs ), + . reg_wr (reg_wr ), + . reg_addr (reg_addr ), + . reg_wdata (reg_wdata ), + . reg_be (reg_be ), + + // Outputs + . reg_rdata (reg_rdata ), + . reg_ack (reg_ack ), + + + // configuration signal + . cfg_tgt_sel (cfg_tgt_sel ), + . cfg_op_req (cfg_op_req ), // SPI operation request + . cfg_op_type (cfg_op_type ), // SPI operation type + . cfg_transfer_size (cfg_transfer_size ), // SPI transfer size + . cfg_sck_period (cfg_sck_period ), // sck clock period + . cfg_sck_cs_period (cfg_sck_cs_period ), // cs setup/hold period + . cfg_cs_byte (cfg_cs_byte ), // cs bit information + . cfg_datain (cfg_datain ), // data for transfer + . cfg_dataout (cfg_dataout ), // data for received + . hware_op_done (hware_op_done ) // operation done + + ); + +endmodule diff --git a/designs/encrypted_ip/uart2spi/spi_ctl.v b/designs/encrypted_ip/uart2spi/spi_ctl.v new file mode 100644 index 000000000..860963217 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/spi_ctl.v @@ -0,0 +1,310 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores SPI Interface Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + + +module spi_ctl + ( clk, + reset_n, + sck_int, + + + cfg_op_req, + cfg_op_type, + cfg_transfer_size, + cfg_sck_period, + cfg_sck_cs_period, + cfg_cs_byte, + cfg_datain, + cfg_dataout, + op_done, + + cs_int_n, + sck_pe, + sck_ne, + shift_out, + shift_in, + byte_out, + byte_in, + load_byte + + ); + + //************************************************************************* + + input clk, reset_n; + input cfg_op_req; + input [1:0] cfg_op_type; + input [1:0] cfg_transfer_size; + + input [5:0] cfg_sck_period; + input [4:0] cfg_sck_cs_period; // cs setup & hold period + input [7:0] cfg_cs_byte; + input [31:0] cfg_datain; + output [31:0] cfg_dataout; + + output [7:0] byte_out; // Byte out for Serial Shifting out + input [7:0] byte_in; // Serial Received Byte + output sck_int; + output cs_int_n; + output sck_pe; + output sck_ne; + output shift_out; + output shift_in; + output load_byte; + output op_done; + + reg [31:0] cfg_dataout; + reg sck_ne; + reg sck_pe; + reg sck_int; + reg [5:0] clk_cnt; + reg [5:0] sck_cnt; + + reg [3:0] spiif_cs; + reg shift_enb; + reg cs_int_n; + reg clr_sck_cnt ; + reg sck_out_en; + + wire [5:0] sck_half_period; + reg load_byte; + reg shift_in; + reg op_done; + reg [2:0] byte_cnt; + + + `define SPI_IDLE 4'b0000 + `define SPI_CS_SU 4'b0001 + `define SPI_WRITE 4'b0010 + `define SPI_READ 4'b0011 + `define SPI_CS_HLD 4'b0100 + `define SPI_WAIT 4'b0101 + + + assign sck_half_period = {1'b0, cfg_sck_period[5:1]}; + // The first transition on the sck_toggle happens one SCK period + // after op_en or boot_en is asserted + always @(posedge clk or negedge reset_n) begin + if(!reset_n) begin + sck_ne <= 1'b0; + clk_cnt <= 6'h1; + sck_pe <= 1'b0; + sck_int <= 1'b0; + end // if (!reset_n) + else + begin + if(cfg_op_req) + begin + if(clk_cnt == sck_half_period) + begin + sck_ne <= 1'b1; + sck_pe <= 1'b0; + if(sck_out_en) sck_int <= 0; + clk_cnt <= clk_cnt + 1'b1; + end // if (clk_cnt == sck_half_period) + else + begin + if(clk_cnt == cfg_sck_period) + begin + sck_ne <= 1'b0; + sck_pe <= 1'b1; + if(sck_out_en) sck_int <= 1; + clk_cnt <= 6'h1; + end // if (clk_cnt == cfg_sck_period) + else + begin + clk_cnt <= clk_cnt + 1'b1; + sck_pe <= 1'b0; + sck_ne <= 1'b0; + end // else: !if(clk_cnt == cfg_sck_period) + end // else: !if(clk_cnt == sck_half_period) + end // if (op_en) + else + begin + clk_cnt <= 6'h1; + sck_pe <= 1'b0; + sck_ne <= 1'b0; + end // else: !if(op_en) + end // else: !if(!reset_n) + end // always @ (posedge clk or negedge reset_n) + + +wire [1:0] cs_data = (byte_cnt == 2'b00) ? cfg_cs_byte[7:6] : + (byte_cnt == 2'b01) ? cfg_cs_byte[5:4] : + (byte_cnt == 2'b10) ? cfg_cs_byte[3:2] : cfg_cs_byte[1:0] ; + +wire [7:0] byte_out = (byte_cnt == 2'b00) ? cfg_datain[31:24] : + (byte_cnt == 2'b01) ? cfg_datain[23:16] : + (byte_cnt == 2'b10) ? cfg_datain[15:8] : cfg_datain[7:0] ; + +assign shift_out = shift_enb && sck_ne; + +always @(posedge clk or negedge reset_n) begin + if(!reset_n) begin + spiif_cs <= `SPI_IDLE; + sck_cnt <= 6'h0; + shift_in <= 1'b0; + clr_sck_cnt <= 1'b1; + byte_cnt <= 2'b00; + cs_int_n <= 1'b1; + sck_out_en <= 1'b0; + shift_enb <= 1'b0; + cfg_dataout <= 32'h0; + load_byte <= 1'b0; + end + else begin + if(sck_ne) + sck_cnt <= clr_sck_cnt ? 6'h0 : sck_cnt + 1 ; + + case(spiif_cs) + `SPI_IDLE : + begin + op_done <= 0; + clr_sck_cnt <= 1'b1; + sck_out_en <= 1'b0; + shift_enb <= 1'b0; + if(cfg_op_req) + begin + cfg_dataout <= 32'h0; + spiif_cs <= `SPI_CS_SU; + end + else begin + spiif_cs <= `SPI_IDLE; + end + end + + `SPI_CS_SU : + begin + if(sck_ne) begin + cs_int_n <= cs_data[1]; + if(sck_cnt == cfg_sck_cs_period) begin + clr_sck_cnt <= 1'b1; + if(cfg_op_type == 0) begin // Write Mode + load_byte <= 1'b1; + spiif_cs <= `SPI_WRITE; + shift_enb <= 1'b0; + end else begin + shift_in <= 1; + spiif_cs <= `SPI_READ; + end + end + else begin + clr_sck_cnt <= 1'b0; + end + end + end + + `SPI_WRITE : + begin + load_byte <= 1'b0; + if(sck_ne) begin + if(sck_cnt == 3'h7 )begin + clr_sck_cnt <= 1'b1; + spiif_cs <= `SPI_CS_HLD; + shift_enb <= 1'b0; + sck_out_en <= 1'b0; // Disable clock output + end + else begin + shift_enb <= 1'b1; + sck_out_en <= 1'b1; + clr_sck_cnt <= 1'b0; + end + end else begin + shift_enb <= 1'b1; + end + end + + `SPI_READ : + begin + if(sck_ne) begin + if( sck_cnt == 3'h7 ) begin + clr_sck_cnt <= 1'b1; + shift_in <= 0; + spiif_cs <= `SPI_CS_HLD; + sck_out_en <= 1'b0; // Disable clock output + end + else begin + sck_out_en <= 1'b1; // Disable clock output + clr_sck_cnt <= 1'b0; + end + end + end + + `SPI_CS_HLD : begin + if(sck_ne) begin + cs_int_n <= cs_data[0]; + if(sck_cnt == cfg_sck_cs_period) begin + if(cfg_op_type == 1) begin // Read Mode + cfg_dataout <= (byte_cnt[1:0] == 2'b00) ? { byte_in, cfg_dataout[23:0] } : + (byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:24] , + byte_in, cfg_dataout[15:0] } : + (byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16] , + byte_in, cfg_dataout[7:0] } : + { cfg_dataout[31:8] , + byte_in } ; + end + clr_sck_cnt <= 1'b1; + if(byte_cnt == cfg_transfer_size) begin + spiif_cs <= `SPI_WAIT; + byte_cnt <= 0; + op_done <= 1; + end else begin + byte_cnt <= byte_cnt +1; + spiif_cs <= `SPI_CS_SU; + end + end + else begin + clr_sck_cnt <= 1'b0; + end + end + end // case: `SPI_CS_HLD + `SPI_WAIT : begin + if(!cfg_op_req) // Wait for Request de-assertion + spiif_cs <= `SPI_IDLE; + end + endcase // casex(spiif_cs) + end +end // always @(sck_ne + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/uart2spi/spi_if.v b/designs/encrypted_ip/uart2spi/spi_if.v new file mode 100644 index 000000000..0998fd74d --- /dev/null +++ b/designs/encrypted_ip/uart2spi/spi_if.v @@ -0,0 +1,137 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores SPI Interface Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module spi_if + ( + clk, + reset_n, + + // towards ctrl i/f + sck_pe, + sck_int, + cs_int_n, + byte_in, + load_byte, + byte_out, + shift_out, + shift_in, + + cfg_tgt_sel, + + sck, + so, + si, + cs_n + ); + + input clk,reset_n; + input sck_pe; + input sck_int,cs_int_n; + + input load_byte; + input [1:0] cfg_tgt_sel; + + input [7:0] byte_out; + input shift_out,shift_in; + + output [7:0] byte_in; + output sck,so; + output [3:0] cs_n; + input si; + + + reg [7:0] so_reg; + reg [7:0] si_reg; + wire [7:0] byte_out; + wire sck; + reg so; + wire [3:0] cs_n; + + + //Output Shift Register + + always @(posedge clk or negedge reset_n) begin + if(!reset_n) begin + so_reg <= 8'h00; + so <= 1'b0; + end + else begin + if(load_byte) begin + so_reg <= byte_out; + if(shift_out) begin + // Handling backto back case : + // Last Transfer bit + New Trasfer Load + so <= so_reg[7]; + end + end // if (load_byte) + else begin + if(shift_out) begin + so <= so_reg[7]; + so_reg <= {so_reg[6:0],1'b0}; + end // if (shift_out) + end // else: !if(load_byte) + end // else: !if(!reset_n) + end // always @ (posedge clk or negedge reset_n) + + +// Input shift register + always @(posedge clk or negedge reset_n) begin + if(!reset_n) begin + si_reg <= 8'h0; + end + else begin + if(sck_pe & shift_in) begin + si_reg[7:0] <= {si_reg[6:0],si}; + end // if (sck_pe & shift_in) + end // else: !if(!reset_n) + end // always @ (posedge clk or negedge reset_n) + + + assign byte_in[7:0] = si_reg[7:0]; + assign cs_n[0] = (cfg_tgt_sel[1:0] == 2'b00) ? cs_int_n : 1'b1; + assign cs_n[1] = (cfg_tgt_sel[1:0] == 2'b01) ? cs_int_n : 1'b1; + assign cs_n[2] = (cfg_tgt_sel[1:0] == 2'b10) ? cs_int_n : 1'b1; + assign cs_n[3] = (cfg_tgt_sel[1:0] == 2'b11) ? cs_int_n : 1'b1; + assign sck = sck_int; + +endmodule diff --git a/designs/encrypted_ip/uart2spi/top.v b/designs/encrypted_ip/uart2spi/top.v new file mode 100644 index 000000000..5e2645966 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/top.v @@ -0,0 +1,82 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 07/10/2017 10:59:08 AM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module top( + input clk, + input reset, // Not used + input [15:0] sw, + input [4:0] btn, // Not used + output [15:0] led, + output [6:0] seg, // Not used + output dp, + output [7:0] an // Not used + ); + + assign seg = {btn, reset, 1'b0}; + assign an = 8'b00000000; + + wire [63:0] concat; + assign concat = {sw, sw, sw, sw}; + + wire top_valid_out; + wire [15:0] top_data_out; + + gng gng_0( + .INIT_Z1(concat), + .INIT_Z2(concat), + .INIT_Z3(concat), + .clk(clk), + .rstn(sw[0]), + .ce(sw[1]), + .valid_out(top_valid_out), + .data_out(top_data_out) + ); + + assign led = top_data_out; + + + wire frm_error, par_error, baud_clk_16x; + wire txd, sck, so; + wire [3:0] cs_n; + + uart2spi uart2spi_0 ( + concat[0], + clk, + concat[0], + concat[1], + concat[2], + concat[4:3], + concat[16:5], + frm_error, + par_error, + baud_clk_16x, + concat[16], + txd, + sck, + so, + concat[17], + cs_n + ); + wire red; + assign red = top_valid_out ^ frm_error ^ par_error ^ baud_clk_16x ^ txd ^ sck ^ so ^ (^cs_n); + assign dp = red; + +endmodule diff --git a/designs/encrypted_ip/uart2spi/uart2spi.v b/designs/encrypted_ip/uart2spi/uart2spi.v new file mode 100644 index 000000000..871c98a1c --- /dev/null +++ b/designs/encrypted_ip/uart2spi/uart2spi.v @@ -0,0 +1,228 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// UART2SPI Top Module //// +//// //// +//// This file is part of the uart2spi cores project //// +//// http://www.opencores.org/cores/uart2spi/ //// +//// //// +//// Description //// +//// Uart2SPI top level integration. //// +//// 1. spi_core //// +//// 2. uart_core //// +//// 3. uart_msg_handler //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module uart2spi ( + line_reset_n , + line_clk , + + // configuration control + cfg_tx_enable , // Enable Transmit Path + cfg_rx_enable , // Enable Received Path + cfg_stop_bit , // 0 -> 1 Start , 1 -> 2 Stop Bits + cfg_pri_mod , // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd + cfg_baud_16x , + + // Status information + frm_error , + par_error , + + baud_clk_16x, + + // Line Interface + rxd, + txd, + + // Spi I/F + sck, + so, + si, + cs_n + + ); + + + +//--------------------------------- +// Global Dec +// --------------------------------- + +input line_reset_n ; // line reset +input line_clk ; // line clock + +//------------------------------------- +// Configuration +// ------------------------------------- +input cfg_tx_enable ; // Tx Enable +input cfg_rx_enable ; // Rx Enable +input cfg_stop_bit ; // 0 -> 1 Stop, 1 -> 2 Stop +input [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd +input [11:0] cfg_baud_16x ; // 16x Baud clock generation + +//-------------------------------------- +// ERROR Indication +// ------------------------------------- +output frm_error ; // framing error +output par_error ; // par error + +output baud_clk_16x ; // 16x Baud clock + + +//------------------------------------- +// Line Interface +// ------------------------------------- +input rxd ; // uart rxd +output txd ; // uart txd + +//------------------------------------- +// Spi I/F +//------------------------------------- +output sck ; // clock out +output so ; // serial data out +input si ; // serial data in +output [3:0] cs_n ; // cs_n +//--------------------------------------- +// Control Unit interface +// -------------------------------------- + +wire [15:0] reg_addr ; // Register Address +wire [31:0] reg_wdata ; // Register Wdata +wire reg_req ; // Register Request +wire reg_wr ; // 1 -> write; 0 -> read +wire reg_ack ; // Register Ack +wire [31:0] reg_rdata ; +//-------------------------------------- +// TXD Path +// ------------------------------------- +wire tx_data_avail ; // Indicate valid TXD Data +wire [7:0] tx_data ; // TXD Data to be transmited +wire tx_rd ; // Indicate TXD Data Been Read + + +//-------------------------------------- +// RXD Path +// ------------------------------------- +wire rx_ready ; // Indicate Ready to accept the Read Data +wire [7:0] rx_data ; // RXD Data +wire rx_wr ; // Valid RXD Data + +spi_core u_spi ( + + .clk (baud_clk_16x), + .reset_n (line_reset_n), + + // Reg Bus Interface Signal + .reg_cs (reg_req ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr[5:2]), + .reg_wdata (reg_wdata ), + .reg_be (4'b1111 ), + + // Outputs + .reg_rdata (reg_rdata ), + .reg_ack (reg_ack ), + + // line interface + .sck (sck ), + .so (so ), + .si (si ), + .cs_n (cs_n ) + + ); + + uart_core u_core ( + .line_reset_n (line_reset_n) , + .line_clk (line_clk) , + + // configuration control + .cfg_tx_enable (cfg_tx_enable) , + .cfg_rx_enable (cfg_rx_enable) , + .cfg_stop_bit (cfg_stop_bit) , + .cfg_pri_mod (cfg_pri_mod) , + .cfg_baud_16x (cfg_baud_16x) , + + // TXD Information + .tx_data_avail (tx_data_avail) , + .tx_rd (tx_rd) , + .tx_data (tx_data) , + + + // RXD Information + .rx_ready (rx_ready) , + .rx_wr (rx_wr) , + .rx_data (rx_data) , + + // Status information + .frm_error (frm_error) , + .par_error (par_error) , + + .baud_clk_16x (baud_clk_16x) , + + // Line Interface + .rxd (rxd) , + .txd (txd) + + ); + + + +uart_msg_handler u_msg ( + .reset_n (line_reset_n ) , + .sys_clk (baud_clk_16x ) , + + + // UART-TX Information + .tx_data_avail (tx_data_avail) , + .tx_rd (tx_rd) , + .tx_data (tx_data) , + + + // UART-RX Information + .rx_ready (rx_ready) , + .rx_wr (rx_wr) , + .rx_data (rx_data) , + + // Towards Control Unit + .reg_addr (reg_addr), + .reg_wr (reg_wr), + .reg_wdata (reg_wdata), + .reg_req (reg_req), + .reg_ack (reg_ack), + .reg_rdata (reg_rdata) + + ); + +endmodule diff --git a/designs/encrypted_ip/uart2spi/uart_core.v b/designs/encrypted_ip/uart2spi/uart_core.v new file mode 100644 index 000000000..580ab2e95 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/uart_core.v @@ -0,0 +1,190 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores UART Interface Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +module uart_core ( + line_reset_n , + line_clk , + + // configuration control + cfg_tx_enable , // Enable Transmit Path + cfg_rx_enable , // Enable Received Path + cfg_stop_bit , // 0 -> 1 Start , 1 -> 2 Stop Bits + cfg_pri_mod , // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd + cfg_baud_16x , + + // TXD Information + tx_data_avail, + tx_rd, + tx_data, + + + // RXD Information + rx_ready, + rx_wr, + rx_data, + + // Status information + frm_error, + par_error, + + baud_clk_16x, + + // Line Interface + rxd, + txd + + ); + + + +//--------------------------------- +// Global Dec +// --------------------------------- + +input line_reset_n ; // line reset +input line_clk ; // line clock + +//------------------------------------- +// Configuration +// ------------------------------------- +input cfg_tx_enable ; // Tx Enable +input cfg_rx_enable ; // Rx Enable +input cfg_stop_bit ; // 0 -> 1 Stop, 1 -> 2 Stop +input [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd +input [11:0] cfg_baud_16x ; // 16x Baud clock generation + +//-------------------------------------- +// TXD Path +// ------------------------------------- +input tx_data_avail ; // Indicate valid TXD Data +input [7:0] tx_data ; // TXD Data to be transmited +output tx_rd ; // Indicate TXD Data Been Read + + +//-------------------------------------- +// RXD Path +// ------------------------------------- +input rx_ready ; // Indicate Ready to accept the Read Data +output [7:0] rx_data ; // RXD Data +output rx_wr ; // Valid RXD Data + + +//-------------------------------------- +// ERROR Indication +// ------------------------------------- +output frm_error ; // framing error +output par_error ; // par error + +output baud_clk_16x ; // 16x Baud clock + + +//------------------------------------- +// Line Interface +// ------------------------------------- +input rxd ; // uart rxd +output txd ; // uart txd + +// Wire Declaration + +wire [1 : 0] error_ind ; + + +// 16x Baud clock generation +// Example: to generate 19200 Baud clock from 50Mhz Link clock +// 50 * 1000 * 1000 / (2 + cfg_baud_16x) = 19200 * 16 +// cfg_baud_16x = 0xA0 (160) + +clk_ctl #(11) u_clk_ctl ( + // Outputs + .clk_o (baud_clk_16x), + + // Inputs + .mclk (line_clk), + .reset_n (line_reset_n), + .clk_div_ratio (cfg_baud_16x) + ); + + +uart_txfsm u_txfsm ( + . reset_n ( line_reset_n ), + . baud_clk_16x ( baud_clk_16x ), + + . cfg_tx_enable ( cfg_tx_enable ), + . cfg_stop_bit ( cfg_stop_bit ), + . cfg_pri_mod ( cfg_pri_mod ), + + // FIFO control signal + . fifo_empty ( !tx_data_avail ), + . fifo_rd ( tx_rd ), + . fifo_data ( tx_data ), + + // Line Interface + . so ( txd ) + ); + + +uart_rxfsm u_rxfsm ( + . reset_n ( line_reset_n ), + . baud_clk_16x ( baud_clk_16x ) , + + . cfg_rx_enable ( cfg_rx_enable ), + . cfg_stop_bit ( cfg_stop_bit ), + . cfg_pri_mod ( cfg_pri_mod ), + + . error_ind ( error_ind ), + + // FIFO control signal + . fifo_aval ( rx_ready ), + . fifo_wr ( rx_wr ), + . fifo_data ( rx_data ), + + // Line Interface + . si (rxd ) + ); + + +wire frm_error = (error_ind == 2'b01); +wire par_error = (error_ind == 2'b10); + + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/uart_msg_handler.v b/designs/encrypted_ip/uart2spi/uart_msg_handler.v new file mode 100644 index 000000000..e32c89562 --- /dev/null +++ b/designs/encrypted_ip/uart2spi/uart_msg_handler.v @@ -0,0 +1,384 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// UART Message Handler Module //// +//// //// +//// This file is part of the uart2spi cores project //// +//// http://www.opencores.org/cores/uart2spi/ //// +//// //// +//// Description //// +//// Uart Message Handler definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module uart_msg_handler ( + reset_n , + sys_clk , + + + // UART-TX Information + tx_data_avail, + tx_rd, + tx_data, + + + // UART-RX Information + rx_ready, + rx_wr, + rx_data, + + // Towards Register Interface + reg_addr, + reg_wr, + reg_wdata, + reg_req, + reg_ack, + reg_rdata + + ); + + +// Define the Message Hanlde States +`define IDLE 4'h0 +`define IDLE_TX_MSG1 4'h1 +`define IDLE_TX_MSG2 4'h2 +`define RX_CMD_PHASE 4'h3 +`define WR_ADR_PHASE 4'h4 +`define WR_DATA_PHASE 4'h5 +`define SEND_WR_REQ 4'h6 +`define RD_ADDR_PHASE 4'h7 +`define SEND_RD_REQ 4'h8 +`define SEND_RD_DATA 4'h9 +`define TX_MSG 4'hA + +`define BREAK_CHAR 8'h0A + +//--------------------------------- +// Global Dec +// --------------------------------- + +input reset_n ; // line reset +input sys_clk ; // line clock + + +//-------------------------------------- +// UART TXD Path +// ------------------------------------- +output tx_data_avail ; // Indicate valid TXD Data available +output [7:0] tx_data ; // TXD Data to be transmited +input tx_rd ; // Indicate TXD Data Been Read + + +//-------------------------------------- +// UART RXD Path +// ------------------------------------- +output rx_ready ; // Indicate Ready to accept the Read Data +input [7:0] rx_data ; // RXD Data +input rx_wr ; // Valid RXD Data + +//--------------------------------------- +// Control Unit interface +// -------------------------------------- + +output [15:0] reg_addr ; // Operend-1 +output [31:0] reg_wdata ; // Operend-2 +output reg_req ; // Register Request +output reg_wr ; // 1 -> write; 0 -> read +input reg_ack ; // Register Ack +input [31:0] reg_rdata ; + +// Local Wire/Register Decleration +// +// +reg tx_data_avail ; +reg [7:0] tx_data ; +reg [16*8-1:0] TxMsgBuf ; // 16 Byte Tx Message Buffer +reg [4:0] TxMsgSize ; +reg [4:0] RxMsgCnt ; // Count the Receive Message Count +reg [3:0] State ; +reg [3:0] NextState ; +reg [15:0] cmd ; // command +reg [15:0] reg_addr ; // reg_addr +reg [31:0] reg_wdata ; // reg_addr +reg reg_wr ; // 1 -> Reg Write request, 0 -> Read Requestion +reg reg_req ; // 1 -> Register request + + +wire rx_ready = 1; +/**************************************************************** +* UART Message Hanlding Steps +* +* 1. On Reset Or Unknown command, Send the Default Message +* Select Option: +* wr +* rd +* 2. Wait for User command +* 3. On command move to write address phase; +* phase +* A. After write address phase move to write data phase +* B. After write data phase, once user press \r command ; send register req +* and write request and address + data +* C. On receiving register ack response; send message back and move +* to state-2 +* 3. On command move to read address phase; +* A. After read address phase , once user press '\r' command; send +* register req , read request +* C. On receiving register ack response; send message and move +* to state-2 +* *****************************************************************/ + +always @(negedge reset_n or posedge sys_clk) +begin + if(reset_n == 1'b0) begin + tx_data_avail <= 0; + reg_req <= 0; + State <= `IDLE; + NextState <= `IDLE; + end else begin + case(State) + // Send Default Message + `IDLE: begin + TxMsgBuf <= "Command Format:\n"; // Align to 16 character format by appending space character + TxMsgSize <= 16; + tx_data_avail <= 0; + State <= `TX_MSG; + NextState <= `IDLE_TX_MSG1; + end + + // Send Default Message (Contd..) + `IDLE_TX_MSG1: begin + TxMsgBuf <= "wm \n "; // Align to 16 character format by appending space character + TxMsgSize <= 15; + tx_data_avail <= 0; + State <= `TX_MSG; + NextState <= `IDLE_TX_MSG2; + end + + // Send Default Message (Contd..) + `IDLE_TX_MSG2: begin + TxMsgBuf <= "rm \n>> "; // Align to 16 character format by appending space character + TxMsgSize <= 10; + tx_data_avail <= 0; + RxMsgCnt <= 0; + State <= `TX_MSG; + NextState <= `RX_CMD_PHASE; + end + + // Wait for Response + `RX_CMD_PHASE: begin + if(rx_wr == 1) begin + //if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the same + if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the same + //end else if(RxMsgCnt > 0 && rx_data == " ") begin // Check the command + end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Check the command + //if(cmd == "wm") begin + if(cmd == 16'h776D) begin + RxMsgCnt <= 0; + reg_addr <= 0; + reg_wdata <= 0; + State <= `WR_ADR_PHASE; + //end else if(cmd == "rm") begin + end else if(cmd == 16'h726D) begin + reg_addr <= 0; + RxMsgCnt <= 0; + State <= `RD_ADDR_PHASE; + end else begin // Unknow command + State <= `IDLE; + end + //end else if(rx_data == "\n") begin // Error State + end else if(rx_data == `BREAK_CHAR) begin // Error State + State <= `IDLE; + end + else begin + cmd <= (cmd << 8) | rx_data ; + RxMsgCnt <= RxMsgCnt+1; + end + end + end + // Write Address Phase + `WR_ADR_PHASE: begin + if(rx_wr == 1) begin + //if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the Space character + if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the Space character + //end else if(RxMsgCnt > 0 && rx_data == " ") begin // Move to write data phase + end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Move to write data phase + State <= `WR_DATA_PHASE; + //end else if(rx_data == "\n") begin // Error State + end else if(rx_data == `BREAK_CHAR) begin // Error State + State <= `IDLE; + end else begin + reg_addr <= (reg_addr << 4) | char2hex(rx_data); + RxMsgCnt <= RxMsgCnt+1; + end + end + end + // Write Data Phase + `WR_DATA_PHASE: begin + if(rx_wr == 1) begin + //if(rx_data == " ") begin // Ignore the Space character + if(rx_data == 8'h20) begin // Ignore the Space character + //end else if(rx_data == "\n") begin // Error State + end else if(rx_data == `BREAK_CHAR) begin // Error State + State <= `SEND_WR_REQ; + reg_wr <= 1'b1; // Write request + reg_req <= 1'b1; + end else begin // A to F + reg_wdata <= (reg_wdata << 4) | char2hex(rx_data); + end + end + end + `SEND_WR_REQ: begin + if(reg_ack) begin + reg_req <= 1'b0; + TxMsgBuf <= "cmd success\n>> "; // Align to 16 character format by appending space character + TxMsgSize <= 14; + tx_data_avail <= 0; + State <= `TX_MSG; + NextState <= `RX_CMD_PHASE; + end + end + + // Write Address Phase + `RD_ADDR_PHASE: begin + if(rx_wr == 1) begin + //if(rx_data == " ") begin // Ignore the Space character + if(rx_data == 8'h20) begin // Ignore the Space character + //end else if(rx_data == "\n") begin // Error State + end else if(rx_data == `BREAK_CHAR) begin // Error State + State <= `SEND_RD_REQ; + reg_wr <= 1'b0; // Read request + reg_req <= 1'b1; // Reg Request + end + else begin // A to F + reg_addr <= (reg_addr << 4) | char2hex(rx_data); + RxMsgCnt <= RxMsgCnt+1; + end + end + end + + `SEND_RD_REQ: begin + if(reg_ack) begin + reg_req <= 1'b0; + TxMsgBuf <= "Response: "; // Align to 16 character format by appending space character + TxMsgSize <= 10; + tx_data_avail <= 0; + State <= `TX_MSG; + NextState <= `SEND_RD_DATA; + end + end + `SEND_RD_DATA: begin // Wait for Operation Completion + TxMsgBuf[16*8-1:15*8] <= hex2char(reg_rdata[31:28]); + TxMsgBuf[15*8-1:14*8] <= hex2char(reg_rdata[27:24]); + TxMsgBuf[14*8-1:13*8] <= hex2char(reg_rdata[23:20]); + TxMsgBuf[13*8-1:12*8] <= hex2char(reg_rdata[19:16]); + TxMsgBuf[12*8-1:11*8] <= hex2char(reg_rdata[15:12]); + TxMsgBuf[11*8-1:10*8] <= hex2char(reg_rdata[11:8]); + TxMsgBuf[10*8-1:9*8] <= hex2char(reg_rdata[7:4]); + TxMsgBuf[9*8-1:8*8] <= hex2char(reg_rdata[3:0]); + TxMsgBuf[8*8-1:7*8] <= "\n"; + TxMsgSize <= 9; + tx_data_avail <= 0; + State <= `TX_MSG; + NextState <= `RX_CMD_PHASE; + end + + // Send Default Message (Contd..) + `TX_MSG: begin + tx_data_avail <= 1; + tx_data <= TxMsgBuf[16*8-1:15*8]; + if(TxMsgSize == 0) begin + tx_data_avail <= 0; + State <= NextState; + end else if(tx_rd) begin + TxMsgBuf <= TxMsgBuf << 8; + TxMsgSize <= TxMsgSize -1; + end + end + endcase + end +end + + +// Character to hex number +function [3:0] char2hex; +input [7:0] data_in; +case (data_in) + 8'h30: char2hex = 4'h0; // character '0' + 8'h31: char2hex = 4'h1; // character '1' + 8'h32: char2hex = 4'h2; // character '2' + 8'h33: char2hex = 4'h3; // character '3' + 8'h34: char2hex = 4'h4; // character '4' + 8'h35: char2hex = 4'h5; // character '5' + 8'h36: char2hex = 4'h6; // character '6' + 8'h37: char2hex = 4'h7; // character '7' + 8'h38: char2hex = 4'h8; // character '8' + 8'h39: char2hex = 4'h9; // character '9' + 8'h41: char2hex = 4'hA; // character 'A' + 8'h42: char2hex = 4'hB; // character 'B' + 8'h43: char2hex = 4'hC; // character 'C' + 8'h44: char2hex = 4'hD; // character 'D' + 8'h45: char2hex = 4'hE; // character 'E' + 8'h46: char2hex = 4'hF; // character 'F' + 8'h61: char2hex = 4'hA; // character 'a' + 8'h62: char2hex = 4'hB; // character 'b' + 8'h63: char2hex = 4'hC; // character 'c' + 8'h64: char2hex = 4'hD; // character 'd' + 8'h65: char2hex = 4'hE; // character 'e' + 8'h66: char2hex = 4'hF; // character 'f' + default : char2hex = 4'hF; + endcase +endfunction + +// Hex to Asci Character +function [7:0] hex2char; +input [3:0] data_in; +case (data_in) + 4'h0: hex2char = 8'h30; // character '0' + 4'h1: hex2char = 8'h31; // character '1' + 4'h2: hex2char = 8'h32; // character '2' + 4'h3: hex2char = 8'h33; // character '3' + 4'h4: hex2char = 8'h34; // character '4' + 4'h5: hex2char = 8'h35; // character '5' + 4'h6: hex2char = 8'h36; // character '6' + 4'h7: hex2char = 8'h37; // character '7' + 4'h8: hex2char = 8'h38; // character '8' + 4'h9: hex2char = 8'h39; // character '9' + 4'hA: hex2char = 8'h41; // character 'A' + 4'hB: hex2char = 8'h42; // character 'B' + 4'hC: hex2char = 8'h43; // character 'C' + 4'hD: hex2char = 8'h44; // character 'D' + 4'hE: hex2char = 8'h45; // character 'E' + 4'hF: hex2char = 8'h46; // character 'F' + endcase +endfunction +endmodule diff --git a/designs/encrypted_ip/uart2spi/uart_rxfsm.v b/designs/encrypted_ip/uart2spi/uart_rxfsm.v new file mode 100644 index 000000000..ba113285e --- /dev/null +++ b/designs/encrypted_ip/uart2spi/uart_rxfsm.v @@ -0,0 +1,207 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores UART Interface Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// UART rx state machine + +module uart_rxfsm ( + reset_n , + baud_clk_16x , + + cfg_rx_enable , + cfg_stop_bit , + cfg_pri_mod , + + error_ind , + + // FIFO control signal + fifo_aval , + fifo_wr , + fifo_data , + + // Line Interface + si + ); + + +input reset_n ; // active low reset signal +input baud_clk_16x ; // baud clock-16x + +input cfg_rx_enable ; // transmit interface enable +input cfg_stop_bit ; // stop bit + // 0 --> 1 stop, 1 --> 2 Stop +input [1:0] cfg_pri_mod ;// Priority Mode + // 2'b00 --> None + // 2'b10 --> Even priority + // 2'b11 --> Odd priority + +output [1:0] error_ind ; // 2'b00 --> Normal + // 2'b01 --> framing error + // 2'b10 --> parity error + // 2'b11 --> fifo full +//-------------------------------------- +// FIFO control signal +//-------------------------------------- +input fifo_aval ; // fifo empty +output fifo_wr ; // fifo write, assumed no back to back write +output [7:0] fifo_data ; // fifo write data + +// Line Interface +input si ; // rxd pin + + + +reg [7:0] fifo_data ; // fifo write data +reg fifo_wr ; // fifo write +reg [1:0] error_ind ; +reg [2:0] cnt ; +reg [3:0] offset ; // free-running counter from 0 - 15 +reg [3:0] rxpos ; // stable rx position +reg [2:0] rxstate ; +reg si_d ; // delayed si +reg si_2d ; // 2 cycle delayed si + +parameter idle_st = 3'b000; +parameter xfr_start = 3'b001; +parameter xfr_data_st = 3'b010; +parameter xfr_pri_st = 3'b011; +parameter xfr_stop_st1 = 3'b100; +parameter xfr_stop_st2 = 3'b101; + + +always @(negedge reset_n or posedge baud_clk_16x) begin + if(reset_n == 0) begin + rxstate <= 3'b0; + offset <= 4'b0; + rxpos <= 4'b0; + cnt <= 3'b0; + error_ind <= 2'b0; + fifo_wr <= 1'b0; + fifo_data <= 8'h0; + si_d <= 1'b1; + si_2d <= 1'b1; + end + else begin + // two cycle double sync uart-si to take care of async behaviour + si_d <= si; + si_2d <= si_d; + offset <= offset + 1; + case(rxstate) + idle_st : begin + if(!si_2d) begin // Start indication + if(fifo_aval && cfg_rx_enable) begin + rxstate <= xfr_start; + cnt <= 0; + rxpos <= offset + 8; // Assign center rxoffset + error_ind <= 2'b00; + end + else begin + error_ind <= 2'b11; // fifo full error indication + end + end else begin + error_ind <= 2'b00; // Reset Error + end + end + xfr_start : begin + // Make Sure that minimum 8 cycle low is detected + if(cnt < 7 && si_2d) begin // Start indication + rxstate <= idle_st; + end + else if(cnt == 7 && !si_2d) begin // Start indication + rxstate <= xfr_data_st; + cnt <= 0; + end else begin + cnt <= cnt +1; + end + end + xfr_data_st : begin + if(rxpos == offset) begin + fifo_data[cnt] <= si_2d; + cnt <= cnt+1; + if(cnt == 7) begin + fifo_wr <= 1; + if(cfg_pri_mod == 2'b00) // No Priority + rxstate <= xfr_stop_st1; + else rxstate <= xfr_pri_st; + end + end + end + xfr_pri_st : begin + fifo_wr <= 0; + if(rxpos == offset) begin + if(cfg_pri_mod == 2'b10) // even priority + if( si_2d != ^fifo_data) error_ind <= 2'b10; + else // Odd Priority + if( si_2d != ~(^fifo_data)) error_ind <= 2'b10; + rxstate <= xfr_stop_st1; + end + end + xfr_stop_st1 : begin + fifo_wr <= 0; + if(rxpos == offset) begin + if(si_2d) begin + if(cfg_stop_bit) // Two Stop bit + rxstate <= xfr_stop_st2; + else + rxstate <= idle_st; + end else begin // Framing error + error_ind <= 2'b01; + rxstate <= idle_st; + end + end + end + xfr_stop_st2 : begin + if(rxpos == offset) begin + if(si_2d) begin + rxstate <= idle_st; + end else begin // Framing error + error_ind <= 2'b01; + rxstate <= idle_st; + end + end + end + endcase + end +end + + +endmodule diff --git a/designs/encrypted_ip/uart2spi/uart_txfsm.v b/designs/encrypted_ip/uart2spi/uart_txfsm.v new file mode 100644 index 000000000..4599cd35a --- /dev/null +++ b/designs/encrypted_ip/uart2spi/uart_txfsm.v @@ -0,0 +1,168 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores UART Interface Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +// UART tx state machine + +module uart_txfsm ( + reset_n , + baud_clk_16x , + + cfg_tx_enable , + cfg_stop_bit , + cfg_pri_mod , + + // FIFO control signal + fifo_empty , + fifo_rd , + fifo_data , + + // Line Interface + so + ); + + +input reset_n ; // active low reset signal +input baud_clk_16x ; // baud clock-16x + +input cfg_tx_enable ; // transmit interface enable +input cfg_stop_bit ; // stop bit + // 0 --> 1 stop, 1 --> 2 Stop +input [1:0] cfg_pri_mod ;// Priority Mode + // 2'b00 --> None + // 2'b10 --> Even priority + // 2'b11 --> Odd priority + +//-------------------------------------- +// FIFO control signal +//-------------------------------------- +input fifo_empty ; // fifo empty +output fifo_rd ; // fifo read, assumed no back to back read +input [7:0] fifo_data ; // fifo read data + +// Line Interface +output so ; // txd pin + + +reg [2:0] txstate ; // tx state +reg so ; // txd pin +reg [7:0] txdata ; // local txdata +reg fifo_rd ; // Fifo read enable +reg [2:0] cnt ; // local data cont +reg [3:0] divcnt ; // clock div count + +parameter idle_st = 3'b000; +parameter xfr_data_st = 3'b001; +parameter xfr_pri_st = 3'b010; +parameter xfr_stop_st1 = 3'b011; +parameter xfr_stop_st2 = 3'b100; + + +always @(negedge reset_n or posedge baud_clk_16x) +begin + if(reset_n == 1'b0) begin + txstate <= idle_st; + so <= 1'b1; + cnt <= 3'b0; + txdata <= 8'h0; + fifo_rd <= 1'b0; + divcnt <= 4'b0; + end + else begin + divcnt <= divcnt+1; + if(divcnt == 4'b0000) begin // Do at once in 16 clock + case(txstate) + idle_st : begin + if(!fifo_empty && cfg_tx_enable) begin + so <= 1'b0 ; // Start bit + cnt <= 3'b0; + fifo_rd <= 1'b1; + txdata <= fifo_data; + txstate <= xfr_data_st; + end + end + + xfr_data_st : begin + fifo_rd <= 1'b0; + so <= txdata[cnt]; + cnt <= cnt+1; + if(cnt == 7) begin + if(cfg_pri_mod == 2'b00) begin // No Priority + txstate <= xfr_stop_st1; + end + else begin + txstate <= xfr_pri_st; + end + end + end + + xfr_pri_st : begin + if(cfg_pri_mod == 2'b10) // even priority + so <= ^txdata; + else begin // Odd Priority + so <= ~(^txdata); + end + txstate <= xfr_stop_st1; + end + + xfr_stop_st1 : begin // First Stop Bit + so <= 1; + if(cfg_stop_bit == 0) // 1 Stop Bit + txstate <= idle_st; + else // 2 Stop Bit + txstate <= xfr_stop_st2; + end + + xfr_stop_st2 : begin // Second Stop Bit + so <= 1; + txstate <= idle_st; + end + endcase + end else begin + fifo_rd <= 1'b0; + end + end +end + + +endmodule diff --git a/requirements.txt b/requirements.txt index 8f5917cd3..376b969a8 100644 --- a/requirements.txt +++ b/requirements.txt @@ -15,3 +15,4 @@ scp spydrnet @ git+https://github.com/byuccl/spydrnet@next_release werkzeug boolean.py +pandas \ No newline at end of file From 82102a3c4149747d92e90a98b8786505a719d1cb Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Wed, 13 Dec 2023 09:16:35 -0700 Subject: [PATCH 16/25] add test --- tests/fccm24_encrypted_ip.yaml | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 tests/fccm24_encrypted_ip.yaml diff --git a/tests/fccm24_encrypted_ip.yaml b/tests/fccm24_encrypted_ip.yaml new file mode 100644 index 000000000..2f0aa5c33 --- /dev/null +++ b/tests/fccm24_encrypted_ip.yaml @@ -0,0 +1,4 @@ +flow: EncryptedIP + +design_dirs: + - encrypted_ip/ \ No newline at end of file From 5f7986117611c0c116a56067fde6d03a0a3142ad Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Wed, 13 Dec 2023 09:56:56 -0700 Subject: [PATCH 17/25] fix parsing bug --- bfasst/tools/ip/loader_rules.ninja | 2 +- bfasst/utils/vivado.py | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/bfasst/tools/ip/loader_rules.ninja b/bfasst/tools/ip/loader_rules.ninja index 756b5b667..660001643 100644 --- a/bfasst/tools/ip/loader_rules.ninja +++ b/bfasst/tools/ip/loader_rules.ninja @@ -1,4 +1,4 @@ rule encrypted_ip_bit_patcher command = python3 third_party/encrypted_ip/Project/python_scripts/getLutDataGenPatched2.py $in $out $encypted_ip_yaml_path > $log - description = Patching user bitstream + description = Patching user bitstream $in diff --git a/bfasst/utils/vivado.py b/bfasst/utils/vivado.py index 1c4d92c3f..c924c9408 100644 --- a/bfasst/utils/vivado.py +++ b/bfasst/utils/vivado.py @@ -43,7 +43,11 @@ def parse_hierarchical_utilization(path): elif spaces == prev_spaces: current_path = current_path.parent / cols[0].strip() else: - current_path = current_path.parent.parent / cols[0].strip() + levels_up = (prev_spaces - spaces) // 2 + current_path = current_path.parent + for _ in range(levels_up): + current_path = current_path.parent + current_path /= cols[0].strip() prev_spaces = spaces # Save each column of utilization data From 9eccdca9103adbdd443f923ed32a772b261c04bb Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Wed, 13 Dec 2023 09:57:20 -0700 Subject: [PATCH 18/25] add more ip --- designs/encrypted_ip/des3_perf/ACS.v | 52 ++ designs/encrypted_ip/des3_perf/bmc000.v | 24 + designs/encrypted_ip/des3_perf/bmc001.v | 22 + designs/encrypted_ip/des3_perf/bmc010.v | 23 + designs/encrypted_ip/des3_perf/bmc011.v | 23 + designs/encrypted_ip/des3_perf/bmc100.v | 22 + designs/encrypted_ip/des3_perf/bmc101.v | 22 + designs/encrypted_ip/des3_perf/bmc110.v | 22 + designs/encrypted_ip/des3_perf/bmc111.v | 22 + designs/encrypted_ip/des3_perf/crp.v | 69 ++ designs/encrypted_ip/des3_perf/decoder.v | 563 ++++++++++++ designs/encrypted_ip/des3_perf/des.v | 236 +++++ designs/encrypted_ip/des3_perf/des3_perf.v | 79 ++ designs/encrypted_ip/des3_perf/design.yaml | 9 + designs/encrypted_ip/des3_perf/encoder.v | 151 ++++ designs/encrypted_ip/des3_perf/key_sel.v | 852 ++++++++++++++++++ designs/encrypted_ip/des3_perf/mem_1x1024.v | 25 + designs/encrypted_ip/des3_perf/mem_8x1024.v | 27 + designs/encrypted_ip/des3_perf/sbox1.v | 113 +++ designs/encrypted_ip/des3_perf/sbox2.v | 113 +++ designs/encrypted_ip/des3_perf/sbox3.v | 113 +++ designs/encrypted_ip/des3_perf/sbox4.v | 113 +++ designs/encrypted_ip/des3_perf/sbox5.v | 113 +++ designs/encrypted_ip/des3_perf/sbox6.v | 113 +++ designs/encrypted_ip/des3_perf/sbox7.v | 113 +++ designs/encrypted_ip/des3_perf/sbox8.v | 113 +++ designs/encrypted_ip/des3_perf/tbu.v | 224 +++++ designs/encrypted_ip/des3_perf/top.v | 68 ++ .../encrypted_ip/des3_perf/viterbi_tx_rx.v | 64 ++ .../mul_display/configurable_display.v | 151 ++++ designs/encrypted_ip/mul_display/design.yaml | 12 + designs/encrypted_ip/mul_display/int_mul_8.v | 34 + designs/encrypted_ip/mul_display/top.v | 33 + designs/encrypted_ip/uart2spi/top.v | 32 +- 34 files changed, 3749 insertions(+), 16 deletions(-) create mode 100644 designs/encrypted_ip/des3_perf/ACS.v create mode 100644 designs/encrypted_ip/des3_perf/bmc000.v create mode 100644 designs/encrypted_ip/des3_perf/bmc001.v create mode 100644 designs/encrypted_ip/des3_perf/bmc010.v create mode 100644 designs/encrypted_ip/des3_perf/bmc011.v create mode 100644 designs/encrypted_ip/des3_perf/bmc100.v create mode 100644 designs/encrypted_ip/des3_perf/bmc101.v create mode 100644 designs/encrypted_ip/des3_perf/bmc110.v create mode 100644 designs/encrypted_ip/des3_perf/bmc111.v create mode 100644 designs/encrypted_ip/des3_perf/crp.v create mode 100644 designs/encrypted_ip/des3_perf/decoder.v create mode 100644 designs/encrypted_ip/des3_perf/des.v create mode 100644 designs/encrypted_ip/des3_perf/des3_perf.v create mode 100644 designs/encrypted_ip/des3_perf/design.yaml create mode 100644 designs/encrypted_ip/des3_perf/encoder.v create mode 100644 designs/encrypted_ip/des3_perf/key_sel.v create mode 100644 designs/encrypted_ip/des3_perf/mem_1x1024.v create mode 100644 designs/encrypted_ip/des3_perf/mem_8x1024.v create mode 100644 designs/encrypted_ip/des3_perf/sbox1.v create mode 100644 designs/encrypted_ip/des3_perf/sbox2.v create mode 100644 designs/encrypted_ip/des3_perf/sbox3.v create mode 100644 designs/encrypted_ip/des3_perf/sbox4.v create mode 100644 designs/encrypted_ip/des3_perf/sbox5.v create mode 100644 designs/encrypted_ip/des3_perf/sbox6.v create mode 100644 designs/encrypted_ip/des3_perf/sbox7.v create mode 100644 designs/encrypted_ip/des3_perf/sbox8.v create mode 100644 designs/encrypted_ip/des3_perf/tbu.v create mode 100644 designs/encrypted_ip/des3_perf/top.v create mode 100644 designs/encrypted_ip/des3_perf/viterbi_tx_rx.v create mode 100644 designs/encrypted_ip/mul_display/configurable_display.v create mode 100644 designs/encrypted_ip/mul_display/design.yaml create mode 100644 designs/encrypted_ip/mul_display/int_mul_8.v create mode 100644 designs/encrypted_ip/mul_display/top.v diff --git a/designs/encrypted_ip/des3_perf/ACS.v b/designs/encrypted_ip/des3_perf/ACS.v new file mode 100644 index 000000000..8a8eed82e --- /dev/null +++ b/designs/encrypted_ip/des3_perf/ACS.v @@ -0,0 +1,52 @@ +module ACS +( + path_0_valid, + path_1_valid, + path_0_bmc, + path_1_bmc, + path_0_pmc, + path_1_pmc, + selection, + valid_o, + path_cost +); + input path_0_valid; + input [1:0] path_0_bmc; + input [7:0] path_0_pmc; + + input path_1_valid; + input [1:0] path_1_bmc; + input [7:0] path_1_pmc; + + output reg selection; + output reg valid_o; + output [7:0] path_cost; + + + wire [7:0] path_cost_0; + wire [7:0] path_cost_1; + + assign path_cost_0 = path_0_bmc + path_0_pmc; + assign path_cost_1 = path_1_bmc + path_1_pmc; + + assign path_cost = (valid_o?(selection?path_cost_1:path_cost_0):7'd0); + + + always @ (*) + begin + valid_o = 1'b1; + + case({path_0_valid,path_1_valid}) + 2'b00: + begin + selection = 1'b0; + valid_o = 1'b0; + end + 2'b01: selection = 1'b1; + 2'b10: selection = 1'b0; + 2'b11: selection = (path_cost_0 > path_cost_1)?1'b1:1'b0; + endcase + end + + +endmodule diff --git a/designs/encrypted_ip/des3_perf/bmc000.v b/designs/encrypted_ip/des3_perf/bmc000.v new file mode 100644 index 000000000..bff2a2f1c --- /dev/null +++ b/designs/encrypted_ip/des3_perf/bmc000.v @@ -0,0 +1,24 @@ +module bmc000 +( + rx_pair, + path_0_bmc, + path_1_bmc +); + + + input [1:0] rx_pair; + output [1:0] path_0_bmc; + output [1:0] path_1_bmc; + + + assign tmp00 = (rx_pair[0] ^ 1'b0); + assign tmp01 = (rx_pair[1] ^ 1'b0); + + assign tmp10 = (rx_pair[0] ^ 1'b1); + assign tmp11 = (rx_pair[1] ^ 1'b1); + + assign path_0_bmc = {(tmp00 & tmp01),(tmp00 ^ tmp01)}; + assign path_1_bmc = {(tmp10 & tmp11),(tmp10 ^ tmp11)}; + + +endmodule diff --git a/designs/encrypted_ip/des3_perf/bmc001.v b/designs/encrypted_ip/des3_perf/bmc001.v new file mode 100644 index 000000000..d6a0c51ab --- /dev/null +++ b/designs/encrypted_ip/des3_perf/bmc001.v @@ -0,0 +1,22 @@ +module bmc001 +( + rx_pair, + path_0_bmc, + path_1_bmc +); + + + input [1:0] rx_pair; + output [1:0] path_0_bmc; + output [1:0] path_1_bmc; + + assign tmp00 = (rx_pair[0] ^ 1'b0); + assign tmp01 = (rx_pair[1] ^ 1'b1); + + assign tmp10 = (rx_pair[0] ^ 1'b1); + assign tmp11 = (rx_pair[1] ^ 1'b0); + + assign path_0_bmc = {(tmp00 & tmp01),(tmp00 ^ tmp01)}; + assign path_1_bmc = {(tmp10 & tmp11),(tmp10 ^ tmp11)}; + +endmodule diff --git a/designs/encrypted_ip/des3_perf/bmc010.v b/designs/encrypted_ip/des3_perf/bmc010.v new file mode 100644 index 000000000..a74ee27f7 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/bmc010.v @@ -0,0 +1,23 @@ +module bmc010 +( + rx_pair, + path_0_bmc, + path_1_bmc +); + + + input [1:0] rx_pair; + output [1:0] path_0_bmc; + output [1:0] path_1_bmc; + + assign tmp00 = (rx_pair[0] ^ 1'b0); + assign tmp01 = (rx_pair[1] ^ 1'b1); + + assign tmp10 = (rx_pair[0] ^ 1'b1); + assign tmp11 = (rx_pair[1] ^ 1'b0); + + assign path_0_bmc = {(tmp00 & tmp01),(tmp00 ^ tmp01)}; + assign path_1_bmc = {(tmp10 & tmp11),(tmp10 ^ tmp11)}; + + +endmodule diff --git a/designs/encrypted_ip/des3_perf/bmc011.v b/designs/encrypted_ip/des3_perf/bmc011.v new file mode 100644 index 000000000..e851bc337 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/bmc011.v @@ -0,0 +1,23 @@ +module bmc011 +( + rx_pair, + path_0_bmc, + path_1_bmc +); + + + input [1:0] rx_pair; + output [1:0] path_0_bmc; + output [1:0] path_1_bmc; + + assign tmp00 = (rx_pair[0] ^ 1'b0); + assign tmp01 = (rx_pair[1] ^ 1'b0); + + assign tmp10 = (rx_pair[0] ^ 1'b1); + assign tmp11 = (rx_pair[1] ^ 1'b1); + + assign path_0_bmc = {(tmp00 & tmp01),(tmp00 ^ tmp01)}; + assign path_1_bmc = {(tmp10 & tmp11),(tmp10 ^ tmp11)}; + + +endmodule diff --git a/designs/encrypted_ip/des3_perf/bmc100.v b/designs/encrypted_ip/des3_perf/bmc100.v new file mode 100644 index 000000000..363388bce --- /dev/null +++ b/designs/encrypted_ip/des3_perf/bmc100.v @@ -0,0 +1,22 @@ +module bmc100 +( + rx_pair, + path_0_bmc, + path_1_bmc +); + + + input [1:0] rx_pair; + output [1:0] path_0_bmc; + output [1:0] path_1_bmc; + + assign tmp00 = (rx_pair[0] ^ 1'b0); + assign tmp01 = (rx_pair[1] ^ 1'b0); + + assign tmp10 = (rx_pair[0] ^ 1'b1); + assign tmp11 = (rx_pair[1] ^ 1'b1); + + assign path_0_bmc = {(tmp00 & tmp01),(tmp00 ^ tmp01)}; + assign path_1_bmc = {(tmp10 & tmp11),(tmp10 ^ tmp11)}; + +endmodule diff --git a/designs/encrypted_ip/des3_perf/bmc101.v b/designs/encrypted_ip/des3_perf/bmc101.v new file mode 100644 index 000000000..8f98437d4 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/bmc101.v @@ -0,0 +1,22 @@ +module bmc101 +( + rx_pair, + path_0_bmc, + path_1_bmc +); + + + input [1:0] rx_pair; + output [1:0] path_0_bmc; + output [1:0] path_1_bmc; + + assign tmp00 = (rx_pair[0] ^ 1'b0); + assign tmp01 = (rx_pair[1] ^ 1'b1); + + assign tmp10 = (rx_pair[0] ^ 1'b1); + assign tmp11 = (rx_pair[1] ^ 1'b0); + + assign path_0_bmc = {(tmp00 & tmp01),(tmp00 ^ tmp01)}; + assign path_1_bmc = {(tmp10 & tmp11),(tmp10 ^ tmp11)}; + +endmodule diff --git a/designs/encrypted_ip/des3_perf/bmc110.v b/designs/encrypted_ip/des3_perf/bmc110.v new file mode 100644 index 000000000..06170fda7 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/bmc110.v @@ -0,0 +1,22 @@ +module bmc110 +( + rx_pair, + path_0_bmc, + path_1_bmc +); + + + input [1:0] rx_pair; + output [1:0] path_0_bmc; + output [1:0] path_1_bmc; + + assign tmp00 = (rx_pair[0] ^ 1'b0); + assign tmp01 = (rx_pair[1] ^ 1'b1); + + assign tmp10 = (rx_pair[0] ^ 1'b1); + assign tmp11 = (rx_pair[1] ^ 1'b0); + + assign path_0_bmc = {(tmp00 & tmp01),(tmp00 ^ tmp01)}; + assign path_1_bmc = {(tmp10 & tmp11),(tmp10 ^ tmp11)}; + +endmodule diff --git a/designs/encrypted_ip/des3_perf/bmc111.v b/designs/encrypted_ip/des3_perf/bmc111.v new file mode 100644 index 000000000..79a4547fa --- /dev/null +++ b/designs/encrypted_ip/des3_perf/bmc111.v @@ -0,0 +1,22 @@ +module bmc111 +( + rx_pair, + path_0_bmc, + path_1_bmc +); + + + input [1:0] rx_pair; + output [1:0] path_0_bmc; + output [1:0] path_1_bmc; + + assign tmp00 = (rx_pair[0] ^ 1'b0); + assign tmp01 = (rx_pair[1] ^ 1'b0); + + assign tmp10 = (rx_pair[0] ^ 1'b1); + assign tmp11 = (rx_pair[1] ^ 1'b1); + + assign path_0_bmc = {(tmp00 & tmp01),(tmp00 ^ tmp01)}; + assign path_1_bmc = {(tmp10 & tmp11),(tmp10 ^ tmp11)}; + +endmodule diff --git a/designs/encrypted_ip/des3_perf/crp.v b/designs/encrypted_ip/des3_perf/crp.v new file mode 100644 index 000000000..5985f2f1a --- /dev/null +++ b/designs/encrypted_ip/des3_perf/crp.v @@ -0,0 +1,69 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// CRP //// +//// DES Crypt Module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module crp(P, R, K_sub); +output [1:32] P; +input [1:32] R; +input [1:48] K_sub; + +wire [1:48] E; +wire [1:48] X; +wire [1:32] S; + +assign E[1:48] = { R[32], R[1], R[2], R[3], R[4], R[5], R[4], R[5], + R[6], R[7], R[8], R[9], R[8], R[9], R[10], R[11], + R[12], R[13], R[12], R[13], R[14], R[15], R[16], + R[17], R[16], R[17], R[18], R[19], R[20], R[21], + R[20], R[21], R[22], R[23], R[24], R[25], R[24], + R[25], R[26], R[27], R[28], R[29], R[28], R[29], + R[30], R[31], R[32], R[1]}; + +assign X = E ^ K_sub; + +sbox1 u0( .addr(X[01:06]), .dout(S[01:04]) ); +sbox2 u1( .addr(X[07:12]), .dout(S[05:08]) ); +sbox3 u2( .addr(X[13:18]), .dout(S[09:12]) ); +sbox4 u3( .addr(X[19:24]), .dout(S[13:16]) ); +sbox5 u4( .addr(X[25:30]), .dout(S[17:20]) ); +sbox6 u5( .addr(X[31:36]), .dout(S[21:24]) ); +sbox7 u6( .addr(X[37:42]), .dout(S[25:28]) ); +sbox8 u7( .addr(X[43:48]), .dout(S[29:32]) ); + +assign P[1:32] = { S[16], S[7], S[20], S[21], S[29], S[12], S[28], + S[17], S[1], S[15], S[23], S[26], S[5], S[18], + S[31], S[10], S[2], S[8], S[24], S[14], S[32], + S[27], S[3], S[9], S[19], S[13], S[30], S[6], + S[22], S[11], S[4], S[25]}; + +endmodule diff --git a/designs/encrypted_ip/des3_perf/decoder.v b/designs/encrypted_ip/des3_perf/decoder.v new file mode 100644 index 000000000..b5b15c811 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/decoder.v @@ -0,0 +1,563 @@ +module decoder +( + clk, + rst, + enable, + d_in, + d_out +); + + input clk; + input rst; + input enable; + input [1:0] d_in; + output d_out; + + reg decoder_o_reg; + + +//bmc module signals + wire [1:0] bmc000_path_0_bmc; + wire [1:0] bmc001_path_0_bmc; + wire [1:0] bmc010_path_0_bmc; + wire [1:0] bmc011_path_0_bmc; + wire [1:0] bmc100_path_0_bmc; + wire [1:0] bmc101_path_0_bmc; + wire [1:0] bmc110_path_0_bmc; + wire [1:0] bmc111_path_0_bmc; + + wire [1:0] bmc000_path_1_bmc; + wire [1:0] bmc001_path_1_bmc; + wire [1:0] bmc010_path_1_bmc; + wire [1:0] bmc011_path_1_bmc; + wire [1:0] bmc100_path_1_bmc; + wire [1:0] bmc101_path_1_bmc; + wire [1:0] bmc110_path_1_bmc; + wire [1:0] bmc111_path_1_bmc; + +//ACS modules signals + reg [7:0] validity; + reg [7:0] selection; + reg [7:0] path_cost [7:0]; + wire [7:0] validity_nets; + wire [7:0] selection_nets; + + wire ACS000_selection; + wire ACS001_selection; + wire ACS010_selection; + wire ACS011_selection; + wire ACS100_selection; + wire ACS101_selection; + wire ACS110_selection; + wire ACS111_selection; + + wire ACS000_valid_o; + wire ACS001_valid_o; + wire ACS010_valid_o; + wire ACS011_valid_o; + wire ACS100_valid_o; + wire ACS101_valid_o; + wire ACS110_valid_o; + wire ACS111_valid_o; + + wire [7:0] ACS000_path_cost; + wire [7:0] ACS001_path_cost; + wire [7:0] ACS010_path_cost; + wire [7:0] ACS011_path_cost; + wire [7:0] ACS100_path_cost; + wire [7:0] ACS101_path_cost; + wire [7:0] ACS110_path_cost; + wire [7:0] ACS111_path_cost; + +//Trelis memory write operation + reg [1:0] mem_bank; + reg [1:0] mem_bank_buf; + reg [1:0] mem_bank_buf_buf; + reg mem_bank_buf_buf_buf; + reg mem_bank_buf_buf_buf_buf; + reg mem_bank_buf_buf_buf_buf_buf; + reg [9:0] wr_mem_counter; + reg [9:0] rd_mem_counter; + + reg [9:0] addr_mem_A; + reg [9:0] addr_mem_B; + reg [9:0] addr_mem_C; + reg [9:0] addr_mem_D; + + reg wr_mem_A; + reg wr_mem_B; + reg wr_mem_C; + reg wr_mem_D; + + reg [7:0] d_in_mem_A; + reg [7:0] d_in_mem_B; + reg [7:0] d_in_mem_C; + reg [7:0] d_in_mem_D; + + wire [7:0] d_o_mem_A; + wire [7:0] d_o_mem_B; + wire [7:0] d_o_mem_C; + wire [7:0] d_o_mem_D; + +//Trace back module signals + reg selection_tbu_0; + reg selection_tbu_1; + + reg [7:0] d_in_0_tbu_0; + reg [7:0] d_in_1_tbu_0; + reg [7:0] d_in_0_tbu_1; + reg [7:0] d_in_1_tbu_1; + + wire d_o_tbu_0; + wire d_o_tbu_1; + + reg enable_tbu_0; + reg enable_tbu_1; + +//Display memory operations + wire wr_disp_mem_0; + wire wr_disp_mem_1; + + wire d_in_disp_mem_0; + wire d_in_disp_mem_1; + + reg [9:0] wr_mem_counter_disp; + reg [9:0] rd_mem_counter_disp; + + reg [9:0] addr_disp_mem_0; + reg [9:0] addr_disp_mem_1; + + + assign d_out = decoder_o_reg; + + +//Branch matrc calculation modules + + bmc000 bmc000_inst(d_in,bmc000_path_0_bmc,bmc000_path_1_bmc); + bmc001 bmc001_inst(d_in,bmc001_path_0_bmc,bmc001_path_1_bmc); + bmc010 bmc010_inst(d_in,bmc010_path_0_bmc,bmc010_path_1_bmc); + bmc011 bmc011_inst(d_in,bmc011_path_0_bmc,bmc011_path_1_bmc); + bmc100 bmc100_inst(d_in,bmc100_path_0_bmc,bmc100_path_1_bmc); + bmc101 bmc101_inst(d_in,bmc101_path_0_bmc,bmc101_path_1_bmc); + bmc110 bmc110_inst(d_in,bmc110_path_0_bmc,bmc110_path_1_bmc); + bmc111 bmc111_inst(d_in,bmc111_path_0_bmc,bmc111_path_1_bmc); + + +//Add Compare Select Modules + + ACS ACS000(validity[0],validity[1],bmc000_path_0_bmc,bmc000_path_1_bmc,path_cost[0],path_cost[1],ACS000_selection,ACS000_valid_o,ACS000_path_cost); + ACS ACS001(validity[3],validity[2],bmc001_path_0_bmc,bmc001_path_1_bmc,path_cost[3],path_cost[2],ACS001_selection,ACS001_valid_o,ACS001_path_cost); + ACS ACS010(validity[4],validity[5],bmc010_path_0_bmc,bmc010_path_1_bmc,path_cost[4],path_cost[5],ACS010_selection,ACS010_valid_o,ACS010_path_cost); + ACS ACS011(validity[7],validity[6],bmc011_path_0_bmc,bmc011_path_1_bmc,path_cost[7],path_cost[6],ACS011_selection,ACS011_valid_o,ACS011_path_cost); + ACS ACS100(validity[1],validity[0],bmc100_path_0_bmc,bmc100_path_1_bmc,path_cost[1],path_cost[0],ACS100_selection,ACS100_valid_o,ACS100_path_cost); + ACS ACS101(validity[2],validity[3],bmc101_path_0_bmc,bmc101_path_1_bmc,path_cost[2],path_cost[3],ACS101_selection,ACS101_valid_o,ACS101_path_cost); + ACS ACS110(validity[5],validity[4],bmc110_path_0_bmc,bmc110_path_1_bmc,path_cost[5],path_cost[4],ACS110_selection,ACS110_valid_o,ACS110_path_cost); + ACS ACS111(validity[6],validity[7],bmc111_path_0_bmc,bmc111_path_1_bmc,path_cost[6],path_cost[7],ACS111_selection,ACS111_valid_o,ACS111_path_cost); + + + assign selection_nets = {ACS111_selection,ACS110_selection,ACS101_selection,ACS100_selection, + ACS011_selection,ACS010_selection,ACS001_selection,ACS000_selection}; + assign validity_nets = {ACS111_valid_o,ACS110_valid_o,ACS101_valid_o,ACS100_valid_o, + ACS011_valid_o,ACS010_valid_o,ACS001_valid_o,ACS000_valid_o}; + + + always @ (posedge clk or negedge rst) + begin + if(rst==1'b0) + begin + validity <= 8'b00000001; + selection <= 8'b00000000; + + path_cost[0] <= 8'd0; + path_cost[1] <= 8'd0; + path_cost[2] <= 8'd0; + path_cost[3] <= 8'd0; + path_cost[4] <= 8'd0; + path_cost[5] <= 8'd0; + path_cost[6] <= 8'd0; + path_cost[7] <= 8'd0; + + end + else if(enable==1'b0) + begin + validity <= 8'b00000001; + selection <= 8'b00000000; + + path_cost[0] <= 8'd0; + path_cost[1] <= 8'd0; + path_cost[2] <= 8'd0; + path_cost[3] <= 8'd0; + path_cost[4] <= 8'd0; + path_cost[5] <= 8'd0; + path_cost[6] <= 8'd0; + path_cost[7] <= 8'd0; + + end + else if( path_cost[0][7] && path_cost[1][7] && path_cost[2][7] && path_cost[3][7] && + path_cost[4][7] && path_cost[5][7] && path_cost[6][7] && path_cost[7][7] ) + begin + + validity <= validity_nets; + selection <= selection_nets; + + path_cost[0] <= 8'b01111111 & ACS000_path_cost; + path_cost[1] <= 8'b01111111 & ACS001_path_cost; + path_cost[2] <= 8'b01111111 & ACS010_path_cost; + path_cost[3] <= 8'b01111111 & ACS011_path_cost; + path_cost[4] <= 8'b01111111 & ACS100_path_cost; + path_cost[5] <= 8'b01111111 & ACS101_path_cost; + path_cost[6] <= 8'b01111111 & ACS110_path_cost; + path_cost[7] <= 8'b01111111 & ACS111_path_cost; + end + else + begin + validity <= validity_nets; + selection <= selection_nets; + + path_cost[0] <= ACS000_path_cost; + path_cost[1] <= ACS001_path_cost; + path_cost[2] <= ACS010_path_cost; + path_cost[3] <= ACS011_path_cost; + path_cost[4] <= ACS100_path_cost; + path_cost[5] <= ACS101_path_cost; + path_cost[6] <= ACS110_path_cost; + path_cost[7] <= ACS111_path_cost; + end + end + + + + always @ (posedge clk or negedge rst) + begin + if(rst==1'b0) + wr_mem_counter <= 10'd0; + else if(enable==1'b0) + wr_mem_counter <= 10'd0; + else + wr_mem_counter <= wr_mem_counter + 10'd1; + end + + always @ (posedge clk or negedge rst) + begin + if(rst==1'b0) + rd_mem_counter <= 10'b1111111111; + else if(enable==1'b0) + rd_mem_counter <= 10'd0; + else + rd_mem_counter <= rd_mem_counter - 10'd1; + end + + + always @ (posedge clk or negedge rst) + begin + if(rst==1'b0) + mem_bank <= 2'b00; + else begin + if(wr_mem_counter==10'b1111111111) + mem_bank <= mem_bank + 2'b01; + end + end + + + always @ (posedge clk) + begin + d_in_mem_A <= selection; + d_in_mem_B <= selection; + d_in_mem_C <= selection; + d_in_mem_D <= selection; + + end + + + always @ (posedge clk) + begin + case(mem_bank) + 2'b00: + begin + addr_mem_A <= wr_mem_counter; + addr_mem_B <= rd_mem_counter; + addr_mem_C <= 10'd0; + addr_mem_D <= rd_mem_counter; + + wr_mem_A <= 1'b1; + wr_mem_B <= 1'b0; + wr_mem_C <= 1'b0; + wr_mem_D <= 1'b0; + end + 2'b01: + begin + addr_mem_A <= rd_mem_counter; + addr_mem_B <= wr_mem_counter; + addr_mem_C <= rd_mem_counter; + addr_mem_D <= 10'd0; + + wr_mem_A <= 1'b0; + wr_mem_B <= 1'b1; + wr_mem_C <= 1'b0; + wr_mem_D <= 1'b0; + + end + 2'b10: + begin + addr_mem_A <= 10'd0; + addr_mem_B <= rd_mem_counter; + addr_mem_C <= wr_mem_counter; + addr_mem_D <= rd_mem_counter; + + wr_mem_A <= 1'b0; + wr_mem_B <= 1'b0; + wr_mem_C <= 1'b1; + wr_mem_D <= 1'b0; + end + 2'b11: + begin + addr_mem_A <= rd_mem_counter; + addr_mem_B <= 10'd0; + addr_mem_C <= rd_mem_counter; + addr_mem_D <= wr_mem_counter; + + wr_mem_A <= 1'b0; + wr_mem_B <= 1'b0; + wr_mem_C <= 1'b0; + wr_mem_D <= 1'b1; + end + endcase + end + +//Trelis memory module instantiation + + mem trelis_mem_A + ( + .clk(clk), + .wr(wr_mem_A), + .addr(addr_mem_A), + .d_i(d_in_mem_A), + .d_o(d_o_mem_A) + ); + + mem trelis_mem_B + ( + .clk(clk), + .wr(wr_mem_B), + .addr(addr_mem_B), + .d_i(d_in_mem_B), + .d_o(d_o_mem_B) + ); + + mem trelis_mem_C + ( + .clk(clk), + .wr(wr_mem_C), + .addr(addr_mem_C), + .d_i(d_in_mem_C), + .d_o(d_o_mem_C) + ); + + mem trelis_mem_D + ( + .clk(clk), + .wr(wr_mem_D), + .addr(addr_mem_D), + .d_i(d_in_mem_D), + .d_o(d_o_mem_D) + ); + +//Trace back module operation + + always @(posedge clk) + mem_bank_buf <= mem_bank; + + always @(posedge clk) + mem_bank_buf_buf <= mem_bank_buf; + + + always @ (posedge clk or negedge rst) + begin + if(rst==1'b0) + enable_tbu_0 <= 1'b0; + else begin + if(mem_bank_buf_buf==2'b10) + enable_tbu_0 <= 1'b1; + else + enable_tbu_0 <= enable_tbu_0; + end + end + + always @ (posedge clk or negedge rst) + begin + if(rst==1'b0) + enable_tbu_1 <= 1'b0; + else begin + if(mem_bank_buf_buf==2'b11) + enable_tbu_1 <= 1'b1; + else + enable_tbu_1 <= enable_tbu_1; + end + end + + always @ (posedge clk) + begin + case(mem_bank_buf_buf) + 2'b00: + begin + d_in_0_tbu_0 <= d_o_mem_D; + d_in_1_tbu_0 <= d_o_mem_C; + + d_in_0_tbu_1 <= d_o_mem_C; + d_in_1_tbu_1 <= d_o_mem_B; + + selection_tbu_0<= 1'b0; + selection_tbu_1<= 1'b1; + + end + 2'b01: + begin + d_in_0_tbu_0 <= d_o_mem_D; + d_in_1_tbu_0 <= d_o_mem_C; + + d_in_0_tbu_1 <= d_o_mem_A; + d_in_1_tbu_1 <= d_o_mem_D; + + selection_tbu_0<= 1'b1; + selection_tbu_1<= 1'b0; + end + 2'b10: + begin + d_in_0_tbu_0 <= d_o_mem_B; + d_in_1_tbu_0 <= d_o_mem_A; + + d_in_0_tbu_1 <= d_o_mem_A; + d_in_1_tbu_1 <= d_o_mem_D; + + selection_tbu_0<= 1'b0; + selection_tbu_1<= 1'b1; + end + 2'b11: + begin + d_in_0_tbu_0 <= d_o_mem_B; + d_in_1_tbu_0 <= d_o_mem_A; + + d_in_0_tbu_1 <= d_o_mem_C; + d_in_1_tbu_1 <= d_o_mem_B; + + selection_tbu_0<= 1'b1; + selection_tbu_1<= 1'b0; + end + endcase + end + +//Trace-Back modules instantiation + + tbu tbu_0 + ( + .clk(clk), + .rst(rst), + .enable(enable_tbu_0), + .selection(selection_tbu_0), + .d_in_0(d_in_0_tbu_0), + .d_in_1(d_in_1_tbu_0), + .d_o(d_o_tbu_0), + .wr_en(wr_disp_mem_0) + ); + + tbu tbu_1 + ( + .clk(clk), + .rst(rst), + .enable(enable_tbu_1), + .selection(selection_tbu_1), + .d_in_0(d_in_0_tbu_1), + .d_in_1(d_in_1_tbu_1), + .d_o(d_o_tbu_1), + .wr_en(wr_disp_mem_1) + ); + +//Display Memory modules Instantioation + + assign d_in_disp_mem_0 = d_o_tbu_0; + assign d_in_disp_mem_1 = d_o_tbu_1; + + + mem_disp disp_mem_0 + ( + .clk(clk), + .wr(wr_disp_mem_0), + .addr(addr_disp_mem_0), + .d_i(d_in_disp_mem_0), + .d_o(d_o_disp_mem_0) + ); + + mem_disp disp_mem_1 + ( + .clk(clk), + .wr(wr_disp_mem_1), + .addr(addr_disp_mem_1), + .d_i(d_in_disp_mem_1), + .d_o(d_o_disp_mem_1) + ); + +// Display memory module operation + always @ (posedge clk) + mem_bank_buf_buf_buf <= mem_bank_buf_buf[0]; + + always @ (posedge clk) + begin + if(rst==1'b0) + wr_mem_counter_disp <= 10'b0000000010; + if(enable==1'b0) + wr_mem_counter_disp <= 10'b0000000010; + else + wr_mem_counter_disp <= wr_mem_counter_disp - 10'd1; + end + + always @ (posedge clk) + begin + if(rst==1'b0) + rd_mem_counter_disp <= 10'b1111111101; + if(enable==1'b0) + rd_mem_counter_disp <= 10'b1111111101; + else + rd_mem_counter_disp <= rd_mem_counter_disp + 10'd1; + end + + + always @ (posedge clk) + begin + case(mem_bank_buf_buf_buf) + 1'b0: + begin + addr_disp_mem_0 <= rd_mem_counter_disp; + addr_disp_mem_1 <= wr_mem_counter_disp; + end + 1'b1: + begin + addr_disp_mem_0 <= wr_mem_counter_disp; + addr_disp_mem_1 <= rd_mem_counter_disp; + end + endcase + end + + + always @ (posedge clk) + mem_bank_buf_buf_buf_buf <= mem_bank_buf_buf_buf; + + always @ (posedge clk) + mem_bank_buf_buf_buf_buf_buf <= mem_bank_buf_buf_buf_buf; + + + + always @ (posedge clk) + begin + case(mem_bank_buf_buf_buf_buf_buf) + 1'b0: + begin + decoder_o_reg <= d_o_disp_mem_0; + end + 1'b1: + begin + decoder_o_reg <= d_o_disp_mem_1; + end + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_perf/des.v b/designs/encrypted_ip/des3_perf/des.v new file mode 100644 index 000000000..151f83863 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/des.v @@ -0,0 +1,236 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// DES //// +//// DES Top Level module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module des(desOut, desIn, key, decrypt, clk); +output [63:0] desOut; +input [63:0] desIn; +input [55:0] key; +input decrypt; +input clk; + +wire [1:64] IP, FP; +reg [63:0] desIn_r; +reg [55:0] key_r; +reg [63:0] desOut; +reg [1:32] L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15; +reg [1:32] R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15; +wire [1:32] out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15; +wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9; +wire [1:48] K10, K11, K12, K13, K14, K15, K16; + +// Register the 56 bit key +always @(posedge clk) + key_r <= #1 key; + +// Register the 64 bit input +always @(posedge clk) + desIn_r <= #1 desIn; + +// XOR 32 bit out15 with 32 bit L14 ( FP 1:32 ) +// then concatinate the 32 bit R14 value ( FP 33:64 ) +// This value ( FP 1:64 ) is then registered by the desOut[63:0] register +assign FP = { (out15 ^ L14), R14}; + +// Key schedule provides a linear means of intermixing the 56 bit key to form a +// different 48 bit key for each of the 16 bit rounds +key_sel uk( + .clk( clk ), + .K( key_r ), + .decrypt( decrypt ), + .K1( K1 ), + .K2( K2 ), + .K3( K3 ), + .K4( K4 ), + .K5( K5 ), + .K6( K6 ), + .K7( K7 ), + .K8( K8 ), + .K9( K9 ), + .K10( K10 ), + .K11( K11 ), + .K12( K12 ), + .K13( K13 ), + .K14( K14 ), + .K15( K15 ), + .K16( K16 ) + ); + +// 16 CRP blocks +crp u0( .P(out0), .R(IP[33:64]), .K_sub(K1) ); +crp u1( .P(out1), .R(R0), .K_sub(K2) ); +crp u2( .P(out2), .R(R1), .K_sub(K3) ); +crp u3( .P(out3), .R(R2), .K_sub(K4) ); +crp u4( .P(out4), .R(R3), .K_sub(K5) ); +crp u5( .P(out5), .R(R4), .K_sub(K6) ); +crp u6( .P(out6), .R(R5), .K_sub(K7) ); +crp u7( .P(out7), .R(R6), .K_sub(K8) ); +crp u8( .P(out8), .R(R7), .K_sub(K9) ); +crp u9( .P(out9), .R(R8), .K_sub(K10) ); +crp u10( .P(out10), .R(R9), .K_sub(K11) ); +crp u11( .P(out11), .R(R10), .K_sub(K12) ); +crp u12( .P(out12), .R(R11), .K_sub(K13) ); +crp u13( .P(out13), .R(R12), .K_sub(K14) ); +crp u14( .P(out14), .R(R13), .K_sub(K15) ); +crp u15( .P(out15), .R(R14), .K_sub(K16) ); + +// 32 bit L0 get upper 32 bits of IP +always @(posedge clk) + L0 <= #1 IP[33:64]; + +// 32 bit R0 gets lower 32 bits of IP XOR'd with 32 bit out0 +always @(posedge clk) + R0 <= #1 IP[01:32] ^ out0; + +// 32 bit L1 gets 32 bit R0 +always @(posedge clk) + L1 <= #1 R0; + +// 32 bit R1 gets 32 bit L0 XOR'd with 32 bit out1 +always @(posedge clk) + R1 <= #1 L0 ^ out1; + +// 32 bit L2 gets 32 bit R1 +always @(posedge clk) + L2 <= #1 R1; + +// 32 bit R2 gets 32 bit L1 XOR'd with 32 bit out2 +always @(posedge clk) + R2 <= #1 L1 ^ out2; + +always @(posedge clk) + L3 <= #1 R2; + +always @(posedge clk) + R3 <= #1 L2 ^ out3; + +always @(posedge clk) + L4 <= #1 R3; + +always @(posedge clk) + R4 <= #1 L3 ^ out4; + +always @(posedge clk) + L5 <= #1 R4; + +always @(posedge clk) + R5 <= #1 L4 ^ out5; + +always @(posedge clk) + L6 <= #1 R5; + +always @(posedge clk) + R6 <= #1 L5 ^ out6; + +always @(posedge clk) + L7 <= #1 R6; + +always @(posedge clk) + R7 <= #1 L6 ^ out7; + +always @(posedge clk) + L8 <= #1 R7; + +always @(posedge clk) + R8 <= #1 L7 ^ out8; + +always @(posedge clk) + L9 <= #1 R8; + +always @(posedge clk) + R9 <= #1 L8 ^ out9; + +always @(posedge clk) + L10 <= #1 R9; + +always @(posedge clk) + R10 <= #1 L9 ^ out10; + +always @(posedge clk) + L11 <= #1 R10; + +always @(posedge clk) + R11 <= #1 L10 ^ out11; + +always @(posedge clk) + L12 <= #1 R11; + +always @(posedge clk) + R12 <= #1 L11 ^ out12; + +always @(posedge clk) + L13 <= #1 R12; + +always @(posedge clk) + R13 <= #1 L12 ^ out13; + +always @(posedge clk) + L14 <= #1 R13; + +always @(posedge clk) + R14 <= #1 L13 ^ out14; + +// 32 bit L15 gets 32 bit R14 +always @(posedge clk) + L15 <= #1 R14; + +// 32 bit R15 gets 32 bit L14 XOR'd with 32 bit out15 +always @(posedge clk) + R15 <= #1 L14 ^ out15; + +// Perform the initial permutationi with the registerd desIn +assign IP[1:64] = { desIn_r[06], desIn_r[14], desIn_r[22], desIn_r[30], desIn_r[38], desIn_r[46], + desIn_r[54], desIn_r[62], desIn_r[04], desIn_r[12], desIn_r[20], desIn_r[28], + desIn_r[36], desIn_r[44], desIn_r[52], desIn_r[60], desIn_r[02], desIn_r[10], + desIn_r[18], desIn_r[26], desIn_r[34], desIn_r[42], desIn_r[50], desIn_r[58], + desIn_r[00], desIn_r[08], desIn_r[16], desIn_r[24], desIn_r[32], desIn_r[40], + desIn_r[48], desIn_r[56], desIn_r[07], desIn_r[15], desIn_r[23], desIn_r[31], + desIn_r[39], desIn_r[47], desIn_r[55], desIn_r[63], desIn_r[05], desIn_r[13], + desIn_r[21], desIn_r[29], desIn_r[37], desIn_r[45], desIn_r[53], desIn_r[61], + desIn_r[03], desIn_r[11], desIn_r[19], desIn_r[27], desIn_r[35], desIn_r[43], + desIn_r[51], desIn_r[59], desIn_r[01], desIn_r[09], desIn_r[17], desIn_r[25], + desIn_r[33], desIn_r[41], desIn_r[49], desIn_r[57] }; + +// Perform the final permutation +always @(posedge clk) + desOut <= #1 { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32], + FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31], + FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30], + FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29], + FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28], + FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27], + FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26], + FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] }; + + +endmodule diff --git a/designs/encrypted_ip/des3_perf/des3_perf.v b/designs/encrypted_ip/des3_perf/des3_perf.v new file mode 100644 index 000000000..e843f34c2 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/des3_perf.v @@ -0,0 +1,79 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Tripple DES //// +//// Tripple DES Top Level module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module des3_perf(desOut, desIn, key1, key2, key3, decrypt, clk); +output [63:0] desOut; +input [63:0] desIn; +input [55:0] key1; +input [55:0] key2; +input [55:0] key3; +input decrypt; +input clk; + +wire [55:0] key_a; +wire [55:0] key_b; +wire [55:0] key_c; +wire [63:0] stage1_out, stage2_out; +reg [55:0] key_b_r [16:0]; +reg [55:0] key_c_r [33:0]; +integer i; + +assign key_a = decrypt ? key3 : key1; +assign key_b = key2; +assign key_c = decrypt ? key1 : key3; + +always @(posedge clk) + key_b_r[0] <= #1 key_b; + +always @(posedge clk) + for(i=0;i<16;i=i+1) + key_b_r[i+1] <= #1 key_b_r[i]; + + +always @(posedge clk) + key_c_r[0] <= #1 key_c; + +always @(posedge clk) + for(i=0;i<33;i=i+1) + key_c_r[i+1] <= #1 key_c_r[i]; + +des u0( .desOut(stage1_out), .desIn(desIn), .key(key_a), .decrypt(decrypt), .clk(clk) ); + +des u1( .desOut(stage2_out), .desIn(stage1_out), .key(key_b_r[16]), .decrypt(!decrypt), .clk(clk) ); + +des u2( .desOut(desOut), .desIn(stage2_out), .key(key_c_r[33]), .decrypt(decrypt), .clk(clk) ); + +endmodule + + diff --git a/designs/encrypted_ip/des3_perf/design.yaml b/designs/encrypted_ip/des3_perf/design.yaml new file mode 100644 index 000000000..d998fb7f8 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/design.yaml @@ -0,0 +1,9 @@ +top: top + +encrypted_ip: + ip: + - definition: "des3_perf" + instances: + - "des3_perf_0" + + user_files: ["top.v"] \ No newline at end of file diff --git a/designs/encrypted_ip/des3_perf/encoder.v b/designs/encrypted_ip/des3_perf/encoder.v new file mode 100644 index 000000000..f6d345106 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/encoder.v @@ -0,0 +1,151 @@ +module encoder +( + clk, + rst, + enable_i, + d_in, + valid_o, + d_out +); + input clk; + input rst; + input enable_i; + input d_in; + output reg valid_o; + output [1:0] d_out; + + reg [2:0] cstate; + reg [2:0] nstate; + + reg [1:0] d_out_reg; + + assign d_out = (enable_i==1'b1)?d_out_reg:2'b00; + + + always @(*) begin + valid_o = enable_i; + case (cstate) + 3'b000: + begin + if(d_in==1'b0) + begin + nstate = 3'b000; + d_out_reg = 2'b00; + end + else + begin + nstate = 3'b100; + d_out_reg = 2'b11; + end + end + 3'b001: + begin + if(d_in==1'b0) + begin + nstate = 3'b100; + d_out_reg = 2'b00; + end + else + begin + nstate = 3'b000; + d_out_reg = 2'b11; + end + end + 3'b010: + begin + if(d_in==1'b0) + begin + nstate = 3'b101; + d_out_reg = 2'b10; + end + else + begin + nstate = 3'b001; + d_out_reg = 2'b01; + end + end + 3'b011: + begin + if(d_in==1'b0) + begin + nstate = 3'b001; + d_out_reg = 2'b10; + end + else + begin + nstate = 3'b101; + d_out_reg = 2'b01; + end + end + 3'b100: + begin + if(d_in==1'b0) + begin + nstate = 3'b010; + d_out_reg = 2'b10; + end + else + begin + nstate = 3'b110; + d_out_reg = 2'b01; + end + end + 3'b101: + begin + if(d_in==1'b0) + begin + nstate = 3'b110; + d_out_reg = 2'b10; + end + else + begin + nstate = 3'b010; + d_out_reg = 2'b01; + end + end + 3'b110: + begin + if(d_in==1'b0) + begin + nstate = 3'b111; + d_out_reg = 2'b00; + end + else + begin + nstate = 3'b011; + d_out_reg = 2'b11; + end + end + 3'b111: + begin + if(d_in==1'b0) + begin + nstate = 3'b011; + d_out_reg = 2'b00; + end + else + begin + nstate = 3'b111; + d_out_reg = 2'b11; + end + end + + endcase + end + + + + always @ (posedge clk,negedge rst) + begin +// $display("data in=%d state=%b%b%b data out=%b%b",d_in,reg_1,reg_2,reg_3,d_out_reg[1],d_out_reg[0]); + if(rst==1'b0) + cstate <= 3'b000; + else if(enable_i==1'b0) + cstate <= 3'b000; + else + cstate <= nstate; + end + + + +endmodule diff --git a/designs/encrypted_ip/des3_perf/key_sel.v b/designs/encrypted_ip/des3_perf/key_sel.v new file mode 100644 index 000000000..c5598d61d --- /dev/null +++ b/designs/encrypted_ip/des3_perf/key_sel.v @@ -0,0 +1,852 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// KEY_SEL //// +//// Generate 16 pipelined sub-keys //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +module key_sel(clk, K, decrypt, K1, K2, K3, K4, K5, K6, K7, K8, K9, + K10, K11, K12, K13, K14, K15, K16); +input clk; +input [55:0] K; +input decrypt; +output [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9; +output [1:48] K10, K11, K12, K13, K14, K15, K16; + +wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9; +wire [1:48] K10, K11, K12, K13, K14, K15, K16; +reg [55:0] K_r0, K_r1, K_r2, K_r3, K_r4, K_r5, K_r6, K_r7; +reg [55:0] K_r8, K_r9, K_r10, K_r11, K_r12, K_r13, K_r14; + +always @(posedge clk) + begin + K_r0 <= #1 K; + K_r1 <= #1 K_r0; + K_r2 <= #1 K_r1; + K_r3 <= #1 K_r2; + K_r4 <= #1 K_r3; + K_r5 <= #1 K_r4; + K_r6 <= #1 K_r5; + K_r7 <= #1 K_r6; + K_r8 <= #1 K_r7; + K_r9 <= #1 K_r8; + K_r10 <= #1 K_r9; + K_r11 <= #1 K_r10; + K_r12 <= #1 K_r11; + K_r13 <= #1 K_r12; + K_r14 <= #1 K_r13; + end + +assign K16[1] = decrypt ? K_r14[47] : K_r14[40]; +assign K16[2] = decrypt ? K_r14[11] : K_r14[4]; +assign K16[3] = decrypt ? K_r14[26] : K_r14[19]; +assign K16[4] = decrypt ? K_r14[3] : K_r14[53]; +assign K16[5] = decrypt ? K_r14[13] : K_r14[6]; +assign K16[6] = decrypt ? K_r14[41] : K_r14[34]; +assign K16[7] = decrypt ? K_r14[27] : K_r14[20]; +assign K16[8] = decrypt ? K_r14[6] : K_r14[24]; +assign K16[9] = decrypt ? K_r14[54] : K_r14[47]; +assign K16[10] = decrypt ? K_r14[48] : K_r14[41]; +assign K16[11] = decrypt ? K_r14[39] : K_r14[32]; +assign K16[12] = decrypt ? K_r14[19] : K_r14[12]; +assign K16[13] = decrypt ? K_r14[53] : K_r14[46]; +assign K16[14] = decrypt ? K_r14[25] : K_r14[18]; +assign K16[15] = decrypt ? K_r14[33] : K_r14[26]; +assign K16[16] = decrypt ? K_r14[34] : K_r14[27]; +assign K16[17] = decrypt ? K_r14[17] : K_r14[10]; +assign K16[18] = decrypt ? K_r14[5] : K_r14[55]; +assign K16[19] = decrypt ? K_r14[4] : K_r14[54]; +assign K16[20] = decrypt ? K_r14[55] : K_r14[48]; +assign K16[21] = decrypt ? K_r14[24] : K_r14[17]; +assign K16[22] = decrypt ? K_r14[32] : K_r14[25]; +assign K16[23] = decrypt ? K_r14[40] : K_r14[33]; +assign K16[24] = decrypt ? K_r14[20] : K_r14[13]; +assign K16[25] = decrypt ? K_r14[36] : K_r14[29]; +assign K16[26] = decrypt ? K_r14[31] : K_r14[51]; +assign K16[27] = decrypt ? K_r14[21] : K_r14[14]; +assign K16[28] = decrypt ? K_r14[8] : K_r14[1]; +assign K16[29] = decrypt ? K_r14[23] : K_r14[16]; +assign K16[30] = decrypt ? K_r14[52] : K_r14[45]; +assign K16[31] = decrypt ? K_r14[14] : K_r14[7]; +assign K16[32] = decrypt ? K_r14[29] : K_r14[22]; +assign K16[33] = decrypt ? K_r14[51] : K_r14[44]; +assign K16[34] = decrypt ? K_r14[9] : K_r14[2]; +assign K16[35] = decrypt ? K_r14[35] : K_r14[28]; +assign K16[36] = decrypt ? K_r14[30] : K_r14[23]; +assign K16[37] = decrypt ? K_r14[2] : K_r14[50]; +assign K16[38] = decrypt ? K_r14[37] : K_r14[30]; +assign K16[39] = decrypt ? K_r14[22] : K_r14[15]; +assign K16[40] = decrypt ? K_r14[0] : K_r14[52]; +assign K16[41] = decrypt ? K_r14[42] : K_r14[35]; +assign K16[42] = decrypt ? K_r14[38] : K_r14[31]; +assign K16[43] = decrypt ? K_r14[16] : K_r14[9]; +assign K16[44] = decrypt ? K_r14[43] : K_r14[36]; +assign K16[45] = decrypt ? K_r14[44] : K_r14[37]; +assign K16[46] = decrypt ? K_r14[1] : K_r14[49]; +assign K16[47] = decrypt ? K_r14[7] : K_r14[0]; +assign K16[48] = decrypt ? K_r14[28] : K_r14[21]; + +assign K15[1] = decrypt ? K_r13[54] : K_r13[33]; +assign K15[2] = decrypt ? K_r13[18] : K_r13[54]; +assign K15[3] = decrypt ? K_r13[33] : K_r13[12]; +assign K15[4] = decrypt ? K_r13[10] : K_r13[46]; +assign K15[5] = decrypt ? K_r13[20] : K_r13[24]; +assign K15[6] = decrypt ? K_r13[48] : K_r13[27]; +assign K15[7] = decrypt ? K_r13[34] : K_r13[13]; +assign K15[8] = decrypt ? K_r13[13] : K_r13[17]; +assign K15[9] = decrypt ? K_r13[4] : K_r13[40]; +assign K15[10] = decrypt ? K_r13[55] : K_r13[34]; +assign K15[11] = decrypt ? K_r13[46] : K_r13[25]; +assign K15[12] = decrypt ? K_r13[26] : K_r13[5]; +assign K15[13] = decrypt ? K_r13[3] : K_r13[39]; +assign K15[14] = decrypt ? K_r13[32] : K_r13[11]; +assign K15[15] = decrypt ? K_r13[40] : K_r13[19]; +assign K15[16] = decrypt ? K_r13[41] : K_r13[20]; +assign K15[17] = decrypt ? K_r13[24] : K_r13[3]; +assign K15[18] = decrypt ? K_r13[12] : K_r13[48]; +assign K15[19] = decrypt ? K_r13[11] : K_r13[47]; +assign K15[20] = decrypt ? K_r13[5] : K_r13[41]; +assign K15[21] = decrypt ? K_r13[6] : K_r13[10]; +assign K15[22] = decrypt ? K_r13[39] : K_r13[18]; +assign K15[23] = decrypt ? K_r13[47] : K_r13[26]; +assign K15[24] = decrypt ? K_r13[27] : K_r13[6]; +assign K15[25] = decrypt ? K_r13[43] : K_r13[22]; +assign K15[26] = decrypt ? K_r13[38] : K_r13[44]; +assign K15[27] = decrypt ? K_r13[28] : K_r13[7]; +assign K15[28] = decrypt ? K_r13[15] : K_r13[49]; +assign K15[29] = decrypt ? K_r13[30] : K_r13[9]; +assign K15[30] = decrypt ? K_r13[0] : K_r13[38]; +assign K15[31] = decrypt ? K_r13[21] : K_r13[0]; +assign K15[32] = decrypt ? K_r13[36] : K_r13[15]; +assign K15[33] = decrypt ? K_r13[31] : K_r13[37]; +assign K15[34] = decrypt ? K_r13[16] : K_r13[50]; +assign K15[35] = decrypt ? K_r13[42] : K_r13[21]; +assign K15[36] = decrypt ? K_r13[37] : K_r13[16]; +assign K15[37] = decrypt ? K_r13[9] : K_r13[43]; +assign K15[38] = decrypt ? K_r13[44] : K_r13[23]; +assign K15[39] = decrypt ? K_r13[29] : K_r13[8]; +assign K15[40] = decrypt ? K_r13[7] : K_r13[45]; +assign K15[41] = decrypt ? K_r13[49] : K_r13[28]; +assign K15[42] = decrypt ? K_r13[45] : K_r13[51]; +assign K15[43] = decrypt ? K_r13[23] : K_r13[2]; +assign K15[44] = decrypt ? K_r13[50] : K_r13[29]; +assign K15[45] = decrypt ? K_r13[51] : K_r13[30]; +assign K15[46] = decrypt ? K_r13[8] : K_r13[42]; +assign K15[47] = decrypt ? K_r13[14] : K_r13[52]; +assign K15[48] = decrypt ? K_r13[35] : K_r13[14]; + +assign K14[1] = decrypt ? K_r12[11] : K_r12[19]; +assign K14[2] = decrypt ? K_r12[32] : K_r12[40]; +assign K14[3] = decrypt ? K_r12[47] : K_r12[55]; +assign K14[4] = decrypt ? K_r12[24] : K_r12[32]; +assign K14[5] = decrypt ? K_r12[34] : K_r12[10]; +assign K14[6] = decrypt ? K_r12[5] : K_r12[13]; +assign K14[7] = decrypt ? K_r12[48] : K_r12[24]; +assign K14[8] = decrypt ? K_r12[27] : K_r12[3]; +assign K14[9] = decrypt ? K_r12[18] : K_r12[26]; +assign K14[10] = decrypt ? K_r12[12] : K_r12[20]; +assign K14[11] = decrypt ? K_r12[3] : K_r12[11]; +assign K14[12] = decrypt ? K_r12[40] : K_r12[48]; +assign K14[13] = decrypt ? K_r12[17] : K_r12[25]; +assign K14[14] = decrypt ? K_r12[46] : K_r12[54]; +assign K14[15] = decrypt ? K_r12[54] : K_r12[5]; +assign K14[16] = decrypt ? K_r12[55] : K_r12[6]; +assign K14[17] = decrypt ? K_r12[13] : K_r12[46]; +assign K14[18] = decrypt ? K_r12[26] : K_r12[34]; +assign K14[19] = decrypt ? K_r12[25] : K_r12[33]; +assign K14[20] = decrypt ? K_r12[19] : K_r12[27]; +assign K14[21] = decrypt ? K_r12[20] : K_r12[53]; +assign K14[22] = decrypt ? K_r12[53] : K_r12[4]; +assign K14[23] = decrypt ? K_r12[4] : K_r12[12]; +assign K14[24] = decrypt ? K_r12[41] : K_r12[17]; +assign K14[25] = decrypt ? K_r12[2] : K_r12[8]; +assign K14[26] = decrypt ? K_r12[52] : K_r12[30]; +assign K14[27] = decrypt ? K_r12[42] : K_r12[52]; +assign K14[28] = decrypt ? K_r12[29] : K_r12[35]; +assign K14[29] = decrypt ? K_r12[44] : K_r12[50]; +assign K14[30] = decrypt ? K_r12[14] : K_r12[51]; +assign K14[31] = decrypt ? K_r12[35] : K_r12[45]; +assign K14[32] = decrypt ? K_r12[50] : K_r12[1]; +assign K14[33] = decrypt ? K_r12[45] : K_r12[23]; +assign K14[34] = decrypt ? K_r12[30] : K_r12[36]; +assign K14[35] = decrypt ? K_r12[1] : K_r12[7]; +assign K14[36] = decrypt ? K_r12[51] : K_r12[2]; +assign K14[37] = decrypt ? K_r12[23] : K_r12[29]; +assign K14[38] = decrypt ? K_r12[31] : K_r12[9]; +assign K14[39] = decrypt ? K_r12[43] : K_r12[49]; +assign K14[40] = decrypt ? K_r12[21] : K_r12[31]; +assign K14[41] = decrypt ? K_r12[8] : K_r12[14]; +assign K14[42] = decrypt ? K_r12[0] : K_r12[37]; +assign K14[43] = decrypt ? K_r12[37] : K_r12[43]; +assign K14[44] = decrypt ? K_r12[9] : K_r12[15]; +assign K14[45] = decrypt ? K_r12[38] : K_r12[16]; +assign K14[46] = decrypt ? K_r12[22] : K_r12[28]; +assign K14[47] = decrypt ? K_r12[28] : K_r12[38]; +assign K14[48] = decrypt ? K_r12[49] : K_r12[0]; + +assign K13[1] = decrypt ? K_r11[25] : K_r11[5]; +assign K13[2] = decrypt ? K_r11[46] : K_r11[26]; +assign K13[3] = decrypt ? K_r11[4] : K_r11[41]; +assign K13[4] = decrypt ? K_r11[13] : K_r11[18]; +assign K13[5] = decrypt ? K_r11[48] : K_r11[53]; +assign K13[6] = decrypt ? K_r11[19] : K_r11[24]; +assign K13[7] = decrypt ? K_r11[5] : K_r11[10]; +assign K13[8] = decrypt ? K_r11[41] : K_r11[46]; +assign K13[9] = decrypt ? K_r11[32] : K_r11[12]; +assign K13[10] = decrypt ? K_r11[26] : K_r11[6]; +assign K13[11] = decrypt ? K_r11[17] : K_r11[54]; +assign K13[12] = decrypt ? K_r11[54] : K_r11[34]; +assign K13[13] = decrypt ? K_r11[6] : K_r11[11]; +assign K13[14] = decrypt ? K_r11[3] : K_r11[40]; +assign K13[15] = decrypt ? K_r11[11] : K_r11[48]; +assign K13[16] = decrypt ? K_r11[12] : K_r11[17]; +assign K13[17] = decrypt ? K_r11[27] : K_r11[32]; +assign K13[18] = decrypt ? K_r11[40] : K_r11[20]; +assign K13[19] = decrypt ? K_r11[39] : K_r11[19]; +assign K13[20] = decrypt ? K_r11[33] : K_r11[13]; +assign K13[21] = decrypt ? K_r11[34] : K_r11[39]; +assign K13[22] = decrypt ? K_r11[10] : K_r11[47]; +assign K13[23] = decrypt ? K_r11[18] : K_r11[55]; +assign K13[24] = decrypt ? K_r11[55] : K_r11[3]; +assign K13[25] = decrypt ? K_r11[16] : K_r11[49]; +assign K13[26] = decrypt ? K_r11[7] : K_r11[16]; +assign K13[27] = decrypt ? K_r11[1] : K_r11[38]; +assign K13[28] = decrypt ? K_r11[43] : K_r11[21]; +assign K13[29] = decrypt ? K_r11[31] : K_r11[36]; +assign K13[30] = decrypt ? K_r11[28] : K_r11[37]; +assign K13[31] = decrypt ? K_r11[49] : K_r11[31]; +assign K13[32] = decrypt ? K_r11[9] : K_r11[42]; +assign K13[33] = decrypt ? K_r11[0] : K_r11[9]; +assign K13[34] = decrypt ? K_r11[44] : K_r11[22]; +assign K13[35] = decrypt ? K_r11[15] : K_r11[52]; +assign K13[36] = decrypt ? K_r11[38] : K_r11[43]; +assign K13[37] = decrypt ? K_r11[37] : K_r11[15]; +assign K13[38] = decrypt ? K_r11[45] : K_r11[50]; +assign K13[39] = decrypt ? K_r11[2] : K_r11[35]; +assign K13[40] = decrypt ? K_r11[35] : K_r11[44]; +assign K13[41] = decrypt ? K_r11[22] : K_r11[0]; +assign K13[42] = decrypt ? K_r11[14] : K_r11[23]; +assign K13[43] = decrypt ? K_r11[51] : K_r11[29]; +assign K13[44] = decrypt ? K_r11[23] : K_r11[1]; +assign K13[45] = decrypt ? K_r11[52] : K_r11[2]; +assign K13[46] = decrypt ? K_r11[36] : K_r11[14]; +assign K13[47] = decrypt ? K_r11[42] : K_r11[51]; +assign K13[48] = decrypt ? K_r11[8] : K_r11[45]; + +assign K12[1] = decrypt ? K_r10[39] : K_r10[48]; +assign K12[2] = decrypt ? K_r10[3] : K_r10[12]; +assign K12[3] = decrypt ? K_r10[18] : K_r10[27]; +assign K12[4] = decrypt ? K_r10[27] : K_r10[4]; +assign K12[5] = decrypt ? K_r10[5] : K_r10[39]; +assign K12[6] = decrypt ? K_r10[33] : K_r10[10]; +assign K12[7] = decrypt ? K_r10[19] : K_r10[53]; +assign K12[8] = decrypt ? K_r10[55] : K_r10[32]; +assign K12[9] = decrypt ? K_r10[46] : K_r10[55]; +assign K12[10] = decrypt ? K_r10[40] : K_r10[17]; +assign K12[11] = decrypt ? K_r10[6] : K_r10[40]; +assign K12[12] = decrypt ? K_r10[11] : K_r10[20]; +assign K12[13] = decrypt ? K_r10[20] : K_r10[54]; +assign K12[14] = decrypt ? K_r10[17] : K_r10[26]; +assign K12[15] = decrypt ? K_r10[25] : K_r10[34]; +assign K12[16] = decrypt ? K_r10[26] : K_r10[3]; +assign K12[17] = decrypt ? K_r10[41] : K_r10[18]; +assign K12[18] = decrypt ? K_r10[54] : K_r10[6]; +assign K12[19] = decrypt ? K_r10[53] : K_r10[5]; +assign K12[20] = decrypt ? K_r10[47] : K_r10[24]; +assign K12[21] = decrypt ? K_r10[48] : K_r10[25]; +assign K12[22] = decrypt ? K_r10[24] : K_r10[33]; +assign K12[23] = decrypt ? K_r10[32] : K_r10[41]; +assign K12[24] = decrypt ? K_r10[12] : K_r10[46]; +assign K12[25] = decrypt ? K_r10[30] : K_r10[35]; +assign K12[26] = decrypt ? K_r10[21] : K_r10[2]; +assign K12[27] = decrypt ? K_r10[15] : K_r10[51]; +assign K12[28] = decrypt ? K_r10[2] : K_r10[7]; +assign K12[29] = decrypt ? K_r10[45] : K_r10[22]; +assign K12[30] = decrypt ? K_r10[42] : K_r10[23]; +assign K12[31] = decrypt ? K_r10[8] : K_r10[44]; +assign K12[32] = decrypt ? K_r10[23] : K_r10[28]; +assign K12[33] = decrypt ? K_r10[14] : K_r10[50]; +assign K12[34] = decrypt ? K_r10[31] : K_r10[8]; +assign K12[35] = decrypt ? K_r10[29] : K_r10[38]; +assign K12[36] = decrypt ? K_r10[52] : K_r10[29]; +assign K12[37] = decrypt ? K_r10[51] : K_r10[1]; +assign K12[38] = decrypt ? K_r10[0] : K_r10[36]; +assign K12[39] = decrypt ? K_r10[16] : K_r10[21]; +assign K12[40] = decrypt ? K_r10[49] : K_r10[30]; +assign K12[41] = decrypt ? K_r10[36] : K_r10[45]; +assign K12[42] = decrypt ? K_r10[28] : K_r10[9]; +assign K12[43] = decrypt ? K_r10[38] : K_r10[15]; +assign K12[44] = decrypt ? K_r10[37] : K_r10[42]; +assign K12[45] = decrypt ? K_r10[7] : K_r10[43]; +assign K12[46] = decrypt ? K_r10[50] : K_r10[0]; +assign K12[47] = decrypt ? K_r10[1] : K_r10[37]; +assign K12[48] = decrypt ? K_r10[22] : K_r10[31]; + +assign K11[1] = decrypt ? K_r9[53] : K_r9[34]; +assign K11[2] = decrypt ? K_r9[17] : K_r9[55]; +assign K11[3] = decrypt ? K_r9[32] : K_r9[13]; +assign K11[4] = decrypt ? K_r9[41] : K_r9[47]; +assign K11[5] = decrypt ? K_r9[19] : K_r9[25]; +assign K11[6] = decrypt ? K_r9[47] : K_r9[53]; +assign K11[7] = decrypt ? K_r9[33] : K_r9[39]; +assign K11[8] = decrypt ? K_r9[12] : K_r9[18]; +assign K11[9] = decrypt ? K_r9[3] : K_r9[41]; +assign K11[10] = decrypt ? K_r9[54] : K_r9[3]; +assign K11[11] = decrypt ? K_r9[20] : K_r9[26]; +assign K11[12] = decrypt ? K_r9[25] : K_r9[6]; +assign K11[13] = decrypt ? K_r9[34] : K_r9[40]; +assign K11[14] = decrypt ? K_r9[6] : K_r9[12]; +assign K11[15] = decrypt ? K_r9[39] : K_r9[20]; +assign K11[16] = decrypt ? K_r9[40] : K_r9[46]; +assign K11[17] = decrypt ? K_r9[55] : K_r9[4]; +assign K11[18] = decrypt ? K_r9[11] : K_r9[17]; +assign K11[19] = decrypt ? K_r9[10] : K_r9[48]; +assign K11[20] = decrypt ? K_r9[4] : K_r9[10]; +assign K11[21] = decrypt ? K_r9[5] : K_r9[11]; +assign K11[22] = decrypt ? K_r9[13] : K_r9[19]; +assign K11[23] = decrypt ? K_r9[46] : K_r9[27]; +assign K11[24] = decrypt ? K_r9[26] : K_r9[32]; +assign K11[25] = decrypt ? K_r9[44] : K_r9[21]; +assign K11[26] = decrypt ? K_r9[35] : K_r9[43]; +assign K11[27] = decrypt ? K_r9[29] : K_r9[37]; +assign K11[28] = decrypt ? K_r9[16] : K_r9[52]; +assign K11[29] = decrypt ? K_r9[0] : K_r9[8]; +assign K11[30] = decrypt ? K_r9[1] : K_r9[9]; +assign K11[31] = decrypt ? K_r9[22] : K_r9[30]; +assign K11[32] = decrypt ? K_r9[37] : K_r9[14]; +assign K11[33] = decrypt ? K_r9[28] : K_r9[36]; +assign K11[34] = decrypt ? K_r9[45] : K_r9[49]; +assign K11[35] = decrypt ? K_r9[43] : K_r9[51]; +assign K11[36] = decrypt ? K_r9[7] : K_r9[15]; +assign K11[37] = decrypt ? K_r9[38] : K_r9[42]; +assign K11[38] = decrypt ? K_r9[14] : K_r9[22]; +assign K11[39] = decrypt ? K_r9[30] : K_r9[7]; +assign K11[40] = decrypt ? K_r9[8] : K_r9[16]; +assign K11[41] = decrypt ? K_r9[50] : K_r9[31]; +assign K11[42] = decrypt ? K_r9[42] : K_r9[50]; +assign K11[43] = decrypt ? K_r9[52] : K_r9[1]; +assign K11[44] = decrypt ? K_r9[51] : K_r9[28]; +assign K11[45] = decrypt ? K_r9[21] : K_r9[29]; +assign K11[46] = decrypt ? K_r9[9] : K_r9[45]; +assign K11[47] = decrypt ? K_r9[15] : K_r9[23]; +assign K11[48] = decrypt ? K_r9[36] : K_r9[44]; + +assign K10[1] = decrypt ? K_r8[10] : K_r8[20]; +assign K10[2] = decrypt ? K_r8[6] : K_r8[41]; +assign K10[3] = decrypt ? K_r8[46] : K_r8[24]; +assign K10[4] = decrypt ? K_r8[55] : K_r8[33]; +assign K10[5] = decrypt ? K_r8[33] : K_r8[11]; +assign K10[6] = decrypt ? K_r8[4] : K_r8[39]; +assign K10[7] = decrypt ? K_r8[47] : K_r8[25]; +assign K10[8] = decrypt ? K_r8[26] : K_r8[4]; +assign K10[9] = decrypt ? K_r8[17] : K_r8[27]; +assign K10[10] = decrypt ? K_r8[11] : K_r8[46]; +assign K10[11] = decrypt ? K_r8[34] : K_r8[12]; +assign K10[12] = decrypt ? K_r8[39] : K_r8[17]; +assign K10[13] = decrypt ? K_r8[48] : K_r8[26]; +assign K10[14] = decrypt ? K_r8[20] : K_r8[55]; +assign K10[15] = decrypt ? K_r8[53] : K_r8[6]; +assign K10[16] = decrypt ? K_r8[54] : K_r8[32]; +assign K10[17] = decrypt ? K_r8[12] : K_r8[47]; +assign K10[18] = decrypt ? K_r8[25] : K_r8[3]; +assign K10[19] = decrypt ? K_r8[24] : K_r8[34]; +assign K10[20] = decrypt ? K_r8[18] : K_r8[53]; +assign K10[21] = decrypt ? K_r8[19] : K_r8[54]; +assign K10[22] = decrypt ? K_r8[27] : K_r8[5]; +assign K10[23] = decrypt ? K_r8[3] : K_r8[13]; +assign K10[24] = decrypt ? K_r8[40] : K_r8[18]; +assign K10[25] = decrypt ? K_r8[31] : K_r8[7]; +assign K10[26] = decrypt ? K_r8[49] : K_r8[29]; +assign K10[27] = decrypt ? K_r8[43] : K_r8[23]; +assign K10[28] = decrypt ? K_r8[30] : K_r8[38]; +assign K10[29] = decrypt ? K_r8[14] : K_r8[49]; +assign K10[30] = decrypt ? K_r8[15] : K_r8[50]; +assign K10[31] = decrypt ? K_r8[36] : K_r8[16]; +assign K10[32] = decrypt ? K_r8[51] : K_r8[0]; +assign K10[33] = decrypt ? K_r8[42] : K_r8[22]; +assign K10[34] = decrypt ? K_r8[0] : K_r8[35]; +assign K10[35] = decrypt ? K_r8[2] : K_r8[37]; +assign K10[36] = decrypt ? K_r8[21] : K_r8[1]; +assign K10[37] = decrypt ? K_r8[52] : K_r8[28]; +assign K10[38] = decrypt ? K_r8[28] : K_r8[8]; +assign K10[39] = decrypt ? K_r8[44] : K_r8[52]; +assign K10[40] = decrypt ? K_r8[22] : K_r8[2]; +assign K10[41] = decrypt ? K_r8[9] : K_r8[44]; +assign K10[42] = decrypt ? K_r8[1] : K_r8[36]; +assign K10[43] = decrypt ? K_r8[7] : K_r8[42]; +assign K10[44] = decrypt ? K_r8[38] : K_r8[14]; +assign K10[45] = decrypt ? K_r8[35] : K_r8[15]; +assign K10[46] = decrypt ? K_r8[23] : K_r8[31]; +assign K10[47] = decrypt ? K_r8[29] : K_r8[9]; +assign K10[48] = decrypt ? K_r8[50] : K_r8[30]; + +assign K9[1] = decrypt ? K_r7[24] : K_r7[6]; +assign K9[2] = decrypt ? K_r7[20] : K_r7[27]; +assign K9[3] = decrypt ? K_r7[3] : K_r7[10]; +assign K9[4] = decrypt ? K_r7[12] : K_r7[19]; +assign K9[5] = decrypt ? K_r7[47] : K_r7[54]; +assign K9[6] = decrypt ? K_r7[18] : K_r7[25]; +assign K9[7] = decrypt ? K_r7[4] : K_r7[11]; +assign K9[8] = decrypt ? K_r7[40] : K_r7[47]; +assign K9[9] = decrypt ? K_r7[6] : K_r7[13]; +assign K9[10] = decrypt ? K_r7[25] : K_r7[32]; +assign K9[11] = decrypt ? K_r7[48] : K_r7[55]; +assign K9[12] = decrypt ? K_r7[53] : K_r7[3]; +assign K9[13] = decrypt ? K_r7[5] : K_r7[12]; +assign K9[14] = decrypt ? K_r7[34] : K_r7[41]; +assign K9[15] = decrypt ? K_r7[10] : K_r7[17]; +assign K9[16] = decrypt ? K_r7[11] : K_r7[18]; +assign K9[17] = decrypt ? K_r7[26] : K_r7[33]; +assign K9[18] = decrypt ? K_r7[39] : K_r7[46]; +assign K9[19] = decrypt ? K_r7[13] : K_r7[20]; +assign K9[20] = decrypt ? K_r7[32] : K_r7[39]; +assign K9[21] = decrypt ? K_r7[33] : K_r7[40]; +assign K9[22] = decrypt ? K_r7[41] : K_r7[48]; +assign K9[23] = decrypt ? K_r7[17] : K_r7[24]; +assign K9[24] = decrypt ? K_r7[54] : K_r7[4]; +assign K9[25] = decrypt ? K_r7[45] : K_r7[52]; +assign K9[26] = decrypt ? K_r7[8] : K_r7[15]; +assign K9[27] = decrypt ? K_r7[2] : K_r7[9]; +assign K9[28] = decrypt ? K_r7[44] : K_r7[51]; +assign K9[29] = decrypt ? K_r7[28] : K_r7[35]; +assign K9[30] = decrypt ? K_r7[29] : K_r7[36]; +assign K9[31] = decrypt ? K_r7[50] : K_r7[2]; +assign K9[32] = decrypt ? K_r7[38] : K_r7[45]; +assign K9[33] = decrypt ? K_r7[1] : K_r7[8]; +assign K9[34] = decrypt ? K_r7[14] : K_r7[21]; +assign K9[35] = decrypt ? K_r7[16] : K_r7[23]; +assign K9[36] = decrypt ? K_r7[35] : K_r7[42]; +assign K9[37] = decrypt ? K_r7[7] : K_r7[14]; +assign K9[38] = decrypt ? K_r7[42] : K_r7[49]; +assign K9[39] = decrypt ? K_r7[31] : K_r7[38]; +assign K9[40] = decrypt ? K_r7[36] : K_r7[43]; +assign K9[41] = decrypt ? K_r7[23] : K_r7[30]; +assign K9[42] = decrypt ? K_r7[15] : K_r7[22]; +assign K9[43] = decrypt ? K_r7[21] : K_r7[28]; +assign K9[44] = decrypt ? K_r7[52] : K_r7[0]; +assign K9[45] = decrypt ? K_r7[49] : K_r7[1]; +assign K9[46] = decrypt ? K_r7[37] : K_r7[44]; +assign K9[47] = decrypt ? K_r7[43] : K_r7[50]; +assign K9[48] = decrypt ? K_r7[9] : K_r7[16]; + +assign K8[1] = decrypt ? K_r6[6] : K_r6[24]; +assign K8[2] = decrypt ? K_r6[27] : K_r6[20]; +assign K8[3] = decrypt ? K_r6[10] : K_r6[3]; +assign K8[4] = decrypt ? K_r6[19] : K_r6[12]; +assign K8[5] = decrypt ? K_r6[54] : K_r6[47]; +assign K8[6] = decrypt ? K_r6[25] : K_r6[18]; +assign K8[7] = decrypt ? K_r6[11] : K_r6[4]; +assign K8[8] = decrypt ? K_r6[47] : K_r6[40]; +assign K8[9] = decrypt ? K_r6[13] : K_r6[6]; +assign K8[10] = decrypt ? K_r6[32] : K_r6[25]; +assign K8[11] = decrypt ? K_r6[55] : K_r6[48]; +assign K8[12] = decrypt ? K_r6[3] : K_r6[53]; +assign K8[13] = decrypt ? K_r6[12] : K_r6[5]; +assign K8[14] = decrypt ? K_r6[41] : K_r6[34]; +assign K8[15] = decrypt ? K_r6[17] : K_r6[10]; +assign K8[16] = decrypt ? K_r6[18] : K_r6[11]; +assign K8[17] = decrypt ? K_r6[33] : K_r6[26]; +assign K8[18] = decrypt ? K_r6[46] : K_r6[39]; +assign K8[19] = decrypt ? K_r6[20] : K_r6[13]; +assign K8[20] = decrypt ? K_r6[39] : K_r6[32]; +assign K8[21] = decrypt ? K_r6[40] : K_r6[33]; +assign K8[22] = decrypt ? K_r6[48] : K_r6[41]; +assign K8[23] = decrypt ? K_r6[24] : K_r6[17]; +assign K8[24] = decrypt ? K_r6[4] : K_r6[54]; +assign K8[25] = decrypt ? K_r6[52] : K_r6[45]; +assign K8[26] = decrypt ? K_r6[15] : K_r6[8]; +assign K8[27] = decrypt ? K_r6[9] : K_r6[2]; +assign K8[28] = decrypt ? K_r6[51] : K_r6[44]; +assign K8[29] = decrypt ? K_r6[35] : K_r6[28]; +assign K8[30] = decrypt ? K_r6[36] : K_r6[29]; +assign K8[31] = decrypt ? K_r6[2] : K_r6[50]; +assign K8[32] = decrypt ? K_r6[45] : K_r6[38]; +assign K8[33] = decrypt ? K_r6[8] : K_r6[1]; +assign K8[34] = decrypt ? K_r6[21] : K_r6[14]; +assign K8[35] = decrypt ? K_r6[23] : K_r6[16]; +assign K8[36] = decrypt ? K_r6[42] : K_r6[35]; +assign K8[37] = decrypt ? K_r6[14] : K_r6[7]; +assign K8[38] = decrypt ? K_r6[49] : K_r6[42]; +assign K8[39] = decrypt ? K_r6[38] : K_r6[31]; +assign K8[40] = decrypt ? K_r6[43] : K_r6[36]; +assign K8[41] = decrypt ? K_r6[30] : K_r6[23]; +assign K8[42] = decrypt ? K_r6[22] : K_r6[15]; +assign K8[43] = decrypt ? K_r6[28] : K_r6[21]; +assign K8[44] = decrypt ? K_r6[0] : K_r6[52]; +assign K8[45] = decrypt ? K_r6[1] : K_r6[49]; +assign K8[46] = decrypt ? K_r6[44] : K_r6[37]; +assign K8[47] = decrypt ? K_r6[50] : K_r6[43]; +assign K8[48] = decrypt ? K_r6[16] : K_r6[9]; + +assign K7[1] = decrypt ? K_r5[20] : K_r5[10]; +assign K7[2] = decrypt ? K_r5[41] : K_r5[6]; +assign K7[3] = decrypt ? K_r5[24] : K_r5[46]; +assign K7[4] = decrypt ? K_r5[33] : K_r5[55]; +assign K7[5] = decrypt ? K_r5[11] : K_r5[33]; +assign K7[6] = decrypt ? K_r5[39] : K_r5[4]; +assign K7[7] = decrypt ? K_r5[25] : K_r5[47]; +assign K7[8] = decrypt ? K_r5[4] : K_r5[26]; +assign K7[9] = decrypt ? K_r5[27] : K_r5[17]; +assign K7[10] = decrypt ? K_r5[46] : K_r5[11]; +assign K7[11] = decrypt ? K_r5[12] : K_r5[34]; +assign K7[12] = decrypt ? K_r5[17] : K_r5[39]; +assign K7[13] = decrypt ? K_r5[26] : K_r5[48]; +assign K7[14] = decrypt ? K_r5[55] : K_r5[20]; +assign K7[15] = decrypt ? K_r5[6] : K_r5[53]; +assign K7[16] = decrypt ? K_r5[32] : K_r5[54]; +assign K7[17] = decrypt ? K_r5[47] : K_r5[12]; +assign K7[18] = decrypt ? K_r5[3] : K_r5[25]; +assign K7[19] = decrypt ? K_r5[34] : K_r5[24]; +assign K7[20] = decrypt ? K_r5[53] : K_r5[18]; +assign K7[21] = decrypt ? K_r5[54] : K_r5[19]; +assign K7[22] = decrypt ? K_r5[5] : K_r5[27]; +assign K7[23] = decrypt ? K_r5[13] : K_r5[3]; +assign K7[24] = decrypt ? K_r5[18] : K_r5[40]; +assign K7[25] = decrypt ? K_r5[7] : K_r5[31]; +assign K7[26] = decrypt ? K_r5[29] : K_r5[49]; +assign K7[27] = decrypt ? K_r5[23] : K_r5[43]; +assign K7[28] = decrypt ? K_r5[38] : K_r5[30]; +assign K7[29] = decrypt ? K_r5[49] : K_r5[14]; +assign K7[30] = decrypt ? K_r5[50] : K_r5[15]; +assign K7[31] = decrypt ? K_r5[16] : K_r5[36]; +assign K7[32] = decrypt ? K_r5[0] : K_r5[51]; +assign K7[33] = decrypt ? K_r5[22] : K_r5[42]; +assign K7[34] = decrypt ? K_r5[35] : K_r5[0]; +assign K7[35] = decrypt ? K_r5[37] : K_r5[2]; +assign K7[36] = decrypt ? K_r5[1] : K_r5[21]; +assign K7[37] = decrypt ? K_r5[28] : K_r5[52]; +assign K7[38] = decrypt ? K_r5[8] : K_r5[28]; +assign K7[39] = decrypt ? K_r5[52] : K_r5[44]; +assign K7[40] = decrypt ? K_r5[2] : K_r5[22]; +assign K7[41] = decrypt ? K_r5[44] : K_r5[9]; +assign K7[42] = decrypt ? K_r5[36] : K_r5[1]; +assign K7[43] = decrypt ? K_r5[42] : K_r5[7]; +assign K7[44] = decrypt ? K_r5[14] : K_r5[38]; +assign K7[45] = decrypt ? K_r5[15] : K_r5[35]; +assign K7[46] = decrypt ? K_r5[31] : K_r5[23]; +assign K7[47] = decrypt ? K_r5[9] : K_r5[29]; +assign K7[48] = decrypt ? K_r5[30] : K_r5[50]; + +assign K6[1] = decrypt ? K_r4[34] : K_r4[53]; +assign K6[2] = decrypt ? K_r4[55] : K_r4[17]; +assign K6[3] = decrypt ? K_r4[13] : K_r4[32]; +assign K6[4] = decrypt ? K_r4[47] : K_r4[41]; +assign K6[5] = decrypt ? K_r4[25] : K_r4[19]; +assign K6[6] = decrypt ? K_r4[53] : K_r4[47]; +assign K6[7] = decrypt ? K_r4[39] : K_r4[33]; +assign K6[8] = decrypt ? K_r4[18] : K_r4[12]; +assign K6[9] = decrypt ? K_r4[41] : K_r4[3]; +assign K6[10] = decrypt ? K_r4[3] : K_r4[54]; +assign K6[11] = decrypt ? K_r4[26] : K_r4[20]; +assign K6[12] = decrypt ? K_r4[6] : K_r4[25]; +assign K6[13] = decrypt ? K_r4[40] : K_r4[34]; +assign K6[14] = decrypt ? K_r4[12] : K_r4[6]; +assign K6[15] = decrypt ? K_r4[20] : K_r4[39]; +assign K6[16] = decrypt ? K_r4[46] : K_r4[40]; +assign K6[17] = decrypt ? K_r4[4] : K_r4[55]; +assign K6[18] = decrypt ? K_r4[17] : K_r4[11]; +assign K6[19] = decrypt ? K_r4[48] : K_r4[10]; +assign K6[20] = decrypt ? K_r4[10] : K_r4[4]; +assign K6[21] = decrypt ? K_r4[11] : K_r4[5]; +assign K6[22] = decrypt ? K_r4[19] : K_r4[13]; +assign K6[23] = decrypt ? K_r4[27] : K_r4[46]; +assign K6[24] = decrypt ? K_r4[32] : K_r4[26]; +assign K6[25] = decrypt ? K_r4[21] : K_r4[44]; +assign K6[26] = decrypt ? K_r4[43] : K_r4[35]; +assign K6[27] = decrypt ? K_r4[37] : K_r4[29]; +assign K6[28] = decrypt ? K_r4[52] : K_r4[16]; +assign K6[29] = decrypt ? K_r4[8] : K_r4[0]; +assign K6[30] = decrypt ? K_r4[9] : K_r4[1]; +assign K6[31] = decrypt ? K_r4[30] : K_r4[22]; +assign K6[32] = decrypt ? K_r4[14] : K_r4[37]; +assign K6[33] = decrypt ? K_r4[36] : K_r4[28]; +assign K6[34] = decrypt ? K_r4[49] : K_r4[45]; +assign K6[35] = decrypt ? K_r4[51] : K_r4[43]; +assign K6[36] = decrypt ? K_r4[15] : K_r4[7]; +assign K6[37] = decrypt ? K_r4[42] : K_r4[38]; +assign K6[38] = decrypt ? K_r4[22] : K_r4[14]; +assign K6[39] = decrypt ? K_r4[7] : K_r4[30]; +assign K6[40] = decrypt ? K_r4[16] : K_r4[8]; +assign K6[41] = decrypt ? K_r4[31] : K_r4[50]; +assign K6[42] = decrypt ? K_r4[50] : K_r4[42]; +assign K6[43] = decrypt ? K_r4[1] : K_r4[52]; +assign K6[44] = decrypt ? K_r4[28] : K_r4[51]; +assign K6[45] = decrypt ? K_r4[29] : K_r4[21]; +assign K6[46] = decrypt ? K_r4[45] : K_r4[9]; +assign K6[47] = decrypt ? K_r4[23] : K_r4[15]; +assign K6[48] = decrypt ? K_r4[44] : K_r4[36]; + +assign K5[1] = decrypt ? K_r3[48] : K_r3[39]; +assign K5[2] = decrypt ? K_r3[12] : K_r3[3]; +assign K5[3] = decrypt ? K_r3[27] : K_r3[18]; +assign K5[4] = decrypt ? K_r3[4] : K_r3[27]; +assign K5[5] = decrypt ? K_r3[39] : K_r3[5]; +assign K5[6] = decrypt ? K_r3[10] : K_r3[33]; +assign K5[7] = decrypt ? K_r3[53] : K_r3[19]; +assign K5[8] = decrypt ? K_r3[32] : K_r3[55]; +assign K5[9] = decrypt ? K_r3[55] : K_r3[46]; +assign K5[10] = decrypt ? K_r3[17] : K_r3[40]; +assign K5[11] = decrypt ? K_r3[40] : K_r3[6]; +assign K5[12] = decrypt ? K_r3[20] : K_r3[11]; +assign K5[13] = decrypt ? K_r3[54] : K_r3[20]; +assign K5[14] = decrypt ? K_r3[26] : K_r3[17]; +assign K5[15] = decrypt ? K_r3[34] : K_r3[25]; +assign K5[16] = decrypt ? K_r3[3] : K_r3[26]; +assign K5[17] = decrypt ? K_r3[18] : K_r3[41]; +assign K5[18] = decrypt ? K_r3[6] : K_r3[54]; +assign K5[19] = decrypt ? K_r3[5] : K_r3[53]; +assign K5[20] = decrypt ? K_r3[24] : K_r3[47]; +assign K5[21] = decrypt ? K_r3[25] : K_r3[48]; +assign K5[22] = decrypt ? K_r3[33] : K_r3[24]; +assign K5[23] = decrypt ? K_r3[41] : K_r3[32]; +assign K5[24] = decrypt ? K_r3[46] : K_r3[12]; +assign K5[25] = decrypt ? K_r3[35] : K_r3[30]; +assign K5[26] = decrypt ? K_r3[2] : K_r3[21]; +assign K5[27] = decrypt ? K_r3[51] : K_r3[15]; +assign K5[28] = decrypt ? K_r3[7] : K_r3[2]; +assign K5[29] = decrypt ? K_r3[22] : K_r3[45]; +assign K5[30] = decrypt ? K_r3[23] : K_r3[42]; +assign K5[31] = decrypt ? K_r3[44] : K_r3[8]; +assign K5[32] = decrypt ? K_r3[28] : K_r3[23]; +assign K5[33] = decrypt ? K_r3[50] : K_r3[14]; +assign K5[34] = decrypt ? K_r3[8] : K_r3[31]; +assign K5[35] = decrypt ? K_r3[38] : K_r3[29]; +assign K5[36] = decrypt ? K_r3[29] : K_r3[52]; +assign K5[37] = decrypt ? K_r3[1] : K_r3[51]; +assign K5[38] = decrypt ? K_r3[36] : K_r3[0]; +assign K5[39] = decrypt ? K_r3[21] : K_r3[16]; +assign K5[40] = decrypt ? K_r3[30] : K_r3[49]; +assign K5[41] = decrypt ? K_r3[45] : K_r3[36]; +assign K5[42] = decrypt ? K_r3[9] : K_r3[28]; +assign K5[43] = decrypt ? K_r3[15] : K_r3[38]; +assign K5[44] = decrypt ? K_r3[42] : K_r3[37]; +assign K5[45] = decrypt ? K_r3[43] : K_r3[7]; +assign K5[46] = decrypt ? K_r3[0] : K_r3[50]; +assign K5[47] = decrypt ? K_r3[37] : K_r3[1]; +assign K5[48] = decrypt ? K_r3[31] : K_r3[22]; + +assign K4[1] = decrypt ? K_r2[5] : K_r2[25]; +assign K4[2] = decrypt ? K_r2[26] : K_r2[46]; +assign K4[3] = decrypt ? K_r2[41] : K_r2[4]; +assign K4[4] = decrypt ? K_r2[18] : K_r2[13]; +assign K4[5] = decrypt ? K_r2[53] : K_r2[48]; +assign K4[6] = decrypt ? K_r2[24] : K_r2[19]; +assign K4[7] = decrypt ? K_r2[10] : K_r2[5]; +assign K4[8] = decrypt ? K_r2[46] : K_r2[41]; +assign K4[9] = decrypt ? K_r2[12] : K_r2[32]; +assign K4[10] = decrypt ? K_r2[6] : K_r2[26]; +assign K4[11] = decrypt ? K_r2[54] : K_r2[17]; +assign K4[12] = decrypt ? K_r2[34] : K_r2[54]; +assign K4[13] = decrypt ? K_r2[11] : K_r2[6]; +assign K4[14] = decrypt ? K_r2[40] : K_r2[3]; +assign K4[15] = decrypt ? K_r2[48] : K_r2[11]; +assign K4[16] = decrypt ? K_r2[17] : K_r2[12]; +assign K4[17] = decrypt ? K_r2[32] : K_r2[27]; +assign K4[18] = decrypt ? K_r2[20] : K_r2[40]; +assign K4[19] = decrypt ? K_r2[19] : K_r2[39]; +assign K4[20] = decrypt ? K_r2[13] : K_r2[33]; +assign K4[21] = decrypt ? K_r2[39] : K_r2[34]; +assign K4[22] = decrypt ? K_r2[47] : K_r2[10]; +assign K4[23] = decrypt ? K_r2[55] : K_r2[18]; +assign K4[24] = decrypt ? K_r2[3] : K_r2[55]; +assign K4[25] = decrypt ? K_r2[49] : K_r2[16]; +assign K4[26] = decrypt ? K_r2[16] : K_r2[7]; +assign K4[27] = decrypt ? K_r2[38] : K_r2[1]; +assign K4[28] = decrypt ? K_r2[21] : K_r2[43]; +assign K4[29] = decrypt ? K_r2[36] : K_r2[31]; +assign K4[30] = decrypt ? K_r2[37] : K_r2[28]; +assign K4[31] = decrypt ? K_r2[31] : K_r2[49]; +assign K4[32] = decrypt ? K_r2[42] : K_r2[9]; +assign K4[33] = decrypt ? K_r2[9] : K_r2[0]; +assign K4[34] = decrypt ? K_r2[22] : K_r2[44]; +assign K4[35] = decrypt ? K_r2[52] : K_r2[15]; +assign K4[36] = decrypt ? K_r2[43] : K_r2[38]; +assign K4[37] = decrypt ? K_r2[15] : K_r2[37]; +assign K4[38] = decrypt ? K_r2[50] : K_r2[45]; +assign K4[39] = decrypt ? K_r2[35] : K_r2[2]; +assign K4[40] = decrypt ? K_r2[44] : K_r2[35]; +assign K4[41] = decrypt ? K_r2[0] : K_r2[22]; +assign K4[42] = decrypt ? K_r2[23] : K_r2[14]; +assign K4[43] = decrypt ? K_r2[29] : K_r2[51]; +assign K4[44] = decrypt ? K_r2[1] : K_r2[23]; +assign K4[45] = decrypt ? K_r2[2] : K_r2[52]; +assign K4[46] = decrypt ? K_r2[14] : K_r2[36]; +assign K4[47] = decrypt ? K_r2[51] : K_r2[42]; +assign K4[48] = decrypt ? K_r2[45] : K_r2[8]; + +assign K3[1] = decrypt ? K_r1[19] : K_r1[11]; +assign K3[2] = decrypt ? K_r1[40] : K_r1[32]; +assign K3[3] = decrypt ? K_r1[55] : K_r1[47]; +assign K3[4] = decrypt ? K_r1[32] : K_r1[24]; +assign K3[5] = decrypt ? K_r1[10] : K_r1[34]; +assign K3[6] = decrypt ? K_r1[13] : K_r1[5]; +assign K3[7] = decrypt ? K_r1[24] : K_r1[48]; +assign K3[8] = decrypt ? K_r1[3] : K_r1[27]; +assign K3[9] = decrypt ? K_r1[26] : K_r1[18]; +assign K3[10] = decrypt ? K_r1[20] : K_r1[12]; +assign K3[11] = decrypt ? K_r1[11] : K_r1[3]; +assign K3[12] = decrypt ? K_r1[48] : K_r1[40]; +assign K3[13] = decrypt ? K_r1[25] : K_r1[17]; +assign K3[14] = decrypt ? K_r1[54] : K_r1[46]; +assign K3[15] = decrypt ? K_r1[5] : K_r1[54]; +assign K3[16] = decrypt ? K_r1[6] : K_r1[55]; +assign K3[17] = decrypt ? K_r1[46] : K_r1[13]; +assign K3[18] = decrypt ? K_r1[34] : K_r1[26]; +assign K3[19] = decrypt ? K_r1[33] : K_r1[25]; +assign K3[20] = decrypt ? K_r1[27] : K_r1[19]; +assign K3[21] = decrypt ? K_r1[53] : K_r1[20]; +assign K3[22] = decrypt ? K_r1[4] : K_r1[53]; +assign K3[23] = decrypt ? K_r1[12] : K_r1[4]; +assign K3[24] = decrypt ? K_r1[17] : K_r1[41]; +assign K3[25] = decrypt ? K_r1[8] : K_r1[2]; +assign K3[26] = decrypt ? K_r1[30] : K_r1[52]; +assign K3[27] = decrypt ? K_r1[52] : K_r1[42]; +assign K3[28] = decrypt ? K_r1[35] : K_r1[29]; +assign K3[29] = decrypt ? K_r1[50] : K_r1[44]; +assign K3[30] = decrypt ? K_r1[51] : K_r1[14]; +assign K3[31] = decrypt ? K_r1[45] : K_r1[35]; +assign K3[32] = decrypt ? K_r1[1] : K_r1[50]; +assign K3[33] = decrypt ? K_r1[23] : K_r1[45]; +assign K3[34] = decrypt ? K_r1[36] : K_r1[30]; +assign K3[35] = decrypt ? K_r1[7] : K_r1[1]; +assign K3[36] = decrypt ? K_r1[2] : K_r1[51]; +assign K3[37] = decrypt ? K_r1[29] : K_r1[23]; +assign K3[38] = decrypt ? K_r1[9] : K_r1[31]; +assign K3[39] = decrypt ? K_r1[49] : K_r1[43]; +assign K3[40] = decrypt ? K_r1[31] : K_r1[21]; +assign K3[41] = decrypt ? K_r1[14] : K_r1[8]; +assign K3[42] = decrypt ? K_r1[37] : K_r1[0]; +assign K3[43] = decrypt ? K_r1[43] : K_r1[37]; +assign K3[44] = decrypt ? K_r1[15] : K_r1[9]; +assign K3[45] = decrypt ? K_r1[16] : K_r1[38]; +assign K3[46] = decrypt ? K_r1[28] : K_r1[22]; +assign K3[47] = decrypt ? K_r1[38] : K_r1[28]; +assign K3[48] = decrypt ? K_r1[0] : K_r1[49]; + +assign K2[1] = decrypt ? K_r0[33] : K_r0[54]; +assign K2[2] = decrypt ? K_r0[54] : K_r0[18]; +assign K2[3] = decrypt ? K_r0[12] : K_r0[33]; +assign K2[4] = decrypt ? K_r0[46] : K_r0[10]; +assign K2[5] = decrypt ? K_r0[24] : K_r0[20]; +assign K2[6] = decrypt ? K_r0[27] : K_r0[48]; +assign K2[7] = decrypt ? K_r0[13] : K_r0[34]; +assign K2[8] = decrypt ? K_r0[17] : K_r0[13]; +assign K2[9] = decrypt ? K_r0[40] : K_r0[4]; +assign K2[10] = decrypt ? K_r0[34] : K_r0[55]; +assign K2[11] = decrypt ? K_r0[25] : K_r0[46]; +assign K2[12] = decrypt ? K_r0[5] : K_r0[26]; +assign K2[13] = decrypt ? K_r0[39] : K_r0[3]; +assign K2[14] = decrypt ? K_r0[11] : K_r0[32]; +assign K2[15] = decrypt ? K_r0[19] : K_r0[40]; +assign K2[16] = decrypt ? K_r0[20] : K_r0[41]; +assign K2[17] = decrypt ? K_r0[3] : K_r0[24]; +assign K2[18] = decrypt ? K_r0[48] : K_r0[12]; +assign K2[19] = decrypt ? K_r0[47] : K_r0[11]; +assign K2[20] = decrypt ? K_r0[41] : K_r0[5]; +assign K2[21] = decrypt ? K_r0[10] : K_r0[6]; +assign K2[22] = decrypt ? K_r0[18] : K_r0[39]; +assign K2[23] = decrypt ? K_r0[26] : K_r0[47]; +assign K2[24] = decrypt ? K_r0[6] : K_r0[27]; +assign K2[25] = decrypt ? K_r0[22] : K_r0[43]; +assign K2[26] = decrypt ? K_r0[44] : K_r0[38]; +assign K2[27] = decrypt ? K_r0[7] : K_r0[28]; +assign K2[28] = decrypt ? K_r0[49] : K_r0[15]; +assign K2[29] = decrypt ? K_r0[9] : K_r0[30]; +assign K2[30] = decrypt ? K_r0[38] : K_r0[0]; +assign K2[31] = decrypt ? K_r0[0] : K_r0[21]; +assign K2[32] = decrypt ? K_r0[15] : K_r0[36]; +assign K2[33] = decrypt ? K_r0[37] : K_r0[31]; +assign K2[34] = decrypt ? K_r0[50] : K_r0[16]; +assign K2[35] = decrypt ? K_r0[21] : K_r0[42]; +assign K2[36] = decrypt ? K_r0[16] : K_r0[37]; +assign K2[37] = decrypt ? K_r0[43] : K_r0[9]; +assign K2[38] = decrypt ? K_r0[23] : K_r0[44]; +assign K2[39] = decrypt ? K_r0[8] : K_r0[29]; +assign K2[40] = decrypt ? K_r0[45] : K_r0[7]; +assign K2[41] = decrypt ? K_r0[28] : K_r0[49]; +assign K2[42] = decrypt ? K_r0[51] : K_r0[45]; +assign K2[43] = decrypt ? K_r0[2] : K_r0[23]; +assign K2[44] = decrypt ? K_r0[29] : K_r0[50]; +assign K2[45] = decrypt ? K_r0[30] : K_r0[51]; +assign K2[46] = decrypt ? K_r0[42] : K_r0[8]; +assign K2[47] = decrypt ? K_r0[52] : K_r0[14]; +assign K2[48] = decrypt ? K_r0[14] : K_r0[35]; + +assign K1[1] = decrypt ? K[40] : K[47]; +assign K1[2] = decrypt ? K[4] : K[11]; +assign K1[3] = decrypt ? K[19] : K[26]; +assign K1[4] = decrypt ? K[53] : K[3]; +assign K1[5] = decrypt ? K[6] : K[13]; +assign K1[6] = decrypt ? K[34] : K[41]; +assign K1[7] = decrypt ? K[20] : K[27]; +assign K1[8] = decrypt ? K[24] : K[6]; +assign K1[9] = decrypt ? K[47] : K[54]; +assign K1[10] = decrypt ? K[41] : K[48]; +assign K1[11] = decrypt ? K[32] : K[39]; +assign K1[12] = decrypt ? K[12] : K[19]; +assign K1[13] = decrypt ? K[46] : K[53]; +assign K1[14] = decrypt ? K[18] : K[25]; +assign K1[15] = decrypt ? K[26] : K[33]; +assign K1[16] = decrypt ? K[27] : K[34]; +assign K1[17] = decrypt ? K[10] : K[17]; +assign K1[18] = decrypt ? K[55] : K[5]; +assign K1[19] = decrypt ? K[54] : K[4]; +assign K1[20] = decrypt ? K[48] : K[55]; +assign K1[21] = decrypt ? K[17] : K[24]; +assign K1[22] = decrypt ? K[25] : K[32]; +assign K1[23] = decrypt ? K[33] : K[40]; +assign K1[24] = decrypt ? K[13] : K[20]; +assign K1[25] = decrypt ? K[29] : K[36]; +assign K1[26] = decrypt ? K[51] : K[31]; +assign K1[27] = decrypt ? K[14] : K[21]; +assign K1[28] = decrypt ? K[1] : K[8]; +assign K1[29] = decrypt ? K[16] : K[23]; +assign K1[30] = decrypt ? K[45] : K[52]; +assign K1[31] = decrypt ? K[7] : K[14]; +assign K1[32] = decrypt ? K[22] : K[29]; +assign K1[33] = decrypt ? K[44] : K[51]; +assign K1[34] = decrypt ? K[2] : K[9]; +assign K1[35] = decrypt ? K[28] : K[35]; +assign K1[36] = decrypt ? K[23] : K[30]; +assign K1[37] = decrypt ? K[50] : K[2]; +assign K1[38] = decrypt ? K[30] : K[37]; +assign K1[39] = decrypt ? K[15] : K[22]; +assign K1[40] = decrypt ? K[52] : K[0]; +assign K1[41] = decrypt ? K[35] : K[42]; +assign K1[42] = decrypt ? K[31] : K[38]; +assign K1[43] = decrypt ? K[9] : K[16]; +assign K1[44] = decrypt ? K[36] : K[43]; +assign K1[45] = decrypt ? K[37] : K[44]; +assign K1[46] = decrypt ? K[49] : K[1]; +assign K1[47] = decrypt ? K[0] : K[7]; +assign K1[48] = decrypt ? K[21] : K[28]; + +endmodule diff --git a/designs/encrypted_ip/des3_perf/mem_1x1024.v b/designs/encrypted_ip/des3_perf/mem_1x1024.v new file mode 100644 index 000000000..8ff1c743b --- /dev/null +++ b/designs/encrypted_ip/des3_perf/mem_1x1024.v @@ -0,0 +1,25 @@ +module mem_disp +( + clk, + wr, + addr, + d_i, + d_o +); + + input clk; + input wr; + input [9:0] addr; + input d_i; + output reg d_o; + + reg mem [1023:0]; + + + always @ (posedge clk) + begin + if(wr) + mem[addr] <= d_i; + d_o <= mem[addr]; + end +endmodule diff --git a/designs/encrypted_ip/des3_perf/mem_8x1024.v b/designs/encrypted_ip/des3_perf/mem_8x1024.v new file mode 100644 index 000000000..4f7ec64e9 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/mem_8x1024.v @@ -0,0 +1,27 @@ +module mem +( + clk, + wr, + addr, + d_i, + d_o +); + + input clk; + input wr; + input [9:0] addr; + input [7:0] d_i; + output reg [7:0] d_o; + + reg [7:0] mem [1023:0]; + + + + always @ (posedge clk) + begin + if(wr) + mem[addr] <= d_i; + d_o <= mem[addr]; + + end +endmodule diff --git a/designs/encrypted_ip/des3_perf/sbox1.v b/designs/encrypted_ip/des3_perf/sbox1.v new file mode 100644 index 000000000..76d5e22f6 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/sbox1.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox1(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 14; + 1: dout = 4; + 2: dout = 13; + 3: dout = 1; + 4: dout = 2; + 5: dout = 15; + 6: dout = 11; + 7: dout = 8; + 8: dout = 3; + 9: dout = 10; + 10: dout = 6; + 11: dout = 12; + 12: dout = 5; + 13: dout = 9; + 14: dout = 0; + 15: dout = 7; + + 16: dout = 0; + 17: dout = 15; + 18: dout = 7; + 19: dout = 4; + 20: dout = 14; + 21: dout = 2; + 22: dout = 13; + 23: dout = 1; + 24: dout = 10; + 25: dout = 6; + 26: dout = 12; + 27: dout = 11; + 28: dout = 9; + 29: dout = 5; + 30: dout = 3; + 31: dout = 8; + + 32: dout = 4; + 33: dout = 1; + 34: dout = 14; + 35: dout = 8; + 36: dout = 13; + 37: dout = 6; + 38: dout = 2; + 39: dout = 11; + 40: dout = 15; + 41: dout = 12; + 42: dout = 9; + 43: dout = 7; + 44: dout = 3; + 45: dout = 10; + 46: dout = 5; + 47: dout = 0; + + 48: dout = 15; + 49: dout = 12; + 50: dout = 8; + 51: dout = 2; + 52: dout = 4; + 53: dout = 9; + 54: dout = 1; + 55: dout = 7; + 56: dout = 5; + 57: dout = 11; + 58: dout = 3; + 59: dout = 14; + 60: dout = 10; + 61: dout = 0; + 62: dout = 6; + 63: dout = 13; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_perf/sbox2.v b/designs/encrypted_ip/des3_perf/sbox2.v new file mode 100644 index 000000000..aa505f3a2 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/sbox2.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox2(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 15; + 1: dout = 1; + 2: dout = 8; + 3: dout = 14; + 4: dout = 6; + 5: dout = 11; + 6: dout = 3; + 7: dout = 4; + 8: dout = 9; + 9: dout = 7; + 10: dout = 2; + 11: dout = 13; + 12: dout = 12; + 13: dout = 0; + 14: dout = 5; + 15: dout = 10; + + 16: dout = 3; + 17: dout = 13; + 18: dout = 4; + 19: dout = 7; + 20: dout = 15; + 21: dout = 2; + 22: dout = 8; + 23: dout = 14; + 24: dout = 12; + 25: dout = 0; + 26: dout = 1; + 27: dout = 10; + 28: dout = 6; + 29: dout = 9; + 30: dout = 11; + 31: dout = 5; + + 32: dout = 0; + 33: dout = 14; + 34: dout = 7; + 35: dout = 11; + 36: dout = 10; + 37: dout = 4; + 38: dout = 13; + 39: dout = 1; + 40: dout = 5; + 41: dout = 8; + 42: dout = 12; + 43: dout = 6; + 44: dout = 9; + 45: dout = 3; + 46: dout = 2; + 47: dout = 15; + + 48: dout = 13; + 49: dout = 8; + 50: dout = 10; + 51: dout = 1; + 52: dout = 3; + 53: dout = 15; + 54: dout = 4; + 55: dout = 2; + 56: dout = 11; + 57: dout = 6; + 58: dout = 7; + 59: dout = 12; + 60: dout = 0; + 61: dout = 5; + 62: dout = 14; + 63: dout = 9; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_perf/sbox3.v b/designs/encrypted_ip/des3_perf/sbox3.v new file mode 100644 index 000000000..0c6cddf03 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/sbox3.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox3(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 10; + 1: dout = 0; + 2: dout = 9; + 3: dout = 14; + 4: dout = 6; + 5: dout = 3; + 6: dout = 15; + 7: dout = 5; + 8: dout = 1; + 9: dout = 13; + 10: dout = 12; + 11: dout = 7; + 12: dout = 11; + 13: dout = 4; + 14: dout = 2; + 15: dout = 8; + + 16: dout = 13; + 17: dout = 7; + 18: dout = 0; + 19: dout = 9; + 20: dout = 3; + 21: dout = 4; + 22: dout = 6; + 23: dout = 10; + 24: dout = 2; + 25: dout = 8; + 26: dout = 5; + 27: dout = 14; + 28: dout = 12; + 29: dout = 11; + 30: dout = 15; + 31: dout = 1; + + 32: dout = 13; + 33: dout = 6; + 34: dout = 4; + 35: dout = 9; + 36: dout = 8; + 37: dout = 15; + 38: dout = 3; + 39: dout = 0; + 40: dout = 11; + 41: dout = 1; + 42: dout = 2; + 43: dout = 12; + 44: dout = 5; + 45: dout = 10; + 46: dout = 14; + 47: dout = 7; + + 48: dout = 1; + 49: dout = 10; + 50: dout = 13; + 51: dout = 0; + 52: dout = 6; + 53: dout = 9; + 54: dout = 8; + 55: dout = 7; + 56: dout = 4; + 57: dout = 15; + 58: dout = 14; + 59: dout = 3; + 60: dout = 11; + 61: dout = 5; + 62: dout = 2; + 63: dout = 12; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_perf/sbox4.v b/designs/encrypted_ip/des3_perf/sbox4.v new file mode 100644 index 000000000..ec531c1e8 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/sbox4.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox4(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 7; + 1: dout = 13; + 2: dout = 14; + 3: dout = 3; + 4: dout = 0; + 5: dout = 6; + 6: dout = 9; + 7: dout = 10; + 8: dout = 1; + 9: dout = 2; + 10: dout = 8; + 11: dout = 5; + 12: dout = 11; + 13: dout = 12; + 14: dout = 4; + 15: dout = 15; + + 16: dout = 13; + 17: dout = 8; + 18: dout = 11; + 19: dout = 5; + 20: dout = 6; + 21: dout = 15; + 22: dout = 0; + 23: dout = 3; + 24: dout = 4; + 25: dout = 7; + 26: dout = 2; + 27: dout = 12; + 28: dout = 1; + 29: dout = 10; + 30: dout = 14; + 31: dout = 9; + + 32: dout = 10; + 33: dout = 6; + 34: dout = 9; + 35: dout = 0; + 36: dout = 12; + 37: dout = 11; + 38: dout = 7; + 39: dout = 13; + 40: dout = 15; + 41: dout = 1; + 42: dout = 3; + 43: dout = 14; + 44: dout = 5; + 45: dout = 2; + 46: dout = 8; + 47: dout = 4; + + 48: dout = 3; + 49: dout = 15; + 50: dout = 0; + 51: dout = 6; + 52: dout = 10; + 53: dout = 1; + 54: dout = 13; + 55: dout = 8; + 56: dout = 9; + 57: dout = 4; + 58: dout = 5; + 59: dout = 11; + 60: dout = 12; + 61: dout = 7; + 62: dout = 2; + 63: dout = 14; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_perf/sbox5.v b/designs/encrypted_ip/des3_perf/sbox5.v new file mode 100644 index 000000000..f874c25cc --- /dev/null +++ b/designs/encrypted_ip/des3_perf/sbox5.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox5(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 2; + 1: dout = 12; + 2: dout = 4; + 3: dout = 1; + 4: dout = 7; + 5: dout = 10; + 6: dout = 11; + 7: dout = 6; + 8: dout = 8; + 9: dout = 5; + 10: dout = 3; + 11: dout = 15; + 12: dout = 13; + 13: dout = 0; + 14: dout = 14; + 15: dout = 9; + + 16: dout = 14; + 17: dout = 11; + 18: dout = 2; + 19: dout = 12; + 20: dout = 4; + 21: dout = 7; + 22: dout = 13; + 23: dout = 1; + 24: dout = 5; + 25: dout = 0; + 26: dout = 15; + 27: dout = 10; + 28: dout = 3; + 29: dout = 9; + 30: dout = 8; + 31: dout = 6; + + 32: dout = 4; + 33: dout = 2; + 34: dout = 1; + 35: dout = 11; + 36: dout = 10; + 37: dout = 13; + 38: dout = 7; + 39: dout = 8; + 40: dout = 15; + 41: dout = 9; + 42: dout = 12; + 43: dout = 5; + 44: dout = 6; + 45: dout = 3; + 46: dout = 0; + 47: dout = 14; + + 48: dout = 11; + 49: dout = 8; + 50: dout = 12; + 51: dout = 7; + 52: dout = 1; + 53: dout = 14; + 54: dout = 2; + 55: dout = 13; + 56: dout = 6; + 57: dout = 15; + 58: dout = 0; + 59: dout = 9; + 60: dout = 10; + 61: dout = 4; + 62: dout = 5; + 63: dout = 3; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_perf/sbox6.v b/designs/encrypted_ip/des3_perf/sbox6.v new file mode 100644 index 000000000..58fc86af0 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/sbox6.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox6(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 12; + 1: dout = 1; + 2: dout = 10; + 3: dout = 15; + 4: dout = 9; + 5: dout = 2; + 6: dout = 6; + 7: dout = 8; + 8: dout = 0; + 9: dout = 13; + 10: dout = 3; + 11: dout = 4; + 12: dout = 14; + 13: dout = 7; + 14: dout = 5; + 15: dout = 11; + + 16: dout = 10; + 17: dout = 15; + 18: dout = 4; + 19: dout = 2; + 20: dout = 7; + 21: dout = 12; + 22: dout = 9; + 23: dout = 5; + 24: dout = 6; + 25: dout = 1; + 26: dout = 13; + 27: dout = 14; + 28: dout = 0; + 29: dout = 11; + 30: dout = 3; + 31: dout = 8; + + 32: dout = 9; + 33: dout = 14; + 34: dout = 15; + 35: dout = 5; + 36: dout = 2; + 37: dout = 8; + 38: dout = 12; + 39: dout = 3; + 40: dout = 7; + 41: dout = 0; + 42: dout = 4; + 43: dout = 10; + 44: dout = 1; + 45: dout = 13; + 46: dout = 11; + 47: dout = 6; + + 48: dout = 4; + 49: dout = 3; + 50: dout = 2; + 51: dout = 12; + 52: dout = 9; + 53: dout = 5; + 54: dout = 15; + 55: dout = 10; + 56: dout = 11; + 57: dout = 14; + 58: dout = 1; + 59: dout = 7; + 60: dout = 6; + 61: dout = 0; + 62: dout = 8; + 63: dout = 13; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_perf/sbox7.v b/designs/encrypted_ip/des3_perf/sbox7.v new file mode 100644 index 000000000..f27957e2f --- /dev/null +++ b/designs/encrypted_ip/des3_perf/sbox7.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox7(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 4; + 1: dout = 11; + 2: dout = 2; + 3: dout = 14; + 4: dout = 15; + 5: dout = 0; + 6: dout = 8; + 7: dout = 13; + 8: dout = 3; + 9: dout = 12; + 10: dout = 9; + 11: dout = 7; + 12: dout = 5; + 13: dout = 10; + 14: dout = 6; + 15: dout = 1; + + 16: dout = 13; + 17: dout = 0; + 18: dout = 11; + 19: dout = 7; + 20: dout = 4; + 21: dout = 9; + 22: dout = 1; + 23: dout = 10; + 24: dout = 14; + 25: dout = 3; + 26: dout = 5; + 27: dout = 12; + 28: dout = 2; + 29: dout = 15; + 30: dout = 8; + 31: dout = 6; + + 32: dout = 1; + 33: dout = 4; + 34: dout = 11; + 35: dout = 13; + 36: dout = 12; + 37: dout = 3; + 38: dout = 7; + 39: dout = 14; + 40: dout = 10; + 41: dout = 15; + 42: dout = 6; + 43: dout = 8; + 44: dout = 0; + 45: dout = 5; + 46: dout = 9; + 47: dout = 2; + + 48: dout = 6; + 49: dout = 11; + 50: dout = 13; + 51: dout = 8; + 52: dout = 1; + 53: dout = 4; + 54: dout = 10; + 55: dout = 7; + 56: dout = 9; + 57: dout = 5; + 58: dout = 0; + 59: dout = 15; + 60: dout = 14; + 61: dout = 2; + 62: dout = 3; + 63: dout = 12; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_perf/sbox8.v b/designs/encrypted_ip/des3_perf/sbox8.v new file mode 100644 index 000000000..5ebad6388 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/sbox8.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox8(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 13; + 1: dout = 2; + 2: dout = 8; + 3: dout = 4; + 4: dout = 6; + 5: dout = 15; + 6: dout = 11; + 7: dout = 1; + 8: dout = 10; + 9: dout = 9; + 10: dout = 3; + 11: dout = 14; + 12: dout = 5; + 13: dout = 0; + 14: dout = 12; + 15: dout = 7; + + 16: dout = 1; + 17: dout = 15; + 18: dout = 13; + 19: dout = 8; + 20: dout = 10; + 21: dout = 3; + 22: dout = 7; + 23: dout = 4; + 24: dout = 12; + 25: dout = 5; + 26: dout = 6; + 27: dout = 11; + 28: dout = 0; + 29: dout = 14; + 30: dout = 9; + 31: dout = 2; + + 32: dout = 7; + 33: dout = 11; + 34: dout = 4; + 35: dout = 1; + 36: dout = 9; + 37: dout = 12; + 38: dout = 14; + 39: dout = 2; + 40: dout = 0; + 41: dout = 6; + 42: dout = 10; + 43: dout = 13; + 44: dout = 15; + 45: dout = 3; + 46: dout = 5; + 47: dout = 8; + + 48: dout = 2; + 49: dout = 1; + 50: dout = 14; + 51: dout = 7; + 52: dout = 4; + 53: dout = 10; + 54: dout = 8; + 55: dout = 13; + 56: dout = 15; + 57: dout = 12; + 58: dout = 9; + 59: dout = 0; + 60: dout = 3; + 61: dout = 5; + 62: dout = 6; + 63: dout = 11; + + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_perf/tbu.v b/designs/encrypted_ip/des3_perf/tbu.v new file mode 100644 index 000000000..e8388d0cb --- /dev/null +++ b/designs/encrypted_ip/des3_perf/tbu.v @@ -0,0 +1,224 @@ +module tbu +( + clk, + rst, + enable, + selection, + d_in_0, + d_in_1, + d_o, + wr_en +); + + input clk; + input rst; + input enable; + input selection; + input [7:0] d_in_0; + input [7:0] d_in_1; + output reg d_o; + output reg wr_en; + + + reg d_o_reg; + reg wr_en_reg; + + + reg [2:0] pstate; + reg [2:0] nstate; + + reg selection_buf; + + always @(posedge clk) + begin + selection_buf <= selection; + wr_en <= wr_en_reg; + d_o <= d_o_reg; + end + always @(posedge clk or negedge rst) + begin + if(rst==1'b0) + pstate <= 3'b000; + else if(enable==1'b0) + pstate <= 3'b000; + else if(selection_buf==1'b1 && selection==1'b0) + pstate <= 3'b000; + else + pstate <= nstate; + end + + + always @(*) + begin + case (pstate) + 3'b000: + begin + if(selection==1'b0) + begin + wr_en_reg = 1'b0; + case(d_in_0[0]) + 1'b0: nstate = 3'b000; + 1'b1: nstate = 3'b001; + endcase + end + else + begin + d_o_reg = d_in_1[0]; + wr_en_reg = 1'b1; + case(d_in_1[0]) + 1'b0: nstate = 3'b000; + 1'b1: nstate = 3'b001; + endcase + end + end + + 3'b001: + begin + if(selection==1'b0) + begin + wr_en_reg = 1'b0; + case(d_in_0[1]) + 1'b0: nstate = 3'b011; + 1'b1: nstate = 3'b010; + endcase + end + else + begin + d_o_reg = d_in_1[1]; + wr_en_reg = 1'b1; + case(d_in_1[1]) + 1'b0: nstate = 3'b011; + 1'b1: nstate = 3'b010; + endcase + end + end + + 3'b010: + begin + if(selection==1'b0) + begin + wr_en_reg = 1'b0; + case(d_in_0[2]) + 1'b0: nstate = 3'b100; + 1'b1: nstate = 3'b101; + endcase + end + else + begin + d_o_reg = d_in_1[2]; + wr_en_reg = 1'b1; + case(d_in_1[2]) + 1'b0: nstate = 3'b100; + 1'b1: nstate = 3'b101; + endcase + end + end + + 3'b011: + begin + if(selection==1'b0) + begin + wr_en_reg = 1'b0; + case(d_in_0[3]) + 1'b0: nstate = 3'b111; + 1'b1: nstate = 3'b110; + endcase + end + else + begin + d_o_reg = d_in_1[3]; + wr_en_reg = 1'b1; + case(d_in_1[3]) + 1'b0: nstate = 3'b111; + 1'b1: nstate = 3'b110; + endcase + end + end + + 3'b100: + begin + if(selection==1'b0) + begin + wr_en_reg = 1'b0; + case(d_in_0[4]) + 1'b0: nstate = 3'b001; + 1'b1: nstate = 3'b000; + endcase + end + else + begin + d_o_reg = d_in_1[4]; + wr_en_reg = 1'b1; + case(d_in_1[4]) + 1'b0: nstate = 3'b001; + 1'b1: nstate = 3'b000; + endcase + end + end + + 3'b101: + begin + if(selection==1'b0) + begin + wr_en_reg = 1'b0; + case(d_in_0[5]) + 1'b0: nstate = 3'b010; + 1'b1: nstate = 3'b011; + endcase + end + else + begin + d_o_reg = d_in_1[5]; + wr_en_reg = 1'b1; + case(d_in_1[5]) + 1'b0: nstate = 3'b010; + 1'b1: nstate = 3'b011; + endcase + end + end + + 3'b110: + begin + if(selection==1'b0) + begin + wr_en_reg = 1'b0; + case(d_in_0[6]) + 1'b0: nstate = 3'b101; + 1'b1: nstate = 3'b100; + endcase + end + else + begin + d_o_reg = d_in_1[6]; + wr_en_reg = 1'b1; + case(d_in_1[6]) + 1'b0: nstate = 3'b101; + 1'b1: nstate = 3'b100; + endcase + end + end + + 3'b111: + begin + if(selection==1'b0) + begin + wr_en_reg = 1'b0; + case(d_in_0[7]) + 1'b0: nstate = 3'b110; + 1'b1: nstate = 3'b111; + endcase + end + else + begin + d_o_reg = d_in_1[7]; + wr_en_reg = 1'b1; + case(d_in_1[7]) + 1'b0: nstate = 3'b110; + 1'b1: nstate = 3'b111; + endcase + end + end + endcase + end + +endmodule diff --git a/designs/encrypted_ip/des3_perf/top.v b/designs/encrypted_ip/des3_perf/top.v new file mode 100644 index 000000000..4f946ef53 --- /dev/null +++ b/designs/encrypted_ip/des3_perf/top.v @@ -0,0 +1,68 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 07/11/2017 04:14:44 PM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module top( + input clk, + input reset, // Not used + input [15:0] sw, + input [4:0] btn, // Not used + output [15:0] led, + output [6:0] seg, // Not used + output dp, // Not used + output [7:0] an // Not used + ); + + + assign seg = {btn, reset, 1'b0}; + assign dp = 1'b0; + assign an = 8'b00000000; + // This is a very simple top module that instantiates a des3_perf module. + // I anticipate that we may find a perfect match with this simple design + // In the future, I hope to add viterbi modules to the top module and + // will inspect if and how much this changes the instantiated des3_perf. + + wire [63:0] desOut; + wire [63:0] desIn; + wire [55:0] key1; + wire [55:0] key2; + wire [55:0] key3; + wire decrypt; + + assign desIn = {4{sw[15:0]}}; + assign key1 = desIn[63:8]; + assign key2 = desIn[60:5]; + assign key3 = desIn[55:0]; + assign decrypt = desIn[23]; + + des3_perf des3_perf_0( + .desOut(desOut), + .desIn(desIn), + .key1(key1), + .key2(key2), + .key3(key3), + .decrypt(decrypt), + .clk(clk) + ); + + assign led[15:0] = {16{^desOut}}; + +endmodule diff --git a/designs/encrypted_ip/des3_perf/viterbi_tx_rx.v b/designs/encrypted_ip/des3_perf/viterbi_tx_rx.v new file mode 100644 index 000000000..6d9b5ec0c --- /dev/null +++ b/designs/encrypted_ip/des3_perf/viterbi_tx_rx.v @@ -0,0 +1,64 @@ +module viterbi_tx_rx( + clk, + rst, + encoder_i, + enable_encoder_i, + decoder_o +); + input clk; + input rst; + input encoder_i; + input enable_encoder_i; + output decoder_o; + + wire [1:0] encoder_o; + + + reg [3:0] error_counter; + reg [1:0] encoder_o_reg; + + reg enable_decoder_in; + wire valid_encoder_o; + + + + always @ (posedge clk or negedge rst) + begin + if(rst==1'b0) + begin + error_counter <= 4'd0; + encoder_o_reg <= 2'b00; + enable_decoder_in <= 1'b0; + end + else + begin + enable_decoder_in <= valid_encoder_o; + encoder_o_reg <= 2'b00; + error_counter <= error_counter + 4'd1; + if(error_counter==4'b1111) + encoder_o_reg <= {~encoder_o[1],encoder_o[0]}; + else + encoder_o_reg <= {encoder_o[1],encoder_o[0]}; + end + end + + + encoder encoder1 + ( + .clk(clk), + .rst(rst), + .enable_i(enable_encoder_i), + .d_in(encoder_i), + .valid_o(valid_encoder_o), + .d_out(encoder_o) + ); + + decoder decoder1 + ( + .clk(clk), + .rst(rst), + .enable(enable_decoder_in), + .d_in(encoder_o_reg), + .d_out(decoder_o) + ); +endmodule diff --git a/designs/encrypted_ip/mul_display/configurable_display.v b/designs/encrypted_ip/mul_display/configurable_display.v new file mode 100644 index 000000000..6faa2e430 --- /dev/null +++ b/designs/encrypted_ip/mul_display/configurable_display.v @@ -0,0 +1,151 @@ +`timescale 1ns / 1ps + +// IP that controls the seven segment display using the buttons + +module configurable_display( + input clk, + input reset, + input [4:0] buttons, + output [6:0] segments, + output dot_point, + output [7:0] anodes + ); + + // Mapping of button_value to 7-segment display + reg [6:0] seven_seg_map [0:15] = { + 7'b1000000, // 0 + 7'b1111001, // 1 + 7'b0100100, // 2 + 7'b0110000, // 3 + 7'b0011001, // 4 + 7'b0010010, // 5 + 7'b0000010, // 6 + 7'b1111000, // 7 + 7'b0000000, // 8 + 7'b0010000, // 9 + 7'b0001000, // A + 7'b0000011, // b + 7'b1000110, // C + 7'b0100001, // d + 7'b0000110, // E + 7'b0001110 // F + }; + + reg [4:0] buttons_buf; + + always @(posedge clk) + if (!reset) + buttons_buf <= 0; + else + buttons_buf <= buttons; + + + reg [4:0] final_button_values; + + + // Copied from ChatGPT-4 + + reg [4:0] button_buf_prev; + reg [4:0] button_buf_stable; + reg [4:0] button_buf_edge; + reg [19:0] counters[4:0]; + + integer i; + + localparam DEBOUNCE_COUNT = 1000000; + + always @(posedge clk) begin + if (!reset) begin + button_buf_prev <= 0; + button_buf_stable <= 0; + button_buf_edge <= 0; + final_button_values <= 0; + for (i = 0; i < 5; i = i + 1) begin + counters[i] <= 0; + end + end else begin + for (i = 0; i < 5; i = i + 1) begin + if (buttons_buf[i] != button_buf_prev[i]) begin + counters[i] <= counters[i] + 1; + if (counters[i] >= DEBOUNCE_COUNT) begin + button_buf_edge[i] <= !button_buf_edge[i]; + button_buf_stable[i] <= buttons_buf[i]; + counters[i] <= 0; + end + end else begin + counters[i] <= 0; + end + end + final_button_values <= (button_buf_stable ^ button_buf_prev) & button_buf_edge; + button_buf_prev <= button_buf_stable; + end + end + + // End copy + + reg [6:0] segments_buf; + reg dot_point_buf; + reg [7:0] anodes_buf; + reg [3:0] values [0:7]; // The current numerical value of each digit on the display + reg [2:0] selection; // Which digit on the display is currently selected + + assign segments = segments_buf; + assign dot_point = dot_point_buf; + assign anodes = anodes_buf; + + // Cycle through which digit is selected + always @(posedge clk) + if (!reset || final_button_values == 5'b00001) + selection <= 0; + else if (final_button_values == 5'b00100 && selection != 7) + selection <= selection + 1; + else if (final_button_values == 5'b01000 && selection != 0) + selection <= selection - 1; + else + selection <= selection; + + // Increment or decrement selected digit when buttons pressed + always @(posedge clk) + for (i = 0; i < 8; i = i + 1) + if (!reset || final_button_values == 5'b00001) + values[i] <= 0; + else if (final_button_values == 5'b00010 && i == selection) // Button up + values[i] <= values[i] + 1; + else if (final_button_values == 5'b10000 && i == selection) // Button down + values[i] <= values[i] - 1; + else + values[i] <= values[i]; + + reg [15:0] display_cycle_counter; + + always @(posedge clk) + if (!reset) + display_cycle_counter <= 0; + else + display_cycle_counter <= display_cycle_counter + 1; + + // SEGMENT VALUES + always @(posedge clk) + if (!reset || final_button_values == 5'b00001) + segments_buf <= seven_seg_map[0]; + else + segments_buf <= seven_seg_map[values[display_cycle_counter[15:13]]]; + + // DOT POINT VALUE + always @(posedge clk) + if (!reset || final_button_values == 5'b00001) + dot_point_buf <= 1; + else if (display_cycle_counter[15:13] == selection) + dot_point_buf <= 0; + else + dot_point_buf <= 1; + + // ANODE VALUES + always @(posedge clk) + if (!reset || final_button_values == 5'b00001) + anodes_buf <= ~1; + else + anodes_buf <= ~(1 << display_cycle_counter[15:13]); + + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/mul_display/design.yaml b/designs/encrypted_ip/mul_display/design.yaml new file mode 100644 index 000000000..81adb6346 --- /dev/null +++ b/designs/encrypted_ip/mul_display/design.yaml @@ -0,0 +1,12 @@ +top: top + +encrypted_ip: + ip: + - definition: "int_mul_8" + instances: + - "int_mul_inst" + - definition: "configurable_display" + instances: + - "display_inst" + + user_files: ["top.v"] \ No newline at end of file diff --git a/designs/encrypted_ip/mul_display/int_mul_8.v b/designs/encrypted_ip/mul_display/int_mul_8.v new file mode 100644 index 000000000..186c29208 --- /dev/null +++ b/designs/encrypted_ip/mul_display/int_mul_8.v @@ -0,0 +1,34 @@ +`timescale 1ns / 1ps + +// IP that controls the LEDs using the switches + +module int_mul_8( + input clk, + input reset, + input [7:0] num1, + input [7:0] num2, + output [15:0] result + ); + + reg [7:0] num1_buf; + reg [7:0] num2_buf; + + always @(posedge clk) + if (!reset) begin + num1_buf <= 0; + num2_buf <= 0; + end else begin + num1_buf <= num1; + num2_buf <= num2; + end + + reg [15:0] result_buf; + + assign result = result_buf; + + always @(posedge clk) + if (!reset) + result_buf <= 0; + else + result_buf <= num1_buf * num2_buf; +endmodule diff --git a/designs/encrypted_ip/mul_display/top.v b/designs/encrypted_ip/mul_display/top.v new file mode 100644 index 000000000..dec075911 --- /dev/null +++ b/designs/encrypted_ip/mul_display/top.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps + +// Top level user-space module that instantiates IP + +module top( + input clk, + input reset, + input [15:0] sw, + input [4:0] btn, + output [15:0] led, + output [6:0] seg, + output dp, + output [7:0] an + ); + + int_mul_8 int_mul_inst ( + .clk(clk), + .reset(reset), + .num1(sw[7:0]), + .num2(sw[15:8]), + .result(led[15:0]) + ); + + configurable_display display_inst ( + .clk(clk), + .reset(reset), + .buttons(btn), + .segments(seg), + .dot_point(dp), + .anodes(an) + ); + +endmodule diff --git a/designs/encrypted_ip/uart2spi/top.v b/designs/encrypted_ip/uart2spi/top.v index 5e2645966..88d74969c 100644 --- a/designs/encrypted_ip/uart2spi/top.v +++ b/designs/encrypted_ip/uart2spi/top.v @@ -58,22 +58,22 @@ module top( wire [3:0] cs_n; uart2spi uart2spi_0 ( - concat[0], - clk, - concat[0], - concat[1], - concat[2], - concat[4:3], - concat[16:5], - frm_error, - par_error, - baud_clk_16x, - concat[16], - txd, - sck, - so, - concat[17], - cs_n + .line_reset_n(concat[0]), + .line_clk(clk), + .cfg_tx_enable(concat[0]), + .cfg_rx_enable(concat[1]), + .cfg_stop_bit(concat[2]), + .cfg_pri_mod(concat[4:3]), + .cfg_baud_16x(concat[16:5]), + .frm_error(frm_error), + .par_error(par_error), + .baud_clk_16x(baud_clk_16x), + .rxd(concat[16]), + .txd(txd), + .sck(sck), + .so(so), + .si(concat[17]), + .cs_n(cs_n) ); wire red; assign red = top_valid_out ^ frm_error ^ par_error ^ baud_clk_16x ^ txd ^ sck ^ so ^ (^cs_n); From 0acbcaed9697a80c153584d104fd96d8a0756738 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Wed, 13 Dec 2023 09:59:42 -0700 Subject: [PATCH 19/25] simplify logic --- bfasst/utils/vivado.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/bfasst/utils/vivado.py b/bfasst/utils/vivado.py index c924c9408..1debe4f5e 100644 --- a/bfasst/utils/vivado.py +++ b/bfasst/utils/vivado.py @@ -40,11 +40,10 @@ def parse_hierarchical_utilization(path): else: if spaces > prev_spaces: current_path /= cols[0].strip() - elif spaces == prev_spaces: - current_path = current_path.parent / cols[0].strip() else: - levels_up = (prev_spaces - spaces) // 2 + # Belongs to a parent module current_path = current_path.parent + levels_up = (prev_spaces - spaces) // 2 for _ in range(levels_up): current_path = current_path.parent current_path /= cols[0].strip() From 3ba8706ec381913d7fb06cc9585ee13c258c4f90 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Wed, 13 Dec 2023 10:02:46 -0700 Subject: [PATCH 20/25] Update encrypted ip --- third_party/encrypted_ip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/third_party/encrypted_ip b/third_party/encrypted_ip index 21ae601b9..b82ae8f0c 160000 --- a/third_party/encrypted_ip +++ b/third_party/encrypted_ip @@ -1 +1 @@ -Subproject commit 21ae601b93eb77a3a240bd9e66679062893c8698 +Subproject commit b82ae8f0c8f86184be2111729ed2b250173da528 From 9782afd5cee2eb919f2ad5ea72bb1b1c3dbc13bb Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Sun, 17 Dec 2023 15:34:16 -0700 Subject: [PATCH 21/25] update --- bfasst/external_tools.py | 5 +++++ bfasst/tools/common/vivado_rules.ninja.mustache | 2 +- bfasst/tools/synth/vivado_synth.py | 2 -- bfasst/tools/synth/vivado_synth.tcl.mustache | 16 ++++++++-------- external_tools.mk | 11 ++++++++++- scripts/run.py | 2 +- tests/fccm24_encrypted_ip.yaml | 2 +- 7 files changed, 26 insertions(+), 14 deletions(-) diff --git a/bfasst/external_tools.py b/bfasst/external_tools.py index 5216c67fc..9136ad1a5 100644 --- a/bfasst/external_tools.py +++ b/bfasst/external_tools.py @@ -11,6 +11,7 @@ from bfasst.config import PART, VIVADO_BIN_PATH from bfasst.paths import ( + ENCRYPTED_IP_PATH, RAPIDWRIGHT_PATH, ROOT_PATH, THIRD_PARTY_PATH, @@ -61,6 +62,10 @@ def check_yosys(): return (YOSYS_PATH / "yosys").is_file() +def check_encrypted_ip(): + return (ENCRYPTED_IP_PATH / "README.md").is_file() + + ################################################################################ # Command Line Interface ################################################################################ diff --git a/bfasst/tools/common/vivado_rules.ninja.mustache b/bfasst/tools/common/vivado_rules.ninja.mustache index 109fd7450..4469d78ff 100644 --- a/bfasst/tools/common/vivado_rules.ninja.mustache +++ b/bfasst/tools/common/vivado_rules.ninja.mustache @@ -1,5 +1,5 @@ rule vivado - command = export tempjou=$$(mktemp); export templog=$$(mktemp); cd $cwd && {{ utils_path }}/retry.sh {{ vivado_path }} -mode batch -journal $$tempjou -log $$templog -source $in >&- && mv $$tempjou $journal && mv $$templog $log + command = cd $cwd && {{ utils_path }}/retry.sh {{ vivado_path }} -mode batch -journal $journal -log $log -source $in >&- 2>&- description = vivado $in rule vivado_ioparse diff --git a/bfasst/tools/synth/vivado_synth.py b/bfasst/tools/synth/vivado_synth.py index f3a80ad32..eb89464f4 100644 --- a/bfasst/tools/synth/vivado_synth.py +++ b/bfasst/tools/synth/vivado_synth.py @@ -13,8 +13,6 @@ class VivadoSynth(SynthTool): def __init__(self, flow, design_path, ooc=False, synth_options="", top=None): super().__init__(flow, design_path, top=top, ooc=ooc) self.synth_options = synth_options - if ooc: - self.synth_options += " -mode out_of_context" self._my_dir_path = pathlib.Path(__file__).parent if ooc: self.synth_options += " -mode out_of_context" diff --git a/bfasst/tools/synth/vivado_synth.tcl.mustache b/bfasst/tools/synth/vivado_synth.tcl.mustache index 579c285df..321b8b3ef 100644 --- a/bfasst/tools/synth/vivado_synth.tcl.mustache +++ b/bfasst/tools/synth/vivado_synth.tcl.mustache @@ -1,4 +1,3 @@ -if { [ catch { set_part {{ part }} {{#verilog}} @@ -20,16 +19,17 @@ read_vhdl -library {{1}} {{0}} synth_design -top {{ top }} {{ synth_args }} {{#io}} place_ports - +report_io -force -file {{ . }} {{/io}} + write_edif -force {{ synth_output }}/viv_synth.edf -write_checkpoint -force -file {{ synth_output }}/synth.dcp write_verilog -force -file {{ synth_output }}/viv_synth.v report_utilization -file {{ synth_output }}/utilization.txt -hierarchical -{{#io}} -report_io -force -file {{ . }} +file delete {{ synth_output }}/synth.dcp +write_checkpoint -file {{ synth_output }}/synth.dcp +if { ! [ file exists {{ synth_output }}/synth.dcp ] } { + exit 1 +} +exit -{{/io}} -} ] } { exit 1 } -exit \ No newline at end of file diff --git a/external_tools.mk b/external_tools.mk index 95c979412..f58a1d926 100644 --- a/external_tools.mk +++ b/external_tools.mk @@ -71,4 +71,13 @@ install_yosys: install_wafove: $(IN_ENV) python -m pip install -e third_party/WaFoVe - $(IN_ENV) cd third_party/WaFoVe && make build \ No newline at end of file + $(IN_ENV) cd third_party/WaFoVe && make build + +################################################################################ +# Encrypted IP +################################################################################ + +install_encrypted_ip: + git submodule init third_party/encrypted_ip + git submodule update third_party/encrypted_ip + $(IN_ENV) pip install -r third_party/encrypted_ip \ No newline at end of file diff --git a/scripts/run.py b/scripts/run.py index 30c4b7268..9bb5289ee 100644 --- a/scripts/run.py +++ b/scripts/run.py @@ -134,4 +134,4 @@ def parse_args(args): check_tools=not parsed_args.no_tool_checks, ) else: - ApplicationRunner().run_yaml(parsed_args.yaml, check_tools=parsed_args.no_tool_checks) + ApplicationRunner().run_yaml(parsed_args.yaml, check_tools=not parsed_args.no_tool_checks) diff --git a/tests/fccm24_encrypted_ip.yaml b/tests/fccm24_encrypted_ip.yaml index 2f0aa5c33..93d645798 100644 --- a/tests/fccm24_encrypted_ip.yaml +++ b/tests/fccm24_encrypted_ip.yaml @@ -1,4 +1,4 @@ flow: EncryptedIP -design_dirs: +designs: - encrypted_ip/ \ No newline at end of file From 68353294b0494bfb7b15e29f7c16954d67f50ee2 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Sun, 17 Dec 2023 21:37:26 -0700 Subject: [PATCH 22/25] runtimes --- bfasst/tools/ip/loader_vivado.tcl.mustache | 18 ++++++------------ bfasst/tools/synth/vivado_synth.tcl.mustache | 7 +++++++ external_tools.mk | 2 +- 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/bfasst/tools/ip/loader_vivado.tcl.mustache b/bfasst/tools/ip/loader_vivado.tcl.mustache index 0f9963930..1899e553b 100644 --- a/bfasst/tools/ip/loader_vivado.tcl.mustache +++ b/bfasst/tools/ip/loader_vivado.tcl.mustache @@ -6,32 +6,26 @@ open_checkpoint {{ loader_impl_dcp }} read_checkpoint -cell "static_top_i/top_0" {{ user_synth_dcp }} # Step 4: Place and route -puts "Time starting implementing partition DTIMING" -puts [exec date] +set timen [exec date] +puts "Loader impl start time: $timen" place_design route_design -puts "Time ending implementing partition DTIMING" -puts [exec date] # Step 4: Write out implemented checkpoints write_checkpoint {{ final }}.dcp -force write_edif {{ final }}.edif -force report_utilization -file {{ final }}_utilization_report.txt -hierarchical -puts "Time starting writing bitstream DTIMING" -puts [exec date] - - # Step 5.1: Bitstream for timing purposes write_bitstream -bin_file -cell "static_top_i/top_0" {{ user_partial_bitstream }} -force - -puts "Time starting writing bitstreams not applicable for timing DTIMING" -puts [exec date] - # Step 5.2: Write out full bitstream write_bitstream -bin_file {{ final }}_unencrypted.bit -force +set timen [exec date] +puts "Loader impl end time: $timen" + + #Step 6: Write out encrypted bitstream set_property BITSTREAM.ENCRYPTION.ENCRYPT YES [get_designs checkpoint_implemented_loader] set_property BITSTREAM.ENCRYPTION.ENCRYPTKEYSELECT EFUSE [get_designs checkpoint_implemented_loader] diff --git a/bfasst/tools/synth/vivado_synth.tcl.mustache b/bfasst/tools/synth/vivado_synth.tcl.mustache index 321b8b3ef..501812c41 100644 --- a/bfasst/tools/synth/vivado_synth.tcl.mustache +++ b/bfasst/tools/synth/vivado_synth.tcl.mustache @@ -16,7 +16,14 @@ read_vhdl {{ . }} read_vhdl -library {{1}} {{0}} {{/vhdl_libs}} +set timen [exec date] + +puts "Synth start time: $timen" + synth_design -top {{ top }} {{ synth_args }} + +set timen [exec date] +puts "Synth start time: $timen" {{#io}} place_ports report_io -force -file {{ . }} diff --git a/external_tools.mk b/external_tools.mk index f58a1d926..13118c449 100644 --- a/external_tools.mk +++ b/external_tools.mk @@ -80,4 +80,4 @@ install_wafove: install_encrypted_ip: git submodule init third_party/encrypted_ip git submodule update third_party/encrypted_ip - $(IN_ENV) pip install -r third_party/encrypted_ip \ No newline at end of file + $(IN_ENV) pip install -r third_party/encrypted_ip/requirements.txt \ No newline at end of file From 14afb6ddd00a6d1272a94d8f275befeff79e29b0 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Wed, 20 Dec 2023 11:25:07 -0700 Subject: [PATCH 23/25] designs --- bfasst/flows/encrypted_ip.py | 6 + designs/base/pic/top.v | 1 + designs/base/simon_core/top.v | 34 +- designs/encrypted_ip/cpu8080/CONTROL.v | 472 +++++ designs/encrypted_ip/cpu8080/CRYPTO_PATH.v | 155 ++ designs/encrypted_ip/cpu8080/KEY_SCHED.v | 193 ++ designs/encrypted_ip/cpu8080/RF.v | 173 ++ designs/encrypted_ip/cpu8080/SKG.v | 470 +++++ designs/encrypted_ip/cpu8080/WF.v | 123 ++ designs/encrypted_ip/cpu8080/WKG.v | 129 ++ designs/encrypted_ip/cpu8080/common.vhd | 51 + designs/encrypted_ip/cpu8080/cpu8080.v | 1681 +++++++++++++++++ designs/encrypted_ip/cpu8080/dds.vhd | 91 + designs/encrypted_ip/cpu8080/dds_sinus.vhd | 159 ++ designs/encrypted_ip/cpu8080/delay.vhd | 52 + designs/encrypted_ip/cpu8080/design.yaml | 26 + .../encrypted_ip/cpu8080/fixed_point_sqrt.vhd | 177 ++ designs/encrypted_ip/cpu8080/graphiti.vhd | 318 ++++ designs/encrypted_ip/cpu8080/hight.v | 181 ++ designs/encrypted_ip/cpu8080/lfsr_pkg.vhd | 405 ++++ designs/encrypted_ip/cpu8080/lfsr_randgen.vhd | 89 + designs/encrypted_ip/cpu8080/myfir.vhd | 66 + designs/encrypted_ip/cpu8080/paltimer.vhd | 211 +++ designs/encrypted_ip/cpu8080/rgb2yuv.vhd | 169 ++ designs/encrypted_ip/cpu8080/top.v | 121 ++ designs/encrypted_ip/pic/basic_component.vhd | 63 + designs/encrypted_ip/pic/basic_size.vhd | 64 + designs/encrypted_ip/pic/design.yaml | 25 + designs/encrypted_ip/pic/down_clocking_even.v | 37 + designs/encrypted_ip/pic/down_clocking_odd.v | 69 + designs/encrypted_ip/pic/minus_one.v | 122 ++ designs/encrypted_ip/pic/pci_mini.v | 626 ++++++ designs/encrypted_ip/pic/pic.vhd | 250 +++ designs/encrypted_ip/pic/potato.vhd | 150 ++ designs/encrypted_ip/pic/pp_alu.vhd | 58 + .../encrypted_ip/pic/pp_alu_control_unit.vhd | 141 ++ designs/encrypted_ip/pic/pp_alu_mux.vhd | 49 + designs/encrypted_ip/pic/pp_comparator.vhd | 43 + designs/encrypted_ip/pic/pp_constants.vhd | 15 + designs/encrypted_ip/pic/pp_control_unit.vhd | 220 +++ designs/encrypted_ip/pic/pp_core.vhd | 454 +++++ designs/encrypted_ip/pic/pp_counter.vhd | 40 + designs/encrypted_ip/pic/pp_csr.vhd | 127 ++ designs/encrypted_ip/pic/pp_csr_alu.vhd | 43 + designs/encrypted_ip/pic/pp_csr_unit.vhd | 294 +++ designs/encrypted_ip/pic/pp_decode.vhd | 140 ++ designs/encrypted_ip/pic/pp_execute.vhd | 541 ++++++ designs/encrypted_ip/pic/pp_fetch.vhd | 89 + designs/encrypted_ip/pic/pp_icache.vhd | 293 +++ designs/encrypted_ip/pic/pp_imm_decoder.vhd | 35 + designs/encrypted_ip/pic/pp_memory.vhd | 154 ++ designs/encrypted_ip/pic/pp_register_file.vhd | 55 + designs/encrypted_ip/pic/pp_types.vhd | 70 + designs/encrypted_ip/pic/pp_utilities.vhd | 94 + designs/encrypted_ip/pic/pp_wb_adapter.vhd | 126 ++ designs/encrypted_ip/pic/pp_wb_arbiter.vhd | 100 + designs/encrypted_ip/pic/pp_writeback.vhd | 71 + designs/encrypted_ip/pic/pwm.v | 219 +++ designs/encrypted_ip/pic/quadratic_func.vhd | 203 ++ designs/encrypted_ip/pic/top.v | 166 ++ .../Simon_bit_serial_datapath_FPGA.v | 225 +++ .../Simon_bit_serial_key_expansion_FPGA.v | 241 +++ designs/encrypted_ip/simon_core/ac_behave.vhd | 35 + .../encrypted_ip/simon_core/alu_behave.vhd | 37 + .../encrypted_ip/simon_core/b_reg_behave.vhd | 31 + .../simon_core/control_unit_fsm.vhd | 149 ++ designs/encrypted_ip/simon_core/design.yaml | 19 + .../encrypted_ip/simon_core/f_permutation_h.v | 69 + .../encrypted_ip/simon_core/f_permutation_l.v | 69 + designs/encrypted_ip/simon_core/ir_behave.vhd | 47 + .../encrypted_ip/simon_core/irdec_behave.vhd | 43 + .../encrypted_ip/simon_core/mar_behave.vhd | 31 + designs/encrypted_ip/simon_core/o_behave.vhd | 30 + designs/encrypted_ip/simon_core/padder1_h.v | 33 + designs/encrypted_ip/simon_core/padder1_l.v | 37 + designs/encrypted_ip/simon_core/padder_h.v | 88 + designs/encrypted_ip/simon_core/padder_l.v | 88 + designs/encrypted_ip/simon_core/pc_behave.vhd | 46 + .../simon_core/random_pulse_generator.v | 53 + designs/encrypted_ip/simon_core/rconst.v | 34 + designs/encrypted_ip/simon_core/rconst2in1.v | 46 + .../simon_core/rom_16_8_behave.vhd | 58 + designs/encrypted_ip/simon_core/round.v | 171 ++ designs/encrypted_ip/simon_core/round2in1.v | 284 +++ designs/encrypted_ip/simon_core/sap.vhd | 265 +++ .../simon_core/sha3_high_throughput.v | 98 + .../simon_core/sha3_low_throughput.v | 100 + designs/encrypted_ip/simon_core/simon_core.v | 45 + designs/encrypted_ip/simon_core/top.v | 125 ++ 89 files changed, 13379 insertions(+), 17 deletions(-) create mode 100644 designs/encrypted_ip/cpu8080/CONTROL.v create mode 100644 designs/encrypted_ip/cpu8080/CRYPTO_PATH.v create mode 100644 designs/encrypted_ip/cpu8080/KEY_SCHED.v create mode 100644 designs/encrypted_ip/cpu8080/RF.v create mode 100644 designs/encrypted_ip/cpu8080/SKG.v create mode 100644 designs/encrypted_ip/cpu8080/WF.v create mode 100644 designs/encrypted_ip/cpu8080/WKG.v create mode 100644 designs/encrypted_ip/cpu8080/common.vhd create mode 100644 designs/encrypted_ip/cpu8080/cpu8080.v create mode 100644 designs/encrypted_ip/cpu8080/dds.vhd create mode 100644 designs/encrypted_ip/cpu8080/dds_sinus.vhd create mode 100644 designs/encrypted_ip/cpu8080/delay.vhd create mode 100644 designs/encrypted_ip/cpu8080/design.yaml create mode 100644 designs/encrypted_ip/cpu8080/fixed_point_sqrt.vhd create mode 100644 designs/encrypted_ip/cpu8080/graphiti.vhd create mode 100644 designs/encrypted_ip/cpu8080/hight.v create mode 100644 designs/encrypted_ip/cpu8080/lfsr_pkg.vhd create mode 100644 designs/encrypted_ip/cpu8080/lfsr_randgen.vhd create mode 100644 designs/encrypted_ip/cpu8080/myfir.vhd create mode 100644 designs/encrypted_ip/cpu8080/paltimer.vhd create mode 100644 designs/encrypted_ip/cpu8080/rgb2yuv.vhd create mode 100644 designs/encrypted_ip/cpu8080/top.v create mode 100644 designs/encrypted_ip/pic/basic_component.vhd create mode 100644 designs/encrypted_ip/pic/basic_size.vhd create mode 100644 designs/encrypted_ip/pic/design.yaml create mode 100644 designs/encrypted_ip/pic/down_clocking_even.v create mode 100644 designs/encrypted_ip/pic/down_clocking_odd.v create mode 100644 designs/encrypted_ip/pic/minus_one.v create mode 100644 designs/encrypted_ip/pic/pci_mini.v create mode 100644 designs/encrypted_ip/pic/pic.vhd create mode 100644 designs/encrypted_ip/pic/potato.vhd create mode 100644 designs/encrypted_ip/pic/pp_alu.vhd create mode 100644 designs/encrypted_ip/pic/pp_alu_control_unit.vhd create mode 100644 designs/encrypted_ip/pic/pp_alu_mux.vhd create mode 100644 designs/encrypted_ip/pic/pp_comparator.vhd create mode 100644 designs/encrypted_ip/pic/pp_constants.vhd create mode 100644 designs/encrypted_ip/pic/pp_control_unit.vhd create mode 100644 designs/encrypted_ip/pic/pp_core.vhd create mode 100644 designs/encrypted_ip/pic/pp_counter.vhd create mode 100644 designs/encrypted_ip/pic/pp_csr.vhd create mode 100644 designs/encrypted_ip/pic/pp_csr_alu.vhd create mode 100644 designs/encrypted_ip/pic/pp_csr_unit.vhd create mode 100644 designs/encrypted_ip/pic/pp_decode.vhd create mode 100644 designs/encrypted_ip/pic/pp_execute.vhd create mode 100644 designs/encrypted_ip/pic/pp_fetch.vhd create mode 100644 designs/encrypted_ip/pic/pp_icache.vhd create mode 100644 designs/encrypted_ip/pic/pp_imm_decoder.vhd create mode 100644 designs/encrypted_ip/pic/pp_memory.vhd create mode 100644 designs/encrypted_ip/pic/pp_register_file.vhd create mode 100644 designs/encrypted_ip/pic/pp_types.vhd create mode 100644 designs/encrypted_ip/pic/pp_utilities.vhd create mode 100644 designs/encrypted_ip/pic/pp_wb_adapter.vhd create mode 100644 designs/encrypted_ip/pic/pp_wb_arbiter.vhd create mode 100644 designs/encrypted_ip/pic/pp_writeback.vhd create mode 100644 designs/encrypted_ip/pic/pwm.v create mode 100644 designs/encrypted_ip/pic/quadratic_func.vhd create mode 100644 designs/encrypted_ip/pic/top.v create mode 100644 designs/encrypted_ip/simon_core/Simon_bit_serial_datapath_FPGA.v create mode 100644 designs/encrypted_ip/simon_core/Simon_bit_serial_key_expansion_FPGA.v create mode 100644 designs/encrypted_ip/simon_core/ac_behave.vhd create mode 100644 designs/encrypted_ip/simon_core/alu_behave.vhd create mode 100644 designs/encrypted_ip/simon_core/b_reg_behave.vhd create mode 100644 designs/encrypted_ip/simon_core/control_unit_fsm.vhd create mode 100644 designs/encrypted_ip/simon_core/design.yaml create mode 100644 designs/encrypted_ip/simon_core/f_permutation_h.v create mode 100644 designs/encrypted_ip/simon_core/f_permutation_l.v create mode 100644 designs/encrypted_ip/simon_core/ir_behave.vhd create mode 100644 designs/encrypted_ip/simon_core/irdec_behave.vhd create mode 100644 designs/encrypted_ip/simon_core/mar_behave.vhd create mode 100644 designs/encrypted_ip/simon_core/o_behave.vhd create mode 100644 designs/encrypted_ip/simon_core/padder1_h.v create mode 100644 designs/encrypted_ip/simon_core/padder1_l.v create mode 100644 designs/encrypted_ip/simon_core/padder_h.v create mode 100644 designs/encrypted_ip/simon_core/padder_l.v create mode 100644 designs/encrypted_ip/simon_core/pc_behave.vhd create mode 100644 designs/encrypted_ip/simon_core/random_pulse_generator.v create mode 100644 designs/encrypted_ip/simon_core/rconst.v create mode 100644 designs/encrypted_ip/simon_core/rconst2in1.v create mode 100644 designs/encrypted_ip/simon_core/rom_16_8_behave.vhd create mode 100644 designs/encrypted_ip/simon_core/round.v create mode 100644 designs/encrypted_ip/simon_core/round2in1.v create mode 100644 designs/encrypted_ip/simon_core/sap.vhd create mode 100644 designs/encrypted_ip/simon_core/sha3_high_throughput.v create mode 100644 designs/encrypted_ip/simon_core/sha3_low_throughput.v create mode 100644 designs/encrypted_ip/simon_core/simon_core.v create mode 100644 designs/encrypted_ip/simon_core/top.v diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py index 7b84ba9d0..bd7e28635 100644 --- a/bfasst/flows/encrypted_ip.py +++ b/bfasst/flows/encrypted_ip.py @@ -102,8 +102,14 @@ def post_execute(self): "Instance": instance, "LUTs-Regular": regular_data[instance]["Total LUTs"], "FFs-Regular": regular_data[instance]["FFs"], + "RAMB-Regular": regular_data[instance]["RAMB36"] + + regular_data[instance]["RAMB18"], + "DSP-Regular": regular_data[instance]["DSP Blocks"], "LUTs-Encrypted": encrypted_data[instance]["Total LUTs"], "FFs-Encrypted": encrypted_data[instance]["FFs"], + "RAMB-Encrypted": encrypted_data[instance]["RAMB36"] + + encrypted_data[instance]["RAMB18"], + "DSP-Encrypted": encrypted_data[instance]["DSP Blocks"], } ) df = pd.concat( diff --git a/designs/base/pic/top.v b/designs/base/pic/top.v index 6883ffabe..df59128f4 100644 --- a/designs/base/pic/top.v +++ b/designs/base/pic/top.v @@ -56,6 +56,7 @@ module top( assign led[7] = ^pwm_o_wb_data; assign led[8] = pwm_o_wb_ack ^ pwm_o_pwm; assign led[9] = ^y_out; + assign led[10] = INTR_O; pci_mini pci_mini_0( diff --git a/designs/base/simon_core/top.v b/designs/base/simon_core/top.v index ad0a60c50..35fcc870b 100644 --- a/designs/base/simon_core/top.v +++ b/designs/base/simon_core/top.v @@ -45,12 +45,12 @@ module top( .q(q) ); - sap sap_0( - .clk(clk), - .clr(btnCpuReset), - .hlt(1'b0), - .q3(q3) - ); + // sap sap_0( + // .clk(clk), + // .clr(btnCpuReset), + // .hlt(1'b0), + // .q3(q3) + // ); sha3_high_throughput sha3_high_throughput_0( .clk(clk), @@ -64,17 +64,17 @@ module top( .out_ready(sha3_high_out_ready) ); - sha3_low_throughput sha3_low_throughput_0( - .clk(clk), - .reset(btnCpuReset), - .in(total_in[49:18]), - .in_ready(sw[0]), - .is_last(sw[1]), - .byte_num(JB[1:0]), - .buffer_full(sha3_low_buffer_full), - .out(sha3_low_out), - .out_ready(sha3_low_out_ready) - ); + // sha3_low_throughput sha3_low_throughput_0( + // .clk(clk), + // .reset(btnCpuReset), + // .in(total_in[49:18]), + // .in_ready(sw[0]), + // .is_last(sw[1]), + // .byte_num(JB[1:0]), + // .buffer_full(sha3_low_buffer_full), + // .out(sha3_low_out), + // .out_ready(sha3_low_out_ready) + // ); simon_core simon_core_0( .clk(clk), diff --git a/designs/encrypted_ip/cpu8080/CONTROL.v b/designs/encrypted_ip/cpu8080/CONTROL.v new file mode 100644 index 000000000..85de521cb --- /dev/null +++ b/designs/encrypted_ip/cpu8080/CONTROL.v @@ -0,0 +1,472 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Control module for HIGHT Crypto Core //// +//// //// +//// This file is part of the HIGHT Crypto Core project //// +//// http://github.com/OpenSoCPlus/hight_crypto_core //// +//// http://www.opencores.org/project,hight //// +//// //// +//// Description //// +//// __description__ //// +//// //// +//// Author(s): //// +//// - JoonSoo Ha, json.ha@gmail.com //// +//// - Younjoo Kim, younjookim.kr@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module CONTROL( + rstn , + clk , + + i_mk_rdy , + i_post_rdy , + i_text_val , + + o_rdy , + o_text_done , + + o_xf_sel , + o_rf_final , + + o_key_sel , + o_rnd_idx , + o_wf_post_pre +); + + +//===================================== +// +// PARAMETERS +// +//===================================== +localparam S_IDLE = 6'b1_10000; +localparam S_KEY_CONFIG = 6'b1_00000; +localparam S_RDY = 6'b0_00000; +localparam S_WF1 = 6'b0_00001; +localparam S_RF1 = 6'b0_00010; +localparam S_RF2 = 6'b0_00011; +localparam S_RF3 = 6'b0_00100; +localparam S_RF4 = 6'b0_00101; +localparam S_RF5 = 6'b0_00110; +localparam S_RF6 = 6'b0_00111; +localparam S_RF7 = 6'b0_01000; +localparam S_RF8 = 6'b0_01001; +localparam S_RF9 = 6'b0_01010; +localparam S_RF10 = 6'b0_01011; +localparam S_RF11 = 6'b0_01100; +localparam S_RF12 = 6'b0_01101; +localparam S_RF13 = 6'b0_01110; +localparam S_RF14 = 6'b0_01111; +localparam S_RF15 = 6'b0_10000; +localparam S_RF16 = 6'b0_10001; +localparam S_RF17 = 6'b0_10010; +localparam S_RF18 = 6'b0_10011; +localparam S_RF19 = 6'b0_10100; +localparam S_RF20 = 6'b0_10101; +localparam S_RF21 = 6'b0_10110; +localparam S_RF22 = 6'b0_10111; +localparam S_RF23 = 6'b0_11000; +localparam S_RF24 = 6'b0_11001; +localparam S_RF25 = 6'b0_11010; +localparam S_RF26 = 6'b0_11011; +localparam S_RF27 = 6'b0_11100; +localparam S_RF28 = 6'b0_11101; +localparam S_RF29 = 6'b0_11110; +localparam S_RF30 = 6'b0_11111; +localparam S_RF31 = 6'b1_11111; +localparam S_RF32 = 6'b1_11110; +localparam S_DONE = 6'b1_11100; +localparam S_ERROR = 6'b1_01010; + + +//===================================== +// +// I/O PORTS +// +//===================================== +input rstn ; +input clk ; + +input i_mk_rdy ; +input i_post_rdy ; +input i_text_val ; + +output o_rdy ; +output o_text_done ; + +output[2:0] o_xf_sel ; +output o_rf_final ; + +output o_key_sel ; +output[4:0] o_rnd_idx ; +output o_wf_post_pre ; + + +//===================================== +// +// REGISTERS +// +//===================================== +// state register +reg[5:0] r_pstate ; + + +//===================================== +// +// WIRES +// +//===================================== +// nstate +reg[5:0] w_nstate ; + + +//===================================== +// +// MAIN +// +//===================================== +// state register +always @(negedge rstn or posedge clk) + if(~rstn) + r_pstate <= #1 S_IDLE ; + else + r_pstate <= #1 w_nstate; + + +// nstate +always @(i_mk_rdy or i_text_val or i_post_rdy or r_pstate) + case(r_pstate) + S_IDLE : + begin + if(i_mk_rdy) + w_nstate <= S_RDY; + else + w_nstate <= S_KEY_CONFIG; + end + S_KEY_CONFIG : + begin + if(i_mk_rdy) + w_nstate <= S_RDY; + else + w_nstate <= r_pstate; + end + S_RDY : + begin + if(i_text_val) + if(i_mk_rdy) + w_nstate <= S_WF1; + else // ~i_mk_rdy + w_nstate <= S_ERROR; + else // ~i_text_val + if(i_mk_rdy) + w_nstate <= r_pstate; + else // ~i_mk_rdy + w_nstate <= S_KEY_CONFIG; + end + S_WF1 : + begin + if(i_mk_rdy) + w_nstate <= S_RF1; + else + w_nstate <= S_ERROR; + end + S_RF1 : + begin + if(i_mk_rdy) + w_nstate <= S_RF2; + else + w_nstate <= S_ERROR; + end + S_RF2 : + begin + if(i_mk_rdy) + w_nstate <= S_RF3; + else + w_nstate <= S_ERROR; + end + S_RF3 : + begin + if(i_mk_rdy) + w_nstate <= S_RF4; + else + w_nstate <= S_ERROR; + end + S_RF4 : + begin + if(i_mk_rdy) + w_nstate <= S_RF5; + else + w_nstate <= S_ERROR; + end + S_RF5 : + begin + if(i_mk_rdy) + w_nstate <= S_RF6; + else + w_nstate <= S_ERROR; + end + S_RF6 : + begin + if(i_mk_rdy) + w_nstate <= S_RF7; + else + w_nstate <= S_ERROR; + end + S_RF7 : + begin + if(i_mk_rdy) + w_nstate <= S_RF8; + else + w_nstate <= S_ERROR; + end + S_RF8 : + begin + if(i_mk_rdy) + w_nstate <= S_RF9; + else + w_nstate <= S_ERROR; + end + S_RF9 : + begin + if(i_mk_rdy) + w_nstate <= S_RF10; + else + w_nstate <= S_ERROR; + end + S_RF10 : + begin + if(i_mk_rdy) + w_nstate <= S_RF11; + else + w_nstate <= S_ERROR; + end + S_RF11 : + begin + if(i_mk_rdy) + w_nstate <= S_RF12; + else + w_nstate <= S_ERROR; + end + S_RF12 : + begin + if(i_mk_rdy) + w_nstate <= S_RF13; + else + w_nstate <= S_ERROR; + end + S_RF13 : + begin + if(i_mk_rdy) + w_nstate <= S_RF14; + else + w_nstate <= S_ERROR; + end + S_RF14 : + begin + if(i_mk_rdy) + w_nstate <= S_RF15; + else + w_nstate <= S_ERROR; + end + S_RF15 : + begin + if(i_mk_rdy) + w_nstate <= S_RF16; + else + w_nstate <= S_ERROR; + end + S_RF16 : + begin + if(i_mk_rdy) + w_nstate <= S_RF17; + else + w_nstate <= S_ERROR; + end + S_RF17 : + begin + if(i_mk_rdy) + w_nstate <= S_RF18; + else + w_nstate <= S_ERROR; + end + S_RF18 : + begin + if(i_mk_rdy) + w_nstate <= S_RF19; + else + w_nstate <= S_ERROR; + end + S_RF19 : + begin + if(i_mk_rdy) + w_nstate <= S_RF20; + else + w_nstate <= S_ERROR; + end + S_RF20 : + begin + if(i_mk_rdy) + w_nstate <= S_RF21; + else + w_nstate <= S_ERROR; + end + S_RF21 : + begin + if(i_mk_rdy) + w_nstate <= S_RF22; + else + w_nstate <= S_ERROR; + end + S_RF22 : + begin + if(i_mk_rdy) + w_nstate <= S_RF23; + else + w_nstate <= S_ERROR; + end + S_RF23 : + begin + if(i_mk_rdy) + w_nstate <= S_RF24; + else + w_nstate <= S_ERROR; + end + S_RF24 : + begin + if(i_mk_rdy) + w_nstate <= S_RF25; + else + w_nstate <= S_ERROR; + end + S_RF25 : + begin + if(i_mk_rdy) + w_nstate <= S_RF26; + else + w_nstate <= S_ERROR; + end + S_RF26 : + begin + if(i_mk_rdy) + w_nstate <= S_RF27; + else + w_nstate <= S_ERROR; + end + S_RF27 : + begin + if(i_mk_rdy) + w_nstate <= S_RF28; + else + w_nstate <= S_ERROR; + end + S_RF28 : + begin + if(i_mk_rdy) + w_nstate <= S_RF29; + else + w_nstate <= S_ERROR; + end + S_RF29 : + begin + if(i_mk_rdy) + w_nstate <= S_RF30; + else + w_nstate <= S_ERROR; + end + S_RF30 : + begin + if(i_mk_rdy) + w_nstate <= S_RF31; + else + w_nstate <= S_ERROR; + end + S_RF31 : + begin + if(i_mk_rdy) + w_nstate <= S_RF32; + else + w_nstate <= S_ERROR; + end + S_RF32 : + begin + if(i_mk_rdy) + w_nstate <= S_DONE; + else + w_nstate <= S_ERROR; + end + S_DONE : + begin + if(i_post_rdy) + if(i_mk_rdy) + w_nstate <= S_RDY; + else + w_nstate <= S_KEY_CONFIG; + else + w_nstate <= r_pstate; + end + S_ERROR : + begin + w_nstate <= S_IDLE; + end + default : + begin + w_nstate <= S_ERROR; + end + endcase + + +// o_rdy +assign o_rdy = i_mk_rdy & (r_pstate == S_RDY); + +// o_text_done +assign o_text_done = (r_pstate == S_DONE) & i_post_rdy; + +// o_xf_sel +assign o_xf_sel[2] = (r_pstate == S_RDY) & i_text_val; +assign o_xf_sel[1:0] = ((r_pstate == S_RDY) & i_text_val) ? 2'b01 : + (((r_pstate != S_RDY) & ~r_pstate[5]) | (r_pstate == S_RF31)) ? 2'b10 : + (r_pstate == S_RF32) ? 2'b01 : + 2'b00 ; +// o_rf_final +assign o_rf_final = (r_pstate == S_RF31); + +// o_key_sel +assign o_key_sel = ((r_pstate == S_RDY) & i_text_val) | ((r_pstate != S_RDY) & (~r_pstate[5])); + +// o_rnd_idx +assign o_rnd_idx = r_pstate[4:0]; + +// o_wf_post_pre +assign o_wf_post_pre = (r_pstate == S_RF31); + +endmodule + + + + diff --git a/designs/encrypted_ip/cpu8080/CRYPTO_PATH.v b/designs/encrypted_ip/cpu8080/CRYPTO_PATH.v new file mode 100644 index 000000000..125657383 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/CRYPTO_PATH.v @@ -0,0 +1,155 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Main datapath for HIGHT Crypto Core //// +//// //// +//// This file is part of the HIGHT Crypto Core project //// +//// http://github.com/OpenSoCPlus/hight_crypto_core //// +//// http://www.opencores.org/project,hight //// +//// //// +//// Description //// +//// __description__ //// +//// //// +//// Author(s): //// +//// - JoonSoo Ha, json.ha@gmail.com //// +//// - Younjoo Kim, younjookim.kr@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module CRYPTO_PATH( + rstn , + clk , + + i_op , + + i_wrsk , + + i_text_in , + + i_xf_sel , + i_rf_final , + + o_text_out +); + + +//===================================== +// +// PARAMETERS +// +//===================================== + + +//===================================== +// +// I/O PORTS +// +//===================================== +input rstn ; +input clk ; + +input i_op ; + +input[31:0] i_wrsk ; + +input[63:0] i_text_in ; + +input[2:0] i_xf_sel ; +input i_rf_final ; + +output[63:0] o_text_out ; + + +//===================================== +// +// REGISTERS +// +//===================================== +// xf register +reg[63:0] r_xf ; + + +//===================================== +// +// WIRES +// +//===================================== +// wf_in mux +wire[63:0] w_wf_in_mux ; +// w_wf_out +wire[63:0] w_wf_out ; +// w_rf_out +wire[63:0] w_rf_out ; +// xf mux +wire[63:0] w_xf_mux ; + +//===================================== +// +// MAIN +// +//===================================== +// WF(WhiteningFunction) instance +WF u_WF( + .i_op ( i_op ) , + .i_wk ( i_wrsk ) , + .i_wf_in ( w_wf_in_mux ) , + + .o_wf_out ( w_wf_out ) +); + +// RF(RoundFunction) instance +RF u_RF( + .i_op ( i_op ) , + .i_rf_final ( i_rf_final ) , + .i_rf_in ( r_xf ) , + .i_rsk ( i_wrsk ) , + + .o_rf_out ( w_rf_out ) +); + +// wf_in mux +assign w_wf_in_mux = (~i_xf_sel[2]) ? r_xf : // i_xf_sel[2] == 0 + i_text_in ; // i_xf_sel[2] == 1 + +// xf mux +assign w_xf_mux = (i_xf_sel[1:0] == 2'b00) ? r_xf : // i_xf_sel[1:0] == 0 + (i_xf_sel[1:0] == 2'b01) ? w_wf_out : // i_xf_sel[1:0] == 1 + w_rf_out ; // i_xf_sel[1:0] == 2, 3 + +// xf register +always @(negedge rstn or posedge clk) + if(~rstn) + r_xf <= #1 64'h0 ; + else + r_xf <= #1 w_xf_mux ; + +// o_text_out +assign o_text_out = r_xf; + +endmodule + + diff --git a/designs/encrypted_ip/cpu8080/KEY_SCHED.v b/designs/encrypted_ip/cpu8080/KEY_SCHED.v new file mode 100644 index 000000000..ab5d6cc2b --- /dev/null +++ b/designs/encrypted_ip/cpu8080/KEY_SCHED.v @@ -0,0 +1,193 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Key scheduler for HIGHT Crypto Core //// +//// //// +//// This file is part of the HIGHT Crypto Core project //// +//// http://github.com/OpenSoCPlus/hight_crypto_core //// +//// http://www.opencores.org/project,hight //// +//// //// +//// Description //// +//// __description__ //// +//// //// +//// Author(s): //// +//// - JoonSoo Ha, json.ha@gmail.com //// +//// - Younjoo Kim, younjookim.kr@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module KEY_SCHED( + rstn , + clk , + + i_mk , + + i_op , + + i_key_sel , + i_rnd_idx , + i_wf_post_pre , + + o_rnd_key +); + + +//===================================== +// +// PARAMETERS +// +//===================================== + + +//===================================== +// +// I/O PORTS +// +//===================================== +input rstn ; +input clk ; + +input[127:0] i_mk ; + +input i_op ; + +input i_key_sel ; +input[4:0] i_rnd_idx ; +input i_wf_post_pre ; + +output[31:0] o_rnd_key ; + + +//===================================== +// +// REGISTERS +// +//===================================== +// r_rnd_key_3x ~ r_rnd_key_0x register +reg[7:0] r_rnd_key_3x ; +reg[7:0] r_rnd_key_2x ; +reg[7:0] r_rnd_key_1x ; +reg[7:0] r_rnd_key_0x ; + + +//===================================== +// +// WIRES +// +//===================================== +// w_wk3x ~ w_wk0x +wire[7:0] w_wk3x ; +wire[7:0] w_wk2x ; +wire[7:0] w_wk1x ; +wire[7:0] w_wk0x ; + +// w_sk3x ~ w_sk0x +wire[7:0] w_sk3x ; +wire[7:0] w_sk2x ; +wire[7:0] w_sk1x ; +wire[7:0] w_sk0x ; + + +//===================================== +// +// MAIN +// +//===================================== +// WKG(Whitening Key Generator) instance +WKG u_WKG( + .i_op (i_op ) , + + .i_wf_post_pre (i_wf_post_pre) , + + .i_mk3to0 (i_mk[31:0] ) , + .i_mk15to12 (i_mk[127:96] ) , + + .o_wk3_7 (w_wk3x ) , + .o_wk2_6 (w_wk2x ) , + .o_wk1_5 (w_wk1x ) , + .o_wk0_4 (w_wk0x ) +); + +// SKG(SubKey Generator) instance +SKG u_SKG( + .i_op (i_op ) , + .i_rnd_idx (i_rnd_idx ) , + .i_mk (i_mk ) , + + .o_sk3x (w_sk3x ) , + .o_sk2x (w_sk2x ) , + .o_sk1x (w_sk1x ) , + .o_sk0x (w_sk0x ) +); + +// r_rnd_key_3x ~ r_rnd_key_0x register +always @(negedge rstn or posedge clk) + if(~rstn) begin + r_rnd_key_3x <= #1 8'h00; + r_rnd_key_2x <= #1 8'h00; + r_rnd_key_1x <= #1 8'h00; + r_rnd_key_0x <= #1 8'h00; + end + else begin + if(~i_key_sel) begin + r_rnd_key_3x <= #1 w_wk3x; + r_rnd_key_2x <= #1 w_wk2x; + r_rnd_key_1x <= #1 w_wk1x; + r_rnd_key_0x <= #1 w_wk0x; + end + else begin + r_rnd_key_3x <= #1 w_sk3x; + r_rnd_key_2x <= #1 w_sk2x; + r_rnd_key_1x <= #1 w_sk1x; + r_rnd_key_0x <= #1 w_sk0x; + end + end + +// o_rnd_key +assign o_rnd_key = {r_rnd_key_3x,r_rnd_key_2x,r_rnd_key_1x,r_rnd_key_0x}; + +endmodule + + + + + + + + + + + + + + + + + + + + diff --git a/designs/encrypted_ip/cpu8080/RF.v b/designs/encrypted_ip/cpu8080/RF.v new file mode 100644 index 000000000..2e16c9e82 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/RF.v @@ -0,0 +1,173 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Round function of main datapath for HIGHT Crypto Core //// +//// //// +//// This file is part of the HIGHT Crypto Core project //// +//// http://github.com/OpenSoCPlus/hight_crypto_core //// +//// http://www.opencores.org/project,hight //// +//// //// +//// Description //// +//// __description__ //// +//// //// +//// Author(s): //// +//// - JoonSoo Ha, json.ha@gmail.com //// +//// - Younjoo Kim, younjookim.kr@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module RF( + i_op , + + i_rsk , + + i_rf_in , + + i_rf_final , + + o_rf_out +); + + +//===================================== +// +// PARAMETERS +// +//===================================== + + +//===================================== +// +// I/O PORTS +// +//===================================== +input i_op ; + +input[31:0] i_rsk ; + +input[63:0] i_rf_in ; + +input i_rf_final ; + +output[63:0] o_rf_out ; + + +//===================================== +// +// REGISTERS +// +//===================================== + + +//===================================== +// +// WIRES +// +//===================================== +// w_rf_out +wire[63:0] w_rf_out ; +// w_rf_out (7 ~ 0) +wire[7:0] w_rf_out7 ; +wire[7:0] w_rf_out6 ; +wire[7:0] w_rf_out5 ; +wire[7:0] w_rf_out4 ; +wire[7:0] w_rf_out3 ; +wire[7:0] w_rf_out2 ; +wire[7:0] w_rf_out1 ; +wire[7:0] w_rf_out0 ; +// w_f_function +wire[7:0] w_f0_6 ; +wire[7:0] w_f1_4 ; +wire[7:0] w_f0_2 ; +wire[7:0] w_f1_0 ; +// w_rf_median_value +wire[7:0] w_rf_mv[0:3]; +//===================================== +// +// MAIN +// +//===================================== + +assign w_f0_6 = {i_rf_in[54:48],i_rf_in[55]} ^ + {i_rf_in[53:48],i_rf_in[55:54]} ^ + {i_rf_in[48] ,i_rf_in[55:49]}; +assign w_f1_4 = {i_rf_in[36:32],i_rf_in[39:37]} ^ + {i_rf_in[35:32],i_rf_in[39:36]} ^ + {i_rf_in[33:32],i_rf_in[39:34]}; +assign w_f0_2 = {i_rf_in[22:16],i_rf_in[23]} ^ + {i_rf_in[21:16],i_rf_in[23:22]} ^ + {i_rf_in[16] ,i_rf_in[23:17]}; +assign w_f1_0 = {i_rf_in[4:0] ,i_rf_in[7:5]} ^ + {i_rf_in[3:0] ,i_rf_in[7:4]} ^ + {i_rf_in[1:0] ,i_rf_in[7:2]}; + +assign w_rf_mv[3] = (i_op == 0) ? i_rf_in[63:56] ^ (w_f0_6 + i_rsk[31:24]): + i_rf_in[63:56] ^ (w_f0_6 + i_rsk[7:0]); + +assign w_rf_mv[2] = (i_op == 0) ? i_rf_in[47:40] + (w_f1_4 ^ i_rsk[23:16]): + i_rf_in[47:40] - (w_f1_4 ^ i_rsk[15:8]); + +assign w_rf_mv[1] = (i_op == 0) ? i_rf_in[31:24] ^ (w_f0_2 + i_rsk[15:8]): + i_rf_in[31:24] ^ (w_f0_2 + i_rsk[23:16]); + +assign w_rf_mv[0] = (i_op == 0) ? i_rf_in[15:8] + (w_f1_0 ^ i_rsk[7:0]): + i_rf_in[15:8] - (w_f1_0 ^ i_rsk[31:24]); + +assign w_rf_out7 = (i_rf_final == 1) ? w_rf_mv[3] : + (i_op == 0) ? i_rf_in[55:48] : + i_rf_in[7:0]; +assign w_rf_out6 = (i_rf_final == 1) ? i_rf_in[55:48] : + (i_op == 0) ? w_rf_mv[2] : + w_rf_mv[3]; +assign w_rf_out5 = (i_rf_final == 1) ? w_rf_mv[2] : + (i_op == 0) ? i_rf_in[39:32] : + i_rf_in[55:48]; +assign w_rf_out4 = (i_rf_final == 1) ? i_rf_in[39:32] : + (i_op == 0) ? w_rf_mv[1] : + w_rf_mv[2]; +assign w_rf_out3 = (i_rf_final == 1) ? w_rf_mv[1] : + (i_op == 0) ? i_rf_in[23:16] : + i_rf_in[39:32]; +assign w_rf_out2 = (i_rf_final == 1) ? i_rf_in[23:16] : + (i_op == 0) ? w_rf_mv[0] : + w_rf_mv[1]; + +assign w_rf_out1 = (i_rf_final == 1) ? w_rf_mv[0] : + (i_op == 0) ? i_rf_in[7:0] : + i_rf_in[23:16]; + +assign w_rf_out0 = (i_rf_final == 1) ? i_rf_in[7:0] : + (i_op == 0) ? w_rf_mv[3] : + w_rf_mv[0]; + +assign w_rf_out = {w_rf_out7, w_rf_out6, w_rf_out5, w_rf_out4, w_rf_out3, w_rf_out2, w_rf_out1, w_rf_out0}; +assign o_rf_out = w_rf_out; + + +endmodule + + diff --git a/designs/encrypted_ip/cpu8080/SKG.v b/designs/encrypted_ip/cpu8080/SKG.v new file mode 100644 index 000000000..d9c870820 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/SKG.v @@ -0,0 +1,470 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Subkey generator of key scheduler for HIGHT Crypto Core //// +//// //// +//// This file is part of the HIGHT Crypto Core project //// +//// http://github.com/OpenSoCPlus/hight_crypto_core //// +//// http://www.opencores.org/project,hight //// +//// //// +//// Description //// +//// __description__ //// +//// //// +//// Author(s): //// +//// - JoonSoo Ha, json.ha@gmail.com //// +//// - Younjoo Kim, younjookim.kr@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module SKG( + i_op , + i_rnd_idx , + i_mk , + + o_sk3x , + o_sk2x , + o_sk1x , + o_sk0x +); + + +//===================================== +// +// PARAMETERS +// +//===================================== + + +//===================================== +// +// I/O PORTS +// +//===================================== +input i_op ; +input[4:0] i_rnd_idx ; +input[127:0] i_mk ; + +output[7:0] o_sk3x ; +output[7:0] o_sk2x ; +output[7:0] o_sk1x ; +output[7:0] o_sk0x ; + + +//===================================== +// +// REGISTERS +// +//===================================== + + +//===================================== +// +// WIRES +// +//===================================== +// w_mk15 ~ w_mk0 +wire[7:0] w_mk15 = i_mk[127:120]; +wire[7:0] w_mk14 = i_mk[119:112]; +wire[7:0] w_mk13 = i_mk[111:104]; +wire[7:0] w_mk12 = i_mk[103: 96]; +wire[7:0] w_mk11 = i_mk[ 95: 88]; +wire[7:0] w_mk10 = i_mk[ 87: 80]; +wire[7:0] w_mk9 = i_mk[ 79: 72]; +wire[7:0] w_mk8 = i_mk[ 71: 64]; +wire[7:0] w_mk7 = i_mk[ 63: 56]; +wire[7:0] w_mk6 = i_mk[ 55: 48]; +wire[7:0] w_mk5 = i_mk[ 47: 40]; +wire[7:0] w_mk4 = i_mk[ 39: 32]; +wire[7:0] w_mk3 = i_mk[ 31: 24]; +wire[7:0] w_mk2 = i_mk[ 23: 16]; +wire[7:0] w_mk1 = i_mk[ 15: 8]; +wire[7:0] w_mk0 = i_mk[ 7: 0]; + +// w_base +wire[4:0] w_base; + +// w_d3x ~ w_d0x +reg[6:0] w_d3x; +reg[6:0] w_d2x; +reg[6:0] w_d1x; +reg[6:0] w_d0x; + +// w_mk3x ~ w_mk0x +reg[7:0] w_mk3x; +reg[7:0] w_mk2x; +reg[7:0] w_mk1x; +reg[7:0] w_mk0x; + +// w_sk3x_tmp ~ w_sk0x_tmp +wire[7:0] w_sk3x_tmp; +wire[7:0] w_sk2x_tmp; +wire[7:0] w_sk1x_tmp; +wire[7:0] w_sk0x_tmp; + + +//===================================== +// +// MAIN +// +//===================================== +// w_base +assign w_base = (~i_op) ? i_rnd_idx : + 5'd31 - i_rnd_idx ; + +// w_d3x +always @(w_base) + case(w_base) + 5'd00 : w_d3x <= 7'h1b; // idx : 3 + 5'd01 : w_d3x <= 7'h41; // idx : 7 + 5'd02 : w_d3x <= 7'h4c; // idx : 11 + 5'd03 : w_d3x <= 7'h2c; // idx : 15 + 5'd04 : w_d3x <= 7'h4a; // idx : 19 + 5'd05 : w_d3x <= 7'h1c; // idx : 23 + 5'd06 : w_d3x <= 7'h79; // idx : 27 + 5'd07 : w_d3x <= 7'h37; // idx : 31 + 5'd08 : w_d3x <= 7'h0b; // idx : 35 + 5'd09 : w_d3x <= 7'h50; // idx : 39 + 5'd10 : w_d3x <= 7'h55; // idx : 43 + 5'd11 : w_d3x <= 7'h7d; // idx : 47 + 5'd12 : w_d3x <= 7'h17; // idx : 51 + 5'd13 : w_d3x <= 7'h29; // idx : 55 + 5'd14 : w_d3x <= 7'h62; // idx : 59 + 5'd15 : w_d3x <= 7'h76; // idx : 63 + 5'd16 : w_d3x <= 7'h47; // idx : 67 + 5'd17 : w_d3x <= 7'h7c; // idx : 71 + 5'd18 : w_d3x <= 7'h1f; // idx : 75 + 5'd19 : w_d3x <= 7'h61; // idx : 79 + 5'd20 : w_d3x <= 7'h6e; // idx : 83 + 5'd21 : w_d3x <= 7'h1e; // idx : 87 + 5'd22 : w_d3x <= 7'h69; // idx : 91 + 5'd23 : w_d3x <= 7'h26; // idx : 95 + 5'd24 : w_d3x <= 7'h12; // idx : 99 + 5'd25 : w_d3x <= 7'h01; // idx : 103 + 5'd26 : w_d3x <= 7'h08; // idx : 107 + 5'd27 : w_d3x <= 7'h48; // idx : 111 + 5'd28 : w_d3x <= 7'h0c; // idx : 115 + 5'd29 : w_d3x <= 7'h68; // idx : 119 + 5'd30 : w_d3x <= 7'h2e; // idx : 123 + 5'd31 : w_d3x <= 7'h5a; // idx : 127 + endcase + +// w_d2x +always @(w_base) + case(w_base) + 5'd00 : w_d2x <= 7'h36; // idx : 2 + 5'd01 : w_d2x <= 7'h03; // idx : 6 + 5'd02 : w_d2x <= 7'h18; // idx : 10 + 5'd03 : w_d2x <= 7'h59; // idx : 14 + 5'd04 : w_d2x <= 7'h15; // idx : 18 + 5'd05 : w_d2x <= 7'h39; // idx : 22 + 5'd06 : w_d2x <= 7'h73; // idx : 26 + 5'd07 : w_d2x <= 7'h6f; // idx : 30 + 5'd08 : w_d2x <= 7'h16; // idx : 34 + 5'd09 : w_d2x <= 7'h21; // idx : 38 + 5'd10 : w_d2x <= 7'h2a; // idx : 42 + 5'd11 : w_d2x <= 7'h7a; // idx : 46 + 5'd12 : w_d2x <= 7'h2f; // idx : 50 + 5'd13 : w_d2x <= 7'h52; // idx : 54 + 5'd14 : w_d2x <= 7'h45; // idx : 58 + 5'd15 : w_d2x <= 7'h6c; // idx : 62 + 5'd16 : w_d2x <= 7'h0e; // idx : 66 + 5'd17 : w_d2x <= 7'h78; // idx : 70 + 5'd18 : w_d2x <= 7'h3f; // idx : 74 + 5'd19 : w_d2x <= 7'h43; // idx : 78 + 5'd20 : w_d2x <= 7'h5c; // idx : 82 + 5'd21 : w_d2x <= 7'h3d; // idx : 86 + 5'd22 : w_d2x <= 7'h53; // idx : 90 + 5'd23 : w_d2x <= 7'h4d; // idx : 94 + 5'd24 : w_d2x <= 7'h24; // idx : 98 + 5'd25 : w_d2x <= 7'h02; // idx : 102 + 5'd26 : w_d2x <= 7'h10; // idx : 106 + 5'd27 : w_d2x <= 7'h11; // idx : 110 + 5'd28 : w_d2x <= 7'h19; // idx : 114 + 5'd29 : w_d2x <= 7'h51; // idx : 118 + 5'd30 : w_d2x <= 7'h5d; // idx : 122 + 5'd31 : w_d2x <= 7'h35; // idx : 126 + endcase + +// w_d1x +always @(w_base) + case(w_base) + 5'd00 : w_d1x <= 7'h6d; // idx : 1 + 5'd01 : w_d1x <= 7'h06; // idx : 5 + 5'd02 : w_d1x <= 7'h30; // idx : 9 + 5'd03 : w_d1x <= 7'h33; // idx : 13 + 5'd04 : w_d1x <= 7'h2b; // idx : 17 + 5'd05 : w_d1x <= 7'h72; // idx : 21 + 5'd06 : w_d1x <= 7'h67; // idx : 25 + 5'd07 : w_d1x <= 7'h5e; // idx : 29 + 5'd08 : w_d1x <= 7'h2d; // idx : 33 + 5'd09 : w_d1x <= 7'h42; // idx : 37 + 5'd10 : w_d1x <= 7'h54; // idx : 41 + 5'd11 : w_d1x <= 7'h75; // idx : 45 + 5'd12 : w_d1x <= 7'h5f; // idx : 49 + 5'd13 : w_d1x <= 7'h25; // idx : 53 + 5'd14 : w_d1x <= 7'h0a; // idx : 57 + 5'd15 : w_d1x <= 7'h58; // idx : 61 + 5'd16 : w_d1x <= 7'h1d; // idx : 65 + 5'd17 : w_d1x <= 7'h71; // idx : 69 + 5'd18 : w_d1x <= 7'h7f; // idx : 73 + 5'd19 : w_d1x <= 7'h07; // idx : 77 + 5'd20 : w_d1x <= 7'h38; // idx : 81 + 5'd21 : w_d1x <= 7'h7b; // idx : 85 + 5'd22 : w_d1x <= 7'h27; // idx : 89 + 5'd23 : w_d1x <= 7'h1a; // idx : 93 + 5'd24 : w_d1x <= 7'h49; // idx : 97 + 5'd25 : w_d1x <= 7'h04; // idx : 101 + 5'd26 : w_d1x <= 7'h20; // idx : 105 + 5'd27 : w_d1x <= 7'h22; // idx : 109 + 5'd28 : w_d1x <= 7'h32; // idx : 113 + 5'd29 : w_d1x <= 7'h23; // idx : 117 + 5'd30 : w_d1x <= 7'h3a; // idx : 121 + 5'd31 : w_d1x <= 7'h6b; // idx : 125 + endcase + +// w_d0x +always @(w_base) + case(w_base) + 5'd00 : w_d0x <= 7'h5a; // idx : 0 + 5'd01 : w_d0x <= 7'h0d; // idx : 4 + 5'd02 : w_d0x <= 7'h60; // idx : 8 + 5'd03 : w_d0x <= 7'h66; // idx : 12 + 5'd04 : w_d0x <= 7'h56; // idx : 16 + 5'd05 : w_d0x <= 7'h65; // idx : 20 + 5'd06 : w_d0x <= 7'h4e; // idx : 24 + 5'd07 : w_d0x <= 7'h3c; // idx : 28 + 5'd08 : w_d0x <= 7'h5b; // idx : 32 + 5'd09 : w_d0x <= 7'h05; // idx : 36 + 5'd10 : w_d0x <= 7'h28; // idx : 40 + 5'd11 : w_d0x <= 7'h6a; // idx : 44 + 5'd12 : w_d0x <= 7'h3e; // idx : 48 + 5'd13 : w_d0x <= 7'h4b; // idx : 52 + 5'd14 : w_d0x <= 7'h14; // idx : 56 + 5'd15 : w_d0x <= 7'h31; // idx : 60 + 5'd16 : w_d0x <= 7'h3b; // idx : 64 + 5'd17 : w_d0x <= 7'h63; // idx : 68 + 5'd18 : w_d0x <= 7'h7e; // idx : 72 + 5'd19 : w_d0x <= 7'h0f; // idx : 76 + 5'd20 : w_d0x <= 7'h70; // idx : 80 + 5'd21 : w_d0x <= 7'h77; // idx : 84 + 5'd22 : w_d0x <= 7'h4f; // idx : 88 + 5'd23 : w_d0x <= 7'h34; // idx : 92 + 5'd24 : w_d0x <= 7'h13; // idx : 96 + 5'd25 : w_d0x <= 7'h09; // idx : 100 + 5'd26 : w_d0x <= 7'h40; // idx : 104 + 5'd27 : w_d0x <= 7'h44; // idx : 108 + 5'd28 : w_d0x <= 7'h64; // idx : 112 + 5'd29 : w_d0x <= 7'h46; // idx : 116 + 5'd30 : w_d0x <= 7'h74; // idx : 120 + 5'd31 : w_d0x <= 7'h57; // idx : 124 + endcase + +// w_mk3x +always @(*) + case(w_base) + 5'd00 : w_mk3x <= w_mk3 ; // idx : 3 + 5'd01 : w_mk3x <= w_mk7 ; // idx : 7 + 5'd02 : w_mk3x <= w_mk11; // idx : 11 + 5'd03 : w_mk3x <= w_mk15; // idx : 15 + 5'd04 : w_mk3x <= w_mk2 ; // idx : 19 + 5'd05 : w_mk3x <= w_mk6 ; // idx : 23 + 5'd06 : w_mk3x <= w_mk10; // idx : 27 + 5'd07 : w_mk3x <= w_mk14; // idx : 31 + 5'd08 : w_mk3x <= w_mk1 ; // idx : 35 + 5'd09 : w_mk3x <= w_mk5 ; // idx : 39 + 5'd10 : w_mk3x <= w_mk9 ; // idx : 43 + 5'd11 : w_mk3x <= w_mk13; // idx : 47 + 5'd12 : w_mk3x <= w_mk0 ; // idx : 51 + 5'd13 : w_mk3x <= w_mk4 ; // idx : 55 + 5'd14 : w_mk3x <= w_mk8 ; // idx : 59 + 5'd15 : w_mk3x <= w_mk12; // idx : 63 + 5'd16 : w_mk3x <= w_mk7 ; // idx : 67 + 5'd17 : w_mk3x <= w_mk3 ; // idx : 71 + 5'd18 : w_mk3x <= w_mk15; // idx : 75 + 5'd19 : w_mk3x <= w_mk11; // idx : 79 + 5'd20 : w_mk3x <= w_mk6 ; // idx : 83 + 5'd21 : w_mk3x <= w_mk2 ; // idx : 87 + 5'd22 : w_mk3x <= w_mk14; // idx : 91 + 5'd23 : w_mk3x <= w_mk10; // idx : 95 + 5'd24 : w_mk3x <= w_mk5 ; // idx : 99 + 5'd25 : w_mk3x <= w_mk1 ; // idx : 103 + 5'd26 : w_mk3x <= w_mk13; // idx : 107 + 5'd27 : w_mk3x <= w_mk9 ; // idx : 111 + 5'd28 : w_mk3x <= w_mk4 ; // idx : 115 + 5'd29 : w_mk3x <= w_mk0 ; // idx : 119 + 5'd30 : w_mk3x <= w_mk12; // idx : 123 + 5'd31 : w_mk3x <= w_mk8 ; // idx : 127 + endcase + +// w_mk2x +always @(*) + case(w_base) + 5'd00 : w_mk2x <= w_mk2 ; // idx : 2 + 5'd01 : w_mk2x <= w_mk6 ; // idx : 6 + 5'd02 : w_mk2x <= w_mk10; // idx : 10 + 5'd03 : w_mk2x <= w_mk14; // idx : 14 + 5'd04 : w_mk2x <= w_mk1 ; // idx : 18 + 5'd05 : w_mk2x <= w_mk5 ; // idx : 22 + 5'd06 : w_mk2x <= w_mk9 ; // idx : 26 + 5'd07 : w_mk2x <= w_mk13; // idx : 30 + 5'd08 : w_mk2x <= w_mk0 ; // idx : 34 + 5'd09 : w_mk2x <= w_mk4 ; // idx : 38 + 5'd10 : w_mk2x <= w_mk8 ; // idx : 42 + 5'd11 : w_mk2x <= w_mk12; // idx : 46 + 5'd12 : w_mk2x <= w_mk7 ; // idx : 50 + 5'd13 : w_mk2x <= w_mk3 ; // idx : 54 + 5'd14 : w_mk2x <= w_mk15; // idx : 58 + 5'd15 : w_mk2x <= w_mk11; // idx : 62 + 5'd16 : w_mk2x <= w_mk6 ; // idx : 66 + 5'd17 : w_mk2x <= w_mk2 ; // idx : 70 + 5'd18 : w_mk2x <= w_mk14; // idx : 74 + 5'd19 : w_mk2x <= w_mk10; // idx : 78 + 5'd20 : w_mk2x <= w_mk5 ; // idx : 82 + 5'd21 : w_mk2x <= w_mk1 ; // idx : 86 + 5'd22 : w_mk2x <= w_mk13; // idx : 90 + 5'd23 : w_mk2x <= w_mk9 ; // idx : 94 + 5'd24 : w_mk2x <= w_mk4 ; // idx : 98 + 5'd25 : w_mk2x <= w_mk0 ; // idx : 102 + 5'd26 : w_mk2x <= w_mk12; // idx : 106 + 5'd27 : w_mk2x <= w_mk8 ; // idx : 110 + 5'd28 : w_mk2x <= w_mk3 ; // idx : 114 + 5'd29 : w_mk2x <= w_mk7 ; // idx : 118 + 5'd30 : w_mk2x <= w_mk11; // idx : 122 + 5'd31 : w_mk2x <= w_mk15; // idx : 126 + endcase + +// w_mk1x +always @(*) + case(w_base) + 5'd00 : w_mk1x <= w_mk1 ; // idx : 1 + 5'd01 : w_mk1x <= w_mk5 ; // idx : 5 + 5'd02 : w_mk1x <= w_mk9 ; // idx : 9 + 5'd03 : w_mk1x <= w_mk13; // idx : 13 + 5'd04 : w_mk1x <= w_mk0 ; // idx : 17 + 5'd05 : w_mk1x <= w_mk4 ; // idx : 21 + 5'd06 : w_mk1x <= w_mk8 ; // idx : 25 + 5'd07 : w_mk1x <= w_mk12; // idx : 29 + 5'd08 : w_mk1x <= w_mk7 ; // idx : 33 + 5'd09 : w_mk1x <= w_mk3 ; // idx : 37 + 5'd10 : w_mk1x <= w_mk15; // idx : 41 + 5'd11 : w_mk1x <= w_mk11; // idx : 45 + 5'd12 : w_mk1x <= w_mk6 ; // idx : 49 + 5'd13 : w_mk1x <= w_mk2 ; // idx : 53 + 5'd14 : w_mk1x <= w_mk14; // idx : 57 + 5'd15 : w_mk1x <= w_mk10; // idx : 61 + 5'd16 : w_mk1x <= w_mk5 ; // idx : 65 + 5'd17 : w_mk1x <= w_mk1 ; // idx : 69 + 5'd18 : w_mk1x <= w_mk13; // idx : 73 + 5'd19 : w_mk1x <= w_mk9 ; // idx : 77 + 5'd20 : w_mk1x <= w_mk4 ; // idx : 81 + 5'd21 : w_mk1x <= w_mk0 ; // idx : 85 + 5'd22 : w_mk1x <= w_mk12; // idx : 89 + 5'd23 : w_mk1x <= w_mk8 ; // idx : 93 + 5'd24 : w_mk1x <= w_mk3 ; // idx : 97 + 5'd25 : w_mk1x <= w_mk7 ; // idx : 101 + 5'd26 : w_mk1x <= w_mk11; // idx : 105 + 5'd27 : w_mk1x <= w_mk15; // idx : 109 + 5'd28 : w_mk1x <= w_mk2 ; // idx : 113 + 5'd29 : w_mk1x <= w_mk6 ; // idx : 117 + 5'd30 : w_mk1x <= w_mk10; // idx : 121 + 5'd31 : w_mk1x <= w_mk14; // idx : 125 + endcase + +// w_mk0x +always @(*) + case(w_base) + 5'd00 : w_mk0x <= w_mk0 ; // idx : 0 + 5'd01 : w_mk0x <= w_mk4 ; // idx : 4 + 5'd02 : w_mk0x <= w_mk8 ; // idx : 8 + 5'd03 : w_mk0x <= w_mk12; // idx : 12 + 5'd04 : w_mk0x <= w_mk7 ; // idx : 16 + 5'd05 : w_mk0x <= w_mk3 ; // idx : 20 + 5'd06 : w_mk0x <= w_mk15; // idx : 24 + 5'd07 : w_mk0x <= w_mk11; // idx : 28 + 5'd08 : w_mk0x <= w_mk6 ; // idx : 32 + 5'd09 : w_mk0x <= w_mk2 ; // idx : 36 + 5'd10 : w_mk0x <= w_mk14; // idx : 40 + 5'd11 : w_mk0x <= w_mk10; // idx : 44 + 5'd12 : w_mk0x <= w_mk5 ; // idx : 48 + 5'd13 : w_mk0x <= w_mk1 ; // idx : 52 + 5'd14 : w_mk0x <= w_mk13; // idx : 56 + 5'd15 : w_mk0x <= w_mk9 ; // idx : 60 + 5'd16 : w_mk0x <= w_mk4 ; // idx : 64 + 5'd17 : w_mk0x <= w_mk0 ; // idx : 68 + 5'd18 : w_mk0x <= w_mk12; // idx : 72 + 5'd19 : w_mk0x <= w_mk8 ; // idx : 76 + 5'd20 : w_mk0x <= w_mk3 ; // idx : 80 + 5'd21 : w_mk0x <= w_mk7 ; // idx : 84 + 5'd22 : w_mk0x <= w_mk11; // idx : 88 + 5'd23 : w_mk0x <= w_mk15; // idx : 92 + 5'd24 : w_mk0x <= w_mk2 ; // idx : 96 + 5'd25 : w_mk0x <= w_mk6 ; // idx : 100 + 5'd26 : w_mk0x <= w_mk10; // idx : 104 + 5'd27 : w_mk0x <= w_mk14; // idx : 108 + 5'd28 : w_mk0x <= w_mk1 ; // idx : 112 + 5'd29 : w_mk0x <= w_mk5 ; // idx : 116 + 5'd30 : w_mk0x <= w_mk9 ; // idx : 120 + 5'd31 : w_mk0x <= w_mk13; // idx : 124 + endcase + +// w_sk3x_tmp +assign w_sk3x_tmp = {1'b0,w_d3x} + w_mk3x; + +// w_sk2x_tmp +assign w_sk2x_tmp = {1'b0,w_d2x} + w_mk2x; + +// w_sk1x_tmp +assign w_sk1x_tmp = {1'b0,w_d1x} + w_mk1x; + +// w_sk0x_tmp +assign w_sk0x_tmp = {1'b0,w_d0x} + w_mk0x; + +// o_sk3x +assign o_sk3x = (~i_op) ? w_sk3x_tmp : // i_op == 0 + w_sk0x_tmp ; // i_op == 1 + +// o_sk2x +assign o_sk2x = (~i_op) ? w_sk2x_tmp : // i_op == 0 + w_sk1x_tmp ; // i_op == 1 + +// o_sk1x +assign o_sk1x = (~i_op) ? w_sk1x_tmp : // i_op == 0 + w_sk2x_tmp ; // i_op == 1 + +// o_sk0x +assign o_sk0x = (~i_op) ? w_sk0x_tmp : // i_op == 0 + w_sk3x_tmp ; // i_op == 1 + +endmodule + + + + + + + + diff --git a/designs/encrypted_ip/cpu8080/WF.v b/designs/encrypted_ip/cpu8080/WF.v new file mode 100644 index 000000000..c259c6bfb --- /dev/null +++ b/designs/encrypted_ip/cpu8080/WF.v @@ -0,0 +1,123 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Whitening function of main datapath for HIGHT Crypto Core //// +//// //// +//// This file is part of the HIGHT Crypto Core project //// +//// http://github.com/OpenSoCPlus/hight_crypto_core //// +//// http://www.opencores.org/project,hight //// +//// //// +//// Description //// +//// __description__ //// +//// //// +//// Author(s): //// +//// - JoonSoo Ha, json.ha@gmail.com //// +//// - Younjoo Kim, younjookim.kr@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module WF( + + i_op , + + i_wf_in , + + i_wk , + + o_wf_out +); + + +//===================================== +// +// PARAMETERS +// +//===================================== + + +//===================================== +// +// I/O PORTS +// +//===================================== + +input i_op ; + +input[63:0] i_wf_in ; + +input[31:0] i_wk ; + +output[63:0] o_wf_out ; + + +//===================================== +// +// REGISTERS +// +//===================================== + + +//===================================== +// +// WIRES +// +//===================================== +// w_wf_out +wire[63:0] w_wf_out ; +// w_rf_out(7:0) +wire[7:0] w_wf_out7 ; +wire[7:0] w_wf_out6 ; +wire[7:0] w_wf_out5 ; +wire[7:0] w_wf_out4 ; +wire[7:0] w_wf_out3 ; +wire[7:0] w_wf_out2 ; +wire[7:0] w_wf_out1 ; +wire[7:0] w_wf_out0 ; + +//===================================== +// +// MAIN +// +//===================================== + +assign w_wf_out7 = i_wf_in[63:56]; +assign w_wf_out6 = i_wf_in[55:48] ^ i_wk[31:24]; +assign w_wf_out5 = i_wf_in[47:40]; +assign w_wf_out4 = (i_op == 0) ? (i_wf_in[39:32] + i_wk[23:16]) : + (i_wf_in[39:32] - i_wk[23:16]) ; +assign w_wf_out3 = i_wf_in[31:24]; +assign w_wf_out2 = i_wf_in[23:16] ^ i_wk[15:8]; +assign w_wf_out1 = i_wf_in[15:8]; +assign w_wf_out0 = (i_op == 0) ? (i_wf_in[7:0] + i_wk[7:0]) : + (i_wf_in[7:0] - i_wk[7:0]) ; + +assign w_wf_out = {w_wf_out7, w_wf_out6, w_wf_out5, w_wf_out4, w_wf_out3, w_wf_out2, w_wf_out1, w_wf_out0}; +assign o_wf_out = w_wf_out; + +endmodule + + diff --git a/designs/encrypted_ip/cpu8080/WKG.v b/designs/encrypted_ip/cpu8080/WKG.v new file mode 100644 index 000000000..c1eda8b7a --- /dev/null +++ b/designs/encrypted_ip/cpu8080/WKG.v @@ -0,0 +1,129 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Whitening key generator of key scheduler //// +//// for HIGHT Crypto Core //// +//// //// +//// This file is part of the HIGHT Crypto Core project //// +//// http://github.com/OpenSoCPlus/hight_crypto_core //// +//// http://www.opencores.org/project,hight //// +//// //// +//// Description //// +//// __description__ //// +//// //// +//// Author(s): //// +//// - JoonSoo Ha, json.ha@gmail.com //// +//// - Younjoo Kim, younjookim.kr@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module WKG( + i_op , + + i_wf_post_pre , + + i_mk3to0 , + i_mk15to12 , + + o_wk3_7 , + o_wk2_6 , + o_wk1_5 , + o_wk0_4 +); + + +//===================================== +// +// PARAMETERS +// +//===================================== + + +//===================================== +// +// I/O PORTS +// +//===================================== +input i_op ; + +input i_wf_post_pre ; + +input[31:0] i_mk3to0 ; +input[31:0] i_mk15to12 ; + +output[7:0] o_wk3_7 ; +output[7:0] o_wk2_6 ; +output[7:0] o_wk1_5 ; +output[7:0] o_wk0_4 ; + + +//===================================== +// +// REGISTERS +// +//===================================== + + +//===================================== +// +// WIRES +// +//===================================== +wire w_out_sel; + + +//===================================== +// +// MAIN +// +//===================================== +// w_out_sel +assign w_out_sel = i_op ^ i_wf_post_pre; // 0 if 2 signals have same value + // 1 if 2 signals hava different value + +// o_wk3_7 +assign o_wk3_7 = (~w_out_sel) ? i_mk15to12[31:24] : // w_out_sel == 0 + i_mk3to0[31:24] ; // w_out_sel == 1 +// o_wk2_6 +assign o_wk2_6 = (~w_out_sel) ? i_mk15to12[23:16] : // w_out_sel == 0 + i_mk3to0[23:16] ; // w_out_sel == 1 +// o_wk1_5 +assign o_wk1_5 = (~w_out_sel) ? i_mk15to12[15:8] : // w_out_sel == 0 + i_mk3to0[15:8] ; // w_out_sel == 1 +// o_wk0_4 +assign o_wk0_4 = (~w_out_sel) ? i_mk15to12[7:0] : // w_out_sel == 0 + i_mk3to0[7:0] ; // w_out_sel == 1 + +endmodule + + + + + + + + diff --git a/designs/encrypted_ip/cpu8080/common.vhd b/designs/encrypted_ip/cpu8080/common.vhd new file mode 100644 index 000000000..c0b62fe0b --- /dev/null +++ b/designs/encrypted_ip/cpu8080/common.vhd @@ -0,0 +1,51 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package common is + + constant YES : std_logic := '1'; + constant NO : std_logic := '0'; + constant HI : std_logic := '1'; + constant LO : std_logic := '0'; + constant ONE : std_logic := '1'; + constant ZERO : std_logic := '0'; + function boolean2stdlogic(b : in boolean) return std_logic; + function log2(v : in natural) return natural; + +end package common; + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + + +package body common is + + function boolean2stdlogic(b : in boolean) return std_logic is + variable s : std_logic; + begin + if b then + s := '1'; + else + s := '0'; + end if; + return s; + end function boolean2stdlogic; + + function log2(v : in natural) return natural is + variable n : natural; + variable logn : natural; + begin + n := 1; + for i in 0 to 128 loop + logn := i; + exit when (n >= v); + n := n * 2; + end loop; + return logn; + end function log2; + +end package body common; diff --git a/designs/encrypted_ip/cpu8080/cpu8080.v b/designs/encrypted_ip/cpu8080/cpu8080.v new file mode 100644 index 000000000..c57815e42 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/cpu8080.v @@ -0,0 +1,1681 @@ +//////////////////////////////////////////////////////////////////////////////// +// Company: // +// Engineer: Scott Moore // +// // +// Additional contributions by: // +// // +// Chris N. Strahm - Modifications for Altera Quartus build. // +// // +// Create Date: 11:45:32 09/04/2006 // +// Design Name: // +// Module Name: cpu8080 // +// Project Name: cpu8080 // +// Target Devices: xc3c200, xc3s1000 // +// Tool versions: // +// Description: // +// // +// Executes the 8080 instruction set. It is designed to be an internal // +// cell. Each of the I/Os are positive logic, and all signals are // +// constant with the exception of the data bus. The control signals are // +// fully decoded (unlike the orignal 8080), and features read and write // +// signals for both memory and I/O space. The I/O space is an 8 bit // +// address as in the original 8080. It does NOT echo the lower 8 bits to // +// the higher 8 bits, as was the practice in some systems. // +// // +// Like the original 8080, the interrupt vectoring is fully external. The // +// the external controller forces a full instruction onto the data bus. // +// The sequence begins with the assertion of interrupt request. The CPU // +// will then assert interrupt acknowledge, then it will run a special // +// read cycle with inta asserted for each cycle of a possibly // +// multibyte instruction. This matches the original 8080, which typically // +// used single byte restart instructions to form a simple interrupt // +// controller, but was capable of full vectoring via insertion of a jump, // +// call or similar instruction. // +// // +// Note that the interrupt vector instruction should branch. This is // +// because the PC gets changed by the vector instruction, so if it does // +// not branch, it will have skipped a number of bytes after the interrupt // +// equivalent to the vector instruction. The only instructions that // +// should really be used to vector are jmp, rst and call instructions. // +// Specifically, rst and call instruction compensate for the pc movement // +// by putting the pc unmodified on the stack. // +// // +// The memory, I/O and interrupt fetches all obey a simple clocking // +// sequence as follows. The CPU uses the positive clock edge to assert // +// and sample signals and data. The external logic theoretically uses the // +// negative edge to check signal assertions and sample data, but it can // +// either use the negative edge, or actually be asynronous logic. // +// // +// A standard read sequence is as follows: // +// // +// 1. At the positive clock edge, readmem, readio or readint is asserted. // +// 2. At the negative clock edge (or immediately), the external memory // +// places data onto the data bus. // +// 3. We hold automatically for one cycle. // +// 4. At the next positive clock edge, the data is sampled, and the read // +// Signal is deasserted. // +// // +// A standard write sequence is as follows: // +// // +// 1. At the positive edge, data is asserted on the data bus. // +// 2. At the next postive clock edge, writemem or writeio is asserted. // +// 3. At the next positive clock edge, writemem or writeio is deasserted. // +// 4. At the next positive edge, the data is deasserted. // +// // +// Dependencies: // +// // +// Revision: // +// Revision 0.01 - File Created // +// Additional Comments: // +// // +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// Build option +// +// Uncomment this line to build without wait state ability. Many FPGA +// applications don't require wait states. This can save silicon area. +// +// Defining this option will cause the wait line to be ignored. +// +// `define NOWAIT + +// +// Build option +// +// Uncomment this line to build without I/O instruction ability. An application +// may have memory mapped I/O only, and not require I/O instructions. This can +// save silicon area. +// +// Defining this option will cause I/O instructions to be treated as no-ops. +// alternately, you can modify what they do. +// +// `define NOIO + +// +// CPU states +// + +`define cpus_idle 6'h00 // Idle +`define cpus_fetchi 6'h01 // Instruction fetch +`define cpus_fetchi2 6'h02 // Instruction fetch 2 +`define cpus_fetchi3 6'h03 // Instruction fetch 3 +`define cpus_fetchi4 6'h04 // Instruction fetch 4 +`define cpus_halt 6'h05 // Halt (wait for interrupt) +`define cpus_alucb 6'h06 // alu cycleback +`define cpus_indcb 6'h07 // inr/dcr cycleback +`define cpus_movmtbc 6'h08 // Move memory to bc +`define cpus_movmtde 6'h09 // Move memory to de +`define cpus_movmthl 6'h0a // Move memory to hl +`define cpus_movmtsp 6'h0b // Move memory to sp +`define cpus_lhld 6'h0c // LHLD +`define cpus_jmp 6'h0d // JMP +`define cpus_write 6'h0e // write byte +`define cpus_write2 6'h0f // write byte #2 +`define cpus_write3 6'h10 // write byte #3 +`define cpus_write4 6'h11 // write byte #4 +`define cpus_read 6'h12 // read byte +`define cpus_read2 6'h13 // read byte #2 +`define cpus_read3 6'h14 // read byte #3 +`define cpus_pop 6'h15 // POP completion +`define cpus_in 6'h16 // IN +`define cpus_in2 6'h17 // IN #2 +`define cpus_in3 6'h18 // IN #3 +`define cpus_out 6'h19 // OUT +`define cpus_out2 6'h1a // OUT #2 +`define cpus_out3 6'h1b // OUT #3 +`define cpus_out4 6'h1c // OUT #4 +`define cpus_movtr 6'h1d // move to register +`define cpus_movrtw 6'h1e // move read to write +`define cpus_movrtwa 6'h1f // move read to write address +`define cpus_movrtra 6'h20 // move read to read address +`define cpus_accimm 6'h21 // accumulator immediate operations +`define cpus_daa 6'h22 // DAA completion +`define cpus_call 6'h23 // CALL completion +`define cpus_ret 6'h24 // RET completion +`define cpus_movtalua 6'h25 // move to alu a +`define cpus_movtalub 6'h26 // move to alu b +`define cpus_indm 6'h27 // inc/dec m + +// +// Register numbers +// + +`define reg_b 3'b000 // B +`define reg_c 3'b001 // C +`define reg_d 3'b010 // D +`define reg_e 3'b011 // E +`define reg_h 3'b100 // H +`define reg_l 3'b101 // L +`define reg_m 3'b110 // M +`define reg_a 3'b111 // A + +// +// ALU operations +// + +`define aluop_add 3'b000 // add +`define aluop_adc 3'b001 // add with carry in +`define aluop_sub 3'b010 // subtract +`define aluop_sbb 3'b011 // subtract with borrow in +`define aluop_and 3'b100 // and +`define aluop_xor 3'b101 // xor +`define aluop_or 3'b110 // or +`define aluop_cmp 3'b111 // compare + +// +// State macros +// +`define mac_writebyte 1 // write a byte +`define mac_readbtoreg 2 // read a byte, place in register +`define mac_readdtobc 4 // read double byte to BC +`define mac_readdtode 6 // read double byte to DE +`define mac_readdtohl 8 // read double byte to HL +`define mac_readdtosp 10 // read double byte to SP +`define mac_readbmtw 12 // read byte and move to write +`define mac_readbmtr 15 // read byte and move to register +`define mac_sta 17 // STA +`define mac_lda 21 // LDA +`define mac_shld 26 // SHLD +`define mac_lhld 31 // LHLD +`define mac_writedbyte 37 // write double byte +`define mac_pop 39 // POP +`define mac_xthl 41 // XTHL +`define mac_accimm 45 // accumulator immediate +`define mac_jmp 46 // JMP +`define mac_call 48 // CALL +`define mac_in 52 // IN +`define mac_out 53 // OUT +`define mac_rst 54 // RST +`define mac_ret 56 // RET +`define mac_alum 58 // op a,m +`define mac_indm 60 // inc/dec m + +module cpu8080(addr, // Address out + data, // Data bus + readmem, // Memory read + writemem, // Memory write + readio, // Read I/O space + writeio, // Write I/O space + intr, // Interrupt request + inta, // Interrupt request + waitr, // Wait request + reset, // Reset + clock); // System clock + + output [15:0] addr; + inout [7:0] data; + output readmem; + output writemem; + output readio; + output writeio; + input intr; + output inta; + input waitr; + input reset; + input clock; + + // Output or input lines that need to be registered + + reg readmem; + reg writemem; + reg [15:0] pc; + reg [15:0] addr; + reg readio; + reg writeio; + reg inta; + reg [15:0] sp; + + // Local registers + + reg [5:0] state; // CPU state machine + reg [2:0] regd; // Destination register + reg [7:0] datao; // Data output register + reg dataeno; // Enable output data + reg [15:0] waddrhold; // address holding for write + reg [15:0] raddrhold; // address holding for read + reg [7:0] wdatahold; // single byte write data holding + reg [7:0] wdatahold2; // single byte write data holding + reg [7:0] rdatahold; // single byte read data holding + reg [7:0] rdatahold2; // single byte read data holding + reg [1:0] popdes; // POP destination code + reg [5:0] statesel; // state map selector + reg [5:0] nextstate; // next state output + reg eienb; // interrupt enable delay shift reg + reg [7:0] opcode; // opcode holding + + // Register file. Note that 3'b110 (6) is not used, and is the code for a + // memory reference. + + reg [7:0] regfil[0:7]; + + // The flags are represented individually + + reg carry; // carry bit + reg auxcar; // auxiliary carry bit + reg sign; // sign bit + reg zero; // zero bit + reg parity; // parity bit + reg ei; // interrupt enable + reg intcyc; // in interrupt cycle + + // ALU communication + + wire [7:0] alures; // result + reg [7:0] aluopra; // left side operand + reg [7:0] aluoprb; // right side operand + reg alucin; // carry in + wire alucout; // carry out + wire alupar; // parity out + wire aluaxc; // auxiliary carry + reg [2:0] alusel; // alu operational select + + // Instantiate the ALU + + alu alu(alures, aluopra, aluoprb, alucin, alucout, aluzout, alusout, alupar, + aluaxc, alusel); + + always @(posedge clock) + if (reset) begin // syncronous reset actions + + state <= `cpus_fetchi; // Clear CPU state to initial fetch + pc <= 0; // reset program counter to 1st location + dataeno <= 0; // get off the data bus + readmem <= 0; // all signals out false + writemem <= 0; + readio <= 0; + writeio <= 0; + inta <= 0; + intcyc <= 0; + ei <= 1; // interrupts on by default + eienb <= 0; + + end else case (state) + + `cpus_fetchi: begin // start of instruction fetch + + // if interrupt request is on, enter interrupt cycle, else exit it now + if (intr&&ei) begin + + intcyc <= 1; // enter interrupt cycle + inta <= 1; // activate interrupt acknowledge + ei <= 0; // disable interrupts + + end else begin + + intcyc <= 0; // leave interrupt cycle + readmem <= 1; // activate instruction memory read + + end + + addr <= pc; // place current program count on output + if (eienb) ei <=1; // process delayed interrupt enable + eienb <=0; // reset interrupt enabler + state <= `cpus_fetchi2; // next state + + end + + `cpus_fetchi2: begin // wait + + state <= `cpus_fetchi3; // next state + + end + + `cpus_fetchi3: begin // complete instruction memory read + +`ifndef NOWAIT + if (!waitr) +`endif + begin // no wait selected, otherwise cycle + + opcode <= data; // latch opcode + readmem <= 0; // Deactivate instruction memory read + inta <= 0; // and interrupt acknowledge + state <= `cpus_fetchi4; // next state + + end + + end + + `cpus_fetchi4: begin // complete instruction memory read + + // We split off the instructions into 4 groups. Most of the 8080 + // instructions are in the MOV and ACC operations class. + + case (opcode[7:6]) // Decode top level + + 2'b00: begin // 00: Data transfers and others + + case (opcode[5:0]) // decode these instructions + + 6'b000000: begin // NOP + + // yes, do nothing + + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b110111: begin // STC + + carry <= 1; // set carry flag + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b111111: begin // CMC + + carry <= ~carry; // complement carry flag + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b101111: begin // CMA + + regfil[`reg_a] <= ~regfil[`reg_a]; // complement accumulator + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b100111: begin // DAA + + // decimal adjust accumulator, or remove by carry any + // results in nybbles greater than 9 + + if (regfil[`reg_a][3:0] > 9 || auxcar) + { auxcar, regfil[`reg_a] } <= regfil[`reg_a]+8'h06; + state <= `cpus_daa; // finish DAA + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b000100, 6'b001100, 6'b010100, 6'b011100, 6'b100100, + 6'b101100, 6'b110100, 6'b111100, 6'b000101, 6'b001101, + 6'b010101, 6'b011101, 6'b100101, 6'b101101, 6'b110101, + 6'b111101: begin // INR/DCR + + regd <= opcode[5:3]; // get source/destination reg + aluopra <= regfil[opcode[5:3]]; // load as alu a + aluoprb <= 1; // load 1 as alu b + if (opcode[0]) alusel <= `aluop_sub; // set subtract + else alusel <= `aluop_add; // set add + if (opcode[5:3] == `reg_m) begin + + raddrhold <= regfil[`reg_h]<<8|regfil[`reg_l]; + statesel <= `mac_indm; // inc/dec m + state <= `cpus_read; // read byte + + end else state <= `cpus_indcb; // go inr/dcr cycleback + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b000010, 6'b010010: begin // STAX + + wdatahold <= regfil[`reg_a]; // place A as source + if (opcode[4]) // use DE pair + waddrhold <= regfil[`reg_d]<<8|regfil[`reg_e]; + else // use BC pair + waddrhold <= regfil[`reg_b] << 8|regfil[`reg_c]; + statesel <= `mac_writebyte; // write byte + state <= `cpus_write; + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b001010, 6'b011010: begin // LDAX + + regd <= `reg_a; // set A as destination + if (opcode[4]) // use DE pair + raddrhold <= regfil[`reg_d]<<8|regfil[`reg_e]; + else // use BC pair + raddrhold <= regfil[`reg_b]<<8|regfil[`reg_c]; + statesel <= `mac_readbtoreg; // read byte to register + state <= `cpus_read; + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b000111: begin // RLC + + // rotate left circular + { carry, regfil[`reg_a] } <= + (regfil[`reg_a] << 1)+regfil[`reg_a][7]; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b010111: begin // RAL + + // rotate left through carry + { carry, regfil[`reg_a] } <= (regfil[`reg_a] << 1)+carry; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b001111: begin // RRC + + // rotate right circular + regfil[`reg_a] <= + (regfil[`reg_a] >> 1)+(regfil[`reg_a][0] << 7); + carry <= regfil[`reg_a][0]; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b011111: begin // RAR + + // rotate right through carry + regfil[`reg_a] <= (regfil[`reg_a] >> 1)+(carry << 7); + carry <= regfil[`reg_a][0]; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b001001: begin // DAD B + + // add BC to HL + { carry, regfil[`reg_h], regfil[`reg_l] } <= + (regfil[`reg_h] << 8)+regfil[`reg_l]+ + (regfil[`reg_b] << 8)+regfil[`reg_c]; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b011001: begin // DAD D + + // add DE to HL + { carry, regfil[`reg_h], regfil[`reg_l] } <= + (regfil[`reg_h] << 8)+regfil[`reg_l]+ + (regfil[`reg_d] << 8)+regfil[`reg_e]; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b101001: begin // DAD H + + // add HL to HL + { carry, regfil[`reg_h], regfil[`reg_l] } <= + (regfil[`reg_h] << 8)+regfil[`reg_l]+ + (regfil[`reg_h] << 8)+regfil[`reg_l]; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b111001: begin // DAD SP + + // add SP to HL + { carry, regfil[`reg_h], regfil[`reg_l] } <= + (regfil[`reg_h] << 8)+regfil[`reg_l]+sp; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b000011: begin // INX B + + // increment BC, no flags set + regfil[`reg_b] <= + (((regfil[`reg_b] << 8)+regfil[`reg_c])+16'h1)>>8; + regfil[`reg_c] <= + ((regfil[`reg_b] << 8)+regfil[`reg_c])+16'h1; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b010011: begin // INX D + + // increment DE, no flags set + regfil[`reg_d] <= + (((regfil[`reg_d] << 8)+regfil[`reg_e])+16'h1)>>8; + regfil[`reg_e] <= + ((regfil[`reg_d] << 8)+regfil[`reg_e])+16'h1; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b100011: begin // INX H + + // increment HL, no flags set + regfil[`reg_h] <= + (((regfil[`reg_h] << 8)+regfil[`reg_l])+16'h1)>>8; + regfil[`reg_l] <= + ((regfil[`reg_h] << 8)+regfil[`reg_l])+16'h1; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b110011: begin // INX SP + + // increment SP, no flags set + sp <= sp + 16'b1; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b001011: begin // DCX B + + // decrement BC, no flags set + regfil[`reg_b] <= + (((regfil[`reg_b] << 8)+regfil[`reg_c])-16'h1)>>8; + regfil[`reg_c] <= + ((regfil[`reg_b] << 8)+regfil[`reg_c])-16'h1; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b011011: begin // DCX D + + // decrement DE, no flags set + regfil[`reg_d] <= + (((regfil[`reg_d] << 8)+regfil[`reg_e])-16'h1)>>8; + regfil[`reg_e] <= + ((regfil[`reg_d] << 8)+regfil[`reg_e])-16'h1; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b101011: begin // DCX H + + // decrement HL, no flags set + regfil[`reg_h] <= + (((regfil[`reg_h] << 8)+regfil[`reg_l])-16'h1)>>8; + regfil[`reg_l] <= + ((regfil[`reg_h] << 8)+regfil[`reg_l])-16'h1; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+1'h1; // Next instruction byte + + end + + 6'b111011: begin // DCX SP + + // decrement SP, no flags set + sp <= sp-16'b1; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b000001: begin // LXI B + + raddrhold <= pc+16'h1; // pick up after instruction + statesel <= `mac_readdtobc; // read double to BC + state <= `cpus_read; + pc <= pc+16'h3; // skip + + end + + 6'b010001: begin // LXI D + + raddrhold <= pc+16'h1; // pick up after instruction + statesel <= `mac_readdtode; // read double to DE + state <= `cpus_read; + pc <= pc+16'h3; // skip + + end + + 6'b100001: begin // LXI H + + raddrhold <= pc+16'h1; // pick up after instruction + statesel <= `mac_readdtohl; // read double to HL + state <= `cpus_read; + pc <= pc+16'h3; // skip + + end + + 6'b110001: begin // LXI SP + + raddrhold <= pc+16'h1; // pick up after instruction + statesel <= `mac_readdtosp; // read double to SP + state <= `cpus_read; + pc <= pc+16'h3; // skip + + end + + 6'b000110, 6'b001110, 6'b010110, 6'b011110, 6'b100110, + 6'b101110, 6'b110110, 6'b111110: begin // MVI + + // move immediate to register + regd <= opcode[5:3]; // set destination register + raddrhold <= pc+16'h1; // set pickup address + if (opcode[5:3] == `reg_m) begin // it's mvi m,imm + + regd <= opcode[5:3]; // set destination register + // set destination address + waddrhold <= { regfil[`reg_h], regfil[`reg_l] }; + statesel <= `mac_readbmtw; // read byte and move to write + + end else + statesel <= `mac_readbmtr; // read byte and move to register + state <= `cpus_read; + pc <= pc+16'h2; // advance over byte + + end + + 6'b110010: begin // STA + + wdatahold <= regfil[`reg_a]; // set write data + raddrhold <= pc+16'h1; // set read address + statesel <= `mac_sta; // perform sta + state <= `cpus_read; + pc <= pc + 16'h3; // next + + end + + 6'b111010: begin // LDA + + raddrhold <= pc+16'h1; // set read address + regd <= `reg_a; // set destination + statesel <= `mac_lda; // perform lda + state <= `cpus_read; + pc <= pc+16'h3; // next + + end + + 6'b100010: begin // SHLD + + wdatahold <= regfil[`reg_l]; // set write data + wdatahold2 <= regfil[`reg_h]; + raddrhold <= pc+16'h1; // set read address + statesel <= `mac_shld; // perform SHLD + state <= `cpus_read; + pc <= pc+16'h3; // skip + + end + + 6'b101010: begin // LHLD + + raddrhold <= pc+16'h1; // set read address + statesel <= `mac_lhld; // perform LHLD + state <= `cpus_read; + pc <= pc+16'h3; // skip + + end + + // the illegal opcodes behave as NOPs + + 6'b001000, 6'b010000, 6'b011000, 6'b100000, 6'b101000, + 6'b110000, 6'b110000: begin + + state <= `cpus_fetchi; // fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + endcase + + end + + 2'b01: begin // 01: MOV instruction + + // Check its the halt instruction, which occupies the invalid + // "MOV M,M" instruction. + if (opcode == 8'b01110110) state <= `cpus_halt; + // Otherwise, the 01 prefix is single instruction format. + else begin + + // Format 01DDDSSS + + // Check memory source, use state if so + if (opcode[2:0] == `reg_m) begin + + // place hl as address + raddrhold <= regfil[`reg_h]<<8|regfil[`reg_l]; + regd <= opcode[5:3]; // set destination + statesel <= `mac_readbtoreg; // read byte to register + state <= `cpus_read; + + // Check memory destination, use state if so + end else if (opcode[5:3] == `reg_m) begin + + // place hl as address + waddrhold <= regfil[`reg_h]<<8|regfil[`reg_l]; + wdatahold <= regfil[opcode[2:0]]; // place data to write + statesel <= `mac_writebyte; // write byte + state <= `cpus_write; + + // otherwise simple register to register + end else begin + + regfil[opcode[5:3]] <= regfil[opcode[2:0]]; + state <= `cpus_fetchi; // Fetch next instruction + + end + + end + pc <= pc+16'h1; // Next instruction byte + + end + + 2'b10: begin // 10: Reg or mem to accumulator ops + + // 10 prefix is single instruction format + aluopra <= regfil[`reg_a]; // load as alu a + aluoprb <= regfil[opcode[2:0]]; // load as alu b + alusel <= opcode[5:3]; // set alu operation from instruction + alucin <= carry; // input carry + if (opcode[2:0] == `reg_m) begin + + // set read address + raddrhold <= regfil[`reg_h]<<8|regfil[`reg_l]; + statesel <= `mac_alum; // alu from m + state <= `cpus_read; // read byte + + end else + state <= `cpus_alucb; // go to alu cycleback + pc <= pc+16'h1; // Next instruction byte + + end + + 2'b11: begin // 11: jmp/call and others + + case (opcode[5:0]) // decode these instructions + + 6'b000101, 6'b010101, 6'b100101, 6'b110101: begin // PUSH + + waddrhold <= sp-16'h2; // write to stack + sp <= sp-16'h2; // pushdown stack + case (opcode[5:4]) // register set + + 2'b00: { wdatahold2, wdatahold } <= + { regfil[`reg_b], regfil[`reg_c] }; + 2'b01: { wdatahold2, wdatahold } <= + { regfil[`reg_d], regfil[`reg_e] }; + 2'b10: { wdatahold2, wdatahold } <= + { regfil[`reg_h], regfil[`reg_l] }; + 2'b11: { wdatahold2, wdatahold } <= + { regfil[`reg_a], sign, zero, 1'b0, auxcar, + 1'b0, parity, 1'b1, carry }; + + endcase + statesel <= `mac_writedbyte; // write double byte + state <= `cpus_write; + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b000001, 6'b010001, 6'b100001, 6'b110001: begin // POP + + popdes <= opcode[5:4]; // set destination + raddrhold <= sp; // read from stack + sp <= sp+16'h2; // pushup stack + statesel <= `mac_pop; // perform POP + state <= `cpus_read; + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b101011: begin // XCHG + + regfil[`reg_d] <= regfil[`reg_h]; + regfil[`reg_e] <= regfil[`reg_l]; + regfil[`reg_h] <= regfil[`reg_d]; + regfil[`reg_l] <= regfil[`reg_e]; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b100011: begin // XTHL + + raddrhold <= sp; // address SP for read + waddrhold <= sp; // address SP for write + wdatahold <= regfil[`reg_l]; // set data is HL + wdatahold2 <= regfil[`reg_h]; + statesel <= `mac_xthl; // perform XTHL + state <= `cpus_read; + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b111001: begin // SPHL + + sp <= { regfil[`reg_h], regfil[`reg_l] }; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b000110, 6'b001110, 6'b010110, 6'b011110, 6'b100110, + 6'b101110, 6'b110110, + 6'b111110: begin // immediate arithmetic to accumulator + + aluopra <= regfil[`reg_a]; // load as alu a + alusel <= opcode[5:3]; // set alu operation from instruction + alucin <= carry; // input carry + raddrhold <= pc+16'h1; // read at PC + statesel <= `mac_accimm; // finish accumulator immediate + state <= `cpus_read; + pc <= pc+16'h2; // skip immediate byte + + end + + 6'b101001: begin // PCHL + + state <= `cpus_fetchi; // Fetch next instruction + pc <= { regfil[`reg_h], regfil[`reg_l] }; + + end + + 6'b000011: begin // JMP + + raddrhold <= pc+16'h1; // pick up jump address + statesel <= `mac_jmp; // finish JMP + state <= `cpus_read; + + end + + 6'b000010, 6'b001010, 6'b010010, 6'b011010, 6'b100010, + 6'b101010, 6'b110010, 6'b111010: begin // Jcc + + raddrhold <= pc+16'h1; // pick up jump address + statesel <= `mac_jmp; // finish JMP + // choose continue or read according to condition + case (opcode[5:3]) // decode flag cases + + 3'b000: if (zero) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b001: if (!zero) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b010: if (carry) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b011: if (!carry) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b100: if (parity) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b101: if (!parity) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b110: if (sign) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b111: if (!sign) state <= `cpus_fetchi; + else state <= `cpus_read; + + endcase + pc <= pc+16'h3; // advance after jump for false + + end + + 6'b001101: begin // CALL + + raddrhold <= pc+16'h1; // pick up call address + waddrhold <= sp-16'h2; // place address on stack + // if interrupt cycle, use current pc, else use address + // after call + if (intcyc) { wdatahold2, wdatahold } <= pc; + else { wdatahold2, wdatahold } <= pc+16'h3; + statesel <= `mac_call; // finish CALL + state <= `cpus_read; + + end + + 6'b000100, 6'b001100, 6'b010100, 6'b011100, 6'b100100, + 6'b101100, 6'b110100, 6'b111100: begin // Ccc + + raddrhold <= pc+16'h1; // pick up call address + waddrhold <= sp-16'h2; // place address on stack + // of address after call + { wdatahold2, wdatahold } <= pc + 16'h3; + statesel <= `mac_call; // finish CALL + // choose continue or read according to condition + case (opcode[5:3]) // decode flag cases + + 3'b000: if (zero) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b001: if (!zero) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b010: if (carry) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b011: if (!carry) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b100: if (parity) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b101: if (!parity) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b110: if (sign) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b111: if (!sign) state <= `cpus_fetchi; + else state <= `cpus_read; + + endcase + pc <= pc+16'h3; // advance after jump for false + + end + + 6'b001001: begin // RET + + raddrhold <= sp; // read from stack + statesel <= `mac_ret; // finish RET + state <= `cpus_read; + + end + + 6'b000000, 6'b001000, 6'b010000, 6'b011000, 6'b100000, + 6'b101000, 6'b110000, 6'b111000: begin // Rcc + + raddrhold <= sp; // read from stack + statesel <= `mac_ret; // finish JMP + // choose read or continue according to condition + case (opcode[5:3]) // decode flag cases + + 3'b000: if (zero) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b001: if (!zero) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b010: if (carry) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b011: if (!carry) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b100: if (parity) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b101: if (!parity) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b110: if (sign) state <= `cpus_fetchi; + else state <= `cpus_read; + 3'b111: if (!sign) state <= `cpus_fetchi; + else state <= `cpus_read; + + endcase + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b000111, 6'b001111, 6'b010111, 6'b011111, 6'b100111, + 6'b101111, 6'b110111, 6'b111111: begin // RST + + pc <= opcode & 8'b00111000; // place restart value in PC + waddrhold <= sp-16'h2; // place address on stack + // if interrupt cycle, use current pc, else use address + // after call + if (intcyc) { wdatahold2, wdatahold } <= pc; + else { wdatahold2, wdatahold } <= pc+16'h3; + { wdatahold2, wdatahold } <= pc+16'h1; // of address after call + sp <= sp-16'h2; // pushdown stack CNS + statesel <= `mac_writedbyte; // finish RST + state <= `cpus_write; // write to stack + + end + + 6'b111011: begin // EI + + eienb <= 1'b1; // set delayed interrupt enable + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b110011: begin // DI + + ei <= 1'b0; + state <= `cpus_fetchi; // Fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + 6'b011011: begin // IN p + +`ifndef NOIO + // perform input + raddrhold <= pc+1; // pick up byte I/O address + statesel <= `mac_in; // finish IN + state <= `cpus_read; + pc <= pc+16'h2; // advance over byte +`else + // ignore instruction + state <= `cpus_fetchi; // fetch next instruction + pc <= pc+16'h1; // Next instruction byte +`endif + + end + + 6'b010011: begin // OUT p + +`ifndef NOIO + // perform output + raddrhold <= pc+1; // pick up byte I/O address + statesel <= `mac_out; // finish OUT + state <= `cpus_read; + pc <= pc+16'h2; // advance over byte +`else + // ignore instruction + state <= `cpus_fetchi; // fetch next instruction + pc <= pc+16'h1; // Next instruction byte +`endif + + end + + // the illegal opcodes behave as NOPs + + 6'b001011, 6'b011001, 6'b011101, 6'b101101, + 6'b111101: begin + + state <= `cpus_fetchi; // fetch next instruction + pc <= pc+16'h1; // Next instruction byte + + end + + endcase + + end + + endcase + + end + + // Follow states. These state handlers implement the following cycles past + // M1, or primary fetch state. + + // + // single byte write, writes wdatahold to the waddrhold address + // + + `cpus_write: begin + + addr <= waddrhold; // place address on output + waddrhold <= waddrhold + 1'b1; // next address + datao <= wdatahold; // set data to output + wdatahold <= wdatahold2; // next data + dataeno <= 1; // enable output data + state <= `cpus_write2; // next state + + end + + `cpus_write2: begin // continue write #2 + + writemem <= 1; // enable write memory data + state <= `cpus_write3; // idle one cycle for write + + end + + `cpus_write3: begin // continue write #3 + +`ifndef NOWAIT + if (!waitr) +`endif + begin // no wait selected, otherwise cycle + + writemem <= 0; // disable write memory data + state <= `cpus_write4; // idle hold time + + end + + end + + `cpus_write4: begin // continue write #4 + + dataeno <= 0; // disable output data + state <= nextstate; // get next macro state + statesel <= statesel+6'b1; // and index next in macro + + end + + // + // single byte read, reads rdatahold from the raddrhold address + // + + `cpus_read: begin + + addr <= raddrhold; // place address on output + raddrhold <= raddrhold + 16'h1; // next address + if (intcyc) inta <= 1; // activate interrupt acknowledge + else readmem <= 1; // activate memory read + state <= `cpus_read2; // next state + + end + + `cpus_read2: begin // continue read #2 + + // wait one cycle + state <= `cpus_read3; // next state + + end + + `cpus_read3: begin // continue read #3 + +`ifndef NOWAIT + if (!waitr) +`endif + begin // no wait selected, otherwise cycle + + rdatahold2 <= rdatahold; // shift data + rdatahold <= data; // read new data + readmem <= 0; // deactivate instruction memory read + inta <= 0; // deactivate interrupt acknowledge + state <= nextstate; // get next macro state + statesel <= statesel+6'b1; // and index next in macro + + end + + end + + `cpus_pop: begin // finish POP instruction + + case (popdes) // register set + + 2'b00: { regfil[`reg_b], regfil[`reg_c] } <= + { rdatahold, rdatahold2 }; + 2'b01: { regfil[`reg_d], regfil[`reg_e] } <= + { rdatahold, rdatahold2 }; + 2'b10: { regfil[`reg_h], regfil[`reg_l] } <= + { rdatahold, rdatahold2 }; + 2'b11: begin + + regfil[`reg_a] <= rdatahold; + sign <= ((rdatahold2 >> 7)& 1'b1) ? 1'b1:1'b0; + zero <= ((rdatahold2 >> 6)& 1'b1) ? 1'b1:1'b0; + auxcar <= ((rdatahold2 >> 4)& 1'b1) ? 1'b1:1'b0; + parity <= ((rdatahold2 >> 2)& 1'b1) ? 1'b1:1'b0; + carry <= ((rdatahold2 >> 0)& 1'b1) ? 1'b1:1'b0; + + end + + endcase + state <= `cpus_fetchi; // Fetch next instruction + + end + + `cpus_jmp: begin // jump address + + state <= `cpus_fetchi; // and return to instruction fetch + pc <= { rdatahold, rdatahold2 }; + + end + + `cpus_call: begin // call address + + sp <= sp-16'h2; // pushdown stack + state <= `cpus_fetchi; // and return to instruction fetch + pc <= { rdatahold, rdatahold2 }; + + end + + `cpus_ret: begin // return from call + + sp <= sp+16'h2; // pushup stack + state <= `cpus_fetchi; // and return to instruction fetch + pc <= { rdatahold, rdatahold2 }; + + end + +`ifndef NOIO // if I/O instructions are to be included + `cpus_in: begin // input single byte to A + + addr <= rdatahold; // place I/O address on address lines + readio <= 1; // set read I/O + state <= `cpus_in2; // continue + + end + + `cpus_in2: begin // input single byte to A #2 + + // wait one cycle + state <= `cpus_in3; // continue + + end + + `cpus_in3: begin // input single byte to A #3 + +`ifndef NOWAIT + if (!waitr) +`endif + begin // no wait selected, otherwise cycle + + regfil[`reg_a] <= data; // place input data + readio <= 0; // clear read I/O + state <= `cpus_fetchi; // Fetch next instruction + + end + + end + + `cpus_out: begin // output single byte from A + + addr <= rdatahold; // place address on output + datao <= regfil[`reg_a]; // set data to output + dataeno <= 1; // enable output data + state <= `cpus_out2; // next state + + end + + `cpus_out2: begin // continue out #2 + + writeio <= 1; // enable write I/O data + state <= `cpus_out3; // idle one cycle for write + + end + + `cpus_out3: begin // continue out #3 + +`ifndef NOWAIT + if (!waitr) +`endif + begin // no wait selected, otherwise cycle + + writeio <= 0; // disable write I/O data + state <= `cpus_out4; // idle hold time + + end + + end + + `cpus_out4: begin // continue write #4 + + dataeno <= 0; // disable output data + state <= `cpus_fetchi; // Fetch next instruction + + end +`endif + + `cpus_halt: begin // Halt waiting for interrupt + + // If there is an interrupt request and interrupts are enabled, then we + // can leave halt. Otherwise we stay here. + if (intr&&ei) state <= `cpus_fetchi; // Fetch next instruction + else state <= `cpus_halt; + + end + + `cpus_movtr: begin // move to register + + regfil[regd] <= rdatahold; // place data + state <= nextstate; // get next macro state + statesel <= statesel+6'b1; // and index next in macro + + end + + `cpus_movtalua: begin // move to alu a + + aluopra <= rdatahold; // place data + state <= nextstate; // get next macro state + statesel <= statesel+6'b1; // and index next in macro + + end + + `cpus_movtalub: begin // move to alu b + + aluoprb <= rdatahold; // place data + state <= nextstate; // get next macro state + statesel <= statesel+6'b1; // and index next in macro + + end + + `cpus_alucb: begin // alu cycleback + + regfil[`reg_a] <= alures; // place alu result back to A + carry <= alucout; // place carry + sign <= alusout; // place sign + zero <= aluzout; // place zero + parity <= alupar; // place parity + auxcar <= aluaxc; // place auxiliary carry + state <= `cpus_fetchi; // and return to instruction fetch + + end + + `cpus_indcb: begin // inr/dcr cycleback + + regfil[regd] <= alures; // place alu result back to source/dest + sign <= alures[7]; // place sign + zero <= aluzout; // place zero + parity <= alupar; // place parity + auxcar <= aluaxc; // place auxiliary carry + state <= `cpus_fetchi; // and return to instruction fetch + + end + + `cpus_indm: begin // inr/dcr cycleback to m + + waddrhold <= regfil[`reg_h]<<8|regfil[`reg_l]; // place address + wdatahold <= alures; // place data to write + sign <= alures[7]; // place sign + zero <= aluzout; // place zero + parity <= alupar; // place parity + auxcar <= aluaxc; // place auxiliary carry + state <= nextstate; // get next macro state + statesel <= statesel+6'b1; // and index next in macro + + end + + `cpus_movmtbc: begin // finish LXI B + + regfil[`reg_b] <= rdatahold; // place upper + regfil[`reg_c] <= rdatahold2; // place lower + state <= `cpus_fetchi; // and return to instruction fetch + + end + + `cpus_movmtde: begin // finish LXI D + + regfil[`reg_d] <= rdatahold; // place upper + regfil[`reg_e] <= rdatahold2; // place lower + state <= `cpus_fetchi; // and return to instruction fetch + + end + + `cpus_movmthl: begin // finish LXI H + + regfil[`reg_h] <= rdatahold; // place upper + regfil[`reg_l] <= rdatahold2; // place lower + state <= `cpus_fetchi; // and return to instruction fetch + + end + + `cpus_movmtsp: begin // finish LXI SP + + sp <= { rdatahold, rdatahold2 }; // place + state <= `cpus_fetchi; // and return to instruction fetch + + end + + `cpus_movrtw: begin // move read to write + + wdatahold <= rdatahold; // move read to write data + state <= nextstate; // get next macro state + statesel <= statesel+6'b1; // and index next in macro + + end + + `cpus_movrtwa: begin // move read data to write address + + waddrhold <= { rdatahold, rdatahold2 }; + state <= nextstate; // get next macro state + statesel <= statesel+6'b1; // and index next in macro + + end + + `cpus_movrtra: begin // move read data to read address + + raddrhold <= { rdatahold, rdatahold2 }; + state <= nextstate; // get next macro state + statesel <= statesel+6'b1; // and index next in macro + + end + + `cpus_lhld: begin // load HL from read data + + regfil[`reg_l] <= rdatahold2; // low + regfil[`reg_h] <= rdatahold; // high + state <= nextstate; // get next macro state + statesel <= statesel+6'b1; // and index next in macro CNS + + end + + `cpus_accimm: begin + + aluoprb <= rdatahold; // load as alu b + state <= `cpus_alucb; // go to alu cycleback + + end + + `cpus_daa: begin + + if (regfil[`reg_a][7:4] > 9 || carry) + { carry, regfil[`reg_a] } <= regfil[`reg_a]+8'h60; + state <= `cpus_fetchi; // and return to instruction fetch + + end + + default: state <= 5'bx; + + endcase + + // Enable drive for data output + assign data = dataeno ? datao: 8'bz; + + // + // State macro generator + // + // This ROM contains series of state execution lists that perform various + // tasks, usually involving reads or writes. + // + + always @(statesel) case (statesel) + + // mac_writebyte: write a byte + + 1: nextstate = `cpus_fetchi; // fetch next instruction + + // mac_readbtoreg: read a byte, place in register + + 2: nextstate = `cpus_movtr; // move to register + 3: nextstate = `cpus_fetchi; // Fetch next instruction + + // mac_readdtobc: read double byte to BC + + 4: nextstate = `cpus_read; // get high byte + 5: nextstate = `cpus_movmtbc; // place in BC + + // mac_readdtode: read double byte to DE + + 6: nextstate = `cpus_read; // get high byte + 7: nextstate = `cpus_movmtde; // place in DE + + // mac_readdtohl: read double byte to HL + + 8: nextstate = `cpus_read; // get high byte + 9: nextstate = `cpus_movmthl; // place in HL + + // mac_readdtosp: read double byte to SP + + 10: nextstate = `cpus_read; // get high byte + 11: nextstate = `cpus_movmtsp; // place in SP + + // mac_readbmtw: read byte and move to write + + 12: nextstate = `cpus_movrtw; // move read to write + 13: nextstate = `cpus_write; // write to destination + 14: nextstate = `cpus_fetchi; // Fetch next instruction + + // mac_readbmtr: read byte and move to register + + 15: nextstate = `cpus_movtr; // place in register + 16: nextstate = `cpus_fetchi; // Fetch next instruction + + // mac_sta: STA + + 17: nextstate = `cpus_read; // read high byte + 18: nextstate = `cpus_movrtwa; // move read to write address + 19: nextstate = `cpus_write; // write to destination + 20: nextstate = `cpus_fetchi; // Fetch next instruction + + // mac_lda: LDA + + 21: nextstate = `cpus_read; // read high byte + 22: nextstate = `cpus_movrtra; // move read to write address + 23: nextstate = `cpus_read; // read byte + 24: nextstate = `cpus_movtr; // move to register + 25: nextstate = `cpus_fetchi; // Fetch next instruction + + // mac_shld: SHLD + + 26: nextstate = `cpus_read; // read high byte + 27: nextstate = `cpus_movrtwa; // move read to write address + 28: nextstate = `cpus_write; // write to destination low + 29: nextstate = `cpus_write; // write to destination high + 30: nextstate = `cpus_fetchi; // Fetch next instruction + + // mac_lhld: LHLD + + 31: nextstate = `cpus_read; // read high byte + 32: nextstate = `cpus_movrtra; // move read to write address + 33: nextstate = `cpus_read; // read byte low + 34: nextstate = `cpus_read; // read byte high + 35: nextstate = `cpus_lhld; // move to register + 36: nextstate = `cpus_fetchi; // Fetch next instruction + + // mac_writedbyte: write double byte + + 37: nextstate = `cpus_write; // double write + 38: nextstate = `cpus_fetchi; // then fetch + + // mac_pop: POP + + 39: nextstate = `cpus_read; // double it + 40: nextstate = `cpus_pop; // then finish + + // mac_xthl: XTHL + + 41: nextstate = `cpus_read; // double it + 42: nextstate = `cpus_write; // then write + 43: nextstate = `cpus_write; // double it + 44: nextstate = `cpus_movmthl; // place word in hl + + // mac_accimm: accumulator immediate + + 45: nextstate = `cpus_accimm; // finish + + // mac_jmp: JMP + + 46: nextstate = `cpus_read; // double read + 47: nextstate = `cpus_jmp; // then go pc + + // mac_call: CALL + + 48: nextstate = `cpus_read; // double read + 49: nextstate = `cpus_write; // then write + 50: nextstate = `cpus_write; // double write + 51: nextstate = `cpus_call; // then go to that + + // mac_in: IN + + 52: nextstate = `cpus_in; // go to IN after getting that + + // mac_out: OUT + + 53: nextstate = `cpus_out; // go to OUT after getting that + + // mac_rst: RST + + 54: nextstate = `cpus_write; // double write + 55: nextstate = `cpus_jmp; // then go to that + + // mac_ret: RET + + 56: nextstate = `cpus_read; // double read + 57: nextstate = `cpus_ret; // then go to that + + // mac_alum: op a,m + + 58: nextstate = `cpus_movtalub; // go move to alu a + 59: nextstate = `cpus_alucb; // cycle back to acc + + // mac_idm: inc/dec m + + 60: nextstate = `cpus_movtalua; // go move to alu b + 61: nextstate = `cpus_indm; // set up alu result + 62: nextstate = `cpus_write; // write it + 63: nextstate = `cpus_fetchi; // Fetch next instruction + + default nextstate = 6'bx; // other states never reached + + endcase + +endmodule + +// +// Alu module +// +// Finds arithmetic operations needed. Latches on the positive edge of the +// clock. There are 8 different types of operations, which come from bits +// 3-5 of the instruction. +// + +module alu(res, opra, oprb, cin, cout, zout, sout, parity, auxcar, sel); + + input [7:0] opra; // Input A + input [7:0] oprb; // Input B + input cin; // Carry in + output cout; // Carry out + output zout; // Zero out + output sout; // Sign out + output parity; // parity + output auxcar; // auxiliary carry + input [2:0] sel; // Operation select + output [7:0] res; // Result of alu operation + + reg cout; // Carry out + reg zout; // Zero out + reg sout; // sign out + reg parity; // parity + reg auxcar; // auxiliary carry + reg [7:0] resi; // Result of alu operation intermediate + reg [7:0] res; // Result of alu operation + + always @(opra, oprb, cin, sel, res, resi) begin + + case (sel) + + `aluop_add: begin // add + + { cout, resi } = opra+oprb; // find result and carry + // find auxiliary carry + auxcar = (((opra[3:0]+oprb[3:0]) >> 4) & 8'b1) ? 1'b1 : 1'b0; + + end + `aluop_adc: begin // adc + + { cout, resi } = opra+oprb+cin; // find result and carry + // find auxiliary carry + auxcar = (((opra[3:0]+oprb[3:0]+cin) >> 4) & 8'b1) ? 1'b1 : 1'b0; + + end + `aluop_sub, `aluop_cmp: begin // sub/cmp + + { cout, resi } = opra-oprb; // find result and carry + // find auxiliary borrow + auxcar = (((opra[3:0]-oprb[3:0]) >> 4) & 8'b1) ? 1'b1 : 1'b0; + + end + `aluop_sbb: begin // sbb + + { cout, resi } = opra-oprb-cin; // find result and carry + // find auxiliary borrow + auxcar = (((opra[3:0]-oprb[3:0]-cin >> 4)) & 8'b1) ? 1'b1 : 1'b0; + + end + `aluop_and: begin // ana + + { cout, resi } = {1'b0, opra&oprb}; // find result and carry + auxcar = 1'b0; // clear auxillary carry + + end + `aluop_xor: begin // xra + + { cout, resi } = {1'b0, opra^oprb}; // find result and carry + auxcar = 1'b0; // clear auxillary carry + + end + `aluop_or: begin // ora + + { cout, resi } = {1'b0, opra|oprb}; // find result and carry + auxcar = 1'b0; // clear auxillary carry + + end + + endcase + + if (sel != `aluop_cmp) res = resi; else res = opra; + zout <= ~|resi; // set zero flag from result + sout <= resi[7]; // set sign flag from result + parity <= ~^resi; // set parity flag from result + + end + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/cpu8080/dds.vhd b/designs/encrypted_ip/cpu8080/dds.vhd new file mode 100644 index 000000000..4329014e2 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/dds.vhd @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------- +-- MiniGA +-- Author: Thomas Pototschnig (thomas.pototschnig@gmx.de) +-- +-- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License +-- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ +-- +-- If you want to use MiniGA for commercial purposes please contact the author +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity dds is + Port ( clk : in std_logic; + reset : in std_logic; + phase : in std_logic_vector (1 downto 0); + addi : out std_logic_vector (8 downto 0); + data : out std_logic_vector (15 downto 0)); +end dds; + +architecture Behavioral of dds is + +component dds_sinus + Port ( clk : in std_logic; + reset : in std_logic; + adr : in std_logic_vector (6 downto 0); + output1 : out std_logic_vector (15 downto 0)); +end component; + +signal adr : std_logic_vector (6 downto 0); +signal output : std_logic_vector (15 downto 0); + +begin +I_O: dds_sinus port map ( clk => clk, reset => reset, adr => adr, output1 => output); + + + process (clk, reset) + variable step48 : unsigned (63 downto 0) := X"1938ECE0531174F2"; + variable ctr_48 : unsigned (63 downto 0) := X"FFC0000000000000"; + variable ctr90_48 : unsigned (63 downto 0):= X"3FC0000000000000"; + variable ctr135_48 : unsigned (63 downto 0):= X"5FC0000000000000"; + variable ctr225_48 : unsigned (63 downto 0):= X"9FC0000000000000"; + variable curctr : unsigned (8 downto 0); + + variable abschnittu : unsigned (1 downto 0); + variable indexu : unsigned (6 downto 0); + + + begin + if reset='0' then + ctr_48 := X"FFC0000000000000"; + ctr90_48 := X"3FC0000000000000"; + ctr135_48 := X"5FC0000000000000"; + ctr225_48 := X"9FC0000000000000"; + data <= (others => '0'); + elsif clk'event and clk='1' then + ctr_48 := ctr_48 + step48; + ctr90_48 := ctr90_48 + step48; + ctr135_48 := ctr135_48 + step48; + ctr225_48 := ctr225_48 + step48; + + case phase is + when "00" => curctr := ctr_48 (63 downto 55); + when "01" => curctr := ctr90_48 (63 downto 55); + when "10" => curctr := ctr135_48 (63 downto 55); + when "11" => curctr := ctr225_48 (63 downto 55); + when others => curctr := (others=>'0'); + end case; + + addi <= std_logic_vector(curctr);--(others => '0');--conv_std_logic_vector(curctr,9); + + indexu := curctr (6 downto 0); -- index für die tabelle + + case abschnittu(1) is + when '1' => data <= conv_std_logic_vector(-signed(output),16); + when '0' => data <= conv_std_logic_vector(signed(output),16); + when others => data <= (others=>'0'); + end case; + + abschnittu := curctr (8 downto 7); + + case abschnittu(0) is + when '0' => adr <= conv_std_logic_vector(indexu,7); + when '1' => adr <= conv_std_logic_vector(127-indexu,7); + when others => adr <= (others=>'0'); + end case; + end if; + end process; +end Behavioral; diff --git a/designs/encrypted_ip/cpu8080/dds_sinus.vhd b/designs/encrypted_ip/cpu8080/dds_sinus.vhd new file mode 100644 index 000000000..881125b5d --- /dev/null +++ b/designs/encrypted_ip/cpu8080/dds_sinus.vhd @@ -0,0 +1,159 @@ +------------------------------------------------------------------------------- +-- MiniGA +-- Author: Thomas Pototschnig (thomas.pototschnig@gmx.de) +-- +-- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License +-- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ +-- +-- If you want to use MiniGA for commercial purposes please contact the author +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity dds_sinus is + Port ( clk : in std_logic; + reset : in std_logic; + adr : in std_logic_vector (6 downto 0); + output1 : out std_logic_vector (15 downto 0)); +end dds_sinus; + +architecture Behavioral of dds_sinus is + +begin + process (adr) + begin + case adr is + when "0000000" => output1 <= "0000000011001001"; -- 0.0061 + when "0000001" => output1 <= "0000001001011011"; -- 0.0184 + when "0000010" => output1 <= "0000001111101101"; -- 0.0307 + when "0000011" => output1 <= "0000010101111110"; -- 0.0430 + when "0000100" => output1 <= "0000011100010000"; -- 0.0552 + when "0000101" => output1 <= "0000100010100001"; -- 0.0675 + when "0000110" => output1 <= "0000101000110010"; -- 0.0798 + when "0000111" => output1 <= "0000101111000011"; -- 0.0920 + when "0001000" => output1 <= "0000110101010011"; -- 0.1043 + when "0001001" => output1 <= "0000111011100011"; -- 0.1166 + when "0001010" => output1 <= "0001000001110010"; -- 0.1289 + when "0001011" => output1 <= "0001001000000000"; -- 0.1411 + when "0001100" => output1 <= "0001001110001110"; -- 0.1534 + when "0001101" => output1 <= "0001010100011011"; -- 0.1657 + when "0001110" => output1 <= "0001011010100111"; -- 0.1779 + when "0001111" => output1 <= "0001100000110011"; -- 0.1902 + when "0010000" => output1 <= "0001100110111101"; -- 0.2025 + when "0010001" => output1 <= "0001101101000110"; -- 0.2148 + when "0010010" => output1 <= "0001110011001111"; -- 0.2270 + when "0010011" => output1 <= "0001111001010110"; -- 0.2393 + when "0010100" => output1 <= "0001111111011100"; -- 0.2516 + when "0010101" => output1 <= "0010000101100001"; -- 0.2638 + when "0010110" => output1 <= "0010001011100100"; -- 0.2761 + when "0010111" => output1 <= "0010010001100111"; -- 0.2884 + when "0011000" => output1 <= "0010010111100111"; -- 0.3007 + when "0011001" => output1 <= "0010011101100111"; -- 0.3129 + when "0011010" => output1 <= "0010100011100101"; -- 0.3252 + when "0011011" => output1 <= "0010101001100001"; -- 0.3375 + when "0011100" => output1 <= "0010101111011011"; -- 0.3497 + when "0011101" => output1 <= "0010110101010100"; -- 0.3620 + when "0011110" => output1 <= "0010111011001100"; -- 0.3743 + when "0011111" => output1 <= "0011000001000001"; -- 0.3866 + when "0100000" => output1 <= "0011000110110100"; -- 0.3988 + when "0100001" => output1 <= "0011001100100110"; -- 0.4111 + when "0100010" => output1 <= "0011010010010110"; -- 0.4234 + when "0100011" => output1 <= "0011011000000011"; -- 0.4357 + when "0100100" => output1 <= "0011011101101111"; -- 0.4479 + when "0100101" => output1 <= "0011100011011000"; -- 0.4602 + when "0100110" => output1 <= "0011101000111111"; -- 0.4725 + when "0100111" => output1 <= "0011101110100100"; -- 0.4847 + when "0101000" => output1 <= "0011110100000111"; -- 0.4970 + when "0101001" => output1 <= "0011111001100111"; -- 0.5093 + when "0101010" => output1 <= "0011111111000101"; -- 0.5216 + when "0101011" => output1 <= "0100000100100000"; -- 0.5338 + when "0101100" => output1 <= "0100001001111001"; -- 0.5461 + when "0101101" => output1 <= "0100001111010000"; -- 0.5584 + when "0101110" => output1 <= "0100010100100011"; -- 0.5706 + when "0101111" => output1 <= "0100011001110100"; -- 0.5829 + when "0110000" => output1 <= "0100011111000011"; -- 0.5952 + when "0110001" => output1 <= "0100100100001110"; -- 0.6075 + when "0110010" => output1 <= "0100101001010111"; -- 0.6197 + when "0110011" => output1 <= "0100101110011101"; -- 0.6320 + when "0110100" => output1 <= "0100110011100000"; -- 0.6443 + when "0110101" => output1 <= "0100111000100000"; -- 0.6565 + when "0110110" => output1 <= "0100111101011101"; -- 0.6688 + when "0110111" => output1 <= "0101000010010111"; -- 0.6811 + when "0111000" => output1 <= "0101000111001110"; -- 0.6934 + when "0111001" => output1 <= "0101001100000001"; -- 0.7056 + when "0111010" => output1 <= "0101010000110010"; -- 0.7179 + when "0111011" => output1 <= "0101010101011111"; -- 0.7302 + when "0111100" => output1 <= "0101011010001001"; -- 0.7424 + when "0111101" => output1 <= "0101011110110000"; -- 0.7547 + when "0111110" => output1 <= "0101100011010011"; -- 0.7670 + when "0111111" => output1 <= "0101100111110011"; -- 0.7793 + when "1000000" => output1 <= "0101101100001111"; -- 0.7915 + when "1000001" => output1 <= "0101110000101000"; -- 0.8038 + when "1000010" => output1 <= "0101110100111101"; -- 0.8161 + when "1000011" => output1 <= "0101111001001111"; -- 0.8283 + when "1000100" => output1 <= "0101111101011101"; -- 0.8406 + when "1000101" => output1 <= "0110000001100111"; -- 0.8529 + when "1000110" => output1 <= "0110000101101110"; -- 0.8652 + when "1000111" => output1 <= "0110001001110001"; -- 0.8774 + when "1001000" => output1 <= "0110001101110000"; -- 0.8897 + when "1001001" => output1 <= "0110010001101011"; -- 0.9020 + when "1001010" => output1 <= "0110010101100010"; -- 0.9143 + when "1001011" => output1 <= "0110011001010110"; -- 0.9265 + when "1001100" => output1 <= "0110011101000101"; -- 0.9388 + when "1001101" => output1 <= "0110100000110001"; -- 0.9511 + when "1001110" => output1 <= "0110100100011001"; -- 0.9633 + when "1001111" => output1 <= "0110100111111100"; -- 0.9756 + when "1010000" => output1 <= "0110101011011011"; -- 0.9879 + when "1010001" => output1 <= "0110101110110111"; -- 1.0002 + when "1010010" => output1 <= "0110110010001110"; -- 1.0124 + when "1010011" => output1 <= "0110110101100001"; -- 1.0247 + when "1010100" => output1 <= "0110111000110000"; -- 1.0370 + when "1010101" => output1 <= "0110111011111010"; -- 1.0492 + when "1010110" => output1 <= "0110111111000000"; -- 1.0615 + when "1010111" => output1 <= "0111000010000010"; -- 1.0738 + when "1011000" => output1 <= "0111000101000000"; -- 1.0861 + when "1011001" => output1 <= "0111000111111001"; -- 1.0983 + when "1011010" => output1 <= "0111001010101110"; -- 1.1106 + when "1011011" => output1 <= "0111001101011110"; -- 1.1229 + when "1011100" => output1 <= "0111010000001010"; -- 1.1351 + when "1011101" => output1 <= "0111010010110001"; -- 1.1474 + when "1011110" => output1 <= "0111010101010100"; -- 1.1597 + when "1011111" => output1 <= "0111010111110011"; -- 1.1720 + when "1100000" => output1 <= "0111011010001101"; -- 1.1842 + when "1100001" => output1 <= "0111011100100010"; -- 1.1965 + when "1100010" => output1 <= "0111011110110011"; -- 1.2088 + when "1100011" => output1 <= "0111100000111111"; -- 1.2210 + when "1100100" => output1 <= "0111100011000110"; -- 1.2333 + when "1100101" => output1 <= "0111100101001001"; -- 1.2456 + when "1100110" => output1 <= "0111100111000111"; -- 1.2579 + when "1100111" => output1 <= "0111101001000001"; -- 1.2701 + when "1101000" => output1 <= "0111101010110101"; -- 1.2824 + when "1101001" => output1 <= "0111101100100101"; -- 1.2947 + when "1101010" => output1 <= "0111101110010001"; -- 1.3070 + when "1101011" => output1 <= "0111101111110111"; -- 1.3192 + when "1101100" => output1 <= "0111110001011001"; -- 1.3315 + when "1101101" => output1 <= "0111110010110110"; -- 1.3438 + when "1101110" => output1 <= "0111110100001110"; -- 1.3560 + when "1101111" => output1 <= "0111110101100001"; -- 1.3683 + when "1110000" => output1 <= "0111110110110000"; -- 1.3806 + when "1110001" => output1 <= "0111110111111001"; -- 1.3929 + when "1110010" => output1 <= "0111111000111110"; -- 1.4051 + when "1110011" => output1 <= "0111111001111110"; -- 1.4174 + when "1110100" => output1 <= "0111111010111001"; -- 1.4297 + when "1110101" => output1 <= "0111111011101111"; -- 1.4419 + when "1110110" => output1 <= "0111111100100000"; -- 1.4542 + when "1110111" => output1 <= "0111111101001100"; -- 1.4665 + when "1111000" => output1 <= "0111111101110100"; -- 1.4788 + when "1111001" => output1 <= "0111111110010110"; -- 1.4910 + when "1111010" => output1 <= "0111111110110100"; -- 1.5033 + when "1111011" => output1 <= "0111111111001101"; -- 1.5156 + when "1111100" => output1 <= "0111111111100000"; -- 1.5278 + when "1111101" => output1 <= "0111111111101111"; -- 1.5401 + when "1111110" => output1 <= "0111111111111001"; -- 1.5524 + when "1111111" => output1 <= "0111111111111110"; -- 1.5647 + when others => output1 <= (others => '0'); + end case; + end process; +end Behavioral; diff --git a/designs/encrypted_ip/cpu8080/delay.vhd b/designs/encrypted_ip/cpu8080/delay.vhd new file mode 100644 index 000000000..2cf2f3d09 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/delay.vhd @@ -0,0 +1,52 @@ +------------------------------------------------------------------------------- +-- MiniGA +-- Author: Thomas Pototschnig (thomas.pototschnig@gmx.de) +-- +-- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License +-- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ +-- +-- If you want to use MiniGA for commercial purposes please contact the author +------------------------------------------------------------------------------- +-- delay +-- for synchronizing u,v,y after FIR filter +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity delay is + generic ( + TAPS : integer := 8 -- group-delay der FIR-Filter ist 500ns + ); + + port ( + clk : in std_logic; + reset : in std_logic; + input : in std_logic_vector(11 downto 0); + output : out std_logic_vector(11 downto 0) + ); +end delay; + +architecture behaviour of delay is +begin + process (clk, reset) + type tsr is array(0 to TAPS-1) of signed(11 downto 0); + variable sr : tsr; + begin + if reset='0' then + for I in 0 to TAPS-1 loop + sr(I) := (others => '0'); + end loop; + output <= (others => '0'); + elsif clk'event and clk='1' then +-- Schieberegister + for I in (TAPS-1) downto 1 loop + sr(I):=sr(I-1); + end loop; + sr(0) := signed(input); + + output <= conv_std_logic_vector(sr(TAPS-1),12); + end if; + end process; + +end architecture; diff --git a/designs/encrypted_ip/cpu8080/design.yaml b/designs/encrypted_ip/cpu8080/design.yaml new file mode 100644 index 000000000..d685091b7 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/design.yaml @@ -0,0 +1,26 @@ +top: top + +include_all_vhdl_files: True + +include_all_verilog_files: True + + + +encrypted_ip: + user_files: ["top.v"] + ip: + - definition: "fixed_point_sqrt" + instances: + - "fixed_point_sqrt_0" + - definition: "graphiti" + instances: + - "graphiti_0" + - definition: "hight" + instances: + - "hight_0" + - definition: "lfsr_randgen" + instances: + - "lfsr_randgen_0" + - definition: "cpu8080" + instances: + - "cpu8080_0" \ No newline at end of file diff --git a/designs/encrypted_ip/cpu8080/fixed_point_sqrt.vhd b/designs/encrypted_ip/cpu8080/fixed_point_sqrt.vhd new file mode 100644 index 000000000..d27caff64 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/fixed_point_sqrt.vhd @@ -0,0 +1,177 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity fixed_point_sqrt is + generic( + WIDTH : positive := 32 + ); + port( + clk : in std_logic; + res : in std_logic; + ARG : in unsigned (WIDTH - 1 downto 0); + Z : out unsigned (WIDTH - 1 downto 0) + ); +end entity fixed_point_sqrt; + + +architecture rtl of fixed_point_sqrt is + +constant SQRT_LUT_K : positive := 8; +constant SQRT_LUT_N : positive := 128; --2^(K-1) +constant SQRT_ITER : positive := 3; + +type sqrt_table is array (natural range <>) of unsigned (WIDTH-1 downto 0); +type pipe is array (natural range <>) of unsigned (WIDTH - 1 downto 0); + +constant SQRT_TABLE_1 : sqrt_table(0 to SQRT_LUT_N -1) := ( +x"B504F334", x"B44F9363", x"B39C5088", x"B2EB2034", +x"B23BF845", x"B18ECED9", x"B0E39A54", x"B03A5158", +x"AF92EAC8", x"AEED5DC0", x"AE49A198", x"ADA7ADE2", +x"AD077A62", x"AC68FF15", x"ABCC3428", x"AB3111FD", +x"AA979122", x"A9FFAA55", x"A9695681", x"A8D48EBE", +x"A8414C4B", x"A7AF8892", x"A71F3D24", x"A69063BA", +x"A602F631", x"A576EE88", x"A4EC46E7", x"A462F992", +x"A3DB00F1", x"A354578E", x"A2CEF80E", x"A24ADD38", +x"A1C801EF", x"A1466132", x"A0C5F61D", x"A046BBE7", +x"9FC8ADE0", x"9F4BC775", x"9ED00428", x"9E555F96", +x"9DDBD571", x"9D636184", x"9CEBFFB1", x"9C75ABED", +x"9C006245", x"9B8C1ED8", x"9B18DDDC", x"9AA69B99", +x"9A355468", x"99C504B9", x"9955A90B", x"98E73DF0", +x"9879C009", x"980D2C0B", x"97A17EB9", x"9736B4E7", +x"96CCCB78", x"9663BF5F", x"95FB8D9D", x"95943342", +x"952DAD6B", x"94C7F945", x"94631407", x"93FEFAF9", +x"939BAB6C", x"933922C1", x"92D75E64", x"92765BCB", +x"9216187A", x"91B69200", x"9157C5F6", x"90F9B200", +x"909C53CF", x"903FA91C", x"8FE3AFAB", x"8F886548", +x"8F2DC7CC", x"8ED3D518", x"8E7A8B16", x"8E21E7B8", +x"8DC9E8FC", x"8D728CE5", x"8D1BD182", x"8CC5B4E8", +x"8C703534", x"8C1B508D", x"8BC70521", x"8B735123", +x"8B2032D2", x"8ACDA871", x"8A7BB04A", x"8A2A48B2", +x"89D97000", x"89892494", x"893964D5", x"88EA2F2F", +x"889B8216", x"884D5C04", x"87FFBB77", x"87B29EF6", +x"8766050B", x"8719EC47", x"86CE5342", x"86833897", +x"86389AE8", x"85EE78DC", x"85A4D11E", x"855BA261", +x"8512EB59", x"84CAAAC3", x"8482DF5D", x"843B87ED", +x"83F4A33B", x"83AE3016", x"83682D4F", x"832299BD", +x"82DD743A", x"8298BBA6", x"82546EE5", x"82108CDC", +x"81CD1478", x"818A04A6", x"81475C5C", x"81051A8E", +x"80C33E38", x"8081C657", x"8040B1ED", x"80000000" +); + + +constant SQRT_TABLE_2 : sqrt_table(0 to SQRT_LUT_N -1) := ( +x"FFFFFFFF", x"FE000000", x"FC07F020", x"FA17A17A", +x"F82EE698", x"F64D9365", x"F4737D1D", x"F2A07A45", +x"F0D4629B", x"EF0F0F0F", x"ED5059B2", x"EB981DAE", +x"E9E63740", x"E83A83A8", x"E694E122", x"E4F52EE0", +x"E35B4CFB", x"E1C71C72", x"E0387F1E", x"DEAF57AC", +x"DD2B8994", x"DBACF915", x"DA338B2B", x"D8BF258C", +x"D74FAE9F", x"D5E50D79", x"D47F29D4", x"D31DEC0D", +x"D1C13D1C", x"D0690690", x"CF15328C", x"CDC5ABBF", +x"CC7A5D62", x"CB333333", x"C9F01971", x"C8B0FCD7", +x"C775CA9A", x"C63E7064", x"C50ADC51", x"C3DAFCEA", +x"C2AEC126", x"C1861862", x"C060F25E", x"BF3F3F3F", +x"BE20EF88", x"BD05F418", x"BBEE3E26", x"BAD9BF44", +x"B9C86953", x"B8BA2E8C", x"B7AF0172", x"B6A6D4DB", +x"B5A19BE3", x"B49F49F5", x"B39FD2BE", x"B2A32A33", +x"B1A9448C", x"B0B21643", x"AFBD9411", x"AECBB2ED", +x"ADDC680B", x"ACEFA8DA", x"AC056B01", x"AB1DA461", +x"AA384B0F", x"A9555555", x"A874B9B3", x"A7966ED8", +x"A6BA6BA7", x"A5E0A72F", x"A50918B1", x"A433B799", +x"A3607B7F", x"A28F5C29", x"A1C05183", x"A0F353A5", +x"A0285ACC", x"9F5F5F5F", x"9E9859EA", x"9DD3431B", +x"9D1013CA", x"9C4EC4EC", x"9B8F4F9E", x"9AD1AD1B", +x"9A15D6C0", x"995BC60A", x"98A37495", x"97ECDC1D", +x"9737F679", x"9684BDA1", x"95D32BA6", x"95233AB7", +x"9474E51D", x"93C8253D", x"931CF593", x"927350B9", +x"91CB315D", x"91249249", x"907F6E5D", x"8FDBC091", +x"8F3983F2", x"8E98B3A6", x"8DF94AE6", x"8D5B4502", +x"8CBE9D5E", x"8C234F73", x"8B8956CC", x"8AF0AF0B", +x"8A5953E1", x"89C34116", x"892E727F", x"889AE409", +x"880891AC", x"87777777", x"86E79187", x"8658DC08", +x"85CB533A", x"853EF369", x"84B3B8F2", x"8429A043", +x"83A0A5D4", x"8318C632", x"8291FDF2", x"820C49BA", +x"8187A63F", x"81041041", x"8081848E", x"80000000" +); + + +constant one_and_half : unsigned(WIDTH-1 downto 0) := x"C0000000";--"11000000000000000000000000000000"; + +signal n : pipe(0 to SQRT_ITER); +signal n_next : pipe(0 to SQRT_ITER); +signal d : pipe(0 to SQRT_ITER); +signal d_next : pipe(0 to SQRT_ITER); +signal r : pipe(0 to SQRT_ITER); +signal r_next : pipe(0 to SQRT_ITER); +signal rsqr : pipe(0 to SQRT_ITER); +signal rsqr_next : pipe(0 to SQRT_ITER); + +begin + +-- pipe stages + + process(clk) is + begin + if rising_edge(clk) then + for i in 0 to SQRT_ITER loop + if (res = '0') then + n(i) <= (others => '0'); + d(i) <= (others => '0'); + r(i) <= (others => '0'); + rsqr(i) <= (others => '0'); + else + n(i) <= n_next(i); + d(i) <= d_next(i); + r(i) <= r_next(i); + rsqr(i) <= rsqr_next(i); + end if; + end loop; + end if; + end process; + +-- process inputs for the next stage + + process(d,r,rsqr,n,ARG) is + variable n_extended : unsigned(2*WIDTH-1 downto 0); + variable d_extended : unsigned(2*WIDTH-1 downto 0); + variable r_next_tmp : unsigned(WIDTH-1 downto 0); + variable d_shift : unsigned(WIDTH-1 downto 0); + variable rsqr_extended : unsigned(2*WIDTH-1 downto 0); + + variable index_vec : unsigned(SQRT_LUT_K-2 downto 0); + variable index : integer; + + begin + n_next(0) <= ARG; + d_next(0) <= ARG; + + index_vec := ARG(WIDTH - 3 downto WIDTH - SQRT_LUT_K - 1); + index := to_integer(index_vec); + + r_next(0) <= SQRT_TABLE_1(index); + rsqr_next(0)<= SQRT_TABLE_2(index); + + for i in 1 to SQRT_ITER loop + --operations + n_extended := n(i-1) * r(i-1); + d_extended := d(i-1) * rsqr(i-1); + d_shift := "0" & d_extended(2*WIDTH -2 downto WIDTH); + r_next_tmp := one_and_half - d_shift; + rsqr_extended := r_next_tmp * r_next_tmp; + + --assignments + n_next(i) <= n_extended(2*WIDTH-2 downto WIDTH-1); + d_next(i) <= d_extended(2*WIDTH-2 downto WIDTH-1); + rsqr_next(i) <= rsqr_extended(2*WIDTH-2 downto WIDTH-1); + r_next(i) <= r_next_tmp; + + end loop; + end process; + + +-- assign output + Z <= n(SQRT_ITER); + +end rtl; diff --git a/designs/encrypted_ip/cpu8080/graphiti.vhd b/designs/encrypted_ip/cpu8080/graphiti.vhd new file mode 100644 index 000000000..591efd7d6 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/graphiti.vhd @@ -0,0 +1,318 @@ +------------------------------------------------------------------------------- +-- MiniGA +-- Author: Thomas Pototschnig (thomas.pototschnig@gmx.de) +-- +-- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License +-- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ +-- +-- If you want to use MiniGA for commercial purposes please contact the author +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity graphiti is + Port ( + clk : in std_logic; + clk15M : in std_logic; + reset : in std_logic; + output : out std_logic_vector (15 downto 0); + in_r : in std_logic_vector (4 downto 0); + in_g : in std_logic_vector (4 downto 0); + in_b : in std_logic_vector (4 downto 0); + framereset : out std_logic; + en_bild : out std_logic; + readmem: out std_logic + ); +end graphiti; + +architecture behaviour of graphiti is + +component paltimer is + Port ( + clk : in std_logic; + clk15m : in std_logic; + reset : in std_logic; + en_sync : out std_logic; + en_schwarz : out std_logic; + en_bild : out std_logic; + en_vertbr : out std_logic; + en_verteq : out std_logic; + en_burst : out std_logic; + phase : out std_logic; + framereset : out std_logic; + sync : out std_logic; + readmem : out std_logic; + austastung : out std_logic + ); +end component; + +component dds is + Port ( + clk : in std_logic; + reset : in std_logic; + phase : in std_logic_vector (1 downto 0); + addi : out std_logic_vector (8 downto 0); + data : out std_logic_vector (15 downto 0) + ); +end component; + +component rgb2yuv is + Port ( + clk : in std_logic; + reset : in std_logic; + in_r, in_g, in_b : in std_logic_vector (4 downto 0); + out_y, out_u, out_v : out std_logic_vector (11 downto 0) + ); +end component; + +component myfir is + generic ( + TAPS : integer := 16 + ); + port ( + clk : in std_logic; + reset : in std_logic; + input : in std_logic_vector(11 downto 0); + output : out std_logic_vector(11 downto 0) + ); +end component; + +component delay is + generic ( + TAPS : integer := 8 -- group-delay der FIR-Filter ist 500ns + ); + port ( + clk : in std_logic; + reset : in std_logic; + input : in std_logic_vector(11 downto 0); + output : out std_logic_vector(11 downto 0) + ); +end component; + + +signal cos_data : signed (15 downto 0); +signal sin_data : signed (15 downto 0); + +signal pre_yuv_y : signed (11 downto 0); +signal pre_yuv_u : signed (11 downto 0); +signal pre_yuv_v : signed (11 downto 0); + +signal pre_yuv_u2 : signed (11 downto 0); +signal pre_yuv_v2 : signed (11 downto 0); + + + +signal yuv_y : signed (11 downto 0); +signal yuv_u : signed (11 downto 0); +signal yuv_v : signed (11 downto 0); + + +signal tmr_phase : std_logic; +signal tmr_sync : std_logic; +signal tmr_austastung : std_logic; +signal tmr_en_bild : std_logic; +signal tmr_en_burst : std_logic; + +--signal prevideo : signed (16 downto 0); +--signal preout_u : signed (16 downto 0); +--signal preout_v : signed (16 downto 0); +--signal preout_y : signed (16 downto 0); + +--pipelining wegen geschwindigkeit +signal modu : signed(27 downto 0); +signal modv : signed(27 downto 0); +signal mody : signed (11 downto 0); + +signal modus : signed(28 downto 0); +signal modvs : signed(28 downto 0); +signal modys : signed(28 downto 0); + + +-- workaround für xilinx +signal input_fir1 : std_logic_vector (11 downto 0); +signal input_fir2 : std_logic_vector (11 downto 0); +signal input_delay : std_logic_vector (11 downto 0); + +signal output_fir1 : std_logic_vector (11 downto 0); +signal output_fir2 : std_logic_vector (11 downto 0); +signal output_delay : std_logic_vector (11 downto 0); + +signal dds1_data : std_logic_vector (15 downto 0); +signal dds2_data : std_logic_vector (15 downto 0); + +signal rgb_out_v : std_logic_vector (11 downto 0); +signal rgb_out_u : std_logic_vector (11 downto 0); +signal rgb_out_y : std_logic_vector (11 downto 0); + + +begin + input_fir1 <= std_logic_vector(pre_yuv_u); + input_fir2 <= std_logic_vector(pre_yuv_v); + input_delay <= std_logic_vector(pre_yuv_y); + + yuv_u <= signed(output_fir1); + yuv_v <= signed(output_fir2); + yuv_y <= signed(output_delay); + +I_4: myfir port map ( + clk => clk15M, + reset => reset, + input => input_fir1, + output => output_fir1 +); + +I_5: myfir port map ( + clk => clk15M, + reset => reset, + input => input_fir2, + output => output_fir2 +); + +I_6: delay port map ( + clk => clk15M, + reset => reset, + input => input_delay, + output => output_delay + +); + +I_0: paltimer port map ( + clk => clk, + clk15m => clk15m, + reset => reset, + en_sync => open, + en_schwarz => open, + en_bild => tmr_en_bild, + en_vertbr => open, + en_verteq => open, + en_burst => tmr_en_burst, + phase => tmr_phase, + sync => tmr_sync, + austastung => tmr_austastung, + framereset => framereset, + readmem => readmem + ); + +I_1: dds port map ( + clk => clk, + reset => reset, + phase => "01", -- cosinus + addi => open, + data => dds1_data + ); + + cos_data <= signed(dds1_data); + sin_data <= signed(dds2_data); + +I_2: dds port map ( + clk => clk, + reset => reset, + phase => "00", -- sinus + addi => open, + data => dds2_data + ); + +I_3: rgb2yuv port map ( + clk => clk15m, + reset => reset, + in_r => in_r, + in_g => in_g, + in_b => in_b, + out_y => rgb_out_y, + out_u => rgb_out_u, + out_v => rgb_out_v + ); + +pre_yuv_y <= signed(rgb_out_y); +pre_yuv_u2 <= signed(rgb_out_u); +pre_yuv_v2 <= signed(rgb_out_v); + + +en_bild <= tmr_en_bild; + + +process (tmr_en_burst, tmr_austastung, tmr_en_bild, pre_yuv_u2, pre_yuv_v2) +begin + if tmr_austastung = '1' then + if tmr_en_bild='1' then + pre_yuv_u <= pre_yuv_u2; + pre_yuv_v <= pre_yuv_v2; + elsif tmr_en_burst = '1' then + pre_yuv_u <= conv_signed(-171,12); + pre_yuv_v <= conv_signed(171,12); + else + pre_yuv_u <= conv_signed(0,12); + pre_yuv_v <= conv_signed(0,12); + end if; + else + pre_yuv_u <= conv_signed(0,12); + pre_yuv_v <= conv_signed(0,12); + end if; +end process; + +process (clk, reset) + +variable skaleuv : signed(16 downto 0) := conv_signed(30000,17);--40000 +variable skaley : signed(16 downto 0) := conv_signed(36408,17); +variable skaleburst : signed (11 downto 0) := conv_signed(240,12); +variable psin : signed (15 downto 0); + +variable preout_u : signed (16 downto 0); +variable preout_v : signed (16 downto 0); +variable preout_y : signed (16 downto 0); +variable prevideo : signed (16 downto 0); + +variable bursts : signed (27 downto 0); + +variable burstsin : signed (17 downto 0); +variable burstcos : signed (17 downto 0); +variable burst17 : signed (16 downto 0); + +variable i_output : signed (16 downto 0); + +begin + + if reset='0' then + output <= (others => '0'); + elsif clk'event and clk='1' then + if tmr_phase='1' then + psin := -sin_data; + else + psin := sin_data; + end if; + +-- u und v modulieren + modu <= cos_data * yuv_u; + modv <= psin * yuv_v; + mody <= yuv_y; + +-- jetzt skalieren + modus <= modu (26 downto 15) * skaleuv; + modvs <= modv (26 downto 15) * skaleuv; + modys <= mody * skaley; -- yuv_y + + preout_u := modus (26 downto 10); + preout_v := modvs (26 downto 10); + preout_y := modys (26 downto 10); + +-- Y, U und V jetzt zum Signal zusammenbauen + prevideo := preout_u + preout_v; + + if tmr_austastung = '1' and tmr_en_bild='1' then + prevideo := prevideo + preout_y; + end if; + + if tmr_sync ='0' then + i_output := (others => '0'); + else + i_output := conv_signed(14563,17) + prevideo; + end if; + + output <= conv_std_logic_vector (i_output (15 downto 0),16); + + end if; +end process; + +end behaviour; diff --git a/designs/encrypted_ip/cpu8080/hight.v b/designs/encrypted_ip/cpu8080/hight.v new file mode 100644 index 000000000..d499d14d8 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/hight.v @@ -0,0 +1,181 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Top module for HIGHT Crypto Core //// +//// //// +//// This file is part of the HIGHT Crypto Core project //// +//// http://github.com/OpenSoCPlus/hight_crypto_core //// +//// http://www.opencores.org/project,hight //// +//// //// +//// Description //// +//// __description__ //// +//// //// +//// Author(s): //// +//// - JoonSoo Ha, json.ha@gmail.com //// +//// - Younjoo Kim, younjookim.kr@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module hight( + rstn , + clk , + + i_mk_rdy , + i_mk , + + i_post_rdy , + + i_op , + + i_text_val , + i_text_in , + + o_text_done , + o_text_out , + + o_rdy +); + + +//===================================== +// +// PARAMETERS +// +//===================================== + + +//===================================== +// +// I/O PORTS +// +//===================================== +input rstn ; +input clk ; + +input i_mk_rdy ; +input[127:0] i_mk ; + +input i_post_rdy ; + +input i_op ; + +input i_text_val ; +input[63:0] i_text_in ; + +output o_text_done ; +output[63:0] o_text_out ; + +output o_rdy ; + + +//===================================== +// +// REGISTERS +// +//===================================== + + +//===================================== +// +// WIRES +// +//===================================== +wire[31:0] w_rnd_key ; + +wire[2:0] w_xf_sel ; +wire w_rf_final ; + +wire w_key_sel ; +wire[4:0] w_rnd_idx ; +wire w_wf_post_pre ; + + +//===================================== +// +// MAIN +// +//===================================== +// CYPTO_PATH instance +CRYPTO_PATH u_CRYPTO_PATH( + .rstn ( rstn ) , + .clk ( clk ) , + + .i_op ( i_op ) , + + .i_wrsk ( w_rnd_key ) , + + .i_text_in ( i_text_in ) , + + .i_xf_sel ( w_xf_sel ) , + .i_rf_final ( w_rf_final ) , + + .o_text_out ( o_text_out ) +); + + +// KEY_SCHED instance +KEY_SCHED u_KEY_SCHED( + .rstn ( rstn ) , + .clk ( clk ) , + + .i_mk ( i_mk ) , + + .i_op ( i_op ) , + + .i_key_sel ( w_key_sel ) , + .i_rnd_idx ( w_rnd_idx ) , + .i_wf_post_pre ( w_wf_post_pre ) , + + .o_rnd_key ( w_rnd_key ) +); + + +// CONTROL instance +CONTROL u_CONTROL( + .rstn ( rstn ) , + .clk ( clk ) , + + .i_mk_rdy ( i_mk_rdy ) , + .i_post_rdy ( i_post_rdy ) , + .i_text_val ( i_text_val ) , + + + .o_rdy ( o_rdy ) , + .o_text_done ( o_text_done ) , + + .o_xf_sel ( w_xf_sel ) , + .o_rf_final ( w_rf_final ) , + + .o_key_sel ( w_key_sel ) , + .o_rnd_idx ( w_rnd_idx ) , + .o_wf_post_pre ( w_wf_post_pre ) +); + + +endmodule + + diff --git a/designs/encrypted_ip/cpu8080/lfsr_pkg.vhd b/designs/encrypted_ip/cpu8080/lfsr_pkg.vhd new file mode 100644 index 000000000..ee24d5916 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/lfsr_pkg.vhd @@ -0,0 +1,405 @@ +---------------------------------------------------------------------------- +---- Create Date: 14:30:08 07/28/2010 ---- +---- Design Name: lfsr_pkg ---- +---- Project Name: lfsr_randgen ---- +---- Description: ---- +---- This is the package file used in the lfsr_randgen project.The ---- +---- package contain the function for XORing bits from various tap ---- +---- locations depending on the generic parameter(width of lfsr ) ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- This file is a part of the lfsr_randgen project at ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Author(s): ---- +---- Vipin Lal, lalnitt@gmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2010 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +package lfsr_pkg is + +function xor_gates( random : std_logic_vector) return std_logic; + +end lfsr_pkg; + +--Package body starts from here. +package body lfsr_pkg is + +--function for XORing from tap values. +function xor_gates( random : std_logic_vector ) return std_logic is + +variable xor_out : std_logic:='0'; +variable rand : std_logic_vector(random'length-1 downto 0):=random; + +begin +if(rand'length = 3) then --3 +xor_out := rand(2) xor rand(1); +elsif(rand'length = 4) then --4 +xor_out := rand(3) xor rand(2); +elsif(rand'length = 5) then --5 +xor_out := rand(4) xor rand(2); +elsif(rand'length = 6) then --6 +xor_out := rand(5) xor rand(4); +elsif(rand'length = 7) then --7 +xor_out := rand(6) xor rand(5); +elsif(rand'length = 8) then --8 +xor_out := rand(7) xor rand(5) xor rand(4) xor rand(3); +elsif(rand'length = 9) then --9 +xor_out := rand(8) xor rand(4); +elsif(rand'length = 10)then --10 +xor_out := rand(9) xor rand(6); +elsif(rand'length =11) then --11 +xor_out := rand(10) xor rand(8); +elsif(rand'length = 12) then --12 +xor_out := rand(11) xor rand(5) xor rand(3) xor rand(0); +elsif(rand'length = 13) then --13 +xor_out := rand(12) xor rand(3) xor rand(2) xor rand(0); +elsif(rand'length = 14) then --14 +xor_out := rand(13) xor rand(4) xor rand(2) xor rand(0); +elsif(rand'length = 15) then --15 +xor_out := rand(14) xor rand(13); +elsif(rand'length = 16) then --16 +xor_out := rand(15) xor rand(14) xor rand(12) xor rand(3); +elsif(rand'length = 17) then --17 +xor_out := rand(16) xor rand(13); +elsif(rand'length = 18) then --18 +xor_out := rand(17) xor rand(10); +elsif(rand'length = 19) then --19 +xor_out := rand(18) xor rand(5) xor rand(1) xor rand(0); +elsif(rand'length = 20) then --20 +xor_out := rand(19) xor rand(16); +elsif(rand'length = 21) then --21 +xor_out := rand(20) xor rand(18); +elsif(rand'length = 22) then --22 +xor_out := rand(21) xor rand(20); +elsif(rand'length = 23) then --23 +xor_out := rand(22) xor rand(17); +elsif(rand'length = 24) then --24 +xor_out := rand(23) xor rand(22) xor rand(21) xor rand(16); +elsif(rand'length = 25) then --25 +xor_out := rand(24) xor rand(21); +elsif(rand'length = 26) then --26 +xor_out := rand(25) xor rand(5) xor rand(1) xor rand(0); +elsif(rand'length = 27) then --27 +xor_out := rand(26) xor rand(4) xor rand(1) xor rand(0); +elsif(rand'length = 28) then --28 +xor_out := rand(27) xor rand(24); +elsif(rand'length = 29) then --29 +xor_out := rand(28) xor rand(26); +elsif(rand'length = 30) then --30 +xor_out := rand(29) xor rand(5) xor rand(3) xor rand(0); +elsif(rand'length = 31) then --31 +xor_out := rand(30) xor rand(27); +elsif(rand'length = 32) then --32 +xor_out := rand(31) xor rand(21) xor rand(1) xor rand(0); +elsif(rand'length = 33) then --33 +xor_out := rand(32) xor rand(19); +elsif(rand'length = 34) then --34 +xor_out := rand(33) xor rand(26) xor rand(1) xor rand(0); +elsif(rand'length = 35) then --35 +xor_out := rand(34) xor rand(32); +elsif(rand'length = 36) then --36 +xor_out := rand(35) xor rand(24); +elsif(rand'length = 37) then --37 +xor_out := rand(36) xor rand(4) xor rand(3) xor rand(2) xor rand(1) xor rand(0); +elsif(rand'length = 38) then --38 +xor_out := rand(37) xor rand(5) xor rand(4) xor rand(0); +elsif(rand'length = 39) then --39 +xor_out := rand(38) xor rand(34); +elsif(rand'length = 40) then --40 +xor_out := rand(39) xor rand(37) xor rand(20) xor rand(18); +elsif(rand'length = 41) then --41 +xor_out := rand(40) xor rand(37); +elsif(rand'length = 42) then --42 +xor_out := rand(41) xor rand(40) xor rand(19) xor rand(18); +elsif(rand'length = 43) then --43 +xor_out := rand(42) xor rand(41) xor rand(37) xor rand(36); +elsif(rand'length = 44) then --44 +xor_out := rand(43) xor rand(42) xor rand(17) xor rand(16); +elsif(rand'length = 45) then --45 +xor_out := rand(44) xor rand(43) xor rand(41) xor rand(40); +elsif(rand'length = 46) then --46 +xor_out := rand(45) xor rand(44) xor rand(25) xor rand(24); +elsif(rand'length = 47) then --47 +xor_out := rand(46) xor rand(41); +elsif(rand'length = 48) then --48 +xor_out := rand(47) xor rand(46) xor rand(20) xor rand(19); +elsif(rand'length = 49) then --49 +xor_out := rand(48) xor rand(39); +elsif(rand'length = 50) then --50 +xor_out := rand(49) xor rand(48) xor rand(23) xor rand(22); +elsif(rand'length = 51) then --51 +xor_out := rand(50) xor rand(49) xor rand(35) xor rand(34); +elsif(rand'length = 52) then --52 +xor_out := rand(51) xor rand(48); +elsif(rand'length = 53) then --53 +xor_out := rand(52) xor rand(51) xor rand(37) xor rand(36); +elsif(rand'length = 54) then --54 +xor_out := rand(53) xor rand(52) xor rand(17) xor rand(16); +elsif(rand'length = 55) then --55 +xor_out := rand(54) xor rand(30); +elsif(rand'length = 56) then --56 +xor_out := rand(55) xor rand(54) xor rand(34) xor rand(33); +elsif(rand'length = 57) then --57 +xor_out := rand(56) xor rand(49); +elsif(rand'length = 58) then --58 +xor_out := rand(57) xor rand(38); +elsif(rand'length = 59) then --59 +xor_out := rand(58) xor rand(57) xor rand(37) xor rand(36); +elsif(rand'length = 60) then --60 +xor_out := rand(59) xor rand(58); +elsif(rand'length = 61) then --61 +xor_out := rand(60) xor rand(59) xor rand(45) xor rand(44); +elsif(rand'length = 62) then --62 +xor_out := rand(61) xor rand(60) xor rand(5) xor rand(4); +elsif(rand'length = 63) then --63 +xor_out := rand(62) xor rand(61); +elsif(rand'length = 64) then --64 +xor_out := rand(63) xor rand(62) xor rand(60) xor rand(59); +elsif(rand'length = 65) then --65 +xor_out := rand(64) xor rand(46); +elsif(rand'length = 66) then --66 +xor_out := rand(65) xor rand(64) xor rand(56) xor rand(55); +elsif(rand'length = 67) then --67 +xor_out := rand(66) xor rand(65) xor rand(57) xor rand(56); +elsif(rand'length = 68) then --68 +xor_out := rand(67) xor rand(58); +elsif(rand'length = 69) then --69 +xor_out := rand(68) xor rand(66) xor rand(41) xor rand(39); +elsif(rand'length = 70) then --70 +xor_out := rand(69) xor rand(68) xor rand(54) xor rand(53); +elsif(rand'length = 71) then --71 +xor_out := rand(70) xor rand(64); +elsif(rand'length = 72) then --72 +xor_out := rand(71) xor rand(65) xor rand(24) xor rand(18); +elsif(rand'length = 73) then --73 +xor_out := rand(72) xor rand(47); +elsif(rand'length = 74) then --74 +xor_out := rand(73) xor rand(72) xor rand(58) xor rand(57); +elsif(rand'length = 75) then --75 +xor_out := rand(74) xor rand(73) xor rand(64) xor rand(63); +elsif(rand'length = 76) then --76 +xor_out := rand(75) xor rand(74) xor rand(40) xor rand(39); +elsif(rand'length = 77) then --77 +xor_out := rand(76) xor rand(75) xor rand(46) xor rand(45); +elsif(rand'length = 78) then --78 +xor_out := rand(77) xor rand(76) xor rand(58) xor rand(57); +elsif(rand'length = 79) then --79 +xor_out := rand(78) xor rand(69); +elsif(rand'length = 80) then --80 +xor_out := rand(79) xor rand(78) xor rand(42) xor rand(41); +elsif(rand'length = 81) then --81 +xor_out := rand(80) xor rand(76); +elsif(rand'length = 82) then --82 +xor_out := rand(81) xor rand(78) xor rand(46) xor rand(43); +elsif(rand'length = 83) then --83 +xor_out := rand(82) xor rand(81) xor rand(37) xor rand(36); +elsif(rand'length = 84) then --84 +xor_out := rand(83) xor rand(70); +elsif(rand'length = 85) then --85 +xor_out := rand(84) xor rand(83) xor rand(57) xor rand(56); +elsif(rand'length = 86) then --86 +xor_out := rand(85) xor rand(84) xor rand(73) xor rand(72); +elsif(rand'length = 87) then --87 +xor_out := rand(86) xor rand(73); +elsif(rand'length = 88) then --88 +xor_out := rand(87) xor rand(86) xor rand(16) xor rand(15); +elsif(rand'length = 89) then --89 +xor_out := rand(88) xor rand(50); +elsif(rand'length = 90) then --90 +xor_out := rand(89) xor rand(88) xor rand(71) xor rand(70); +elsif(rand'length = 91) then --91 +xor_out := rand(90) xor rand(89) xor rand(7) xor rand(6); +elsif(rand'length = 92) then --92 +xor_out := rand(91) xor rand(90) xor rand(79) xor rand(78); +elsif(rand'length = 93) then --93 +xor_out := rand(92) xor rand(90); +elsif(rand'length = 94) then --94 +xor_out := rand(93) xor rand(72); +elsif(rand'length = 95) then --95 +xor_out := rand(94) xor rand(83); +elsif(rand'length = 96) then --96 +xor_out := rand(95) xor rand(93) xor rand(48) xor rand(46); +elsif(rand'length = 97) then --97 +xor_out := rand(96) xor rand(90); +elsif(rand'length = 98) then --98 +xor_out := rand(97) xor rand(86); +elsif(rand'length = 99) then --99 +xor_out := rand(98) xor rand(96) xor rand(53) xor rand(51); +elsif(rand'length = 100) then --100 +xor_out := rand(99) xor rand(62); +elsif(rand'length = 101) then --101 +xor_out := rand(100) xor rand(99) xor rand(94) xor rand(93); +elsif(rand'length = 102) then --102 +xor_out := rand(101) xor rand(100) xor rand(35) xor rand(34); +elsif(rand'length = 103) then --103 +xor_out := rand(102) xor rand(93); +elsif(rand'length = 104) then --104 +xor_out := rand(103) xor rand(102) xor rand(93) xor rand(92); +elsif(rand'length = 105) then --105 +xor_out := rand(104) xor rand(88); +elsif(rand'length = 106) then --106 +xor_out := rand(105) xor rand(90); +elsif(rand'length = 107) then --107 +xor_out := rand(106) xor rand(104) xor rand(43) xor rand(41); +elsif(rand'length = 108) then --108 +xor_out := rand(107) xor rand(76); +elsif(rand'length = 109) then --109 +xor_out := rand(108) xor rand(107) xor rand(102) xor rand(101); +elsif(rand'length = 110)then --110 +xor_out := rand(109) xor rand(108) xor rand(97) xor rand(96); +elsif(rand'length = 111) then --111 +xor_out := rand(110) xor rand(100); +elsif(rand'length = 112) then --112 +xor_out := rand(111) xor rand(109) xor rand(68) xor rand(66); +elsif(rand'length = 113) then --113 +xor_out := rand(112) xor rand(103); +elsif(rand'length = 114) then --114 +xor_out := rand(113) xor rand(112) xor rand(32) xor rand(31); +elsif(rand'length = 115) then --115 +xor_out := rand(114) xor rand(113) xor rand(100) xor rand(99); +elsif(rand'length = 116) then --116 +xor_out := rand(115) xor rand(114) xor rand(45) xor rand(44); +elsif(rand'length = 117) then --117 +xor_out := rand(116) xor rand(114) xor rand(98) xor rand(96); +elsif(rand'length = 118) then --118 +xor_out := rand(117) xor rand(84); +elsif(rand'length = 119) then --119 +xor_out := rand(118) xor rand(110); +elsif(rand'length = 120) then --120 +xor_out := rand(119) xor rand(112) xor rand(8) xor rand(1); +elsif(rand'length = 121) then --121 +xor_out := rand(120) xor rand(102); +elsif(rand'length = 122) then --122 +xor_out := rand(121) xor rand(120) xor rand(62) xor rand(61); +elsif(rand'length = 123) then --123 +xor_out := rand(122) xor rand(120); +elsif(rand'length = 124) then --124 +xor_out := rand(123) xor rand(86); +elsif(rand'length = 125) then --125 +xor_out := rand(124) xor rand(123) xor rand(17) xor rand(16); +elsif(rand'length = 126) then --126 +xor_out := rand(125) xor rand(124) xor rand(89) xor rand(88); +elsif(rand'length = 127) then --127 +xor_out := rand(126) xor rand(125); +elsif(rand'length = 128) then --128 +xor_out := rand(127) xor rand(125) xor rand(100) xor rand(98); +elsif(rand'length = 129) then --129 +xor_out := rand(128) xor rand(123); +elsif(rand'length = 130) then --130 +xor_out := rand(129) xor rand(126); +elsif(rand'length = 131) then --131 +xor_out := rand(130) xor rand(129) xor rand(83) xor rand(82); +elsif(rand'length = 132) then --132 +xor_out := rand(131) xor rand(102); +elsif(rand'length = 133) then --133 +xor_out := rand(132) xor rand(131) xor rand(81) xor rand(80); +elsif(rand'length = 134) then --134 +xor_out := rand(133) xor rand(76); +elsif(rand'length = 135) then --135 +xor_out := rand(134) xor rand(123); +elsif(rand'length = 136) then --136 +xor_out := rand(135) xor rand(134) xor rand(10) xor rand(9); +elsif(rand'length = 137) then --137 +xor_out := rand(136) xor rand(115); +elsif(rand'length = 138) then --138 +xor_out := rand(137) xor rand(136) xor rand(130) xor rand(129); +elsif(rand'length = 139) then --139 +xor_out := rand(138) xor rand(135) xor rand(133) xor rand(130); +elsif(rand'length = 140) then --140 +xor_out := rand(139) xor rand(110); +elsif(rand'length = 141) then --141 +xor_out := rand(140) xor rand(139) xor rand(109) xor rand(108); +elsif(rand'length = 142) then --142 +xor_out := rand(141) xor rand(120); +elsif(rand'length = 143) then --143 +xor_out := rand(142) xor rand(141) xor rand(122) xor rand(121); +elsif(rand'length = 144) then --144 +xor_out := rand(143) xor rand(142) xor rand(74) xor rand(73); +elsif(rand'length = 145) then --145 +xor_out := rand(144) xor rand(92); +elsif(rand'length = 146) then --146 +xor_out := rand(145) xor rand(144) xor rand(86) xor rand(85); +elsif(rand'length = 147) then --147 +xor_out := rand(146) xor rand(145) xor rand(109) xor rand(108); +elsif(rand'length = 148) then --148 +xor_out := rand(147) xor rand(120); +elsif(rand'length = 149) then --149 +xor_out := rand(148) xor rand(147) xor rand(39) xor rand(38); +elsif(rand'length = 150) then --150 +xor_out := rand(149) xor rand(96); +elsif(rand'length = 151) then --151 +xor_out := rand(150) xor rand(147); +elsif(rand'length = 152) then --152 +xor_out := rand(151) xor rand(150) xor rand(86) xor rand(85); +elsif(rand'length = 153) then --153 +xor_out := rand(152) xor rand(151); +elsif(rand'length = 154) then --154 +xor_out := rand(153) xor rand(151) xor rand(26) xor rand(24); +elsif(rand'length = 155) then --155 +xor_out := rand(154) xor rand(153) xor rand(123) xor rand(122); +elsif(rand'length = 156) then --156 +xor_out := rand(155) xor rand(154) xor rand(40) xor rand(39); +elsif(rand'length = 157) then --157 +xor_out := rand(156) xor rand(155) xor rand(130) xor rand(129); +elsif(rand'length = 158) then --158 +xor_out := rand(157) xor rand(156) xor rand(131) xor rand(130); +elsif(rand'length = 159) then --159 +xor_out := rand(158) xor rand(127); +elsif(rand'length = 160) then --160 +xor_out := rand(159) xor rand(158) xor rand(141) xor rand(140); +elsif(rand'length = 161) then --161 +xor_out := rand(160) xor rand(142); +elsif(rand'length = 162) then --162 +xor_out := rand(161) xor rand(160) xor rand(74) xor rand(73); +elsif(rand'length = 163) then --163 +xor_out := rand(162) xor rand(161) xor rand(103) xor rand(102); +elsif(rand'length = 164) then --164 +xor_out := rand(163) xor rand(162) xor rand(150) xor rand(149); +elsif(rand'length = 165) then --165 +xor_out := rand(164) xor rand(163) xor rand(134) xor rand(133); +elsif(rand'length = 166) then --166 +xor_out := rand(165) xor rand(164) xor rand(127) xor rand(126); +elsif(rand'length = 167) then --167 +xor_out := rand(166) xor rand(160); +elsif(rand'length = 168) then --168 +xor_out := rand(167) xor rand(165) xor rand(152) xor rand(150); +end if; + +return xor_out; +end xor_gates; +--END function for XORing using tap values. + +end lfsr_pkg; +--End of the package. \ No newline at end of file diff --git a/designs/encrypted_ip/cpu8080/lfsr_randgen.vhd b/designs/encrypted_ip/cpu8080/lfsr_randgen.vhd new file mode 100644 index 000000000..b9ed8bc76 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/lfsr_randgen.vhd @@ -0,0 +1,89 @@ +---------------------------------------------------------------------------- +---- Create Date: 13:06:08 07/28/2010 ---- +---- Design Name: lfsr_randgen ---- +---- Project Name: lfsr_randgen ---- +---- Description: ---- +---- A random number generator based on linear feedback shift ---- +---- register(LFSR).A LFSR is a shift register whose input bit is a ---- +---- linear function of its previous state.The detailed documentation ---- +---- is available in the file named manual.pdf. ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- This file is a part of the lfsr_randgen project at ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Author(s): ---- +---- Vipin Lal, lalnitt@gmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2010 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library work; +use work.lfsr_pkg.ALL; + +entity lfsr_randgen is + generic (width : integer := 4); +port (clk : in std_logic; + set_seed : in std_logic; + seed : in std_logic_vector(width-1 downto 0); + rand_out : out std_logic_vector(width-1 downto 0) + ); +end lfsr_randgen; + +architecture Behavioral of lfsr_randgen is + +begin + +process(clk) + +variable rand_temp : std_logic_vector (width-1 downto 0):=(0 => '1',others => '0'); +variable temp : std_logic := '0'; + +begin + +if(rising_edge(clk)) then + +if(set_seed = '1') then +rand_temp := seed; +end if; + +temp := xor_gates(rand_temp); +rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0); +rand_temp(0) := temp; + +end if; +rand_out <= rand_temp; + +end process; + +end Behavioral; + diff --git a/designs/encrypted_ip/cpu8080/myfir.vhd b/designs/encrypted_ip/cpu8080/myfir.vhd new file mode 100644 index 000000000..06b9e2ad3 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/myfir.vhd @@ -0,0 +1,66 @@ +------------------------------------------------------------------------------- +-- MiniGA +-- Author: Thomas Pototschnig (thomas.pototschnig@gmx.de) +-- +-- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License +-- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ +-- +-- If you want to use MiniGA for commercial purposes please contact the author +------------------------------------------------------------------------------- +-- fir filter +-- uses even and symmetric number of coefficients +-- input format: s0,xxxxxxxxxx +-- input must be <1024! +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity myfir is + generic ( + TAPS : integer := 16 + ); + + port ( + clk : in std_logic; + reset : in std_logic; + input : in std_logic_vector(11 downto 0); + output : out std_logic_vector(11 downto 0) + ); +end myfir; + +architecture behaviour of myfir is +begin + process (clk, reset) + type tsr is array(0 to TAPS-1) of signed(11 downto 0); + type tcoff is array(0 to (TAPS/2)-1) of signed(11 downto 0); +-- format: s0,xxxxxxxxxx; +-- koeffizienten für 16tap 1,3MHz hamming-tiefpass bei 15MHz sampling frequenz + variable coff : tcoff := ( + x"FFA", x"FFB", x"004", x"027", x"06E", x"0D0", x"132", x"170" + ); + variable sr : tsr; + variable y : signed (63 downto 0); + begin + if reset='0' then + for I in 0 to TAPS-1 loop + sr(I) := (others => '0'); + end loop; + output <= (others => '0'); + elsif clk'event and clk='1' then +-- Schieberegister + for I in (TAPS-1) downto 1 loop + sr(I):=sr(I-1); + end loop; + sr(0) := signed(input); +-- jetzt berechnen + y:= (others => '0'); + for I in 0 to (TAPS/2)-1 loop + y:=y+ (sr(I) + sr((TAPS-1)-I)) * coff(I); + end loop; + + output <= conv_std_logic_vector(y(22 downto 11),12); + end if; + end process; + +end architecture; diff --git a/designs/encrypted_ip/cpu8080/paltimer.vhd b/designs/encrypted_ip/cpu8080/paltimer.vhd new file mode 100644 index 000000000..b09aca863 --- /dev/null +++ b/designs/encrypted_ip/cpu8080/paltimer.vhd @@ -0,0 +1,211 @@ +------------------------------------------------------------------------------- +-- MiniGA +-- Author: Thomas Pototschnig (thomas.pototschnig@gmx.de) +-- +-- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License +-- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ +-- +-- If you want to use MiniGA for commercial purposes please contact the author +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity paltimer is + Port ( clk : in std_logic; + clk15m : in std_logic; + reset : in std_logic; + en_sync : out std_logic; + en_schwarz : out std_logic; + en_bild : out std_logic; + en_vertbr : out std_logic; + en_verteq : out std_logic; + en_burst : out std_logic; + phase : out std_logic; + sync : out std_logic; + framereset : out std_logic; + readmem : out std_logic; + austastung : out std_logic); + +end paltimer; + +architecture Behavioral of paltimer is + +attribute clock_signal : string; + +begin + process (clk15m, reset) + variable pixctr : integer := 0; + variable hlctr : integer :=0; + variable i_en_sync : std_logic := '0'; + variable i_en_sync_last : std_logic := '0'; + + variable i_en_schwarz : std_logic := '0'; + variable i_en_bild : std_logic := '0'; + variable i_en_burst : std_logic := '0'; + variable i_en_vertbr : std_logic := '0'; + variable i_en_vertbr_last : std_logic := '0'; + variable i_en_verteq : std_logic := '0'; + variable i_austastung : std_logic := '0'; + variable i_framereset : std_logic := '0'; + variable i_sync : std_logic := '0'; + variable i_readmem : std_logic := '0'; + variable i_phase : std_logic := '0'; + variable i_sync_c : integer := 0; + begin + if reset='0' then + pixctr := 0; + hlctr :=0; + i_en_sync := '0'; + i_en_schwarz := '0'; + i_en_bild := '0'; + i_en_burst := '0'; + i_en_vertbr := '0'; + i_en_verteq := '0'; + i_austastung := '0'; + i_framereset := '0'; + i_sync := '0'; + i_readmem := '0'; + i_phase := '0'; + + en_sync <= '0'; + en_schwarz <= '0'; + en_bild <= '0'; + en_vertbr <= '0'; + en_verteq <= '0'; + en_burst <= '0'; + phase <= '0'; + sync <= '0'; + framereset <= '1'; + readmem <= '0'; + austastung <= '0'; + elsif clk15m'event and clk15m='1' then + pixctr:=pixctr+1; + if pixctr = 960 then + pixctr:=0; + end if; + + if pixctr >= 0 AND pixctr <= 70 then + i_en_sync := '1'; + else + i_en_sync := '0'; + end if; +-- flanke nochmal checken ... + if i_en_sync ='0' and i_en_sync_last='1' then + i_phase := NOT i_phase; + end if; + + i_en_sync_last := i_en_sync; + + if (pixctr >= 0 AND pixctr <= 157 ) then + i_en_schwarz := '1'; + elsif (pixctr >= 938 AND pixctr <= 959 ) then + i_en_schwarz := '1'; + else + i_en_schwarz := '0'; + end if; + + if pixctr >= 158 AND pixctr <= 937 then + i_en_bild := '1'; + else + i_en_bild := '0'; + end if; + + if pixctr >= 81 AND pixctr <= 118 then + i_en_burst := '1'; + else + i_en_burst := '0'; + end if; + + + if pixctr >= 0 AND pixctr <= 408 then + i_en_vertbr := '1'; + elsif pixctr >= 480 AND pixctr <= 888 then + i_en_vertbr := '1'; + else + i_en_vertbr := '0'; + end if; + + if pixctr >= 0 AND pixctr <= 34 then + i_en_verteq := '1'; + elsif pixctr >= 480 AND pixctr <= 514 then + i_en_verteq := '1'; + else + i_en_verteq := '0'; + end if; + + if i_en_vertbr='1' and i_en_vertbr_last='0' then + hlctr:=hlctr+1; + + if hlctr = 1250 then + hlctr:=0; + i_framereset := '1'; + else + i_framereset := '0'; + end if; + + if hlctr >= 0 and hlctr <= 4 then + i_sync_c := 1; + elsif hlctr >= 5 and hlctr <= 9 then + i_sync_c := 2; + elsif hlctr >= 10 and hlctr <= 619 then + i_sync_c := 3; + elsif hlctr >= 620 and hlctr <= 624 then + i_sync_c := 2; + elsif hlctr >= 625 and hlctr <= 629 then + i_sync_c := 1; + elsif hlctr >= 630 and hlctr <= 634 then + i_sync_c := 2; + elsif hlctr >= 635 and hlctr <= 1244 then + i_sync_c := 3; + elsif hlctr >= 1245 and hlctr <= 1249 then + i_sync_c := 2; + else + i_sync_c := 0; + end if; + + if hlctr >= 1245 and hlctr <= 1249 then + i_austastung := '1'; + elsif hlctr >= 0 and hlctr <= 44 then + i_austastung := '1'; + elsif hlctr >= 620 and hlctr <= 668 then + i_austastung := '1'; + else + i_austastung := '0'; + end if; + + if hlctr >= 42 and hlctr <= 617 then + i_readmem := '1'; + elsif hlctr >= 668 and hlctr <= 1241 then + i_readmem := '1'; + else + i_readmem := '0'; + end if; + end if; + + i_en_vertbr_last := i_en_vertbr; + + case i_sync_c is + when 0 => i_sync := '0'; + when 1 => i_sync := i_en_vertbr; + when 2 => i_sync := i_en_verteq; + when 3 => i_sync := i_en_sync; + when others => i_sync := '0'; + end case; + + phase <= i_phase; + en_sync <= i_en_sync; + en_schwarz <= i_en_schwarz; + en_bild <= i_en_bild; + en_vertbr <= i_en_vertbr; + en_verteq <= i_en_verteq; + en_burst <= i_en_burst; + readmem <= i_readmem; + sync <= NOT i_sync; + austastung <= NOT i_austastung; + framereset <= i_framereset; + end if; + end process; + +end Behavioral; diff --git a/designs/encrypted_ip/cpu8080/rgb2yuv.vhd b/designs/encrypted_ip/cpu8080/rgb2yuv.vhd new file mode 100644 index 000000000..1e3444c9e --- /dev/null +++ b/designs/encrypted_ip/cpu8080/rgb2yuv.vhd @@ -0,0 +1,169 @@ +------------------------------------------------------------------------------- +-- MiniGA +-- Author: Thomas Pototschnig (thomas.pototschnig@gmx.de) +-- +-- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License +-- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ +-- +-- If you want to use MiniGA for commercial purposes please contact the author +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity rgb2yuv is + Port ( clk : in std_logic; + reset : in std_logic; + in_r, in_g, in_b : in std_logic_vector (4 downto 0); -- signed + out_y, out_u, out_v : out std_logic_vector (11 downto 0)); -- unsigned +end rgb2yuv; + +architecture Behavioral of rgb2yuv is +begin + process (clk, reset) + variable multu : signed (11 downto 0) := conv_signed (517,12); + variable multv : signed (11 downto 0) := conv_signed (929,12); + variable var_y : signed (11 downto 0); + variable in_rs : signed (11 downto 0); + variable in_gs : signed (11 downto 0); + variable in_bs : signed (11 downto 0); + + variable worku24 : signed (23 downto 0); + variable workv24 : signed (23 downto 0); + + variable rsigned : signed (11 downto 0) := conv_signed(0,12); + variable bsigned : signed (11 downto 0) := conv_signed(0,12); + + begin + if reset='0' then + out_u <= (others => '0'); + out_v <= (others => '0'); + out_y <= (others => '0'); + elsif clk='1' and clk'event then + case in_r is + when "00000" => in_rs := "000000000000"; -- 0.0000 + when "00001" => in_rs := "000000001001"; -- 0.0094 + when "00010" => in_rs := "000000010011"; -- 0.0187 + when "00011" => in_rs := "000000011100"; -- 0.0281 + when "00100" => in_rs := "000000100110"; -- 0.0375 + when "00101" => in_rs := "000000110000"; -- 0.0469 + when "00110" => in_rs := "000000111001"; -- 0.0562 + when "00111" => in_rs := "000001000011"; -- 0.0656 + when "01000" => in_rs := "000001001100"; -- 0.0750 + when "01001" => in_rs := "000001010110"; -- 0.0844 + when "01010" => in_rs := "000001100000"; -- 0.0938 + when "01011" => in_rs := "000001101001"; -- 0.1031 + when "01100" => in_rs := "000001110011"; -- 0.1125 + when "01101" => in_rs := "000001111100"; -- 0.1219 + when "01110" => in_rs := "000010000110"; -- 0.1313 + when "01111" => in_rs := "000010010000"; -- 0.1406 + when "10000" => in_rs := "000010011001"; -- 0.1500 + when "10001" => in_rs := "000010100011"; -- 0.1594 + when "10010" => in_rs := "000010101100"; -- 0.1687 + when "10011" => in_rs := "000010110110"; -- 0.1781 + when "10100" => in_rs := "000011000000"; -- 0.1875 + when "10101" => in_rs := "000011001001"; -- 0.1969 + when "10110" => in_rs := "000011010011"; -- 0.2062 + when "10111" => in_rs := "000011011100"; -- 0.2156 + when "11000" => in_rs := "000011100110"; -- 0.2250 + when "11001" => in_rs := "000011110000"; -- 0.2344 + when "11010" => in_rs := "000011111001"; -- 0.2437 + when "11011" => in_rs := "000100000011"; -- 0.2531 + when "11100" => in_rs := "000100001100"; -- 0.2625 + when "11101" => in_rs := "000100010110"; -- 0.2719 + when "11110" => in_rs := "000100100000"; -- 0.2813 + when "11111" => in_rs := "000100101001"; -- 0.2906 + when others => in_rs := (others => '0'); + end case; + + case in_g is + when "00000" => in_gs := "000000000000"; -- 0.0000 + when "00001" => in_gs := "000000010010"; -- 0.0184 + when "00010" => in_gs := "000000100101"; -- 0.0369 + when "00011" => in_gs := "000000111000"; -- 0.0553 + when "00100" => in_gs := "000001001011"; -- 0.0737 + when "00101" => in_gs := "000001011110"; -- 0.0922 + when "00110" => in_gs := "000001110001"; -- 0.1106 + when "00111" => in_gs := "000010000100"; -- 0.1291 + when "01000" => in_gs := "000010010111"; -- 0.1475 + when "01001" => in_gs := "000010101001"; -- 0.1659 + when "01010" => in_gs := "000010111100"; -- 0.1844 + when "01011" => in_gs := "000011001111"; -- 0.2028 + when "01100" => in_gs := "000011100010"; -- 0.2213 + when "01101" => in_gs := "000011110101"; -- 0.2397 + when "01110" => in_gs := "000100001000"; -- 0.2581 + when "01111" => in_gs := "000100011011"; -- 0.2766 + when "10000" => in_gs := "000100101110"; -- 0.2950 + when "10001" => in_gs := "000101000000"; -- 0.3134 + when "10010" => in_gs := "000101010011"; -- 0.3319 + when "10011" => in_gs := "000101100110"; -- 0.3503 + when "10100" => in_gs := "000101111001"; -- 0.3687 + when "10101" => in_gs := "000110001100"; -- 0.3872 + when "10110" => in_gs := "000110011111"; -- 0.4056 + when "10111" => in_gs := "000110110010"; -- 0.4241 + when "11000" => in_gs := "000111000101"; -- 0.4425 + when "11001" => in_gs := "000111011000"; -- 0.4609 + when "11010" => in_gs := "000111101010"; -- 0.4794 + when "11011" => in_gs := "000111111101"; -- 0.4978 + when "11100" => in_gs := "001000010000"; -- 0.5162 + when "11101" => in_gs := "001000100011"; -- 0.5347 + when "11110" => in_gs := "001000110110"; -- 0.5531 + when "11111" => in_gs := "001001001001"; -- 0.5716 + when others => in_gs := (others => '0'); + end case; + + case in_b is + when "00000" => in_bs := "000000000000"; -- 0.0000 + when "00001" => in_bs := "000000000011"; -- 0.0034 + when "00010" => in_bs := "000000000111"; -- 0.0069 + when "00011" => in_bs := "000000001010"; -- 0.0103 + when "00100" => in_bs := "000000001110"; -- 0.0138 + when "00101" => in_bs := "000000010001"; -- 0.0172 + when "00110" => in_bs := "000000010101"; -- 0.0206 + when "00111" => in_bs := "000000011000"; -- 0.0241 + when "01000" => in_bs := "000000011100"; -- 0.0275 + when "01001" => in_bs := "000000011111"; -- 0.0309 + when "01010" => in_bs := "000000100011"; -- 0.0344 + when "01011" => in_bs := "000000100110"; -- 0.0378 + when "01100" => in_bs := "000000101010"; -- 0.0413 + when "01101" => in_bs := "000000101101"; -- 0.0447 + when "01110" => in_bs := "000000110001"; -- 0.0481 + when "01111" => in_bs := "000000110100"; -- 0.0516 + when "10000" => in_bs := "000000111000"; -- 0.0550 + when "10001" => in_bs := "000000111011"; -- 0.0584 + when "10010" => in_bs := "000000111111"; -- 0.0619 + when "10011" => in_bs := "000001000010"; -- 0.0653 + when "10100" => in_bs := "000001000110"; -- 0.0688 + when "10101" => in_bs := "000001001001"; -- 0.0722 + when "10110" => in_bs := "000001001101"; -- 0.0756 + when "10111" => in_bs := "000001010000"; -- 0.0791 + when "11000" => in_bs := "000001010100"; -- 0.0825 + when "11001" => in_bs := "000001011000"; -- 0.0859 + when "11010" => in_bs := "000001011011"; -- 0.0894 + when "11011" => in_bs := "000001011111"; -- 0.0928 + when "11100" => in_bs := "000001100010"; -- 0.0963 + when "11101" => in_bs := "000001100110"; -- 0.0997 + when "11110" => in_bs := "000001101001"; -- 0.1031 + when "11111" => in_bs := "000001101101"; -- 0.1066 + when others => in_bs := (others => '0'); + end case; + + rsigned := (others => '0'); + bsigned := (others => '0'); + + rsigned (9 downto 5) := signed(in_r); + bsigned (9 downto 5) := signed(in_b); + + var_y := signed(in_rs) + signed(in_gs) + signed(in_bs); + + worku24 := (bsigned-signed(var_y))* multu; + workv24 := (rsigned-signed(var_y))* multv; + + out_u <= conv_std_logic_vector(worku24 (21 downto 10),12); + out_v <= conv_std_logic_vector(workv24 (21 downto 10),12); + out_y <= conv_std_logic_vector (var_y, var_y'length); + end if; + end process; + +end Behavioral; diff --git a/designs/encrypted_ip/cpu8080/top.v b/designs/encrypted_ip/cpu8080/top.v new file mode 100644 index 000000000..1780f391e --- /dev/null +++ b/designs/encrypted_ip/cpu8080/top.v @@ -0,0 +1,121 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11/09/2017 02:08:02 PM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module top( + input clk, + input reset, + input [15:0] sw, + input [4:0] btn, // Not used + output [15:0] led, + output [6:0] seg, // Not used + output dp, // Not used + output [7:0] an // Not used + ); + + wire [31:0] Z; + wire btnCpuReset; + wire [7:0] sw2, JA, JB, JC, JD; + + assign btnCpuReset = reset; + assign sw2 = sw[7:0]; + assign JA = sw[15:8]; + assign JB = {btn, sw[15:13]}; + assign JC = {btn ^ sw[12:8], btn[2:0] & sw[2:0]}; + assign JD = {sw[15:8] ^ sw[7:0]}; + + + + fixed_point_sqrt fixed_point_sqrt_0( + .clk(clk), + .res(btnCpuReset), + .ARG({JA, JB, JC, JD}), + .Z(Z) + ); + + wire [15:0] my_output; + wire framereset, en_bild, readmem; + + graphiti graphiti_0( + .clk(clk), + .clk15M(clk), + .reset(btnCpuReset), + .\output (my_output), + .in_r(JA[3:0]), + .in_g(JB[3:0]), + .in_b(JC[3:0]), + .framereset(framereset), + .en_bild(en_bild), + .readmem(readmem) + ); + + wire o_text_done, o_rdy; + wire [63:0] o_text_out; + + hight hight_0( + .rstn(btnCpuReset), + .clk(clk), + .i_mk_rdy(sw2[0]), + .i_mk({16{JA}}), + .i_post_rdy(sw2[1]), + .i_op(sw2[2]), + .i_text_val(sw2[3]), + .i_text_in({2{Z}}), + .o_text_done(o_text_done), + .o_text_out(o_text_out), + .o_rdy(o_rdy) + ); + + wire [3:0] rand_out; + + lfsr_randgen lfsr_randgen_0( + .clk(clk), + .set_seed(o_rdy), + .seed({4{o_text_done}}), + .rand_out(rand_out) + ); + + wire [15:0] addr; + wire readmem_cpu, writemem, readio, writeio, inta; + wire [7:0] data; + + cpu8080 cpu8080_0( + .addr(addr), + .data(data), + .readmem(readmem_cpu), + .writemem(writemem), + .readio(readio), + .writeio(writeio), + .intr(framereset ^ en_bild ^ readmem), + .inta(inta), + .waitr(^rand_out[3:0]), + .reset(btnCpuReset), + .clock(clk) + ); + + assign led[4:0] = {readmem_cpu, writemem, readio, writeio, inta}; + assign led[5] = ^addr; + assign led[6] = ^my_output; + assign led[7] = o_text_out ^ readmem; + assign led[15:8] = data; + + +endmodule diff --git a/designs/encrypted_ip/pic/basic_component.vhd b/designs/encrypted_ip/pic/basic_component.vhd new file mode 100644 index 000000000..416a1dc58 --- /dev/null +++ b/designs/encrypted_ip/pic/basic_component.vhd @@ -0,0 +1,63 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.basic_size.all; +package basic_component is +component parallel_find_top is +GENERIC (N: NATURAL := N ; WIDTH :NATURAL := WIDTH); +port ( a : in WORD_ARRAY; + y : out STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) + ); +end component parallel_find_top; + +component mux_sel is +GENERIC (level:INTEGER:=0; Cell_count:INTEGER:=8); +port( + left_op: in std_logic_vector(Cell_count-1 downto 0 ); + right_op: in std_logic_vector(Cell_count-1 downto 0 ); + o: out std_logic_vector(Cell_count-1 downto 0 ) +); +end component mux_sel; + +component Ripple is +GENERIC (cells : Natural:=6); +port( + left_op : IN std_logic_vector (cells -1 DOWNTO 0); + right_op : IN std_logic_vector (cells -1 DOWNTO 0); + choose_cur : out std_logic; + found_cur : out std_logic; + choose_sel : OUT std_logic_vector (cells -1 DOWNTO 0)); +end component Ripple; +component Result is +GENERIC (Cell_count : Natural:=6); +port( + i1: in std_logic_vector(Cell_count-1 downto 0); + i2: in std_logic_vector(Cell_count-1 downto 0); + choose_sel : In std_logic_vector(Cell_count-1 downto 0); + o: out std_logic_vector(Cell_count-1 downto 0 )); + end component Result; + +COMPONENT carry_cell_NOR is +port( + a: IN std_logic; + b: IN std_logic; + choose_prev : in std_logic; + found_prev : in std_logic; + choose_cur_bar : out std_logic; + found_cur_bar : out std_logic); +end COMPONENT carry_cell_NOR; +COMPONENT carry_cell_NAND is +port( + a: IN std_logic; + b: IN std_logic; + choose_prev_bar : in std_logic; + found_prev_bar : in std_logic; + choose_cur : out std_logic; + found_cur : out std_logic); +end COMPONENT carry_cell_NAND; + + +end package basic_component; + +package body basic_component is +end package body; \ No newline at end of file diff --git a/designs/encrypted_ip/pic/basic_size.vhd b/designs/encrypted_ip/pic/basic_size.vhd new file mode 100644 index 000000000..97b97d0c4 --- /dev/null +++ b/designs/encrypted_ip/pic/basic_size.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +package basic_size is + function log2_ceil(N : integer) return integer; + function count_satges(cells : integer) return integer; + function odd_even_stage(i : integer; ripple_width : integer; cs_w : integer) return integer ; +constant width : integer :=8; +constant N : integer := 64; +constant logN : integer := log2_ceil(N); + + +--constant P_stages : integer := count_satges(N); +constant K : integer := 2; + +type n_ports_array is array (0 to N-1) of std_logic_vector(width-1 downto 0); +type max_tornment_array is array (0 to N-2) of std_logic_vector(width-1 downto 0); + +TYPE WORD IS array (WIDTH-1 DOWNTO 0) of STD_LOGIC; +type WORD_ARRAY is array (0 TO N-1 ) of std_logic_vector(width-1 downto 0); + +end package basic_size; + +package body basic_size is +function log2_ceil(N : integer) return integer is +begin + +if (N <= 2) then +return 1; +else +if (N mod 2 = 0) then +return 1 + log2_ceil(N/2); +else +return 1 + log2_ceil((N+1)/2); +end if; +end if; +end function log2_ceil; + +function count_satges(cells : integer) return integer is +variable K : integer := 2; --original input. +variable P : integer := 0; --original input. +variable a : integer := 1; --original input. +variable series : integer := 0; --original input. +begin +counter : while a**2 +(a*(2*K -1))+2*(K - cells ) - K < 0 loop + a := a + 1; +end loop counter; +return a; +end function count_satges; + + + + function odd_even_stage(i : integer; ripple_width : integer; cs_w : integer) return integer is +variable rp_width : integer := 2 ; --original input. +begin + if i = 0 then + return (ripple_width mod 2); + elsif cs_w mod 2 = 0 then + return i mod 2; +else return 1; +end if; +end function odd_even_stage; + +end package body; \ No newline at end of file diff --git a/designs/encrypted_ip/pic/design.yaml b/designs/encrypted_ip/pic/design.yaml new file mode 100644 index 000000000..7c67e5a31 --- /dev/null +++ b/designs/encrypted_ip/pic/design.yaml @@ -0,0 +1,25 @@ +top: top + +include_all_vhdl_files: True + +include_all_verilog_files: True + +encrypted_ip: + ip: + - definition: "pci_mini" + instances: + - "pci_mini_0" + - definition: "pic" + instances: + - "pic_0" + - definition: "potato" + instances: + - "potato_0" + - definition: "pwm" + instances: + - "pwm_0" + - definition: "quadratic_func" + instances: + - "quadratic_func_0" + + user_files: ["top.v"] \ No newline at end of file diff --git a/designs/encrypted_ip/pic/down_clocking_even.v b/designs/encrypted_ip/pic/down_clocking_even.v new file mode 100644 index 000000000..bfebb0130 --- /dev/null +++ b/designs/encrypted_ip/pic/down_clocking_even.v @@ -0,0 +1,37 @@ +/*Down clocking module +Output clock frequency is the original frequency divided by an even number +*/ +module down_clocking_even( +input i_clk, +input i_rst, +input [15:0]i_divisor, +output o_clk +); + +wire [15:0]divisor; +wire borrow; + +minus_one minus_one_0( +i_divisor, +divisor, +borrow +); + +wire go; +assign go=((i_divisor!=0)&&i_rst); +reg [15:0]ct; +reg clk; +always@(posedge i_clk or negedge i_rst) + if(!i_rst)begin + ct<=0; + clk<=0; + end + else if(go)begin + if(ct>=divisor)begin + ct<=0; + clk<=~clk; + end + else ct<=ct+1; + end +assign o_clk=go?clk:i_clk; +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pic/down_clocking_odd.v b/designs/encrypted_ip/pic/down_clocking_odd.v new file mode 100644 index 000000000..52f48de34 --- /dev/null +++ b/designs/encrypted_ip/pic/down_clocking_odd.v @@ -0,0 +1,69 @@ +/*Author: Zhuxu + m99a1@yahoo.cn +Down clocking module +Output clock frequency is the original frequency divided by an odd number +*/ +module down_clocking_odd( +input i_clk, +input i_rst, +input [15:0]i_divisor, +output o_clk +); + +reg a,b; +wire c; + +assign c=(~a)&(~b); +wire [15:0]divisor; +wire borrow; +minus_one minus_one_0( +i_divisor, +divisor, +borrow +); + +wire go; +assign go=((i_divisor!=0)&&i_rst); +reg [15:0]ct_0; +always@(posedge i_clk or negedge i_rst) + if(!i_rst)begin + a<=0; + ct_0<=0; + end + else if(go)begin + if(a)begin + if(ct_0>=divisor)begin + ct_0<=0; + a<=0; + end + else ct_0<=ct_0+1; + end + else if(c)a<=c; + end + + +reg [15:0]ct_1; +always@(negedge i_clk or negedge i_rst) + if(!i_rst)begin + b<=0; + ct_1<=0; + end + else if(go)begin + if(b)begin + if(ct_1>=divisor)begin + ct_1<=0; + b<=0; + end + else ct_1<=ct_1+1; + end + else if(c)b<=c; + end + +reg clk; +always@(posedge c or negedge i_rst) + if(!i_rst)clk<=0; + else clk<=~clk; + +assign o_clk=go?clk:i_clk; + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pic/minus_one.v b/designs/encrypted_ip/pic/minus_one.v new file mode 100644 index 000000000..f3575c94f --- /dev/null +++ b/designs/encrypted_ip/pic/minus_one.v @@ -0,0 +1,122 @@ +/*Author: Zhuxu + m99a1@yahoo.cn +Use parallel prefix tree structure to reduce a 16-bit number by one. + +stage 0: number of genration=16; number of logic operation=16; G_0[xx]=~i_operand[xx]; +stage 1: NOG=16; NOO=8; G_1[2n-1]=G_0[2n-1]&&G_0[2n-2]; n=8:1 +stage 2: NOG=16; NOO=7; G_2[2n-1]=G_1[2n-1]&&G_1[2n-3]; n=8:2 +stage 3: NOG=16; NOO=6; G_3[2n-1]=G_2[2n-1]&&G_2[2n-5]; n=8:3 +stage 4: NOG=16; NOO=4; G_4[2n-1]=G_3[2n-1]&&G_3[2n-9]; n=8:5 +stage 5: NOG=16; NOO=7; G_5[2n]=G_4[2n]&&G_4[2n-1]; n=7:1 + +*/ +module minus_one( +input [15:0]i_operand, +output [15:0]o_result, +output o_borrow +); +//stage 0 +wire [15:0]G_0; +assign G_0=~i_operand; + +//stage 1 +wire [15:0]G_1; +assign G_1[1]=G_0[1]&G_0[0]; +assign G_1[3]=G_0[3]&G_0[2]; +assign G_1[5]=G_0[5]&G_0[4]; +assign G_1[7]=G_0[7]&G_0[6]; +assign G_1[9]=G_0[9]&G_0[8]; +assign G_1[11]=G_0[11]&G_0[10]; +assign G_1[13]=G_0[13]&G_0[12]; +assign G_1[15]=G_0[15]&G_0[14]; +assign G_1[0]=G_0[0]; +assign G_1[2]=G_0[2]; +assign G_1[4]=G_0[4]; +assign G_1[6]=G_0[6]; +assign G_1[8]=G_0[8]; +assign G_1[10]=G_0[10]; +assign G_1[12]=G_0[12]; +assign G_1[14]=G_0[14]; + +//stage 2 +wire [15:0]G_2; +assign G_2[3]=G_1[3]&G_1[1]; +assign G_2[5]=G_1[5]&G_1[3]; +assign G_2[7]=G_1[7]&G_1[5]; +assign G_2[9]=G_1[9]&G_1[7]; +assign G_2[11]=G_1[11]&G_1[9]; +assign G_2[13]=G_1[13]&G_1[11]; +assign G_2[15]=G_1[15]&G_1[13]; +assign G_2[0]=G_1[0]; +assign G_2[2]=G_1[2]; +assign G_2[1]=G_1[1]; +assign G_2[4]=G_1[4]; +assign G_2[6]=G_1[6]; +assign G_2[8]=G_1[8]; +assign G_2[10]=G_1[10]; +assign G_2[12]=G_1[12]; +assign G_2[14]=G_1[14]; + +//stage 3 +wire [15:0]G_3; +assign G_3[5]=G_2[5]&G_2[1]; +assign G_3[7]=G_2[7]&G_2[3]; +assign G_3[9]=G_2[9]&G_2[5]; +assign G_3[11]=G_2[11]&G_2[7]; +assign G_3[13]=G_2[13]&G_2[9]; +assign G_3[15]=G_2[15]&G_2[11]; +assign G_3[0]=G_2[0]; +assign G_3[2]=G_2[2]; +assign G_3[1]=G_2[1]; +assign G_3[4]=G_2[4]; +assign G_3[3]=G_2[3]; +assign G_3[6]=G_2[6]; +assign G_3[8]=G_2[8]; +assign G_3[10]=G_2[10]; +assign G_3[12]=G_2[12]; +assign G_3[14]=G_2[14]; + +//stage 4 +wire [15:0]G_4; +assign G_4[9]=G_3[9]&G_3[1]; +assign G_4[11]=G_3[11]&G_3[3]; +assign G_4[13]=G_3[13]&G_3[5]; +assign G_4[15]=G_3[15]&G_3[7]; +assign G_4[0]=G_3[0]; +assign G_4[2]=G_3[2]; +assign G_4[1]=G_3[1]; +assign G_4[4]=G_3[4]; +assign G_4[3]=G_3[3]; +assign G_4[6]=G_3[6]; +assign G_4[5]=G_3[5]; +assign G_4[8]=G_3[8]; +assign G_4[7]=G_3[7]; +assign G_4[10]=G_3[10]; +assign G_4[12]=G_3[12]; +assign G_4[14]=G_3[14]; + +//stage 5 +wire [15:0]G_5; +assign G_5[2]=G_4[2]&G_4[1]; +assign G_5[4]=G_4[4]&G_4[3]; +assign G_5[6]=G_4[6]&G_4[5]; +assign G_5[8]=G_4[8]&G_4[7]; +assign G_5[10]=G_4[10]&G_4[9]; +assign G_5[12]=G_4[12]&G_4[11]; +assign G_5[14]=G_4[14]&G_4[13]; +assign G_5[1]=G_4[1]; +assign G_5[3]=G_4[3]; +assign G_5[5]=G_4[5]; +assign G_5[7]=G_4[7]; +assign G_5[9]=G_4[9]; +assign G_5[11]=G_4[11]; +assign G_5[13]=G_4[13]; +assign G_5[15]=G_4[15]; +assign G_5[0]=G_4[0]; + +//stage 6 +assign o_result[0]=~i_operand[0]; +assign o_result[15:1]=(G_5[14:0]&(~i_operand[15:1]))|((~G_5[14:0])&i_operand[15:1]); +assign o_borrow=G_5[15]; + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pic/pci_mini.v b/designs/encrypted_ip/pic/pci_mini.v new file mode 100644 index 000000000..5f389a5c8 --- /dev/null +++ b/designs/encrypted_ip/pic/pci_mini.v @@ -0,0 +1,626 @@ +// *************************************************************** // +// // +// PCI_TARGET-Wishbone_MASTER INTERFACE MODULE (PCI-mini) // +// v2.0 // +// // +// The original PCI module is from: Ben Jackson // +// http://www.ben.com/minipci/verilog.php // +// // +// Redesigned for wishbone : Istvan Nagy, buenos@freemail.hu // +// PEC Products, Industrial Technologies // +// // +// *************************************************************** // + +// The core implements a 16MB relocable memory image. Relocable on the +// wb bus. the wb address = 4M*wb_baseaddr_reg + PCI_addr[23:2] +// Only Dword aligned Dword accesses allowed on the PCI. This way +// we can access to the 4GB wb-space through a 16MB PCI-window. +// The addressing on the wb-bus, is Dword addressing, while on the +// PCI bus, the addressing is byte addressing. A(pci_mini)=A(wb)*4 +// The PCI address is increasing by 4, and we get 4 bytes. The wb +// address is increasing by 1, and we get 1 Dword (= 4 bytes also). +// The wb_baseaddr_reg is the wb image relocation register, can be +// accessed at 50h address in the PCI configuration space. +// Other bridge status and command is at the 54h and 58h addresses. +// if access fails with timeout, then the address will be in the +// wb address will be stored in the failed_addr_reg at 5Ch address. +// +// Wishbone compatibility: +// Wishbone signals: wb_address, wb_dat_o, wb_dat_i, wb_sel_o, wb_cyc_o, +// wb_stb_o, wb_wr_o, wb_reset_o, wb_clk_o, wb_ack_i. +// Not implemented wb signals: error, lock, retry, tag-signals. +// The peripheral has to response with ack in 16 clk cycles. +// The core has wishbone clk and reset outputs, just like a Syscon module. +// The core generates single reads/writes. These are made of 4 phases, so +// dont write new data, until internal data movement finishes: about 300...500ns +// +// PCI compatibility: +// Only single DWORD reads/writes are supported. between them, the software has +// to wait 300...500nsec, to prevent data corrupting. STOP signaling is not +// implemented, so target terminations also not. +// Single Byte access is NOT supported! It may cause corrupt data. +// The core uses INTA interrupt signal. There are some special PCI config +// registers, from 50h...60h config-space addresses. +// PCI-parity: it generates parity, but doesnt check incoming parity. +// Because of the PC chipset, if you read a value and write it back, +// the chipset will not write anything, because it can see the data is not +// changed. This is important at some peripherals, where you write, to control. +// Device specific PCI config header registers: +// name: addr: function: +// wb_baseaddr_reg; 50h A(wb)=(A(pci_mini)-BAR0)/4 + wb_baseaddr_reg +// user_status_reg; 54h not used yet +// user_command_reg; 58h not used yet +// failed_addr_reg; 5Ch address, when timeout occurs on the wb bus. +// +// Local bus arbitration: +// This is not really wishbone compatible, but needed for the PCI. +// The method is: "brute force". it means if the PCI interface wants to +// be mastering on the local (wishbone) bus, then it will be mastering, +// so, the other master(s) must stop anything immediately. The req signal +// goes high when there is an Address hit on teh PCI bus. so the other +// master has few clk cycles to finish. +// Restrictions: the peripherals have to be fast: If the other master +// starts a transaction before req goes high, the ack has to arrive before +// the PCI interface starts its own transaction. (max 4clk ACK delay) +// The other master or the bus unit must sense the req, and give bus +// mastering to the PCI-IF immediatelly, not just when the other master +// finished everything, like at normal arbitration schemes. +// +// Buffering: +// There is a single Dword buffering only. +// +// The led_out interface: +// only for system-debug: we can write to the LEDs, at any address. +// (in the same time there is a wishbone write also) +// +// Changes since original version: wishbone interface, +// bigger memory-image, parity-generation, +// interrupt handling. Code size is 3x bigger. New registers, +// +// *************************************************************** // + + + +module pci_mini(reset,clk,frame,irdy,trdy,devsel,idsel,ad,cbe,par,stop,inta,serr,perr,led_out, wb_address, wb_dat_o, wb_dat_i, wb_sel_o, wb_cyc_o, wb_stb_o, wb_wr_o, wb_reset_o, wb_clk_o, wb_ack_i, wb_irq, wb_req, wb_gnt, wb_req_other); + input reset; + input clk; + input frame; + input irdy; + output trdy; + output devsel; + input idsel; + inout [31:0] ad; + input [3:0] cbe; + inout par; + output stop; + output inta; + output serr; + output perr; + output [3:0] led_out; + output [31:0] wb_address; + output [31:0] wb_dat_o; + input [31:0] wb_dat_i; + output [3:0] wb_sel_o; + output wb_cyc_o; + output wb_stb_o; + output wb_wr_o; + output wb_reset_o; + output wb_clk_o; + input wb_ack_i; + input wb_irq; + output wb_req; + input wb_gnt; + input wb_req_other; + + + +parameter DEVICE_ID = 16'h9500; +parameter VENDOR_ID = 16'h10EE; // 16'h10EE=xilinx, 16'h106d; // Sequent! +parameter DEVICE_CLASS = 24'h068000; // Bridge device - other_bridge_type (original:FF0000 Misc) +parameter DEVICE_REV = 8'h01; +parameter SUBSYSTEM_ID = 16'h0001; // Card identifier +parameter SUBSYSTEM_VENDOR_ID = 16'hBEBE; // Card identifier +parameter DEVSEL_TIMING = 2'b00; // Fast! + +reg [2:0] state; +reg [31:0] data; + +reg [1:0] enable; +parameter EN_NONE = 0; +parameter EN_RD = 1; +parameter EN_WR = 2; +parameter EN_TR = 3; + +reg memen; // respond to baseaddr? +reg [7:0] baseaddr; +reg [5:0] address; + +reg [9:0] wb_baseaddr_reg; //remap the image on the wishbone bus +reg [31:0] wb_address_1; +reg [31:0] user_status_reg; +reg [31:0] user_command_reg; +reg [31:0] failed_addr_reg; +reg [31:0] dummy_reg; +reg [31:0] pci_read_reg; +reg [31:0] pci_write_reg; +reg [31:0] wb_read_reg; +reg [31:0] wb_write_reg; +reg [3:0] pci_read_sel_reg; +reg [3:0] pci_write_sel_reg; +reg [3:0] wb_read_sel_reg; +reg [3:0] wb_write_sel_reg; + +parameter ST_IDLE = 3'b000; +parameter ST_BUSY = 3'b010; +parameter ST_MEMREAD = 3'b100; +parameter ST_MEMWRITE = 3'b101; +parameter ST_CFGREAD = 3'b110; +parameter ST_CFGWRITE = 3'b111; + +parameter MEMREAD = 4'b0110; +parameter MEMWRITE = 4'b0111; +parameter CFGREAD = 4'b1010; +parameter CFGWRITE = 4'b1011; + +`define LED +`ifdef LED +reg [3:0] led; +`endif + +`undef STATE_DEBUG_LED +`ifdef STATE_DEBUG_LED +assign led_out = ~state; +`else +`ifdef LED +assign led_out = ~led; +`endif +`endif + +assign ad = (enable == EN_RD) ? data : 32'bZ; +assign trdy = (enable == EN_NONE) ? 'bZ : (enable == EN_TR ? 1 : 0); +//assign par = (enable == EN_RD) ? 0 : 'bZ; +reg devsel; + +assign stop = 1'bZ; +//assign inta = 1'bZ; +assign serr = 1'bZ; +assign perr = 1'bZ; + + +wire cfg_hit = ((cbe == CFGREAD || cbe == CFGWRITE) && idsel && ad[1:0] == 2'b00); +wire addr_hit = ((cbe == MEMREAD || cbe == MEMWRITE) && memen && ad[31:24] == {baseaddr}); +wire hit = cfg_hit | addr_hit; + +// Wishbone SYSCON: output signals------------------------------------ +assign wb_reset_o = ~reset; +assign wb_clk_o = clk; +//reg wb_clk_o; + //always @(posedge clk) + //wb_clk_o = wb_clk_o+ 1; + + +// PCI parity generation:--------------------------------------------- +// during read, the parity on AD, and delayen by one clk. +reg par_en; +reg par_latched; +reg EN_RDd; +wire data_par = (data[31] ^ data[30] ^ data[29] ^ data[28]) ^ + (data[27] ^ data[26] ^ data[25] ^ data[24]) ^ + (data[23] ^ data[22] ^ data[21] ^ data[20]) ^ + (data[19] ^ data[18] ^ data[17] ^ data[16]) ^ + (data[15] ^ data[14] ^ data[13] ^ data[12]) ^ + (data[11] ^ data[10] ^ data[9] ^ data[8]) ^ + (data[7] ^ data[6] ^ data[5] ^ data[4]) ^ + (cbe[3] ^ cbe[2] ^ cbe[1] ^ cbe[0]) ^ + (data[3] ^ data[2] ^ data[1] ^ data[0]) ; + + always @(posedge clk) //delaying of parity + if ((enable == EN_RD)|(enable == EN_TR)) begin + par_latched = data_par; end + else + begin par_latched = 0; end + + always @(posedge clk) //delaying of EN_RD + EN_RDd = EN_RD; + + //assign par = (enable == EN_RD) ? 0 : 'bZ; + assign par = ((enable == EN_RD)|(enable == EN_RDd)) ? par_latched : 'bZ; //output control + + + +// Interrupt handling:-------------------------------------------------------------------- +reg int_dis; +wire int_stat; +reg [7:0] int_line; +assign inta = ((wb_irq == 1) && (int_dis == 0)) ? 1'b0 : 1'bZ; +assign int_stat = wb_irq; + + + +// WB bus arbitration:-------------------------------------------------------------------- +//assign wb_req = mastering; +reg arb_start; +reg arb_stop; +reg wb_req; + + parameter arb_state1 = 2'b00; + parameter arb_state2 = 2'b01; + reg arb_state = arb_state1; + always@(posedge clk) begin + if (wb_reset_o) begin + arb_state <= arb_state1; + wb_req <= 0; + end + else + case (arb_state) + arb_state1 : begin //arbitration is not needed: IDLE + wb_req <= 0; + if (arb_start == 1) + arb_state <= arb_state2; + end + arb_state2 : begin //arbitration is needed + wb_req <= 1; + if (arb_stop == 1) + arb_state <= arb_state1; + end + default : begin // Fault Recovery + arb_state <= arb_state1; + wb_req <= 0; + end + endcase + end + + + +// -------------- wishbone state machine -------------------------------------------------- +//write FIFO buffer: +reg [31:0] wb_wr_buf [5:0]; //64 Dwords wb write buffer: wb_wr_buf[index] <= value; +reg [3:0] wb_wr_sel_buf [5:0]; //select lines, write buffer: wb_wr_buf[index] <= value; +reg [31:0] fifo_start_wb_addr; +reg [31:0] fifo_act_wb_addr; +reg [5:0] fifo_max_count; +reg [5:0] fifo_wb_counter; +reg [5:0] fifo_wb_counter_o; +reg fifo_flush; //wb output mux control +reg fifo_flush_start; //start pulse +reg fifo_fill; //disable wb during filling fifo +reg [3:0] wbw_timeout_count_new; +reg [1:0] wbw_phase; +//read FIFO buffer: +reg [31:0] wb_rd_buf [5:0]; //64 Dwords wb read buffer: wb_rd_buf[index] <= value; +reg [3:0] wb_rd_sel_buf [5:0]; //select lines, write buffer: wb_wr_buf[index] <= value; +reg [31:0] fifo_start_wb_addr_rd; +reg [31:0] fifo_act_wb_addr_rd; +reg [5:0] fifo_max_count_rd; +reg [5:0] fifo_wb_counter_rd; +reg [5:0] fifo_wb_counter_o_rd; +reg fifo_flush_rd; //wb output mux control +reg fifo_fill_start_rd; //start pulse +reg fifo_fill_rd; //disable wb during filling fifo +reg [3:0] wbr_timeout_count_new; +reg [1:0] wbr_phase; +// +reg wb_cyc_o; +reg wb_stb_o; +reg wb_wr_o; +reg [31:0] wb_address; +reg [3:0] wb_sel_o; +reg [31:0] wb_dat_o; +reg machinereset; +reg mastering; +//assign wb_req = mastering; + + + parameter machine_waiting = 2'b00; + parameter machine_flushing = 2'b01; + parameter machine_read_filling = 2'b11; + reg [1:0] wbwf_state = machine_waiting; + + always@(posedge wb_clk_o) + if (wb_reset_o) begin + wbwf_state <= machine_waiting; + wbw_phase <= 0; + wbw_timeout_count_new <= 0; + fifo_wb_counter_o<=0; + fifo_flush <= 0; + wb_cyc_o <= 0; + wb_stb_o <= 0; + wb_wr_o <= 0; + wbr_phase <= 0; + wbr_timeout_count_new <= 0; + fifo_wb_counter_o_rd<=0; + fifo_fill_rd <= 0; + wb_address[31:0] = 32'b0; + wb_sel_o = 4'b0; + wb_dat_o = 32'b0; + pci_read_reg <= 0; + mastering <= 0; + arb_stop <= 0; + failed_addr_reg <= 0; + end + else + case (wbwf_state) + + machine_waiting : begin //no operation on Wishbone bus ************** + wbw_phase <= 0; + wbw_timeout_count_new <= 0; + wbr_phase <= 0; + wbr_timeout_count_new <= 0; + wb_address[31:0] = 32'b0; + wb_cyc_o <= 0; + wb_stb_o <= 0; + wb_wr_o <= 0; + wb_sel_o = 4'b0; + wb_dat_o = 32'b0; + arb_stop <= 0; + if (fifo_flush_start == 1) + begin fifo_flush <= 1; wbwf_state <= machine_flushing; fifo_wb_counter_o<=0; mastering <= 1; end + else if (fifo_fill_start_rd == 1) + begin fifo_fill_rd <= 1; wbwf_state <= machine_read_filling; fifo_wb_counter_o_rd<=0; mastering <= 1; end + end + + machine_flushing : begin //wr-FIFO flushing: wb write*********************** + wb_sel_o = pci_write_sel_reg; + wb_dat_o = pci_write_reg; //wb_wr_buf[fifo_wb_counter_o]; + wb_address[31:0] = fifo_start_wb_addr; //[31:0]+fifo_wb_counter_o ; + if ( wbw_phase== 0 ) begin //phase 0: setup + wb_cyc_o <= 0; + wb_stb_o <= 0; + wb_wr_o <= 0; + wbw_phase <= wbw_phase + 1; + //address and data also changes now, from FIFO + end + else if ( wbw_phase== 1 ) begin //phase 1: access + wb_cyc_o <= 1; + wb_stb_o <= 1; + wb_wr_o <= 1; + wbw_phase <= wbw_phase + 1; + end + else if ( wbw_phase== 2 ) begin //phase 2: wait for ack + wbw_timeout_count_new <= wbw_timeout_count_new +1; + if ((wb_ack_i==1) | (wbw_timeout_count_new==15)) begin + wbw_phase <= wbw_phase + 1; + wb_cyc_o <= 0; + wb_stb_o <= 0; + wb_wr_o <= 0; + if (wbw_timeout_count_new==15) begin failed_addr_reg <= wb_address; end + end + else begin wb_cyc_o <= 1; wb_stb_o <= 1; wb_wr_o <= 1; end + end + else if ( wbw_phase== 3 ) begin //phase 3: hold (finish) + wb_cyc_o <= 0; + wb_stb_o <= 0; + wb_wr_o <= 0; + wbw_phase <= wbw_phase + 1; + wbw_timeout_count_new <=0; + fifo_wb_counter_o <= fifo_wb_counter_o + 1; //for next word + //if ((fifo_wb_counter_o == fifo_max_count-1)|(machinereset == 1)) begin + fifo_flush <= 0; + wbwf_state <= machine_waiting; + fifo_wb_counter_o<=0; + mastering <= 0; + arb_stop <= 1; + //end + end + end + + machine_read_filling : begin //rd-FIFO filling: wb read******************** + wb_sel_o = pci_read_sel_reg; + wb_dat_o = 32'b0; + wb_address[31:0] = fifo_start_wb_addr_rd; //[31:0]+fifo_wb_counter_o_rd ; + if ( wbr_phase== 0 ) begin //phase 0: setup + wb_cyc_o <= 0; + wb_stb_o <= 0; + wb_wr_o <= 0; + wbr_phase <= wbr_phase + 1; + //address and data also changes now, from FIFO + end + else if ( wbr_phase== 1 ) begin //phase 1: access + wb_cyc_o <= 1; + wb_stb_o <= 1; + wb_wr_o <= 0; + wbr_phase <= wbr_phase + 1; + end + else if ( wbr_phase== 2 ) begin //phase 2: wait for ack + wbr_timeout_count_new <= wbr_timeout_count_new +1; + if ((wb_ack_i==1) | (wbr_timeout_count_new==15)) begin + //wb_rd_buf[fifo_wb_counter_o_rd] <= wb_dat_i; //sampling + pci_read_reg <= wb_dat_i; //sampling + wbr_phase <= wbr_phase + 1; + wb_cyc_o <= 0; + wb_stb_o <= 0; + wb_wr_o <= 0; + if (wbw_timeout_count_new==15) begin failed_addr_reg <= wb_address; end + end + else begin wb_cyc_o <= 1; wb_stb_o <= 1; wb_wr_o <= 0; end + end + else if ( wbr_phase== 3 ) begin //phase 3: hold (finish) + wb_cyc_o <= 0; + wb_stb_o <= 0; + wb_wr_o <= 0; + wbr_phase <= wbw_phase + 1; + wbr_timeout_count_new <=0; + fifo_wb_counter_o_rd <= fifo_wb_counter_o_rd + 1; //for next word + //if ((fifo_wb_counter_o_rd == fifo_max_count_rd-1)|(machinereset == 1)) begin + fifo_fill_rd <= 0; + wbwf_state <= machine_waiting; + fifo_wb_counter_o_rd<=0; + mastering <= 0; + arb_stop <= 1; + //end + end + end + + default : begin // Fault Recovery + wbwf_state <= machine_waiting; + end + + + endcase + + + + + + + +// main PCI state machine: --------------------------------------------------------------- +always @(posedge clk) +begin + if (~reset) begin + state <= ST_IDLE; + enable <= EN_NONE; + baseaddr <= 0; + devsel <= 'bZ; + memen <= 0; + int_line <= 8'b0; + int_dis <= 0; + wb_baseaddr_reg <= 0; + wb_address_1[31:0] <= 0; + user_status_reg <= 0; + user_command_reg <= 0; + fifo_flush_start <= 0; + fifo_fill_start_rd <= 0; + fifo_wb_counter <= 0; + fifo_wb_counter_rd <= 0; + dummy_reg <= 0; + pci_write_reg <= 0; + machinereset <= 0; + led <= 0; + arb_start <= 0; + + end + else begin + + case (state) + ST_IDLE: begin + enable <= EN_NONE; + devsel <= 'bZ; + fifo_flush_start <= 0; + fifo_fill_start_rd <= 0; + fifo_wb_counter <= 0; + fifo_wb_counter_rd <= 0; + machinereset <= 0; + if (~frame) begin + address <= ad[7:2]; + if (hit) begin + state <= {1'b1, cbe[3], cbe[0]}; + if (addr_hit) begin arb_start <= 1; end + devsel <= 0; + wb_address_1[31:0] <= {wb_baseaddr_reg, ad[23:2]}; + //if (wbwf_state == machine_waiting) begin //sample address, if FIFO is not busy + fifo_start_wb_addr <= {wb_baseaddr_reg, ad[23:2]}; + fifo_start_wb_addr_rd <= {wb_baseaddr_reg, ad[23:2]}; + //end + // pipeline the write enable + if (cbe[0]) + enable <= EN_WR; + end + else begin + state <= ST_BUSY; + enable <= EN_NONE; + end + end + end + + ST_BUSY: begin + devsel <= 'bZ; + enable <= EN_NONE; + arb_start <= 0; + if (frame) + state <= ST_IDLE; + end + + ST_CFGREAD: begin + enable <= EN_RD; + if (~irdy || trdy) begin + case (address) + 0: data <= { DEVICE_ID, VENDOR_ID }; + 1: data <= { 5'b0, DEVSEL_TIMING, 5'b0, int_stat, 8'b0, int_dis, 8'b0, memen, 1'b0}; + 2: data <= { DEVICE_CLASS, DEVICE_REV }; + 4: data <= { baseaddr, 12'b0, 8'b0, 4'b0000 }; // baseaddr + request mem < 1Mbyte + 11: data <= {SUBSYSTEM_ID, SUBSYSTEM_VENDOR_ID }; + 15: data <= {16'b0, 7'b0, 1'b1, int_line}; //irq pin and line + 16: data <= { 24'b0, baseaddr }; + 20: data <= { wb_baseaddr_reg, 22'b0}; //wb base address: for wb-local relocation + 21: data <= user_status_reg; + 22: data <= user_command_reg; + 23: data <= failed_addr_reg; //actual addr, at a timeout + default: data <= 'h00000000; + endcase + address <= address + 1; + arb_start <= 0; + end + if (frame && ~irdy && ~trdy) begin + devsel <= 1; + state <= ST_IDLE; + enable <= EN_TR; + end + end + + ST_CFGWRITE: begin + enable <= EN_WR; + if (~irdy) begin + case (address) + 4: baseaddr <= ad[31:24]; // XXX examine cbe + 1: begin memen <= ad[1]; int_dis <= ad[10]; end + 15: int_line <= ad[7:0]; + 20: wb_baseaddr_reg <= ad[31:22]; + 22: user_command_reg <= ad[31:0]; + 24: machinereset <= 1; //resetting the wb state machine (60h) + default: ; + endcase + address <= address + 1; + arb_start <= 0; + if (frame) begin + devsel <= 1; + state <= ST_IDLE; + enable <= EN_TR; + end + end + end + + ST_MEMREAD: begin + enable <= EN_RD; + arb_start <= 0; + if (~irdy || trdy) begin + address <= address + 1; + data <= pci_read_reg; + pci_read_sel_reg <= ~cbe; + end + if (frame && ~irdy && ~trdy) begin + devsel <= 1; + state <= ST_IDLE; + enable <= EN_TR; + fifo_fill_rd<=0; + //if (wbwf_state == machine_waiting) begin + fifo_fill_start_rd <= 1; + //end + end + end + + ST_MEMWRITE: begin + enable <= EN_WR; + arb_start <= 0; + if (~irdy) begin + led <= ad[3:0]; + pci_write_reg <= ad[31:0]; + pci_write_sel_reg <= ~cbe; + address <= address + 1; + if (frame) begin + devsel <= 1; + state <= ST_IDLE; + enable <= EN_TR; + fifo_fill<=0; + //if (wbwf_state == machine_waiting) begin + fifo_flush_start <= 1; + //end + end + end + + end + + endcase + end +end +endmodule diff --git a/designs/encrypted_ip/pic/pic.vhd b/designs/encrypted_ip/pic/pic.vhd new file mode 100644 index 000000000..3e217d202 --- /dev/null +++ b/designs/encrypted_ip/pic/pic.vhd @@ -0,0 +1,250 @@ +---------------------------------------------------------------------------- +---- Create Date: 00:12:45 10/23/2010 +---- Design Name: pic +---- Project Name: pic +---- Description: +---- A Programmable Interrupt Controller which can handle upto 8 ---- +---- level triggered interrupts.The operating modes available are ---- +---- polling fixed priority modes. ---- ---- +---------------------------------------------------------------------------- +---- ---- +---- This file is a part of the pic project at ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Author(s): ---- +---- Vipin Lal, lalnitt@gmail.com ---- +---- ---- +---------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2010 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity pic is +port( CLK_I : in std_logic; --Clock. + RST_I : in std_logic; --Reset + IR : in unsigned(7 downto 0); --Interrupt requests from peripherals. + DataBus : inout unsigned(7 downto 0); --Data bus between processor pic. + INTR_O : out std_logic; --Interrupt Request pin of processor. + INTA_I : in std_logic --Interrupt ack. + ); +end pic; + +architecture Behavioral of pic is + +type state_type is (reset_s,get_commands,jump_int_method,start_polling,tx_int_info_polling,ack_ISR_done, + ack_txinfo_rxd,start_priority_check,tx_int_info_priority,ack_txinfo_rxd_priority,ack_ISR_done_pt); +signal next_s : state_type :=reset_s; +signal int_type : unsigned(1 downto 0):="01"; +signal int_index,count_cmd : integer := 0; +type prior_table is array (0 to 7) of unsigned(2 downto 0); +signal pt : prior_table := (others => (others => '0')); +signal int_pt : unsigned(2 downto 0):="000"; +signal flag,flag1 : std_logic := '0'; --These flags are used for timing purposes. + +begin + +process(CLK_I,RST_I) +begin +if( RST_I = '1') then + next_s <= reset_s; +elsif( rising_edge(CLK_I) ) then + flag <= INTA_I; + case next_s is + when reset_s => + --initialze signals to zero. + flag <= '0'; + flag1 <= '0'; + int_type <= "00"; + int_index <= 0; + count_cmd <= 0; + int_pt <= "000"; + pt <= (others => (others => '0')); + if( RST_I = '0' ) then + next_s <= get_commands; + else + next_s <= reset_s; + end if; + DataBus <= (others => 'Z'); + when get_commands => --Get commands and operating mode from the processor. + if( DataBus(1 downto 0) = "01" ) then + int_type <= "01"; + next_s <= jump_int_method; + elsif( DataBus(1 downto 0) = "10" and count_cmd = 0) then + pt(0) <= DataBus(7 downto 5); + pt(1) <= DataBus(4 downto 2); + count_cmd <= count_cmd + 1; + next_s <= get_commands; + elsif( DataBus(1 downto 0) = "10" and count_cmd = 1) then + pt(2) <= DataBus(7 downto 5); + pt(3) <= DataBus(4 downto 2); + count_cmd <= count_cmd + 1; + next_s <= get_commands; + elsif( DataBus(1 downto 0) = "10" and count_cmd = 2) then + pt(4) <= DataBus(7 downto 5); + pt(5) <= DataBus(4 downto 2); + count_cmd <= count_cmd + 1; + next_s <= get_commands; + elsif( DataBus(1 downto 0) = "10" and count_cmd = 3) then + pt(6) <= DataBus(7 downto 5); + pt(7) <= DataBus(4 downto 2); + count_cmd <= 0; + int_type <= "10"; + next_s <= jump_int_method; + else + next_s <= get_commands; + end if; + when jump_int_method => --Check which method is used to determine the interrupts. + flag <= '0'; + flag1 <= '0'; + int_index <= 0; + count_cmd <= 0; + int_pt <= "000"; + if( int_type = "01" ) then + next_s <= start_polling; --Polling method for checking the interrupts. + elsif( int_type = "10" ) then + next_s <= start_priority_check; --Fixed priority scheme. + else + next_s <= reset_s; --Error if no method is specified. + end if; + DataBus <= (others => 'Z'); + when start_polling => --Check for interrupts(one by one) using polling method. + if( IR(int_index) = '1' ) then + INTR_O <= '1'; + next_s <= tx_int_info_polling; + else + INTR_O <= '0'; + end if; + if( int_index = 7 ) then + int_index <= 0; + else + int_index <= int_index+1; + end if; + DataBus <= (others => 'Z'); + when tx_int_info_polling => --Transmit interrupt information if an interrupt is found. + if( INTA_I = '0' ) then + INTR_O <= '0'; + end if; + if( flag = '0' ) then + DataBus <= "01011" & to_unsigned( (int_index-1),3); --MSB "01011" is for matching purpose. + flag1 <= '1'; + else + flag1 <= '0'; + end if; + if ( flag1 = '1' ) then + next_s <= ack_txinfo_rxd; + if( INTA_I = '0' ) then + DataBus <= (others => 'Z'); + end if; + end if; + when ack_txinfo_rxd => --ACK send by processor to tell pic that interrupt info is received correctly. + if( INTA_I <= '0' ) then + next_s <= ack_ISR_done; + DataBus <= (others => 'Z'); + end if; + when ack_ISR_done => --Wait for the ISR for the particular interrupt to get over. + if( INTA_I = '0' and DataBus(7 downto 3) = "10100" and DataBus(2 downto 0) = to_unsigned(int_index-1,3) ) then + next_s <= start_polling; + else + next_s <= ack_ISR_done; + end if; + when start_priority_check => --Fixed priority method for interrupt handling. + --Interrupts are checked based on their priority. + if( IR(to_integer(pt(0))) = '1' ) then + int_pt <= pt(0); + INTR_O <= '1'; + next_s <= tx_int_info_priority; + elsif( IR(to_integer(pt(1))) = '1' ) then + int_pt <= pt(1); + INTR_O <= '1'; + next_s <= tx_int_info_priority; + elsif( IR(to_integer(pt(2))) = '1' ) then + int_pt <= pt(2); + INTR_O <= '1'; + next_s <= tx_int_info_priority; + elsif( IR(to_integer(pt(3))) = '1' ) then + int_pt <= pt(3); + INTR_O <= '1'; + next_s <= tx_int_info_priority; + elsif( IR(to_integer(pt(4))) = '1' ) then + int_pt <= pt(4); + INTR_O <= '1'; + next_s <= tx_int_info_priority; + elsif( IR(to_integer(pt(5))) = '1' ) then + int_pt <= pt(5); + INTR_O <= '1'; + next_s <= tx_int_info_priority; + elsif( IR(to_integer(pt(6))) = '1' ) then + int_pt <= pt(6); + INTR_O <= '1'; + next_s <= tx_int_info_priority; + elsif( IR(to_integer(pt(7))) = '1' ) then + int_pt <= pt(7); + INTR_O <= '1'; + next_s <= tx_int_info_priority; + else + next_s <= start_priority_check; + end if; + DataBus <= (others => 'Z'); + when tx_int_info_priority => --Transmit interrupt information if an interrupt is found. + if( INTA_I = '0' ) then + INTR_O <= '0'; + end if; + if( flag = '0' ) then + DataBus <= "10011" & int_pt; --MSB "10011" is for matching purpose. + flag1 <= '1'; + else + flag1 <= '0'; + end if; + if ( flag1 = '1' ) then + next_s <= ack_txinfo_rxd_priority; + if( INTA_I = '0' ) then + DataBus <= (others => 'Z'); + end if; + end if; + when ack_txinfo_rxd_priority => --ACK send by processor to tell pic that interrupt info is received correctly. + if( INTA_I <= '0' ) then + next_s <= ack_ISR_done_pt; + DataBus <= (others => 'Z'); + end if; + when ack_ISR_done_pt => --Wait for the ISR for the particular interrupt to get over. + if( INTA_I = '0' and DataBus(7 downto 3) = "01100" and DataBus(2 downto 0) = int_pt ) then + next_s <= start_priority_check; + elsif( DataBus(7 downto 3) /= "01100" or DataBus(2 downto 0) /= int_pt ) then + next_s <= reset_s; --Error. + else + next_s <= ack_ISR_done_pt; + end if; + when others => + DataBus <= (others => 'Z'); + end case; +end if; +end process; + +end Behavioral; + diff --git a/designs/encrypted_ip/pic/potato.vhd b/designs/encrypted_ip/pic/potato.vhd new file mode 100644 index 000000000..fc662beee --- /dev/null +++ b/designs/encrypted_ip/pic/potato.vhd @@ -0,0 +1,150 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; + +use work.pp_types.all; + +--! @brief The Potato Processor. +--! This file provides a Wishbone-compatible interface to the Potato processor. +entity potato is + generic( + PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID. + RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000200" --! Address of the first instruction to execute. + ); + port( + clk : in std_logic; + timer_clk : in std_logic; + reset : in std_logic; + + -- Interrupts: + irq : in std_logic_vector(7 downto 0); + + -- Host/Target interface: + fromhost_data : in std_logic_vector(31 downto 0); + fromhost_updated : in std_logic; + tohost_data : out std_logic_vector(31 downto 0); + tohost_updated : out std_logic; + + -- Wishbone interface: + wb_adr_out : out std_logic_vector(31 downto 0); + wb_sel_out : out std_logic_vector( 3 downto 0); + wb_cyc_out : out std_logic; + wb_stb_out : out std_logic; + wb_we_out : out std_logic; + wb_dat_out : out std_logic_vector(31 downto 0); + wb_dat_in : in std_logic_vector(31 downto 0); + wb_ack_in : in std_logic + ); +end entity potato; + +architecture behaviour of potato is + + -- Instruction memory signals: + signal imem_address : std_logic_vector(31 downto 0); + signal imem_data : std_logic_vector(31 downto 0); + signal imem_req, imem_ack : std_logic; + + -- Data memory signals: + signal dmem_address : std_logic_vector(31 downto 0); + signal dmem_data_in : std_logic_vector(31 downto 0); + signal dmem_data_out : std_logic_vector(31 downto 0); + signal dmem_data_size : std_logic_vector( 1 downto 0); + signal dmem_read_req : std_logic; + signal dmem_read_ack : std_logic; + signal dmem_write_req : std_logic; + signal dmem_write_ack : std_logic; + + -- Wishbone signals: + signal icache_inputs, dmem_if_inputs : wishbone_master_inputs; + signal icache_outputs, dmem_if_outputs : wishbone_master_outputs; + +begin + processor: entity work.pp_core + generic map( + PROCESSOR_ID => PROCESSOR_ID, + RESET_ADDRESS => RESET_ADDRESS + ) port map( + clk => clk, + reset => reset, + timer_clk => timer_clk, + imem_address => imem_address, + imem_data_in => imem_data, + imem_req => imem_req, + imem_ack => imem_ack, + dmem_address => dmem_address, + dmem_data_in => dmem_data_in, + dmem_data_out => dmem_data_out, + dmem_data_size => dmem_data_size, + dmem_read_req => dmem_read_req, + dmem_read_ack => dmem_read_ack, + dmem_write_req => dmem_write_req, + dmem_write_ack => dmem_write_ack, + fromhost_data => fromhost_data, + fromhost_write_en => fromhost_updated, + tohost_data => tohost_data, + tohost_write_en => tohost_updated, + irq => irq + ); + + icache: entity work.pp_icache + generic map( + LINE_SIZE => 4, + NUM_LINES => 128 + ) port map( + clk => clk, + reset => reset, + cache_enable => '1', + cache_flush => '0', + cached_areas => (others => '1'), + mem_address_in => imem_address, + mem_data_out => imem_data, + mem_data_in => (others => '0'), + mem_data_size => b"00", + mem_read_req => imem_req, + mem_read_ack => imem_ack, + mem_write_req => '0', + mem_write_ack => open, + wb_inputs => icache_inputs, + wb_outputs => icache_outputs + ); + + dmem_if: entity work.pp_wb_adapter + port map( + clk => clk, + reset => reset, + dmem_address => dmem_address, + dmem_data_in => dmem_data_out, + dmem_data_out => dmem_data_in, + dmem_data_size => dmem_data_size, + dmem_read_req => dmem_read_req, + dmem_read_ack => dmem_read_ack, + dmem_write_req => dmem_write_req, + dmem_write_ack => dmem_write_ack, + wb_inputs => dmem_if_inputs, + wb_outputs => dmem_if_outputs + ); + + arbiter: entity work.pp_wb_arbiter + port map( + clk => clk, + reset => reset, + --m1_inputs => dmem_if_inputs, + --m1_outputs => dmem_if_outputs, + m1_inputs => icache_inputs, + m1_outputs => icache_outputs, + m2_inputs => dmem_if_inputs, + m2_outputs => dmem_if_outputs, + wb_adr_out => wb_adr_out, + wb_sel_out => wb_sel_out, + wb_cyc_out => wb_cyc_out, + wb_stb_out => wb_stb_out, + wb_we_out => wb_we_out, + wb_dat_out => wb_dat_out, + wb_dat_in => wb_dat_in, + wb_ack_in => wb_ack_in + ); + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_alu.vhd b/designs/encrypted_ip/pic/pp_alu.vhd new file mode 100644 index 000000000..a28aafd1b --- /dev/null +++ b/designs/encrypted_ip/pic/pp_alu.vhd @@ -0,0 +1,58 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_types.all; + +entity pp_alu is + port( + x, y : in std_logic_vector(31 downto 0); + result : out std_logic_vector(31 downto 0); + operation : in alu_operation + ); +end entity pp_alu; + +architecture behaviour of pp_alu is +begin + + calculate: process(operation, x, y) + begin + case operation is + when ALU_AND => + result <= x and y; + when ALU_OR => + result <= x or y; + when ALU_XOR => + result <= x xor y; + when ALU_SLT => + if signed(x) < signed(y) then + result <= (0 => '1', others => '0'); + else + result <= (others => '0'); + end if; + when ALU_SLTU => + if unsigned(x) < unsigned(y) then + result <= (0 => '1', others => '0'); + else + result <= (others => '0'); + end if; + when ALU_ADD => + result <= std_logic_vector(unsigned(x) + unsigned(y)); + when ALU_SUB => + result <= std_logic_vector(unsigned(x) - unsigned(y)); + when ALU_SRL => + result <= std_logic_vector(shift_right(unsigned(x), to_integer(unsigned(y(4 downto 0))))); + when ALU_SLL => + result <= std_logic_vector(shift_left(unsigned(x), to_integer(unsigned(y(4 downto 0))))); + when ALU_SRA => + result <= std_logic_vector(shift_right(signed(x), to_integer(unsigned(y(4 downto 0))))); + when others => + result <= (others => '0'); + end case; + end process calculate; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_alu_control_unit.vhd b/designs/encrypted_ip/pic/pp_alu_control_unit.vhd new file mode 100644 index 000000000..f995c5b4f --- /dev/null +++ b/designs/encrypted_ip/pic/pp_alu_control_unit.vhd @@ -0,0 +1,141 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; + +use work.pp_types.all; +use work.pp_constants.all; + +entity pp_alu_control_unit is + port( + opcode : in std_logic_vector( 4 downto 0); + funct3 : in std_logic_vector( 2 downto 0); + funct7 : in std_logic_vector( 6 downto 0); + + -- Sources of ALU operands: + alu_x_src, alu_y_src : out alu_operand_source; + + -- ALU operation: + alu_op : out alu_operation + ); +end entity pp_alu_control_unit; + +architecture behaviour of pp_alu_control_unit is +begin + + decode_alu: process(opcode, funct3, funct7) + begin + case opcode is + when b"01101" => -- Load upper immediate + alu_x_src <= ALU_SRC_NULL; + alu_y_src <= ALU_SRC_IMM; + alu_op <= ALU_ADD; + when b"00101" => -- Add upper immediate to PC + alu_x_src <= ALU_SRC_PC; + alu_y_src <= ALU_SRC_IMM; + alu_op <= ALU_ADD; + when b"11011" => -- Jump and link + alu_x_src <= ALU_SRC_PC_NEXT; + alu_y_src <= ALU_SRC_NULL; + alu_op <= ALU_ADD; + when b"11001" => -- Jump and link register + alu_x_src <= ALU_SRC_PC_NEXT; + alu_y_src <= ALU_SRC_NULL; + alu_op <= ALU_ADD; + when b"11000" => -- Branch operations + -- The funct3 field decides which type of branch comparison is + -- done; this is decoded in the branch comparator module. + alu_x_src <= ALU_SRC_NULL; + alu_y_src <= ALU_SRC_NULL; + alu_op <= ALU_NOP; + when b"00000" => -- Load instruction + alu_x_src <= ALU_SRC_REG; + alu_y_src <= ALU_SRC_IMM; + alu_op <= ALU_ADD; + when b"01000" => -- Store instruction + alu_x_src <= ALU_SRC_REG; + alu_y_src <= ALU_SRC_IMM; + alu_op <= ALU_ADD; + when b"00100" => -- Register-immediate operations + alu_x_src <= ALU_SRC_REG; + + if funct3 = b"001" or funct3 = b"101" then + alu_y_src <= ALU_SRC_SHAMT; + else + alu_y_src <= ALU_SRC_IMM; + end if; + + case funct3 is + when b"000" => + alu_op <= ALU_ADD; + when b"001" => + alu_op <= ALU_SLL; + when b"010" => + alu_op <= ALU_SLT; + when b"011" => + alu_op <= ALU_SLTU; + when b"100" => + alu_op <= ALU_XOR; + when b"101" => + if funct7 = b"0000000" then + alu_op <= ALU_SRL; + else + alu_op <= ALU_SRA; + end if; + when b"110" => + alu_op <= ALU_OR; + when b"111" => + alu_op <= ALU_AND; + when others => + alu_op <= ALU_INVALID; + end case; + when b"01100" => -- Register-register operations + alu_x_src <= ALU_SRC_REG; + alu_y_src <= ALU_SRC_REG; + + case funct3 is + when b"000" => + if funct7 = b"0000000" then + alu_op <= ALU_ADD; + else + alu_op <= ALU_SUB; + end if; + when b"001" => + alu_op <= ALU_SLL; + when b"010" => + alu_op <= ALU_SLT; + when b"011" => + alu_op <= ALU_SLTU; + when b"100" => + alu_op <= ALU_XOR; + when b"101" => + if funct7 = b"0000000" then + alu_op <= ALU_SRL; + else + alu_op <= ALU_SRA; + end if; + when b"110" => + alu_op <= ALU_OR; + when b"111" => + alu_op <= ALU_AND; + when others => + alu_op <= ALU_INVALID; + end case; + when b"00011" => -- Fence instructions, ignored + alu_x_src <= ALU_SRC_REG; + alu_y_src <= ALU_SRC_REG; + alu_op <= ALU_NOP; + when b"11100" => -- System instructions + alu_x_src <= ALU_SRC_CSR; + alu_y_src <= ALU_SRC_NULL; + alu_op <= ALU_ADD; + when others => + alu_x_src <= ALU_SRC_REG; + alu_y_src <= ALU_SRC_REG; + alu_op <= ALU_INVALID; + end case; + end process decode_alu; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_alu_mux.vhd b/designs/encrypted_ip/pic/pp_alu_mux.vhd new file mode 100644 index 000000000..fcc20c1dd --- /dev/null +++ b/designs/encrypted_ip/pic/pp_alu_mux.vhd @@ -0,0 +1,49 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_types.all; + +--! @brief Multiplexer used to choose between ALU inputs. +entity pp_alu_mux is + port( + source : in alu_operand_source; + + register_value : in std_logic_vector(31 downto 0); + immediate_value : in std_logic_vector(31 downto 0); + shamt_value : in std_logic_vector( 4 downto 0); + pc_value : in std_logic_vector(31 downto 0); + csr_value : in std_logic_vector(31 downto 0); + + output : out std_logic_vector(31 downto 0) + ); +end entity pp_alu_mux; + +architecture behaviour of pp_alu_mux is +begin + + mux: process(source, register_value, immediate_value, shamt_value, pc_value, csr_value) + begin + case source is + when ALU_SRC_REG => + output <= register_value; + when ALU_SRC_IMM => + output <= immediate_value; + when ALU_SRC_PC => + output <= pc_value; + when ALU_SRC_PC_NEXT => + output <= std_logic_vector(unsigned(pc_value) + 4); + when ALU_SRC_CSR => + output <= csr_value; + when ALU_SRC_SHAMT => + output <= (31 downto 5 => '0') & shamt_value; + when ALU_SRC_NULL => + output <= (others => '0'); + end case; + end process mux; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_comparator.vhd b/designs/encrypted_ip/pic/pp_comparator.vhd new file mode 100644 index 000000000..b3205fddd --- /dev/null +++ b/designs/encrypted_ip/pic/pp_comparator.vhd @@ -0,0 +1,43 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_utilities.all; + +--! @brief Component for comparing two registers in the ID stage whens branching. +entity pp_comparator is + port( + funct3 : in std_logic_vector(14 downto 12); + rs1, rs2 : in std_logic_vector(31 downto 0); + result : out std_logic --! Result of the comparison. + ); +end entity pp_comparator; + +architecture behaviour of pp_comparator is +begin + + compare: process(funct3, rs1, rs2) + begin + case funct3 is + when b"000" => -- EQ + result <= to_std_logic(rs1 = rs2); + when b"001" => -- NE + result <= to_std_logic(rs1 /= rs2); + when b"100" => -- LT + result <= to_std_logic(signed(rs1) < signed(rs2)); + when b"101" => -- GE + result <= to_std_logic(signed(rs1) >= signed(rs2)); + when b"110" => -- LTU + result <= to_std_logic(unsigned(rs1) < unsigned(rs2)); + when b"111" => -- GEU + result <= to_std_logic(unsigned(rs1) >= unsigned(rs2)); + when others => + result <= '0'; + end case; + end process compare; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_constants.vhd b/designs/encrypted_ip/pic/pp_constants.vhd new file mode 100644 index 000000000..74d33c423 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_constants.vhd @@ -0,0 +1,15 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; + +use work.pp_types.all; + +package pp_constants is + + --! No-operation instruction, addi x0, x0, 0. + constant RISCV_NOP : std_logic_vector(31 downto 0) := (31 downto 5 => '0') & b"10011"; --! ADDI x0, x0, 0. + +end package pp_constants; diff --git a/designs/encrypted_ip/pic/pp_control_unit.vhd b/designs/encrypted_ip/pic/pp_control_unit.vhd new file mode 100644 index 000000000..f3361c2e3 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_control_unit.vhd @@ -0,0 +1,220 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; + +use work.pp_constants.all; +use work.pp_csr.all; +use work.pp_types.all; +use work.pp_utilities.all; + +--! @brief Unit decoding instructions and setting control signals apropriately. +entity pp_control_unit is + port( + -- Inputs, indices correspond to instruction word indices: + opcode : in std_logic_vector( 4 downto 0); + funct3 : in std_logic_vector( 2 downto 0); + funct7 : in std_logic_vector( 6 downto 0); + funct12 : in std_logic_vectoR(11 downto 0); + + -- Control signals: + rd_write : out std_logic; + branch : out branch_type; + + -- Exception signals: + decode_exception : out std_logic; + decode_exception_cause : out csr_exception_cause; + + -- Control register signals: + csr_write : out csr_write_mode; + csr_imm : out std_logic; --! Indicating an immediate variant of the csrr* instructions. + + -- Sources of operands to the ALU: + alu_x_src, alu_y_src : out alu_operand_source; + + -- ALU operation: + alu_op : out alu_operation; + + -- Memory transaction parameters: + mem_op : out memory_operation_type; + mem_size : out memory_operation_size + ); +end entity pp_control_unit; + +architecture behaviour of pp_control_unit is + signal exception : std_logic; + signal exception_cause : csr_exception_cause; + signal alu_op_temp : alu_operation; +begin + + csr_imm <= funct3(2); + alu_op <= alu_op_temp; + + decode_exception <= exception or to_std_logic(alu_op_temp = ALU_INVALID); + decode_exception_cause <= exception_cause when alu_op_temp /= ALU_INVALID + else CSR_CAUSE_INVALID_INSTR; + + alu_control: entity work.pp_alu_control_unit + port map( + opcode => opcode, + funct3 => funct3, + funct7 => funct7, + alu_x_src => alu_x_src, + alu_y_src => alu_y_src, + alu_op => alu_op_temp + ); + + decode_ctrl: process(opcode, funct3, funct12) + begin + case opcode is + when b"01101" => -- Load upper immediate + rd_write <= '1'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_NONE; + when b"00101" => -- Add upper immediate to PC + rd_write <= '1'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_NONE; + when b"11011" => -- Jump and link + rd_write <= '1'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_JUMP; + when b"11001" => -- Jump and link register + rd_write <= '1'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_JUMP_INDIRECT; + when b"11000" => -- Branch operations + rd_write <= '0'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_CONDITIONAL; + when b"00000" => -- Load instructions + rd_write <= '1'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_NONE; + when b"01000" => -- Store instructions + rd_write <= '0'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_NONE; + when b"00100" => -- Register-immediate operations + rd_write <= '1'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_NONE; + when b"01100" => -- Register-register operations + rd_write <= '1'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_NONE; + when b"00011" => -- Fence instructions, ignored + rd_write <= '0'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_NONE; + when b"11100" => -- System instructions + if funct3 = b"000" then + rd_write <= '0'; + + if funct12 = x"000" then + exception <= '1'; + exception_cause <= CSR_CAUSE_ECALL; + branch <= BRANCH_NONE; + elsif funct12 = x"001" then + exception <= '1'; + exception_cause <= CSR_CAUSE_BREAKPOINT; + branch <= BRANCH_NONE; + elsif funct12 = CSR_EPC_ERET then + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_SRET; + else + exception <= '1'; + exception_cause <= CSR_CAUSE_INVALID_INSTR; + branch <= BRANCH_NONE; + end if; + else + rd_write <= '1'; + exception <= '0'; + exception_cause <= CSR_CAUSE_NONE; + branch <= BRANCH_NONE; + end if; + when others => + rd_write <= '0'; + exception <= '1'; + exception_cause <= CSR_CAUSE_INVALID_INSTR; + branch <= BRANCH_NONE; + end case; + end process decode_ctrl; + + decode_csr: process(opcode, funct3) + begin + if opcode = b"11100" then + case funct3 is + when b"001" | b"101" => -- csrrw/i + csr_write <= CSR_WRITE_REPLACE; + when b"010" | b"110" => -- csrrs/i + csr_write <= CSR_WRITE_SET; + when b"011" | b"111" => -- csrrc/i + csr_write <= CSR_WRITE_CLEAR; + when others => + csr_write <= CSR_WRITE_NONE; + end case; + else + csr_write <= CSR_WRITE_NONE; + end if; + end process decode_csr; + + decode_mem: process(opcode, funct3) + begin + case opcode is + when b"00000" => -- Load instructions + case funct3 is + when b"000" => -- lw + mem_size <= MEMOP_SIZE_BYTE; + mem_op <= MEMOP_TYPE_LOAD; + when b"001" => -- lh + mem_size <= MEMOP_SIZE_HALFWORD; + mem_op <= MEMOP_TYPE_LOAD; + when b"010" | b"110" => -- lw + mem_size <= MEMOP_SIZE_WORD; + mem_op <= MEMOP_TYPE_LOAD; + when b"100" => -- lbu + mem_size <= MEMOP_SIZE_BYTE; + mem_op <= MEMOP_TYPE_LOAD_UNSIGNED; + when b"101" => -- lhu + mem_size <= MEMOP_SIZE_HALFWORD; + mem_op <= MEMOP_TYPE_LOAD_UNSIGNED; + when others => -- FIXME: Treat others as lw. + mem_size <= MEMOP_SIZE_WORD; + mem_op <= MEMOP_TYPE_INVALID; + end case; + when b"01000" => -- Store instructions + case funct3 is + when b"000" => + mem_op <= MEMOP_TYPE_STORE; + mem_size <= MEMOP_SIZE_BYTE; + when b"001" => + mem_op <= MEMOP_TYPE_STORE; + mem_size <= MEMOP_SIZE_HALFWORD; + when b"010" => + mem_op <= MEMOP_TYPE_STORE; + mem_size <= MEMOP_SIZE_WORD; + when others => + mem_op <= MEMOP_TYPE_INVALID; + mem_size <= MEMOP_SIZE_WORD; + end case; + when others => + mem_op <= MEMOP_TYPE_NONE; + mem_size <= MEMOP_SIZE_WORD; + end case; + end process decode_mem; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_core.vhd b/designs/encrypted_ip/pic/pp_core.vhd new file mode 100644 index 000000000..5e4e0db34 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_core.vhd @@ -0,0 +1,454 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_types.all; +use work.pp_constants.all; +use work.pp_utilities.all; +use work.pp_csr.all; + +--! @brief The Potato Processor is a simple processor core for use in FPGAs. +entity pp_core is + generic( + PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID. + RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000200" --! Address of the first instruction to execute. + ); + port( + -- Control inputs: + clk : in std_logic; --! Processor clock + reset : in std_logic; --! Reset signal + + timer_clk : in std_logic; --! Clock used for the timer/counter + + -- Instruction memory interface: + imem_address : out std_logic_vector(31 downto 0); --! Address of the next instruction + imem_data_in : in std_logic_vector(31 downto 0); --! Instruction input + imem_req : out std_logic; + imem_ack : in std_logic; + + -- Data memory interface: + dmem_address : out std_logic_vector(31 downto 0); --! Data address + dmem_data_in : in std_logic_vector(31 downto 0); --! Input from the data memory + dmem_data_out : out std_logic_vector(31 downto 0); --! Ouptut to the data memory + dmem_data_size : out std_logic_vector( 1 downto 0); --! Size of the data, 1 = 8 bits, 2 = 16 bits, 0 = 32 bits. + dmem_read_req : out std_logic; --! Data memory read request + dmem_read_ack : in std_logic; --! Data memory read acknowledge + dmem_write_req : out std_logic; --! Data memory write request + dmem_write_ack : in std_logic; --! Data memory write acknowledge + + -- Tohost/fromhost interface: + fromhost_data : in std_logic_vector(31 downto 0); --! Data from the host/simulator. + fromhost_write_en : in std_logic; --! Write enable signal from the host/simulator. + tohost_data : out std_logic_vector(31 downto 0); --! Data to the host/simulator. + tohost_write_en : out std_logic; --! Write enable signal to the host/simulator. + + -- External interrupt input: + irq : in std_logic_vector(7 downto 0) --! IRQ inputs. + ); +end entity pp_core; + +architecture behaviour of pp_core is + + ------- Flush signals ------- + signal flush_if, flush_id, flush_ex : std_logic; + + ------- Stall signals ------- + signal stall_if, stall_id, stall_ex, stall_mem : std_logic; + + -- Signals used to determine if an instruction should be counted + -- by the instret counter: + signal if_count_instruction, id_count_instruction : std_logic; + signal ex_count_instruction, mem_count_instruction : std_logic; + signal wb_count_instruction : std_logic; + + -- CSR read port signals: + signal csr_read_data : std_logic_vector(31 downto 0); + signal csr_read_writeable : boolean; + signal csr_read_address, csr_read_address_p : csr_address; + + -- Status register outputs: + signal mtvec : std_logic_vector(31 downto 0); + signal mie : std_logic_vector(31 downto 0); + signal ie, ie1 : std_logic; + + -- Internal interrupt signals: + signal software_interrupt, timer_interrupt : std_logic; + + -- Load hazard detected in the execute stage: + signal load_hazard_detected : std_logic; + + -- Branch targets: + signal exception_target, branch_target : std_logic_vector(31 downto 0); + signal branch_taken, exception_taken : std_logic; + + -- Register file read ports: + signal rs1_address_p, rs2_address_p : register_address; + signal rs1_address, rs2_address : register_address; + signal rs1_data, rs2_data : std_logic_vector(31 downto 0); + + -- Data memory signals: + signal dmem_address_p : std_logic_vector(31 downto 0); + signal dmem_data_size_p : std_logic_vector(1 downto 0); + signal dmem_data_out_p : std_logic_vector(31 downto 0); + signal dmem_read_req_p : std_logic; + signal dmem_write_req_p : std_logic; + + -- Fetch stage signals: + signal if_instruction, if_pc : std_logic_vector(31 downto 0); + signal if_instruction_ready : std_logic; + + -- Decode stage signals: + signal id_funct3 : std_logic_vector(2 downto 0); + signal id_rd_address : register_address; + signal id_rd_write : std_logic; + signal id_rs1_address : register_address; + signal id_rs2_address : register_address; + signal id_csr_address : csr_address; + signal id_csr_write : csr_write_mode; + signal id_csr_use_immediate : std_logic; + signal id_shamt : std_logic_vector(4 downto 0); + signal id_immediate : std_logic_vector(31 downto 0); + signal id_branch : branch_type; + signal id_alu_x_src, id_alu_y_src : alu_operand_source; + signal id_alu_op : alu_operation; + signal id_mem_op : memory_operation_type; + signal id_mem_size : memory_operation_size; + signal id_pc : std_logic_vector(31 downto 0); + signal id_exception : std_logic; + signal id_exception_cause : csr_exception_cause; + + -- Execute stage signals: + signal ex_dmem_address : std_logic_vector(31 downto 0); + signal ex_dmem_data_size : std_logic_vector(1 downto 0); + signal ex_dmem_data_out : std_logic_vector(31 downto 0); + signal ex_dmem_read_req : std_logic; + signal ex_dmem_write_req : std_logic; + signal ex_rd_address : register_address; + signal ex_rd_data : std_logic_vector(31 downto 0); + signal ex_rd_write : std_logic; + signal ex_pc : std_logic_vector(31 downto 0); + signal ex_csr_address : csr_address; + signal ex_csr_write : csr_write_mode; + signal ex_csr_data : std_logic_vector(31 downto 0); + signal ex_branch : branch_type; + signal ex_mem_op : memory_operation_type; + signal ex_mem_size : memory_operation_size; + signal ex_exception_context : csr_exception_context; + + -- Memory stage signals: + signal mem_rd_write : std_logic; + signal mem_rd_address : register_address; + signal mem_rd_data : std_logic_vector(31 downto 0); + signal mem_csr_address : csr_address; + signal mem_csr_write : csr_write_mode; + signal mem_csr_data : std_logic_vector(31 downto 0); + signal mem_mem_op : memory_operation_type; + + signal mem_exception : std_logic; + signal mem_exception_context : csr_exception_context; + + -- Writeback signals: + signal wb_rd_address : register_address; + signal wb_rd_data : std_logic_vector(31 downto 0); + signal wb_rd_write : std_logic; + signal wb_csr_address : csr_address; + signal wb_csr_write : csr_write_mode; + signal wb_csr_data : std_logic_vector(31 downto 0); + + signal wb_exception : std_logic; + signal wb_exception_context : csr_exception_context; + +begin + + stall_if <= stall_id; + stall_id <= stall_ex; + stall_ex <= load_hazard_detected or stall_mem; + stall_mem <= to_std_logic(memop_is_load(mem_mem_op) and dmem_read_ack = '0') + or to_std_logic(mem_mem_op = MEMOP_TYPE_STORE and dmem_write_ack = '0'); + + flush_if <= (branch_taken or exception_taken) and not stall_if; + flush_id <= (branch_taken or exception_taken) and not stall_id; + flush_ex <= (branch_taken or exception_taken) and not stall_ex; + + ------- Control and status module ------- + csr_unit: entity work.pp_csr_unit + generic map( + PROCESSOR_ID => PROCESSOR_ID + ) port map( + clk => clk, + reset => reset, + timer_clk => timer_clk, + irq => irq, + count_instruction => wb_count_instruction, + fromhost_data => fromhost_data, + fromhost_updated => fromhost_write_en, + tohost_data => tohost_data, + tohost_updated => tohost_write_en, + read_address => csr_read_address, + read_data_out => csr_read_data, + read_writeable => csr_read_writeable, + write_address => wb_csr_address, + write_data_in => wb_csr_data, + write_mode => wb_csr_write, + exception_context => wb_exception_context, + exception_context_write => wb_exception, + mie_out => mie, + mtvec_out => mtvec, + ie_out => ie, + ie1_out => ie1, + software_interrupt_out => software_interrupt, + timer_interrupt_out => timer_interrupt + ); + + csr_read_address <= id_csr_address when stall_ex = '0' else csr_read_address_p; + store_previous_csr_addr: process(clk, stall_ex) + begin + if rising_edge(clk) and stall_ex = '0' then + csr_read_address_p <= id_csr_address; + end if; + end process store_previous_csr_addr; + + ------- Register file ------- + regfile: entity work.pp_register_file + port map( + clk => clk, + rs1_addr => rs1_address, + rs2_addr => rs2_address, + rs1_data => rs1_data, + rs2_data => rs2_data, + rd_addr => wb_rd_address, + rd_data => wb_rd_data, + rd_write => wb_rd_write + ); + + rs1_address <= id_rs1_address when stall_ex = '0' else rs1_address_p; + rs2_address <= id_rs2_address when stall_ex = '0' else rs2_address_p; + + store_previous_rsaddr: process(clk, stall_ex) + begin + if rising_edge(clk) and stall_ex = '0' then + rs1_address_p <= id_rs1_address; + rs2_address_p <= id_rs2_address; + end if; + end process store_previous_rsaddr; + + ------- Instruction Fetch (IF) Stage ------- + fetch: entity work.pp_fetch + generic map( + RESET_ADDRESS => RESET_ADDRESS + ) port map( + clk => clk, + reset => reset, + imem_address => imem_address, + imem_data_in => imem_data_in, + imem_req => imem_req, + imem_ack => imem_ack, + stall => stall_if, + flush => flush_if, + branch => branch_taken, + exception => exception_taken, + branch_target => branch_target, + evec => exception_target, + instruction_data => if_instruction, + instruction_address => if_pc, + instruction_ready => if_instruction_ready + ); + if_count_instruction <= if_instruction_ready; + + ------- Instruction Decode (ID) Stage ------- + decode: entity work.pp_decode + generic map( + RESET_ADDRESS => RESET_ADDRESS, + PROCESSOR_ID => PROCESSOR_ID + ) port map( + clk => clk, + reset => reset, + flush => flush_id, + stall => stall_id, + instruction_data => if_instruction, + instruction_address => if_pc, + instruction_ready => if_instruction_ready, + instruction_count => if_count_instruction, + funct3 => id_funct3, + rs1_addr => id_rs1_address, + rs2_addr => id_rs2_address, + rd_addr => id_rd_address, + csr_addr => id_csr_address, + shamt => id_shamt, + immediate => id_immediate, + rd_write => id_rd_write, + branch => id_branch, + alu_x_src => id_alu_x_src, + alu_y_src => id_alu_y_src, + alu_op => id_alu_op, + mem_op => id_mem_op, + mem_size => id_mem_size, + count_instruction => id_count_instruction, + pc => id_pc, + csr_write => id_csr_write, + csr_use_imm => id_csr_use_immediate, + decode_exception => id_exception, + decode_exception_cause => id_exception_cause + ); + + ------- Execute (EX) Stage ------- + execute: entity work.pp_execute + port map( + clk => clk, + reset => reset, + stall => stall_ex, + flush => flush_ex, + irq => irq, + software_interrupt => software_interrupt, + timer_interrupt => timer_interrupt, + dmem_address => ex_dmem_address, + dmem_data_size => ex_dmem_data_size, + dmem_data_out => ex_dmem_data_out, + dmem_read_req => ex_dmem_read_req, + dmem_write_req => ex_dmem_write_req, + rs1_addr_in => rs1_address, + rs2_addr_in => rs2_address, + rd_addr_in => id_rd_address, + rd_addr_out => ex_rd_address, + rs1_data_in => rs1_data, + rs2_data_in => rs2_data, + shamt_in => id_shamt, + immediate_in => id_immediate, + funct3_in => id_funct3, + pc_in => id_pc, + pc_out => ex_pc, + csr_addr_in => csr_read_address, + csr_addr_out => ex_csr_address, + csr_write_in => id_csr_write, + csr_write_out => ex_csr_write, + csr_value_in => csr_read_data, + csr_value_out => ex_csr_data, + csr_writeable_in => csr_read_writeable, + csr_use_immediate_in => id_csr_use_immediate, + alu_op_in => id_alu_op, + alu_x_src_in => id_alu_x_src, + alu_y_src_in => id_alu_y_src, + rd_write_in => id_rd_write, + rd_write_out => ex_rd_write, + rd_data_out => ex_rd_data, + branch_in => id_branch, + branch_out => ex_branch, + mem_op_in => id_mem_op, + mem_op_out => ex_mem_op, + mem_size_in => id_mem_size, + mem_size_out => ex_mem_size, + count_instruction_in => id_count_instruction, + count_instruction_out => ex_count_instruction, + ie_in => ie, + ie1_in => ie1, + mie_in => mie, + mtvec_in => mtvec, + mtvec_out => exception_target, + decode_exception_in => id_exception, + decode_exception_cause_in => id_exception_cause, + exception_out => exception_taken, + exception_context_out => ex_exception_context, + jump_out => branch_taken, + jump_target_out => branch_target, + mem_rd_write => mem_rd_write, + mem_rd_addr => mem_rd_address, + mem_rd_value => mem_rd_data, + mem_csr_addr => mem_csr_address, + mem_csr_value => mem_csr_data, + mem_csr_write => mem_csr_write, + mem_exception => mem_exception, + mem_exception_context => mem_exception_context, + wb_rd_write => wb_rd_write, + wb_rd_addr => wb_rd_address, + wb_rd_value => wb_rd_data, + wb_csr_addr => wb_csr_address, + wb_csr_value => wb_csr_data, + wb_csr_write => wb_csr_write, + wb_exception => wb_exception, + wb_exception_context => wb_exception_context, + mem_mem_op => mem_mem_op, + hazard_detected => load_hazard_detected + ); + + dmem_address <= ex_dmem_address when stall_mem = '0' else dmem_address_p; + dmem_data_size <= ex_dmem_data_size when stall_mem = '0' else dmem_data_size_p; + dmem_data_out <= ex_dmem_data_out when stall_mem = '0' else dmem_data_out_p; + dmem_read_req <= ex_dmem_read_req when stall_mem = '0' else dmem_read_req_p; + dmem_write_req <= ex_dmem_write_req when stall_mem = '0' else dmem_write_req_p; + + store_previous_dmem_address: process(clk, stall_mem) + begin + if rising_edge(clk) and stall_mem = '0' then + dmem_address_p <= ex_dmem_address; + dmem_data_size_p <= ex_dmem_data_size; + dmem_data_out_p <= ex_dmem_data_out; + dmem_read_req_p <= ex_dmem_read_req; + dmem_write_req_p <= ex_dmem_write_req; + end if; + end process store_previous_dmem_address; + + ------- Memory (MEM) Stage ------- + memory: entity work.pp_memory + port map( + clk => clk, + reset => reset, + stall => stall_mem, + dmem_data_in => dmem_data_in, + dmem_read_ack => dmem_read_ack, + dmem_write_ack => dmem_write_ack, + pc => ex_pc, + rd_write_in => ex_rd_write, + rd_write_out => mem_rd_write, + rd_data_in => ex_rd_data, + rd_data_out => mem_rd_data, + rd_addr_in => ex_rd_address, + rd_addr_out => mem_rd_address, + branch => ex_branch, + mem_op_in => ex_mem_op, + mem_op_out => mem_mem_op, + mem_size_in => ex_mem_size, + count_instr_in => ex_count_instruction, + count_instr_out => mem_count_instruction, + exception_in => exception_taken, + exception_out => mem_exception, + exception_context_in => ex_exception_context, + exception_context_out => mem_exception_context, + csr_addr_in => ex_csr_address, + csr_addr_out => mem_csr_address, + csr_write_in => ex_csr_write, + csr_write_out => mem_csr_write, + csr_data_in => ex_csr_data, + csr_data_out => mem_csr_data + ); + + ------- Writeback (WB) Stage ------- + writeback: entity work.pp_writeback + port map( + clk => clk, + reset => reset, + count_instr_in => mem_count_instruction, + count_instr_out => wb_count_instruction, + exception_ctx_in => mem_exception_context, + exception_ctx_out => wb_exception_context, + exception_in => mem_exception, + exception_out => wb_exception, + csr_write_in => mem_csr_write, + csr_write_out => wb_csr_write, + csr_data_in => mem_csr_data, + csr_data_out => wb_csr_data, + csr_addr_in => mem_csr_address, + csr_addr_out => wb_csr_address, + rd_addr_in => mem_rd_address, + rd_addr_out => wb_rd_address, + rd_write_in => mem_rd_write, + rd_write_out => wb_rd_write, + rd_data_in => mem_rd_data, + rd_data_out => wb_rd_data + ); + +end architecture behaviour; + diff --git a/designs/encrypted_ip/pic/pp_counter.vhd b/designs/encrypted_ip/pic/pp_counter.vhd new file mode 100644 index 000000000..1fb169000 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_counter.vhd @@ -0,0 +1,40 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 -2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity pp_counter is + generic( + COUNTER_WIDTH : natural := 64; + COUNTER_STEP : natural := 1 + ); + port( + clk : in std_logic; + reset : in std_logic; + + count : out std_logic_vector(COUNTER_WIDTH - 1 downto 0); + increment : in std_logic + ); +end entity pp_counter; + +architecture behaviour of pp_counter is + signal current_count : std_logic_vector(COUNTER_WIDTH - 1 downto 0); +begin + + count <= current_count; + + counter: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + current_count <= (others => '0'); + elsif increment = '1' then + current_count <= std_logic_vector(unsigned(current_count) + COUNTER_STEP); + end if; + end if; + end process counter; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_csr.vhd b/designs/encrypted_ip/pic/pp_csr.vhd new file mode 100644 index 000000000..b08a669a2 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_csr.vhd @@ -0,0 +1,127 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; + +--! @brief Package containing constants and utility functions relating to status and control registers. +package pp_csr is + + --! Type used for specifying control and status register addresses. + subtype csr_address is std_logic_vector(11 downto 0); + + --! Type used for exception cause values. + subtype csr_exception_cause is std_logic_vector(5 downto 0); -- Upper bit is the interrupt bit + + --! Converts an exception cause to a std_logic_vector. + function to_std_logic_vector(input : in csr_exception_cause) return std_logic_vector; + + --! Control/status register write mode: + type csr_write_mode is ( + CSR_WRITE_NONE, CSR_WRITE_SET, CSR_WRITE_CLEAR, CSR_WRITE_REPLACE + ); + + -- Exception cause values: + constant CSR_CAUSE_INSTR_MISALIGN : csr_exception_cause := b"000000"; + constant CSR_CAUSE_INSTR_FETCH : csr_exception_cause := b"000001"; + constant CSR_CAUSE_INVALID_INSTR : csr_exception_cause := b"000010"; + constant CSR_CAUSE_BREAKPOINT : csr_exception_cause := b"000011"; + constant CSR_CAUSE_LOAD_MISALIGN : csr_exception_cause := b"000100"; + constant CSR_CAUSE_LOAD_ERROR : csr_exception_cause := b"000101"; + constant CSR_CAUSE_STORE_MISALIGN : csr_exception_cause := b"000110"; + constant CSR_CAUSE_STORE_ERROR : csr_exception_cause := b"000111"; + constant CSR_CAUSE_ECALL : csr_exception_cause := b"001011"; + constant CSR_CAUSE_NONE : csr_exception_cause := b"011111"; + + constant CSR_CAUSE_SOFTWARE_INT : csr_exception_cause := b"100000"; + constant CSR_CAUSE_TIMER_INT : csr_exception_cause := b"100001"; + constant CSR_CAUSE_IRQ_BASE : csr_exception_cause := b"110000"; + + -- Control register IDs, specified in the immediate field of csr* instructions: + constant CSR_CYCLE : csr_address := x"c00"; + constant CSR_CYCLEH : csr_address := x"c80"; + constant CSR_TIME : csr_address := x"c01"; + constant CSR_TIMEH : csr_address := x"c81"; + constant CSR_INSTRET : csr_address := x"c02"; + constant CSR_INSTRETH : csr_address := x"c82"; + + constant CSR_MCPUID : csr_address := x"f00"; + constant CSR_MIMPID : csr_address := x"f01"; + constant CSR_MHARTID : csr_address := x"f10"; + + constant CSR_MSTATUS : csr_address := x"300"; + constant CSR_MTVEC : csr_address := x"301"; + constant CSR_MTDELEG : csr_address := x"302"; + constant CSR_MIE : csr_address := x"304"; + + constant CSR_MTIMECMP : csr_address := x"321"; + constant CSR_MTIME : csr_address := x"701"; + + constant CSR_MSCRATCH : csr_address := x"340"; + constant CSR_MEPC : csr_address := x"341"; + constant CSR_MCAUSE : csr_address := x"342"; + constant CSR_MBADADDR : csr_address := x"343"; + constant CSR_MIP : csr_address := x"344"; + + constant CSR_MTOHOST : csr_address := x"780"; + constant CSR_MFROMHOST : csr_address := x"781"; + + -- Values used as control register IDs in ERET: + constant CSR_EPC_ERET : csr_address := x"100"; + + -- Offset into the exception vector for handling machine-mode exceptions: + constant CSR_MTVEC_M_OFFSET : natural := 192; + + -- Additional CSRs from supervisor mode that aliases machine mode registers + -- in this implementation: + --constant CSR_STVEC : csr_address := x"101"; + --constant CSR_SEPC : csr_address := x"141"; + + -- Status register bit indices: + constant CSR_SR_IE : natural := 0; + constant CSR_SR_IE1 : natural := 3; + + -- MIE and MIP register bit indices: + constant CSR_MIE_MSIE : natural := 3; + constant CSR_MIE_MTIE : natural := 7; + constant CSR_MIP_MSIP : natural := CSR_MIE_MSIE; + constant CSR_MIP_MTIP : natural := CSR_MIE_MTIE; + + -- Exception context; this record contains all state that can be manipulated + -- when an exception is taken. + type csr_exception_context is + record + ie, ie1 : std_logic; -- Enable Interrupt bits + cause : csr_exception_cause; + badaddr : std_logic_vector(31 downto 0); + end record; + + --! Creates the value of the mstatus registe from the EI and EI1 bits. + function csr_make_mstatus(ie, ie1 : in std_logic) return std_logic_vector; + +end package pp_csr; + +package body pp_csr is + + function to_std_logic_vector(input : in csr_exception_cause) + return std_logic_vector is + begin + return (31 => input(5), 30 downto 5 => '0') & input(4 downto 0); + end function to_std_logic_vector; + + function csr_make_mstatus(ie, ie1 : in std_logic) return std_logic_vector is + variable retval : std_logic_vector(31 downto 0); + begin + retval := ( + 11 downto 10 => '1', -- PRV3 + 8 downto 7 => '1', -- PRV2 + 5 downto 4 => '1', -- PRV1 + CSR_SR_IE1 => ie1, -- IE1 + 2 downto 1 => '1', -- PRV + CSR_SR_IE => ie, -- IE + others => '0'); + return retval; + end function csr_make_mstatus; + +end package body pp_csr; diff --git a/designs/encrypted_ip/pic/pp_csr_alu.vhd b/designs/encrypted_ip/pic/pp_csr_alu.vhd new file mode 100644 index 000000000..2c5ab5812 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_csr_alu.vhd @@ -0,0 +1,43 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_csr.all; + +--! @brief ALU used for calculating new values of control and status registers. +entity pp_csr_alu is + port( + x, y : in std_logic_vector(31 downto 0); + result : out std_logic_vector(31 downto 0); + immediate : in std_logic_vector(4 downto 0); + use_immediate : in std_logic; + write_mode : in csr_write_mode + ); +end entity pp_csr_alu; + +architecture behaviour of pp_csr_alu is + signal a, b : std_logic_vector(31 downto 0); +begin + + a <= x; + b <= y when use_immediate = '0' else std_logic_vector(resize(unsigned(immediate), b'length)); + + calculate: process(a, b, write_mode) + begin + case write_mode is + when CSR_WRITE_NONE => + result <= a; + when CSR_WRITE_SET => + result <= a or b; + when CSR_WRITE_CLEAR => + result <= a and (not b); + when CSR_WRITE_REPLACE => + result <= b; + end case; + end process calculate; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_csr_unit.vhd b/designs/encrypted_ip/pic/pp_csr_unit.vhd new file mode 100644 index 000000000..cebae2da4 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_csr_unit.vhd @@ -0,0 +1,294 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_csr.all; +use work.pp_utilities.all; + +entity pp_csr_unit is + generic( + PROCESSOR_ID : std_logic_vector(31 downto 0) + ); + port( + clk, timer_clk : in std_logic; + reset : in std_logic; + + -- IRQ signals: + irq : in std_logic_vector(7 downto 0); + + -- Count retired instruction: + count_instruction : in std_logic; + + -- HTIF interface: + fromhost_data : in std_logic_vector(31 downto 0); + fromhost_updated : in std_logic; + tohost_data : out std_logic_vector(31 downto 0); + tohost_updated : out std_logic; + + -- Read port: + read_address : in csr_address; + read_data_out : out std_logic_vector(31 downto 0); + read_writeable : out boolean; + + -- Write port: + write_address : in csr_address; + write_data_in : in std_logic_vector(31 downto 0); + write_mode : in csr_write_mode; + + -- Exception context write port: + exception_context : in csr_exception_context; + exception_context_write : in std_logic; + + -- Interrupts originating from this unit: + software_interrupt_out : out std_logic; + timer_interrupt_out : out std_logic; + + -- Registers needed for exception handling, always read: + mie_out : out std_logic_vector(31 downto 0); + mtvec_out : out std_logic_vector(31 downto 0); + ie_out, ie1_out : out std_logic + ); +end entity pp_csr_unit; + +architecture behaviour of pp_csr_unit is + + -- Counters: + signal counter_time : std_logic_vector(63 downto 0); + signal counter_cycle : std_logic_vector(63 downto 0); + signal counter_instret : std_logic_vector(63 downto 0); + + -- Machine time counter: + signal counter_mtime : std_logic_vector(31 downto 0); + signal mtime_compare : std_logic_vector(31 downto 0); + + -- Machine-mode registers: + signal mcause : csr_exception_cause; + signal mbadaddr : std_logic_vector(31 downto 0); + signal mscratch : std_logic_vector(31 downto 0); + signal mepc : std_logic_vector(31 downto 0); + signal mtvec : std_logic_vector(31 downto 0) := x"00000100"; + signal mie : std_logic_vector(31 downto 0) := (others => '0'); + + -- Interrupt enable bits: + signal ie, ie1 : std_logic; + + -- HTIF FROMHOST register: + signal fromhost: std_logic_vector(31 downto 0); + + -- Interrupt signals: + signal timer_interrupt : std_logic; + signal software_interrupt : std_logic; + +begin + + -- Interrupt signals: + software_interrupt_out <= software_interrupt; + timer_interrupt_out <= timer_interrupt; + ie_out <= ie; + ie1_out <= ie1; + mie_out <= mie; + + -- The two upper bits of the CSR address encodes the accessibility of the CSR: + read_writeable <= read_address(11 downto 10) /= b"11"; + + --! Updates the FROMHOST register when new data is available. + htif_fromhost: process(clk) + begin + if rising_edge(clk) then + if fromhost_updated = '1' then + fromhost <= fromhost_data; + end if; + end if; + end process htif_fromhost; + + --! Sends a word to the host over the HTIF interface. + htif_tohost: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + tohost_data <= (others => '0'); + tohost_updated <= '0'; + else + if write_mode /= CSR_WRITE_NONE and write_address = CSR_MTOHOST then + tohost_data <= write_data_in; + tohost_updated <= '1'; + else + tohost_updated <= '0'; + end if; + end if; + end if; + end process htif_tohost; + + mtime_counter: process(timer_clk, reset) + begin + if reset = '1' then -- Asynchronous reset because timer_clk is slower than clk + counter_mtime <= (others => '0'); + elsif rising_edge(timer_clk) then + counter_mtime <= std_logic_vector(unsigned(counter_mtime) + 1); + end if; + end process mtime_counter; + + mtime_interrupt: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + timer_interrupt <= '0'; + else + if write_mode /= CSR_WRITE_NONE and write_address = CSR_MTIMECMP then + timer_interrupt <= '0'; + elsif counter_mtime = mtime_compare then + timer_interrupt <= '1'; + end if; + end if; + end if; + end process mtime_interrupt; + + write: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + software_interrupt <= '0'; + mtvec <= x"00000100"; + mepc <= x"00000100"; + mie <= (others => '0'); + ie <= '0'; + ie1 <= '0'; + else + if exception_context_write = '1' then + ie <= exception_context.ie; + ie1 <= exception_context.ie1; + mcause <= exception_context.cause; + mbadaddr <= exception_context.badaddr; + end if; + + if write_mode /= CSR_WRITE_NONE then + case write_address is + when CSR_MSTATUS => -- Status register + ie1 <= write_data_in(CSR_SR_IE1); + ie <= write_data_in(CSR_SR_IE); + when CSR_MSCRATCH => -- Scratch register + mscratch <= write_data_in; + when CSR_MEPC => -- Exception return address + mepc <= write_data_in; + --when CSR_MCAUSE => -- Exception cause + -- mcause <= write_data_in(31) & write_data_in(4 downto 0); + when CSR_MTVEC => -- Exception vector address + mtvec <= write_data_in; + when CSR_MTIMECMP => -- Time compare register + mtime_compare <= write_data_in; + when CSR_MIE => -- Interrupt enable register: + mie <= write_data_in; + when CSR_MIP => -- Interrupt pending register: + software_interrupt <= write_data_in(CSR_MIP_MSIP); + when others => + -- Ignore writes to invalid or read-only registers + end case; + end if; + end if; + end if; + end process write; + + read: process(clk) + begin + if rising_edge(clk) then + + if write_mode /= CSR_WRITE_NONE and write_address = CSR_MTVEC then + mtvec_out <= write_data_in; + else + mtvec_out <= mtvec; + end if; + + if write_mode /= CSR_WRITE_NONE and write_address = read_address then + read_data_out <= write_data_in; + else + case read_address is + + -- Machine mode registers: + when CSR_MCPUID => -- CPU features register + read_data_out <= ( + 8 => '1', -- Set the bit corresponding to I + others => '0'); + when CSR_MIMPID => -- Implementation/Implementor ID + read_data_out <= (31 downto 16 => '0') & x"8000"; + -- The anonymous source ID, 0x8000 is used until an open-source implementation ID + -- is available for use. + when CSR_MHARTID => -- Hardware thread ID + read_data_out <= PROCESSOR_ID; + when CSR_MFROMHOST => -- Data from a host environment + read_data_out <= fromhost; + when CSR_MSTATUS => -- Status register + read_data_out <= csr_make_mstatus(ie, ie1); + when CSR_MSCRATCH => -- Scratch register + read_data_out <= mscratch; + when CSR_MEPC => -- Exception PC value + read_data_out <= mepc; + when CSR_MTVEC => -- Exception vector address + read_data_out <= mtvec; + when CSR_MTDELEG => -- Exception vector delegation register, unsupported + read_data_out <= (others => '0'); + when CSR_MIP => -- Interrupt pending + read_data_out <= irq & (CSR_MIP_MTIP => timer_interrupt, CSR_MIP_MSIP => software_interrupt, + 23 downto 8 => '0', 6 downto 4 => '0', 2 downto 0 => '0'); + when CSR_MIE => -- Interrupt enable register + read_data_out <= mie; + when CSR_MBADADDR => -- Bad memory address + read_data_out <= mbadaddr; + when CSR_MCAUSE => -- Exception cause + read_data_out <= mcause(5) & (30 downto 5 => '0') & mcause(4 downto 0); --to_std_logic_vector(mcause); + + -- Timers and counters: + when CSR_MTIME => -- Machine time counter register + read_data_out <= counter_mtime; + when CSR_MTIMECMP => -- Machine time compare register + read_data_out <= mtime_compare; + + when CSR_TIME => + read_data_out <= counter_time(31 downto 0); + when CSR_TIMEH => + read_data_out <= counter_time(63 downto 32); + when CSR_CYCLE => + read_data_out <= counter_cycle(31 downto 0); + when CSR_CYCLEH => + read_data_out <= counter_cycle(63 downto 32); + when CSR_INSTRET => + read_data_out <= counter_instret(31 downto 0); + when CSR_INSTRETH => + read_data_out <= counter_instret(63 downto 32); + + -- Return zero from write-only registers and invalid register addresses: + when others => + read_data_out <= (others => '0'); + end case; + end if; + end if; + end process read; + + timer_counter: entity work.pp_counter + port map( + clk => timer_clk, + reset => reset, + count => counter_time, + increment => '1' + ); + + cycle_counter: entity work.pp_counter + port map( + clk => clk, + reset => reset, + count => counter_cycle, + increment => '1' + ); + + instret_counter: entity work.pp_counter + port map( + clk => clk, + reset => reset, + count => counter_instret, + increment => count_instruction + ); + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_decode.vhd b/designs/encrypted_ip/pic/pp_decode.vhd new file mode 100644 index 000000000..9d5b57f54 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_decode.vhd @@ -0,0 +1,140 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_types.all; +use work.pp_constants.all; +use work.pp_csr.all; + +--! @brief Instruction decode unit. +entity pp_decode is + generic( + RESET_ADDRESS : std_logic_vector(31 downto 0); + PROCESSOR_ID : std_logic_vector(31 downto 0) + ); + port( + clk : in std_logic; + reset : in std_logic; + + flush : in std_logic; + stall : in std_logic; + + -- Instruction input: + instruction_data : in std_logic_vector(31 downto 0); + instruction_address : in std_logic_vector(31 downto 0); + instruction_ready : in std_logic; + instruction_count : in std_logic; + + -- Register addresses: + rs1_addr, rs2_addr, rd_addr : out register_address; + csr_addr : out csr_address; + + -- Shamt value for shift operations: + shamt : out std_logic_vector(4 downto 0); + funct3 : out std_logic_vector(2 downto 0); + + -- Immediate value for immediate instructions: + immediate : out std_logic_vector(31 downto 0); + + -- Control signals: + rd_write : out std_logic; + branch : out branch_type; + alu_x_src : out alu_operand_source; + alu_y_src : out alu_operand_source; + alu_op : out alu_operation; + mem_op : out memory_operation_type; + mem_size : out memory_operation_size; + count_instruction : out std_logic; + + -- Instruction address: + pc : out std_logic_vector(31 downto 0); + + -- CSR control signals: + csr_write : out csr_write_mode; + csr_use_imm : out std_logic; + + -- Exception output signals: + decode_exception : out std_logic; + decode_exception_cause : out csr_exception_cause + ); + +end entity pp_decode; + +architecture behaviour of pp_decode is + signal instruction : std_logic_vector(31 downto 0); + signal immediate_value : std_logic_vector(31 downto 0); +begin + + immediate <= immediate_value; + + get_instruction: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + instruction <= RISCV_NOP; + pc <= RESET_ADDRESS; + count_instruction <= '0'; + elsif stall = '1' then + count_instruction <= '0'; + elsif flush = '1' or instruction_ready = '0' then + instruction <= RISCV_NOP; + count_instruction <= '0'; + else + instruction <= instruction_data; + count_instruction <= instruction_count; + pc <= instruction_address; + end if; + end if; + end process get_instruction; + +-- -- Extract register addresses from the instruction word: + rs1_addr <= instruction(19 downto 15); + rs2_addr <= instruction(24 downto 20); + rd_addr <= instruction(11 downto 7); + + -- Extract the shamt value from the instruction word: + shamt <= instruction(24 downto 20); + + -- Extract the value specifying which comparison to do in branch instructions: + funct3 <= instruction(14 downto 12); + + -- Extract the immediate value from the instruction word: + immediate_decoder: entity work.pp_imm_decoder + port map( + instruction => instruction(31 downto 2), + immediate => immediate_value + ); + + decode_csr_addr: process(immediate_value) + begin + if immediate_value(11 downto 0) = CSR_EPC_ERET then + csr_addr <= CSR_MEPC; + else + csr_addr <= immediate_value(11 downto 0); + end if; + end process decode_csr_addr; + + control_unit: entity work.pp_control_unit + port map( + opcode => instruction(6 downto 2), + funct3 => instruction(14 downto 12), + funct7 => instruction(31 downto 25), + funct12 => instruction(31 downto 20), + rd_write => rd_write, + branch => branch, + alu_x_src => alu_x_src, + alu_y_src => alu_y_src, + alu_op => alu_op, + mem_op => mem_op, + mem_size => mem_size, + decode_exception => decode_exception, + decode_exception_cause => decode_exception_cause, + csr_write => csr_write, + csr_imm => csr_use_imm + ); + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_execute.vhd b/designs/encrypted_ip/pic/pp_execute.vhd new file mode 100644 index 000000000..a723d38f7 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_execute.vhd @@ -0,0 +1,541 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_types.all; +use work.pp_csr.all; +use work.pp_utilities.all; + +entity pp_execute is + port( + clk : in std_logic; + reset : in std_logic; + + stall, flush : in std_logic; + + -- Interrupt inputs: + irq : in std_logic_vector(7 downto 0); + software_interrupt, timer_interrupt : in std_logic; + + -- Data memory outputs: + dmem_address : out std_logic_vector(31 downto 0); + dmem_data_out : out std_logic_vector(31 downto 0); + dmem_data_size : out std_logic_vector( 1 downto 0); + dmem_read_req : out std_logic; + dmem_write_req : out std_logic; + + -- Register addresses: + rs1_addr_in, rs2_addr_in, rd_addr_in : in register_address; + rd_addr_out : out register_address; + + -- Register values: + rs1_data_in, rs2_data_in : in std_logic_vector(31 downto 0); + rd_data_out : out std_logic_vector(31 downto 0); + + -- Constant values: + shamt_in : in std_logic_vector(4 downto 0); + immediate_in : in std_logic_vector(31 downto 0); + + -- Instruction address: + pc_in : in std_logic_vector(31 downto 0); + pc_out : out std_logic_vector(31 downto 0); + + -- Funct3 value from the instruction, used to choose which comparison + -- is used when branching: + funct3_in : in std_logic_vector(2 downto 0); + + -- CSR signals: + csr_addr_in : in csr_address; + csr_addr_out : out csr_address; + csr_write_in : in csr_write_mode; + csr_write_out : out csr_write_mode; + csr_value_in : in std_logic_vector(31 downto 0); + csr_value_out : out std_logic_vector(31 downto 0); + csr_writeable_in : in boolean; + csr_use_immediate_in : in std_logic; + + -- Control signals: + alu_op_in : in alu_operation; + alu_x_src_in : in alu_operand_source; + alu_y_src_in : in alu_operand_source; + rd_write_in : in std_logic; + rd_write_out : out std_logic; + branch_in : in branch_type; + branch_out : out branch_type; + + -- Memory control signals: + mem_op_in : in memory_operation_type; + mem_op_out : out memory_operation_type; + mem_size_in : in memory_operation_size; + mem_size_out : out memory_operation_size; + + -- Whether the instruction should be counted: + count_instruction_in : in std_logic; + count_instruction_out : out std_logic; + + -- Exception control registers: + ie_in, ie1_in : in std_logic; + mie_in : in std_logic_vector(31 downto 0); + mtvec_in : in std_logic_vector(31 downto 0); + mtvec_out : out std_logic_vector(31 downto 0); + --mepc_in : in std_logic_vector(31 downto 0); + + -- Exception signals: + decode_exception_in : in std_logic; + decode_exception_cause_in : in csr_exception_cause; + + -- Exception outputs: + exception_out : out std_logic; + exception_context_out : out csr_exception_context; + + -- Control outputs: + jump_out : out std_logic; + jump_target_out : out std_logic_vector(31 downto 0); + + -- Inputs to the forwarding logic from the MEM stage: + mem_rd_write : in std_logic; + mem_rd_addr : in register_address; + mem_rd_value : in std_logic_vector(31 downto 0); + mem_csr_addr : in csr_address; + mem_csr_write : in csr_write_mode; + mem_csr_value : in std_logic_vector(31 downto 0); + mem_exception : in std_logic; + mem_exception_context : in csr_exception_context; + + -- Inputs to the forwarding logic from the WB stage: + wb_rd_write : in std_logic; + wb_rd_addr : in register_address; + wb_rd_value : in std_logic_vector(31 downto 0); + wb_csr_addr : in csr_address; + wb_csr_write : in csr_write_mode; + wb_csr_value : in std_logic_vector(31 downto 0); + wb_exception : in std_logic; + wb_exception_context : in csr_exception_context; + + -- Hazard detection unit signals: + mem_mem_op : in memory_operation_type; + hazard_detected : out std_logic + ); +end entity pp_execute; + +architecture behaviour of pp_execute is + signal alu_op : alu_operation; + signal alu_x_src, alu_y_src : alu_operand_source; + + signal alu_x, alu_y, alu_result : std_logic_vector(31 downto 0); + + signal rs1_addr, rs2_addr : register_address; + signal rs1_data, rs2_data : std_logic_vector(31 downto 0); + + signal mem_op : memory_operation_type; + signal mem_size : memory_operation_size; + + signal pc : std_logic_vector(31 downto 0); + signal immediate : std_logic_vector(31 downto 0); + signal shamt : std_logic_vector( 4 downto 0); + signal funct3 : std_logic_vector( 2 downto 0); + + signal rs1_forwarded, rs2_forwarded : std_logic_vector(31 downto 0); + + signal branch : branch_type; + signal branch_condition : std_logic; + signal do_jump : std_logic; + signal jump_target : std_logic_vector(31 downto 0); + + signal mtvec, mtvec_forwarded : std_logic_vector(31 downto 0); + signal mie, mie_forwarded : std_logic_vector(31 downto 0); + + signal csr_write : csr_write_mode; + signal csr_addr : csr_address; + signal csr_use_immediate : std_logic; + signal csr_writeable : boolean; + + signal csr_value, csr_value_forwarded : std_logic_vector(31 downto 0); + + signal decode_exception : std_logic; + signal decode_exception_cause : csr_exception_cause; + + signal exception_taken : std_logic; + signal exception_cause : csr_exception_cause; + signal exception_addr : std_logic_vector(31 downto 0); + + signal exception_context_forwarded : csr_exception_context; + + signal data_misaligned, instr_misaligned : std_logic; + + signal irq_asserted : std_logic; + signal irq_asserted_num : std_logic_vector(3 downto 0); +begin + + -- Register values should not be latched in by a clocked process, + -- this is already done in the register files. + csr_value <= csr_value_in; + rd_data_out <= alu_result; + + branch_out <= branch; + + mem_op_out <= mem_op; + mem_size_out <= mem_size; + + csr_write_out <= csr_write; + csr_addr_out <= csr_addr; + + pc_out <= pc; + + exception_out <= exception_taken; + exception_context_out <= ( + ie => exception_context_forwarded.ie, + ie1 => exception_context_forwarded.ie1, + cause => exception_cause, + badaddr => exception_addr + ) when exception_taken = '1' else exception_context_forwarded; + + do_jump <= (to_std_logic(branch = BRANCH_JUMP or branch = BRANCH_JUMP_INDIRECT) + or (to_std_logic(branch = BRANCH_CONDITIONAL) and branch_condition) + or to_std_logic(branch = BRANCH_SRET)) and not stall; + jump_out <= do_jump; + jump_target_out <= jump_target; + + mtvec_out <= std_logic_vector(unsigned(mtvec_forwarded) + CSR_MTVEC_M_OFFSET); + exception_taken <= not stall and (decode_exception or to_std_logic(exception_cause /= CSR_CAUSE_NONE)); + + irq_asserted <= to_std_logic(exception_context_forwarded.ie = '1' and (irq and mie_forwarded(31 downto 24)) /= x"00"); + + rs1_data <= rs1_data_in; + rs2_data <= rs2_data_in; + + dmem_address <= alu_result when (mem_op /= MEMOP_TYPE_NONE and mem_op /= MEMOP_TYPE_INVALID) and exception_taken = '0' + else (others => '0'); + dmem_data_out <= rs2_forwarded; + dmem_write_req <= '1' when mem_op = MEMOP_TYPE_STORE and exception_taken = '0' else '0'; + dmem_read_req <= '1' when memop_is_load(mem_op) and exception_taken = '0' else '0'; + + pipeline_register: process(clk) + begin + if rising_edge(clk) then + if reset = '1' or flush = '1' then + rd_write_out <= '0'; + branch <= BRANCH_NONE; + csr_write <= CSR_WRITE_NONE; + mem_op <= MEMOP_TYPE_NONE; + decode_exception <= '0'; + count_instruction_out <= '0'; + elsif stall = '0' then + pc <= pc_in; + count_instruction_out <= count_instruction_in; + + -- Register signals: + rd_write_out <= rd_write_in; + rd_addr_out <= rd_addr_in; + rs1_addr <= rs1_addr_in; + rs2_addr <= rs2_addr_in; + + -- ALU signals: + alu_op <= alu_op_in; + alu_x_src <= alu_x_src_in; + alu_y_src <= alu_y_src_in; + + -- Control signals: + branch <= branch_in; + mem_op <= mem_op_in; + mem_size <= mem_size_in; + + -- Constant values: + immediate <= immediate_in; + shamt <= shamt_in; + funct3 <= funct3_in; + + -- CSR signals: + csr_write <= csr_write_in; + csr_addr <= csr_addr_in; + csr_use_immediate <= csr_use_immediate_in; + csr_writeable <= csr_writeable_in; + + -- Exception vector base: + mtvec <= mtvec_in; + mie <= mie_in; + + -- Instruction decoder exceptions: + decode_exception <= decode_exception_in; + decode_exception_cause <= decode_exception_cause_in; + end if; + end if; + end process pipeline_register; + + set_data_size: process(mem_size) + begin + case mem_size is + when MEMOP_SIZE_BYTE => + dmem_data_size <= b"01"; + when MEMOP_SIZE_HALFWORD => + dmem_data_size <= b"10"; + when MEMOP_SIZE_WORD => + dmem_data_size <= b"00"; + when others => + dmem_data_size <= b"11"; + end case; + end process set_data_size; + + get_irq_num: process(irq, exception_context_forwarded, mie_forwarded) + variable temp : std_logic_vector(3 downto 0); + begin + temp := (others => '0'); + + for i in 0 to 7 loop + if irq(i) = '1' and mie_forwarded(24 + i) = '1' then + temp := std_logic_vector(to_unsigned(i, temp'length)); + exit; + end if; + end loop; + + irq_asserted_num <= temp; + end process get_irq_num; + + data_misalign_check: process(mem_size, alu_result) + begin + case mem_size is + when MEMOP_SIZE_HALFWORD => + if alu_result(0) /= '0' then + data_misaligned <= '1'; + else + data_misaligned <= '0'; + end if; + when MEMOP_SIZE_WORD => + if alu_result(1 downto 0) /= b"00" then + data_misaligned <= '1'; + else + data_misaligned <= '0'; + end if; + when others => + data_misaligned <= '0'; + end case; + end process data_misalign_check; + + instr_misalign_check: process(jump_target, branch, branch_condition, do_jump) + begin + if jump_target(1 downto 0) /= b"00" and do_jump = '1' then + instr_misaligned <= '1'; + else + instr_misaligned <= '0'; + end if; + end process instr_misalign_check; + + find_exception_cause: process(decode_exception, decode_exception_cause, mem_op, + data_misaligned, instr_misaligned, irq_asserted, irq_asserted_num, mie_forwarded, + software_interrupt, timer_interrupt, exception_context_forwarded) + begin + if irq_asserted = '1' then + exception_cause <= std_logic_vector(unsigned(CSR_CAUSE_IRQ_BASE) + unsigned(irq_asserted_num)); + elsif software_interrupt = '1' and mie_forwarded(CSR_MIE_MSIE) = '1' and exception_context_forwarded.ie = '1' then + exception_cause <= CSR_CAUSE_SOFTWARE_INT; + elsif timer_interrupt = '1' and mie_forwarded(CSR_MIE_MTIE) = '1' and exception_context_forwarded.ie = '1' then + exception_cause <= CSR_CAUSE_TIMER_INT; + elsif decode_exception = '1' then + exception_cause <= decode_exception_cause; + elsif mem_op = MEMOP_TYPE_INVALID then + exception_cause <= CSR_CAUSE_INVALID_INSTR; + elsif instr_misaligned = '1' then + exception_cause <= CSR_CAUSE_INSTR_MISALIGN; + elsif data_misaligned = '1' and mem_op = MEMOP_TYPE_STORE then + exception_cause <= CSR_CAUSE_STORE_MISALIGN; + elsif data_misaligned = '1' and memop_is_load(mem_op) then + exception_cause <= CSR_CAUSE_LOAD_MISALIGN; + else + exception_cause <= CSR_CAUSE_NONE; + end if; + end process find_exception_cause; + + find_exception_addr: process(instr_misaligned, data_misaligned, jump_target, alu_result) + begin + if instr_misaligned = '1' then + exception_addr <= jump_target; + elsif data_misaligned = '1' then + exception_addr <= alu_result; + else + exception_addr <= (others => '0'); + end if; + end process find_exception_addr; + + calc_jump_tgt: process(branch, pc, rs1_forwarded, immediate, csr_value_forwarded) + begin + case branch is + when BRANCH_JUMP | BRANCH_CONDITIONAL => + jump_target <= std_logic_vector(unsigned(pc) + unsigned(immediate)); + when BRANCH_JUMP_INDIRECT => + jump_target <= std_logic_vector(unsigned(rs1_forwarded) + unsigned(immediate)); + when BRANCH_SRET => + jump_target <= csr_value_forwarded; + when others => + jump_target <= (others => '0'); + end case; + end process calc_jump_tgt; + + alu_x_mux: entity work.pp_alu_mux + port map( + source => alu_x_src, + register_value => rs1_forwarded, + immediate_value => immediate, + shamt_value => shamt, + pc_value => pc, + csr_value => csr_value_forwarded, + output => alu_x + ); + + alu_y_mux: entity work.pp_alu_mux + port map( + source => alu_y_src, + register_value => rs2_forwarded, + immediate_value => immediate, + shamt_value => shamt, + pc_value => pc, + csr_value => csr_value_forwarded, + output => alu_y + ); + + alu_x_forward: process(mem_rd_write, mem_rd_value, mem_rd_addr, rs1_addr, + rs1_data, wb_rd_write, wb_rd_addr, wb_rd_value) + begin + if mem_rd_write = '1' and mem_rd_addr = rs1_addr and mem_rd_addr /= b"00000" then + rs1_forwarded <= mem_rd_value; + elsif wb_rd_write = '1' and wb_rd_addr = rs1_addr and wb_rd_addr /= b"00000" then + rs1_forwarded <= wb_rd_value; + else + rs1_forwarded <= rs1_data; + end if; + end process alu_x_forward; + + alu_y_forward: process(mem_rd_write, mem_rd_value, mem_rd_addr, rs2_addr, + rs2_data, wb_rd_write, wb_rd_addr, wb_rd_value) + begin + if mem_rd_write = '1' and mem_rd_addr = rs2_addr and mem_rd_addr /= b"00000" then + rs2_forwarded <= mem_rd_value; + elsif wb_rd_write = '1' and wb_rd_addr = rs2_addr and wb_rd_addr /= b"00000" then + rs2_forwarded <= wb_rd_value; + else + rs2_forwarded <= rs2_data; + end if; + end process alu_y_forward; + + csr_forward: process(mem_csr_write, wb_csr_write, csr_addr, mem_csr_addr, wb_csr_addr, + csr_value, mem_csr_value, wb_csr_value, csr_writeable, mem_exception, wb_exception, + mem_exception_context, wb_exception_context) + begin + if csr_addr = CSR_MCAUSE and mem_exception = '1' then + csr_value_forwarded <= to_std_logic_vector(mem_exception_context.cause); + elsif csr_addr = CSR_MSTATUS and mem_exception = '1' then + csr_value_forwarded <= csr_make_mstatus(mem_exception_context.ie, mem_exception_context.ie1); + elsif csr_addr = CSR_MBADADDR and mem_exception = '1' then + csr_value_forwarded <= mem_exception_context.badaddr; + elsif mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = csr_addr and csr_writeable then + csr_value_forwarded <= mem_csr_value; + elsif csr_addr = CSR_MCAUSE and wb_exception = '1' then + csr_value_forwarded <= to_std_logic_vector(wb_exception_context.cause); + elsif csr_addr = CSR_MSTATUS and wb_exception = '1' then + csr_value_forwarded <= csr_make_mstatus(wb_exception_context.ie, wb_exception_context.ie1); + elsif csr_addr = CSR_MBADADDR and wb_exception = '1' then + csr_value_forwarded <= wb_exception_context.badaddr; + elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = csr_addr and csr_writeable then + csr_value_forwarded <= wb_csr_value; + else + csr_value_forwarded <= csr_value; + end if; + end process csr_forward; + + mtvec_forward: process(mem_csr_write, mem_csr_addr, mem_csr_value, + wb_csr_write, wb_csr_addr, wb_csr_value, mtvec) + begin + if mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MTVEC then + mtvec_forwarded <= mem_csr_value; + elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MTVEC then + mtvec_forwarded <= wb_csr_value; + else + mtvec_forwarded <= mtvec; + end if; + end process mtvec_forward; + + mie_forward: process(mem_csr_write, mem_csr_addr, mem_csr_value, + wb_csr_write, wb_csr_addr, wb_csr_value, mie) + begin + if mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MIE then + mie_forwarded <= mem_csr_value; + elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MIE then + mie_forwarded <= wb_csr_value; + else + mie_forwarded <= mie; + end if; + end process mie_forward; + + exception_ctx_forward: process(mem_exception, wb_exception, mem_exception_context, wb_exception_context, + exception_cause, exception_addr, mem_csr_write, mem_csr_addr, mem_csr_value, + wb_csr_write, wb_csr_addr, wb_csr_value, ie_in, ie1_in) + begin + if mem_exception = '1' then + exception_context_forwarded <= mem_exception_context; + elsif mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MSTATUS then + exception_context_forwarded <= ( + ie => mem_csr_value(CSR_SR_IE), + ie1 => mem_csr_value(CSR_SR_IE1), + cause => exception_cause, + badaddr => exception_addr); + elsif wb_exception = '1' then + exception_context_forwarded <= wb_exception_context; + elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MSTATUS then + exception_context_forwarded <= ( + ie => wb_csr_value(CSR_SR_IE), + ie1 => wb_csr_value(CSR_SR_IE1), + cause => exception_cause, + badaddr => exception_addr); + else + exception_context_forwarded.ie <= ie_in; + exception_context_forwarded.ie1 <= ie1_in; + exception_context_forwarded.cause <= exception_cause; + exception_context_forwarded.badaddr <= exception_addr; + end if; + end process exception_ctx_forward; + + detect_load_hazard: process(mem_mem_op, mem_rd_addr, rs1_addr, rs2_addr, + alu_x_src, alu_y_src) + begin + if (mem_mem_op = MEMOP_TYPE_LOAD or mem_mem_op = MEMOP_TYPE_LOAD_UNSIGNED) and + ((alu_x_src = ALU_SRC_REG and mem_rd_addr = rs1_addr and rs1_addr /= b"00000") + or + (alu_y_src = ALU_SRC_REG and mem_rd_addr = rs2_addr and rs2_addr /= b"00000")) + then + hazard_detected <= '1'; + else + hazard_detected <= '0'; + end if; + end process detect_load_hazard; + + branch_comparator: entity work.pp_comparator + port map( + funct3 => funct3, + rs1 => rs1_forwarded, + rs2 => rs2_forwarded, + result => branch_condition + ); + + alu_instance: entity work.pp_alu + port map( + result => alu_result, + x => alu_x, + y => alu_y, + operation => alu_op + ); + + csr_alu_instance: entity work.pp_csr_alu + port map( + x => csr_value_forwarded, + y => rs1_forwarded, + result => csr_value_out, + immediate => rs1_addr, + use_immediate => csr_use_immediate, + write_mode => csr_write + ); + + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_fetch.vhd b/designs/encrypted_ip/pic/pp_fetch.vhd new file mode 100644 index 000000000..5da5fd735 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_fetch.vhd @@ -0,0 +1,89 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_constants.all; + +--! @brief Instruction fetch unit. +entity pp_fetch is + generic( + RESET_ADDRESS : std_logic_vector(31 downto 0) + ); + port( + clk : in std_logic; + reset : in std_logic; + + -- Instruction memory connections: + imem_address : out std_logic_vector(31 downto 0); + imem_data_in : in std_logic_vector(31 downto 0); + imem_req : out std_logic; + imem_ack : in std_logic; + + -- Control inputs: + stall : in std_logic; + flush : in std_logic; + branch : in std_logic; + exception : in std_logic; + + branch_target : in std_logic_vector(31 downto 0); + evec : in std_logic_vector(31 downto 0); + + -- Outputs to the instruction decode unit: + instruction_data : out std_logic_vector(31 downto 0); + instruction_address : out std_logic_vector(31 downto 0); + instruction_ready : out std_logic + ); +end entity pp_fetch; + +architecture behaviour of pp_fetch is + signal pc : std_logic_vector(31 downto 0); + signal pc_next : std_logic_vector(31 downto 0); + signal cancel_fetch : std_logic; +begin + + imem_address <= pc_next when cancel_fetch = '0' else pc; + + instruction_data <= imem_data_in; + instruction_ready <= imem_ack and (not stall) and (not cancel_fetch); + instruction_address <= pc; + + imem_req <= '1'; + + set_pc: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + pc <= RESET_ADDRESS; + cancel_fetch <= '0'; + else + if (exception = '1' or branch = '1') and imem_ack = '0' then + cancel_fetch <= '1'; + pc <= pc_next; + elsif cancel_fetch = '1' and imem_ack = '1' then + --pc <= pc_next; + cancel_fetch <= '0'; + else + pc <= pc_next; + end if; + end if; + end if; + end process set_pc; + + calc_next_pc: process(reset, stall, branch, exception, imem_ack, branch_target, evec, pc, cancel_fetch) + begin + if exception = '1' then + pc_next <= evec; + elsif branch = '1' then + pc_next <= branch_target; + elsif imem_ack = '1' and stall = '0' and cancel_fetch = '0' then + pc_next <= std_logic_vector(unsigned(pc) + 4); + else + pc_next <= pc; + end if; + end process calc_next_pc; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_icache.vhd b/designs/encrypted_ip/pic/pp_icache.vhd new file mode 100644 index 000000000..93c5a2305 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_icache.vhd @@ -0,0 +1,293 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_types.all; +use work.pp_utilities.all; + +--! @brief Simple read-only direct-mapped instruction cache. +entity pp_icache is + generic( + LINE_SIZE : natural := 4; --! Number of words per cache line + NUM_LINES : natural := 128 --! Number of lines in the cache + ); + port( + clk : in std_logic; + reset : in std_logic; + + -- Control interface: + cache_enable : in std_logic; + cache_flush : in std_logic; + cached_areas : in std_logic_vector(31 downto 0); + + -- Memory interface: + mem_address_in : in std_logic_vector(31 downto 0); + mem_data_in : in std_logic_vector(31 downto 0); + mem_data_out : out std_logic_vector(31 downto 0); + mem_data_size : in std_logic_vector( 1 downto 0); + mem_read_req : in std_logic; + mem_read_ack : out std_logic; + mem_write_req : in std_logic; + mem_write_ack : out std_logic; + + -- Wishbone interface: + wb_inputs : in wishbone_master_inputs; + wb_outputs : out wishbone_master_outputs + ); +end entity pp_icache; + +architecture behaviour of pp_icache is + + -- Counter types: + subtype line_counter_type is natural range 0 to NUM_LINES; + subtype word_counter_type is natural range 0 to LINE_SIZE; + + -- Cache line types: + subtype cache_line_type is std_logic_vector((LINE_SIZE * 32) - 1 downto 0); + type cache_line_word_array is array(0 to LINE_SIZE - 1) of std_logic_vector(31 downto 0); + type cache_line_array is array(0 to NUM_LINES - 1) of cache_line_type; + + -- Cache tag type: + subtype cache_tag_type is std_logic_vector(31 - log2(LINE_SIZE * 4) - log2(NUM_LINES) downto 0); + type cache_tag_array is array(0 to NUM_LINES - 1) of cache_tag_type; + + -- Cache memories: + signal cache_memory : cache_line_array; + signal tag_memory : cache_tag_array; + signal valid : std_logic_vector(NUM_LINES - 1 downto 0) := (others => '0'); + + attribute ram_style : string; + attribute ram_style of cache_memory: signal is "block"; + --attribute ram_style of tag_memory: signal is "block"; + + -- Cache controller signals: + type state_type is (IDLE, CACHE_READ_STALL, SINGLE_READ, SINGLE_WRITE, + LOAD_CACHELINE_START, LOAD_CACHELINE_WAIT_ACK, LOAD_CACHELINE_FINISH); + signal state : state_type := IDLE; + + -- Is the current input address in the cache? + signal input_address_cached : boolean; + + -- Input address components: + signal input_address_line : std_logic_vector(log2(NUM_LINES) - 1 downto 0); + signal input_address_word : std_logic_vector(log2(LINE_SIZE) - 1 downto 0); + signal input_address_tag : std_logic_vector(31 - log2(LINE_SIZE * 4) - log2(NUM_LINES) downto 0); + + -- Cacheline matching the current input address: + signal current_cache_line, cache_lookup : cache_line_type; + signal current_cache_line_words : cache_line_word_array; + signal current_tag : cache_tag_type; + + -- Base address to store a cacheline to: + signal cl_store_address : std_logic_vector(31 downto log2(LINE_SIZE * 4)); + -- Base address to load a cacheline from: + signal cl_load_address : std_logic_vector(31 downto log2(LINE_SIZE * 4)); + -- Cache line to load: + signal cl_current_line : line_counter_type; + -- Current word being loaded/stored: + signal cl_current_word : word_counter_type; + + -- Buffer for holding a cache line while loading: + signal load_buffer : cache_line_type; + signal load_buffer_tag : cache_tag_type; + + -- Causes a cache line to be stored in the cache memory: + signal store_cache_line : std_logic; + + -- Set when the current input address matches a cache line: + signal cache_hit : std_logic; + + -- For regular reads: + signal read_ack : std_logic; + signal read_data_out : std_logic_vector(31 downto 0); + + -- For regular writes: + signal write_ack : std_logic; + + -- Gets the amount to shift output data to the processor with for requests of size != 32 bits: + function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector) + return natural is + begin + case size is + when b"01" => + case address(1 downto 0) is + when b"00" => + return 0; + when b"01" => + return 8; + when b"10" => + return 16; + when b"11" => + return 24; + when others => + return 0; + end case; + when b"10" => + if address(1) = '0' then + return 0; + else + return 16; + end if; + when others => + return 0; + end case; + end function get_data_shift; + +begin + + --assert is_pow2(LINE_SIZE) report "Cache line size must be a power of 2!" severity FAILURE; + --assert is_pow2(NUM_LINES) report "Number of cache lines must be a power of 2!" severity FAILURE; + + -- Check if the current input address should be/is in the cache: + input_address_cached <= cached_areas(to_integer(unsigned(mem_address_in(31 downto 27)))) = '1'; + + mem_data_out <= current_cache_line_words(to_integer(unsigned(input_address_word))) when + input_address_cached and cache_enable = '1' and cache_flush = '0' + else read_data_out; + mem_read_ack <= (cache_hit and mem_read_req) + when state = IDLE and input_address_cached and cache_enable = '1' and cache_flush = '0' + else read_ack; + write_ack <= wb_inputs.ack when state = SINGLE_WRITE else '0'; + mem_write_ack <= write_ack; + + input_address_line <= mem_address_in(log2(LINE_SIZE * 4) + log2(NUM_LINES) - 1 downto log2(LINE_SIZE * 4)); + input_address_tag <= mem_address_in(31 downto log2(LINE_SIZE * 4) + log2(NUM_LINES)); + + find_word: process(clk) + begin + if rising_edge(clk) then + input_address_word <= mem_address_in(log2(LINE_SIZE * 4) - 1 downto 2); + end if; + end process find_word; + + cacheline_lookup: process(clk) + begin + if rising_edge(clk) then + if store_cache_line = '1' then + cache_memory(cl_current_line) <= load_buffer; + end if; + + current_cache_line <= cache_memory(to_integer(unsigned(input_address_line))); + end if; + end process cacheline_lookup; + + decompose_cache_line: for i in 0 to LINE_SIZE - 1 generate + current_cache_line_words(i) <= current_cache_line(32 * i + 31 downto 32 * i); + end generate decompose_cache_line; + + tag_lookup: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + cache_hit <= '0'; + else + if store_cache_line = '1' then + tag_memory(cl_current_line) <= load_buffer_tag; + end if; + + current_tag <= tag_memory(to_integer(unsigned(input_address_line))); + cache_hit <= valid(to_integer(unsigned(input_address_line))) and to_std_logic(tag_memory(to_integer(unsigned(input_address_line))) = input_address_tag); + end if; + end if; + end process tag_lookup; + + controller: process(clk) + variable current_word : std_logic_vector(31 downto 0); + begin + if rising_edge(clk) then + if reset = '1' then + state <= IDLE; + wb_outputs.cyc <= '0'; + wb_outputs.stb <= '0'; + store_cache_line <= '0'; + read_ack <= '0'; + valid <= (others => '0'); + read_data_out <= (others => '0'); + else + case state is + when IDLE => + read_ack <= '0'; + if cache_flush = '1' then + valid <= (others => '0'); + elsif input_address_cached and cache_enable = '1' then + if (mem_read_req = '1' or mem_write_req = '1') and cache_hit = '0' then + wb_outputs.adr <= mem_address_in(31 downto log2(LINE_SIZE * 4)) & (log2(LINE_SIZE * 4) - 1 downto 0 => '0'); + wb_outputs.cyc <= '1'; + wb_outputs.we <= '0'; + wb_outputs.sel <= (others => '1'); + load_buffer_tag <= input_address_tag; + cl_load_address <= mem_address_in(31 downto log2(LINE_SIZE * 4)); + cl_store_address <= input_address_tag & input_address_line; + cl_current_line <= to_integer(unsigned(input_address_line)); + cl_current_word <= 0; + state <= LOAD_CACHELINE_START; + end if; + else + if mem_read_req = '1' and read_ack = '0' then -- Do an uncached read + wb_outputs.adr <= mem_address_in; + wb_outputs.sel <= wb_get_data_sel(mem_data_size, mem_address_in); + wb_outputs.cyc <= '1'; + wb_outputs.stb <= '1'; + wb_outputs.we <= '0'; + state <= SINGLE_READ; + elsif mem_write_req = '1' then -- Do an uncached write + wb_outputs.adr <= mem_address_in; + wb_outputs.dat <= std_logic_vector(shift_left(unsigned(mem_data_in), + get_data_shift(mem_data_size, mem_address_in))); + wb_outputs.sel <= wb_get_data_sel(mem_data_size, mem_address_in); + wb_outputs.cyc <= '1'; + wb_outputs.stb <= '1'; + wb_outputs.we <= '1'; + state <= SINGLE_WRITE; + end if; + end if; + when CACHE_READ_STALL => + state <= IDLE; + when SINGLE_READ => + if wb_inputs.ack = '1' then + read_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat), + get_data_shift(mem_data_size, mem_address_in))); + wb_outputs.cyc <= '0'; + wb_outputs.stb <= '0'; + read_ack <= '1'; + state <= IDLE; + end if; + when SINGLE_WRITE => + if wb_inputs.ack = '1' then + wb_outputs.cyc <= '0'; + wb_outputs.stb <= '0'; + wb_outputs.we <= '0'; + state <= IDLE; + end if; + when LOAD_CACHELINE_START => + wb_outputs.stb <= '1'; + wb_outputs.we <= '0'; + wb_outputs.adr <= cl_load_address & std_logic_vector(to_unsigned(cl_current_word, log2(LINE_SIZE))) & b"00"; + state <= LOAD_CACHELINE_WAIT_ACK; + when LOAD_CACHELINE_WAIT_ACK => + if wb_inputs.ack = '1' then + wb_outputs.stb <= '0'; + load_buffer(cl_current_word * 32 + 31 downto cl_current_word * 32) <= wb_inputs.dat; + if natural(cl_current_word) = LINE_SIZE - 1 then + wb_outputs.cyc <= '0'; + store_cache_line <= '1'; + state <= LOAD_CACHELINE_FINISH; + else + cl_current_word <= cl_current_word + 1; + state <= LOAD_CACHELINE_START; + end if; + end if; + when LOAD_CACHELINE_FINISH => + store_cache_line <= '0'; + valid(cl_current_line) <= '1'; + state <= CACHE_READ_STALL; + end case; + end if; + end if; + end process controller; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_imm_decoder.vhd b/designs/encrypted_ip/pic/pp_imm_decoder.vhd new file mode 100644 index 000000000..33700e652 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_imm_decoder.vhd @@ -0,0 +1,35 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; + +--! @brief Module decoding immediate values from instruction words. +entity pp_imm_decoder is + port( + instruction : in std_logic_vector(31 downto 2); + immediate : out std_logic_vector(31 downto 0) + ); +end entity pp_imm_decoder; + +architecture behaviour of pp_imm_decoder is +begin + decode: process(instruction) + begin + case instruction(6 downto 2) is + when b"01101" | b"00101" => -- U type + immediate <= instruction(31 downto 12) & (11 downto 0 => '0'); + when b"11011" => -- UJ type + immediate <= (31 downto 20 => instruction(31)) & instruction(19 downto 12) & instruction(20) & instruction(30 downto 21) & '0'; + when b"11001" | b"00000" | b"00100" | b"11100"=> -- I type + immediate <= (31 downto 11 => instruction(31)) & instruction(30 downto 20); + when b"11000" => -- SB type + immediate <= (31 downto 12 => instruction(31)) & instruction(7) & instruction(30 downto 25) & instruction(11 downto 8) & '0'; + when b"01000" => -- S type + immediate <= (31 downto 11 => instruction(31)) & instruction(30 downto 25) & instruction(11 downto 7); + when others => + immediate <= (others => '0'); + end case; + end process decode; +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_memory.vhd b/designs/encrypted_ip/pic/pp_memory.vhd new file mode 100644 index 000000000..f40254ea4 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_memory.vhd @@ -0,0 +1,154 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_types.all; +use work.pp_csr.all; +use work.pp_utilities.all; + +entity pp_memory is + port( + clk : in std_logic; + reset : in std_logic; + stall : in std_logic; + + -- Data memory inputs: + dmem_read_ack : in std_logic; + dmem_write_ack : in std_logic; + dmem_data_in : in std_logic_vector(31 downto 0); + + -- Current PC value: + pc : in std_logic_vector(31 downto 0); + + -- Destination register signals: + rd_write_in : in std_logic; + rd_write_out : out std_logic; + rd_data_in : in std_logic_vector(31 downto 0); + rd_data_out : out std_logic_vector(31 downto 0); + rd_addr_in : in register_address; + rd_addr_out : out register_address; + + -- Control signals: + branch : in branch_type; + mem_op_in : in memory_operation_type; + mem_size_in : in memory_operation_size; + mem_op_out : out memory_operation_type; + + -- Whether the instruction should be counted: + count_instr_in : in std_logic; + count_instr_out : out std_logic; + + -- Exception signals: + exception_in : in std_logic; + exception_out : out std_logic; + exception_context_in : in csr_exception_context; + exception_context_out : out csr_exception_context; + + -- CSR signals: + csr_addr_in : in csr_address; + csr_addr_out : out csr_address; + csr_write_in : in csr_write_mode; + csr_write_out : out csr_write_mode; + csr_data_in : in std_logic_vector(31 downto 0); + csr_data_out : out std_logic_vector(31 downto 0) + ); +end entity pp_memory; + +architecture behaviour of pp_memory is + signal mem_op : memory_operation_type; + signal mem_size : memory_operation_size; + + signal rd_data : std_logic_vector(31 downto 0); +begin + + mem_op_out <= mem_op; + + pipeline_register: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + rd_write_out <= '0'; + csr_write_out <= CSR_WRITE_NONE; + count_instr_out <= '0'; + mem_op <= MEMOP_TYPE_NONE; + elsif stall = '0' then + mem_size <= mem_size_in; + rd_data <= rd_data_in; + rd_addr_out <= rd_addr_in; + + if exception_in = '1' then + mem_op <= MEMOP_TYPE_NONE; + rd_write_out <= '0'; + csr_write_out <= CSR_WRITE_REPLACE; + csr_addr_out <= CSR_MEPC; + csr_data_out <= pc; + count_instr_out <= '0'; + else + mem_op <= mem_op_in; + rd_write_out <= rd_write_in; + csr_write_out <= csr_write_in; + csr_addr_out <= csr_addr_in; + csr_data_out <= csr_data_in; + count_instr_out <= count_instr_in; + end if; + end if; + end if; + end process pipeline_register; + + update_exception_context: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + exception_out <= '0'; + else + exception_out <= exception_in or to_std_logic(branch = BRANCH_SRET); + + if exception_in = '1' then + exception_context_out.ie <= '0'; + exception_context_out.ie1 <= exception_context_in.ie; + exception_context_out.cause <= exception_context_in.cause; + exception_context_out.badaddr <= exception_context_in.badaddr; + elsif branch = BRANCH_SRET then + exception_context_out.ie <= exception_context_in.ie1; + exception_context_out.ie1 <= exception_context_in.ie; + exception_context_out.cause <= CSR_CAUSE_NONE; + exception_context_out.badaddr <= (others => '0'); + else + exception_context_out.ie <= exception_context_in.ie; + exception_context_out.ie1 <= exception_context_in.ie1; + exception_context_out.cause <= CSR_CAUSE_NONE; + exception_context_out.badaddr <= (others => '0'); + end if; + end if; + end if; + end process update_exception_context; + + rd_data_mux: process(rd_data, dmem_data_in, mem_op, mem_size) + begin + if mem_op = MEMOP_TYPE_LOAD or mem_op = MEMOP_TYPE_LOAD_UNSIGNED then + case mem_size is + when MEMOP_SIZE_BYTE => + if mem_op = MEMOP_TYPE_LOAD_UNSIGNED then + rd_data_out <= std_logic_vector(resize(unsigned(dmem_data_in(7 downto 0)), rd_data_out'length)); + else + rd_data_out <= std_logic_vector(resize(signed(dmem_data_in(7 downto 0)), rd_data_out'length)); + end if; + when MEMOP_SIZE_HALFWORD => + if mem_op = MEMOP_TYPE_LOAD_UNSIGNED then + rd_data_out <= std_logic_vector(resize(unsigned(dmem_data_in(15 downto 0)), rd_data_out'length)); + else + rd_data_out <= std_logic_vector(resize(signed(dmem_data_in(15 downto 0)), rd_data_out'length)); + end if; + when MEMOP_SIZE_WORD => + rd_data_out <= dmem_data_in; + end case; + else + rd_data_out <= rd_data; + end if; + end process rd_data_mux; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_register_file.vhd b/designs/encrypted_ip/pic/pp_register_file.vhd new file mode 100644 index 000000000..5ae749a07 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_register_file.vhd @@ -0,0 +1,55 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_types.all; +use work.pp_utilities.all; + +--! @brief 32-bit RISC-V register file. +entity pp_register_file is + port( + clk : in std_logic; + + -- Read port 1: + rs1_addr : in register_address; + rs1_data : out std_logic_vector(31 downto 0); + + -- Read port 2: + rs2_addr : in register_address; + rs2_data : out std_logic_vector(31 downto 0); + + -- Write port: + rd_addr : in register_address; + rd_data : in std_logic_vector(31 downto 0); + rd_write : in std_logic + ); +end entity pp_register_file; + +architecture behaviour of pp_register_file is + + --! Register array type. + type regfile_array is array(0 to 31) of std_logic_vector(31 downto 0); + + --! Register array. + --shared variable registers : regfile_array := (others => (others => '0')); -- Shared variable used to simulate write-first RAM + +begin + + regfile: process(clk) + variable registers : regfile_array := (others => (others => '0')); + begin + if rising_edge(clk) then + if rd_write = '1' and rd_addr /= b"00000" then + registers(to_integer(unsigned(rd_addr))) := rd_data; + end if; + + rs1_data <= registers(to_integer(unsigned(rs1_addr))); + rs2_data <= registers(to_integer(unsigned(rs2_addr))); + end if; + end process regfile; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_types.vhd b/designs/encrypted_ip/pic/pp_types.vhd new file mode 100644 index 000000000..373b10cbc --- /dev/null +++ b/designs/encrypted_ip/pic/pp_types.vhd @@ -0,0 +1,70 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; + +package pp_types is + + --! Type used for register addresses. + subtype register_address is std_logic_vector(4 downto 0); + + --! The available ALU operations. + type alu_operation is ( + ALU_AND, ALU_OR, ALU_XOR, + ALU_SLT, ALU_SLTU, + ALU_ADD, ALU_SUB, + ALU_SRL, ALU_SLL, ALU_SRA, + ALU_NOP, ALU_INVALID + ); + + --! Types of branches. + type branch_type is ( + BRANCH_NONE, BRANCH_JUMP, BRANCH_JUMP_INDIRECT, BRANCH_CONDITIONAL, BRANCH_SRET + ); + + --! Source of an ALU operand. + type alu_operand_source is ( + ALU_SRC_REG, ALU_SRC_IMM, ALU_SRC_SHAMT, ALU_SRC_PC, ALU_SRC_PC_NEXT, ALU_SRC_NULL, ALU_SRC_CSR + ); + + --! Type of memory operation: + type memory_operation_type is ( + MEMOP_TYPE_NONE, MEMOP_TYPE_INVALID, MEMOP_TYPE_LOAD, MEMOP_TYPE_LOAD_UNSIGNED, MEMOP_TYPE_STORE + ); + + -- Determines if a memory operation is a load: + function memop_is_load(input : in memory_operation_type) return boolean; + + --! Size of a memory operation: + type memory_operation_size is ( + MEMOP_SIZE_BYTE, MEMOP_SIZE_HALFWORD, MEMOP_SIZE_WORD + ); + + --! Wishbone master output signals: + type wishbone_master_outputs is record + adr : std_logic_vector(31 downto 0); + sel : std_logic_vector( 3 downto 0); + cyc : std_logic; + stb : std_logic; + we : std_logic; + dat : std_logic_vector(31 downto 0); + end record; + + --! Wishbone master input signals: + type wishbone_master_inputs is record + dat : std_logic_vector(31 downto 0); + ack : std_logic; + end record; + +end package pp_types; + +package body pp_types is + + function memop_is_load(input : in memory_operation_type) return boolean is + begin + return (input = MEMOP_TYPE_LOAD or input = MEMOP_TYPE_LOAD_UNSIGNED); + end function memop_is_load; + +end package body pp_types; diff --git a/designs/encrypted_ip/pic/pp_utilities.vhd b/designs/encrypted_ip/pic/pp_utilities.vhd new file mode 100644 index 000000000..138af2171 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_utilities.vhd @@ -0,0 +1,94 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; + +use work.pp_types.all; +use work.pp_constants.all; + +package pp_utilities is + + --! Converts a boolean to an std_logic. + function to_std_logic(input : in boolean) return std_logic; + + -- Checks if a number is 2^n: + function is_pow2(input : in natural) return boolean; + + --! Calculates log2 with integers. + function log2(input : in natural) return natural; + + -- Gets the value of the sel signals to the wishbone interconnect for the specified + -- operand size and address. + function wb_get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector) + return std_logic_vector; + +end package pp_utilities; + +package body pp_utilities is + + function to_std_logic(input : in boolean) return std_logic is + begin + if input then + return '1'; + else + return '0'; + end if; + end function to_std_logic; + + function is_pow2(input : in natural) return boolean is + variable c : natural := 1; + begin + for i in 0 to 30 loop -- FIXME: Simulator complains about 2^31 being out of range! + if input = i then + return true; + end if; + + c := c * 2; + end loop; + + return false; + end function is_pow2; + + function log2(input : in natural) return natural is + variable retval : natural := 0; + variable temp : natural := input; + begin + while temp > 1 loop + retval := retval + 1; + temp := temp / 2; + end loop; + + return retval; + end function log2; + + function wb_get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector) + return std_logic_vector is + begin + case size is + when b"01" => + case address(1 downto 0) is + when b"00" => + return b"0001"; + when b"01" => + return b"0010"; + when b"10" => + return b"0100"; + when b"11" => + return b"1000"; + when others => + return b"0001"; + end case; + when b"10" => + if address(1) = '0' then + return b"0011"; + else + return b"1100"; + end if; + when others => + return b"1111"; + end case; + end function wb_get_data_sel; + +end package body pp_utilities; diff --git a/designs/encrypted_ip/pic/pp_wb_adapter.vhd b/designs/encrypted_ip/pic/pp_wb_adapter.vhd new file mode 100644 index 000000000..56fba7256 --- /dev/null +++ b/designs/encrypted_ip/pic/pp_wb_adapter.vhd @@ -0,0 +1,126 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_types.all; +use work.pp_utilities.all; + +--! @brief Wishbone adapter, for connecting the processor to a Wishbone bus when not using caches. +entity pp_wb_adapter is + port( + clk : in std_logic; + reset : in std_logic; + + -- Processor data memory signals: + signal dmem_address : in std_logic_vector(31 downto 0); + signal dmem_data_in : in std_logic_vector(31 downto 0); -- Data in to the bus + signal dmem_data_out : out std_logic_vector(31 downto 0); -- Data out to the bus + signal dmem_data_size : in std_logic_vector( 1 downto 0); + signal dmem_read_req : in std_logic; + signal dmem_read_ack : out std_logic; + signal dmem_write_req : in std_logic; + signal dmem_write_ack : out std_logic; + + -- Wishbone interface: + wb_inputs : in wishbone_master_inputs; + wb_outputs : out wishbone_master_outputs + ); +end entity pp_wb_adapter; + +architecture behaviour of pp_wb_adapter is + + type states is (IDLE, READ_WAIT_ACK, WRITE_WAIT_ACK); + signal state : states; + + signal dmem_r_ack : std_logic; + + function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector) + return natural is + begin + case size is + when b"01" => + case address(1 downto 0) is + when b"00" => + return 0; + when b"01" => + return 8; + when b"10" => + return 16; + when b"11" => + return 24; + when others => + return 0; + end case; + when b"10" => + if address(1) = '0' then + return 0; + else + return 16; + end if; + when others => + return 0; + end case; + end function get_data_shift; + +begin + + dmem_write_ack <= '1' when state = WRITE_WAIT_ACK and wb_inputs.ack = '1' else '0'; + dmem_read_ack <= dmem_r_ack; + + wishbone: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + state <= IDLE; + wb_outputs.cyc <= '0'; + wb_outputs.stb <= '0'; + dmem_r_ack <= '0'; + else + case state is + when IDLE => + dmem_r_ack <= '0'; + + -- Prioritize requests from the data memory: + if dmem_write_req = '1' then + wb_outputs.adr <= dmem_address; + wb_outputs.dat <= std_logic_vector(shift_left(unsigned(dmem_data_in), + get_data_shift(dmem_data_size, dmem_address))); + wb_outputs.sel <= wb_get_data_sel(dmem_data_size, dmem_address); + wb_outputs.cyc <= '1'; + wb_outputs.stb <= '1'; + wb_outputs.we <= '1'; + state <= WRITE_WAIT_ACK; + elsif dmem_read_req = '1' then + wb_outputs.adr <= dmem_address; + wb_outputs.sel <= wb_get_data_sel(dmem_data_size, dmem_address); + wb_outputs.cyc <= '1'; + wb_outputs.stb <= '1'; + wb_outputs.we <= '0'; + state <= READ_WAIT_ACK; + end if; + when READ_WAIT_ACK => + if wb_inputs.ack = '1' then + dmem_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat), + get_data_shift(dmem_data_size, dmem_address))); + wb_outputs.cyc <= '0'; + wb_outputs.stb <= '0'; + dmem_r_ack <= '1'; + state <= IDLE; + end if; + when WRITE_WAIT_ACK => + if wb_inputs.ack = '1' then + wb_outputs.cyc <= '0'; + wb_outputs.stb <= '0'; + wb_outputs.we <= '0'; + state <= IDLE; + end if; + end case; + end if; + end if; + end process wishbone; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_wb_arbiter.vhd b/designs/encrypted_ip/pic/pp_wb_arbiter.vhd new file mode 100644 index 000000000..1a6e93ded --- /dev/null +++ b/designs/encrypted_ip/pic/pp_wb_arbiter.vhd @@ -0,0 +1,100 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; + +use work.pp_types.all; + +--! @brief Simple priority-based wishbone arbiter. +--! This module is used as an arbiter between the instruction and data caches. +entity pp_wb_arbiter is + port( + clk : in std_logic; + reset : in std_logic; + + -- Wishbone input 1: + m1_inputs : out wishbone_master_inputs; + m1_outputs : in wishbone_master_outputs; + + -- Wishbone input 2: + m2_inputs : out wishbone_master_inputs; + m2_outputs : in wishbone_master_outputs; + + -- Wishbone interface: + wb_adr_out : out std_logic_vector(31 downto 0); + wb_sel_out : out std_logic_vector( 3 downto 0); + wb_cyc_out : out std_logic; + wb_stb_out : out std_logic; + wb_we_out : out std_logic; + wb_dat_out : out std_logic_vector(31 downto 0); + wb_dat_in : in std_logic_vector(31 downto 0); + wb_ack_in : in std_logic + ); +end entity pp_wb_arbiter; + +architecture behaviour of pp_wb_arbiter is + + type state_type is (IDLE, M1_BUSY, M2_BUSY); + signal state : state_type := IDLE; + +begin + + m1_inputs <= (ack => wb_ack_in, dat => wb_dat_in) when state = M1_BUSY else (ack => '0', dat => (others => '0')); + m2_inputs <= (ack => wb_ack_in, dat => wb_dat_in) when state = M2_BUSY else (ack => '0', dat => (others => '0')); + + output_mux: process(state, m1_outputs, m2_outputs) + begin + case state is + when IDLE => + wb_adr_out <= (others => '0'); + wb_sel_out <= (others => '0'); + wb_dat_out <= (others => '0'); + wb_cyc_out <= '0'; + wb_stb_out <= '0'; + wb_we_out <= '0'; + when M1_BUSY => + wb_adr_out <= m1_outputs.adr; + wb_sel_out <= m1_outputs.sel; + wb_dat_out <= m1_outputs.dat; + wb_cyc_out <= m1_outputs.cyc; + wb_stb_out <= m1_outputs.stb; + wb_we_out <= m1_outputs.we; + when M2_BUSY => + wb_adr_out <= m2_outputs.adr; + wb_sel_out <= m2_outputs.sel; + wb_dat_out <= m2_outputs.dat; + wb_cyc_out <= m2_outputs.cyc; + wb_stb_out <= m2_outputs.stb; + wb_we_out <= m2_outputs.we; + end case; + end process output_mux; + + controller: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + state <= IDLE; + else + case state is + when IDLE => + if m1_outputs.cyc = '1' then + state <= M1_BUSY; + elsif m2_outputs.cyc = '1' then + state <= M2_BUSY; + end if; + when M1_BUSY => + if m1_outputs.cyc = '0' then + state <= IDLE; + end if; + when M2_BUSY => + if m2_outputs.cyc = '0' then + state <= IDLE; + end if; + end case; + end if; + end if; + end process controller; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pp_writeback.vhd b/designs/encrypted_ip/pic/pp_writeback.vhd new file mode 100644 index 000000000..447ce5d6e --- /dev/null +++ b/designs/encrypted_ip/pic/pp_writeback.vhd @@ -0,0 +1,71 @@ +-- The Potato Processor - A simple processor for FPGAs +-- (c) Kristian Klomsten Skordal 2014 - 2015 +-- Report bugs and issues on + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.pp_types.all; +use work.pp_csr.all; + +entity pp_writeback is + port( + clk : in std_logic; + reset : in std_logic; + + -- Count instruction: + count_instr_in : in std_logic; + count_instr_out : out std_logic; + + -- Exception signals: + exception_ctx_in : in csr_exception_context; + exception_in : in std_logic; + exception_ctx_out : out csr_exception_context; + exception_out : out std_logic; + + -- CSR signals: + csr_write_in : in csr_write_mode; + csr_write_out : out csr_write_mode; + csr_data_in : in std_logic_vector(31 downto 0); + csr_data_out : out std_logic_vector(31 downto 0); + csr_addr_in : in csr_address; + csr_addr_out : out csr_address; + + -- Destination register interface: + rd_addr_in : in register_address; + rd_addr_out : out register_address; + rd_write_in : in std_logic; + rd_write_out : out std_logic; + rd_data_in : in std_logic_vector(31 downto 0); + rd_data_out : out std_logic_vector(31 downto 0) + ); +end entity pp_writeback; + +architecture behaviour of pp_writeback is +begin + + pipeline_register: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + rd_write_out <= '0'; + exception_out <= '0'; + count_instr_out <= '0'; + else + count_instr_out <= count_instr_in; + rd_data_out <= rd_data_in; + rd_write_out <= rd_write_in; + rd_addr_out <= rd_addr_in; + + exception_out <= exception_in; + exception_ctx_out <= exception_ctx_in; + + csr_write_out <= csr_write_in; + csr_data_out <= csr_data_in; + csr_addr_out <= csr_addr_in; + end if; + end if; + end process pipeline_register; + +end architecture behaviour; diff --git a/designs/encrypted_ip/pic/pwm.v b/designs/encrypted_ip/pic/pwm.v new file mode 100644 index 000000000..cee7c8608 --- /dev/null +++ b/designs/encrypted_ip/pic/pwm.v @@ -0,0 +1,219 @@ +/*Author: Zhuxu + m99a1@yahoo.cn +Pulse Width Generators/timers with 16-bit main counter. +Period or timers target number is controlled by register [15:0]period. +Duty cycle is controlled by register [15:0]DC. +Clock used for pwm signal generation can be switched between Wishbone Bus clock and external clock. It is down clocked first. +o_pwm outputs pwm signal or timers interrupt. + +control register [7:0]ctrl: +bit 0: When set, external clock is chosen for pwm/timer. When cleared, wb clock is used for pwm/timer. +bit 1: When set, pwm is enabled. When cleared, timer is enabled. +bit 2: When set, pwm/timer starts. When cleared, pwm/timer stops. +bit 3: When set, timer runs continuously. When cleared, timer runs one time. +bit 4: When set, o_pwm enabled. +bit 5: timer interrupt bit When it is written with 0, interrupt request is cleared. +bit 6: When set, a 16-bit external signal i_DC is used as duty cycle. When cleared, register DC is used. +bit 7: When set, counter reset for pwm/timer, it's output and bit 5 will also be cleared. When changing from pwm mode to timer mode reset is needed before timer starts. +*/ +module pwm( +//wishbone slave interface +input i_wb_clk, +input i_wb_rst, +input i_wb_cyc, +input i_wb_stb, +input i_wb_we, +input [15:0]i_wb_adr, +input [15:0]i_wb_data, +output [15:0]o_wb_data, +output o_wb_ack, + +input i_extclk, +input [15:0]i_DC, +input i_valid_DC, +output o_pwm + +); + +////////////////////control logic//////////////////////////// +parameter adr_ctrl=0, + adr_divisor=2, + adr_period=4, + adr_DC=6; +reg [7:0]ctrl; +reg [15:0]period; +reg [15:0]DC; +reg [15:0]divisor; //for down clocking. If(divisor==0)To=Ti; else To=Ti/divisor; +integer i; +wire write; +assign write=i_wb_cyc&i_wb_stb&i_wb_we; +assign o_wb_ack=i_wb_stb; +always@(posedge i_wb_clk or posedge i_wb_rst) + if(i_wb_rst)begin + ctrl[4:0]<=0; + ctrl[7:6]<=0; + DC<=0; + period<=0; + divisor<=0; + end + else if(write)begin + case(i_wb_adr) + adr_ctrl:begin + ctrl[4:0]<=i_wb_data[4:0]; + ctrl[7:6]<=i_wb_data[7:6]; + end + adr_divisor:divisor<=i_wb_data; + adr_period:period<=i_wb_data; + adr_DC:DC<=i_wb_data; + endcase + end + +//interrupt bit control +wire pwm; +assign pwm=ctrl[1]; +reg [1:0]state; +reg clrint; //signal to pwm/timer logic +wire ack_clrint; //signal from pwm/timer logic +wire int; //signal from pwm/timer logic +always@(posedge i_wb_clk or posedge i_wb_rst) + if(i_wb_rst)begin + ctrl[5]<=0; + state<=0; + clrint<=0; + end + else begin + case(state) + 1:begin + if(write)begin + if(i_wb_data[7])begin + ctrl[5]<=0; + state<=0; + end + else if(!i_wb_data[5])begin + ctrl[5]<=0; + if(!pwm)begin + clrint<=1; + state<=2; + end + else state<=0; + end + end + end + 2:if(ack_clrint)begin + clrint<=0; + state<=0; + end + default:begin + if(!pwm)ctrl[5]<=int; + if(int)state<=1; + end + endcase + end + + +/////////////////////////////////////////////////////////// + +//////down clocking for pwm/timer/////////////////// +wire clk_source; +wire eclk,oclk; +assign clk_source=ctrl[0]?i_extclk:i_wb_clk; +down_clocking_even down_clocking_even_0( +clk_source, +(!i_wb_rst), +{1'b0,divisor[15:1]}, +eclk +); +down_clocking_odd down_clocking_odd_0( +clk_source, +(!i_wb_rst), +{1'b0,divisor[15:1]}, +oclk +); +wire clk; +assign clk=divisor[0]?oclk:eclk; +/////////////////////////////////////////////////////// + +/////////////////main counter ////////////////////////// +reg [15:0]ct; +reg pts; //pwm signal or timer interrupt signal +reg [15:0]extDC; +wire [15:0]DC_1; +assign DC_1=ctrl[6]?extDC:DC; //external or internal duty cycle toggle +wire [15:0]period_1; +assign period_1=(period==0)?0:(period-1); +reg switch_ack_clrint; +wire state_timer; +assign state_timer=ctrl[3]; +wire rst_ct; +assign rst_ct=i_wb_rst|ctrl[7]; +assign int=pwm?0:pts; +assign ack_clrint=switch_ack_clrint?clrint:0; +always@(posedge clk or posedge rst_ct) + if(rst_ct)begin + pts<=0; + ct<=0; + switch_ack_clrint<=0; + extDC<=0; + end + else begin + if(i_valid_DC)extDC<=i_DC; + if(switch_ack_clrint&&(!clrint))switch_ack_clrint<=0; + if(ctrl[2])begin + case(pwm) + 1:begin + if(ct>=period_1)ct<=0; + else ct<=ct+1; + + if(ct=period_1)begin + if(clrint)begin + pts<=0; + ct<=0; + end + else pts<=1; + + end + else ct<=ct+1; + end + 1:begin + if(ct>=period_1)begin + pts<=1; + ct<=0; + end + else begin + if(clrint)begin + switch_ack_clrint<=1; + pts<=0; + end + ct<=ct+1; + end + end + endcase + end + endcase + end + else if(clrint)begin + switch_ack_clrint<=1; + if(!pwm)begin + pts<=0; + ct<=0; + end + end + end +////////////////////////////////////////////////////////// + +assign o_pwm=ctrl[4]?pts:0; +assign o_wb_data= i_wb_adr==adr_ctrl?{8'h0,ctrl}: + i_wb_adr==adr_divisor?divisor: + i_wb_adr==adr_period?period: + i_wb_adr==adr_DC?DC:0; + + +endmodule \ No newline at end of file diff --git a/designs/encrypted_ip/pic/quadratic_func.vhd b/designs/encrypted_ip/pic/quadratic_func.vhd new file mode 100644 index 000000000..a23620c74 --- /dev/null +++ b/designs/encrypted_ip/pic/quadratic_func.vhd @@ -0,0 +1,203 @@ +---------------------------------------------------------------------- +-- -- +-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE -- +-- -- +---------------------------------------------------------------------- +-- -- +-- Filename : quadratic_func.vhd -- +-- -- +-- Author : Simon Doherty -- +-- Senior Design Consultant -- +-- www.zipcores.com -- +-- -- +-- Date last modified : 16.02.2009 -- +-- -- +-- Description : Quadratic function computes the -- +-- relation y = ax^2 + bx + c -- +-- -- +---------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_signed.all; + + +entity quadratic_func is + +generic ( fw : integer := 6 ); -- width of fraction in range 0 to 8 + +port ( + + -- system clock + clk : in std_logic; + + -- clock enable + en : in std_logic; + + -- Coefficients as 8-bit signed fraction + coeff_a : in std_logic_vector(7 downto 0); + coeff_b : in std_logic_vector(7 downto 0); + coeff_c : in std_logic_vector(7 downto 0); + + -- Input as a 8-bit signed fraction + x_in : in std_logic_vector(7 downto 0); + + -- Output as a 24-bit signed fraction + y_out : out std_logic_vector(23 downto 0)); + +end entity; + + +architecture rtl of quadratic_func is + + +signal zeros : std_logic_vector(23 downto 0); + +signal coeff_a_reg : std_logic_vector(7 downto 0); +signal coeff_b_reg : std_logic_vector(7 downto 0); +signal coeff_c_reg : std_logic_vector(7 downto 0); +signal coeff_c_del : std_logic_vector(7 downto 0); + +signal x2 : std_logic_vector(15 downto 0); +signal x2_a : std_logic_vector(23 downto 0); +signal x2_a_norm : std_logic_vector(23 downto 0); + +signal x1 : std_logic_vector(7 downto 0); +signal x1_del : std_logic_vector(7 downto 0); +signal x1_b : std_logic_vector(15 downto 0); +signal x1_b_norm : std_logic_vector(15 + fw downto 0); + +signal x0_c_norm : std_logic_vector(7 + fw*2 downto 0); + +signal sum : std_logic_vector(23 downto 0); +signal sum_reg : std_logic_vector(23 downto 0); + + +begin + + +----------------- +-- For padding -- +----------------- + +zeros <= (others => '0'); + +------------------------------------------------------- +-- Rename input x term to maintain naming convention -- +------------------------------------------------------- + +x1 <= x_in; + +------------------------------- +-- Pipeline the coefficients -- +------------------------------- + +coeff_regs: process (clk) +begin + if clk'event and clk = '1' then + if en = '1' then + coeff_a_reg <= coeff_a; + coeff_b_reg <= coeff_b; + coeff_c_reg <= coeff_c; + end if; + end if; +end process coeff_regs; + +----------------------------------------- +-- Delays to compenstate for latencies -- +----------------------------------------- + +pipe_reg_del: process (clk) +begin + if clk'event and clk = '1' then + if en = '1' then + -- x term requires 1 cycle of delay + x1_del <= x1; + -- coeff c requires 1 cycle of delay + coeff_c_del <= coeff_c_reg; + end if; + end if; +end process pipe_reg_del; + +-------------- +-- x^2 term -- +-------------- + +pipe_reg_x2: process (clk) +begin + if clk'event and clk = '1' then + if en = '1' then + x2 <= x1 * x1; -- 8*8 = 16-bits + end if; + end if; +end process pipe_reg_x2; + +------------------- +-- x^2 * coeff_a -- +------------------- + +pipe_reg_x2_a: process (clk) +begin + if clk'event and clk = '1' then + if en = '1' then + x2_a <= x2 * coeff_a_reg; -- 16*8 = 24-bits + end if; + end if; +end process pipe_reg_x2_a; + +----------------- +-- x * coeff_b -- +----------------- + +pipe_reg_x1_b: process (clk) +begin + if clk'event and clk = '1' then + if en = '1' then + x1_b <= x1_del * coeff_b_reg; -- 8*8 = 16-bits + end if; + end if; +end process pipe_reg_x1_b; + +---------------------------------------------- +-- 24-bits + 16-bits + 8-bits -- +-- -- +-- Need to normalize the x1 and c terms so -- +-- that the binary points line up -- +-- -- +-- x1 term << fw, c term << fw*2 -- +---------------------------------------------- + +x2_a_norm <= x2_a; +x1_b_norm <= x1_b & zeros(fw - 1 downto 0); +x0_c_norm <= coeff_c_del & zeros(fw*2 - 1 downto 0); + +------------------------------------------------------------ +-- (x^2 * coeff_a) + (x * coeff_b) + coeff_c (24-bit add) -- +------------------------------------------------------------ + +sum <= x2_a_norm + x1_b_norm + x0_c_norm; + +----------------------------- +-- Register the output sum -- +----------------------------- + +out_reg: process (clk) +begin + if clk'event and clk = '1' then + if en = '1' then + sum_reg <= sum; + end if; + end if; +end process out_reg; + +--------------------------------------------- +-- 24-bit output -- +-- Integer part of result is y_out >> fw*3 -- +--------------------------------------------- + +y_out <= sum_reg; + + +end rtl; \ No newline at end of file diff --git a/designs/encrypted_ip/pic/top.v b/designs/encrypted_ip/pic/top.v new file mode 100644 index 000000000..bf737fe2f --- /dev/null +++ b/designs/encrypted_ip/pic/top.v @@ -0,0 +1,166 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11/09/2017 08:43:26 PM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module top( + input clk, + input reset, + input [15:0] sw, + input [4:0] btn, // Not used + output [15:0] led, + output [6:0] seg, // Not used + output dp, // Not used + output [7:0] an // Not used + ); + + wire [7:0] sw2, JA, JB, JC, JD; + wire btnCpuReset; + assign btnCpuReset = reset; + assign sw2 = sw[7:0]; + assign JA = sw[15:8]; + assign JB = {btn, sw[15:13]}; + assign JC = {btn ^ sw[12:8], btn[2:0] & sw[2:0]}; + assign JD = {sw[15:8] ^ sw[7:0]}; + + wire trdy, devsel, par, stop, inta, serr, perr; // c + wire [31:0] ad, wb_address, wb_dat_o; // c + wire [3:0] led_out, wb_sel_o; //c + wire wb_cyc_o, wb_stb_o, wb_wr_o, wb_reset_o, wb_clk_o, wb_req; // c + + wire [7:0] DataBus; // c + wire INTR_O; // c + + wire [31:0] tohost_data; // c + wire tohost_updated; // c + + wire [31:0] p_wb_adr_out, p_dat_out; // c + wire [3:0] p_wb_sel_out; // c + wire p_wb_cyc_out, p_wb_stb_out, p_wb_we_out; // c + + wire [15:0] pwm_o_wb_data; + wire pwm_o_wb_ack, pwm_o_pwm; + + wire [23:0] y_out; + + assign led[0] = trdy ^ devsel ^ par ^ stop ^ inta ^ serr ^ perr; + assign led[1] = ^led_out ^ wb_sel_o; + assign led[2] = wb_cyc_o ^ wb_stb_o ^ wb_wr_o ^ wb_reset_o ^ wb_clk_o ^ wb_req; + assign led[4] = ^p_wb_adr_out; + assign led[5] = ^p_dat_out; + assign led[6] = p_wb_cyc_out ^ p_wb_stb_out ^ p_wb_we_out; + assign led[7] = ^pwm_o_wb_data; + assign led[8] = pwm_o_wb_ack ^ pwm_o_pwm; + assign led[9] = ^y_out; + assign led[10] = INTR_O; + + + pci_mini pci_mini_0( + .reset(btnCpuReset), + .clk(clk), + .frame(p_wb_stb_out), + .irdy(tohost_updated), + .trdy(trdy), + .devsel(devsel), + .idsel(p_wb_cyc_out), + .ad(ad), + .cbe(p_wb_sel_out), // [3:0] + .par(par), + .stop(stop), + .inta(inta), + .serr(serr), + .perr(perr), + .led_out(led_out), + .wb_address(wb_address), + .wb_dat_o(wb_dat_o), + .wb_dat_i(pwm_o_pwm), + .wb_sel_o(wb_sel_o), + .wb_cyc_o(wb_cyc_o), + .wb_stb_o(wb_stb_o), + .wb_wr_o(wb_wr_o), + .wb_reset_o(wb_reset_o), + .wb_clk_o(wb_clk_o), + .wb_ack_i(pwm_o_pwm), + .wb_irq(pwm_o_wb_ack), + .wb_req(wb_req), + .wb_gnt(p_wb_we_out), + .wb_req_other(INTR_O) + ); + + + pic pic_0( + .CLK_I(clk), + .RST_I(btnCpuReset), + .IR(JA), + .DataBus(DataBus), + .INTR_O(INTR_O), + .INTA_I(inta) + ); + + + + potato potato_0( + .clk(clk), + .timer_clk(clk), + .reset(btnCpuReset), + .irq(pwm_o_wb_data[7:0]), // [7:0] + .fromhost_data(wb_address), // [31:0] + .fromhost_updated(^y_out), // 1 + .tohost_data(tohost_data), + .tohost_updated(tohost_updated), + .wb_adr_out(p_wb_adr_out), + .wb_sel_out(p_wb_sel_out), + .wb_cyc_out(p_wb_cyc_out), + .wb_stb_out(p_wb_stb_out), + .wb_we_out(p_wb_we_out), + .wb_dat_out(p_dat_out), + .wb_dat_in(wb_dat_o), // [31:0] + .wb_ack_in(sw2[0]) + ); + + + pwm pwm_0( + .i_wb_clk(clk), + .i_wb_rst(btnCpuReset), + .i_wb_cyc(sw2[0]), + .i_wb_stb(sw2[1]), + .i_wb_we(sw2[2]), + .i_wb_adr(tohost_data[15:0]), // [15:0] + .i_wb_data(tohost_data[31:16]), // [15:0] + .o_wb_data(pwm_o_wb_data), + .o_wb_ack(pwm_o_wb_ack), + .i_extclk(clk), + .i_DC(wb_dat_o[15:0]), // [15:0] + .i_valid_DC(sw2[3]), + .o_pwm(pwm_o_pwm) + ); + + + quadratic_func quadratic_func_0( + .clk(clk), + .en(btnCpuReset), + .coeff_a(ad[7:0]), // [7:0] + .coeff_b(ad[15:8]), // [7:0] + .coeff_c(ad[23:16]), // [7:0] + .x_in(ad[31:24]), // [7:0] + .y_out(y_out) + ); + +endmodule diff --git a/designs/encrypted_ip/simon_core/Simon_bit_serial_datapath_FPGA.v b/designs/encrypted_ip/simon_core/Simon_bit_serial_datapath_FPGA.v new file mode 100644 index 000000000..e48564b3a --- /dev/null +++ b/designs/encrypted_ip/simon_core/Simon_bit_serial_datapath_FPGA.v @@ -0,0 +1,225 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Team: Virginia Tech Secure Embedded Systems (SES) Lab +// Implementer: Ege Gulcan +// +// Create Date: 17:21:26 11/13/2013 +// Design Name: +// Module Name: simon_datapath_shiftreg +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module simon_datapath_shiftreg(clk,data_in,data_rdy,key_in,cipher_out,round_counter,bit_counter); + +input clk,data_in,key_in; +input [1:0] data_rdy; +input round_counter; +output cipher_out; +output [5:0] bit_counter; + +reg [55:0] shifter1; +reg [63:0] shifter2; +reg shift_in1,shift_in2; +wire shift_out1,shift_out2; +reg shifter_enable1,shifter_enable2; + +reg fifo_ff63,fifo_ff62,fifo_ff61,fifo_ff60,fifo_ff59,fifo_ff58,fifo_ff57,fifo_ff56; +reg lut_ff63,lut_ff62,lut_ff61,lut_ff60,lut_ff59,lut_ff58,lut_ff57,lut_ff56; + +reg lut_ff_input,fifo_ff_input; +reg lut_rol1,lut_rol2,lut_rol8; +reg s1,s4,s5,s6,s7; +reg [1:0] s3; +reg [5:0] bit_counter; +wire lut_out; + + + +// Shift Register1 FIFO 56x1 Begin +// 56x1 Shift register to store the upper word +always @(posedge clk) +begin + if(shifter_enable1) + begin + shifter1 <= {shift_in1, shifter1[55:1]}; + end +end + +assign shift_out1 = shifter1[0]; +// Shift Register1 End + +// Shift Register2 FIFO 64x1 Begin +// 64x1 Shift register to store the lower word +always @(posedge clk) +begin + if(shifter_enable2) + begin + shifter2 <= {shift_in2, shifter2[63:1]}; + end +end + +assign shift_out2 = shifter2[0]; +// Shift Register2 End + + +// 8 Flip-Flops to store the most significant 8 bits of the upper word at even rounds +// Denoted as Shift Register Up (SRU) in Figure 5 +always@(posedge clk) +begin + if(shifter_enable1) + begin + fifo_ff63 <= fifo_ff_input; + fifo_ff62 <= fifo_ff63; + fifo_ff61 <= fifo_ff62; + fifo_ff60 <= fifo_ff61; + fifo_ff59 <= fifo_ff60; + fifo_ff58 <= fifo_ff59; + fifo_ff57 <= fifo_ff58; + fifo_ff56 <= fifo_ff57; + end +end + +// 8 Flip-Flops to store the most significant 8 bits of the upper word at odd rounds +// Denoted as Shift Register Down (SRD) in Figure 5 +always@(posedge clk) +begin + lut_ff63 <= lut_ff_input; + lut_ff62 <= lut_ff63; + lut_ff61 <= lut_ff62; + lut_ff60 <= lut_ff61; + lut_ff59 <= lut_ff60; + lut_ff58 <= lut_ff59; + lut_ff57 <= lut_ff58; + lut_ff56 <= lut_ff57; +end + +// FIFO 64x1 Input MUX +// Input of the lower FIFO is always the output of the upper FIFO +always@(*) +begin + shift_in2 = shift_out1; +end + +// FIFO 56x1 Input MUX +// Input of the upper FIFO depends on the select line S1 +always@(*) +begin + if(s1==0) + shift_in1 = lut_ff56; + else + shift_in1 = fifo_ff56; +end + +// FIFO FF Input MUX +// The input of FIFO_FF can be the input plaintext, output of 56x1 FIFO or the output of LUT +always@(*) +begin + if(s3==0) + fifo_ff_input = data_in; + else if(s3==1) + fifo_ff_input = shift_out1; + else if(s3==2) + fifo_ff_input = lut_out; + else + fifo_ff_input = 1'bx; // Debugging +end + +// LUT FF Input MUX +// The input of the LUT_FF is either the output of 56x1 FIFO or the output of LUT +always@(*) +begin + if(s5==0) + lut_ff_input = shift_out1; + else + lut_ff_input = lut_out; +end + +// LUT Input MUX +always@(*) +begin + if(s7==0) + lut_rol1 = fifo_ff63; + else + lut_rol1 = lut_ff63; + + if(s4==0) + lut_rol2 = fifo_ff62; + else + lut_rol2 = lut_ff62; + + if(s6==0) + lut_rol8 = fifo_ff56; + else + lut_rol8 = lut_ff56; +end + +//Selection MUX +always@(*) +begin + // For the first 8 bits of each even round OR for all the bits after the first 8 bits in odd rounds OR loading the plaintext + if((round_counter==0 && bit_counter<8)||(round_counter==1 && bit_counter>7)||(data_rdy==1)) + s1 = 1; + else + s1 = 0; + + if(data_rdy==1) // Loading plaintext + s3 = 0; + else if(round_counter==0) // Even rounds + s3 = 1; + else if(round_counter==1) // Odd rounds + s3 = 2; + else + s3 = 1'bx; // For debugging + + if(round_counter==0) // Even rounds + s6 = 0; + else + s6 = 1; + + s4 = s6; + s7 = s6; + s5 = ~s6; +end + +// SHIFTER ENABLES +// Two shift registers are enabled when the plaintext is being loaded (1) or when the block cipher is running (3) +always@(*) +begin + if(data_rdy==1 || data_rdy==3) + begin + shifter_enable1 = 1; + shifter_enable2 = 1; + end + else + begin + shifter_enable1 = 0; + shifter_enable2 = 0; + end +end + +// The bit_counter value is incremented in each clock cycle when the block cipher is running +always@(posedge clk) +begin + if(data_rdy==0) + bit_counter <= 0; + else if(data_rdy==3) + bit_counter <= bit_counter + 1; + else + bit_counter <= bit_counter; +end + +// The new computed value +assign lut_out = (lut_rol1 & lut_rol8) ^ shift_out2 ^ lut_rol2 ^ key_in; + +// The global output that gives the ciphertext value +assign cipher_out = lut_out; +endmodule diff --git a/designs/encrypted_ip/simon_core/Simon_bit_serial_key_expansion_FPGA.v b/designs/encrypted_ip/simon_core/Simon_bit_serial_key_expansion_FPGA.v new file mode 100644 index 000000000..12b906b47 --- /dev/null +++ b/designs/encrypted_ip/simon_core/Simon_bit_serial_key_expansion_FPGA.v @@ -0,0 +1,241 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Team: Virginia Tech Secure Embedded Systems (SES) Lab +// Implementer: Ege Gulcan +// +// Create Date: 16:55:06 11/12/2013 +// Design Name: +// Module Name: simon_key_expansion_shiftreg +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module simon_key_expansion_shiftreg(clk,data_in,key_out,data_rdy,bit_counter,round_counter_out); + +input clk; +input data_in; +input [1:0] data_rdy; +input [5:0] bit_counter; +output key_out; +output round_counter_out; + + +reg [59:0] shifter1; +reg [63:0] shifter2; +reg shift_in1,shift_in2; +wire shift_out1,shift_out2; +reg shifter_enable1,shifter_enable2; + +reg lut_ff_enable,fifo_ff_enable; +wire lut_out; +reg lut_in3; +reg s2,s3; +reg [1:0] s1; +reg [6:0] round_counter; +reg z_value; + +reg fifo_ff0,fifo_ff1,fifo_ff2,fifo_ff3; + +//(* shreg_extract = "no" *) +reg lut_ff0,lut_ff1,lut_ff2,lut_ff3; +//Constant value Z ROM +reg [0:67] Z = 68'b10101111011100000011010010011000101000010001111110010110110011101011; +reg c; + + +///////////////////////////////////////// +//// BEGIN CODE //////////////////////// +/////////////////////////////////////// + +// Least bit of the round counter is sent to the datapath to check if it is even or odd +assign round_counter_out = round_counter[0]; + +// Shift Register1 FIFO 60x1 Begin +// 60x1 shift register storing the 60 most significant bits of the upper word of the key +always @(posedge clk) +begin + if(shifter_enable1) + begin + shifter1 <= {shift_in1, shifter1[59:1]}; + end +end + +assign shift_out1 = shifter1[0]; +// Shift Register1 End + +// Shift Register2 FIFO 64x1 Begin +// 64x1 shift register storing the lower word of the key +always @(posedge clk) +begin + if(shifter_enable2) + begin + shifter2 <= {shift_in2, shifter2[63:1]}; + end +end + +assign shift_out2 = shifter2[0]; +// Shift Register2 End + +// 4 flip-flops storing the least significant 4 bits of the upper word in the first round +always @(posedge clk) +begin + if(fifo_ff_enable) + begin + fifo_ff3 <= shift_out1; + fifo_ff2 <= fifo_ff3; + fifo_ff1 <= fifo_ff2; + fifo_ff0 <= fifo_ff1; + end +end + +// 4 flip-flops storing the least significant 4 bits of the upper word after the first round +always@(posedge clk) +begin + if(lut_ff_enable) + begin + lut_ff3 <= lut_out; + lut_ff2 <= lut_ff3; + lut_ff1 <= lut_ff2; + lut_ff0 <= lut_ff1; + end +end + +//FIFO 64x1 Input MUX +always@(*) +begin + if(data_rdy==2) + shift_in2 = fifo_ff0; + else if(data_rdy==3 && (round_counter<1 || bit_counter>3)) + shift_in2 = fifo_ff0; + else if(data_rdy==3 && bit_counter<4 && round_counter>0) + shift_in2 = lut_ff0; + else + shift_in2 = 1'bx; +end + +//LUT >>3 Input MUX +always@(*) +begin + if(s2==0) + lut_in3 = fifo_ff3; + else + lut_in3 = lut_ff3; +end + +//FIFO 60x1 Input MUX +always@(*) +begin + if(s1==0) + shift_in1 = fifo_ff0; + else if(s1==1) + shift_in1 = data_in; + else if(s1==2) + shift_in1 = lut_out; + else if(s1==3) + shift_in1 = lut_ff0; + else + shift_in1 = 1'bx; +end + +//S2 MUX +always@(*) +begin + if(bit_counter==0 && round_counter!=0) + s2 = 1; + else + s2 = 0; +end + +//S1 MUX +always@(*) +begin + if(data_rdy==2) + s1 = 1; + else if(data_rdy==3 && bit_counter<4 && round_counter==0) + s1 = 0; + else if(data_rdy==3 && bit_counter<4 && round_counter>0) + s1 = 3; + else + s1 = 2; +end + +// LUT FF ENABLE MUX +// LUT FFs are used only at the first four clock cycles of each round +always@(*) +begin + if(data_rdy==3 && bit_counter<4) + lut_ff_enable = 1; + else + lut_ff_enable = 0; +end + +//FIFO FF ENABLE MUX +always@(*) +begin + if(data_rdy==2 || data_rdy==3) + fifo_ff_enable = 1; + else + fifo_ff_enable = 0; +end + +//SHIFTER ENABLES +// Shifters are enabled when the key is loaded or block cipher is running +always@(*) +begin + if(data_rdy==2 || data_rdy==3) + shifter_enable1 = 1; + else + shifter_enable1 = 0; + + if(data_rdy==2 || data_rdy==3) + shifter_enable2 = 1; + else + shifter_enable2 = 0; + +end + +//Round Counter +always@(posedge clk) +begin + if(data_rdy==3 && bit_counter==63) + round_counter <= round_counter + 1; + else if(data_rdy==0) + round_counter <= 0; + else + round_counter <= round_counter; +end + +// The necessary bit of the constant Z is selected by the round counter +always @(*) +begin + if(bit_counter==0) + z_value = Z[round_counter]; + else + z_value = 0; +end + +// The value of c is 1 at the first two cycles of each round only +always @(*) +begin + if(bit_counter==0 || bit_counter==1) + c = 0; + else + c = 1; +end + +// New computed key bit +assign lut_out = shift_out2 ^ lut_in3 ^ shift_out1 ^ z_value ^ c; + +// Output key bit that is connected to the datapath +assign key_out = shift_out2; + +endmodule diff --git a/designs/encrypted_ip/simon_core/ac_behave.vhd b/designs/encrypted_ip/simon_core/ac_behave.vhd new file mode 100644 index 000000000..2e5cda48b --- /dev/null +++ b/designs/encrypted_ip/simon_core/ac_behave.vhd @@ -0,0 +1,35 @@ +--! @file +--! @brief Accumulator (AC) +--! @details is a buffer register that stores intermediate amswers during a computer run. +--! It is connected directly to the W-bus (3-state) and Adder-Subtractor/ALU (2-state). + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY AC IS + port (d : in std_logic_vector(7 downto 0); --! 8-bit input data to AC from W-bus + q_alu : out std_logic_vector(7 downto 0); --! 8-bit output data to AC from W-bus + q_data : out std_logic_vector(7 downto 0); --! 8-bit output data to Adder-Subtractor block + clk : in std_logic; --! Rising edge clock + ea : in std_logic; --! Active high enable AC control input signal + clr : in std_logic; --! Active high asynchronous clear + la : in std_logic); --! Active low load AC control input signal +END AC ; + +ARCHITECTURE behave OF AC IS +BEGIN +process (clr,clk,la,ea,d) +begin + if clr = '1' then + q_alu <= (others => '0'); + q_data <= (others => '0'); + elsif rising_edge(clk) then + if la = '0' then + q_alu <= d; q_data <= d; + end if; + end if; +end process; +END behave; + diff --git a/designs/encrypted_ip/simon_core/alu_behave.vhd b/designs/encrypted_ip/simon_core/alu_behave.vhd new file mode 100644 index 000000000..c9866b4a7 --- /dev/null +++ b/designs/encrypted_ip/simon_core/alu_behave.vhd @@ -0,0 +1,37 @@ +--! @file +--! @brief Arithmetic Logic Unit (ALU) +--! @details It just perform addition and subtraction operation. \n +--! It is asynchronous block. \n + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY ALU IS +port (A : in std_logic_vector(7 downto 0); --! ALU A input 8-bit from AC + B : in std_logic_vector(7 downto 0); --! ALU B input 8-bit from B-register + S : out std_logic_vector(7 downto 0); --! ALU output 8-bit to W-bus + Su : in std_logic; --! Low Add, High Sub + Eu : in std_logic); --! Active low enable ALU (tri-state) +END ALU ; + +ARCHITECTURE behave OF ALU IS +signal sum,sub : std_logic_vector(7 downto 0); +BEGIN +sum <= (unsigned(A) + unsigned(B)); +sub <= (unsigned(A) - unsigned(B)); +process (a,b,su,eu) +begin + if Eu = '0' then + S <= (s'range => 'Z'); + else + if Su = '0' then + S <= sum; + else + S <= sub; + end if; + end if; +end process; +END behave; + diff --git a/designs/encrypted_ip/simon_core/b_reg_behave.vhd b/designs/encrypted_ip/simon_core/b_reg_behave.vhd new file mode 100644 index 000000000..eb8cbf579 --- /dev/null +++ b/designs/encrypted_ip/simon_core/b_reg_behave.vhd @@ -0,0 +1,31 @@ +--! @file +--! @brief B register (B) +--! @details It is another buffer register. It is used in arithmetic operations. \n +--! Its input connected to the W-bus, it transfer the data in when Lb is low. \n +--! Its output connected to ALU B input. + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY B_Reg IS +port (d : in std_logic_vector(7 downto 0); --! 8-bit B input from W-bus + q : out std_logic_vector(7 downto 0); --! 8-bit B output to Adder-Subtractor + clk : in std_logic; --! Rising edge clock + clr : in std_logic; --! Active high asynchronous clear + lb : in std_logic); --! Active low load B content into output +END B_Reg ; + +ARCHITECTURE behave OF B_Reg IS +BEGIN +process (clr,clk,lb) +begin + if clr = '1' then + q <= (others => '0'); + elsif lb = '0' then + if rising_edge(clk) then + q <= d; + end if; + end if; +end process; +END behave; + diff --git a/designs/encrypted_ip/simon_core/control_unit_fsm.vhd b/designs/encrypted_ip/simon_core/control_unit_fsm.vhd new file mode 100644 index 000000000..58f71159b --- /dev/null +++ b/designs/encrypted_ip/simon_core/control_unit_fsm.vhd @@ -0,0 +1,149 @@ +--! @file +--! @brief Controller-Sequencer (CU) +--! @details The output is 12-bit form a word controlling the rest of the processor. \n +--! It is called the contol bus. \n +--! CON = Cp Ep nLm nCE nLi nEi nLa Ea Su Eu nLb nLo \n +--! The control word determines how the registers will react to the next clock edge. \n +--! P.S. n for activ low signal + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY CU IS + PORT( + ADD : IN std_logic; --! Add instruction + CLK : IN std_logic; --! Positive edge trigger clock + CLR : IN std_logic; --! Active high asynchronous clear + LDA : IN std_logic; --! Load Accumulator instruction + O : IN std_logic; --! Out instruction + SUB : IN std_logic; --! Sub instruction + CON : OUT std_logic_vector (11 DOWNTO 0) --! 12-bit control word forming control bus + --! ~ ~ ~ ~ ~ ~ ~ ~ + --! CpEpLmCE LiEiLaEa SuEuLbLo + + ); +END CU ; + +ARCHITECTURE fsm OF CU IS + + TYPE STATE_TYPE IS (s0,s1,s2,s3,s4,s5,s6,s8,s9,s10,s11,s12); + + SIGNAL current_state : STATE_TYPE ; + SIGNAL next_state : STATE_TYPE ; + +BEGIN + + clocked : PROCESS(CLK,CLR) + + BEGIN + IF (CLR = '1') THEN + current_state <= s0; + -- Reset Values + ELSIF (falling_edge(CLK)) THEN + current_state <= next_state; + -- Default Assignment To Internals + + END IF; + + END PROCESS clocked; + + nextstate : PROCESS (ADD,CLR,LDA,O,SUB,current_state) + + BEGIN + -- Default Assignment + CON <= "001111100011"; + -- Default Assignment To Internals + + -- Combined Actions + CASE current_state IS + WHEN s0 => -- Address State + CON <= "010111100011"; + IF (ADD = '1' OR LDA = '1' OR SUB = '1' OR O = '1') THEN + next_state <= s1; + ELSIF (CLR = '1') THEN + next_state <= s0; + ELSE + next_state <= s0; + END IF; + WHEN s1 => -- Increment State + CON<= "101111100011"; + IF (ADD = '1' OR LDA = '1' OR SUB = '1' OR O = '1') THEN + next_state <= s2; + ELSE + next_state <= s1; + END IF; + WHEN s2 => -- Memory State + CON <= "001001100011"; + IF (( LDA = '1' OR ADD = '1' OR SUB = '1' ) AND O = '0') THEN + next_state <= s3; + ELSIF (O = '1' AND ADD = '0' AND LDA = '0' AND SUB = '0') THEN + next_state <= s4; + ELSE + next_state <= s2; + END IF; + WHEN s3 => -- LDA Routine T4 CpEpLmCE LiEiLax xxxx + CON <= "000110100011"; + IF (LDA = '1' AND ADD = '0' AND O = '0' AND SUB = '0') THEN + next_state <= s5; + ELSIF ((ADD = '1' OR SUB = '1' ) AND ( LDA = '0' AND O = '0' )) THEN + next_state <= s6; + ELSIF (O = '1') THEN + next_state <= s4; + ELSE + next_state <= s3; + END IF; + WHEN s4 => -- LDA Routine T6 CpEpLmCE LiEiLax xxxx + CON <= "001111110010"; + IF (ADD = '1' AND O = '0' AND SUB = '0' AND LDA = '0') THEN + next_state <= s3; + ELSIF (O = '1' AND ADD = '0' AND LDA = '0' AND SUB = '0') THEN + next_state <= s8; + ELSE + next_state <= s3; + END IF; + WHEN s5 => -- LDA Routine T5 CpEpLmCE LiEiLax xxxx + CON <= "001011000011"; + IF (LDA = '1' AND ADD = '0' AND O = '0' AND SUB = '0') THEN + next_state <= s12; + ELSE + next_state <= s5; + END IF; + WHEN s6 => + CON <= "001011100001"; + IF (ADD = '1' AND LDA = '0' AND O = '0' AND SUB = '0') THEN + next_state <= s11; + ELSIF (SUB = '1' AND ADD = '0' AND LDA = '0' AND O = '0') THEN + next_state <= s10; + ELSE + next_state <= s6; + END IF; + WHEN s8 => + CON <= "001111100011"; + IF (ADD = '1' AND O = '0' AND SUB = '0' AND LDA = '0') THEN + next_state <= s3; + ELSIF (O = '1' AND ADD = '0' AND LDA = '0' AND SUB = '0') THEN + next_state <= s9; + ELSE + next_state <= s8; + END IF; + WHEN s9 => + CON <= "001111100011"; + next_state <= s0; + WHEN s10 => + CON <= "001111001111"; + next_state <= s0; + WHEN s11 => + CON <= "001111000111"; + next_state <= s0; + WHEN s12 => + CON <= "001111100011"; + next_state <= s0; + WHEN OTHERS => + next_state <= s0; + END CASE; + + END PROCESS nextstate; + +END fsm; diff --git a/designs/encrypted_ip/simon_core/design.yaml b/designs/encrypted_ip/simon_core/design.yaml new file mode 100644 index 000000000..9bdcabc5e --- /dev/null +++ b/designs/encrypted_ip/simon_core/design.yaml @@ -0,0 +1,19 @@ +top: top + +include_all_vhdl_files: True + +include_all_verilog_files: True + +encrypted_ip: + ip: + - definition: "random_pulse_generator" + instances: + - "random_pulse_generator_0" + - definition: "sha3_high_throughput" + instances: + - "sha3_high_throughput_0" + - definition: "simon_core" + instances: + - "simon_core_0" + + user_files: ["top.v"] \ No newline at end of file diff --git a/designs/encrypted_ip/simon_core/f_permutation_h.v b/designs/encrypted_ip/simon_core/f_permutation_h.v new file mode 100644 index 000000000..dac68fc87 --- /dev/null +++ b/designs/encrypted_ip/simon_core/f_permutation_h.v @@ -0,0 +1,69 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* if "ack" is 1, then current input has been used. */ + +module f_permutation_h(clk, reset, in, in_ready, ack, out, out_ready); + input clk, reset; + input [575:0] in; + input in_ready; + output ack; + output reg [1599:0] out; + output reg out_ready; + + reg [10:0] i; /* select round constant */ + wire [1599:0] round_in, round_out; + wire [63:0] rc1, rc2; + wire update; + wire accept; + reg calc; /* == 1: calculating rounds */ + + assign accept = in_ready & (~ calc); // in_ready & (i == 0) + + always @ (posedge clk) + if (reset) i <= 0; + else i <= {i[9:0], accept}; + + always @ (posedge clk) + if (reset) calc <= 0; + else calc <= (calc & (~ i[10])) | accept; + + assign update = calc | accept; + + assign ack = accept; + + always @ (posedge clk) + if (reset) + out_ready <= 0; + else if (accept) + out_ready <= 0; + else if (i[10]) // only change at the last round + out_ready <= 1; + + assign round_in = accept ? {in ^ out[1599:1599-575], out[1599-576:0]} : out; + + rconst2in1 + rconst_ ({i, accept}, rc1, rc2); + + round2in1 + round_ (round_in, rc1, rc2, round_out); + + always @ (posedge clk) + if (reset) + out <= 0; + else if (update) + out <= round_out; +endmodule diff --git a/designs/encrypted_ip/simon_core/f_permutation_l.v b/designs/encrypted_ip/simon_core/f_permutation_l.v new file mode 100644 index 000000000..32025f11a --- /dev/null +++ b/designs/encrypted_ip/simon_core/f_permutation_l.v @@ -0,0 +1,69 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* if "ack" is 1, then current input has been used. */ + +module f_permutation_l(clk, reset, in, in_ready, ack, out, out_ready); + input clk, reset; + input [575:0] in; + input in_ready; + output ack; + output reg [1599:0] out; + output reg out_ready; + + reg [22:0] i; /* select round constant */ + wire [1599:0] round_in, round_out; + wire [63:0] rc; /* round constant */ + wire update; + wire accept; + reg calc; /* == 1: calculating rounds */ + + assign accept = in_ready & (~ calc); // in_ready & (i == 0) + + always @ (posedge clk) + if (reset) i <= 0; + else i <= {i[21:0], accept}; + + always @ (posedge clk) + if (reset) calc <= 0; + else calc <= (calc & (~ i[22])) | accept; + + assign update = calc | accept; + + assign ack = accept; + + always @ (posedge clk) + if (reset) + out_ready <= 0; + else if (accept) + out_ready <= 0; + else if (i[22]) // only change at the last round + out_ready <= 1; + + assign round_in = accept ? {in ^ out[1599:1599-575], out[1599-576:0]} : out; + + rconst + rconst_ ({i, accept}, rc); + + round + round_ (round_in, rc, round_out); + + always @ (posedge clk) + if (reset) + out <= 0; + else if (update) + out <= round_out; +endmodule diff --git a/designs/encrypted_ip/simon_core/ir_behave.vhd b/designs/encrypted_ip/simon_core/ir_behave.vhd new file mode 100644 index 000000000..39d33ee5a --- /dev/null +++ b/designs/encrypted_ip/simon_core/ir_behave.vhd @@ -0,0 +1,47 @@ +--! @file +--! @brief Instruction Register (IR) +--! @details It is a part of the control unit. \n +--! The output of the IR is 8-bit word. It is divided into two nibbles. \n +--! Upper Nibble Lower Nibble \n +--! 2-state 3-state \n +--! CU W-bus \n +--! The provided instruction set is: \n +--! LDA \t 0000 Load Accumulator with corresponding memory content \n +--! ADD \t 0001 Add the content of the AC to the content of the memory adder \n +--! SUB \t 0010 Subtract the content of the memory location from the AC \n +--! OUT \t 1110 Transfer the AC content to the output port \n +--! HLT \t 1111 Stop processing data \n +--! Fetch = 3 cycles +--! Execute = 3 cycles + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY IR IS + port ( clk : in std_logic; --! Rising edge clock + clr : in std_logic; --! Active high asynchronous clear + li : in std_logic; --! Active low load instruction into IR + ei : in std_logic; --! Active low enable IR output + d : in std_logic_vector(7 downto 0); --! IR 8-bit input data word from W-bus + q_w : out std_logic_vector(3 downto 0); --! IR 4-bit output data word to W-bus + q_c : out std_logic_vector(3 downto 0)); --! IR 4-bit output control word to Control-Sequencer block +END IR ; + +ARCHITECTURE behave OF IR IS +BEGIN +process (clr,clk,li,ei) +begin + if clr = '1' then + q_w <= (others => '0'); + q_c <= (others => '0'); + elsif rising_edge(clk) then + if li = '0' then + q_c <= d(7 downto 4); + end if; + end if; + if ei = '0' then q_w <= d(3 downto 0); + else q_w <= "ZZZZ"; + end if; +end process; +END behave; + diff --git a/designs/encrypted_ip/simon_core/irdec_behave.vhd b/designs/encrypted_ip/simon_core/irdec_behave.vhd new file mode 100644 index 000000000..7bef5348b --- /dev/null +++ b/designs/encrypted_ip/simon_core/irdec_behave.vhd @@ -0,0 +1,43 @@ +--! @file +--! @brief Instruction Register Decoder (IRDec) +--! @details It is equivelent to a ring counter driving the CU. + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY IRDec IS + port (q_c : IN std_logic_vector (3 DOWNTO 0); + LDA : OUT std_logic; + ADD : OUT std_logic; + SUB : OUT std_logic; + OUTPUT : OUT std_logic; + -- jmp : OUT std_logic; + HLT : OUT std_logic); +END IRDec ; + +ARCHITECTURE behave OF IRDec IS +signal instruction : std_logic_vector(5 downto 0); +BEGIN +process (q_c) +begin + if q_c = "0000" then + instruction <= "000001" ; + elsif q_c = "0001" then + instruction <= "000010" ; + elsif q_c = "0010" then + instruction <= "000100" ; + elsif q_c = "1110" then + instruction <= "001000" ; + elsif q_c = "1111" then + instruction <= "100000"; + end if; +end process; + +LDA <= instruction(0); +ADD <= instruction(1); +SUB <= instruction(2); +OUTPUT <= instruction(3); +--jmp <= instruction(4); +HLT <= instruction(5); +END behave; + diff --git a/designs/encrypted_ip/simon_core/mar_behave.vhd b/designs/encrypted_ip/simon_core/mar_behave.vhd new file mode 100644 index 000000000..5118dee0b --- /dev/null +++ b/designs/encrypted_ip/simon_core/mar_behave.vhd @@ -0,0 +1,31 @@ +--! @file +--! @brief Memory Address Register (MAR) +--! @details It is part of the processor memory. During a computer run, the address in the PC is latched into the MAR. \n +--! A bit later, the MAR applies this 4-bit address to the RAM, where a read operation is performed. + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY MAR IS + port (CLK : in std_logic; --! Rising edge clock + CLR : in std_logic; --! Active high asynchronous clear + Lm : in std_logic; --! Active low load MAR + D : in std_logic_vector(3 downto 0); --! MAR 4-bit address input + Q : out std_logic_vector(3 downto 0)); --! MAR 4-bit address output +END MAR ; + +ARCHITECTURE behave OF MAR IS +BEGIN +process (CLR,CLK,Lm,D) +begin +if CLR = '1' then + Q <= "0000"; +elsif lm = '0' then + if rising_edge(CLK) then + Q <= D; + end if; +end if; +end process; +END behave; diff --git a/designs/encrypted_ip/simon_core/o_behave.vhd b/designs/encrypted_ip/simon_core/o_behave.vhd new file mode 100644 index 000000000..47b549c1e --- /dev/null +++ b/designs/encrypted_ip/simon_core/o_behave.vhd @@ -0,0 +1,30 @@ +--! @file +--! @brief Output Register (O) +--! @details This buffer is used to transfer the answer to the probelm being solved to the outside world. \n +--! At high Ea and low Lo at next clock edge the content of the AC is loaded into the O register. + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY O IS +port (d : in std_logic_vector(7 downto 0); --! 8-bit O input from W-bus + q : out std_logic_vector(7 downto 0); --! 8-bit O output + clk : in std_logic; --! Rising edge clock + clr : in std_logic; --! Active high asynchronous clear + lo : in std_logic); --! Active low load O content into output +END O ; + +ARCHITECTURE behave OF O IS +BEGIN +process (clr,clk,lo,d) +begin + if clr = '1' then + q <= (others => '0'); + elsif lo = '0' then + if rising_edge(clk) then + q <= d; + end if; + end if; +end process; +END behave; + diff --git a/designs/encrypted_ip/simon_core/padder1_h.v b/designs/encrypted_ip/simon_core/padder1_h.v new file mode 100644 index 000000000..73f0eefcb --- /dev/null +++ b/designs/encrypted_ip/simon_core/padder1_h.v @@ -0,0 +1,33 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +module padder1_h(in, byte_num, out); + input [63:0] in; + input [2:0] byte_num; + output reg [63:0] out; + + always @ (*) + case (byte_num) + 0: out = 64'h0100000000000000; + 1: out = {in[63:56], 56'h01000000000000}; + 2: out = {in[63:48], 48'h010000000000}; + 3: out = {in[63:40], 40'h0100000000}; + 4: out = {in[63:32], 32'h01000000}; + 5: out = {in[63:24], 24'h010000}; + 6: out = {in[63:16], 16'h0100}; + 7: out = {in[63:8], 8'h01}; + endcase +endmodule diff --git a/designs/encrypted_ip/simon_core/padder1_l.v b/designs/encrypted_ip/simon_core/padder1_l.v new file mode 100644 index 000000000..82bd529f8 --- /dev/null +++ b/designs/encrypted_ip/simon_core/padder1_l.v @@ -0,0 +1,37 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * in byte_num out + * 0x11223344 0 0x01000000 + * 0x11223344 1 0x11010000 + * 0x11223344 2 0x11220100 + * 0x11223344 3 0x11223301 + */ + +module padder1_l(in, byte_num, out); + input [31:0] in; + input [1:0] byte_num; + output reg [31:0] out; + + always @ (*) + case (byte_num) + 0: out = 32'h1000000; + 1: out = {in[31:24], 24'h010000}; + 2: out = {in[31:16], 16'h0100}; + 3: out = {in[31:8], 8'h01}; + endcase +endmodule diff --git a/designs/encrypted_ip/simon_core/padder_h.v b/designs/encrypted_ip/simon_core/padder_h.v new file mode 100644 index 000000000..c570d5f2c --- /dev/null +++ b/designs/encrypted_ip/simon_core/padder_h.v @@ -0,0 +1,88 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* "is_last" == 0 means byte number is 8, no matter what value "byte_num" is. */ +/* if "in_ready" == 0, then "is_last" should be 0. */ +/* the user switch to next "in" only if "ack" == 1. */ + +module padder_h(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready, f_ack); + input clk, reset; + input [63:0] in; + input in_ready, is_last; + input [2:0] byte_num; + output buffer_full; /* to "user" module */ + output reg [575:0] out; /* to "f_permutation" module */ + output out_ready; /* to "f_permutation" module */ + input f_ack; /* from "f_permutation" module */ + + reg state; /* state == 0: user will send more input data + * state == 1: user will not send any data */ + reg done; /* == 1: out_ready should be 0 */ + reg [8:0] i; /* length of "out" buffer */ + wire [63:0] v0; /* output of module "padder1" */ + reg [63:0] v1; /* to be shifted into register "out" */ + wire accept, /* accept user input? */ + update; + + assign buffer_full = i[8]; + assign out_ready = buffer_full; + assign accept = (~ state) & in_ready & (~ buffer_full); // if state == 1, do not eat input + assign update = (accept | (state & (~ buffer_full))) & (~ done); // don't fill buffer if done + + always @ (posedge clk) + if (reset) + out <= 0; + else if (update) + out <= {out[575-64:0], v1}; + + always @ (posedge clk) + if (reset) + i <= 0; + else if (f_ack | update) + i <= {i[7:0], 1'b1} & {9{~ f_ack}}; +/* if (f_ack) i <= 0; */ +/* if (update) i <= {i[7:0], 1'b1}; // increase length */ + + always @ (posedge clk) + if (reset) + state <= 0; + else if (is_last) + state <= 1; + + always @ (posedge clk) + if (reset) + done <= 0; + else if (state & out_ready) + done <= 1; + + padder1_h p0 (in, byte_num, v0); + + always @ (*) + begin + if (state) + begin + v1 = 0; + v1[7] = v1[7] | i[7]; /* "v1[7]" is the MSB of its last byte */ + end + else if (is_last == 0) + v1 = in; + else + begin + v1 = v0; + v1[7] = v1[7] | i[7]; + end + end +endmodule diff --git a/designs/encrypted_ip/simon_core/padder_l.v b/designs/encrypted_ip/simon_core/padder_l.v new file mode 100644 index 000000000..64c15a60f --- /dev/null +++ b/designs/encrypted_ip/simon_core/padder_l.v @@ -0,0 +1,88 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* "is_last" == 0 means byte number is 4, no matter what value "byte_num" is. */ +/* if "in_ready" == 0, then "is_last" should be 0. */ +/* the user switch to next "in" only if "ack" == 1. */ + +module padder_l(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready, f_ack); + input clk, reset; + input [31:0] in; + input in_ready, is_last; + input [1:0] byte_num; + output buffer_full; /* to "user" module */ + output reg [575:0] out; /* to "f_permutation" module */ + output out_ready; /* to "f_permutation" module */ + input f_ack; /* from "f_permutation" module */ + + reg state; /* state == 0: user will send more input data + * state == 1: user will not send any data */ + reg done; /* == 1: out_ready should be 0 */ + reg [17:0] i; /* length of "out" buffer */ + wire [31:0] v0; /* output of module "padder1" */ + reg [31:0] v1; /* to be shifted into register "out" */ + wire accept, /* accept user input? */ + update; + + assign buffer_full = i[17]; + assign out_ready = buffer_full; + assign accept = (~ state) & in_ready & (~ buffer_full); // if state == 1, do not eat input + assign update = (accept | (state & (~ buffer_full))) & (~ done); // don't fill buffer if done + + always @ (posedge clk) + if (reset) + out <= 0; + else if (update) + out <= {out[575-32:0], v1}; + + always @ (posedge clk) + if (reset) + i <= 0; + else if (f_ack | update) + i <= {i[16:0], 1'b1} & {18{~ f_ack}}; +/* if (f_ack) i <= 0; */ +/* if (update) i <= {i[16:0], 1'b1}; // increase length */ + + always @ (posedge clk) + if (reset) + state <= 0; + else if (is_last) + state <= 1; + + always @ (posedge clk) + if (reset) + done <= 0; + else if (state & out_ready) + done <= 1; + + padder1_l p0 (in, byte_num, v0); + + always @ (*) + begin + if (state) + begin + v1 = 0; + v1[7] = v1[7] | i[16]; // "v1[7]" is the MSB of the last byte of "v1" + end + else if (is_last == 0) + v1 = in; + else + begin + v1 = v0; + v1[7] = v1[7] | i[16]; + end + end +endmodule diff --git a/designs/encrypted_ip/simon_core/pc_behave.vhd b/designs/encrypted_ip/simon_core/pc_behave.vhd new file mode 100644 index 000000000..bb6ebba6b --- /dev/null +++ b/designs/encrypted_ip/simon_core/pc_behave.vhd @@ -0,0 +1,46 @@ +--! @file +--! @brief Program Counter (PC) +--! @details The PC is reset to 0000 before the processor runs. Then the PC send the address 0000 to the RAM/ROM, \n +--! to fetch and exectute the corresponding instruction. After the first instruction is fetched and exectuted \n +--! the PC sends the following address 0001 to the RAM/ROM, and so on. \n +--! The PC is part of the conrtol unit, it counts from 0000 to 1111. \n +--! It is called pointer; it points to a memory location where instruction is stored. \n +--! It work as 4-bit counter. + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; + +ENTITY PC IS +PORT (ep : in std_logic; --! Active high otuput enable from PC, or tri-state + clr : in std_logic; --! Active high asynchronous clear + clk : in std_logic; --! Falling edge clock + cp : in std_logic; --! Active high enable PC to count + q : out std_logic_vector(3 downto 0)); --! 4-bit PC output +END PC ; + +ARCHITECTURE behave OF PC IS +signal count :std_logic_vector(3 downto 0); +BEGIN +process (clr,ep,cp,clk,count) +begin + if clr = '1' then + q <= "0000"; + count <= "0000"; + elsif cp = '1' then + if falling_edge(clk) then + if count < "1111" then count <= count + 1; + else count <= "0000"; + end if; + end if; + end if; + + if ep = '0' then + q <= "ZZZZ"; + else + q <= count; + end if; + +end process; +END behave; + diff --git a/designs/encrypted_ip/simon_core/random_pulse_generator.v b/designs/encrypted_ip/simon_core/random_pulse_generator.v new file mode 100644 index 000000000..b98466e6b --- /dev/null +++ b/designs/encrypted_ip/simon_core/random_pulse_generator.v @@ -0,0 +1,53 @@ +/////////////////////////////////////////////////////////////////////////////////////////////////// +// +// File: random_pulse_generator.v +// File history: +// Version 1: 2015-03-24: Created +// +// Description: +// +// Poisson process generator. +// Generate Poisson process with desired inversed rate (number of clocks per hit). +// The rate is defined by parameter LN2_PERIOD. For example, the LN2_PERIOD=4 will generate +// in average one pulse per 16 clocks. +// +// Author: Andrey Sukhanov +// +/////////////////////////////////////////////////////////////////////////////////////////////////// +`timescale 1ns/1ps + +//'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' +module pseudo_random(input clk, ce, rst, output reg [31:0] q); +// 32-bit uniform pseudo-random number generator, based on fibonacci LFSR +// Other 32-bit uniform random generators can be used as well. + +wire feedback = q[31]^q[29]^q[28]^ q[27]^ q[23]^q[20]^ q[19]^q[17]^ q[15]^q[14]^q[12]^ q[11]^q[9]^ q[4]^ q[3]^q[2]; +//feedback term B89ADA1C, other terms can be found from this table +// http://www.ece.cmu.edu/~koopman/lfsr/index.html + +always @(posedge clk or posedge rst) + if (rst) + q <= 32'haaaaaaaa; // the start is more random with this initialization + else if (ce) + q <= {q[30:0], feedback} ; +endmodule +//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +//'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' +module random_pulse_generator( input clk, ce, rst, output reg q); + +parameter LN2_PERIOD = 4; // 1 < LN2_PERIOD < 31 +// log2 of the inversed process rate , + +parameter MASK = {LN2_PERIOD{1'b0}}; // any number with LN2_PERIOD bits can be used as a MASK +wire [31:0] uniform_random; +wire [LN2_PERIOD-1:0] sample; +pseudo_random pseudo_random_gen(clk, ce, rst, uniform_random); + +assign sample = uniform_random[LN2_PERIOD-1:0]; // any subset of LN2_PERIOD bits can be used as a sample +always @ (posedge clk) + if(ce) begin + if (sample == MASK) q <= 1'b1; + if (q) q <= 1'b0; + end +endmodule +//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, diff --git a/designs/encrypted_ip/simon_core/rconst.v b/designs/encrypted_ip/simon_core/rconst.v new file mode 100644 index 000000000..b92b18404 --- /dev/null +++ b/designs/encrypted_ip/simon_core/rconst.v @@ -0,0 +1,34 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* round constant */ +module rconst(i, rc); + input [23:0] i; + output reg [63:0] rc; + + always @ (i) + begin + rc = 0; + rc[0] = i[0] | i[4] | i[5] | i[6] | i[7] | i[10] | i[12] | i[13] | i[14] | i[15] | i[20] | i[22]; + rc[1] = i[1] | i[2] | i[4] | i[8] | i[11] | i[12] | i[13] | i[15] | i[16] | i[18] | i[19]; + rc[3] = i[2] | i[4] | i[7] | i[8] | i[9] | i[10] | i[11] | i[12] | i[13] | i[14] | i[18] | i[19] | i[23]; + rc[7] = i[1] | i[2] | i[4] | i[6] | i[8] | i[9] | i[12] | i[13] | i[14] | i[17] | i[20] | i[21]; + rc[15] = i[1] | i[2] | i[3] | i[4] | i[6] | i[7] | i[10] | i[12] | i[14] | i[15] | i[16] | i[18] | i[20] | i[21] | i[23]; + rc[31] = i[3] | i[5] | i[6] | i[10] | i[11] | i[12] | i[19] | i[20] | i[22] | i[23]; + rc[63] = i[2] | i[3] | i[6] | i[7] | i[13] | i[14] | i[15] | i[16] | i[17] | i[19] | i[20] | i[21] | i[23]; + end +endmodule + diff --git a/designs/encrypted_ip/simon_core/rconst2in1.v b/designs/encrypted_ip/simon_core/rconst2in1.v new file mode 100644 index 000000000..f05145360 --- /dev/null +++ b/designs/encrypted_ip/simon_core/rconst2in1.v @@ -0,0 +1,46 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* round constant (2 in 1 ~ ~) */ +module rconst2in1(i, rc1, rc2); + input [11:0] i; + output [63:0] rc1, rc2; + reg [63:0] rc1, rc2; + + always @ (i) + begin + rc1 = 0; + rc1[0] = i[0] | i[2] | i[3] | i[5] | i[6] | i[7] | i[10] | i[11]; + rc1[1] = i[1] | i[2] | i[4] | i[6] | i[8] | i[9]; + rc1[3] = i[1] | i[2] | i[4] | i[5] | i[6] | i[7] | i[9]; + rc1[7] = i[1] | i[2] | i[3] | i[4] | i[6] | i[7] | i[10]; + rc1[15] = i[1] | i[2] | i[3] | i[5] | i[6] | i[7] | i[8] | i[9] | i[10]; + rc1[31] = i[3] | i[5] | i[6] | i[10] | i[11]; + rc1[63] = i[1] | i[3] | i[7] | i[8] | i[10]; + end + + always @ (i) + begin + rc2 = 0; + rc2[0] = i[2] | i[3] | i[6] | i[7]; + rc2[1] = i[0] | i[5] | i[6] | i[7] | i[9]; + rc2[3] = i[3] | i[4] | i[5] | i[6] | i[9] | i[11]; + rc2[7] = i[0] | i[4] | i[6] | i[8] | i[10]; + rc2[15] = i[0] | i[1] | i[3] | i[7] | i[10] | i[11]; + rc2[31] = i[1] | i[2] | i[5] | i[9] | i[11]; + rc2[63] = i[1] | i[3] | i[6] | i[7] | i[8] | i[9] | i[10] | i[11]; + end +endmodule diff --git a/designs/encrypted_ip/simon_core/rom_16_8_behave.vhd b/designs/encrypted_ip/simon_core/rom_16_8_behave.vhd new file mode 100644 index 000000000..e6cb6a998 --- /dev/null +++ b/designs/encrypted_ip/simon_core/rom_16_8_behave.vhd @@ -0,0 +1,58 @@ +--! @file +--! @brief Read Only Memory +--! @details It is used to store the program on it. It replaces a RAM on the original design. + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY ROM_16_8 IS +PORT( read : IN std_logic; --! Active low enable ROM signal, (tri-state) + address : IN std_logic_vector (3 DOWNTO 0); --! 4-bit ROM address bits from MAR + data_out : OUT std_logic_vector (7 DOWNTO 0)); --! 8-bit ROM output word to W-bus +END ROM_16_8 ; + +ARCHITECTURE behave OF ROM_16_8 IS +type mem is array (0 to 15) of std_logic_vector(7 downto 0) ; +signal rom : mem; +BEGIN + --! @verbatim + --! This program works as follow: + --! + --! Load 5 to AC (memory content of 9) + --! Output 5 (content of AC) + --! Add 7 (memory content of 10) to 5 (AC content) + --! Output 12 (content of AC) + --! Add 3 (memory content of 11) to 12 (AC content) + --! Subtract 4 (memory content of 12) from 15 (AC content) + --! Output 11 (content of AC) + --! + --! @endverbatim + rom <= ( + 0 => "00001001" , -- LDA 9h ... Load AC with the content of memory location 9 + 1 => "11101111" , -- OUT + 2 => "00011010" , -- ADD Ah ... Add the contents of memory location A to the AC content and replace the AC + 3 => "11101111" , -- OUT + 4 => "00011011" , -- ADD Bh ... Add the contents of memory location B to the AC content and replace the AC + 5 => "00101100" , -- SUB Ch ... Sub the contents of memory location C from the AC content and replace the AC + 6 => "11101111" , -- OUT + 7 => "11111111" , -- HLT + 8 => "11111111" , + 9 => "00000101" , --5 + 10=> "00000111" , --7 + 11=> "00000011" , --3 + 12=> "00000100" , --4 + 13=> "11111111" , + 14=> "11111111" , + 15=> "11111111" ); + + process (read,address) + begin + if read = '0' then + data_out <= rom(conv_integer(address)) ; + else + data_out <= (data_out'range => 'Z'); + end if; + end process ; +END behave; diff --git a/designs/encrypted_ip/simon_core/round.v b/designs/encrypted_ip/simon_core/round.v new file mode 100644 index 000000000..939c9f3d0 --- /dev/null +++ b/designs/encrypted_ip/simon_core/round.v @@ -0,0 +1,171 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +`define low_pos(x,y) `high_pos(x,y) - 63 +`define high_pos(x,y) 1599 - 64*(5*y+x) +`define add_1(x) (x == 4 ? 0 : x + 1) +`define add_2(x) (x == 3 ? 0 : x == 4 ? 1 : x + 2) +`define sub_1(x) (x == 0 ? 4 : x - 1) +`define rot_up(in, n) {in[63-n:0], in[63:63-n+1]} +`define rot_up_1(in) {in[62:0], in[63]} + +module round(in, round_const, out); + input [1599:0] in; + input [63:0] round_const; + output [1599:0] out; + + wire [63:0] a[4:0][4:0]; + wire [63:0] b[4:0]; + wire [63:0] c[4:0][4:0], d[4:0][4:0], e[4:0][4:0], f[4:0][4:0], g[4:0][4:0]; + + genvar x, y; + + /* assign "a[x][y][z] == in[w(5y+x)+z]" */ + generate + for(y=0; y<5; y=y+1) + begin : L0 + for(x=0; x<5; x=x+1) + begin : L1 + assign a[x][y] = in[`high_pos(x,y) : `low_pos(x,y)]; + end + end + endgenerate + + /* calc "b[x] == a[x][0] ^ a[x][1] ^ ... ^ a[x][4]" */ + generate + for(x=0; x<5; x=x+1) + begin : L2 + assign b[x] = a[x][0] ^ a[x][1] ^ a[x][2] ^ a[x][3] ^ a[x][4]; + end + endgenerate + + /* calc "c == theta(a)" */ + generate + for(y=0; y<5; y=y+1) + begin : L3 + for(x=0; x<5; x=x+1) + begin : L4 + assign c[x][y] = a[x][y] ^ b[`sub_1(x)] ^ `rot_up_1(b[`add_1(x)]); + end + end + endgenerate + + /* calc "d == rho(c)" */ + assign d[0][0] = c[0][0]; + assign d[1][0] = `rot_up_1(c[1][0]); + assign d[2][0] = `rot_up(c[2][0], 62); + assign d[3][0] = `rot_up(c[3][0], 28); + assign d[4][0] = `rot_up(c[4][0], 27); + assign d[0][1] = `rot_up(c[0][1], 36); + assign d[1][1] = `rot_up(c[1][1], 44); + assign d[2][1] = `rot_up(c[2][1], 6); + assign d[3][1] = `rot_up(c[3][1], 55); + assign d[4][1] = `rot_up(c[4][1], 20); + assign d[0][2] = `rot_up(c[0][2], 3); + assign d[1][2] = `rot_up(c[1][2], 10); + assign d[2][2] = `rot_up(c[2][2], 43); + assign d[3][2] = `rot_up(c[3][2], 25); + assign d[4][2] = `rot_up(c[4][2], 39); + assign d[0][3] = `rot_up(c[0][3], 41); + assign d[1][3] = `rot_up(c[1][3], 45); + assign d[2][3] = `rot_up(c[2][3], 15); + assign d[3][3] = `rot_up(c[3][3], 21); + assign d[4][3] = `rot_up(c[4][3], 8); + assign d[0][4] = `rot_up(c[0][4], 18); + assign d[1][4] = `rot_up(c[1][4], 2); + assign d[2][4] = `rot_up(c[2][4], 61); + assign d[3][4] = `rot_up(c[3][4], 56); + assign d[4][4] = `rot_up(c[4][4], 14); + + /* calc "e == pi(d)" */ + assign e[0][0] = d[0][0]; + assign e[0][2] = d[1][0]; + assign e[0][4] = d[2][0]; + assign e[0][1] = d[3][0]; + assign e[0][3] = d[4][0]; + assign e[1][3] = d[0][1]; + assign e[1][0] = d[1][1]; + assign e[1][2] = d[2][1]; + assign e[1][4] = d[3][1]; + assign e[1][1] = d[4][1]; + assign e[2][1] = d[0][2]; + assign e[2][3] = d[1][2]; + assign e[2][0] = d[2][2]; + assign e[2][2] = d[3][2]; + assign e[2][4] = d[4][2]; + assign e[3][4] = d[0][3]; + assign e[3][1] = d[1][3]; + assign e[3][3] = d[2][3]; + assign e[3][0] = d[3][3]; + assign e[3][2] = d[4][3]; + assign e[4][2] = d[0][4]; + assign e[4][4] = d[1][4]; + assign e[4][1] = d[2][4]; + assign e[4][3] = d[3][4]; + assign e[4][0] = d[4][4]; + + /* calc "f = chi(e)" */ + generate + for(y=0; y<5; y=y+1) + begin : L5 + for(x=0; x<5; x=x+1) + begin : L6 + assign f[x][y] = e[x][y] ^ ((~ e[`add_1(x)][y]) & e[`add_2(x)][y]); + end + end + endgenerate + + /* calc "g = iota(f)" */ + generate + for(x=0; x<64; x=x+1) + begin : L60 + if(x==0 || x==1 || x==3 || x==7 || x==15 || x==31 || x==63) + assign g[0][0][x] = f[0][0][x] ^ round_const[x]; + else + assign g[0][0][x] = f[0][0][x]; + end + endgenerate + + generate + for(y=0; y<5; y=y+1) + begin : L7 + for(x=0; x<5; x=x+1) + begin : L8 + if(x!=0 || y!=0) + assign g[x][y] = f[x][y]; + end + end + endgenerate + + /* assign "out[w(5y+x)+z] == out_var[x][y][z]" */ + generate + for(y=0; y<5; y=y+1) + begin : L99 + for(x=0; x<5; x=x+1) + begin : L100 + assign out[`high_pos(x,y) : `low_pos(x,y)] = g[x][y]; + end + end + endgenerate +endmodule + +`undef low_pos +`undef high_pos +`undef add_1 +`undef add_2 +`undef sub_1 +`undef rot_up +`undef rot_up_1 diff --git a/designs/encrypted_ip/simon_core/round2in1.v b/designs/encrypted_ip/simon_core/round2in1.v new file mode 100644 index 000000000..4db161c3c --- /dev/null +++ b/designs/encrypted_ip/simon_core/round2in1.v @@ -0,0 +1,284 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +`define low_pos(x,y) `high_pos(x,y) - 63 +`define high_pos(x,y) 1599 - 64*(5*y+x) +`define add_1(x) (x == 4 ? 0 : x + 1) +`define add_2(x) (x == 3 ? 0 : x == 4 ? 1 : x + 2) +`define sub_1(x) (x == 0 ? 4 : x - 1) +`define rot_up(in, n) {in[63-n:0], in[63:63-n+1]} +`define rot_up_1(in) {in[62:0], in[63]} + +module round2in1(in, round_const_1, round_const_2, out); + input [1599:0] in; + input [63:0] round_const_1, round_const_2; + output [1599:0] out; + + /* "a ~ g" for round 1 */ + wire [63:0] a[4:0][4:0]; + wire [63:0] b[4:0]; + wire [63:0] c[4:0][4:0], d[4:0][4:0], e[4:0][4:0], f[4:0][4:0], g[4:0][4:0]; + + /* "aa ~ gg" for round 2 */ + wire [63:0] bb[4:0]; + wire [63:0] cc[4:0][4:0], dd[4:0][4:0], ee[4:0][4:0], ff[4:0][4:0], gg[4:0][4:0]; + + genvar x, y; + + /* assign "a[x][y][z] == in[w(5y+x)+z]" */ + generate + for(y=0; y<5; y=y+1) + begin : L0 + for(x=0; x<5; x=x+1) + begin : L1 + assign a[x][y] = in[`high_pos(x,y) : `low_pos(x,y)]; + end + end + endgenerate + + /* calc "b[x] == a[x][0] ^ a[x][1] ^ ... ^ a[x][4]" */ + generate + for(x=0; x<5; x=x+1) + begin : L2 + assign b[x] = a[x][0] ^ a[x][1] ^ a[x][2] ^ a[x][3] ^ a[x][4]; + end + endgenerate + + /* calc "c == theta(a)" */ + generate + for(y=0; y<5; y=y+1) + begin : L3 + for(x=0; x<5; x=x+1) + begin : L4 + assign c[x][y] = a[x][y] ^ b[`sub_1(x)] ^ `rot_up_1(b[`add_1(x)]); + end + end + endgenerate + + /* calc "d == rho(c)" */ + assign d[0][0] = c[0][0]; + assign d[1][0] = `rot_up_1(c[1][0]); + assign d[2][0] = `rot_up(c[2][0], 62); + assign d[3][0] = `rot_up(c[3][0], 28); + assign d[4][0] = `rot_up(c[4][0], 27); + assign d[0][1] = `rot_up(c[0][1], 36); + assign d[1][1] = `rot_up(c[1][1], 44); + assign d[2][1] = `rot_up(c[2][1], 6); + assign d[3][1] = `rot_up(c[3][1], 55); + assign d[4][1] = `rot_up(c[4][1], 20); + assign d[0][2] = `rot_up(c[0][2], 3); + assign d[1][2] = `rot_up(c[1][2], 10); + assign d[2][2] = `rot_up(c[2][2], 43); + assign d[3][2] = `rot_up(c[3][2], 25); + assign d[4][2] = `rot_up(c[4][2], 39); + assign d[0][3] = `rot_up(c[0][3], 41); + assign d[1][3] = `rot_up(c[1][3], 45); + assign d[2][3] = `rot_up(c[2][3], 15); + assign d[3][3] = `rot_up(c[3][3], 21); + assign d[4][3] = `rot_up(c[4][3], 8); + assign d[0][4] = `rot_up(c[0][4], 18); + assign d[1][4] = `rot_up(c[1][4], 2); + assign d[2][4] = `rot_up(c[2][4], 61); + assign d[3][4] = `rot_up(c[3][4], 56); + assign d[4][4] = `rot_up(c[4][4], 14); + + /* calc "e == pi(d)" */ + assign e[0][0] = d[0][0]; + assign e[0][2] = d[1][0]; + assign e[0][4] = d[2][0]; + assign e[0][1] = d[3][0]; + assign e[0][3] = d[4][0]; + assign e[1][3] = d[0][1]; + assign e[1][0] = d[1][1]; + assign e[1][2] = d[2][1]; + assign e[1][4] = d[3][1]; + assign e[1][1] = d[4][1]; + assign e[2][1] = d[0][2]; + assign e[2][3] = d[1][2]; + assign e[2][0] = d[2][2]; + assign e[2][2] = d[3][2]; + assign e[2][4] = d[4][2]; + assign e[3][4] = d[0][3]; + assign e[3][1] = d[1][3]; + assign e[3][3] = d[2][3]; + assign e[3][0] = d[3][3]; + assign e[3][2] = d[4][3]; + assign e[4][2] = d[0][4]; + assign e[4][4] = d[1][4]; + assign e[4][1] = d[2][4]; + assign e[4][3] = d[3][4]; + assign e[4][0] = d[4][4]; + + /* calc "f = chi(e)" */ + generate + for(y=0; y<5; y=y+1) + begin : L5 + for(x=0; x<5; x=x+1) + begin : L6 + assign f[x][y] = e[x][y] ^ ((~ e[`add_1(x)][y]) & e[`add_2(x)][y]); + end + end + endgenerate + + /* calc "g = iota(f)" */ + generate + for(x=0; x<64; x=x+1) + begin : L60 + if(x==0 || x==1 || x==3 || x==7 || x==15 || x==31 || x==63) + assign g[0][0][x] = f[0][0][x] ^ round_const_1[x]; + else + assign g[0][0][x] = f[0][0][x]; + end + endgenerate + + generate + for(y=0; y<5; y=y+1) + begin : L7 + for(x=0; x<5; x=x+1) + begin : L8 + if(x!=0 || y!=0) + assign g[x][y] = f[x][y]; + end + end + endgenerate + + /* round 2 */ + + /* calc "bb[x] == g[x][0] ^ g[x][1] ^ ... ^ g[x][4]" */ + generate + for(x=0; x<5; x=x+1) + begin : L12 + assign bb[x] = g[x][0] ^ g[x][1] ^ g[x][2] ^ g[x][3] ^ g[x][4]; + end + endgenerate + + /* calc "cc == theta(g)" */ + generate + for(y=0; y<5; y=y+1) + begin : L13 + for(x=0; x<5; x=x+1) + begin : L14 + assign cc[x][y] = g[x][y] ^ bb[`sub_1(x)] ^ `rot_up_1(bb[`add_1(x)]); + end + end + endgenerate + + /* calc "dd == rho(cc)" */ + assign dd[0][0] = cc[0][0]; + assign dd[1][0] = `rot_up_1(cc[1][0]); + assign dd[2][0] = `rot_up(cc[2][0], 62); + assign dd[3][0] = `rot_up(cc[3][0], 28); + assign dd[4][0] = `rot_up(cc[4][0], 27); + assign dd[0][1] = `rot_up(cc[0][1], 36); + assign dd[1][1] = `rot_up(cc[1][1], 44); + assign dd[2][1] = `rot_up(cc[2][1], 6); + assign dd[3][1] = `rot_up(cc[3][1], 55); + assign dd[4][1] = `rot_up(cc[4][1], 20); + assign dd[0][2] = `rot_up(cc[0][2], 3); + assign dd[1][2] = `rot_up(cc[1][2], 10); + assign dd[2][2] = `rot_up(cc[2][2], 43); + assign dd[3][2] = `rot_up(cc[3][2], 25); + assign dd[4][2] = `rot_up(cc[4][2], 39); + assign dd[0][3] = `rot_up(cc[0][3], 41); + assign dd[1][3] = `rot_up(cc[1][3], 45); + assign dd[2][3] = `rot_up(cc[2][3], 15); + assign dd[3][3] = `rot_up(cc[3][3], 21); + assign dd[4][3] = `rot_up(cc[4][3], 8); + assign dd[0][4] = `rot_up(cc[0][4], 18); + assign dd[1][4] = `rot_up(cc[1][4], 2); + assign dd[2][4] = `rot_up(cc[2][4], 61); + assign dd[3][4] = `rot_up(cc[3][4], 56); + assign dd[4][4] = `rot_up(cc[4][4], 14); + + /* calc "ee == pi(dd)" */ + assign ee[0][0] = dd[0][0]; + assign ee[0][2] = dd[1][0]; + assign ee[0][4] = dd[2][0]; + assign ee[0][1] = dd[3][0]; + assign ee[0][3] = dd[4][0]; + assign ee[1][3] = dd[0][1]; + assign ee[1][0] = dd[1][1]; + assign ee[1][2] = dd[2][1]; + assign ee[1][4] = dd[3][1]; + assign ee[1][1] = dd[4][1]; + assign ee[2][1] = dd[0][2]; + assign ee[2][3] = dd[1][2]; + assign ee[2][0] = dd[2][2]; + assign ee[2][2] = dd[3][2]; + assign ee[2][4] = dd[4][2]; + assign ee[3][4] = dd[0][3]; + assign ee[3][1] = dd[1][3]; + assign ee[3][3] = dd[2][3]; + assign ee[3][0] = dd[3][3]; + assign ee[3][2] = dd[4][3]; + assign ee[4][2] = dd[0][4]; + assign ee[4][4] = dd[1][4]; + assign ee[4][1] = dd[2][4]; + assign ee[4][3] = dd[3][4]; + assign ee[4][0] = dd[4][4]; + + /* calc "ff = chi(ee)" */ + generate + for(y=0; y<5; y=y+1) + begin : L15 + for(x=0; x<5; x=x+1) + begin : L16 + assign ff[x][y] = ee[x][y] ^ ((~ ee[`add_1(x)][y]) & ee[`add_2(x)][y]); + end + end + endgenerate + + /* calc "gg = iota(ff)" */ + generate + for(x=0; x<64; x=x+1) + begin : L160 + if(x==0 || x==1 || x==3 || x==7 || x==15 || x==31 || x==63) + assign gg[0][0][x] = ff[0][0][x] ^ round_const_2[x]; + else + assign gg[0][0][x] = ff[0][0][x]; + end + endgenerate + + generate + for(y=0; y<5; y=y+1) + begin : L17 + for(x=0; x<5; x=x+1) + begin : L18 + if(x!=0 || y!=0) + assign gg[x][y] = ff[x][y]; + end + end + endgenerate + + /* assign "out[w(5y+x)+z] == out_var[x][y][z]" */ + generate + for(y=0; y<5; y=y+1) + begin : L99 + for(x=0; x<5; x=x+1) + begin : L100 + assign out[`high_pos(x,y) : `low_pos(x,y)] = gg[x][y]; + end + end + endgenerate +endmodule + +`undef low_pos +`undef high_pos +`undef add_1 +`undef add_2 +`undef sub_1 +`undef rot_up +`undef rot_up_1 diff --git a/designs/encrypted_ip/simon_core/sap.vhd b/designs/encrypted_ip/simon_core/sap.vhd new file mode 100644 index 000000000..723080c19 --- /dev/null +++ b/designs/encrypted_ip/simon_core/sap.vhd @@ -0,0 +1,265 @@ +--------------------------------------------------------------------------------------------------- +--! @file +--! @brief This is the top-level design for a simple 8-bit microprossesor. +--! @details This is a 8-bit microprocessor which is know as SAP-1 or +--! Simple-As-Possible Computer. It is described in [1]. +--! @author Ahmed Shahein +--! @email ahmed.shahein@ieee.org +--! @see [1] Malvino, A.P. and Brown, J.A., "Digital computer electronics", Glencoe/McGraw-Hill, 1992. +--! +--! @image html Architecture.png +--------------------------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY sap IS + PORT( + clk : IN std_logic; --! Active high asynchronous clear + clr : IN std_logic; --! Rising edge clock + hlt : OUT std_logic; --! Halt signal to stop processing data + q3 : OUT std_logic_vector (7 DOWNTO 0) --! 8-bit output + ); +END sap ; + +ARCHITECTURE struct OF sap IS + + -- Internal signal declarations + SIGNAL Ce : std_logic; --! Chip select for ROM + SIGNAL D : std_logic_vector(3 DOWNTO 0); --! MAR 4-bit address input + SIGNAL Eu : std_logic; --! Enable ALU + SIGNAL Lm : std_logic; --! Content of PC are latched into MAR on the next +ve edge (LOW) + SIGNAL Q2 : std_logic_vector(3 DOWNTO 0); --! MAR 4-bit address output + SIGNAL Su : std_logic; --! Add or Sub + SIGNAL W : std_logic_vector(7 DOWNTO 0); --! W-bus the major internal data bus + SIGNAL add : std_logic; --! IR decoder add control signal + SIGNAL con : std_logic_vector(11 DOWNTO 0); --! Control word bus + SIGNAL Cp : std_logic; --! Chip select PC + SIGNAL d1 : std_logic_vector(7 DOWNTO 0); --! 8-bit output data to Adder-Subtractor block + SIGNAL Ea : std_logic; --! Enable AC + SIGNAL Ei : std_logic; --! Enable IR + SIGNAL Ep : std_logic; --! Enable PC + SIGNAL La : std_logic; --! Load Accumulator AC + SIGNAL Lb : std_logic; --! Load B Register B + SIGNAL lda : std_logic; --! Load Accumulator instruction + SIGNAL Li : std_logic; --! Load Instruction Register IR + SIGNAL Lo : std_logic; --! Load Output Register O + SIGNAL output : std_logic; --! Output the result + SIGNAL q : std_logic_vector(3 DOWNTO 0); --! 4-bit PC output + SIGNAL q1 : std_logic_vector(7 DOWNTO 0); --! ALU B input 8-bit from B-register + SIGNAL q_alu : std_logic_vector(7 DOWNTO 0); --! ALU A input 8-bit from AC + SIGNAL q_c : std_logic_vector(3 DOWNTO 0); --! IR 4-bit output control word to Control-Sequencer block + SIGNAL q_w : std_logic_vector(3 DOWNTO 0); --! IR 4-bit output data word to W-bus + SIGNAL sub : std_logic; --! IR decoder sub control signal + + + -- Component Declarations + COMPONENT AC + PORT ( + d : IN std_logic_vector (7 DOWNTO 0); + q_alu : OUT std_logic_vector (7 DOWNTO 0); + q_data : OUT std_logic_vector (7 DOWNTO 0); + clk : IN std_logic ; + ea : IN std_logic ; + clr : IN std_logic ; + la : IN std_logic + ); + END COMPONENT; + COMPONENT ALU + PORT ( + A : IN std_logic_vector (7 DOWNTO 0); + B : IN std_logic_vector (7 DOWNTO 0); + S : OUT std_logic_vector (7 DOWNTO 0); + Su : IN std_logic ; + Eu : IN std_logic + ); + END COMPONENT; + COMPONENT B_Reg + PORT ( + d : IN std_logic_vector (7 DOWNTO 0); + q : OUT std_logic_vector (7 DOWNTO 0); + clk : IN std_logic ; + clr : IN std_logic ; + lb : IN std_logic + ); + END COMPONENT; + COMPONENT CU + PORT ( + ADD : IN std_logic ; + CLK : IN std_logic ; + CLR : IN std_logic ; + LDA : IN std_logic ; + O : IN std_logic ; + SUB : IN std_logic ; + con : OUT std_logic_vector (11 DOWNTO 0) + ); + END COMPONENT; + COMPONENT IR + PORT ( + clk : IN std_logic ; + clr : IN std_logic ; + li : IN std_logic ; + ei : IN std_logic ; + d : IN std_logic_vector (7 DOWNTO 0); + q_w : OUT std_logic_vector (3 DOWNTO 0); + q_c : OUT std_logic_vector (3 DOWNTO 0) + ); + END COMPONENT; + COMPONENT IRDec + PORT ( + q_c : IN std_logic_vector (3 DOWNTO 0); + LDA : OUT std_logic; + ADD : OUT std_logic; + SUB : OUT std_logic; + OUTPUT : OUT std_logic; + HLT : OUT std_logic + ); + END COMPONENT; + COMPONENT MAR + PORT ( + CLK : IN std_logic ; + CLR : IN std_logic ; + Lm : IN std_logic ; + D : IN std_logic_vector (3 DOWNTO 0); + Q : OUT std_logic_vector (3 DOWNTO 0) + ); + END COMPONENT; + COMPONENT PC + PORT ( + ep : IN std_logic ; + clr : IN std_logic ; + clk : IN std_logic ; + cp : IN std_logic ; + q : OUT std_logic_vector (3 DOWNTO 0) + ); + END COMPONENT; + COMPONENT ROM_16_8 + PORT ( + read : IN std_logic ; + address : IN std_logic_vector (3 DOWNTO 0); + data_out : OUT std_logic_vector (7 DOWNTO 0) + ); + END COMPONENT; + COMPONENT O + PORT ( + d : IN std_logic_vector (7 DOWNTO 0); + q : OUT std_logic_vector (7 DOWNTO 0); + clk : IN std_logic ; + clr : IN std_logic ; + lo : IN std_logic + ); + END COMPONENT; + +BEGIN + + -- HDL Embedded Text Block 1 eb1 + Cp <= con(11); + Ep <= con(10); + Lm <= con(9); + Ce <= con(8); + Li <= con(7); + Ei <= con(6); + La <= con(5); + Ea <= con(4); + Su <= con(3); + Eu <= con(2); + Lb <= con(1); + Lo <= con(0); + + -- HDL Embedded Text Block 2 eb2 + w(3 downto 0) <= q; + + -- HDL Embedded Text Block 3 eb3 + w(3 downto 0) <= q_w; + + -- HDL Embedded Text Block 4 eb4 + D <= w(3 downto 0); + + -- Instance port mappings. + Accumulator : AC + PORT MAP ( + d => W, + q_alu => q_alu, + q_data => d1, + clk => clk, + ea => ea, + clr => clr, + la => la + ); + AddSub : ALU + PORT MAP ( + A => q_alu, + B => q1, + S => W, + Su => Su, + Eu => Eu + ); + BReg : B_Reg + PORT MAP ( + d => W, + q => q1, + clk => clk, + clr => clr, + lb => lb + ); + CPU : CU + PORT MAP ( + ADD => add, + CLK => clk, + CLR => clr, + LDA => lda, + O => output, + SUB => sub, + con => con + ); + IRReg : IR + PORT MAP ( + clk => clk, + clr => clr, + li => li, + ei => ei, + d => W, + q_w => q_w, + q_c => q_c + ); + IRDecoder : IRDec + PORT MAP ( + q_c => q_c, + lda => lda, + add => add, + sub => sub, + output => output, + hlt => hlt + ); + MemoryAddressReg : MAR + PORT MAP ( + CLK => clk, + CLR => clr, + Lm => Lm, + D => D, + Q => Q2 + ); + ProgramCounter : PC + PORT MAP ( + ep => ep, + clr => clr, + clk => clk, + cp => cp, + q => q + ); + ROM : ROM_16_8 + PORT MAP ( + read => Ce, + address => Q2, + data_out => W + ); + OReg : O + PORT MAP ( + d => d1, + q => q3, + clk => clk, + clr => clr, + lo => lo + ); + +END struct; \ No newline at end of file diff --git a/designs/encrypted_ip/simon_core/sha3_high_throughput.v b/designs/encrypted_ip/simon_core/sha3_high_throughput.v new file mode 100644 index 000000000..973edc5e5 --- /dev/null +++ b/designs/encrypted_ip/simon_core/sha3_high_throughput.v @@ -0,0 +1,98 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* "is_last" == 0 means byte number is 8, no matter what value "byte_num" is. */ +/* if "in_ready" == 0, then "is_last" should be 0. */ +/* the user switch to next "in" only if "ack" == 1. */ + +`define low_pos(w,b) ((w)*64 + (b)*8) +`define low_pos2(w,b) `low_pos(w,7-b) +`define high_pos(w,b) (`low_pos(w,b) + 7) +`define high_pos2(w,b) (`low_pos2(w,b) + 7) + +module sha3_high_throughput(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready); + input clk, reset; + input [63:0] in; + input in_ready, is_last; + input [2:0] byte_num; + output buffer_full; /* to "user" module */ + output [511:0] out; + output reg out_ready; + + reg state; /* state == 0: user will send more input data + * state == 1: user will not send any data */ + wire [575:0] padder_out, + padder_out_1; /* before reorder byte */ + wire padder_out_ready; + wire f_ack; + wire [1599:0] f_out; + wire f_out_ready; + wire [511:0] out1; /* before reorder byte */ + reg [10:0] i; /* gen "out_ready" */ + genvar w, b; + + assign out1 = f_out[1599:1599-511]; + + always @ (posedge clk) + if (reset) + i <= 0; + else + i <= {i[9:0], state & f_ack}; + + always @ (posedge clk) + if (reset) + state <= 0; + else if (is_last) + state <= 1; + + /* reorder byte ~ ~ */ + generate + for(w=0; w<8; w=w+1) + begin : L0 + for(b=0; b<8; b=b+1) + begin : L1 + assign out[`high_pos(w,b):`low_pos(w,b)] = out1[`high_pos2(w,b):`low_pos2(w,b)]; + end + end + endgenerate + + generate + for(w=0; w<9; w=w+1) + begin : L2 + for(b=0; b<8; b=b+1) + begin : L3 + assign padder_out[`high_pos(w,b):`low_pos(w,b)] = padder_out_1[`high_pos2(w,b):`low_pos2(w,b)]; + end + end + endgenerate + + always @ (posedge clk) + if (reset) + out_ready <= 0; + else if (i[10]) + out_ready <= 1; + + padder_h + padder_h_ (clk, reset, in, in_ready, is_last, byte_num, buffer_full, padder_out_1, padder_out_ready, f_ack); + + f_permutation_h + f_permutation_h_ (clk, reset, padder_out, padder_out_ready, f_ack, f_out, f_out_ready); +endmodule + +`undef low_pos +`undef low_pos2 +`undef high_pos +`undef high_pos2 diff --git a/designs/encrypted_ip/simon_core/sha3_low_throughput.v b/designs/encrypted_ip/simon_core/sha3_low_throughput.v new file mode 100644 index 000000000..5007d84e9 --- /dev/null +++ b/designs/encrypted_ip/simon_core/sha3_low_throughput.v @@ -0,0 +1,100 @@ +/* + * Copyright 2013, Homer Hsing + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* "is_last" == 0 means byte number is 8, no matter what value "byte_num" is. */ +/* if "in_ready" == 0, then "is_last" should be 0. */ +/* the user switch to next "in" only if "ack" == 1. */ + +`define low_pos(w,b) ((w)*64 + (b)*8) +`define low_pos2(w,b) `low_pos(w,7-b) +`define high_pos(w,b) (`low_pos(w,b) + 7) +`define high_pos2(w,b) (`low_pos2(w,b) + 7) + +module sha3_low_throughput(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready); + input clk, reset; + input [31:0] in; + input in_ready, is_last; + input [1:0] byte_num; + output buffer_full; /* to "user" module */ + output [511:0] out; + output reg out_ready; + + reg state; /* state == 0: user will send more input data + * state == 1: user will not send any data */ + wire [575:0] padder_out, + padder_out_1; /* before reorder byte */ + wire padder_out_ready; + wire f_ack; + wire [1599:0] f_out; + wire f_out_ready; + wire [511:0] out1; /* before reorder byte */ + reg [22:0] i; /* gen "out_ready" */ + + genvar w, b; + + assign out1 = f_out[1599:1599-511]; + + always @ (posedge clk) + if (reset) + i <= 0; + else + i <= {i[21:0], state & f_ack}; + + always @ (posedge clk) + if (reset) + state <= 0; + else if (is_last) + state <= 1; + + /* reorder byte ~ ~ */ + generate + for(w=0; w<8; w=w+1) + begin : L0 + for(b=0; b<8; b=b+1) + begin : L1 + assign out[`high_pos(w,b):`low_pos(w,b)] = out1[`high_pos2(w,b):`low_pos2(w,b)]; + end + end + endgenerate + + /* reorder byte ~ ~ */ + generate + for(w=0; w<9; w=w+1) + begin : L2 + for(b=0; b<8; b=b+1) + begin : L3 + assign padder_out[`high_pos(w,b):`low_pos(w,b)] = padder_out_1[`high_pos2(w,b):`low_pos2(w,b)]; + end + end + endgenerate + + always @ (posedge clk) + if (reset) + out_ready <= 0; + else if (i[22]) + out_ready <= 1; + + padder_l + padder_l_ (clk, reset, in, in_ready, is_last, byte_num, buffer_full, padder_out_1, padder_out_ready, f_ack); + + f_permutation_l + f_permutation_l_ (clk, reset, padder_out, padder_out_ready, f_ack, f_out, f_out_ready); +endmodule + +`undef low_pos +`undef low_pos2 +`undef high_pos +`undef high_pos2 diff --git a/designs/encrypted_ip/simon_core/simon_core.v b/designs/encrypted_ip/simon_core/simon_core.v new file mode 100644 index 000000000..c1dbe8590 --- /dev/null +++ b/designs/encrypted_ip/simon_core/simon_core.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Team: Virginia Tech Secure Embedded Systems (SES) Lab +// Implementer: Ege Gulcan +// +// Create Date: 19:14:37 11/13/2013 +// Design Name: +// Module Name: simon_core +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module simon_core(clk,data_in,data_rdy,cipher_out); + +input clk,data_in; +input [1:0] data_rdy; +output cipher_out; + +wire key; +wire [5:0] bit_counter; +wire round_counter_out; + +/* + data_rdy=0 -> Reset, Idle + data_rdy=1 -> Load Plaintext + data_rdy=2 -> Load Key + data_rdy=3 -> Run (keep at 3 while the block cipher is running) +*/ + +simon_datapath_shiftreg datapath(.clk(clk), .data_in(data_in), .data_rdy(data_rdy), .key_in(key), + . cipher_out(cipher_out), .round_counter(round_counter_out), .bit_counter(bit_counter)); + +simon_key_expansion_shiftreg key_exp(.clk(clk), .data_in(data_in), .data_rdy(data_rdy), .key_out(key), .bit_counter(bit_counter), + .round_counter_out(round_counter_out)); + + +endmodule diff --git a/designs/encrypted_ip/simon_core/top.v b/designs/encrypted_ip/simon_core/top.v new file mode 100644 index 000000000..e2fe23e6a --- /dev/null +++ b/designs/encrypted_ip/simon_core/top.v @@ -0,0 +1,125 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11/09/2017 01:44:07 PM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module top( + input clk, + input reset, + input [15:0] sw, + input [4:0] btn, // Not used + output [15:0] led, + output [6:0] seg, // Not used + output dp, // Not used + output [7:0] an // Not used + ); + + wire [7:0] sw2, JA, JB, JC, JD; + + assign btnCpuReset = reset; + assign sw2 = sw[7:0]; + assign JA = sw[15:8]; + assign JB = {btn, sw[15:13]}; + assign JC = {btn ^ sw[12:8], btn[2:0] & sw[2:0]}; + assign JD = {sw[15:8] ^ sw[7:0]}; + + + + wire q; + wire [7:0] q3; + + wire [511:0] sha3_high_out, sha3_low_out; + wire sha3_high_buffer_full, sha3_low_buffer_full, sha3_high_out_ready, sha3_low_out_ready; + + wire cipher_out; + + wire [49:0] total_in; + + assign total_in = {sw2, JA, JB, JC, JD}; + + random_pulse_generator random_pulse_generator_0( + .clk(clk), + .ce(1'b1), + .rst(btnCpuReset), + .q(q) + ); + + // sap sap_0( + // .clk(clk), + // .clr(btnCpuReset), + // .hlt(1'b0), + // .q3(q3) + // ); + + sha3_high_throughput sha3_high_throughput_0( + .clk(clk), + .reset(btnCpuReset), + .in({total_in[13:0], total_in}), + .in_ready(sw2[0]), + .is_last(sw2[1]), + .byte_num(JA[2:0]), + .buffer_full(sha3_high_buffer_full), + .out(sha3_high_out), + .out_ready(sha3_high_out_ready) + ); + + // sha3_low_throughput sha3_low_throughput_0( + // .clk(clk), + // .reset(btnCpuReset), + // .in(total_in[49:18]), + // .in_ready(sw2[0]), + // .is_last(sw2[1]), + // .byte_num(JB[1:0]), + // .buffer_full(sha3_low_buffer_full), + // .out(sha3_low_out), + // .out_ready(sha3_low_out_ready) + // ); + + simon_core simon_core_0( + .clk(clk), + .data_in(sw2[2]), + .data_rdy(JC[1:0]), + .cipher_out(cipher_out) + ); + + reg equal_out, equal_buffer_full, equal_out_ready; + + + always @(posedge clk) begin + equal_out <= 0; + equal_buffer_full <= 0; + equal_out_ready <= 0; + if (sha3_high_out == sha3_low_out) + equal_out <= 1; + if (sha3_high_buffer_full == sha3_low_buffer_full) + equal_buffer_full <= 1; + if (sha3_high_out_ready == sha3_low_out_ready) + equal_out_ready <= 1; + end + + assign led[0] = equal_out; + assign led[1] = equal_buffer_full; + assign led[2] = equal_out_ready; + + assign led[3] = cipher_out; + assign led[4] = q; + assign led[15:8] = q3; + +endmodule From 1448d0cc1a12461ddc0e7af43b2684b7f92ce52c Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Fri, 1 Mar 2024 11:53:52 -0700 Subject: [PATCH 24/25] Fix des3perf top --- designs/encrypted_ip/des3_perf/top.v | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/designs/encrypted_ip/des3_perf/top.v b/designs/encrypted_ip/des3_perf/top.v index 4f946ef53..21d0398ef 100644 --- a/designs/encrypted_ip/des3_perf/top.v +++ b/designs/encrypted_ip/des3_perf/top.v @@ -47,7 +47,10 @@ module top( wire [55:0] key3; wire decrypt; - assign desIn = {4{sw[15:0]}}; + wire [15:0] btn16; + assign btn16 = {btn[0], btn, btn, btn}; + + assign desIn = {sw[15:0], sw ^ btn16, sw & btn16, sw | btn16 }; assign key1 = desIn[63:8]; assign key2 = desIn[60:5]; assign key3 = desIn[55:0]; From 592369085a66ba62d58ef13c1059c1e9c055ca83 Mon Sep 17 00:00:00 2001 From: Jeff Goeders Date: Fri, 1 Mar 2024 19:58:02 -0700 Subject: [PATCH 25/25] runtimes --- bfasst/flows/encrypted_ip.py | 69 +++++++++++++++++++- bfasst/flows/flow_descriptions.yaml | 3 +- bfasst/tools/common/dcp_to_v.tcl.mustache | 7 ++ bfasst/tools/impl/vivado_impl.tcl.mustache | 4 ++ bfasst/tools/synth/vivado_synth.tcl.mustache | 2 +- scripts/run.py | 3 +- third_party/encrypted_ip | 2 +- 7 files changed, 84 insertions(+), 6 deletions(-) diff --git a/bfasst/flows/encrypted_ip.py b/bfasst/flows/encrypted_ip.py index bd7e28635..d2b9b589f 100644 --- a/bfasst/flows/encrypted_ip.py +++ b/bfasst/flows/encrypted_ip.py @@ -26,7 +26,10 @@ def __init__(self, design): # Perform the regular vivado CAD flow self.synth_regular = VivadoSynth(self, design) - VivadoImpl(self, design) + self.impl_regular = VivadoImpl(self, design) + + self.synth_tool_per_ip = {} + self.ip_encrypter_tool_per_ip = {} # Synthesize and encrypt each encrypte IP for ip in self.design_props.encrypted_ip["ip"]: @@ -38,6 +41,7 @@ def __init__(self, design): top=ip_definition, synth_options="-flatten_hierarchy full", ) + self.synth_tool_per_ip[ip_definition] = synth_tool synth_tool.override_build_path( synth_tool.build_path.parent / f"{synth_tool.build_path.name}_{ip_definition}" ) @@ -46,6 +50,7 @@ def __init__(self, design): ip_encrypter_tool = IpEncrypter( self, design, ip_definition, synth_tool.outputs["synth_dcp"] ) + self.ip_encrypter_tool_per_ip[ip_definition] = ip_encrypter_tool # ip_encrypter_tool.override_build_path( # ip_encrypter_tool.build_path.parent # / f"{ip_encrypter_tool.build_path.name}_{ip_definition}" @@ -63,7 +68,7 @@ def __init__(self, design): self.top_synth_tool.verilog.extend(encrypted_ip_paths) # Encrypted IP Shell - EncryptedIpLoader( + self.loader_tool = EncryptedIpLoader( self, design, user_synth_dcp_path=self.top_synth_tool.outputs["synth_dcp"], @@ -72,10 +77,28 @@ def __init__(self, design): def get_top_level_flow_path(self): return pathlib.Path(__file__) + + def parse_runtime(self, log_path, str_identifier): + with open(log_path, 'r') as f: + txt = f.read() + + match = re.search(f"^{str_identifier} start time: (.*)$", txt, re.MULTILINE) + assert match + + # Parse the datetime. Example: Fri Mar 1 08:44:27 AM MST 2024 + start_time = pd.to_datetime(match.group(1), format="%a %b %d %I:%M:%S %p %Z %Y") + + match = re.search(f"^{str_identifier} end time: (.*)$", txt, re.MULTILINE) + assert match + + end_time = pd.to_datetime(match.group(1), format="%a %b %d %I:%M:%S %p %Z %Y") + + return (end_time - start_time).total_seconds() def post_execute(self): print("Running post_execute for EncryptedIP flow") out_csv_path = self.design_build_path / "area_results.csv" + out_csv_runtime_path = self.design_build_path / "runtime_results.csv" # Get regular synthesis results reg_utilization_file = self.synth_regular.outputs["utilization"] @@ -117,3 +140,45 @@ def post_execute(self): ) df.to_csv(out_csv_path, index=False) + + + # Get runtimes + df = pd.DataFrame( + columns=["Instance", "Synth-Regular", "Impl-Regular", "Synth-Encrypted", "Impl-Encrypted", "IP-Encryption"] + ) + synth_regular_runtime = self.parse_runtime(self.synth_regular.build_path / "vivado.log", "Synth") + impl_regular_runtime = self.parse_runtime(self.impl_regular.build_path / "vivado.log", "Impl") + synth_encrypted_runtime = self.parse_runtime(self.top_synth_tool.build_path / "vivado.log", "Synth") + impl_encrypted_runtime = self.parse_runtime(self.loader_tool.build_path / "vivado.log", "Loader impl") + + row = pd.Series({ + "Instance": instance, + "Synth-Regular": synth_regular_runtime, + "Impl-Regular": impl_regular_runtime, + "Synth-Encrypted": synth_encrypted_runtime, + "Impl-Encrypted": impl_encrypted_runtime, + "IP-Encryption": "-", + } + ) + df = pd.concat( + [df, row.to_frame().T], + ) + + for ip in self.design_props.encrypted_ip["ip"]: + synth_encrypted_runtime = self.parse_runtime(self.synth_tool_per_ip[ip["definition"]].build_path / "vivado.log", "Synth") + ip_encryption_runtime = self.parse_runtime(self.ip_encrypter_tool_per_ip[ip["definition"]].build_path / "log.txt", "Encryption") + self.parse_runtime(self.ip_encrypter_tool_per_ip[ip["definition"]].build_path / "vivado.log", "DCP to verilog") + + row = pd.Series({ + "Instance": instance, + "Synth-Regular": "-", + "Impl-Regular": "-", + "Synth-Encrypted": synth_encrypted_runtime, + "Impl-Encrypted": "-", + "IP-Encryption": ip_encryption_runtime, + } + ) + df = pd.concat( + [df, row.to_frame().T], + ) + df.to_csv(out_csv_runtime_path, index=False) + diff --git a/bfasst/flows/flow_descriptions.yaml b/bfasst/flows/flow_descriptions.yaml index b932f315a..c082f5478 100644 --- a/bfasst/flows/flow_descriptions.yaml +++ b/bfasst/flows/flow_descriptions.yaml @@ -95,4 +95,5 @@ flows: class: EncryptedIP external_tools: - vivado - - encrypted_ip \ No newline at end of file + - encrypted_ip + - rapidwright \ No newline at end of file diff --git a/bfasst/tools/common/dcp_to_v.tcl.mustache b/bfasst/tools/common/dcp_to_v.tcl.mustache index 0918d5f4f..70d59ed55 100644 --- a/bfasst/tools/common/dcp_to_v.tcl.mustache +++ b/bfasst/tools/common/dcp_to_v.tcl.mustache @@ -1,3 +1,10 @@ +set timen [exec date] +puts "DCP to verilog start time: $timen" + open_checkpoint {{ dcp }} write_verilog {{ verilog }} -force + +set timen [exec date] +puts "DCP to verilog end time: $timen" + close_project \ No newline at end of file diff --git a/bfasst/tools/impl/vivado_impl.tcl.mustache b/bfasst/tools/impl/vivado_impl.tcl.mustache index 1fe2e842e..741ea35aa 100644 --- a/bfasst/tools/impl/vivado_impl.tcl.mustache +++ b/bfasst/tools/impl/vivado_impl.tcl.mustache @@ -7,9 +7,13 @@ read_xdc {{ . }} {{/xdc}} set_property design_mode GateLvl [current_fileset] +set timen [exec date] +puts "Impl start time: $timen" opt_design place_design route_design +set timen [exec date] +puts "Impl end time: $timen" write_checkpoint -force -file {{ impl_output }}/impl.dcp write_edif -force -file {{ impl_output }}/viv_impl.edf write_verilog -force -file {{ impl_output }}/viv_impl.v diff --git a/bfasst/tools/synth/vivado_synth.tcl.mustache b/bfasst/tools/synth/vivado_synth.tcl.mustache index 501812c41..c1eef45a6 100644 --- a/bfasst/tools/synth/vivado_synth.tcl.mustache +++ b/bfasst/tools/synth/vivado_synth.tcl.mustache @@ -23,7 +23,7 @@ puts "Synth start time: $timen" synth_design -top {{ top }} {{ synth_args }} set timen [exec date] -puts "Synth start time: $timen" +puts "Synth end time: $timen" {{#io}} place_ports report_io -force -file {{ . }} diff --git a/scripts/run.py b/scripts/run.py index 9bb5289ee..5dfb1a1d5 100644 --- a/scripts/run.py +++ b/scripts/run.py @@ -54,7 +54,8 @@ def __run_ninja(self): flow_manager.run_flows() # run the build.ninja file - cmd = ["ninja"] + cmd = ["ninja", "-j1"] + # cmd = ["ninja"] proc = subprocess.Popen(cmd, cwd=ROOT_PATH) proc.communicate() return_code = proc.wait() diff --git a/third_party/encrypted_ip b/third_party/encrypted_ip index b82ae8f0c..c926d6608 160000 --- a/third_party/encrypted_ip +++ b/third_party/encrypted_ip @@ -1 +1 @@ -Subproject commit b82ae8f0c8f86184be2111729ed2b250173da528 +Subproject commit c926d6608c966b457537b40dfb706cf63e435d8a