makefile.in

#
V?=0
ifeq ($(V),0)
Q=@
VERBOSE_SWITCH=
else
Q=
VERBOSE_SWITCH=--verbose
endif
#define the following for modules to be compiled with runtime printf support
#CPPFLAGS += -DUSE_PRINTF

allarchlist = ac701 zedboard zc702 zc706 kc705 vc707 zynq100 v2000t miniitx100 de5 htg4 vsim parallella xsim zybo kc705g2 vc707g2 vcs

export DTOP := $(PWD)   # project directory
export BOARD := $(BOARD)
TOPDIR := $(dir $(realpath $(lastword $(MAKEFILE_LIST))))
CONNECTALDIR=$(TOPDIR)/../connectal
CONNECTALSDIR=$(TOPDIR)/connectal
ATOMICCDIR=$(TOPDIR)/../atomicc
ATOMICC_RUNTIME=$(ATOMICCDIR)/runtime/cpp

VERILOG_LIB_GENERATED := $(TOPDIR)/lib/generated
export VERILOG_LIB := $(VERILOG_LIB_GENERATED) $(VERILOG_LIB_GENERATED)/../verilog
CLANGBASE = $(TOPDIR)/../llvm/build/bin/
CPP = $(CLANGBASE)clang++ 
LLC = $(CLANGBASE)llc
LINK = $(CLANGBASE)llvm-link
CPPFLAGS += -I$(TOPDIR)/lib/ -I$(TOPDIR)/xilinx -I.
CPPFLAGS += -std=c++11 -fno-unwind-tables -fno-use-cxa-atexit -fno-cxx-exceptions
CPPFLAGS += -fblocks -fno-diagnostics-color
CPPFLAGS += -Xclang -disable-lifetime-markers
CPPFLAGS += -I/usr/include/c++/4.2.1 -I/usr/include/c++/5
CPPFLAGS += -I/usr/include/c++/7 -I/usr/include/x86_64-linux-gnu/c++/7
CPPFLAGS += -I/usr/include/c++/5 -I/usr/include/x86_64-linux-gnu/c++/5
CPPFLAGS += -I/usr/include/x86_64-linux-gnu/
#   catch signal SIGSEGV
#   set follow-fork-mode child

#CPPFLAGS += -emit-llvm
#CPPFLAGS += -mllvm -dtrace

############################# for running verilator
#
# To compile/run a test:
#
#     make          (this generates the verilog and cppgen files from the original cpp source)
#     make verilator (this compiles the generated files, both for ubuntu.exe and vlsim)
#     make run      (this runs bin/ubuntu.exe)
#     make clean    (this cleans out the objects/etc that were created by 'make verilator')
#

.PHONY: verilator run clean $(allarchlist)
compile: all

verilator:
	BOARD=verilator make gen
	cd verilator; make

run:
	cd verilator; make run

vcsrun:
	cd vcs; make run

$(allarchlist): %:
ifeq ($(BOARD),)
	$(eval BOARD := $@)
endif
	BOARD=$@ make gen
	cd $@; make

gen:
	$(CONNECTALSDIR)/scripts/makefilegen.py -B$(BOARD) --project-dir $(BOARD) \
	$(foreach f, $(CPPFILES), --source $f) \
	$(foreach f, $(ALL_CPPFILES2), --source2 $f) \
        $(foreach f, $(PRINTF_DATAFILE), --printfdata $f) \
	--nonstrict \
	$(FILEGENFLAGS) \
	$(VERBOSE_SWITCH)
	touch $(BOARD)/Makefile.autotop

clean:
	rm -rf SWSOCK* verilator $(allarchlist) generated/yosys vivado*.jou vivado*.log obj_dir

trace:
	#make
	#make clean
	#VERILATOR_TRACE=--trace make verilator
	#rm -f dump.vcd
	DUMP_VCD=dump.vcd make run
#add to Makefile:
#   FILEGENFLAGS += -DVERILATOR_PROJECT_ARGS="--trace"

tracedump:
	$(ATOMICCDIR)/../verilog-vcd-parser/build/vcd-parse verilator/dump.vcd

dump:
	vivado -mode batch -source $(TOPDIR)/shownets.sh 
	$(ATOMICCDIR)/../verilog-rewrite/verilogRewrite zedboard/layoutnet.v

sby:
	sby -f generated/yosys.sby