-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathverilog.cpp
1603 lines (1542 loc) · 72 KB
/
verilog.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
Copyright (C) 2018, The Connectal Project
This program is free software; you can redistribute it and/or modify
it under the terms of version 2 of the GNU General Public License as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <stdio.h>
#include <stdlib.h> // atol
#include <string.h>
#include <assert.h>
#include "AtomiccIR.h"
#include "common.h"
int trace_global;//= 1;
int trace_assign;//= 1;
int trace_declare;//= 1;
int trace_ports;//= 1;
int trace_connect;//= 1;
int trace_skipped;//= 1;
int trace_mux;//= 1;
typedef struct {
std::string value;
std::string type;
} InterfaceMapType;
std::list<PrintfInfo> printfFormat;
ModList modNew;
std::map<std::string, CondLineType> condLines;
std::map<std::string, SyncPinInfo> syncPins; // SyncFF items needed for PipeInSync instances
std::map<std::string, AssignItem> assignList;
std::map<std::string, std::map<std::string, AssignItem>> condAssignList; // used for 'generate' items
std::map<std::string, std::map<std::string, MuxValueElement>> muxValueList; // used to calculate __phi for multiple assignments
static std::map<std::string, ACCExpr *> methodCommitCondition;
static std::map<std::string, std::map<std::string, MuxValueElement>> enableList;
static std::string generateSection; // for 'generate' regions, this is the top level loop expression, otherwise ''
static std::map<std::string, std::string> mapParam;
static ModList::iterator moduleParameter;
static void traceZero(const char *label)
{
if (trace_assign)
for (auto aitem: assignList) {
std::string temp = aitem.first;
int ind = temp.find('[');
if (ind != -1)
temp = temp.substr(0,ind);
if (aitem.second.value && refList[aitem.first].count == 0)
printf("[%s:%d] %s: ASSIGN %s = %s size %d count %d[%d] pin %d type %s\n", __FUNCTION__, __LINE__, label, aitem.first.c_str(), tree2str(aitem.second.value).c_str(), walkCount(aitem.second.value), refList[aitem.first].count, refList[temp].count, refList[temp].pin, refList[temp].type.c_str());
}
}
static void decRef(std::string name)
{
if (refList[name].count > 0 && refList[name].pin != PIN_MODULE) {
refList[name].count--;
if (trace_assign)
printf("[%s:%d] dec count[%s]=%d\n", __FUNCTION__, __LINE__, name.c_str(), refList[name].count);
}
}
static void setReference(std::string target, int count, std::string type, bool out = false, bool inout = false,
int pin = PIN_WIRE, std::string vecCount = "", bool isArgument = false, std::string clockArg = "CLK:nRST")
{
if (trace_global)
printf("%s: target %s pin %d out %d inout %d type %s veccount %s count %d isArgument %d\n", __FUNCTION__, target.c_str(), pin, out, inout, type.c_str(), vecCount.c_str(), count, isArgument);
if (lookupIR(type) != nullptr || lookupInterface(type) != nullptr || vecCount != "") {
count += 1;
printf("[%s:%d]STRUCT %s type %s vecCount %s\n", __FUNCTION__, __LINE__, target.c_str(), type.c_str(), vecCount.c_str());
}
if (refList[target].pin) {
printf("[%s:%d] %s pin exists %d new %d\n", __FUNCTION__, __LINE__, target.c_str(), refList[target].pin, pin);
exit(-1);
}
refList[target] = RefItem{count, type, out, inout, pin, false, vecCount, isArgument, clockArg};
}
static void setAssign(std::string target, ACCExpr *value, std::string type)
{
bool tDir = refList[target].out;
int tPin = refList[target].pin;
if (!value)
return;
std::string valStr = tree2str(value);
bool sDir = refList[valStr].out;
int sPin = refList[valStr].pin;
if (trace_interface || trace_global)
printf("%s: [%s/%d/%d]count[%d] = %s/%d/%d type '%s'\n", __FUNCTION__, target.c_str(), tDir, tPin, refList[target].count, valStr.c_str(), sDir, sPin, type.c_str());
if (sPin == PIN_OBJECT && tPin != PIN_OBJECT && assignList[valStr].type == "") {
value = allocExpr(target);
target = valStr;
}
if (!refList[target].pin && generateSection == "") {
std::string base = target;
int ind = base.find_first_of(PERIOD "[");
if (ind > 0)
base = base.substr(0, ind);
if (!refList[base].pin) {
printf("[%s:%d] missing target [%s] = %s type '%s'\n", __FUNCTION__, __LINE__, target.c_str(), valStr.c_str(), type.c_str());
exit(-1);
}
}
updateWidth(value, convertType(type));
if (assignList[target].type != "" && assignList[target].value->value != "{") { // aggregate alloca items always start with an expansion expr
printf("[%s:%d] duplicate start [%s] = %s type '%s'\n", __FUNCTION__, __LINE__, target.c_str(), tree2str(value).c_str(), type.c_str());
printf("[%s:%d] duplicate was = %s type '%s'\n", __FUNCTION__, __LINE__, tree2str(assignList[target].value).c_str(), assignList[target].type.c_str());
exit(-1);
}
bool noRecursion = (target == "CLK" || target == "nRST" || isEnaName(target));
if (generateSection != "")
condAssignList[generateSection][target] = AssignItem{value, type, noRecursion, 0};
else
assignList[target] = AssignItem{value, type, noRecursion, 0};
}
static void addRead(MetaSet &list, ACCExpr *cond)
{
if(isIdChar(cond->value[0]))
list.insert(cond->value);
for (auto item: cond->operands)
addRead(list, item);
}
static void walkRead (MethodInfo *MI, ACCExpr *expr, ACCExpr *cond)
{
if (!expr)
return;
for (auto item: expr->operands)
walkRead(MI, item, cond);
if (isIdChar(expr->value[0])) {
fixupAccessible(expr->value);
if (cond && (!expr->operands.size() || expr->operands.front()->value != PARAMETER_MARKER))
addRead(MI->meta[MetaRead][expr->value], cond);
}
}
static void addModulePort (ModList &modParam, std::string name, std::string type, int dir, bool inout, std::string isparam, bool isLocal, bool isArgument, std::string vecCount, MapNameValue &mapValue, std::string instance, bool isParam, bool isTrigger)
{
std::string newtype = instantiateType(type, mapValue);
vecCount = instantiateType(vecCount, mapValue);
if (newtype != type) {
printf("[%s:%d] iinst %s CHECKTYPE %s newtype %s\n", __FUNCTION__, __LINE__, instance.c_str(), type.c_str(), newtype.c_str());
//exit(-1);
type = newtype;
}
int refPin = (instance != "" || isLocal) ? PIN_OBJECT: PIN_MODULE;
if (isParam)
refPin = PIN_CONSTANT;
std::string instName = instance + name;
if (trace_assign || trace_ports || trace_interface)
printf("[%s:%d] instance '%s' iName %s name %s type %s dir %d io %d ispar '%s' isLoc %d pin %d vecCount %s isParam %d\n", __FUNCTION__, __LINE__, instance.c_str(), instName.c_str(), name.c_str(), type.c_str(), dir, inout, isparam.c_str(), isLocal, refPin, vecCount.c_str(), isParam);
fixupAccessible(instName);
if (!isLocal || instance == "") {
setReference(instName, (dir != 0 || inout) && instance == "", type, dir != 0, inout, refPin, vecCount, isArgument);
if(instance == "" && vecCount != "")
refList[instName].done = true; // prevent default blanket assignment generation
}
if (!isLocal) {
if (isparam != "")
modParam.insert(moduleParameter, ModData{name, instName, type, false, "", dir, inout, isTrigger, isparam, vecCount});
else {
modParam.push_back(ModData{name, instName, type, false, "", dir, inout, isTrigger, isparam, vecCount});
if (moduleParameter == modParam.end())
moduleParameter--;
}
}
}
static void collectInterfacePins(ModuleIR *IR, ModList &modParam, std::string instance, std::string pinPrefix, std::string methodPrefix, bool isLocal, MapNameValue &parentMap, bool isPtr, std::string vecCount, bool localInterface, bool isVerilog, bool addInterface, bool aout, MapNameValue &interfaceMap, std::string atype)
{
bool forceInterface = false;
std::string topVecCount = vecCount;
assert(IR);
MapNameValue mapValue = parentMap;
vecCount = instantiateType(vecCount, mapValue);
if (addInterface)
pinPrefix += DOLLAR;
//for (auto item: mapValue)
//printf("[%s:%d] [%s] = %s\n", __FUNCTION__, __LINE__, item.first.c_str(), item.second.c_str());
//printf("[%s:%d] IR %s instance %s pinpref %s methpref %s isLocal %d ptr %d isVerilog %d veccount %s\n", __FUNCTION__, __LINE__, IR->name.c_str(), instance.c_str(), pinPrefix.c_str(), methodPrefix.c_str(), isLocal, isPtr, isVerilog, vecCount.c_str());
if (!localInterface || methodPrefix != "")
for (auto MI: IR->methods) {
std::string name = methodPrefix + MI->name;
bool out = (instance != "") ^ isPtr;
if (MI->async && !localInterface)
syncPins[instance + name] = {"", instance, out != (MI->type != ""), MI};
if (addInterface) {
forceInterface = true;
continue;
}
std::string methodType = MI->type;
if (methodType == "")
methodType = "Bit(1)";
addModulePort(modParam, name, methodType, out != (MI->type != ""), false, ""/*not param*/, isLocal, false/*isArgument*/, vecCount, mapValue, instance, false, MI->action || isEnaName(name) || isRdyName(name));
if (MI->action && !isEnaName(name))
addModulePort(modParam, name + "__ENA", "", out ^ (0), false, ""/*not param*/, isLocal, false/*isArgument*/, vecCount, mapValue, instance, false, true);
if (trace_ports)
printf("[%s:%d] instance %s name '%s' type %s\n", __FUNCTION__, __LINE__, instance.c_str(), name.c_str(), MI->type.c_str());
for (auto pitem: MI->params)
addModulePort(modParam, baseMethodName(name) + DOLLAR + pitem.name, pitem.type, out, false, ""/*not param*/, isLocal, instance==""/*isArgument*/, vecCount, mapValue, instance, false, false);
}
if ((!localInterface || pinPrefix != "") && (pinPrefix == "" || !isVerilog))
for (auto fld: IR->fields) {
if (addInterface && !fld.isInout) {
forceInterface = true;
continue;
}
std::string name = pinPrefix + fld.fldName;
//printf("[%s:%d] name %s ftype %s local %d\n", __FUNCTION__, __LINE__, name.c_str(), fld.type.c_str(), isLocal);
bool out = (instance != "") ^ fld.isOutput;
if (fld.isParameter != "") {
std::string init = fld.isParameter;
if (init == " ") {
init = "\"FALSE\"";
if (fld.type == "FLOAT")
init = "0.0";
else if (fld.isPtr)
init = "0";
else if (startswith(fld.type, "Bit("))
init = "0";
}
if (instance == "")
addModulePort(modParam, name, fld.isPtr ? "POINTER" : fld.type, out, fld.isInout, init, isLocal, true/*isArgument*/, vecCount, mapValue, instance, true, false);
}
else
addModulePort(modParam, name, fld.type, out, fld.isInout, ""/*not param*/, isLocal, instance==""/*isArgument*/, vecCount, mapValue, instance, false, true);
}
for (FieldElement item : IR->interfaces) {
if (addInterface) {
forceInterface = true;
continue;
}
MapNameValue imapValue; // interface hoisting only deals with parameters for the interface itself (not containing module)
//printf("[%s:%d] INTERFACES instance %s type %s name %s\n", __FUNCTION__, __LINE__, instance.c_str(), item.type.c_str(), item.fldName.c_str());
if (instance != "")
extractParam("INTERFACES_" + item.fldName, item.type, imapValue);
bool ptrFlag = isPtr || item.isPtr;
bool out = (instance != "") ^ item.isOutput ^ ptrFlag;
ModuleIR *IIR = lookupInterface(item.type);
if (!IIR) {
printf("%s: in module '%s', interface lookup '%s' name '%s' failed\n", __FUNCTION__, IR->name.c_str(), item.type.c_str(), item.fldName.c_str());
exit(-1);
}
std::string type = item.type;
std::string updatedVecCount = vecCount;
if (item.vecCount != "")
updatedVecCount = item.vecCount;
//printf("[%s:%d] name %s type %s veccc %s updated %s\n", __FUNCTION__, __LINE__, (methodPrefix + item.fldName + DOLLAR).c_str(), type.c_str(), item.vecCount.c_str(), updatedVecCount.c_str());
bool localFlag = isLocal || item.isLocalInterface;
collectInterfacePins(IIR, modParam, instance, pinPrefix + item.fldName, methodPrefix + item.fldName + DOLLAR, localFlag, imapValue, ptrFlag, updatedVecCount, localInterface, isVerilog, item.fldName != "" && !isVerilog, out, mapValue, type);
}
if (forceInterface) {
addModulePort(modParam, methodPrefix.substr(0, methodPrefix.length()-1), atype, aout, false, ""/*not param*/, isLocal, false/*isArgument*/, topVecCount, interfaceMap, instance, false, false);
}
}
static void findCLK(ModuleIR *IR, std::string pinPrefix, bool isVerilog, std::string &handleCLK)
{
if (pinPrefix == "" || !isVerilog)
for (auto fld: IR->fields) {
if (fld.isParameter == "") {
handleCLK = "";
return;
}
}
for (FieldElement item : IR->interfaces) {
ModuleIR *IIR = lookupInterface(item.type);
if (item.fldName == "" || isVerilog)
findCLK(IIR, pinPrefix + item.fldName, isVerilog, handleCLK);
}
}
/*
* Generate verilog module header for class definition or reference
*/
static void generateModuleSignature(std::string moduleName, std::string instance, ModList &modParam, std::string moduleParams, std::string vecCount, std::string &handleCLK)
{
ModuleIR *IR = lookupIR(moduleName);
assert(IR);
ModuleIR *implements = lookupInterface(IR->interfaceName);
assert(implements);
std::string minst;
if (instance != "")
minst = instance.substr(0, instance.length()-1);
std::string moduleInstantiation = moduleName;
int ind = moduleInstantiation.find("(");
if (ind > 0)
moduleInstantiation = moduleInstantiation.substr(0, ind);
if (instance != "")
moduleInstantiation = genericModuleParam(moduleName, moduleParams, nullptr);
findCLK(implements, "", IR->isVerilog, handleCLK);
modParam.push_back(ModData{minst, moduleInstantiation, "", true/*moduleStart*/, handleCLK, 0, false, false, ""/*not param*/, vecCount});
moduleParameter = modParam.end();
MapNameValue mapValue, mapValueMod;
extractParam("SIGNIFC_" + moduleName + ":" + instance, IR->interfaceName, mapValue);
if (instance != "")
extractParam("SIGN_" + moduleName + ":" + instance, moduleName, mapValue); // instance values overwrite duplicate interface values (if present)
else // only substitute parameters from interface definition that were not present in original module definition
extractParam("SIGN_" + moduleName, moduleName, mapValueMod);
for (auto item: mapValueMod) {
auto result = mapValue.find(item.first);
if (result != mapValue.end())
mapValue.erase(result);
}
collectInterfacePins(implements, modParam, instance, "", "", false, mapValue, false, vecCount, false, IR->isVerilog, false, false, mapValue, "");
if (instance == "") {
mapValue.clear();
collectInterfacePins(IR, modParam, instance, "", "", false, mapValue, false, vecCount, true, IR->isVerilog, false, false, mapValue, "");
}
for (FieldElement item : IR->parameters) {
std::string interfaceName = item.fldName;
if (interfaceName != "")
interfaceName += PERIOD;
collectInterfacePins(lookupInterface(item.type), modParam, instance, item.fldName, interfaceName, item.isLocalInterface, mapValue, item.isPtr, item.vecCount, false, IR->isVerilog, false, false, mapValue, "");
}
}
static ACCExpr *walkRemoveParam (ACCExpr *expr)
{
ACCExpr *newExpr = allocExpr(expr->value);
std::string op = expr->value;
if (isIdChar(op[0])) {
int pin = refList[op].pin;
if (refList[op].isArgument) {
//if (trace_assign)
printf("[%s:%d] INFO: reject use of non-state op %s %d\n", __FUNCTION__, __LINE__, op.c_str(), pin);
return nullptr;
}
//assert(refList[op].pin);
}
for (auto oitem: expr->operands) {
ACCExpr *operand = walkRemoveParam(oitem);
if (!operand) {
//continue;
if (relationalOp(op) || op == "!")
return nullptr;
if (booleanBinop(op) || arithOp(op))
continue;
printf("[%s:%d] removedope %s relational %d operator %s orig %s\n", __FUNCTION__, __LINE__, tree2str(oitem).c_str(), relationalOp(op), expr->value.c_str(), tree2str(expr).c_str());
continue;
}
newExpr->operands.push_back(operand);
}
return newExpr;
}
static void walkRef (ACCExpr *expr)
{
bool skipRecursion = false;
if (!expr)
return;
std::string item = expr->value;
if (item == PERIOD) {
item = tree2str(expr);
skipRecursion = true;
}
//printf("[%s:%d]FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF %s count %d pin %d\n", __FUNCTION__, __LINE__, item.c_str(), refList[item].count, refList[item].pin);
if (isIdChar(item[0])) {
if (!startswith(item, "__inst$Genvar") && item != "$past") {
std::string base = item;
int ind = base.find(PERIOD "[");
if (ind > 0)
base = base.substr(0, ind);
if (!refList[item].pin) {
if (base != item) {
if (trace_assign)
printf("[%s:%d] RRRRREFFFF %s -> %s\n", __FUNCTION__, __LINE__, base.c_str(), item.c_str());
if(!refList[base].pin) {
printf("[%s:%d] refList[%s] definition missing\n", __FUNCTION__, __LINE__, item.c_str());
//exit(-1);
}
}
}
}
refList[item].count++;
ACCExpr *temp = assignList[item].value;
if (trace_assign)
printf("[%s:%d] inc count[%s]=%d temp '%s'\n", __FUNCTION__, __LINE__, item.c_str(), refList[item].count, tree2str(temp).c_str());
if (temp && refList[item].count == 1)
walkRef(temp);
}
if (!skipRecursion)
for (auto item: expr->operands)
walkRef(item);
}
static ACCExpr *replaceAssign(ACCExpr *expr, std::string guardName = "")
{
if (!expr)
return expr;
if (trace_assign)
printf("[%s:%d] start %s expr %s\n", __FUNCTION__, __LINE__, guardName.c_str(), tree2str(expr).c_str());
std::string item = expr->value;
if (item == PERIOD)
item = tree2str(expr);
if (guardName != "" && startswith(item, guardName)) {
if (trace_interface)
printf("[%s:%d] remove guard '%s' of called method from enable line %s\n", __FUNCTION__, __LINE__, guardName.c_str(), item.c_str());
return allocExpr("1");
}
if (expr->value == PERIOD || (isIdChar(item[0]) && !expr->operands.size())) {
ACCExpr *assignValue = assignList[item].value;
if (trace_interface)
printf("[%s:%d]item %s norec %d enableList %d value %s walkcount %d\n", __FUNCTION__, __LINE__, item.c_str(), assignList[item].noRecursion, guardName != "", tree2str(assignValue).c_str(), walkCount(assignValue));
if (assignValue)
if (!assignList[item].noRecursion || isdigit(assignValue->value[0]) || guardName != "")
if (walkCount(assignValue) < ASSIGN_SIZE_LIMIT || guardName != "") {
decRef(item);
walkRef(assignValue);
std::string val = tree2str(assignValue);
std::string valContents = tree2str(assignList[val].value);
//if (!isdigit(valContents[0]))
//assignList[val].noRecursion = true; // to prevent ping/pong
if (trace_interface)
printf("[%s:%d] replace %s norec %d with %s\n", __FUNCTION__, __LINE__, item.c_str(), assignList[item].noRecursion, tree2str(assignValue).c_str());
return replaceAssign(assignValue, guardName);
}
}
ACCExpr *newExpr = allocExpr(expr->value);
for (auto item: expr->operands)
if (expr->value == PERIOD) // cannot replace just part of a member specification
newExpr->operands.push_back(item);
else
newExpr->operands.push_back(replaceAssign(item, guardName));
newExpr = cleanupExpr(newExpr, true);
if (trace_assign)
printf("[%s:%d] end %s expr %s\n", __FUNCTION__, __LINE__, guardName.c_str(), tree2str(newExpr).c_str());
return newExpr;
}
static ACCExpr *simpleReplace(ACCExpr *expr)
{
if (!expr)
return expr;
ACCExpr *newExpr = allocExpr(expr->value);
std::string item = expr->value;
if (isIdChar(item[0]) && !expr->operands.size()) {
//printf("[%s:%d] item %s norec %d val %s\n", __FUNCTION__, __LINE__, item.c_str(), assignList[item].noRecursion, tree2str(assignList[item].value).c_str());
ACCExpr *assignValue = assignList[item].value;
if (assignValue)
if (!assignList[item].noRecursion || isdigit(assignValue->value[0]))
if (refList[item].pin != PIN_MODULE
&& (checkOperand(assignValue->value) || isRdyName(item) || isEnaName(item)
|| (startswith(item, BLOCK_NAME) && assignList[item].size < COUNT_LIMIT))) {
std::string val = tree2str(assignValue);
std::string valContents = tree2str(assignList[val].value);
//if (!isdigit(valContents[0]))
//assignList[val].noRecursion = true; // to prevent ping/pong
if (trace_interface)
printf("[%s:%d] replace %s with %s\n", __FUNCTION__, __LINE__, item.c_str(), tree2str(assignValue).c_str());
decRef(item);
walkRef(assignValue);
return simpleReplace(assignValue);
}
}
for (auto oitem: expr->operands)
if (expr->value == PERIOD)
newExpr->operands.push_back(oitem);
else
newExpr->operands.push_back(simpleReplace(oitem));
return newExpr;
}
static void setAssignRefCount(ModuleIR *IR)
{
traceZero("SETASSIGNREF");
// before doing the rest, clean up block guards
for (auto &item : assignList) {
if (item.second.type == "Bit(1)" && startswith(item.first, BLOCK_NAME)) {
item.second.value = simpleReplace(item.second.value);
item.second.size = walkCount(item.second.value);
}
}
for (auto item: assignList) {
//printf("[%s:%d] ref[%s].norec %d value %s\n", __FUNCTION__, __LINE__, item.first.c_str(), assignList[item.first].noRecursion, tree2str(item.second.value).c_str());
assignList[item.first].value = cleanupExpr(simpleReplace(item.second.value));
}
for (auto &ctop : condLines) // process all generate sections
for (auto &alwaysGroup : ctop.second.always)
for (auto &tcond : alwaysGroup.second.cond) {
std::string methodName = tcond.first;
walkRef(tcond.second.guard);
tcond.second.guard = cleanupBool(replaceAssign(methodCommitCondition[methodName]));
if (trace_assign)
printf("[%s:%d] %s: guard %s\n", __FUNCTION__, __LINE__, methodName.c_str(), tree2str(tcond.second.guard).c_str());
auto info = tcond.second.info;
tcond.second.info.clear();
walkRef(tcond.second.guard);
for (auto &item : info) {
ACCExpr *cond = cleanupBool(replaceAssign(item.second.cond));
tcond.second.info[tree2str(cond)] = CondGroupInfo{cond, item.second.info};
walkRef(cond);
for (auto citem: item.second.info) {
if (trace_assign)
printf("[%s:%d] %s: %s dest %s value %s\n", __FUNCTION__, __LINE__, methodName.c_str(),
item.first.c_str(), tree2str(citem.dest).c_str(), tree2str(citem.value).c_str());
if (citem.dest) {
walkRef(citem.value);
walkRef(citem.dest);
}
else
walkRef(citem.value->operands.front());
}
}
}
for (auto &top: muxValueList)
for (auto &item: top.second)
walkRef(item.second.phi);
for (auto item: assignList)
if (item.second.value && refList[item.first].pin == PIN_OBJECT) {
refList[item.first].count++;
if (trace_assign)
printf("[%s:%d] inc count[%s]=%d\n", __FUNCTION__, __LINE__, item.first.c_str(), refList[item.first].count);
}
// Now extend 'was referenced' from assignList items actually referenced
for (auto aitem: assignList) {
std::string temp = aitem.first;
int ind = temp.find('[');
if (ind != -1)
temp = temp.substr(0,ind);
if (aitem.second.value && (refList[aitem.first].count || refList[temp].count))
walkRef(aitem.second.value);
}
if (trace_assign)
for (auto aitem: assignList) {
std::string temp = aitem.first;
int ind = temp.find('[');
if (ind != -1)
temp = temp.substr(0,ind);
if (aitem.second.value)
printf("[%s:%d] ASSIGN %s = %s size %d count %d[%d] pin %d type %s\n", __FUNCTION__, __LINE__, aitem.first.c_str(), tree2str(aitem.second.value).c_str(), walkCount(aitem.second.value), refList[aitem.first].count, refList[temp].count, refList[temp].pin, refList[temp].type.c_str());
}
}
static void appendLine(std::string methodName, ACCExpr *cond, ACCExpr *dest, ACCExpr *value, std::string clockName)
{
dest = replaceAssign(dest);
value = replaceAssign(value);
auto &element = condLines[generateSection].always[ALWAYS_CLOCKED + clockName + ")"].cond[methodName];
for (auto &CI : element.info)
if (matchExpr(cond, CI.second.cond)) {
CI.second.info.push_back(CondInfo{dest, value});
return;
}
element.guard = nullptr;
element.info[tree2str(cond)].cond = cond;
element.info[tree2str(cond)].info.push_back(CondInfo{dest, value});
}
static bool getDirection(std::string &name)
{
std::string orig = name;
bool ret = refList[name].out;
int ind = name.find_first_of(PERIOD "[");
if (ind > 0) {
std::string post = name.substr(ind);
name = name.substr(0, ind);
std::string type = refList[name].type;
ret = refList[name].out;
std::string sub;
if (post[0] == '[') {
int ind = post.find("]");
sub = post.substr(0, ind);
post = post.substr(ind);
}
if (post[0] == '.')
post = post.substr(1);
if (trace_assign || trace_connect || trace_interface)
printf("[%s:%d] name %s post %s sub %s type %s count %d\n", __FUNCTION__, __LINE__, name.c_str(), post.c_str(), sub.c_str(), type.c_str(), refList[name].count);
if (auto IR = lookupInterface(type)) {
for (auto MI: IR->methods) {
if (MI->name == post)
if (MI->type != "") {
//ret = !ret;
}
}
}
//refList[orig].count++;
//refList[orig].out = ret;
}
return ret;
}
static void connectTarget(ACCExpr *target, ACCExpr *source, std::string type, bool isForward)
{
std::string tstr = tree2str(target), sstr = tree2str(source);
std::string tif = tstr, sif = sstr;
// TODO: need to update this to be 'has a return type' (i.e. handle value methods
bool tdir = getDirection(tif) ^ isRdyName(tstr);
bool sdir = getDirection(sif) ^ isRdyName(sstr);
if (trace_assign || trace_connect || trace_interface || (!tdir && !sdir))
printf("%s: IFCCC '%s'/%d/%d pin %d '%s'/%d/%d pin %d\n", __FUNCTION__, tstr.c_str(), tdir, refList[target->value].out, refList[tif].pin, sstr.c_str(), sdir, refList[source->value].out, refList[sif].pin);
if (sdir) {
if (assignList[sstr].type == "")
setAssign(sstr, target, type);
else
printf("[%s:%d] skip assign to %s type %s\n", __FUNCTION__, __LINE__, sstr.c_str(), assignList[sstr].type.c_str());
refList[tif].done = true;
}
else {
if (assignList[tstr].type == "")
setAssign(tstr, source, type);
else
printf("[%s:%d] skip assign to %s type %s\n", __FUNCTION__, __LINE__, tstr.c_str(), assignList[tstr].type.c_str());
refList[sif].done = true;
}
}
static void connectMethodList(std::string interfaceName, ACCExpr *targetTree, ACCExpr *sourceTree, bool isForward)
{
ModuleIR *IIR = lookupInterface(interfaceName);
assert(IIR);
std::string ICtarget = tree2str(targetTree);
std::string ICsource = tree2str(sourceTree);
for (auto MI : IIR->methods) {
ACCExpr *target = dupExpr(targetTree), *source = dupExpr(sourceTree);
if (trace_connect)
printf("[%s:%d] ICtarget '%s' ICsource '%s'\n", __FUNCTION__, __LINE__, ICtarget.c_str(), ICsource.c_str());
if (target->value.length() && target->value.substr(target->value.length()-1) == PERIOD)
target->value = target->value.substr(0, target->value.length()-1);
if (source->value.length() && source->value.substr(source->value.length()-1) == PERIOD)
source->value = source->value.substr(0, source->value.length()-1);
target = allocExpr(PERIOD, target, allocExpr(MI->name));
source = allocExpr(PERIOD, source, allocExpr(MI->name));
std::string tstr = replacePeriod(tree2str(target));
std::string sstr = replacePeriod(tree2str(source));
fixupAccessible(tstr);
fixupAccessible(sstr);
target = allocExpr(tstr);
source = allocExpr(sstr);
//printf("[%s:%d] target %s source %s\n", __FUNCTION__, __LINE__, tstr.c_str(), sstr.c_str());
connectTarget(target, source, MI->type, isForward);
tstr = baseMethodName(tstr) + DOLLAR;
sstr = baseMethodName(sstr) + DOLLAR;
for (auto info: MI->params)
connectTarget(allocExpr(tstr+info.name), allocExpr(sstr+info.name), info.type, isForward);
}
}
static bool verilogInterface(ModuleIR *searchIR, std::string searchStr)
{
int ind = searchStr.find("[");
if (ind > 0) {
std::string sub;
extractSubscript(searchStr, ind, sub);
}
searchStr = replacePeriod(searchStr);
ind = searchStr.find(DOLLAR);
if (ind > 0) {
std::string fieldname = searchStr.substr(0, ind);
for (auto item: searchIR->fields)
if (fieldname == item.fldName) {
if (auto IR = lookupIR(item.type))
return IR->isVerilog;
break;
}
}
return false;
}
static void connectMethods(ModuleIR *IR, std::string ainterfaceName, ACCExpr *targetTree, ACCExpr *sourceTree, bool isForward)
{
std::string interfaceName = ainterfaceName;
if (startswith(interfaceName, "ARRAY_")) {
interfaceName = interfaceName.substr(6);
int ind = interfaceName.find(ARRAY_ELEMENT_MARKER);
if (ind > 0)
interfaceName = interfaceName.substr(ind+1);
}
ModuleIR *IIR = lookupInterface(interfaceName);
if (!IIR) {
printf("[%s:%d] interface not found '%s' target %s source %s\n", __FUNCTION__, __LINE__, interfaceName.c_str(), tree2str(targetTree).c_str(), tree2str(sourceTree).c_str());
}
assert(IIR);
std::string ICtarget = tree2str(targetTree);
std::string ICsource = tree2str(sourceTree);
if (ICsource.find(DOLLAR) != std::string::npos && ICtarget.find(DOLLAR) == std::string::npos) {
ACCExpr *temp = targetTree;
targetTree = sourceTree;
sourceTree = temp;
ICtarget = tree2str(targetTree);
ICsource = tree2str(sourceTree);
}
bool targetIsVerilog = verilogInterface(IR, ICtarget);
bool sourceIsVerilog = verilogInterface(IR, ICsource);
if (trace_connect)
printf("%s: CONNECT target '%s' source '%s' forward %d interfaceName %s\n", __FUNCTION__, ICtarget.c_str(), ICsource.c_str(), isForward, interfaceName.c_str());
for (auto fld : IIR->fields) {
ACCExpr *target = dupExpr(targetTree), *source = dupExpr(sourceTree);
if (target->value == "" || endswith(target->value, DOLLAR) || targetIsVerilog)
target->value += fld.fldName;
else
target = allocExpr(PERIOD, target, allocExpr(fld.fldName));
if (source->value == "" || endswith(source->value, DOLLAR) || sourceIsVerilog)
source->value += fld.fldName;
else
source = allocExpr(PERIOD, source, allocExpr(fld.fldName));
if (ModuleIR *IR = lookupIR(fld.type))
connectMethods(IR, IR->interfaceName, target, source, isForward);
else
connectTarget(target, source, fld.type, isForward);
}
for (auto fld : IIR->interfaces) {
ACCExpr *target = dupExpr(targetTree), *source = dupExpr(sourceTree);
target->value += fld.fldName;
source->value += fld.fldName;
connectMethods(IR, fld.type, target, source, isForward);
}
if (IIR->methods.size())
connectTarget(targetTree, sourceTree, interfaceName, isForward);
}
static void appendMux(std::string section, std::string name, ACCExpr *cond, ACCExpr *value, std::string defaultValue, bool isParam)
{
ACCExpr *phi = muxValueList[section][name].phi;
muxValueList[section][name].isParam = isParam;
if (!phi) {
phi = allocExpr("__phi", allocExpr("("));
muxValueList[section][name].phi = phi;
muxValueList[section][name].defaultValue = defaultValue;
}
if (trace_mux) {
printf("[%s:%d] name %s \n", __FUNCTION__, __LINE__, name.c_str());
dumpExpr("COND", cond);
dumpExpr("VALUE", value);
}
if (!checkInteger(value, "0") || refList[name].type != "Bit(1)")
phi->operands.front()->operands.push_back(allocExpr(":", cond ? cond : allocExpr("1"), value));
}
static void generateMethodGuard(ModuleIR *IR, std::string methodName, MethodInfo *MI)
{
std::string clockName = "CLK:nRST";
if (MI->subscript) // from instantiateFor
methodName += "[" + tree2str(MI->subscript) + "]";
generateSection = MI->generateSection;
MI->guard = cleanupExpr(MI->guard);
if (!isRdyName(methodName)) {
walkRead(MI, MI->guard, nullptr);
if (MI->isRule)
setAssign(getEnaName(methodName), allocExpr(getRdyName(methodName)), "Bit(1)");
}
ACCExpr *guard = MI->guard;
if (MI->type == "Bit(1)") {
guard = cleanupBool(guard);
}
std::string methodSignal = methodName;
if (MI->async && isRdyName(methodName)) {
std::string enaName = getEnaName(methodName);
methodSignal = getRdyName(enaName); // __RDY for one-shot enable
std::string regname = "REGGTEMP_" + methodName;
setReference(methodSignal, 4, "Bit(1)", false, false, PIN_OBJECT);
setReference(regname, 4, "Bit(1)", false, false, PIN_REG); // persistent ACK register
appendLine(enaName, allocExpr("1"), allocExpr(regname), allocExpr("1"), clockName); // set persistent ACK in method instantiation (one shot)
// clear persistent ACK when enable falls
appendLine("", cleanupBool(allocExpr("&&", allocExpr(regname), allocExpr("!", allocExpr(enaName)))), allocExpr(regname), allocExpr("0"), clockName);
setAssign(methodName, cleanupBool(allocExpr("|", allocExpr(methodSignal), allocExpr(regname))), MI->type);
guard = allocExpr("&&", allocExpr("!", allocExpr(regname)), guard); // make one shot
}
setAssign(methodSignal, guard, MI->type); // collect the text of the return value into a single 'assign'
for (auto IC : MI->interfaceConnect)
connectMethods(IR, IC.type, IC.target, IC.source, IC.isForward);
}
static std::string getAsyncControl(ACCExpr *value)
{
std::string controlName = replacePeriod("__CONTROL_" + tree2str(value));
int ind = controlName.find_first_of("{" "[");
if (ind > 0)
controlName = controlName.substr(0, ind);
printf("[%s:%d] %s\n", __FUNCTION__, __LINE__, controlName.c_str());
return controlName;
}
static void generateMethod(ModuleIR *IR, std::string methodName, MethodInfo *MI)
{
ACCExpr *commitCondition = nullptr;
if (MI->subscript) // from instantiateFor
methodName += "[" + tree2str(MI->subscript) + "]";
generateSection = MI->generateSection;
for (auto info: MI->callList) {
if (info->isAsync) {
std::string controlName = getAsyncControl(info->value) + DOLLAR;
commitCondition = allocExpr(controlName + "done");
}
}
for (auto info: MI->storeList) {
std::string dest = info->dest->value;
ACCExpr *cond = info->cond;
ACCExpr *value = info->value;
walkRead(MI, cond, nullptr);
walkRead(MI, value, cond);
updateWidth(value, convertType(refList[dest].type));
if (isIdChar(dest[0]) && !info->dest->operands.size() && refList[dest].pin == PIN_WIRE) {
cond = cleanupBool(allocExpr("&&", allocExpr(methodName), cond));
appendMux(generateSection, dest, cond, value, "0", false);
}
else
appendLine(methodName, cleanupBool(cond), info->dest, value, info->clockName);
}
for (auto info: MI->letList) {
ACCExpr *cond = info->cond;
ACCExpr *value = info->value;
std::string dest = tree2str(info->dest);
std::string root = dest;
int ind = root.find(PERIOD);
if (ind > 0)
root = root.substr(0,ind);
auto alloca = MI->alloca.find(root);
if (alloca == MI->alloca.end()) {
//printf("[%s:%d] LEEEEEEEEEEEEETTTTTTTTTTTTTTTTTTTTTTTTTTTTT not alloca %s\n", __FUNCTION__, __LINE__, root.c_str());
if (isEnaName(methodName))
cond = allocExpr("&&", allocExpr(methodName), cond);
}
cond = cleanupBool(cond);
walkRead(MI, cond, nullptr);
walkRead(MI, value, cond);
updateWidth(value, convertType(info->type));
appendMux(generateSection, dest, cond, value, "0", false);
}
for (auto info: MI->assertList) {
ACCExpr *cond = info->cond;
ACCExpr *value = info->value;
walkRead(MI, cond, nullptr);
walkRead(MI, value, cond);
auto par = value->operands.front()->operands;
ACCExpr *param = cleanupBool(par.front());
par.clear();
par.push_back(param);
ACCExpr *guard = nullptr;
if (MethodInfo *MIRdy = lookupMethod(IR, getRdyName(methodName, MI->async))) {
guard = cleanupBool(MIRdy->guard);
}
ACCExpr *tempCond = guard ? allocExpr("&&", guard, cond) : cond;
tempCond = cleanupBool(tempCond);
std::string calledName = value->value, calledEna = getEnaName(calledName);
condLines[generateSection].assertList.push_back(AssertVerilog{tempCond, value});
}
for (auto info: MI->callList) {
if (!info->isAction)
continue;
ACCExpr *subscript = nullptr;
std::string section = generateSection;
ACCExpr *cond = info->cond;
ACCExpr *value = info->value;
ACCExpr *param = nullptr;
int ind = value->value.find("[");
if (ind > 0) {
std::string sub = value->value.substr(ind+1);
int rind = sub.find("]");
if (rind > 0) {
value->value = value->value.substr(0, ind) + sub.substr(rind+1);
sub = sub.substr(0, rind);
subscript = allocExpr(sub);
}
}
walkRead(MI, value, cond);
if (!(isIdChar(value->value[0]) && value->operands.size()
&& (param = value->operands.back()) && param->value == PARAMETER_MARKER)) {
printf("[%s:%d] incorrectly formed call expression\n", __FUNCTION__, __LINE__);
dumpExpr("READCALL", value);
exit(-1);
}
ACCExpr *callTarget = dupExpr(value);
callTarget->operands.pop_back();
std::string calledName = tree2str(callTarget), calledEna = getEnaName(calledName);
std::string vecCount;
MapNameValue mapValue;
MethodInfo *CI = lookupQualName(IR, calledName, vecCount, mapValue);
if (!CI) {
printf("[%s:%d] method %s not found\n", __FUNCTION__, __LINE__, calledName.c_str());
dumpExpr("CALL", value);
exit(-1);
}
ACCExpr *tempCond = cond;
if (subscript) {
std::string sub, post;
ACCExpr *var = allocExpr(GENVAR_NAME "1");
section = makeSection(var->value, allocExpr("0"),
allocExpr("<", var, allocExpr(vecCount)), allocExpr("+", var, allocExpr("1")));
sub = "[" + var->value + "]";
int ind = calledEna.find_last_of(DOLLAR PERIOD);
if (ind > 0) {
post = calledEna.substr(ind);
calledEna = calledEna.substr(0, ind);
ind = post.rfind(DOLLAR);
printf("[%s:%d] called %s ind %d\n", __FUNCTION__, __LINE__, calledEna.c_str(), ind);
if (ind > 1)
post = post.substr(0, ind) + PERIOD + post.substr(ind+1);
}
calledEna += sub + post;
tempCond = allocExpr("&&", allocExpr("==", subscript, var, tempCond));
}
//printf("[%s:%d] CALLLLLL '%s' condition %s\n", __FUNCTION__, __LINE__, calledName.c_str(), tree2str(tempCond).c_str());
//dumpExpr("CALLCOND", tempCond);
ACCExpr *callCommit = commitCondition;
if (info->isAsync || !callCommit)
callCommit = allocExpr(methodName);
tempCond = cleanupBool(allocExpr("&&", callCommit, tempCond));
tempCond = cleanupBool(replaceAssign(simpleReplace(tempCond), getRdyName(calledEna, MI->async))); // remove __RDY before adding subscript!
walkRead(MI, tempCond, nullptr);
if (calledName == "__finish") {
std::string clockName = "CLK:nRST";
appendLine(methodName, tempCond, nullptr, allocExpr("$finish;"), clockName);
continue;
}
std::string calledSignal = calledEna;
ACCExpr *callEnable = tempCond;
if (info->isAsync) {
std::string controlName = getAsyncControl(value) + DOLLAR;
setAssign(controlName + "CLK", allocExpr("CLK"), "Bit(1)");
setAssign(controlName + "nRST", allocExpr("nRST"), "Bit(1)");
setAssign(controlName + "start", cleanupBool(tempCond), "Bit(1)");
setAssign(controlName + "out", allocExpr(calledEna), "Bit(1)");
setAssign(controlName + "ack", allocExpr(getRdyName(calledEna, info->isAsync)), "Bit(1)");
setAssign(controlName + "clear", commitCondition, "Bit(1)");
callEnable = allocExpr(controlName + "out");
tempCond = allocExpr(calledEna);
}
// Now generate the actual enable signal and pass parameters (both mux'ed)
if (!enableList[section][calledSignal].phi) {
enableList[section][calledSignal].phi = allocExpr("|");
enableList[section][calledSignal].defaultValue = "1'd0";
}
enableList[section][calledSignal].phi->operands.push_back(callEnable);
auto AI = CI->params.begin();
std::string pname = baseMethodName(calledEna) + DOLLAR;
int argCount = CI->params.size();
for (auto item: param->operands) {
if(argCount-- > 0) {
std::string size; // = tree2str(cleanupInteger(cleanupExpr(str2tree(convertType(instantiateType(AI->type, mapValue)))))) + "'d";
appendMux(section, pname + AI->name, tempCond, item, size + "0", true);
AI++;
}
}
MI->meta[MetaInvoke][calledEna].insert(tree2str(cond));
}
if (!implementPrintf)
for (auto info: MI->printfList) {
std::string clockName = "CLK:nRST";
appendLine(methodName, info->cond, nullptr, info->value, clockName);
}
// set global commit condition
if (!commitCondition)
commitCondition = allocExpr("&&", allocExpr(getRdyName(methodName)), allocExpr(methodName));
methodCommitCondition[methodName] = commitCondition;
}
static void generateMethodGroup(ModuleIR *IR, void (*generateMethod)(ModuleIR *IR, std::string methodName, MethodInfo *MI))
{
for (auto MI : IR->methods)
if (MI->generateSection == "")
generateMethod(IR, MI->name, MI);
for (auto MI : IR->methods)
if (MI->generateSection != "")
generateMethod(IR, MI->name, MI);
for (auto MI : IR->methods) {
for (auto item: MI->generateFor) {
MethodInfo *MIb = IR->generateBody[item.body];
assert(MIb && "body item ");
generateMethod(IR, MI->name, MIb);
}
for (auto item: MI->instantiateFor) {
MethodInfo *MIb = IR->generateBody[item.body];
assert(MIb && "body item ");
generateMethod(IR, MI->name, MIb);
}
}
}
static void interfaceAssign(std::string target, ACCExpr *source, std::string type)
{
std::string temp = target;
int ind = temp.find('[');
if (ind != -1)
temp = temp.substr(0,ind);
if (!refList[target].done && source)
if (auto interface = lookupInterface(type)) {
connectMethodList(type, allocExpr(target), source, false);
refList[target].done = true; // mark that assigns have already been output
refList[tree2str(source)].done = true; // mark that assigns have already been output
}
}