From 6987ff5523f2756712e974b2cae147d68bbff169 Mon Sep 17 00:00:00 2001
From: Cedrik Hoffmann <cedrik.hoffmann@jgdperl.com>
Date: Thu, 16 Nov 2023 18:09:05 +0100
Subject: [PATCH] Refactor Registers

---
 .idea/misc.xml                     |  1 -
 src/cpu/cpu.rs                     | 34 +++++++-----------------------
 src/cpu/instructions.rs            |  5 ++++-
 src/cpu/mod.rs                     |  1 +
 src/cpu/registers/mod.rs           |  5 +++--
 src/cpu/registers/register_8bit.rs |  1 +
 src/cpu/registers/stack_pointer.rs |  1 +
 src/memory.rs                      |  5 +++++
 8 files changed, 23 insertions(+), 30 deletions(-)

diff --git a/.idea/misc.xml b/.idea/misc.xml
index 3ce3588..135d454 100644
--- a/.idea/misc.xml
+++ b/.idea/misc.xml
@@ -1,4 +1,3 @@
-<?xml version="1.0" encoding="UTF-8"?>
 <project version="4">
   <component name="MarkdownSettingsMigration">
     <option name="stateVersion" value="1" />
diff --git a/src/cpu/cpu.rs b/src/cpu/cpu.rs
index 1fd12d1..d10a6af 100644
--- a/src/cpu/cpu.rs
+++ b/src/cpu/cpu.rs
@@ -1,4 +1,4 @@
-use crate::cpu::instructions::{JumpCondition, Source16Bit, Target16Bit};
+use crate::cpu::instructions::{JumpCondition, Target16Bit};
 use crate::cpu::registers::{Register8BitName, Registers};
 use crate::memory::Memory;
 
@@ -41,7 +41,8 @@ impl CPU {
                 return self.pc.wrapping_add(1);
             }
             Instruction::LDN(target, source) => {
-                return self.match_16bit_load(&target, source);
+                let value = self.register.get_16bit(source.into());
+                return self.match_16bit_load(&target, value);
             }
         }
     }
@@ -61,23 +62,12 @@ impl CPU {
         return self.pc.wrapping_add(1);
     }
 
-    fn match_16bit_load(&mut self, target: &Target16Bit, source: Source16Bit) -> u16 {
+    fn match_16bit_load(&mut self, target: &Target16Bit, value: u16) -> u16 {
         match target {
-            Target16Bit::BC | Target16Bit::DE | Target16Bit::HL | Target16Bit::SP => {
-                // let value = self.register.get_16bit(source.into());
-                let value = match source {
-                    Source16Bit::BC |
-                    Source16Bit::DE |
-                    Source16Bit::HL |
-                    Source16Bit::SP => self.register.get_16bit(source.into()),
-                    Source16Bit::NN => {
-                        let least_sign_byte = self.memory.read_byte(self.pc + 1) as u16;
-                        let most_sign_byte = self.memory.read_byte(self.pc + 2) as u16;
-                        (most_sign_byte << 8) | least_sign_byte
-                    }
-                };
-                self.register.set_16bit(target.into(), value);
-            }
+            Target16Bit::BC => self.register.set_16bit(target.into(), value),
+            Target16Bit::DE => self.register.set_16bit(target.into(), value),
+            Target16Bit::HL => self.register.set_16bit(target.into(), value),
+            Target16Bit::SP => self.register.set_16bit(target.into(), value),
         }
 
         return self.pc.wrapping_add(3);
@@ -371,11 +361,3 @@ impl CPU {
         }
     }
 }
-
-fn print_missing_register(instruction: &str, target: Target8Bit) {
-    unimplemented!(
-        "Missing instruction {} for register {:?}",
-        instruction,
-        target
-    );
-}
diff --git a/src/cpu/instructions.rs b/src/cpu/instructions.rs
index ee88ad0..08720d7 100644
--- a/src/cpu/instructions.rs
+++ b/src/cpu/instructions.rs
@@ -23,6 +23,7 @@ pub enum Instruction {
     // Load Instructions
     LD(Target8Bit, Target8Bit),
     LDN(Target16Bit, Source16Bit),
+    LDD
 }
 
 #[derive(Debug)]
@@ -46,7 +47,7 @@ pub enum Target16Bit {
     SP,
 }
 
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Copy, Clone)]
 pub enum Source16Bit {
     BC,
     DE,
@@ -333,6 +334,8 @@ impl Instruction {
             0x21 => Some(Instruction::LDN(Target16Bit::HL, Source16Bit::NN)),
             0x31 => Some(Instruction::LDN(Target16Bit::SP, Source16Bit::NN)),
 
+            0x32 => Some(Instruction::LDD),
+
             _ => {
                 eprintln!("[INS] Missing byte Instruction 0x{:x}", byte);
                 None
diff --git a/src/cpu/mod.rs b/src/cpu/mod.rs
index 31c9858..14aa4ec 100644
--- a/src/cpu/mod.rs
+++ b/src/cpu/mod.rs
@@ -1,3 +1,4 @@
 pub mod cpu;
 pub mod instructions;
 pub mod registers;
+pub mod arithmetic;
diff --git a/src/cpu/registers/mod.rs b/src/cpu/registers/mod.rs
index fa3d9e6..026374d 100644
--- a/src/cpu/registers/mod.rs
+++ b/src/cpu/registers/mod.rs
@@ -3,11 +3,12 @@ use super::registers::register::Register;
 use super::registers::register_8bit::Register8Bit;
 use super::registers::stack_pointer::StackPointer;
 
-mod flag_register;
+pub(crate) mod flag_register;
 mod register;
 mod register_8bit;
 mod stack_pointer;
 
+#[derive(Clone)]
 pub struct Registers {
     a: Register8Bit,
     b: Register8Bit,
@@ -104,7 +105,7 @@ impl Registers {
         self.a.set(value);
     }
 
-    pub fn read_a(&mut self) -> u8 {
+    pub fn read_a(&self) -> u8 {
         return self.a.get();
     }
 
diff --git a/src/cpu/registers/register_8bit.rs b/src/cpu/registers/register_8bit.rs
index 76c82c2..4e3375b 100644
--- a/src/cpu/registers/register_8bit.rs
+++ b/src/cpu/registers/register_8bit.rs
@@ -1,5 +1,6 @@
 use super::register::Register;
 
+#[derive(Clone)]
 pub struct Register8Bit {
     name: String,
     value: u8,
diff --git a/src/cpu/registers/stack_pointer.rs b/src/cpu/registers/stack_pointer.rs
index 1550b4b..a81415b 100644
--- a/src/cpu/registers/stack_pointer.rs
+++ b/src/cpu/registers/stack_pointer.rs
@@ -1,5 +1,6 @@
 use super::Register;
 
+#[derive(Clone)]
 pub struct StackPointer {
     name: String,
     value: u16
diff --git a/src/memory.rs b/src/memory.rs
index 00dfeb4..d40e741 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -3,6 +3,7 @@ pub const BOOT_ROM_END: usize = 0xFF;
 pub const BOOT_ROM_SIZE: usize = BOOT_ROM_END - BOOT_ROM_BEGIN + 1;
 
 
+#[derive(Clone)]
 pub struct Memory {
     pub memory: [u8; 0xFFFF],
 }
@@ -30,4 +31,8 @@ impl Memory {
         println!("[MEM] Reading memory: address: 0x{:x} value: 0x{:x}", address, mem_value);
         return mem_value;
     }
+
+    pub fn read_next_word(&self, pc: u16) -> u16 {
+        ((self.read_byte(pc + 2) as u16) << 8) | (self.read_byte(pc + 1) as u16)
+    }
 }