spi_slave_to_avalon_master, Mode 0, data are shiftet one position to the right

[bitlischieber]

In SPI Mode 0 (CPOL=0, CPHA=0 and SSPOL=0), the first 32 Bits are interpreted correct. But the following 32 Data Bits are interpreted as shifted one position to the right. Because of this, the LSB is lost.

The picture below shows the capture of a failed read 4 GPIO state read:

• The first 32 Address- and Read-Bit where just sent.
• SS goes high and low again
• 32 Clock cycles are sent by Master
• The interpreted value is 0x0007 instead of the expected 0x000F.

(CH1/ye = SS, CH2/gn = MOSI, CH3/bl = MISO, CH4/rd = CLK)

As a workaround for this issue, a SPI driver modification was necessary:

• The first 32 Address- and Read-Bit where just sent.
• SS goes high
• SCLK goes also high
• SS goes low
• SCLK goes low
• 32 Clock cycles are sent by Master
• The interpreted value equals now the expected one of 0x000F.