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halide 18.0.0: FTBFS on arm64 with SVE: Unhandled exception: Error: For SVE/SVE2 support, target_vector_bits=<size> must be set in target` #8529

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LebedevRI opened this issue Dec 20, 2024 · 4 comments
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@LebedevRI
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https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1087943

On arm64 systems with SVE support halide fails to build with the following
error:

 [2087/4204] cd /<<PKGBUILDDIR>>-build/build/stage-0/halide/python_bindings/apps && /<<PKGBUILDDIR>>-build/build/stage-0/halide/tutorial/lesson_21_auto_scheduler_generate -r app_aot_bilateral_grid.runtime -o . -e object target=host
 FAILED: python_bindings/apps/app_aot_bilateral_grid.runtime.o /<<PKGBUILDDIR>>-build/build/stage-0/halide/python_bindings/apps/app_aot_bilateral_grid.runtime.o
 cd /<<PKGBUILDDIR>>-build/build/stage-0/halide/python_bindings/apps && /<<PKGBUILDDIR>>-build/build/stage-0/halide/tutorial/lesson_21_auto_scheduler_generate -r app_aot_bilateral_grid.runtime -o . -e object target=host
 Unhandled exception: Error: For SVE/SVE2 support, target_vector_bits=<size> must be set in target.

To check if the system has SVE support:

 $ lscpu | grep sve
 Flags:                              fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs paca pacg dcpodp svei8mm svebf16 i8mm bf16 dgh rng

This is probably essentially a duplicate of #8114.
Has this been resolved in 19.0.0 by any chance?

@alexreinking
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I think this would have been introduced by #8298 when we added SVE support detection. We don't have any SVE-capable hardware, which is why this didn't come up in testing. A quick workaround would be to set Halide_TARGET to something like arm-64-linux-arm_dot_prod-arm_fp16 to skip feature detection for SVE.

Relatedly, it would be nice to have no_-* features so we could write host-no_sve instead.

@steven-johnson -- is it ever appropriate to pick target_vector_bits as part of host detection? Should it be detected only in the runtime compatibility stage, and not in host?

@zvookin
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zvookin commented Dec 20, 2024

Likely the answer is to not turn on any SVE features automatically for compilation. Arguably if computing a target for JIT, it is reasonable, but in that case target_vector_bits should be set as well. Even in the JIT case it will be dicey because real systems are likely to be heterogenous re: CPUs.

At present, the entire family of SVE stuff is a failure as any sort of mass market technology. Use cases are inherently specialized and trying to make it easy to use it is pointless.

@steven-johnson
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Likely the answer is to not turn on any SVE features automatically for compilation

+1

@LebedevRI
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Okay, and what about the #8114 case? I think RISC-V does not have fixed vectors.

@alexreinking alexreinking self-assigned this Dec 20, 2024
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