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At serializer.v line 275, i found that signals tmds and tmds_clock are driven by mutiple signals. It made code unsynthesised and wrong simulation.
It would be helpful if you post your algorithm about this seder
The text was updated successfully, but these errors were encountered:
I had this problem today.In fact, someone else has already asked this question #33 , I use Tang Nano 9K and System Verilog 2017 like Apuder , so I guess maybe you are also using Gowin or even Lichee Tang Nano?
Through simple comparison, I concluded two points:
Apuder added define GOWINSEMImacro to solve this problem.
Zwenergy submitted the modification to Added Gowin serializer. #34 , and added the elsif GW_IDE macro in the serializer.sv file.
Therefore, I think adding define GW_IDE to the first line of the serializer.sv file can make the modification of Zwenergy take effect.In fact , the error has been successfully resolved as I supposed.
At serializer.v line 275, i found that signals
tmds
andtmds_clock
are driven by mutiple signals. It made code unsynthesised and wrong simulation.It would be helpful if you post your algorithm about this seder
The text was updated successfully, but these errors were encountered: