diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir index ca9e05e744be3..9161c810aa23c 100644 --- a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir +++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir @@ -1962,7 +1962,7 @@ func.func @test_tiling_cpu_default(%arg0: tensor<256x256xi8>, %arg1: tensor<256x // ----- #executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "+avx512f", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-linux-gnu"}> -func.func @i1_type_tiling_dispatch_0_elementwise_8_i1() attributes {hal.executable.target = #executable_target_embedded_elf_x86_64_} { +func.func @i1_type() attributes {hal.executable.target = #executable_target_embedded_elf_x86_64_} { %c0 = arith.constant 0 : index %0 = hal.interface.binding.subspan layout(, #hal.pipeline.binding, #hal.pipeline.binding], flags = Indirect>) binding(0) alignment(64) offset(%c0) flags("ReadOnly|Indirect") : !flow.dispatch.tensor> %1 = hal.interface.binding.subspan layout(, #hal.pipeline.binding, #hal.pipeline.binding], flags = Indirect>) binding(1) alignment(64) offset(%c0) flags("ReadOnly|Indirect") : !flow.dispatch.tensor> @@ -1980,6 +1980,6 @@ func.func @i1_type_tiling_dispatch_0_elementwise_8_i1() attributes {hal.executa } // CHECK-DAG: #[[CONFIG:.+]] = #iree_codegen.lowering_config -// CHECK: func @i1_type_tiling_dispatch_0_elementwise_8_i1() +// CHECK: func @i1_type() // CHECK: linalg.generic { // CHECK-SAME: {lowering_config = #[[CONFIG]]}