PCI Header MLBAR (BAR0) Fixed Size

[gersner]

The compliance asserts fixed RW bits to BAR0 while the specification allows vendors to increase the mapped memory region size thus adding more RO bits to the MLBAR Base Address field. Currently specification asserts of 0x3fff RO map, which reflects the default size by specification.

From specification (NVME 1.3b, 2.1.10 MLBAR, Base Address field):

Base address of register memory space. For controllers that support a larger number of doorbell registers or have vendor specific space following the doorbell registers, more bits are allowed to be RO such that more memory space is consumed.