diff --git a/.github/workflows/outputs.yml b/.github/workflows/outputs.yml index 321f454..3d136d0 100644 --- a/.github/workflows/outputs.yml +++ b/.github/workflows/outputs.yml @@ -13,9 +13,11 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 + with: + submodules: true - name: gitmarker run: "for i in *.kicad_pcb; do git rev-parse --short HEAD | xargs -I % sed -i 's/{GITHASH}/%/g' $i; done" # add git marker - - uses: INTI-CMNB/KiBot@v2_k7 + - uses: INTI-CMNB/KiBot@v2_k8 with: # Required - kibot config file config: config.kibot.yaml diff --git a/.github/workflows/prerelease.yml b/.github/workflows/prerelease.yml index 3c0fe1d..e79f249 100644 --- a/.github/workflows/prerelease.yml +++ b/.github/workflows/prerelease.yml @@ -15,12 +15,14 @@ jobs: steps: - name: Checkout code uses: actions/checkout@v4 + with: + submodules: true - name: Set tag hash id: tag run: echo "hash=$(git rev-parse --short HEAD)" >> $GITHUB_OUTPUT - name: gitmarker run: "for i in *.kicad_pcb; do sed -i 's/{GITHASH}/${{ steps.tag.outputs.hash }}/g' $i; done" # add git marker - - uses: INTI-CMNB/KiBot@v2_k7 + - uses: INTI-CMNB/KiBot@v2_k8 with: # Required - kibot config file config: config.kibot.yaml diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 4b1452d..1596685 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -15,12 +15,14 @@ jobs: steps: - name: Checkout code uses: actions/checkout@v4 + with: + submodules: true - name: Set tag hash id: tag run: echo "hash=$(git rev-parse --short HEAD)" >> $GITHUB_OUTPUT - name: gitmarker run: "for i in *.kicad_pcb; do sed -i 's/{GITHASH}/${{ steps.tag.outputs.hash }}/g' $i; done" # add git marker - - uses: INTI-CMNB/KiBot@v2_k7 + - uses: INTI-CMNB/KiBot@v2_k8 with: # Required - kibot config file config: config.kibot.yaml diff --git a/config.kibot.yaml b/config.kibot.yaml index 6f66460..8024529 100644 --- a/config.kibot.yaml +++ b/config.kibot.yaml @@ -27,11 +27,10 @@ filters: regex: 'mount.*hole' preflight: - run_erc: true + erc: true update_xml: true - run_drc: true + drc: true check_zone_fills: false - ignore_unconnected: false global: drc_exclusions_workaround: true diff --git a/rs-probe.kicad_pcb b/rs-probe.kicad_pcb index 539fdf2..9cad8c3 100644 --- a/rs-probe.kicad_pcb +++ b/rs-probe.kicad_pcb @@ -1,37316 +1,42734 @@ -(kicad_pcb (version 20221018) (generator pcbnew) - - (general - (thickness 1.6) - ) - - (paper "A4") - (layers - (0 "F.Cu" signal) - (1 "In1.Cu" signal) - (2 "In2.Cu" signal) - (31 "B.Cu" signal) - (32 "B.Adhes" user "B.Adhesive") - (33 "F.Adhes" user "F.Adhesive") - (34 "B.Paste" user) - (35 "F.Paste" user) - (36 "B.SilkS" user "B.Silkscreen") - (37 "F.SilkS" user "F.Silkscreen") - (38 "B.Mask" user) - (39 "F.Mask" user) - (40 "Dwgs.User" user "User.Drawings") - (41 "Cmts.User" user "User.Comments") - (42 "Eco1.User" user "User.Eco1") - (43 "Eco2.User" user "User.Eco2") - (44 "Edge.Cuts" user) - (45 "Margin" user) - (46 "B.CrtYd" user "B.Courtyard") - (47 "F.CrtYd" user "F.Courtyard") - (48 "B.Fab" user) - (49 "F.Fab" user) - ) - - (setup - (stackup - (layer "F.SilkS" (type "Top Silk Screen")) - (layer "F.Paste" (type "Top Solder Paste")) - (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01)) - (layer "F.Cu" (type "copper") (thickness 0.035)) - (layer "dielectric 1" (type "core") (thickness 0.48) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) - (layer "In1.Cu" (type "copper") (thickness 0.035)) - (layer "dielectric 2" (type "prepreg") (thickness 0.48) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) - (layer "In2.Cu" (type "copper") (thickness 0.035)) - (layer "dielectric 3" (type "core") (thickness 0.48) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) - (layer "B.Cu" (type "copper") (thickness 0.035)) - (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01)) - (layer "B.Paste" (type "Bottom Solder Paste")) - (layer "B.SilkS" (type "Bottom Silk Screen")) - (copper_finish "None") - (dielectric_constraints no) - ) - (pad_to_mask_clearance 0) - (aux_axis_origin 148.5 93) - (grid_origin 148.5 93) - (pcbplotparams - (layerselection 0x00210fe_ffffffff) - (plot_on_all_layers_selection 0x0000000_00000000) - (disableapertmacros false) - (usegerberextensions false) - (usegerberattributes false) - (usegerberadvancedattributes false) - (creategerberjobfile false) - (dashed_line_dash_ratio 12.000000) - (dashed_line_gap_ratio 3.000000) - (svgprecision 6) - (plotframeref false) - (viasonmask false) - (mode 1) - (useauxorigin false) - (hpglpennumber 1) - (hpglpenspeed 20) - (hpglpendiameter 15.000000) - (dxfpolygonmode true) - (dxfimperialunits true) - (dxfusepcbnewfont true) - (psnegative false) - (psa4output false) - (plotreference true) - (plotvalue true) - (plotinvisibletext false) - (sketchpadsonfab false) - (subtractmaskfromsilk true) - (outputformat 1) - (mirror false) - (drillshape 0) - (scaleselection 1) - (outputdirectory "order/") - ) - ) - - (net 0 "") - (net 1 "Net-(D1-RK)") - (net 2 "Net-(D1-GK)") - (net 3 "Net-(D1-BK)") - (net 4 "Net-(D3-A)") - (net 5 "GND") - (net 6 "+3.3V") - (net 7 "+5V") - (net 8 "/T_~{RESET}") - (net 9 "/T_GNDDetect") - (net 10 "/T_VCP_RX") - (net 11 "/T_VCP_TX") - (net 12 "Net-(J1-CC1)") - (net 13 "unconnected-(J1-SBU1-PadA8)") - (net 14 "Net-(J1-CC2)") - (net 15 "/LED1") - (net 16 "/LED2") - (net 17 "/LED3") - (net 18 "/P_SWCLK") - (net 19 "/P_SWDIO") - (net 20 "/T_SWO_TDO") - (net 21 "/T_SWDIO_TMS") - (net 22 "/T_SWDCLK_JCLK") - (net 23 "/T_TDI") - (net 24 "/T_VCC") - (net 25 "/T_VCC_EN") - (net 26 "/T_VCC_MEAS") - (net 27 "/D_FS_N") - (net 28 "/D_FS_P") - (net 29 "/GPIO2") - (net 30 "/GPIO1") - (net 31 "/PROTECTED_5V") - (net 32 "unconnected-(J1-SBU2-PadB8)") - (net 33 "/5V_KEY") - (net 34 "/5V_KEY_EN") - (net 35 "/ADJ_T") - (net 36 "/VS_T") - (net 37 "/TRANS_VCC") - (net 38 "/FUSED_5V") - (net 39 "+1V1") - (net 40 "Net-(C5-Pad1)") - (net 41 "/D_P") - (net 42 "/D_N") - (net 43 "/PWM_VS") - (net 44 "Net-(R2-Pad2)") - (net 45 "/VCP_RX") - (net 46 "unconnected-(J5-~{RESET}-Pad3)") - (net 47 "/DIR_VCP_RX") - (net 48 "/VCP_TX") - (net 49 "unconnected-(J5-SWO-Pad6)") - (net 50 "/DIR_VCP_TX") - (net 51 "/~{RESET}") - (net 52 "/GNDDetect") - (net 53 "Net-(Q1A-D1)") - (net 54 "Net-(U3-~{CS})") - (net 55 "Net-(X1-Tri-State)") - (net 56 "Net-(U12-ADJ{slash}NC)") - (net 57 "/TDI") - (net 58 "/SWO_TDO") - (net 59 "/SWDCLK_JCLK") - (net 60 "/SWDIO_TMS") - (net 61 "/DIR_TDI") - (net 62 "/DIR_SWO_TDO") - (net 63 "/DIR_SWDCLK_JCLK") - (net 64 "/DIR_SWDIO_TMS") - (net 65 "/ADJ2_T") - (net 66 "Net-(U1-B)") - (net 67 "Net-(C23-Pad1)") - (net 68 "Net-(U2-B)") - (net 69 "Net-(U3-DO(IO1))") - (net 70 "Net-(U3-IO2)") - (net 71 "Net-(U3-DI(IO0))") - (net 72 "Net-(U3-CLK)") - (net 73 "Net-(U3-IO3)") - (net 74 "/VS2_T") - (net 75 "/PWM2_VS") - (net 76 "Net-(C29-Pad1)") - (net 77 "Net-(U4-5A)") - (net 78 "Net-(U4-6A)") - (net 79 "Net-(U10-B)") - (net 80 "Net-(U11-B)") - (net 81 "unconnected-(U6-GPIO4-Pad6)") - (net 82 "unconnected-(U6-GPIO7-Pad9)") - (net 83 "unconnected-(U6-GPIO13-Pad16)") - (net 84 "unconnected-(U6-GPIO14-Pad17)") - (net 85 "unconnected-(U6-GPIO15-Pad18)") - (net 86 "Net-(U6-XIN)") - (net 87 "unconnected-(U6-XOUT-Pad21)") - (net 88 "unconnected-(U6-GPIO18-Pad29)") - - (footprint "connectors:PinHeader_2x05_FTSH-105-01-L-DV-K" (layer "F.Cu") - (tstamp 00000000-0000-0000-0000-00005e845a9d) - (at 152.8 87) - (descr "surface-mounted straight pin header, 2x07, 1.27mm pitch, double rows") - (tags "Surface mounted pin header SMD 2x07 1.27mm double row") - (property "LCSC" "C2935458, C150517, C920815") - (property "MFPN" "FTSH-105-01-L-DV-K") - (property "MPN" "") - (property "Sheetfile" "rs-probe.kicad_sch") - (property "Sheetname" "") - (path "/00000000-0000-0000-0000-00005eb7aa49") - (attr smd) - (fp_text reference "U5" (at 0 -4.235) (layer "F.SilkS") hide - (effects (font (size 1 1) (thickness 0.15))) - (tstamp 5364bb32-ae67-4584-b4fa-1da0fb0b819e) - ) - (fp_text value "CortexDebug" (at 0 6.3) (layer "F.Fab") hide - (effects (font (size 1 1) (thickness 0.15))) - (tstamp c43e3862-0e23-46e2-8977-c3425d46cc19) - ) - (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab") - (effects (font (size 1 1) (thickness 0.15))) - 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0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.48) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "In1.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 2" + (type "prepreg") + (thickness 0.48) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "In2.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 3" + (type "core") + (thickness 0.48) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (aux_axis_origin 148.5 93) + (grid_origin 148.5 93) + (pcbplotparams + (layerselection 0x00210fe_ffffffff) + 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"design_settings": { "defaults": { - "board_outline_line_width": 0.09999999999999999, - "copper_line_width": 0.19999999999999998, + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, "copper_text_italic": false, "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, "copper_text_upright": false, - "courtyard_line_width": 0.049999999999999996, + "courtyard_line_width": 0.05, "dimension_precision": 4, "dimension_units": 3, "dimensions": { @@ -21,31 +24,30 @@ "text_position": 0, "units_format": 1 }, - "fab_line_width": 0.09999999999999999, + "fab_line_width": 0.1, "fab_text_italic": false, "fab_text_size_h": 1.0, "fab_text_size_v": 1.0, "fab_text_thickness": 0.15, "fab_text_upright": false, - "other_line_width": 0.09999999999999999, + "other_line_width": 0.1, "other_text_italic": false, "other_text_size_h": 1.0, "other_text_size_v": 1.0, "other_text_thickness": 0.15, "other_text_upright": false, "pads": { - "drill": 0.0, - "height": 6.2, - "width": 6.2 + "drill": 0.762, + "height": 1.524, + "width": 1.524 }, - "silk_line_width": 0.15, + "silk_line_width": 0.1, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, - "silk_text_thickness": 0.15, + "silk_text_thickness": 0.1, "silk_text_upright": false, "zones": { - "45_degree_only": false, "min_clearance": 0.12 } }, @@ -56,15 +58,8 @@ "width": 0.0 } ], - "drc_exclusions": [ - "footprint_type_mismatch|148500000|92000000|00000000-0000-0000-0000-00005f10abfb|00000000-0000-0000-0000-000000000000", - "footprint_type_mismatch|179000000|79000000|00000000-0000-0000-0000-00005f10d3b1|00000000-0000-0000-0000-000000000000", - "footprint_type_mismatch|182000000|93000000|00000000-0000-0000-0000-00005f10ea7f|00000000-0000-0000-0000-000000000000", - "items_not_allowed|152400000|80800000|e8740d46-3138-4171-aa9b-2a40056a49ee|00000000-0000-0000-0000-000000000000", - "lib_footprint_mismatch|172500000|81000000|e7d3cdad-117c-4b04-8f8b-e3b2bc618357|00000000-0000-0000-0000-000000000000" - ], + "drc_exclusions": [], "meta": { - "filename": "board_design_settings.json", "version": 2 }, "rule_severities": { @@ -80,15 +75,17 @@ "duplicate_footprints": "warning", "extra_footprint": "warning", "footprint": "error", - "footprint_type_mismatch": "error", + "footprint_symbol_mismatch": "warning", + "footprint_type_mismatch": "ignore", "hole_clearance": "error", "hole_near_hole": "error", + "holes_co_located": "warning", "invalid_outline": "error", "isolated_copper": "warning", "item_on_disabled_layer": "error", - "items_not_allowed": "error", + "items_not_allowed": "ignore", "length_out_of_range": "error", - "lib_footprint_issues": "ignore", + "lib_footprint_issues": "warning", "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", 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"min_text_height": 0.7999999999999999, + "min_text_height": 0.8, "min_text_thickness": 0.08, - "min_through_hole_diameter": 0.19999999999999998, - "min_track_width": 0.09999999999999999, - "min_via_annular_width": 0.049999999999999996, - "min_via_diameter": 0.39999999999999997, + "min_through_hole_diameter": 0.3, + "min_track_width": 0.0, + "min_via_annular_width": 0.07, + "min_via_diameter": 0.45, "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": true }, "teardrop_options": [ { - "td_allow_use_two_tracks": true, - "td_curve_segcount": 5, - "td_on_pad_in_zone": false, "td_onpadsmd": true, "td_onroundshapesonly": false, "td_ontrackend": false, @@ -154,29 +144,35 @@ ], "teardrop_parameters": [ { + "td_allow_use_two_tracks": true, "td_curve_segcount": 0, "td_height_ratio": 1.0, "td_length_ratio": 0.5, "td_maxheight": 2.0, "td_maxlen": 1.0, + "td_on_pad_in_zone": false, "td_target_name": "td_round_shape", "td_width_to_size_filter_ratio": 0.9 }, { + "td_allow_use_two_tracks": true, "td_curve_segcount": 0, "td_height_ratio": 1.0, "td_length_ratio": 0.5, "td_maxheight": 2.0, "td_maxlen": 1.0, + "td_on_pad_in_zone": false, "td_target_name": "td_rect_shape", "td_width_to_size_filter_ratio": 0.9 }, { + "td_allow_use_two_tracks": true, "td_curve_segcount": 0, "td_height_ratio": 1.0, "td_length_ratio": 0.5, "td_maxheight": 2.0, "td_maxlen": 1.0, + "td_on_pad_in_zone": false, "td_target_name": "td_track_end", "td_width_to_size_filter_ratio": 0.9 } @@ -184,14 +180,46 @@ "track_widths": [ 0.0 ], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, "via_dimensions": [ { "diameter": 0.0, "drill": 0.0 } ], - "zones_allow_external_fillets": false, - "zones_use_no_outline": true + "zones_allow_external_fillets": false + }, + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" }, "layer_presets": [], "viewports": [] @@ -411,6 +439,7 @@ "wire_dangling": "error" } }, + "legacy": [], "libraries": { "pinned_footprint_libs": [], "pinned_symbol_libs": [] @@ -424,9 +453,9 @@ { "bus_width": 12, "clearance": 0.1, - "diff_pair_gap": 0.15, + "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, - "diff_pair_width": 0.2286, + "diff_pair_width": 0.2, "line_style": 0, "microvia_diameter": 0.3, "microvia_drill": 0.1, @@ -434,8 +463,8 @@ "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.1, - "via_diameter": 0.45, - "via_drill": 0.2, + "via_diameter": 0.6, + "via_drill": 0.3, "wire_width": 6 } ], @@ -451,14 +480,118 @@ "gencad": "", "idf": "", "netlist": "", + "plot": "", + "pos_files": "", "specctra_dsn": "", "step": "", + "svg": "", "vrml": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, + "bom_export_filename": "", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + }, + { + "group_by": false, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": false, + "label": "#", + "name": "${ITEM_NUMBER}", + "show": false + }, + { + "group_by": false, + "label": "LCSC", + "name": "LCSC", + "show": false + }, + { + "group_by": false, + "label": "MFPN", + "name": "MFPN", + "show": true + }, + { + "group_by": false, + "label": "MPN", + "name": "MPN", + "show": false + }, + { + "group_by": false, + "label": "Specification", + "name": "Specification", + "show": false + }, + { + "group_by": false, + "label": "Tolerance", + "name": "Tolerance", + "show": false + }, + { + "group_by": false, + "label": "Description", + "name": "Description", + "show": false + } + ], + "filter_string": "", + "group_symbols": true, + "name": "", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, "drawing": { "dashed_lines_dash_length_ratio": 12.0, "dashed_lines_gap_length_ratio": 3.0, @@ -472,7 +605,12 @@ "intersheets_ref_suffix": "", "junction_size_choice": 3, "label_size_ratio": 0.25, - "pin_symbol_size": 25.0, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + "operating_point_overlay_v_precision": 3, + "operating_point_overlay_v_range": "~V", + "overbar_offset_ratio": 1.23, + "pin_symbol_size": 0.0, "text_offset_ratio": 0.08 }, "legacy_lib_dir": "", @@ -480,23 +618,14 @@ "meta": { "version": 1 }, - "net_format_name": "Pcbnew", - "ngspice": { - "fix_include_paths": true, - "fix_passive_vals": false, - "meta": { - "version": 0 - }, - "model_mode": 0, - "workbook_filename": "" - }, + "net_format_name": "", "page_layout_descr_file": "", "plot_directory": "", - "spice_adjust_passive_values": false, "spice_current_sheet_as_root": false, "spice_external_command": "spice \"%I\"", "spice_model_current_sheet_as_root": true, "spice_save_all_currents": false, + "spice_save_all_dissipations": false, "spice_save_all_voltages": false, "subpart_first_id": 65, "subpart_id_separator": 0 @@ -504,7 +633,7 @@ "sheets": [ [ "224768bc-6009-43ba-aa4a-70cbaa15b5a3", - "" + "Root" ] ], "text_variables": {} diff --git a/rs-probe.kicad_sch b/rs-probe.kicad_sch index b891e3c..da08f7e 100644 --- a/rs-probe.kicad_sch +++ b/rs-probe.kicad_sch @@ -1,10013 +1,26900 @@ -(kicad_sch (version 20230121) (generator eeschema) - - (uuid 224768bc-6009-43ba-aa4a-70cbaa15b5a3) - - (paper "A3") - - (title_block - (title "The Rusty Probe") - (date "2022-11-28") - (rev "A") - ) - - (lib_symbols - (symbol "Connector:TestPoint" (pin_numbers hide) (pin_names (offset 0.762) hide) (in_bom yes) (on_board yes) - (property "Reference" "TP" (at 0 6.858 0) - (effects (font (size 1.27 1.27))) - ) - (property "Value" "TestPoint" (at 0 5.08 0) - (effects (font (size 1.27 1.27))) - ) - (property "Footprint" "" (at 5.08 0 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Datasheet" "~" (at 5.08 0 0) - (effects (font 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(justify left bottom)) - (uuid 044de712-d3da-40ed-9c9f-d91ef285c74c) - ) - (text "Target SWD/JTAG port with ESD protection\nand level shifters" - (at 187.96 22.86 0) - (effects (font (size 2.54 2.54)) (justify left bottom)) - (uuid 06665bf8-cef1-4e75-8d5b-1537b3c1b090) - ) - (text "Target voltage feedback \nwith PWM DAC control" (at 287.02 133.35 0) - (effects (font (size 2.54 2.54)) (justify left bottom)) - (uuid 0a79db37-f1d9-40b1-a24d-8bdfb8f637e2) - ) - (text "To see the DAC vs Output voltage, \nsee math/find_resistors.m" - (at 294.64 208.28 0) - (effects (font (size 1.27 1.27)) (justify left bottom)) - (uuid 0f97e3e5-69d9-4dae-9e75-babad5cdb08d) - ) - (text "USB-C port with ESD protection" (at 162.56 222.25 0) - (effects (font (size 2.54 2.54)) (justify left bottom)) - (uuid 3e0392c0-affc-4114-9de5-1f1cfe79418a) - ) - (text "DESIGN NOTE:\nT_VCC is read before \nenabling ower." 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(xy 302.26 157.48) + ) + (stroke + (width 0) + (type default) + ) + (uuid "fd53552e-9d93-4481-b7bd-4af464156914") + ) + (wire + (pts + (xy 99.06 139.7) (xy 102.87 139.7) + ) + (stroke + (width 0) + (type default) + ) + (uuid "fe419d7f-726b-4447-a954-2088df4de2be") + ) + (wire + (pts + (xy 260.35 166.37) (xy 260.35 167.64) + ) + (stroke + (width 0) + (type default) + ) + (uuid "ff626743-bb19-425d-a008-12e38410d501") + ) + (text "Designed by: Emil Fresk\nTwitter / Github: @korken89\nLink: https://github.com/probe-rs/rs-probe" + (exclude_from_sim no) + (at 302.26 266.7 0) + (effects + (font + (size 2.54 2.54) + ) + (justify left bottom) + ) + (uuid "044de712-d3da-40ed-9c9f-d91ef285c74c") + ) + (text "Target SWD/JTAG port with ESD protection\nand level shifters" + (exclude_from_sim no) + (at 187.96 22.86 0) + (effects + (font + (size 2.54 2.54) + ) + (justify left bottom) + ) + (uuid "06665bf8-cef1-4e75-8d5b-1537b3c1b090") + ) + (text "Target voltage feedback \nwith PWM DAC control" + (exclude_from_sim no) + (at 287.02 133.35 0) + (effects + (font + (size 2.54 2.54) + ) + (justify left bottom) + ) + (uuid "0a79db37-f1d9-40b1-a24d-8bdfb8f637e2") + ) + (text "To see the DAC vs Output voltage, \nsee math/find_resistors.m" + (exclude_from_sim no) + (at 294.64 208.28 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "0f97e3e5-69d9-4dae-9e75-babad5cdb08d") + ) + (text "USB-C port with ESD protection" + (exclude_from_sim no) + (at 162.56 222.25 0) + (effects + (font + (size 2.54 2.54) + ) + (justify left bottom) + ) + (uuid "3e0392c0-affc-4114-9de5-1f1cfe79418a") + ) + (text "DESIGN NOTE:\nT_VCC is read before \nenabling ower." + (exclude_from_sim no) + (at 205.74 38.1 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "4e677390-a246-4ca0-954c-746e0870f88f") + ) + (text "Board-edge castellated vias" + (exclude_from_sim no) + (at 278.13 19.05 0) + (effects + (font + (size 2.54 2.54) + ) + (justify left bottom) + ) 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(size 2.54 2.54) + ) + (justify left bottom) + ) + (uuid "9f782c92-a5e8-49db-bfda-752b35522ce4") + ) + (text "DESIGN NOTE:\nProtect T_VCC from \nactive discharge." + (exclude_from_sim no) + (at 255.27 191.77 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "9f919ccd-0cd4-4837-8c42-368b4f3bd191") + ) + (text "DESIGN NOTE:\nHold button during power up\nto enter USB bootloader." + (exclude_from_sim no) + (at 22.86 142.24 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "e502d5d2-0416-4e48-a1cf-c60e27baf7b4") + ) + (text "UART1" + (exclude_from_sim no) + (at 130.81 212.09 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "edef56e1-d8ae-485b-99a7-7240ecdcd162") + ) + (text "LICENSE:\nThis work is licensed under CERN-OHL-P." + (exclude_from_sim no) + (at 302.26 248.92 0) + (effects + (font + (size 2.54 2.54) + ) + (justify left bottom) + ) + (uuid "fc4f0835-889b-4d2e-876e-ca524c79ae62") + ) + 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