From 9deeeb264622b74b6c80a12b46a2b089b9817412 Mon Sep 17 00:00:00 2001 From: Yuanlong Xiao Date: Tue, 8 Oct 2024 15:44:34 -0700 Subject: [PATCH] feat(vck5000 AIE): check in AIE VecAdd benchmark --- README.md | 161 +- benchmarks/for_dev/bandwidth4/Makefile | 4 +- .../{ab_config.json => floorplan_config.json} | 0 .../for_dev/bandwidth4/design/run_tapa.sh | 9 + benchmarks/tapa_flow/bandwidth23/README.md | 2 +- benchmarks/tapa_flow/bandwidth52/README.md | 2 +- .../tapa_flow/bandwidth52/design/run_tapa.sh | 6 +- .../tapa_flow/bloomFilter/b3_8_5_8/Makefile | 3 +- .../tapa_flow/bloomFilter/b3_8_5_8/README.md | 10 +- .../{ab_config.json => floorplan_config.json} | 0 .../tapa_flow/bloomFilter/b5_8_5_8/Makefile | 4 +- .../tapa_flow/bloomFilter/b5_8_5_8/README.md | 10 +- .../{ab_config.json => floorplan_config.json} | 0 .../tapa_flow/bloomFilter/b7_8_4_16/Makefile | 4 +- .../tapa_flow/bloomFilter/b7_8_4_16/README.md | 10 +- .../{ab_config.json => floorplan_config.json} | 0 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benchmarks/tapa_flow/sextans/run_u55c.py delete mode 100644 benchmarks/tapa_flow/stencil_sasa/high_congestion/autobridge_fail rename benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/{run.py/ab_config.json => run_u55c.py/floorplan_config.json} (100%) create mode 100644 benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run_u55c.py/impl_config.json rename benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/{run.py => run_u55c.py}/link_config.ini (100%) rename benchmarks/tapa_flow/stencil_sasa/high_congestion/{run.py => run_u55c.py} (100%) rename benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/{run.py/ab_config.json => run_u55c.py/floorplan_config.json} (100%) create mode 100644 benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run_u55c.py/impl_config.json rename benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/{run.py => run_u55c.py}/link_config.ini (100%) rename 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benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_vadd.cpp create mode 100644 benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_vadd.h create mode 100644 benchmarks/vitis_flow/vck5000_VecAdd/design/cfg/xclbin_overlay.cfg create mode 100644 benchmarks/vitis_flow/vck5000_VecAdd/design/hls/krnl_input_mover.cpp create mode 100644 benchmarks/vitis_flow/vck5000_VecAdd/design/hls/krnl_output_mover.cpp create mode 100644 benchmarks/vitis_flow/vck5000_VecAdd/design/host/host_overlay.cpp create mode 100755 benchmarks/vitis_flow/vck5000_VecAdd/design/host/setup_emu.sh create mode 100644 benchmarks/vitis_flow/vck5000_VecAdd/design/host/xrt.ini create mode 100755 benchmarks/vitis_flow/vck5000_VecAdd/design/scripts/launch_hw_emu.sh create mode 100644 getting_started/aie_source/Makefile create mode 100644 getting_started/aie_source/README.md create mode 100755 getting_started/aie_source/data/bkgen.py create mode 100755 getting_started/aie_source/data/gen.py create mode 100755 getting_started/aie_source/data/matmul.py create mode 100644 getting_started/aie_source/design/aie/VecAdd.cpp create mode 100644 getting_started/aie_source/design/aie/VecAdd.h create mode 100644 getting_started/aie_source/design/aie/add_kernel.cpp create mode 100644 getting_started/aie_source/design/aie/add_kernel.h create mode 100644 getting_started/aie_source/design/aie/common.h create mode 100644 getting_started/aie_source/design/aie/read_mem.cpp create mode 100644 getting_started/aie_source/design/aie/read_mem.h create mode 100644 getting_started/aie_source/design/aie/write_mem.cpp create mode 100644 getting_started/aie_source/design/aie/write_mem.h create mode 100644 getting_started/aie_source/design/config/run_u55c.py/floorplan_config.json create mode 100644 getting_started/aie_source/design/config/run_u55c.py/impl_config.json rename getting_started/{tapa_source/design => aie_source/design/config/run_u55c.py}/link_config.ini (100%) create mode 100644 getting_started/aie_source/design/main.cpp create mode 100644 getting_started/aie_source/run_u55c.py create mode 100644 getting_started/aie_source_gmio/Makefile create mode 100644 getting_started/aie_source_gmio/README.md create mode 100755 getting_started/aie_source_gmio/data/bkgen.py create mode 100755 getting_started/aie_source_gmio/data/gen.py create mode 100755 getting_started/aie_source_gmio/data/matmul.py create mode 100644 getting_started/aie_source_gmio/design/aie/VecAdd.cpp create mode 100644 getting_started/aie_source_gmio/design/aie/VecAdd.h create mode 100644 getting_started/aie_source_gmio/design/aie/add_kernel.cpp create mode 100644 getting_started/aie_source_gmio/design/aie/add_kernel.h create mode 100644 getting_started/aie_source_gmio/design/aie/common.h create mode 100644 getting_started/aie_source_gmio/design/aie/read_mem.cpp create mode 100644 getting_started/aie_source_gmio/design/aie/read_mem.h create mode 100644 getting_started/aie_source_gmio/design/aie/weighted_sum.cc create mode 100644 getting_started/aie_source_gmio/design/aie/weighted_sum.h create mode 100644 getting_started/aie_source_gmio/design/aie/write_mem.cpp create mode 100644 getting_started/aie_source_gmio/design/aie/write_mem.h create mode 100644 getting_started/aie_source_gmio/design/config/run_u55c.py/floorplan_config.json create mode 100644 getting_started/aie_source_gmio/design/config/run_u55c.py/impl_config.json create mode 100644 getting_started/aie_source_gmio/design/config/run_u55c.py/link_config.ini create mode 100644 getting_started/aie_source_gmio/design/main.cpp create mode 100644 getting_started/aie_source_gmio/run_u55c.py create mode 100644 getting_started/tapa_aie_source/Makefile create mode 100644 getting_started/tapa_aie_source/README.md create mode 100644 getting_started/tapa_aie_source/design/VecAdd.cpp create mode 100644 getting_started/tapa_aie_source/design/config/run_u55c.py/floorplan_config.json create mode 100644 getting_started/tapa_aie_source/design/config/run_u55c.py/impl_config.json create mode 100644 getting_started/tapa_aie_source/design/config/run_u55c.py/link_config.ini create mode 100644 getting_started/tapa_aie_source/design/main.cpp create mode 100644 getting_started/tapa_aie_source/flatten-67e77237-VecAdd.cpp create mode 100644 getting_started/tapa_aie_source/run_u55c.py create mode 100644 getting_started/tapa_source/design/config/run_u55c.py/floorplan_config.json create mode 100644 getting_started/tapa_source/design/config/run_u55c.py/impl_config.json create mode 100644 getting_started/tapa_source/design/config/run_u55c.py/link_config.ini delete mode 100644 getting_started/tapa_source/run.py create mode 100644 getting_started/tapa_source/run_u55c.py diff --git a/README.md b/README.md index 011585b8..7d0dbbd7 100644 --- a/README.md +++ b/README.md @@ -30,7 +30,7 @@ git clone https://github.com/rapidstream-org/rapidstream-cookbook.git cd rapidstream-cookbook ``` -You must have RapidStream installed, a valid RapidStream license, and a valid Vivado Design Suite license to download or run the cookbooks. If you are an academic researcher or would like to contribute to this cookbook, please contact us at https://rapidstream-da.com/ for a free RapidStream license. +You must have RapidStream installed from [here](https://tapa.readthedocs.io/en/main/user/installation.html) with a valid RapidStream license, and a valid Vivado Design Suite license to download or run the cookbooks. If you are an academic researcher or would like to contribute to this cookbook, please contact us at https://rapidstream-da.com/ for a free RapidStream license. We recommend using Vivado version 2023.2 or later. Source the Vivado settings script before running the RapidStream Python scripts. For example, to source the Vivado settings script, run the following command: @@ -39,10 +39,11 @@ We recommend using Vivado version 2023.2 or later. Source the Vivado settings sc source /Vivado/2023.2/settings64.sh ``` -All RapidStream Python script recipes (`*.py`) in this cookbook should be executed using the `rapidstream` command. For example, to run `getting_started/mixed_sources/run.py`, use the following command: +We've created a `Makefile` for each recipe in this repository to help you get started quickly. Simply navigate to the specific example directory and run `make` to compile. ```bash -rapidstream getting_started/mixed_sources/run.py +cd getting_started/mixed_sources +make ``` The default branch always matches the latest RapidStream release. Please update your software before using the recipes. @@ -62,6 +63,9 @@ Recipes AMD Vitis Design Mixed Sources Design + + Rapidstream TAPA Design + Custom Devices Custom Vitis Platforms @@ -71,6 +75,78 @@ Recipes + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

TAPA Flow Benchmarks

+ Discover how RapidStream flow streamlines FPGA acceleration design of state-of-the-art architectures, enabling you to achieve optimal performance for performance-critical systems. +
Scientific Computation
DesignDeveloperPlatformsSourcesPurpose
SerpensSong et al.
(FPGA '22)		Vitis U55C XDMATAPA HLSAccelerator for general-purpose sparse-matrix dense-matrix multiplication.
SextansSong et al.
(FPGA '22)		Vitis U55C XDMATAPA HLSAccelerator for general-purpose sparse-matrix dense-matrix multiplication.
CallipeplaSong et al.
(FPGA '22)		Vitis U55C XDMATAPA HLSAccelerator for general-purpose sparse-matrix dense-matrix multiplication.
KNN Digit RecognitionXiao et al.
(FPL '22)		Vitis U55C XDMATAPA HLSK-Nearest Neighbours for Digit Recognition.
Bloom FilterSimon Fraser UniversityVitis U55C XDMATAPA HLSAccelerator for Bloom Filter.
Stencil ApplicationSimon Fraser UniversityVitis U55C XDMATAPA HLSAccelerator for Stencil Application.
KNNSimon Fraser UniversityVitis U55C XDMATAPA HLSAccelerator for K-Nearest-Neighbor.
ORC DecoderSimon Fraser UniversityVitis U55C XDMATAPA HLSAccelerator for ORC Decoder.
+ @@ -169,85 +245,6 @@ Recipes
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

TAPA Flow Benchmarks

- Discover how RapidStream flow streamlines FPGA acceleration design of state-of-the-art architectures, enabling you to achieve optimal performance for performance-critical systems. -
Scientific Computation
DesignDeveloperPlatformsSourcesPurpose
SerpensSong et al.
(FPGA '22)		Vitis U280 XDMATAPA HLSAccelerator for general-purpose sparse-matrix dense-matrix multiplication.
SextansSong et al.
(FPGA '22)		Vitis U250 XDMATAPA HLSAccelerator for general-purpose sparse-matrix dense-matrix multiplication.
CallipeplaSong et al.
(FPGA '22)		Vitis U280 XDMATAPA HLSAccelerator for general-purpose sparse-matrix dense-matrix multiplication.
KNN Digit RecognitionXiao et al.
(FPL '22)		Vitis U280 XDMATAPA HLSK-Nearest Neighbours for Digit Recognition.
Bloom FilterSimon Fraser UniversityVitis U280 XDMATAPA HLSAccelerator for Bloom Filter.
Stencil ApplicationSimon Fraser UniversityVitis U280 XDMATAPA HLSAccelerator for Stencil Application.
KNNSimon Fraser UniversityVitis U280 XDMATAPA HLSAccelerator for K-Nearest-Neighbor.
ORC DecoderSimon Fraser UniversityVitis U280 XDMATAPA HLSAccelerator for ORC Decoder.
Convolutional neural networkWang et al.
(FPGA '21)		Vitis U250 XDMATAPA HLSSystolic array accelerator for a convolutional neural network layer.
- How to Get Help --------------- diff --git a/benchmarks/for_dev/bandwidth4/Makefile b/benchmarks/for_dev/bandwidth4/Makefile index 7a282504..fc95f070 100644 --- a/benchmarks/for_dev/bandwidth4/Makefile +++ b/benchmarks/for_dev/bandwidth4/Makefile @@ -3,9 +3,9 @@ ROOT_DIR := $(shell git rev-parse --show-toplevel) KERNEL_NAME := bandwidth4 -RS_SCRIPT := $(CURDIR)/run.py +RS_SCRIPT := $(CURDIR)/run_vck5000.py SRC_DIR := $(CURDIR)/design -AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json +AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json IMPL_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json LINK_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini FIX_NOC_TCL := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/fix_noc.tcl diff --git a/benchmarks/for_dev/bandwidth4/design/config/run_vck5000.py/ab_config.json b/benchmarks/for_dev/bandwidth4/design/config/run_vck5000.py/floorplan_config.json similarity index 100% rename from benchmarks/for_dev/bandwidth4/design/config/run_vck5000.py/ab_config.json rename to benchmarks/for_dev/bandwidth4/design/config/run_vck5000.py/floorplan_config.json diff --git a/benchmarks/for_dev/bandwidth4/design/run_tapa.sh b/benchmarks/for_dev/bandwidth4/design/run_tapa.sh new file mode 100644 index 00000000..fa89bcfe --- /dev/null +++ b/benchmarks/for_dev/bandwidth4/design/run_tapa.sh @@ -0,0 +1,9 @@ +WORK_DIR=work.out + +tapa compile \ + --top bandwidth4 \ + --part-num xcu55c-fsvh2892-2L-e \ + --clock-period 3.33 \ + -o ${WORK_DIR}/bandwidth4.xo \ + -f src/bandwidth4.cpp \ + 2>&1 | tee tapa.log diff --git a/benchmarks/tapa_flow/bandwidth23/README.md b/benchmarks/tapa_flow/bandwidth23/README.md index 9dc435d9..66231a5e 100644 --- a/benchmarks/tapa_flow/bandwidth23/README.md +++ b/benchmarks/tapa_flow/bandwidth23/README.md @@ -90,7 +90,7 @@ The RapidStream flow for TAPA requires the following key inputs: - **tapa-xo-path**: The path to the tapa-generated `xo` file (bandwidth23.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. - **floorplan-config**: The configure file ([ab_config.json](design/config/run_vck5000.py/ab_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run_vck5000.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **implementation-config**: The configure file ([impl_config.json](design/config/run_vck5000.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_vck5000.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. diff --git a/benchmarks/tapa_flow/bandwidth52/README.md b/benchmarks/tapa_flow/bandwidth52/README.md index a9becda5..6abebf52 100644 --- a/benchmarks/tapa_flow/bandwidth52/README.md +++ b/benchmarks/tapa_flow/bandwidth52/README.md @@ -76,7 +76,7 @@ The RapidStream flow for TAPA requires the following key inputs: - **tapa-xo-path**: The path to the tapa-generated `xo` file (bandwidth52.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. - **floorplan-config**: The configure file ([ab_config.json](design/config/run_vhk158.py/ab_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run_vhk158.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **implementation-config**: The configure file ([impl_config.json](design/config/run_vhk158.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_vhk158.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. diff --git a/benchmarks/tapa_flow/bandwidth52/design/run_tapa.sh b/benchmarks/tapa_flow/bandwidth52/design/run_tapa.sh index 0071559b..4667a689 100644 --- a/benchmarks/tapa_flow/bandwidth52/design/run_tapa.sh +++ b/benchmarks/tapa_flow/bandwidth52/design/run_tapa.sh @@ -1,9 +1,9 @@ WORK_DIR=work.out tapa compile \ - --top data_decoding \ + --top bandwidth52 \ --part-num xcu55c-fsvh2892-2L-e \ --clock-period 3.33 \ - -o ${WORK_DIR}/data_decoding.xo \ - -f src/data_decoder.cpp \ + -o ${WORK_DIR}/bandwidth52.xo \ + -f src/bandwidth52.cpp \ 2>&1 | tee tapa.log diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/Makefile b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/Makefile index 127b982f..798bc3a7 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/Makefile +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/Makefile @@ -4,7 +4,7 @@ ROOT_DIR := $(shell git rev-parse --show-toplevel) KERNEL_NAME := workload RS_SCRIPT := $(CURDIR)/run.py -AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json +AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json IMPL_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json LINK_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini PLATFORM := xilinx_u55c_gen3x16_xdma_3_202210_1 @@ -32,7 +32,6 @@ $(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) --tapa-xo-path $< \ --device-config $(DEVICE_CONFIG) \ --floorplan-config $(AB_CONFIG) \ - --single-reg \ --run-impl \ --implementation-config $(IMPL_CONFIG) \ --connectivity-ini $(LINK_CONFIG) diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/README.md b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/README.md index a24dfc60..5044244b 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/README.md +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -41,10 +41,10 @@ tapa compile \ The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. The RapidStream flow for TAPA requires the following key inputs: -- **tapa-xo-path**: The path to the tapa-generated `xo` file (bandwidth52.xo). +- **tapa-xo-path**: The path to the tapa-generated `xo` file (multistream_MurmurHash3.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. -- **floorplan-config**: The configure file ([ab_config.json](design/config/run.py/ab_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. @@ -55,7 +55,7 @@ You can run the command below or execute `make all` supported by our [Makefile]( rapidstream-tapaopt --work-dir build/run.py \ --tapa-xo-path ../../design/generated/multistream_MurmurHash3.xo \ --device-config build/run.py/device.json \ - --floorplan-config design/config/run.py/ab_config.json \ + --floorplan-config design/config/run.py/floorplan_config.json \ --implementation-config design/config/run.py/impl_config.json \ --connectivity-ini design/config/run.py/link_config.ini ``` diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/config/run.py/ab_config.json b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/config/run.py/floorplan_config.json similarity index 100% rename from benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/config/run.py/ab_config.json rename to benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/config/run.py/floorplan_config.json diff --git a/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/Makefile b/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/Makefile index 080c6a8d..798bc3a7 100644 --- a/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/Makefile +++ b/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/Makefile @@ -4,7 +4,7 @@ ROOT_DIR := $(shell git rev-parse --show-toplevel) KERNEL_NAME := workload RS_SCRIPT := $(CURDIR)/run.py -AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json +AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json IMPL_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json LINK_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini PLATFORM := xilinx_u55c_gen3x16_xdma_3_202210_1 @@ -24,7 +24,6 @@ DEVICE_GEN := $(CURDIR)/gen_device.py all: $(RS_TARGET) cd $(RSPATH) && $(RSPYTHON) $(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG) -c clk_kernel_00_unbuffered_net -p 3.333 - @echo $(SUCCESS) $(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) mkdir -p $(TEMP_DIR) @@ -33,7 +32,6 @@ $(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) --tapa-xo-path $< \ --device-config $(DEVICE_CONFIG) \ --floorplan-config $(AB_CONFIG) \ - --single-reg \ --run-impl \ --implementation-config $(IMPL_CONFIG) \ --connectivity-ini $(LINK_CONFIG) diff --git a/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/README.md b/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/README.md index a24dfc60..5044244b 100644 --- a/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/README.md +++ b/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -41,10 +41,10 @@ tapa compile \ The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. The RapidStream flow for TAPA requires the following key inputs: -- **tapa-xo-path**: The path to the tapa-generated `xo` file (bandwidth52.xo). +- **tapa-xo-path**: The path to the tapa-generated `xo` file (multistream_MurmurHash3.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. -- **floorplan-config**: The configure file ([ab_config.json](design/config/run.py/ab_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. @@ -55,7 +55,7 @@ You can run the command below or execute `make all` supported by our [Makefile]( rapidstream-tapaopt --work-dir build/run.py \ --tapa-xo-path ../../design/generated/multistream_MurmurHash3.xo \ --device-config build/run.py/device.json \ - --floorplan-config design/config/run.py/ab_config.json \ + --floorplan-config design/config/run.py/floorplan_config.json \ --implementation-config design/config/run.py/impl_config.json \ --connectivity-ini design/config/run.py/link_config.ini ``` diff --git a/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/design/config/run.py/ab_config.json b/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/design/config/run.py/floorplan_config.json similarity index 100% rename from benchmarks/tapa_flow/bloomFilter/b5_8_5_8/design/config/run.py/ab_config.json rename to benchmarks/tapa_flow/bloomFilter/b5_8_5_8/design/config/run.py/floorplan_config.json diff --git a/benchmarks/tapa_flow/bloomFilter/b7_8_4_16/Makefile b/benchmarks/tapa_flow/bloomFilter/b7_8_4_16/Makefile index 080c6a8d..798bc3a7 100644 --- a/benchmarks/tapa_flow/bloomFilter/b7_8_4_16/Makefile +++ b/benchmarks/tapa_flow/bloomFilter/b7_8_4_16/Makefile @@ -4,7 +4,7 @@ ROOT_DIR := $(shell git rev-parse --show-toplevel) KERNEL_NAME := workload RS_SCRIPT := $(CURDIR)/run.py -AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json +AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json IMPL_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json LINK_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini PLATFORM := xilinx_u55c_gen3x16_xdma_3_202210_1 @@ -24,7 +24,6 @@ DEVICE_GEN := $(CURDIR)/gen_device.py all: $(RS_TARGET) cd $(RSPATH) && $(RSPYTHON) $(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG) -c clk_kernel_00_unbuffered_net -p 3.333 - @echo $(SUCCESS) $(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) mkdir -p $(TEMP_DIR) @@ -33,7 +32,6 @@ $(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) --tapa-xo-path $< \ --device-config $(DEVICE_CONFIG) \ --floorplan-config $(AB_CONFIG) \ - --single-reg \ --run-impl \ --implementation-config $(IMPL_CONFIG) \ --connectivity-ini $(LINK_CONFIG) diff --git a/benchmarks/tapa_flow/bloomFilter/b7_8_4_16/README.md b/benchmarks/tapa_flow/bloomFilter/b7_8_4_16/README.md index a24dfc60..5044244b 100644 --- a/benchmarks/tapa_flow/bloomFilter/b7_8_4_16/README.md +++ b/benchmarks/tapa_flow/bloomFilter/b7_8_4_16/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -41,10 +41,10 @@ tapa compile \ The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. The RapidStream flow for TAPA requires the following key inputs: -- **tapa-xo-path**: The path to the tapa-generated `xo` file (bandwidth52.xo). +- **tapa-xo-path**: The path to the tapa-generated `xo` file (multistream_MurmurHash3.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. -- **floorplan-config**: The configure file ([ab_config.json](design/config/run.py/ab_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. @@ -55,7 +55,7 @@ You can run the command below or execute `make all` supported by our [Makefile]( rapidstream-tapaopt --work-dir build/run.py \ --tapa-xo-path ../../design/generated/multistream_MurmurHash3.xo \ --device-config build/run.py/device.json \ - --floorplan-config design/config/run.py/ab_config.json \ + --floorplan-config design/config/run.py/floorplan_config.json \ --implementation-config design/config/run.py/impl_config.json \ --connectivity-ini design/config/run.py/link_config.ini ``` diff --git a/benchmarks/tapa_flow/bloomFilter/b7_8_4_16/design/config/run.py/ab_config.json b/benchmarks/tapa_flow/bloomFilter/b7_8_4_16/design/config/run.py/floorplan_config.json similarity index 100% rename from benchmarks/tapa_flow/bloomFilter/b7_8_4_16/design/config/run.py/ab_config.json rename to benchmarks/tapa_flow/bloomFilter/b7_8_4_16/design/config/run.py/floorplan_config.json diff --git a/benchmarks/tapa_flow/callipepla/README.md b/benchmarks/tapa_flow/callipepla/README.md index 93fd938a..5844ff8f 100644 --- a/benchmarks/tapa_flow/callipepla/README.md +++ b/benchmarks/tapa_flow/callipepla/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. [TAPA](https://tapa.readthedocs.io/en/release/overview/overview.html), a dataflow HLS framework, features fast compilation, an expressive programming model, and the ability to generate high-frequency FPGA accelerators. We will guide you through the process using a preconditioned conjugate gradient linear solver application from [Callipepla](https://github.com/linghaosong/Callipepla). The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -36,7 +36,7 @@ tapa compile \ ### Step 2: Define Virtual Device In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each -containing 16 clock regions of logic. In actual implementations, the available slots are reduced +containing 16 clock regions of logic. In actual implementations, the available reousrce of each slot is reduced based on the platform specifics, as some resources are reserved for shell logic. AU55C Device @@ -59,8 +59,8 @@ The RapidStream flow for TAPA requires the following key inputs: - **tapa-xo-path**: The path to the tapa-generated `xo` file (Callipepla.xo.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 1 by calling rapidstream APIs based on platform. -- **floorplan-config**: The configure file ([ab_config.json](design/config/run_u55c.py/ab_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. diff --git a/benchmarks/tapa_flow/digit_recognizer/README.md b/benchmarks/tapa_flow/digit_recognizer/README.md index 910224d2..1c784a5a 100644 --- a/benchmarks/tapa_flow/digit_recognizer/README.md +++ b/benchmarks/tapa_flow/digit_recognizer/README.md @@ -60,10 +60,11 @@ cd build/run_u55c.py && tapa compile \ 2>&1 | tee tapa.log ``` + ### Step 2: Define Virtual Device In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each -containing 16 clock regions of logic. In actual implementations, the available slots are reduced +containing 16 clock regions of logic. In actual implementations, the available reousrce of each slot is reduced based on the platform specifics, as some resources are reserved for shell logic. AU55C Device @@ -85,7 +86,7 @@ The RapidStream flow for TAPA requires the following key inputs: - **tapa-xo-path**: The path to the tapa-generated `xo` file (digit_recognizer.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. - **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. @@ -104,7 +105,7 @@ rapidstream-tapaopt --work-dir build/run_u55c.py \ If everything is successful, you should at least get one optimized `.xclbin` file. -### Step 3: Check the Group Module Report +### Step 4: Check the Group Module Report RapidStream mandates a clear distinction between communication and computation within user designs. @@ -119,7 +120,7 @@ To generate a report on group types, execute the commands below or `run make sho ```bash rapidstream ../../../../common/util/get_group.py \ - -i build/passes/0-imported.json \ + -i build/passes/1-importer.json \ -o build/module_types.csv ``` diff --git a/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/README.md b/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/README.md index 07eae322..dd94a36d 100644 --- a/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/README.md +++ b/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -39,7 +39,7 @@ cd build/run_u55c.py && tapa compile \ ### Step 2: Define Virtual Device In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each -containing 16 clock regions of logic. In actual implementations, the available slots are reduced +containing 16 clock regions of logic. In actual implementations, the available resource of each slot is reduced based on the platform specifics, as some resources are reserved for shell logic. AU55C Device @@ -58,10 +58,10 @@ rapidstream run_u55c.py The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. The RapidStream flow for TAPA requires the following key inputs: -- **tapa-xo-path**: The path to the tapa-generated `xo` file (digit_recognizer.xo). +- **tapa-xo-path**: The path to the tapa-generated `xo` file (knn.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. - **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. @@ -70,7 +70,7 @@ You can run the command below or execute `make all` supported by our [Makefile]( ```bash rapidstream-tapaopt --work-dir build/run_u55c.py \ - --tapa-xo-path build/run_u55c.py/digit_recognizer.xo \ + --tapa-xo-path build/run_u55c.py/knn.xo \ --device-config build/run_u55c.py/device.json \ --floorplan-config design/config/run_u55c.py/floorplan_config.json \ --implementation-config design/config/run_u55c.py/impl_config.json \ @@ -96,7 +96,7 @@ To generate a report on group types, execute the commands below or `run make sho ```bash rapidstream ../../../common/util/get_group.py \ - -i build/passes/0-imported.json \ + -i build/passes/1-importer.json \ -o build/module_types.csv ``` diff --git a/benchmarks/tapa_flow/knn_chipknn/k2D_float_15PEs/README.md b/benchmarks/tapa_flow/knn_chipknn/k2D_float_15PEs/README.md index 07eae322..dd94a36d 100644 --- a/benchmarks/tapa_flow/knn_chipknn/k2D_float_15PEs/README.md +++ b/benchmarks/tapa_flow/knn_chipknn/k2D_float_15PEs/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -39,7 +39,7 @@ cd build/run_u55c.py && tapa compile \ ### Step 2: Define Virtual Device In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each -containing 16 clock regions of logic. In actual implementations, the available slots are reduced +containing 16 clock regions of logic. In actual implementations, the available resource of each slot is reduced based on the platform specifics, as some resources are reserved for shell logic. AU55C Device @@ -58,10 +58,10 @@ rapidstream run_u55c.py The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. The RapidStream flow for TAPA requires the following key inputs: -- **tapa-xo-path**: The path to the tapa-generated `xo` file (digit_recognizer.xo). +- **tapa-xo-path**: The path to the tapa-generated `xo` file (knn.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. - **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. @@ -70,7 +70,7 @@ You can run the command below or execute `make all` supported by our [Makefile]( ```bash rapidstream-tapaopt --work-dir build/run_u55c.py \ - --tapa-xo-path build/run_u55c.py/digit_recognizer.xo \ + --tapa-xo-path build/run_u55c.py/knn.xo \ --device-config build/run_u55c.py/device.json \ --floorplan-config design/config/run_u55c.py/floorplan_config.json \ --implementation-config design/config/run_u55c.py/impl_config.json \ @@ -96,7 +96,7 @@ To generate a report on group types, execute the commands below or `run make sho ```bash rapidstream ../../../common/util/get_group.py \ - -i build/passes/0-imported.json \ + -i build/passes/1-importer.json \ -o build/module_types.csv ``` diff --git a/benchmarks/tapa_flow/knn_chipknn/k2D_float_8PEs/README.md b/benchmarks/tapa_flow/knn_chipknn/k2D_float_8PEs/README.md index 07eae322..dd94a36d 100644 --- a/benchmarks/tapa_flow/knn_chipknn/k2D_float_8PEs/README.md +++ b/benchmarks/tapa_flow/knn_chipknn/k2D_float_8PEs/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -39,7 +39,7 @@ cd build/run_u55c.py && tapa compile \ ### Step 2: Define Virtual Device In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each -containing 16 clock regions of logic. In actual implementations, the available slots are reduced +containing 16 clock regions of logic. In actual implementations, the available resource of each slot is reduced based on the platform specifics, as some resources are reserved for shell logic. AU55C Device @@ -58,10 +58,10 @@ rapidstream run_u55c.py The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. The RapidStream flow for TAPA requires the following key inputs: -- **tapa-xo-path**: The path to the tapa-generated `xo` file (digit_recognizer.xo). +- **tapa-xo-path**: The path to the tapa-generated `xo` file (knn.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. - **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. @@ -70,7 +70,7 @@ You can run the command below or execute `make all` supported by our [Makefile]( ```bash rapidstream-tapaopt --work-dir build/run_u55c.py \ - --tapa-xo-path build/run_u55c.py/digit_recognizer.xo \ + --tapa-xo-path build/run_u55c.py/knn.xo \ --device-config build/run_u55c.py/device.json \ --floorplan-config design/config/run_u55c.py/floorplan_config.json \ --implementation-config design/config/run_u55c.py/impl_config.json \ @@ -96,7 +96,7 @@ To generate a report on group types, execute the commands below or `run make sho ```bash rapidstream ../../../common/util/get_group.py \ - -i build/passes/0-imported.json \ + -i build/passes/1-importer.json \ -o build/module_types.csv ``` diff --git a/benchmarks/tapa_flow/knn_chipknn/k64D_8bit_30PEs/README.md b/benchmarks/tapa_flow/knn_chipknn/k64D_8bit_30PEs/README.md index 07eae322..dd94a36d 100644 --- a/benchmarks/tapa_flow/knn_chipknn/k64D_8bit_30PEs/README.md +++ b/benchmarks/tapa_flow/knn_chipknn/k64D_8bit_30PEs/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -39,7 +39,7 @@ cd build/run_u55c.py && tapa compile \ ### Step 2: Define Virtual Device In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each -containing 16 clock regions of logic. In actual implementations, the available slots are reduced +containing 16 clock regions of logic. In actual implementations, the available resource of each slot is reduced based on the platform specifics, as some resources are reserved for shell logic. AU55C Device @@ -58,10 +58,10 @@ rapidstream run_u55c.py The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. The RapidStream flow for TAPA requires the following key inputs: -- **tapa-xo-path**: The path to the tapa-generated `xo` file (digit_recognizer.xo). +- **tapa-xo-path**: The path to the tapa-generated `xo` file (knn.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. - **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. @@ -70,7 +70,7 @@ You can run the command below or execute `make all` supported by our [Makefile]( ```bash rapidstream-tapaopt --work-dir build/run_u55c.py \ - --tapa-xo-path build/run_u55c.py/digit_recognizer.xo \ + --tapa-xo-path build/run_u55c.py/knn.xo \ --device-config build/run_u55c.py/device.json \ --floorplan-config design/config/run_u55c.py/floorplan_config.json \ --implementation-config design/config/run_u55c.py/impl_config.json \ @@ -96,7 +96,7 @@ To generate a report on group types, execute the commands below or `run make sho ```bash rapidstream ../../../common/util/get_group.py \ - -i build/passes/0-imported.json \ + -i build/passes/1-importer.json \ -o build/module_types.csv ``` diff --git a/benchmarks/tapa_flow/knn_chipknn/k64D_8bit_30PEs/design/config/run_u55c.py/floorplan_config.json b/benchmarks/tapa_flow/knn_chipknn/k64D_8bit_30PEs/design/config/run_u55c.py/floorplan_config.json index 5be2b7b5..5c7c3677 100644 --- a/benchmarks/tapa_flow/knn_chipknn/k64D_8bit_30PEs/design/config/run_u55c.py/floorplan_config.json +++ b/benchmarks/tapa_flow/knn_chipknn/k64D_8bit_30PEs/design/config/run_u55c.py/floorplan_config.json @@ -3,7 +3,6 @@ "dse_range_min": 0.7, "partition_strategy": "flat", "port_pre_assignments": { - ".*final_out.*": "HBM[0]", ".*final_out_.*": "HBM[29]", ".*in_0_.*": "HBM[0]", ".*in_10_.*": "HBM[10]", diff --git a/benchmarks/tapa_flow/orcDecoder/README.md b/benchmarks/tapa_flow/orcDecoder/README.md index 33155d25..7b7478cb 100644 --- a/benchmarks/tapa_flow/orcDecoder/README.md +++ b/benchmarks/tapa_flow/orcDecoder/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -41,7 +41,7 @@ cd build/run_u55c.py && tapa compile \ ### Step 2: Define Virtual Device In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each -containing 16 clock regions of logic. In actual implementations, the available slots are reduced +containing 16 clock regions of logic. In actual implementations, the available resource of each slot is reduced based on the platform specifics, as some resources are reserved for shell logic. AU55C Device @@ -60,10 +60,10 @@ rapidstream run_u55c.py The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. The RapidStream flow for TAPA requires the following key inputs: -- **tapa-xo-path**: The path to the tapa-generated `xo` file (digit_recognizer.xo). +- **tapa-xo-path**: The path to the tapa-generated `xo` file (data_decoding.xo). - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. - **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. -- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is the same for vitis link configure file. diff --git a/benchmarks/tapa_flow/serpens/Makefile b/benchmarks/tapa_flow/serpens/Makefile index ea0da5f4..af9324d5 100644 --- a/benchmarks/tapa_flow/serpens/Makefile +++ b/benchmarks/tapa_flow/serpens/Makefile @@ -1,21 +1,47 @@ # Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -ROOT_DIR := $(shell git rev-parse --show-toplevel) -GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py -KRNL_NAME := Serpens -TEMP_DIR := $(CURDIR)/build -RS_TARGET := $(CURDIR)/$(TEMP_DIR)/dse/candidate_3/exported/impl/vitis_run_hw -TAPA_XO := $(CURDIR)/design/generated/$(KRNL_NAME).xo -PLATFORM := xilinx_u280_gen3x16_xdma_1_202211_1 -PART := xcu280-fsvh2892-2L-e -RUN_FILE := $(CURDIR)/run.py +ROOT_DIR := $(shell git rev-parse --show-toplevel) +KERNEL_NAME := Serpens +RS_SCRIPT := $(CURDIR)/run_u55c.py +AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json +IMPL_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json +LINK_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini +PLATFORM := xilinx_u55c_gen3x16_xdma_3_202210_1 +GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py +TEMP_DIR := $(CURDIR)/build/$(notdir $(RS_SCRIPT)) +RS_TARGET := $(TEMP_DIR)/dse/solution_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin +TAPA_XO := $(CURDIR)/design/generated/$(KERNEL_NAME).xo +BUILD_LOG := $(TEMP_DIR)/build.json +SUCCESS := "Build Successful" +TIMING_RPT := impl_1_hw_bb_locked_timing_summary_routed.rpt +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +RSPATH := $(CURDIR) +RSXX := rapidstream +RSPYTHON := rapidstream +DEVICE_CONFIG := $(TEMP_DIR)/device.json +DEVICE_GEN := $(CURDIR)/gen_device.py all: $(RS_TARGET) - -$(RS_TARGET):$(TAPA_XO) - rapidstream $(RUN_FILE) - + cd $(RSPATH) && $(RSPYTHON) $(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG) -c clk_kernel_00_unbuffered_net -p 3.333 + @echo $(SUCCESS) + +$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) $(RS_SCRIPT) + mkdir -p $(TEMP_DIR) + cd $(RSPATH) && $(RSXX)-tapaopt \ + --work-dir $(TEMP_DIR) \ + --tapa-xo-path $< \ + --device-config $(DEVICE_CONFIG) \ + --floorplan-config $(AB_CONFIG) \ + --run-impl \ + --implementation-config $(IMPL_CONFIG) \ + --connectivity-ini $(LINK_CONFIG) + +device: $(DEVICE_CONFIG) + +$(DEVICE_CONFIG):$(RS_SCRIPT) + mkdir -p $(TEMP_DIR) + cd $(RSPATH) && $(RSPYTHON) $< show_groups: rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \ diff --git a/benchmarks/tapa_flow/serpens/README.md b/benchmarks/tapa_flow/serpens/README.md index c9638cbb..eb396abb 100644 --- a/benchmarks/tapa_flow/serpens/README.md +++ b/benchmarks/tapa_flow/serpens/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. [TAPA](https://tapa.readthedocs.io/en/release/overview/overview.html), a dataflow HLS framework, features fast compilation, an expressive programming model, and the ability to generate high-frequency FPGA accelerators. We will guide you through the process using a High bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication from [Serpnes](https://github.com/linghaosong/Serpens). The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -24,118 +24,66 @@ In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. We utilize TAPA to generate the `.xo` file. If you have not installed TAPA, we've already compiled the C++ source to `.xo` using TAPA. The original C++ source files are located in [design/src](design/src). The generated `.xo` file can be found at [design/generated/Serpens.xo](design/generated/Serpens.xo). To compile C++ to `.xo` using TAPA, we use the script [design/run_tapa.sh](design/run_tapa.sh), with the detailed commands shown below. For your convenience, we have also backed up all the generated metadata by TAPA in the [design/generated](design/generated/) directory. ```bash -WORK_DIR=generated - -tapac \ - --work-dir ${WORK_DIR} \ - --top Serpens \ - --part-num xcu280-fsvh2892-2L-e \ - --clock-period 3.33 \ - -o ${WORK_DIR}/Serpens.xo \ - --connectivity design/config/link_config_a24.ini \ - design/src/serpens.cpp \ - 2>&1 | tee ${WORK_DIR}/tapa.log +mkdir -p build/run_u55c.py +cd build/run_u55c.py && tapa compile \ +--top Serpens \ +--part-num xcu55c-fsvh2892-2L-e \ +--clock-period 3.33 \ +-o Serpens.xo \ +-f $< \ +2>&1 | tee tapa.log ``` -### Step 2: Use Rapidstream to Optimize `.xo` Design -The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. -The RapidStream flow for TAPA requires the following key inputs: +### Step 2: Define Virtual Device -- **Platform**: The Vitis platform (e.g., `xilinx_u280_gen3x16_xdma_1_202211_1`). -- **Device**: virtual device define by calling rapidstream APIs based on platform (e.g., `get_u280_vitis_device_factory`). -- **.xo file**: The `.xo` file generated by TAPA -- **Connectivity** (.ini): Include the configuration file for `v++` ([link_config_a24.ini](design/config/link_config_a24.ini)). -- **top_module_name**: Top module name for the kernel. -- **Clock**: All the clock and frequencies. -- **Flatten Module**: Within a design, not all modules need to be optimized. The flatten module name is the target module rapidstream will optimize. - -The Python snippet below shows how we initiate rapidstream instance to set up the rapidstream environment. - -```Python -from rapidstream import get_u280_vitis_device_factory, RapidStreamTAPA -import os - -CURR_DIR = os.path.dirname(os.path.abspath(__file__)) -INI_PATH = f"{CURR_DIR}/design/config/link_config_a24.ini" -VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1" -XO_PATH = f"{CURR_DIR}/design/generated/Sextans.xo" -factory = get_u280_vitis_device_factory(VITIS_PLATFORM) -rs = RapidStreamTAPA(f"{CURR_DIR}build") -rs.set_virtual_device(factory.generate_virtual_device()) -rs.add_xo_file(XO_PATH) -rs.set_vitis_platform(VITIS_PLATFORM) -rs.set_vitis_connectivity_config(INI_PATH) -rs.set_top_module_name("Sextans") -rs.add_clock("ap_clk", 3.33) -rs.add_flatten_targets(["Sextans"]) -``` +In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each +containing 16 clock regions of logic. In actual implementations, the available resource of each slot is reduced + based on the platform specifics, as some resources are reserved for shell logic. + +AU55C Device -To leverage the multi-port capabilities of high-bandwidth memory, we utilize nearly 32 AXI ports of HBM, as illustrated below. - -au280_callipepla - - -As a result, it is necessary to assign the kernel ports to the appropriate slots. The Python code below demonstrates this process. For comprehensive linking details, please refer to the [design/config/link_config_a24.ini](design/config/link_config_a24.ini) file. - - ```Python -right_slot = "SLOT_X1Y0:SLOT_X1Y0" -left_slot = "SLOT_X0Y0:SLOT_X0Y0" -left_args = [ - "edge_list_ptr", - "edge_list_ch_0", - "edge_list_ch_1", - "edge_list_ch_2", - "edge_list_ch_3", - "edge_list_ch_4", - "edge_list_ch_5", - "edge_list_ch_6", - "edge_list_ch_7", - "mat_B_ch_0", - "mat_B_ch_1", - "mat_B_ch_2", - "mat_B_ch_3", -] -for arg in left_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", left_slot) -right_args = [ - "mat_C_ch_0", - "mat_C_ch_1", - "mat_C_ch_2", - "mat_C_ch_3", - "mat_C_ch_4", - "mat_C_ch_5", - "mat_C_ch_6", - "mat_C_ch_7", - "mat_C_ch_in_0", - "mat_C_ch_in_1", - "mat_C_ch_in_2", - "mat_C_ch_in_3", - "mat_C_ch_in_4", - "mat_C_ch_in_5", - "mat_C_ch_in_6", - "mat_C_ch_in_7", -] -for arg in right_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", right_slot) -rs.assign_port_to_region("s_axi_control_.*", left_slot) -rs.assign_port_to_region("ap_clk", left_slot) -rs.assign_port_to_region("ap_rst_n", left_slot) -rs.assign_port_to_region("interrupt", left_slot) +To generate a `device.json` file that details the device features, such as slot resources and + locations, you can either run the `run_u55c.py` script by invoking RapidStream as shown below or + simply enter `make device` in the terminal. + +```bash +rapidstream run_u55c.py ``` -For the complete detail, please refore to [./run.py](./run.py) file. Call the rapidstream by launching the command below or `make all`. + +### Step 3: Use Rapidstream to Optimize `.xo` Design + +The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. +The RapidStream flow for TAPA requires the following key inputs: + +- **tapa-xo-path**: The path to the tapa-generated `xo` file (digit_recognizer.xo). +- **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). +- **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is +the same for vitis link configure file. + +We encapulate the rapidstream command for TAPA as `rapidstream-tapaopt` for invoking. +You can run the command below or execute `make all` supported by our [Makefile](Makefile). ```bash -rapidstream run.py +rapidstream-tapaopt --work-dir build/run_u55c.py \ + --tapa-xo-path design/generated/Serpens.xo \ + --device-config build/run_u55c.py/device.json \ + --floorplan-config design/config/run_u55c.py/floorplan_config.json \ + --implementation-config design/config/run_u55c.py/impl_config.json \ + --connectivity-ini design/config/run_u55c.py/link_config.ini ``` + + If everything is successful, you should at least get one optimized `.xclbin` file. -### Step 3: Check the Group Module Report +### Step 4: Check the Group Module Report RapidStream mandates a clear distinction between communication and computation within user designs. diff --git a/benchmarks/tapa_flow/serpens/design/Serpens.xo b/benchmarks/tapa_flow/serpens/design/Serpens.xo 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@@ -0,0 +1,38 @@ +{ + "dse_range_max": 0.8, + "dse_range_min": 0.7, + "partition_strategy": "flat", + "port_pre_assignments": { + ".*edge_list_ch_0_.*": "HBM[0]", + ".*edge_list_ch_10_.*": "HBM[10]", + ".*edge_list_ch_11_.*": "HBM[11]", + ".*edge_list_ch_12_.*": "HBM[12]", + ".*edge_list_ch_13_.*": "HBM[13]", + ".*edge_list_ch_14_.*": "HBM[14]", + ".*edge_list_ch_15_.*": "HBM[15]", + ".*edge_list_ch_16_.*": "HBM[16]", + ".*edge_list_ch_17_.*": "HBM[17]", + ".*edge_list_ch_18_.*": "HBM[18]", + ".*edge_list_ch_19_.*": "HBM[19]", + ".*edge_list_ch_1_.*": "HBM[1]", + ".*edge_list_ch_20_.*": "HBM[20]", + ".*edge_list_ch_21_.*": "HBM[21]", + ".*edge_list_ch_22_.*": "HBM[22]", + ".*edge_list_ch_23_.*": "HBM[23]", + ".*edge_list_ch_2_.*": "HBM[2]", + ".*edge_list_ch_3_.*": "HBM[3]", + ".*edge_list_ch_4_.*": "HBM[4]", + ".*edge_list_ch_5_.*": "HBM[5]", + ".*edge_list_ch_6_.*": "HBM[6]", + ".*edge_list_ch_7_.*": "HBM[7]", + ".*edge_list_ch_8_.*": "HBM[8]", + ".*edge_list_ch_9_.*": "HBM[9]", + ".*edge_list_ptr_.*": "HBM[24]", + ".*vec_X_.*": "HBM[25]", + ".*vec_Y_.*": "HBM[26]", + "ap_clk": "CLK_RST", + "ap_rst_n": "CLK_RST", + "interrupt": "CLK_RST", + "s_axi_control_.*": "S_AXI_CONTROL" + } +} diff --git a/benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run.py/impl_config.json b/benchmarks/tapa_flow/serpens/design/config/run_u55c.py/impl_config.json similarity index 100% rename from benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run.py/impl_config.json rename to benchmarks/tapa_flow/serpens/design/config/run_u55c.py/impl_config.json diff --git a/benchmarks/tapa_flow/serpens/design/config/link_config_a24.ini b/benchmarks/tapa_flow/serpens/design/config/run_u55c.py/link_config.ini similarity index 100% rename from benchmarks/tapa_flow/serpens/design/config/link_config_a24.ini rename to benchmarks/tapa_flow/serpens/design/config/run_u55c.py/link_config.ini diff --git a/benchmarks/tapa_flow/serpens/design/generated/Serpens.xo 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z4-R+xj`<4|78mvahw@MA5Y+a+fJd2J*6{-1^?(%)9)ZI@ znZDg%#x1Ny%h{C^27c>~+O2ip%fz#Q%vFc;6SZKo%)v@wjm~yHnZCZ@f%zXeJA!#I z7)}6&{4NI(u6(f0iDU2<~g;BfZH4%~M6 z3rtuqH!i*7;?DqWr$PMU)DA%Kcc$;vpKzEv5fiwWz>@xd0SXgxER?(7P69tpbbY_@ zU0a3&h4UW{^-px-U`E1v8?`^^!G{&vJs{pL6W*aW({~&deP=)RD?&JUlf6a5d$$_4 zM-#Q|4~qb3Wxxaw;(&iLef2Qmpy7K2hq?De!ZI9xVG8Wc#n`W-437Z@S-@!^_V7=p zuK^Am!>-i}M**Dpzd(hZM~u{QoGBPo+WoSnN(hGvKS>9(_MqAJJLF~hI*`EO{MjHl zX`tuy-uHTYd3w-H>0OwLlyH~_$}1ehUjFWzFufPsK{IG~v4zmUv2CqjU**hSxC;~H z{j(o;VVW_*VeVN0;v~qu6dp8$ZWkIW3mh7Jui!k`V=@1Q)PqLA>;lK)MgYETmmd%i z`wQ@c`jPJfeNv7x?O8#rAjY5tD!nZ_aQS8VocL6@RQS#-3Y*(1Dqc`GwUzTQw)K!@yJ*gD?qzMQ SbJ@;HP?1+s*j?5}?Ee5xm*9v1 literal 0 HcmV?d00001 diff --git a/benchmarks/tapa_flow/serpens/run.py b/benchmarks/tapa_flow/serpens/run.py deleted file mode 100644 index ed2229b5..00000000 --- a/benchmarks/tapa_flow/serpens/run.py +++ /dev/null @@ -1,141 +0,0 @@ -__copyright__ = """ -Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. -The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -""" - -from rapidstream import get_u280_vitis_device_factory, RapidStreamTAPA -import os - -CURR_DIR = os.path.dirname(os.path.abspath(__file__)) -INI_PATH = f"{CURR_DIR}/design/config/link_config_a24.ini" -VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1" -XO_PATH = f"{CURR_DIR}/design/generated/Serpens.xo" - - -factory = get_u280_vitis_device_factory(VITIS_PLATFORM) - -# Reserve resource for the HBM Memory Sub-System. -# The HMSS is not part of the user kernel so the partition optimization process -# is unaware of its existence. We need to manually reserve resources for it. -# For 512-bit HBM channels, each HBM channel uses approximately the following resources: -# AREA_PER_HBM_CHANNEL = { -# "LUT": 5000, -# "FF": 6500, -# "BRAM": 0, -# "URAM": 0, -# "DSP": 0, -# } -factory.reduce_slot_area(1, 0, lut=5000 * 16, ff=6500 * 16) -factory.reduce_slot_area(0, 0, lut=5000 * 13, ff=6500 * 13) - -# For this U280 platform, the right most DSP column on the boundary between -# dynamic/static region is not usable. So we need to adjust the DSP count -# to reflect the actual available DSPs. -print("Reducing DSP of (1, 1) to make it less congested") -factory.reduce_slot_area(1, 1, dsp=100) - -rs = RapidStreamTAPA(f"{CURR_DIR}/build") - -rs.set_virtual_device(factory.generate_virtual_device()) -rs.add_xo_file(XO_PATH) -rs.set_vitis_platform(VITIS_PLATFORM) -rs.set_vitis_connectivity_config(INI_PATH) - -rs.set_top_module_name("Serpens") -rs.add_clock("ap_clk", 3.33) - -rs.add_flatten_targets(["Serpens"]) - -# Bind ports to HBM 16-31 -right_slot = "SLOT_X1Y0:SLOT_X1Y0" -left_slot = "SLOT_X0Y0:SLOT_X0Y0" - -# The config file binds the following argument to HBM 0 - 15 -# Thus we need to constrain them to the left side of SLR 0 -# sp=Serpens.edge_list_ch_0:HBM[0] -# sp=Serpens.edge_list_ch_1:HBM[1] -# sp=Serpens.edge_list_ch_2:HBM[2] -# sp=Serpens.edge_list_ch_3:HBM[3] -# sp=Serpens.edge_list_ch_4:HBM[4] -# sp=Serpens.edge_list_ch_5:HBM[5] -# sp=Serpens.edge_list_ch_6:HBM[6] -# sp=Serpens.edge_list_ch_7:HBM[7] - -# sp=Serpens.edge_list_ch_8:HBM[8] -# sp=Serpens.edge_list_ch_9:HBM[9] -# sp=Serpens.edge_list_ch_10:HBM[10] -# sp=Serpens.edge_list_ch_11:HBM[11] -# sp=Serpens.edge_list_ch_12:HBM[12] -# sp=Serpens.edge_list_ch_13:HBM[13] -# sp=Serpens.edge_list_ch_14:HBM[14] -# sp=Serpens.edge_list_ch_15:HBM[15] - -left_args = [ - "edge_list_ch_0", - "edge_list_ch_1", - "edge_list_ch_2", - "edge_list_ch_3", - "edge_list_ch_4", - "edge_list_ch_5", - "edge_list_ch_6", - "edge_list_ch_7", - "edge_list_ch_8", - "edge_list_ch_9", - "edge_list_ch_10", - "edge_list_ch_11", - "edge_list_ch_12", - "edge_list_ch_13", - "edge_list_ch_14", - "edge_list_ch_15", -] -for arg in left_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", left_slot) - -# The config file binds the following argument to HBM 16 - 31 -# Thus we need to constrain them to the right side of SLR 0 -# sp=Serpens.edge_list_ch_16:HBM[16] -# sp=Serpens.edge_list_ch_17:HBM[17] -# sp=Serpens.edge_list_ch_18:HBM[18] -# sp=Serpens.edge_list_ch_19:HBM[19] -# sp=Serpens.edge_list_ch_20:HBM[20] -# sp=Serpens.edge_list_ch_21:HBM[21] -# sp=Serpens.edge_list_ch_22:HBM[22] -# sp=Serpens.edge_list_ch_23:HBM[23] -# sp=Serpens.edge_list_ptr:HBM[24] -# sp=Serpens.vec_X:HBM[25] -# sp=Serpens.vec_Y:HBM[26] -# sp=Serpens.vec_Y_out:HBM[27] - -right_args = [ - "edge_list_ch_16", - "edge_list_ch_17", - "edge_list_ch_18", - "edge_list_ch_19", - "edge_list_ch_20", - "edge_list_ch_21", - "edge_list_ch_22", - "edge_list_ch_23", - "edge_list_ptr", - "vec_X", - "vec_Y", -] -for arg in right_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", right_slot) - -# Constrain the remaining control ports. -# All ports must be constrained to a specific slot: -rs.assign_port_to_region("s_axi_control_.*", left_slot) -rs.assign_port_to_region("ap_clk", left_slot) -rs.assign_port_to_region("ap_rst_n", left_slot) -rs.assign_port_to_region("interrupt", left_slot) - -# Xustomize the placement strategy: -rs.set_placement_strategy("EarlyBlockPlacement") - -# Allow two parallel Vitis implementation -rs.run_dse( - max_workers=2, - max_dse_limit=0.85, - min_dse_limit=0.75, - partition_strategy="flat", -) diff --git a/benchmarks/tapa_flow/serpens/run_u55c.py b/benchmarks/tapa_flow/serpens/run_u55c.py new file mode 100644 index 00000000..f356c7b6 --- /dev/null +++ b/benchmarks/tapa_flow/serpens/run_u55c.py @@ -0,0 +1,22 @@ +__copyright__ = """ +Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. +""" + +from pathlib import Path +from rapidstream import get_u55c_vitis_device_factory + +CURR_DIR = Path(__file__).parent +CURR_FILE = Path(__file__).name + +VITIS_PLATFORM = ( + "xilinx_u55c_gen3x16_xdma_3_202210_1" # "xilinx_u280_gen3x16_xdma_1_202211_1" +) + +factory = get_u55c_vitis_device_factory(VITIS_PLATFORM) + +factory.reduce_slot_area(1, 0, lut=50000, ff=60000) +factory.reduce_slot_area(0, 0, lut=50000, ff=60000) +factory.reduce_slot_area(1, 1, dsp=100) + +factory.generate_virtual_device(Path(f"{CURR_DIR}/build/{CURR_FILE}/device.json")) diff --git a/benchmarks/tapa_flow/sextans/Makefile b/benchmarks/tapa_flow/sextans/Makefile index b44aec65..d2b4f612 100644 --- a/benchmarks/tapa_flow/sextans/Makefile +++ b/benchmarks/tapa_flow/sextans/Makefile @@ -1,32 +1,54 @@ # Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -ROOT_DIR := $(shell git rev-parse --show-toplevel) -GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py -PLATFORM := xilinx_u280_gen3x16_xdma_1_202211_1 -KRNL_NAME := Sextans -RS_SCRIPT := $(CURDIR)/run.py -TEMP_DIR := $(CURDIR)/build/$(notdir $(RS_SCRIPT)) -RS_TARGET := $(TEMP_DIR)/dse/candidate_0/vitis_run_hw/$(KRNL_NAME)_$(PLATFORM).xclbin -TAPA_XO := $(CURDIR)/design/generated/$(KRNL_NAME).xo -PART := xcu280-fsvh2892-2L-e -RSXX := rapidstream -TIMING_RPT := impl_1_hw_bb_locked_timing_summary_routed.rpt -SUCCESS := "Build Successful" -SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py -BUILD_LOG := $(TEMP_DIR)/build.json +ROOT_DIR := $(shell git rev-parse --show-toplevel) +KERNEL_NAME := Sextans +RS_SCRIPT := $(CURDIR)/run_u55c.py +AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json +IMPL_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json +LINK_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini +PLATFORM := xilinx_u55c_gen3x16_xdma_3_202210_1 +GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py +TEMP_DIR := $(CURDIR)/build/$(notdir $(RS_SCRIPT)) +RS_TARGET := $(TEMP_DIR)/dse/solution_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin +TAPA_XO := $(CURDIR)/design/generated/$(KERNEL_NAME).xo +BUILD_LOG := $(TEMP_DIR)/build.json +SUCCESS := "Build Successful" +TIMING_RPT := impl_1_hw_bb_locked_timing_summary_routed.rpt +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +RSPATH := $(CURDIR) +RSXX := rapidstream +RSPYTHON := rapidstream +DEVICE_CONFIG := $(TEMP_DIR)/device.json +DEVICE_GEN := $(CURDIR)/gen_device.py all: $(RS_TARGET) - $(RSXX) $(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG) -c clk_kernel_00_unbuffered_net -p 3.333 - echo $(SUCCESS) + cd $(RSPATH) && $(RSPYTHON) $(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG) -c clk_kernel_00_unbuffered_net -p 3.333 + @echo $(SUCCESS) -$(RS_TARGET):$(TAPA_XO) - $(RSXX) $(RS_SCRIPT) +$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) $(RS_SCRIPT) + mkdir -p $(TEMP_DIR) + cd $(RSPATH) && $(RSXX)-tapaopt \ + --work-dir $(TEMP_DIR) \ + --tapa-xo-path $< \ + --device-config $(DEVICE_CONFIG) \ + --floorplan-config $(AB_CONFIG) \ + --run-impl \ + --implementation-config $(IMPL_CONFIG) \ + --connectivity-ini $(LINK_CONFIG) + +device: $(DEVICE_CONFIG) + +$(DEVICE_CONFIG):$(RS_SCRIPT) + mkdir -p $(TEMP_DIR) + cd $(RSPATH) && $(RSPYTHON) $< show_groups: - $(RSXX) $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \ + rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \ -o $(TEMP_DIR)/module_types.csv + + clean: rm -rf $(TEMP_DIR) *.log rm -rf .Xil .run diff --git a/benchmarks/tapa_flow/sextans/README.md b/benchmarks/tapa_flow/sextans/README.md index 8e9119e9..61cb8e0e 100644 --- a/benchmarks/tapa_flow/sextans/README.md +++ b/benchmarks/tapa_flow/sextans/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. [TAPA](https://tapa.readthedocs.io/en/release/overview/overview.html), a dataflow HLS framework, features fast compilation, an expressive programming model, and the ability to generate high-frequency FPGA accelerators. We will guide you through the process using a general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM) from [Sextan](https://github.com/linghaosong/Sextans). The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -24,116 +24,63 @@ In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. We utilize TAPA to generate the `.xo` file. If you have not installed TAPA, we've already compiled the C++ source to `.xo` using TAPA. The original C++ source files are located in [design/src](design/src). The generated `.xo` file can be found at [design/generated/Sextans.xo](design/generated/Sextans.xo). To compile C++ to `.xo` using TAPA, we use the script [design/run_tapa.sh](design/run_tapa.sh), with the detailed commands shown below. For your convenience, we have also backed up all the generated metadata by TAPA in the [design/generated](design/generated/) directory. ```bash -WORK_DIR=generated -tapac \ - --work-dir ${WORK_DIR} \ - --top Sextans \ - --part-num xcu280-fsvh2892-2L-e \ - --clock-period 3.33 \ - -o ${WORK_DIR}/Sextans.xo \ - --connectivity config/link_config.ini \ - src/sextans.cpp \ - 2>&1 | tee ${WORK_DIR}/tapa.log +mkdir -p build/run_u55c.py +cd build/run_u55c.py && tapa compile \ +--top Sextans \ +--part-num xcu55c-fsvh2892-2L-e \ +--clock-period 3.33 \ +-o Sextans.xo \ +-f $< \ +2>&1 | tee tapa.log ``` -### Step 2: Use Rapidstream to Optimize `.xo` Design +### Step 2: Define Virtual Device -The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. -The RapidStream flow for TAPA requires the following key inputs: +In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each +containing 16 clock regions of logic. In actual implementations, the available resource of each slot is reduced + based on the platform specifics, as some resources are reserved for shell logic. -- **Platform**: The Vitis platform (e.g., `xilinx_u280_gen3x16_xdma_1_202211_1`). -- **Device**: virtual device define by calling rapidstream APIs based on platform (e.g., `get_u280_vitis_device_factory`). -- **.xo file**: The `.xo` file generated by TAPA -- **Connectivity** (.ini): Include the configuration file for `v++` ([link_config.ini](design/config/link_config.ini)). -- **top_module_name**: Top module name for the kernel. -- **Clock**: All the clock and frequencies. -- **Flatten Module**: Within a design, not all modules need to be optimized. The flatten module name is the target module rapidstream will optimize. - -The Python snippet below shows how we initiate rapidstream instance to set up the rapidstream environment. - -```Python -from rapidstream import get_u280_vitis_device_factory, RapidStreamTAPA -import os - -CURR_DIR = os.path.dirname(os.path.abspath(__file__)) -INI_PATH = f"{CURR_DIR}/design/config/link_config.ini" -VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1" -XO_PATH = f"{CURR_DIR}/design/generated/Sextans.xo" -factory = get_u280_vitis_device_factory(VITIS_PLATFORM) -rs = RapidStreamTAPA(f"{CURR_DIR}build") -rs.set_virtual_device(factory.generate_virtual_device()) -rs.add_xo_file(XO_PATH) -rs.set_vitis_platform(VITIS_PLATFORM) -rs.set_vitis_connectivity_config(INI_PATH) -rs.set_top_module_name("Sextans") -rs.add_clock("ap_clk", 3.33) -rs.add_flatten_targets(["Sextans"]) -``` +AU55C Device -To leverage the multi-port capabilities of high-bandwidth memory, we utilize nearly 32 AXI ports of HBM, as illustrated below. - -au280_callipepla - - -As a result, it is necessary to assign the kernel ports to the appropriate slots. The Python code below demonstrates this process. For comprehensive linking details, please refer to the [design/config/link_config.ini](design/config/link_config.ini) file. - - ```Python -right_slot = "SLOT_X1Y0:SLOT_X1Y0" -left_slot = "SLOT_X0Y0:SLOT_X0Y0" -left_args = [ - "edge_list_ptr", - "edge_list_ch_0", - "edge_list_ch_1", - "edge_list_ch_2", - "edge_list_ch_3", - "edge_list_ch_4", - "edge_list_ch_5", - "edge_list_ch_6", - "edge_list_ch_7", - "mat_B_ch_0", - "mat_B_ch_1", - "mat_B_ch_2", - "mat_B_ch_3", -] -for arg in left_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", left_slot) -right_args = [ - "mat_C_ch_0", - "mat_C_ch_1", - "mat_C_ch_2", - "mat_C_ch_3", - "mat_C_ch_4", - "mat_C_ch_5", - "mat_C_ch_6", - "mat_C_ch_7", - "mat_C_ch_in_0", - "mat_C_ch_in_1", - "mat_C_ch_in_2", - "mat_C_ch_in_3", - "mat_C_ch_in_4", - "mat_C_ch_in_5", - "mat_C_ch_in_6", - "mat_C_ch_in_7", -] -for arg in right_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", right_slot) -rs.assign_port_to_region("s_axi_control_.*", left_slot) -rs.assign_port_to_region("ap_clk", left_slot) -rs.assign_port_to_region("ap_rst_n", left_slot) -rs.assign_port_to_region("interrupt", left_slot) +To generate a `device.json` file that details the device features, such as slot resources and + locations, you can either run the `run_u55c.py` script by invoking RapidStream as shown below or + simply enter `make device` in the terminal. + +```bash +rapidstream run_u55c.py ``` -For the complete detail, please refore to [./run.py](./run.py) file. Call the rapidstream by launching the command below or `make all`. + +### Step 3: Use Rapidstream to Optimize `.xo` Design + +The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. +The RapidStream flow for TAPA requires the following key inputs: + +- **tapa-xo-path**: The path to the tapa-generated `xo` file (Sextans). +- **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). +- **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is +the same for vitis link configure file. + +We encapulate the rapidstream command for TAPA as `rapidstream-tapaopt` for invoking. +You can run the command below or execute `make all` supported by our [Makefile](Makefile). ```bash -rapidstream run.py +rapidstream-tapaopt --work-dir build/run_u55c.py \ + --tapa-xo-path build/run_u55c.py/Sextans \ + --device-config build/run_u55c.py/device.json \ + --floorplan-config design/config/run_u55c.py/floorplan_config.json \ + --implementation-config design/config/run_u55c.py/impl_config.json \ + --connectivity-ini design/config/run_u55c.py/link_config.ini ``` + If everything is successful, you should at least get one optimized `.xclbin` file. -### Step 3: Check the Group Module Report +### Step 4: Check the Group Module Report RapidStream mandates a clear distinction between communication and computation within user designs. diff --git a/benchmarks/tapa_flow/sextans/design/config/run_u55c.py/floorplan_config.json b/benchmarks/tapa_flow/sextans/design/config/run_u55c.py/floorplan_config.json new file mode 100644 index 00000000..9ca3d839 --- /dev/null +++ b/benchmarks/tapa_flow/sextans/design/config/run_u55c.py/floorplan_config.json @@ -0,0 +1,40 @@ +{ + "dse_range_max": 0.8, + "dse_range_min": 0.7, + "partition_strategy": "flat", + "port_pre_assignments": { + ".*edge_list_ch_0_.*": "HBM[1]", + ".*edge_list_ch_1_.*": "HBM[2]", + ".*edge_list_ch_2_.*": "HBM[3]", + ".*edge_list_ch_3_.*": "HBM[4]", + ".*edge_list_ch_4_.*": "HBM[5]", + ".*edge_list_ch_5_.*": "HBM[6]", + ".*edge_list_ch_6_.*": "HBM[7]", + ".*edge_list_ch_7_.*": "HBM[8]", + ".*edge_list_ptr_.*": "HBM[0]", + ".*mat_B_ch_0_.*": "HBM[9]", + ".*mat_B_ch_1_.*": "HBM[10]", + ".*mat_B_ch_2_.*": "HBM[11]", + ".*mat_B_ch_3_.*": "HBM[12]", + ".*mat_C_ch_0_.*": "HBM[16]", + ".*mat_C_ch_1_.*": "HBM[17]", + ".*mat_C_ch_2_.*": "HBM[18]", + ".*mat_C_ch_3_.*": "HBM[19]", + ".*mat_C_ch_4_.*": "HBM[20]", + ".*mat_C_ch_5_.*": "HBM[21]", + ".*mat_C_ch_6_.*": "HBM[22]", + ".*mat_C_ch_7_.*": "HBM[23]", + ".*mat_C_ch_in_0_.*": "HBM[24]", + ".*mat_C_ch_in_1_.*": "HBM[25]", + ".*mat_C_ch_in_2_.*": "HBM[26]", + ".*mat_C_ch_in_3_.*": "HBM[27]", + ".*mat_C_ch_in_4_.*": "HBM[28]", + ".*mat_C_ch_in_5_.*": "HBM[29]", + ".*mat_C_ch_in_6_.*": "HBM[30]", + ".*mat_C_ch_in_7_.*": "HBM[31]", + "ap_clk": "CLK_RST", + "ap_rst_n": "CLK_RST", + "interrupt": "CLK_RST", + "s_axi_control_.*": "S_AXI_CONTROL" + } +} diff --git a/benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run.py/impl_config.json b/benchmarks/tapa_flow/sextans/design/config/run_u55c.py/impl_config.json similarity index 100% rename from benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run.py/impl_config.json rename to benchmarks/tapa_flow/sextans/design/config/run_u55c.py/impl_config.json diff --git a/benchmarks/tapa_flow/sextans/design/config/link_config.ini b/benchmarks/tapa_flow/sextans/design/config/run_u55c.py/link_config.ini similarity index 99% rename from benchmarks/tapa_flow/sextans/design/config/link_config.ini rename to benchmarks/tapa_flow/sextans/design/config/run_u55c.py/link_config.ini index bf0d4c69..7489ecdf 100644 --- a/benchmarks/tapa_flow/sextans/design/config/link_config.ini +++ b/benchmarks/tapa_flow/sextans/design/config/run_u55c.py/link_config.ini @@ -1,6 +1,5 @@ [connectivity] sp=Sextans.edge_list_ptr:HBM[0] - sp=Sextans.edge_list_ch_0:HBM[1] sp=Sextans.edge_list_ch_1:HBM[2] sp=Sextans.edge_list_ch_2:HBM[3] @@ -9,12 +8,10 @@ sp=Sextans.edge_list_ch_4:HBM[5] sp=Sextans.edge_list_ch_5:HBM[6] sp=Sextans.edge_list_ch_6:HBM[7] sp=Sextans.edge_list_ch_7:HBM[8] - sp=Sextans.mat_B_ch_0:HBM[9] sp=Sextans.mat_B_ch_1:HBM[10] sp=Sextans.mat_B_ch_2:HBM[11] sp=Sextans.mat_B_ch_3:HBM[12] - sp=Sextans.mat_C_ch_0:HBM[16] sp=Sextans.mat_C_ch_1:HBM[17] sp=Sextans.mat_C_ch_2:HBM[18] @@ -23,7 +20,6 @@ sp=Sextans.mat_C_ch_4:HBM[20] sp=Sextans.mat_C_ch_5:HBM[21] sp=Sextans.mat_C_ch_6:HBM[22] sp=Sextans.mat_C_ch_7:HBM[23] - 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a/benchmarks/tapa_flow/sextans/design/generated/cpp/FloatvAddFloatv.cpp +++ /dev/null @@ -1,440 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out) { -#pragma HLS disaggregate variable = fifo_in0 -#pragma HLS interface ap_fifo port = fifo_in0._ -#pragma HLS aggregate variable = fifo_in0._ bit -#pragma HLS interface ap_fifo port = fifo_in0._peek -#pragma HLS aggregate variable = fifo_in0._peek bit - void(fifo_in0._.empty()); - void(fifo_in0._peek.empty()); - -#pragma HLS disaggregate variable = fifo_in1 -#pragma HLS interface ap_fifo port = fifo_in1._ -#pragma HLS aggregate variable = fifo_in1._ bit -#pragma HLS interface ap_fifo port = fifo_in1._peek -#pragma HLS aggregate variable = fifo_in1._peek bit - void(fifo_in1._.empty()); - void(fifo_in1._peek.empty()); - -#pragma HLS disaggregate variable = fifo_out -#pragma HLS interface ap_fifo port = fifo_out._ -#pragma HLS aggregate variable = fifo_out._ bit - void(fifo_out._.full()); - -cc: - for (;;) { -#pragma HLS pipeline style = stp II = 1 - bool flag_nop = fifo_in0.empty() | fifo_in1.empty(); - if (!flag_nop) { - float_v16 tmp0; - fifo_in0.try_read(tmp0); - float_v16 tmp1; - fifo_in1.try_read(tmp1); - float_v16 c_out = tmp0 + tmp1; - fifo_out.write(c_out); - } - } -} -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/FloatvMultConst.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/FloatvMultConst.cpp deleted file mode 100644 index 9681ea62..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/FloatvMultConst.cpp +++ /dev/null @@ -1,436 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out) { - -#pragma HLS disaggregate variable = fifo_in -#pragma HLS interface ap_fifo port = fifo_in._ -#pragma HLS aggregate variable = fifo_in._ bit -#pragma HLS interface ap_fifo port = fifo_in._peek -#pragma HLS aggregate variable = fifo_in._peek bit - void(fifo_in._.empty()); - void(fifo_in._peek.empty()); - -#pragma HLS disaggregate variable = fifo_out -#pragma HLS interface ap_fifo port = fifo_out._ -#pragma HLS aggregate variable = fifo_out._ bit - void(fifo_out._.full()); - - const float alpha_f = tapa::bit_cast(alpha_u); - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int num_ite = ((M + 15) >> 4) * ((N + 7) >> 3) * rp_time; -cc: - for (int i = 0; i < num_ite;) { -#pragma HLS pipeline style = stp II = 1 - float_v16 tmp; - bool read_ready = fifo_in.try_read(tmp); - if (read_ready) { - float_v16 c_out = tmp * alpha_f; - fifo_out.write(c_out); - ++i; - } - } -} -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/Merger.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/Merger.cpp deleted file mode 100644 index dae86a47..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/Merger.cpp +++ /dev/null @@ -1,442 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out) { -#pragma HLS disaggregate variable = fifo_in -#pragma HLS array_partition variable = fifo_in complete -#pragma HLS interface ap_fifo port = fifo_in[0]._ -#pragma HLS aggregate variable = fifo_in[0]._ bit -#pragma HLS interface ap_fifo port = fifo_in[0]._peek -#pragma HLS aggregate variable = fifo_in[0]._peek bit - void(fifo_in[0]._.empty()); - void(fifo_in[0]._peek.empty()); -#pragma HLS interface ap_fifo port = fifo_in[1]._ -#pragma HLS aggregate variable = fifo_in[1]._ bit -#pragma HLS interface ap_fifo port = fifo_in[1]._peek -#pragma HLS aggregate variable = fifo_in[1]._peek bit - void(fifo_in[1]._.empty()); - void(fifo_in[1]._peek.empty()); - -#pragma HLS disaggregate variable = fifo_out -#pragma HLS interface ap_fifo port = fifo_out._ -#pragma HLS aggregate variable = fifo_out._ bit - void(fifo_out._.full()); - - for (;;) { -#pragma HLS pipeline style = stp II = 1 - bool flag_nop = fifo_out.full() | fifo_in[0].empty() | fifo_in[1].empty(); - if (!flag_nop) { - float_v16 tmpv16; - float_v8 tmpv8[2]; -#pragma HLS aggregate variable = tmpv16 - fifo_in[0].try_read(tmpv8[0]); - fifo_in[1].try_read(tmpv8[1]); - for (int i = 0; i < 8; ++i) { - tmpv16[i] = tmpv8[0][i]; - tmpv16[i + 8] = tmpv8[1][i]; - } - fifo_out.try_write(tmpv16); - } - } -} -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/PEG_Bmtx.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/PEG_Bmtx.cpp deleted file mode 100644 index 9c611497..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/PEG_Bmtx.cpp +++ /dev/null @@ -1,601 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec) { -#pragma HLS disaggregate variable = PE_inst_in -#pragma HLS interface ap_fifo port = PE_inst_in._ -#pragma HLS aggregate variable = PE_inst_in._ bit -#pragma HLS interface ap_fifo port = PE_inst_in._peek -#pragma HLS aggregate variable = PE_inst_in._peek bit - void(PE_inst_in._.empty()); - void(PE_inst_in._peek.empty()); - -#pragma HLS disaggregate variable = fifo_inst_in -#pragma HLS interface ap_fifo port = fifo_inst_in._ -#pragma HLS aggregate variable = fifo_inst_in._ bit -#pragma HLS interface ap_fifo port = fifo_inst_in._peek -#pragma HLS aggregate variable = fifo_inst_in._peek bit - void(fifo_inst_in._.empty()); - void(fifo_inst_in._peek.empty()); - -#pragma HLS disaggregate variable = fifo_A -#pragma HLS interface ap_fifo port = fifo_A._ -#pragma HLS aggregate variable = fifo_A._ bit -#pragma HLS interface ap_fifo port = fifo_A._peek -#pragma HLS aggregate variable = fifo_A._peek bit - void(fifo_A._.empty()); - void(fifo_A._peek.empty()); - -#pragma HLS disaggregate variable = fifo_B_in -#pragma HLS array_partition variable = fifo_B_in complete -#pragma HLS interface ap_fifo port = fifo_B_in[0]._ -#pragma HLS aggregate variable = fifo_B_in[0]._ bit -#pragma HLS interface ap_fifo port = fifo_B_in[0]._peek -#pragma HLS aggregate variable = fifo_B_in[0]._peek bit - void(fifo_B_in[0]._.empty()); - void(fifo_B_in[0]._peek.empty()); -#pragma HLS interface ap_fifo port = fifo_B_in[1]._ -#pragma HLS aggregate variable = fifo_B_in[1]._ bit -#pragma HLS interface ap_fifo port = fifo_B_in[1]._peek -#pragma HLS aggregate variable = fifo_B_in[1]._peek bit - void(fifo_B_in[1]._.empty()); - void(fifo_B_in[1]._peek.empty()); -#pragma HLS interface ap_fifo port = fifo_B_in[2]._ -#pragma HLS aggregate variable = fifo_B_in[2]._ bit -#pragma HLS interface ap_fifo port = fifo_B_in[2]._peek -#pragma HLS aggregate variable = fifo_B_in[2]._peek bit - void(fifo_B_in[2]._.empty()); - void(fifo_B_in[2]._peek.empty()); -#pragma HLS interface ap_fifo port = fifo_B_in[3]._ -#pragma HLS aggregate variable = fifo_B_in[3]._ bit -#pragma HLS interface ap_fifo port = fifo_B_in[3]._peek -#pragma HLS aggregate variable = fifo_B_in[3]._peek bit - void(fifo_B_in[3]._.empty()); - void(fifo_B_in[3]._peek.empty()); - -#pragma HLS disaggregate variable = PE_inst_out -#pragma HLS interface ap_fifo port = PE_inst_out._ -#pragma HLS aggregate variable = PE_inst_out._ bit - void(PE_inst_out._.full()); - -#pragma HLS disaggregate variable = fifo_inst_out -#pragma HLS interface ap_fifo port = fifo_inst_out._ -#pragma HLS aggregate variable = fifo_inst_out._ bit - void(fifo_inst_out._.full()); - -#pragma HLS disaggregate variable = fifo_B_out -#pragma HLS array_partition variable = fifo_B_out complete -#pragma HLS interface ap_fifo port = fifo_B_out[0]._ -#pragma HLS aggregate variable = fifo_B_out[0]._ bit - void(fifo_B_out[0]._.full()); -#pragma HLS interface ap_fifo port = fifo_B_out[1]._ -#pragma HLS aggregate variable = fifo_B_out[1]._ bit - void(fifo_B_out[1]._.full()); -#pragma HLS interface ap_fifo port = fifo_B_out[2]._ -#pragma HLS aggregate variable = fifo_B_out[2]._ bit - void(fifo_B_out[2]._.full()); -#pragma HLS interface ap_fifo port = fifo_B_out[3]._ -#pragma HLS aggregate variable = fifo_B_out[3]._ bit - void(fifo_B_out[3]._.full()); - -#pragma HLS disaggregate variable = PE_inst_to_Cmtx -#pragma HLS interface ap_fifo port = PE_inst_to_Cmtx._ -#pragma HLS aggregate variable = PE_inst_to_Cmtx._ bit - void(PE_inst_to_Cmtx._.full()); - -#pragma HLS disaggregate variable = fifo_inst_out_to_Cmtx -#pragma HLS interface ap_fifo port = fifo_inst_out_to_Cmtx._ -#pragma HLS aggregate variable = fifo_inst_out_to_Cmtx._ bit - void(fifo_inst_out_to_Cmtx._.full()); - -#pragma HLS disaggregate variable = fifo_aBvec -#pragma HLS array_partition variable = fifo_aBvec complete -#pragma HLS interface ap_fifo port = fifo_aBvec[0]._ -#pragma HLS aggregate variable = fifo_aBvec[0]._ bit - void(fifo_aBvec[0]._.full()); -#pragma HLS interface ap_fifo port = fifo_aBvec[1]._ -#pragma HLS aggregate variable = fifo_aBvec[1]._ bit - void(fifo_aBvec[1]._.full()); -#pragma HLS interface ap_fifo port = fifo_aBvec[2]._ -#pragma HLS aggregate variable = fifo_aBvec[2]._ bit - void(fifo_aBvec[2]._.full()); -#pragma HLS interface ap_fifo port = fifo_aBvec[3]._ -#pragma HLS aggregate variable = fifo_aBvec[3]._ bit - void(fifo_aBvec[3]._.full()); - - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - PE_inst_to_Cmtx.write(NUM_ITE); - PE_inst_to_Cmtx.write(M); - PE_inst_to_Cmtx.write(P_N); - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - // float local_B[8/2][8][WINDOW_SIZE]; - // float local_B[8][WINDOW_SIZE]; - float local_B[4 / 2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable = local_B latency = 2 -#pragma HLS array_partition variable = local_B complete dim = 1 -#pragma HLS array_partition variable = local_B complete dim = 2 -#pragma HLS array_partition variable = local_B cyclic factor = \ - B_PARTITION_FACTOR dim = 3 - //#pragma HLS array_partition variable=local_B cyclic - // factor=B_PARTITION_FACTOR dim=2 - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - fifo_inst_out_to_Cmtx.write(start_32); - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min = 1 max = 49 - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && - (j < ((K + 7) >> 3) - i * (WINDOW_SIZE >> 3));) { -#pragma HLS loop_tripcount min = 1 max = 512 -#pragma HLS pipeline style = stp II = 1 - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - fifo_B_in[k].try_read(b_512_x[k]); - fifo_B_out[k].try_write(b_512_x[k]); - } - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m / 2][k + m % 2 * 8]; - } - } - } - ++j; - } - } - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - fifo_inst_out_to_Cmtx.write(end_32); - computation: - for (int j = start_32; j < end_32;) { -#pragma HLS loop_tripcount min = 1 max = 200 -#pragma HLS pipeline style = stp II = 1 - // ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - if (a_pes_ready) { - for (int p = 0; p < 4; ++p) { - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - ap_uint<14> a_col = a(63, 50); - ap_uint<18> a_row = a(49, 32); - ap_uint<32> a_val = a(31, 0); - MultBVec rabv; - rabv.row = a_row; - if (a_row[17] == 0) { - // PE process - PEcore_Bmtx(a_col, a_val, local_B[p / 2], rabv.abvec); - } - fifo_aBvec[p].write(rabv); - } - ++j; - } - } - start_32 = end_32; - } - } -} -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/PEG_Cmtx.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/PEG_Cmtx.cpp deleted file mode 100644 index 40cffb8d..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/PEG_Cmtx.cpp +++ /dev/null @@ -1,550 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out) { -#pragma HLS disaggregate variable = PE_inst_in -#pragma HLS interface ap_fifo port = PE_inst_in._ -#pragma HLS aggregate variable = PE_inst_in._ bit -#pragma HLS interface ap_fifo port = PE_inst_in._peek -#pragma HLS aggregate variable = PE_inst_in._peek bit - void(PE_inst_in._.empty()); - void(PE_inst_in._peek.empty()); - -#pragma HLS disaggregate variable = fifo_inst_in -#pragma HLS interface ap_fifo port = fifo_inst_in._ -#pragma HLS aggregate variable = fifo_inst_in._ bit -#pragma HLS interface ap_fifo port = fifo_inst_in._peek -#pragma HLS aggregate variable = fifo_inst_in._peek bit - void(fifo_inst_in._.empty()); - void(fifo_inst_in._peek.empty()); - -#pragma HLS disaggregate variable = fifo_aBvec -#pragma HLS array_partition variable = fifo_aBvec complete -#pragma HLS interface ap_fifo port = fifo_aBvec[0]._ -#pragma HLS aggregate variable = fifo_aBvec[0]._ bit -#pragma HLS interface ap_fifo port = fifo_aBvec[0]._peek -#pragma HLS aggregate variable = fifo_aBvec[0]._peek bit - void(fifo_aBvec[0]._.empty()); - void(fifo_aBvec[0]._peek.empty()); -#pragma HLS interface ap_fifo port = fifo_aBvec[1]._ -#pragma HLS aggregate variable = fifo_aBvec[1]._ bit -#pragma HLS interface ap_fifo port = fifo_aBvec[1]._peek -#pragma HLS aggregate variable = fifo_aBvec[1]._peek bit - void(fifo_aBvec[1]._.empty()); - void(fifo_aBvec[1]._peek.empty()); -#pragma HLS interface ap_fifo port = fifo_aBvec[2]._ -#pragma HLS aggregate variable = fifo_aBvec[2]._ bit -#pragma HLS interface ap_fifo port = fifo_aBvec[2]._peek -#pragma HLS aggregate variable = fifo_aBvec[2]._peek bit - void(fifo_aBvec[2]._.empty()); - void(fifo_aBvec[2]._peek.empty()); -#pragma HLS interface ap_fifo port = fifo_aBvec[3]._ -#pragma HLS aggregate variable = fifo_aBvec[3]._ bit -#pragma HLS interface ap_fifo port = fifo_aBvec[3]._peek -#pragma HLS aggregate variable = fifo_aBvec[3]._peek bit - void(fifo_aBvec[3]._.empty()); - void(fifo_aBvec[3]._peek.empty()); - -#pragma HLS disaggregate variable = fifo_C_out -#pragma HLS interface ap_fifo port = fifo_C_out._ -#pragma HLS aggregate variable = fifo_C_out._ bit - void(fifo_C_out._.full()); - - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - const int num_v_init = (M + 63) >> 6; - // const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - // define local C buffer and pragma to URAM - // ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable = local_C type = RAM_2P impl = \ - URAM latency = 1 -#pragma HLS array_partition complete variable = local_C dim = 1 -#pragma HLS array_partition complete variable = local_C dim = 2 -l_rp: - for (int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - // init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min = 1 max = 800 -#pragma HLS pipeline style = stp II = 1 - // for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - auto start_32 = fifo_inst_in.read(); - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min = 1 max = 49 - // computation - const auto end_32 = fifo_inst_in.read(); - computation: - for (int j = start_32; j < end_32;) { -#pragma HLS loop_tripcount min = 1 max = 200 -#pragma HLS pipeline style = stp II = 1 -#pragma HLS dependence true variable = local_C distance = DEP_DIST_LOAD_STORE - bool nop_flag = false; - for (int p = 0; p < 4; ++p) { - nop_flag |= fifo_aBvec[p].empty(); - } - if (!nop_flag) { - for (int p = 0; p < 4; ++p) { - MultBVec rabv; - fifo_aBvec[p].try_read(rabv); - ap_uint<18> a_row = rabv.row; - if (a_row[17] == 0) { - PEcore_Cmtx(a_row, rabv.abvec, local_C[p]); - } - } - ++j; - } - } - start_32 = end_32; - } - // cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min = 1 max = 1800 -#pragma HLS pipeline style = stp II = 1 - ap_uint<32> u_32_d[8]; - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i >> 2]; - u_32_d[2 * d] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - switch (c_idx) { // 0,2,1,3 - case 0: - c_idx = 2; - break; - case 1: - c_idx = 3; - break; - case 2: - c_idx = 1; - break; - case 3: - c_idx = 0; - break; - } - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - // for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << - // endl; - } - } -} -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/Scatter_1_2.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/Scatter_1_2.cpp deleted file mode 100644 index 0168fb85..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/Scatter_1_2.cpp +++ /dev/null @@ -1,437 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out) { -#pragma HLS disaggregate variable = fifo_in -#pragma HLS interface ap_fifo port = fifo_in._ -#pragma HLS aggregate variable = fifo_in._ bit -#pragma HLS interface ap_fifo port = fifo_in._peek -#pragma HLS aggregate variable = fifo_in._peek bit - void(fifo_in._.empty()); - void(fifo_in._peek.empty()); - -#pragma HLS disaggregate variable = fifo_out -#pragma HLS array_partition variable = fifo_out complete -#pragma HLS interface ap_fifo port = fifo_out[0]._ -#pragma HLS aggregate variable = fifo_out[0]._ bit - void(fifo_out[0]._.full()); -#pragma HLS interface ap_fifo port = fifo_out[1]._ -#pragma HLS aggregate variable = fifo_out[1]._ bit - void(fifo_out[1]._.full()); - - for (;;) { -#pragma HLS pipeline style = stp II = 1 - bool flag_nop = fifo_in.empty(); - for (int i = 0; i < 2; ++i) { - flag_nop |= fifo_out[i].full(); - } - if (!flag_nop) { - ap_uint<512> tmp; - fifo_in.try_read(tmp); - for (int i = 0; i < 2; ++i) { - fifo_out[i].try_write(tmp(255 + i * 256, i * 256)); - } - } - } -} -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/Sextans.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/Sextans.cpp deleted file mode 100644 index c965f0ed..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/Sextans.cpp +++ /dev/null @@ -1,497 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -extern "C" { - -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u) { - -#pragma HLS interface s_axilite port = edge_list_ptr bundle = control - { auto val = reinterpret_cast(edge_list_ptr); } - { auto val = reinterpret_cast(edge_list_ptr); } - -#pragma HLS interface s_axilite port = edge_list_ch_0 bundle = control -#pragma HLS interface s_axilite port = edge_list_ch_1 bundle = control -#pragma HLS interface s_axilite port = edge_list_ch_2 bundle = control -#pragma HLS interface s_axilite port = edge_list_ch_3 bundle = control -#pragma HLS interface s_axilite port = edge_list_ch_4 bundle = control -#pragma HLS interface s_axilite port = edge_list_ch_5 bundle = control -#pragma HLS interface s_axilite port = edge_list_ch_6 bundle = control -#pragma HLS interface s_axilite port = edge_list_ch_7 bundle = control - { auto val = reinterpret_cast(edge_list_ch_0); } - { auto val = reinterpret_cast(edge_list_ch_1); } - { auto val = reinterpret_cast(edge_list_ch_2); } - { auto val = reinterpret_cast(edge_list_ch_3); } - { auto val = reinterpret_cast(edge_list_ch_4); } - { auto val = reinterpret_cast(edge_list_ch_5); } - { auto val = reinterpret_cast(edge_list_ch_6); } - { auto val = reinterpret_cast(edge_list_ch_7); } - -#pragma HLS interface s_axilite port = mat_B_ch_0 bundle = control -#pragma HLS interface s_axilite port = mat_B_ch_1 bundle = control -#pragma HLS interface s_axilite port = mat_B_ch_2 bundle = control -#pragma HLS interface s_axilite port = mat_B_ch_3 bundle = control - { auto val = reinterpret_cast(mat_B_ch_0); } - { auto val = reinterpret_cast(mat_B_ch_1); } - { auto val = reinterpret_cast(mat_B_ch_2); } - { auto val = reinterpret_cast(mat_B_ch_3); } - -#pragma HLS interface s_axilite port = mat_C_ch_in_0 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_in_1 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_in_2 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_in_3 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_in_4 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_in_5 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_in_6 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_in_7 bundle = control - { auto val = reinterpret_cast(mat_C_ch_in_0); } - { auto val = reinterpret_cast(mat_C_ch_in_1); } - { auto val = reinterpret_cast(mat_C_ch_in_2); } - { auto val = reinterpret_cast(mat_C_ch_in_3); } - { auto val = reinterpret_cast(mat_C_ch_in_4); } - { auto val = reinterpret_cast(mat_C_ch_in_5); } - { auto val = reinterpret_cast(mat_C_ch_in_6); } - { auto val = reinterpret_cast(mat_C_ch_in_7); } - -#pragma HLS interface s_axilite port = mat_C_ch_0 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_1 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_2 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_3 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_4 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_5 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_6 bundle = control -#pragma HLS interface s_axilite port = mat_C_ch_7 bundle = control - { auto val = reinterpret_cast(mat_C_ch_0); } - { auto val = reinterpret_cast(mat_C_ch_1); } - { auto val = reinterpret_cast(mat_C_ch_2); } - { auto val = reinterpret_cast(mat_C_ch_3); } - { auto val = reinterpret_cast(mat_C_ch_4); } - { auto val = reinterpret_cast(mat_C_ch_5); } - { auto val = reinterpret_cast(mat_C_ch_6); } - { auto val = reinterpret_cast(mat_C_ch_7); } - -#pragma HLS interface s_axilite port = NUM_ITE bundle = control - { auto val = reinterpret_cast(NUM_ITE); } - -#pragma HLS interface s_axilite port = NUM_A_LEN bundle = control - { auto val = reinterpret_cast(NUM_A_LEN); } - -#pragma HLS interface s_axilite port = M bundle = control - { auto val = reinterpret_cast(M); } - -#pragma HLS interface s_axilite port = K bundle = control - { auto val = reinterpret_cast(K); } - -#pragma HLS interface s_axilite port = P_N bundle = control - { auto val = reinterpret_cast(P_N); } - -#pragma HLS interface s_axilite port = alpha_u bundle = control - { auto val = reinterpret_cast(alpha_u); } - -#pragma HLS interface s_axilite port = beta_u bundle = control - { auto val = reinterpret_cast(beta_u); } - -#pragma HLS interface s_axilite port = return bundle = control -} - -} // extern "C" diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/black_hole_float_v16.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/black_hole_float_v16.cpp deleted file mode 100644 index bf2d8b25..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/black_hole_float_v16.cpp +++ /dev/null @@ -1,418 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in) { -#pragma HLS disaggregate variable = fifo_in -#pragma HLS interface ap_fifo port = fifo_in._ -#pragma HLS aggregate variable = fifo_in._ bit -#pragma HLS interface ap_fifo port = fifo_in._peek -#pragma HLS aggregate variable = fifo_in._peek bit - void(fifo_in._.empty()); - void(fifo_in._peek.empty()); - - for (;;) { -#pragma HLS pipeline style = stp II = 1 - fifo_in.read(nullptr); - } -} -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/black_hole_int.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/black_hole_int.cpp deleted file mode 100644 index 2f064cb8..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/black_hole_int.cpp +++ /dev/null @@ -1,418 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in) { -#pragma HLS disaggregate variable = fifo_in -#pragma HLS interface ap_fifo port = fifo_in._ -#pragma HLS aggregate variable = fifo_in._ bit -#pragma HLS interface ap_fifo port = fifo_in._peek -#pragma HLS aggregate variable = fifo_in._peek bit - void(fifo_in._.empty()); - void(fifo_in._peek.empty()); - - for (;;) { -#pragma HLS pipeline style = stp II = 1 - fifo_in.read(nullptr); - } -} -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/read_A.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/read_A.cpp deleted file mode 100644 index 0d6d0035..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/read_A.cpp +++ /dev/null @@ -1,452 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(tapa::async_mmap> &A, - tapa::ostream> &fifo_A, const int A_len, - const int P_N) { -#pragma HLS disaggregate variable = A -#pragma HLS interface ap_fifo port = A.read_addr._ -#pragma HLS aggregate variable = A.read_addr._ bit -#pragma HLS interface ap_fifo port = A.read_data._ -#pragma HLS aggregate variable = A.read_data._ bit -#pragma HLS interface ap_fifo port = A.write_addr._ -#pragma HLS aggregate variable = A.write_addr._ bit -#pragma HLS interface ap_fifo port = A.write_data._ -#pragma HLS aggregate variable = A.write_data._ bit -#pragma HLS interface ap_fifo port = A.write_resp._ -#pragma HLS aggregate variable = A.write_resp._ bit -#pragma HLS disaggregate variable = A.read_data -#pragma HLS interface ap_fifo port = A.read_data._peek -#pragma HLS aggregate variable = A.read_data._peek bit -#pragma HLS disaggregate variable = A.write_resp -#pragma HLS interface ap_fifo port = A.write_resp._peek -#pragma HLS aggregate variable = A.write_resp._peek bit - void(A.read_addr._.full()); - void(A.read_data._.empty()); - void(A.read_data._peek.empty()); - void(A.write_addr._.full()); - void(A.write_data._.full()); - void(A.write_resp._.empty()); - void(A.write_resp._peek.empty()); - -#pragma HLS disaggregate variable = fifo_A -#pragma HLS interface ap_fifo port = fifo_A._ -#pragma HLS aggregate variable = fifo_A._ bit - void(fifo_A._.full()); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - rd_A: - for (int i_req = 0, i_resp = 0; i_resp < A_len;) { -#pragma HLS loop_tripcount min = 1 max = 10000 -#pragma HLS pipeline style = stp II = 1 - async_read(A, fifo_A, A_len, i_req, i_resp); - } - } -} -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/read_B.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/read_B.cpp deleted file mode 100644 index df81de6b..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/read_B.cpp +++ /dev/null @@ -1,451 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(tapa::async_mmap &B, tapa::ostream &fifo_B, - const int K, const int P_N) { -#pragma HLS disaggregate variable = B -#pragma HLS interface ap_fifo port = B.read_addr._ -#pragma HLS aggregate variable = B.read_addr._ bit -#pragma HLS interface ap_fifo port = B.read_data._ -#pragma HLS aggregate variable = B.read_data._ bit -#pragma HLS interface ap_fifo port = B.write_addr._ -#pragma HLS aggregate variable = B.write_addr._ bit -#pragma HLS interface ap_fifo port = B.write_data._ -#pragma HLS aggregate variable = B.write_data._ bit -#pragma HLS interface ap_fifo port = B.write_resp._ -#pragma HLS aggregate variable = B.write_resp._ bit -#pragma HLS disaggregate variable = B.read_data -#pragma HLS interface ap_fifo port = B.read_data._peek -#pragma HLS aggregate variable = B.read_data._peek bit -#pragma HLS disaggregate variable = B.write_resp -#pragma HLS interface ap_fifo port = B.write_resp._peek -#pragma HLS aggregate variable = B.write_resp._peek bit - void(B.read_addr._.full()); - void(B.read_data._.empty()); - void(B.read_data._peek.empty()); - void(B.write_addr._.full()); - void(B.write_data._.full()); - void(B.write_resp._.empty()); - void(B.write_resp._peek.empty()); - -#pragma HLS disaggregate variable = fifo_B -#pragma HLS interface ap_fifo port = fifo_B._ -#pragma HLS aggregate variable = fifo_B._ bit - void(fifo_B._.full()); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int num_ite_B = ((K + 7) >> 3) * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - rd_B: - for (int i_req = 0, i_resp = 0; i_resp < num_ite_B;) { -#pragma HLS loop_tripcount min = 1 max = 500000 -#pragma HLS pipeline style = stp II = 1 - async_read(B, fifo_B, num_ite_B, i_req, i_resp); - } - } -} -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/read_C.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/read_C.cpp deleted file mode 100644 index 6d06f775..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/read_C.cpp +++ /dev/null @@ -1,458 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(tapa::async_mmap &C, tapa::ostream &fifo_C, - const int M, const int P_N, tapa::ostream &wrC_inst) { -#pragma HLS disaggregate variable = C -#pragma HLS interface ap_fifo port = C.read_addr._ -#pragma HLS aggregate variable = C.read_addr._ bit -#pragma HLS interface ap_fifo port = C.read_data._ -#pragma HLS aggregate variable = C.read_data._ bit -#pragma HLS interface ap_fifo port = C.write_addr._ -#pragma HLS aggregate variable = C.write_addr._ bit -#pragma HLS interface ap_fifo port = C.write_data._ -#pragma HLS aggregate variable = C.write_data._ bit -#pragma HLS interface ap_fifo port = C.write_resp._ -#pragma HLS aggregate variable = C.write_resp._ bit -#pragma HLS disaggregate variable = C.read_data -#pragma HLS interface ap_fifo port = C.read_data._peek -#pragma HLS aggregate variable = C.read_data._peek bit -#pragma HLS disaggregate variable = C.write_resp -#pragma HLS interface ap_fifo port = C.write_resp._peek -#pragma HLS aggregate variable = C.write_resp._peek bit - void(C.read_addr._.full()); - void(C.read_data._.empty()); - void(C.read_data._peek.empty()); - void(C.write_addr._.full()); - void(C.write_data._.full()); - void(C.write_resp._.empty()); - void(C.write_resp._peek.empty()); - -#pragma HLS disaggregate variable = fifo_C -#pragma HLS interface ap_fifo port = fifo_C._ -#pragma HLS aggregate variable = fifo_C._ bit - void(fifo_C._.full()); - -#pragma HLS disaggregate variable = wrC_inst -#pragma HLS interface ap_fifo port = wrC_inst._ -#pragma HLS aggregate variable = wrC_inst._ bit - void(wrC_inst._.full()); - - wrC_inst.write(M); - wrC_inst.write(P_N); - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int num_ite_C = ((M + 15) >> 4) * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - rd_C: - for (int i_req = 0, i_resp = 0; i_resp < num_ite_C;) { -#pragma HLS loop_tripcount min = 1 max = 500000 -#pragma HLS pipeline style = stp II = 1 - async_read(C, fifo_C, num_ite_C, i_req, i_resp); - } - } -} -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/read_edge_list_ptr.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/read_edge_list_ptr.cpp deleted file mode 100644 index 84e841a4..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/read_edge_list_ptr.cpp +++ /dev/null @@ -1,463 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, tapa::async_mmap &edge_list_ptr, - tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) { - -#pragma HLS disaggregate variable = edge_list_ptr -#pragma HLS interface ap_fifo port = edge_list_ptr.read_addr._ -#pragma HLS aggregate variable = edge_list_ptr.read_addr._ bit -#pragma HLS interface ap_fifo port = edge_list_ptr.read_data._ -#pragma HLS aggregate variable = edge_list_ptr.read_data._ bit -#pragma HLS interface ap_fifo port = edge_list_ptr.write_addr._ -#pragma HLS aggregate variable = edge_list_ptr.write_addr._ bit -#pragma HLS interface ap_fifo port = edge_list_ptr.write_data._ -#pragma HLS aggregate variable = edge_list_ptr.write_data._ bit -#pragma HLS interface ap_fifo port = edge_list_ptr.write_resp._ -#pragma HLS aggregate variable = edge_list_ptr.write_resp._ bit -#pragma HLS disaggregate variable = edge_list_ptr.read_data -#pragma HLS interface ap_fifo port = edge_list_ptr.read_data._peek -#pragma HLS aggregate variable = edge_list_ptr.read_data._peek bit -#pragma HLS disaggregate variable = edge_list_ptr.write_resp -#pragma HLS interface ap_fifo port = edge_list_ptr.write_resp._peek -#pragma HLS aggregate variable = edge_list_ptr.write_resp._peek bit - void(edge_list_ptr.read_addr._.full()); - void(edge_list_ptr.read_data._.empty()); - void(edge_list_ptr.read_data._peek.empty()); - void(edge_list_ptr.write_addr._.full()); - void(edge_list_ptr.write_data._.full()); - void(edge_list_ptr.write_resp._.empty()); - void(edge_list_ptr.write_resp._peek.empty()); - -#pragma HLS disaggregate variable = fifo_edge_list_ptr -#pragma HLS interface ap_fifo port = fifo_edge_list_ptr._ -#pragma HLS aggregate variable = fifo_edge_list_ptr._ bit - void(fifo_edge_list_ptr._.full()); - -#pragma HLS disaggregate variable = PE_inst -#pragma HLS interface ap_fifo port = PE_inst._ -#pragma HLS aggregate variable = PE_inst._ bit - void(PE_inst._.full()); - - PE_inst.write(num_ite); - PE_inst.write(M); - PE_inst.write(P_N); - PE_inst.write(K); - const int N = P_N & 0xFFFF; - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int num_ite_plus1 = num_ite + 1; - const int rp_time_N = rp_time * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - rd_ptr: - for (int i_req = 0, i_resp = 0; i_resp < num_ite_plus1;) { -#pragma HLS loop_tripcount min = 1 max = 800 -#pragma HLS pipeline style = stp II = 1 - async_read(edge_list_ptr, fifo_edge_list_ptr, num_ite_plus1, i_req, - i_resp); - } - } -} -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - uint64_t C_out); -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/cpp/write_C.cpp b/benchmarks/tapa_flow/sextans/design/generated/cpp/write_C.cpp deleted file mode 100644 index 16e9e312..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/cpp/write_C.cpp +++ /dev/null @@ -1,475 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, uint64_t edge_list_ptr, tapa::ostream &fifo_edge_list_ptr, - tapa::ostream &PE_inst); -void read_A(uint64_t A, tapa::ostream> &fifo_A, const int A_len, - const int P_N); -void read_B(uint64_t B, tapa::ostream &fifo_B, const int K, - const int P_N); -void read_C(uint64_t C, tapa::ostream &fifo_C, const int M, - const int P_N, tapa::ostream &wrC_inst); -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - tapa::async_mmap &C_out) { -#pragma HLS disaggregate variable = wrC_inst -#pragma HLS interface ap_fifo port = wrC_inst._ -#pragma HLS aggregate variable = wrC_inst._ bit -#pragma HLS interface ap_fifo port = wrC_inst._peek -#pragma HLS aggregate variable = wrC_inst._peek bit - void(wrC_inst._.empty()); - void(wrC_inst._peek.empty()); - -#pragma HLS disaggregate variable = fifo_C -#pragma HLS interface ap_fifo port = fifo_C._ -#pragma HLS aggregate variable = fifo_C._ bit -#pragma HLS interface ap_fifo port = fifo_C._peek -#pragma HLS aggregate variable = fifo_C._peek bit - void(fifo_C._.empty()); - void(fifo_C._peek.empty()); - -#pragma HLS disaggregate variable = C_out -#pragma HLS interface ap_fifo port = C_out.read_addr._ -#pragma HLS aggregate variable = C_out.read_addr._ bit -#pragma HLS interface ap_fifo port = C_out.read_data._ -#pragma HLS aggregate variable = C_out.read_data._ bit -#pragma HLS interface ap_fifo port = C_out.write_addr._ -#pragma HLS aggregate variable = C_out.write_addr._ bit -#pragma HLS interface ap_fifo port = C_out.write_data._ -#pragma HLS aggregate variable = C_out.write_data._ bit -#pragma HLS interface ap_fifo port = C_out.write_resp._ -#pragma HLS aggregate variable = C_out.write_resp._ bit -#pragma HLS disaggregate variable = C_out.read_data -#pragma HLS interface ap_fifo port = C_out.read_data._peek -#pragma HLS aggregate variable = C_out.read_data._peek bit -#pragma HLS disaggregate variable = C_out.write_resp -#pragma HLS interface ap_fifo port = C_out.write_resp._peek -#pragma HLS aggregate variable = C_out.write_resp._peek bit - void(C_out.read_addr._.full()); - void(C_out.read_data._.empty()); - void(C_out.read_data._peek.empty()); - void(C_out.write_addr._.full()); - void(C_out.write_data._.full()); - void(C_out.write_resp._.empty()); - void(C_out.write_resp._peek.empty()); - - int M = wrC_inst.read(); - int P_N = wrC_inst.read(); - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int num_ite_C = ((M + 15) >> 4) * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - wr_C: - for (int i_req = 0, i_resp = 0; i_resp < num_ite_C;) { -#pragma HLS loop_tripcount min = 1 max = 500000 -#pragma HLS pipeline style = stp II = 1 - if ((i_req < num_ite_C) & !fifo_C.empty() & !C_out.write_addr.full() & - !C_out.write_data.full()) { - C_out.write_addr.try_write(i_req); - float_v16 tmpv; - fifo_C.try_read(tmpv); - C_out.write_data.try_write(tmpv); - ++i_req; - } - uint8_t n_resp; - if (C_out.write_resp.try_read(n_resp)) { - i_resp += int(n_resp) + 1; - } - } - } -} -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out); -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out); -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec); -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out); -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out); -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out); -void black_hole_int(tapa::istream &fifo_in); -void black_hole_float_v16(tapa::istream &fifo_in); -void Sextans(uint64_t edge_list_ptr, uint64_t edge_list_ch_0, - uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, - uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, - uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, - uint64_t edge_list_ch_7, uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, - uint64_t mat_B_ch_2, uint64_t mat_B_ch_3, uint64_t mat_C_ch_in_0, - uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, - uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, - uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, - uint64_t mat_C_ch_in_7, uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, - uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, - uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, - const int NUM_ITE, const int NUM_A_LEN, const int M, const int K, - const int P_N, const int alpha_u, const int beta_u); diff --git a/benchmarks/tapa_flow/sextans/design/generated/flatten/flatten-f5eeaffa-sextans.cpp b/benchmarks/tapa_flow/sextans/design/generated/flatten/flatten-f5eeaffa-sextans.cpp deleted file mode 100644 index dea949a0..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/flatten/flatten-f5eeaffa-sextans.cpp +++ /dev/null @@ -1,822 +0,0 @@ - - -#include - -#include - -#include - -#include - -#include - -#include - -#include -constexpr int NUM_CH_SPARSE = 8; -constexpr int NUM_CH_B = 4; -constexpr int NUM_CH_C = 8; -const int WINDOW_SIZE = 4096; -const int DEP_DIST_LOAD_STORE = 10; -const int B_PARTITION_FACTOR = 4; -const int URAM_DEPTH = 8192; -using float_v16 = tapa::vec_t; -using float_v8 = tapa::vec_t; -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, int beta_u); -//#include "modules.h" -constexpr int FIFO_DEPTH = 2; -constexpr int PEG_PER_A = 512 / 256; -struct MultBVec { - ap_uint<18> row; - float_v8 abvec; -}; -template -inline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A, - const R A_len, R &i_req, R &i_resp) { -#pragma HLS inline - if ((i_req < A_len) & !A.read_addr.full()) { - A.read_addr.try_write(i_req); - ++i_req; - } - if (!fifo_A.full() & !A.read_data.empty()) { - T tmp; - A.read_data.try_read(tmp); - fifo_A.try_write(tmp); - ++i_resp; - } -} -void read_edge_list_ptr( - const int num_ite, const int M, - const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N - const int K, tapa::async_mmap &edge_list_ptr, - tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) { - PE_inst.write(num_ite); - PE_inst.write(M); - PE_inst.write(P_N); - PE_inst.write(K); - const int N = P_N & 0xFFFF; - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int num_ite_plus1 = num_ite + 1; - const int rp_time_N = rp_time * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - rd_ptr: - for (int i_req = 0, i_resp = 0; i_resp < num_ite_plus1;) { -#pragma HLS loop_tripcount min = 1 max = 800 -#pragma HLS pipeline style = stp II = 1 - async_read(edge_list_ptr, fifo_edge_list_ptr, num_ite_plus1, i_req, - i_resp); - } - } -} -void read_A(tapa::async_mmap> &A, - tapa::ostream> &fifo_A, const int A_len, - const int P_N) { - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - rd_A: - for (int i_req = 0, i_resp = 0; i_resp < A_len;) { -#pragma HLS loop_tripcount min = 1 max = 10000 -#pragma HLS pipeline style = stp II = 1 - async_read(A, fifo_A, A_len, i_req, i_resp); - } - } -} -void read_B(tapa::async_mmap &B, tapa::ostream &fifo_B, - const int K, const int P_N) { - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int num_ite_B = ((K + 7) >> 3) * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - rd_B: - for (int i_req = 0, i_resp = 0; i_resp < num_ite_B;) { -#pragma HLS loop_tripcount min = 1 max = 500000 -#pragma HLS pipeline style = stp II = 1 - async_read(B, fifo_B, num_ite_B, i_req, i_resp); - } - } -} -void read_C(tapa::async_mmap &C, tapa::ostream &fifo_C, - const int M, const int P_N, tapa::ostream &wrC_inst) { - wrC_inst.write(M); - wrC_inst.write(P_N); - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int num_ite_C = ((M + 15) >> 4) * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - rd_C: - for (int i_req = 0, i_resp = 0; i_resp < num_ite_C;) { -#pragma HLS loop_tripcount min = 1 max = 500000 -#pragma HLS pipeline style = stp II = 1 - async_read(C, fifo_C, num_ite_C, i_req, i_resp); - } - } -} -void write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C, - tapa::async_mmap &C_out) { - int M = wrC_inst.read(); - int P_N = wrC_inst.read(); - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int num_ite_C = ((M + 15) >> 4) * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - wr_C: - for (int i_req = 0, i_resp = 0; i_resp < num_ite_C;) { -#pragma HLS loop_tripcount min = 1 max = 500000 -#pragma HLS pipeline style = stp II = 1 - if ((i_req < num_ite_C) & !fifo_C.empty() & !C_out.write_addr.full() & - !C_out.write_data.full()) { - C_out.write_addr.try_write(i_req); - float_v16 tmpv; - fifo_C.try_read(tmpv); - C_out.write_data.try_write(tmpv); - ++i_req; - } - uint8_t n_resp; - if (C_out.write_resp.try_read(n_resp)) { - i_resp += int(n_resp) + 1; - } - } - } -} -void FloatvMultConst(const int alpha_u, const int M, const int P_N, - tapa::istream &fifo_in, - tapa::ostream &fifo_out) { - const float alpha_f = tapa::bit_cast(alpha_u); - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int num_ite = ((M + 15) >> 4) * ((N + 7) >> 3) * rp_time; -cc: - for (int i = 0; i < num_ite;) { -#pragma HLS pipeline style = stp II = 1 - float_v16 tmp; - bool read_ready = fifo_in.try_read(tmp); - if (read_ready) { - float_v16 c_out = tmp * alpha_f; - fifo_out.write(c_out); - ++i; - } - } -} -void FloatvAddFloatv(tapa::istream &fifo_in0, - tapa::istream &fifo_in1, - tapa::ostream &fifo_out) { -cc: - for (;;) { -#pragma HLS pipeline style = stp II = 1 - bool flag_nop = fifo_in0.empty() | fifo_in1.empty(); - if (!flag_nop) { - float_v16 tmp0; - fifo_in0.try_read(tmp0); - float_v16 tmp1; - fifo_in1.try_read(tmp1); - float_v16 c_out = tmp0 + tmp1; - fifo_out.write(c_out); - } - } -} -/* -void PU2core(ap_uint<18> & addr_c, - float a_val_f, - float b_val_d0_f, - float b_val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH] - ) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - - float c_val_d0_f = tapa::bit_cast(c_val_d0_u); - float c_val_d1_f = tapa::bit_cast(c_val_d1_u); - - c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f; - c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f; - - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} - -void PEcore(ap_uint<14> & addr_b, - ap_uint<18> & addr_c, - ap_uint<32> & a_val_u, - ap_uint<64> local_C[4][URAM_DEPTH], - float local_B[8][WINDOW_SIZE] - ) { -#pragma HLS inline - //if (addr_c != ((ap_uint<18>) 0x3FFFF)) { - if (addr_c[17] == 0) { - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 4; ++i) { - PU2core(addr_c, - a_val_f, - local_B[i*2+0][addr_b], - local_B[i*2+1][addr_b], - local_C[i] - ); - } - } -} -*/ -void PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u, - float local_B[8][WINDOW_SIZE], float_v8 &abv) { -#pragma HLS inline - float a_val_f = tapa::bit_cast(a_val_u); - for (int i = 0; i < 8; ++i) { - abv[i] = a_val_f * local_B[i][addr_b]; - } -} -void PEG_Bmtx( - tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - // tapa::istream> & fifo_A, - tapa::istream> &fifo_A, - tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out, - tapa::ostreams &fifo_B_out, - // to PEG_Cmtx - tapa::ostream &PE_inst_to_Cmtx, - tapa::ostream &fifo_inst_out_to_Cmtx, - tapa::ostreams &fifo_aBvec) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - PE_inst_to_Cmtx.write(NUM_ITE); - PE_inst_to_Cmtx.write(M); - PE_inst_to_Cmtx.write(P_N); - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); -l_rp: - for (int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - // float local_B[8/2][8][WINDOW_SIZE]; - // float local_B[8][WINDOW_SIZE]; - float local_B[4 / 2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable = local_B latency = 2 -#pragma HLS array_partition variable = local_B complete dim = 1 -#pragma HLS array_partition variable = local_B complete dim = 2 -#pragma HLS array_partition variable = local_B cyclic factor = \ - B_PARTITION_FACTOR dim = 3 - //#pragma HLS array_partition variable=local_B cyclic - //factor=B_PARTITION_FACTOR dim=2 - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - fifo_inst_out_to_Cmtx.write(start_32); - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min = 1 max = 49 - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && - (j < ((K + 7) >> 3) - i * (WINDOW_SIZE >> 3));) { -#pragma HLS loop_tripcount min = 1 max = 512 -#pragma HLS pipeline style = stp II = 1 - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - fifo_B_in[k].try_read(b_512_x[k]); - fifo_B_out[k].try_write(b_512_x[k]); - } - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m / 2][k + m % 2 * 8]; - } - } - } - ++j; - } - } - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - fifo_inst_out_to_Cmtx.write(end_32); - computation: - for (int j = start_32; j < end_32;) { -#pragma HLS loop_tripcount min = 1 max = 200 -#pragma HLS pipeline style = stp II = 1 - // ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - if (a_pes_ready) { - for (int p = 0; p < 4; ++p) { - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - ap_uint<14> a_col = a(63, 50); - ap_uint<18> a_row = a(49, 32); - ap_uint<32> a_val = a(31, 0); - MultBVec rabv; - rabv.row = a_row; - if (a_row[17] == 0) { - // PE process - PEcore_Bmtx(a_col, a_val, local_B[p / 2], rabv.abvec); - } - fifo_aBvec[p].write(rabv); - } - ++j; - } - } - start_32 = end_32; - } - } -} -void PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f, - ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) { -#pragma HLS inline - ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c]; - ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0); - ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32); - float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f; - float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f; - c_val_d0_u = tapa::bit_cast>(c_val_d0_f); - c_val_d1_u = tapa::bit_cast>(c_val_d1_f); - c_val_d0_d1_u64(31, 0) = c_val_d0_u; - c_val_d0_d1_u64(63, 32) = c_val_d1_u; - local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64; -} -void PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec, - ap_uint<64> local_C[4][URAM_DEPTH]) { -#pragma HLS inline - for (int i = 0; i < 4; ++i) { - PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]); - } -} -void PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in, - tapa::istreams &fifo_aBvec, - tapa::ostream &fifo_C_out) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0) ? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - const int num_v_init = (M + 63) >> 6; - // const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - // define local C buffer and pragma to URAM - // ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable = local_C type = RAM_2P impl = \ - URAM latency = 1 -#pragma HLS array_partition complete variable = local_C dim = 1 -#pragma HLS array_partition complete variable = local_C dim = 2 -l_rp: - for (int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min = 1 max = 16 - // init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min = 1 max = 800 -#pragma HLS pipeline style = stp II = 1 - // for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - auto start_32 = fifo_inst_in.read(); - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min = 1 max = 49 - // computation - const auto end_32 = fifo_inst_in.read(); - computation: - for (int j = start_32; j < end_32;) { -#pragma HLS loop_tripcount min = 1 max = 200 -#pragma HLS pipeline style = stp II = 1 -#pragma HLS dependence true variable = local_C distance = DEP_DIST_LOAD_STORE - bool nop_flag = false; - for (int p = 0; p < 4; ++p) { - nop_flag |= fifo_aBvec[p].empty(); - } - if (!nop_flag) { - for (int p = 0; p < 4; ++p) { - MultBVec rabv; - fifo_aBvec[p].try_read(rabv); - ap_uint<18> a_row = rabv.row; - if (a_row[17] == 0) { - PEcore_Cmtx(a_row, rabv.abvec, local_C[p]); - } - } - ++j; - } - } - start_32 = end_32; - } - // cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min = 1 max = 1800 -#pragma HLS pipeline style = stp II = 1 - ap_uint<32> u_32_d[8]; - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i >> 2]; - u_32_d[2 * d] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - switch (c_idx) { // 0,2,1,3 - case 0: - c_idx = 2; - break; - case 1: - c_idx = 3; - break; - case 2: - c_idx = 1; - break; - case 3: - c_idx = 0; - break; - } - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - // for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << - // endl; - } - } -} -/* -void PEG(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - tapa::streams fifo_aBvec("fifo_aBvec"); - tapa::stream PE_inst_to_Cmtx("PE_inst_to_Cmtx"); - tapa::stream -fifo_inst_out_to_Cmtx("fifo_inst_out_to_Cmtx"); - - tapa::task() - .invoke(PEG_Bmtx, - PE_inst_in, - fifo_inst_in, - fifo_A, - fifo_B_in, - PE_inst_out, - fifo_inst_out, - fifo_B_out, - // to PEG_Cmtx - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec) - - .invoke(PEG_Cmtx, - PE_inst_to_Cmtx, - fifo_inst_out_to_Cmtx, - fifo_aBvec, - fifo_C_out) - ; -} - -void PEG_c(tapa::istream & PE_inst_in, - tapa::istream & fifo_inst_in, - //tapa::istream> & fifo_A, - tapa::istream> & fifo_A, - tapa::istreams & fifo_B_in, // [256(16)] * 2, 2: -dim d - // [64(32bits * 2.0)] * 8 dim - tapa::ostream & PE_inst_out, - tapa::ostream & fifo_inst_out, - tapa::ostreams & fifo_B_out, - tapa::ostream & fifo_C_out - ) { - const int NUM_ITE = PE_inst_in.read(); - const int M = PE_inst_in.read(); - const int P_N = PE_inst_in.read(); - const int K = PE_inst_in.read(); - - PE_inst_out.write(NUM_ITE); - PE_inst_out.write(M); - PE_inst_out.write(P_N); - PE_inst_out.write(K); - - const int N16 = P_N >> 16; - const int rp_time = (N16 == 0)? 1 : N16; - const int N = P_N & 0xFFFF; - const int rp_time_N = rp_time * ((N + 7) >> 3); - - const int num_v_init = (M + 63) >> 6; - //const int num_v_out = (M + 31) >> 5; - const int num_v_out = (M + 15) >> 4; - - //define local C buffer and pragma to URAM - //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH]; - ap_uint<64> local_C[4][8 / 2][URAM_DEPTH]; -#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1 -#pragma HLS array_partition complete variable=local_C dim=1 -#pragma HLS array_partition complete variable=local_C dim=2 - -l_rp: - for(int rp = 0; rp < rp_time_N; rp++) { -#pragma HLS loop_flatten off -#pragma HLS loop_tripcount min=1 max=16 - - //init local C - init_C: - for (int i = 0; i < num_v_init; ++i) { -#pragma HLS loop_tripcount min=1 max=800 -#pragma HLS pipeline style=stp II=1 - //for (int j = 0; j < 2; ++j) { - for (int j = 0; j < 4; ++j) { - for (int k = 0; k < 8 / 2; ++k) { - local_C[j][k][i] = 0; - } - } - } - //define local B buffer and pragma local B buffer if partition factor > -1 - - //float local_B[8/2][8][WINDOW_SIZE]; - //float local_B[8][WINDOW_SIZE]; - float local_B[4/2][8][WINDOW_SIZE]; -#pragma HLS bind_storage variable=local_B latency=2 -#pragma HLS array_partition variable=local_B complete dim=1 -#pragma HLS array_partition variable=local_B complete dim=2 -#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=3 -//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR -dim=2 - - auto start_32 = fifo_inst_in.read(); - fifo_inst_out.write(start_32); - - main: - for (int i = 0; i < NUM_ITE; ++i) { -#pragma HLS loop_tripcount min=1 max=49 - - // fill onchip B - read_B: - for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i -* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS -pipeline style=stp II = 1 - - bool b_2048_ready = true; - bool b_2048_out_not_full = true; - for (int k = 0; k < NUM_CH_B; ++k) { - b_2048_ready &= !fifo_B_in[k].empty(); - b_2048_out_not_full &= !fifo_B_out[k].full(); - } - - if (b_2048_ready & b_2048_out_not_full) { - float_v16 b_512_x[NUM_CH_B]; - for (int k = 0; k < NUM_CH_B; ++k) { - b_512_x[k] = fifo_B_in[k].read(); - fifo_B_out[k].write(b_512_x[k]); - } - - for (int k = 0; k < 8; ++k) { - for (int m = 0; m < 8; ++m) { - for (int l = 0; l < 2; ++l) { - local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m % -2 * 8]; - } - } - } - ++j; - } - } - - // computation - const auto end_32 = fifo_inst_in.read(); - fifo_inst_out.write(end_32); - - computation: - for (int j = start_32; j < end_32; ) { -#pragma HLS loop_tripcount min=1 max=200 -#pragma HLS pipeline style=stp II=1 -#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE - - //ap_uint<128> a_pes; - ap_uint<256> a_pes; - bool a_pes_ready = fifo_A.try_read(a_pes); - - if (a_pes_ready) { - //for (int p = 0; p < 2; ++p) { - for (int p = 0; p < 4; ++p) { - ap_uint<14> a_col; - ap_uint<18> a_row; - ap_uint<32> a_val; - - ap_uint<64> a = a_pes(63 + p * 64, p * 64); - a_col = a(63, 50); - a_row = a(49, 32); - a_val = a(31, 0); - - // PE process - PEcore(a_col, - a_row, - a_val, - local_C[p], - //local_B - local_B[p/2] - ); - } - ++j; - } - } - start_32 = end_32; - } - - //cout << "PE = " << pe_idx << endl; - write_C_outer: - for (int i = 0, c_idx = 0; i < num_v_out; ++i) { -#pragma HLS loop_tripcount min=1 max=1800 -#pragma HLS pipeline style=stp II=1 - ap_uint<32> u_32_d[8]; - - for (int d = 0; d < 4; ++d) { - ap_uint<64> u_64 = local_C[c_idx][d][i>>2]; - u_32_d[2 * d ] = u_64(31, 0); - u_32_d[2 * d + 1] = u_64(63, 32); - } - - switch (c_idx) { //0,2,1,3 - case 0: c_idx = 2; break; - case 1: c_idx = 3; break; - case 2: c_idx = 1; break; - case 3: c_idx = 0; break; - } - - float_v8 out_v; - for (int d = 0; d < 8; ++d) { - out_v[d] = tapa::bit_cast(u_32_d[d]); - } - fifo_C_out.write(out_v); - //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << " ";} cout << -endl; - } - } -} -*/ -void Scatter_1_2(tapa::istream> &fifo_in, - tapa::ostreams, 2> &fifo_out) { - for (;;) { -#pragma HLS pipeline style = stp II = 1 - bool flag_nop = fifo_in.empty(); - for (int i = 0; i < 2; ++i) { - flag_nop |= fifo_out[i].full(); - } - if (!flag_nop) { - ap_uint<512> tmp; - fifo_in.try_read(tmp); - for (int i = 0; i < 2; ++i) { - fifo_out[i].try_write(tmp(255 + i * 256, i * 256)); - } - } - } -} -void Merger(tapa::istreams &fifo_in, - tapa::ostream &fifo_out) { - for (;;) { -#pragma HLS pipeline style = stp II = 1 - bool flag_nop = fifo_out.full() | fifo_in[0].empty() | fifo_in[1].empty(); - if (!flag_nop) { - float_v16 tmpv16; - float_v8 tmpv8[2]; -#pragma HLS aggregate variable = tmpv16 - fifo_in[0].try_read(tmpv8[0]); - fifo_in[1].try_read(tmpv8[1]); - for (int i = 0; i < 8; ++i) { - tmpv16[i] = tmpv8[0][i]; - tmpv16[i + 8] = tmpv8[1][i]; - } - fifo_out.try_write(tmpv16); - } - } -} -void black_hole_int(tapa::istream &fifo_in) { - for (;;) { -#pragma HLS pipeline style = stp II = 1 - fifo_in.read(nullptr); - } -} -void black_hole_float_v16(tapa::istream &fifo_in) { - for (;;) { -#pragma HLS pipeline style = stp II = 1 - fifo_in.read(nullptr); - } -} -void Sextans(tapa::mmap edge_list_ptr, - tapa::mmaps, NUM_CH_SPARSE> edge_list_ch, - tapa::mmaps mat_B_ch, - tapa::mmaps mat_C_ch_in, - tapa::mmaps mat_C_ch, const int NUM_ITE, - const int NUM_A_LEN, const int M, const int K, const int P_N, - const int alpha_u, const int beta_u) { - tapa::streams PE_inst( - "PE_inst"); - tapa::streams wrC_inst("wrC_inst"); - tapa::streams - fifo_edge_list_ptr("fifo_edge_list_ptr"); - tapa::streams PE_inst_to_Cmtx( - "PE_inst_to_Cmtx"); - tapa::streams - fifo_edge_list_ptr_to_Cmtx("fifo_edge_list_ptr_to_Cmtx"); - /* ============================== */ - tapa::streams, NUM_CH_SPARSE, FIFO_DEPTH> fifo_A("fifo_A"); - tapa::streams, NUM_CH_SPARSE * PEG_PER_A, FIFO_DEPTH> fifo_A_pe( - "fifo_A_pe"); - tapa::streams - fifo_B_pe("fifo_B_pe"); - tapa::streams fifo_C_pe( - "fifo_C_pe"); - tapa::streams fifo_aBvec( - "fifo_aBvec"); - tapa::streams fifo_C_read_in( - "fifo_C_read_in"); - tapa::streams fifo_C_read_in_beta( - "fifo_C_read_in_beta"); - tapa::streams fifo_C_ch_result( - "fifo_C_ch_result"); - tapa::streams fifo_C_ch_result_alpha( - "fifo_C_ch_result_alpha"); - tapa::streams fifo_C_ch("fifo_C_ch"); - tapa::task() - .invoke(read_edge_list_ptr, NUM_ITE, M, P_N, K, edge_list_ptr, - fifo_edge_list_ptr, PE_inst) - .invoke(read_A, edge_list_ch, fifo_A, - NUM_A_LEN, P_N) - .invoke(Scatter_1_2, fifo_A, fifo_A_pe) - .invoke(read_B, mat_B_ch, fifo_B_pe, K, P_N) - .invoke( - PEG_Bmtx, PE_inst, fifo_edge_list_ptr, fifo_A_pe, fifo_B_pe, PE_inst, - fifo_edge_list_ptr, fifo_B_pe, PE_inst_to_Cmtx, - fifo_edge_list_ptr_to_Cmtx, fifo_aBvec) - .invoke(PEG_Cmtx, PE_inst_to_Cmtx, - fifo_edge_list_ptr_to_Cmtx, - fifo_aBvec, fifo_C_pe) - .invoke(black_hole_int, PE_inst) - .invoke(black_hole_int, fifo_edge_list_ptr) - .invoke(black_hole_float_v16, fifo_B_pe) - .invoke(Merger, fifo_C_pe, fifo_C_ch_result) - .invoke(read_C, mat_C_ch_in, fifo_C_read_in, M, P_N, - wrC_inst) - .invoke(FloatvMultConst, beta_u, M, P_N, - fifo_C_read_in, fifo_C_read_in_beta) - .invoke(FloatvMultConst, alpha_u, M, P_N, - fifo_C_ch_result, fifo_C_ch_result_alpha) - .invoke(FloatvAddFloatv, fifo_C_ch_result_alpha, - fifo_C_read_in_beta, fifo_C_ch) - .invoke(write_C, wrC_inst, fifo_C_ch, mat_C_ch); -} diff --git a/benchmarks/tapa_flow/sextans/design/generated/graph.json b/benchmarks/tapa_flow/sextans/design/generated/graph.json deleted file mode 100644 index 7d4ee9cf..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/graph.json +++ /dev/null @@ -1,6798 +0,0 @@ -{ - "cflags": [ - "-std=c++17", - "-I", - "/home/Licheng-Guo/dev/tapa/backend/python/tapa/../../../src", - "-isystem", - "/opt/tools/xilinx/Vitis_HLS/2022.2/include" - ], - "tasks": { - "FloatvAddFloatv": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) {\n#pragma HLS disaggregate variable = fifo_in0\n#pragma HLS interface ap_fifo port = fifo_in0._\n#pragma HLS aggregate variable = fifo_in0._ bit\n#pragma HLS interface ap_fifo port = fifo_in0._peek\n#pragma HLS aggregate variable = fifo_in0._peek bit\nvoid(fifo_in0._.empty());\nvoid(fifo_in0._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_in1\n#pragma HLS interface ap_fifo port = fifo_in1._\n#pragma HLS aggregate variable = fifo_in1._ bit\n#pragma HLS interface ap_fifo port = fifo_in1._peek\n#pragma HLS aggregate variable = fifo_in1._peek bit\nvoid(fifo_in1._.empty());\nvoid(fifo_in1._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_out\n#pragma HLS interface ap_fifo port = fifo_out._\n#pragma HLS aggregate variable = fifo_out._ bit\nvoid(fifo_out._.full());\n\ncc:\n for (;;) {\n#pragma HLS pipeline style = stp II = 1\n bool flag_nop = fifo_in0.empty() | fifo_in1.empty();\n if (!flag_nop) {\n float_v16 tmp0;\n fifo_in0.try_read(tmp0);\n float_v16 tmp1;\n fifo_in1.try_read(tmp1);\n float_v16 c_out = tmp0 + tmp1;\n fifo_out.write(c_out);\n }\n }\n}\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "FloatvMultConst": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) {\n\n\n\n#pragma HLS disaggregate variable = fifo_in\n#pragma HLS interface ap_fifo port = fifo_in._\n#pragma HLS aggregate variable = fifo_in._ bit\n#pragma HLS interface ap_fifo port = fifo_in._peek\n#pragma HLS aggregate variable = fifo_in._peek bit\nvoid(fifo_in._.empty());\nvoid(fifo_in._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_out\n#pragma HLS interface ap_fifo port = fifo_out._\n#pragma HLS aggregate variable = fifo_out._ bit\nvoid(fifo_out._.full());\n\n const float alpha_f = tapa::bit_cast(alpha_u);\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0) ? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int num_ite = ((M + 15) >> 4) * ((N + 7) >> 3) * rp_time;\ncc:\n for (int i = 0; i < num_ite;) {\n#pragma HLS pipeline style = stp II = 1\n float_v16 tmp;\n bool read_ready = fifo_in.try_read(tmp);\n if (read_ready) {\n float_v16 c_out = tmp * alpha_f;\n fifo_out.write(c_out);\n ++i;\n }\n }\n}\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "Merger": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) {\n#pragma HLS disaggregate variable = fifo_in\n#pragma HLS array_partition variable = fifo_in complete\n#pragma HLS interface ap_fifo port = fifo_in[0]._\n#pragma HLS aggregate variable = fifo_in[0]._ bit\n#pragma HLS interface ap_fifo port = fifo_in[0]._peek\n#pragma HLS aggregate variable = fifo_in[0]._peek bit\nvoid(fifo_in[0]._.empty());\nvoid(fifo_in[0]._peek.empty());\n#pragma HLS interface ap_fifo port = fifo_in[1]._\n#pragma HLS aggregate variable = fifo_in[1]._ bit\n#pragma HLS interface ap_fifo port = fifo_in[1]._peek\n#pragma HLS aggregate variable = fifo_in[1]._peek bit\nvoid(fifo_in[1]._.empty());\nvoid(fifo_in[1]._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_out\n#pragma HLS interface ap_fifo port = fifo_out._\n#pragma HLS aggregate variable = fifo_out._ bit\nvoid(fifo_out._.full());\n\n for (;;) {\n#pragma HLS pipeline style = stp II = 1\n bool flag_nop = fifo_out.full() | fifo_in[0].empty() | fifo_in[1].empty();\n if (!flag_nop) {\n float_v16 tmpv16;\n float_v8 tmpv8[2];\n#pragma HLS aggregate variable = tmpv16\n fifo_in[0].try_read(tmpv8[0]);\n fifo_in[1].try_read(tmpv8[1]);\n for (int i = 0; i < 8; ++i) {\n tmpv16[i] = tmpv8[0][i];\n tmpv16[i + 8] = tmpv8[1][i];\n }\n fifo_out.try_write(tmpv16);\n }\n }\n}\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "PEG_Bmtx": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) {\n#pragma HLS disaggregate variable = PE_inst_in\n#pragma HLS interface ap_fifo port = PE_inst_in._\n#pragma HLS aggregate variable = PE_inst_in._ bit\n#pragma HLS interface ap_fifo port = PE_inst_in._peek\n#pragma HLS aggregate variable = PE_inst_in._peek bit\nvoid(PE_inst_in._.empty());\nvoid(PE_inst_in._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_inst_in\n#pragma HLS interface ap_fifo port = fifo_inst_in._\n#pragma HLS aggregate variable = fifo_inst_in._ bit\n#pragma HLS interface ap_fifo port = fifo_inst_in._peek\n#pragma HLS aggregate variable = fifo_inst_in._peek bit\nvoid(fifo_inst_in._.empty());\nvoid(fifo_inst_in._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_A\n#pragma HLS interface ap_fifo port = fifo_A._\n#pragma HLS aggregate variable = fifo_A._ bit\n#pragma HLS interface ap_fifo port = fifo_A._peek\n#pragma HLS aggregate variable = fifo_A._peek bit\nvoid(fifo_A._.empty());\nvoid(fifo_A._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_B_in\n#pragma HLS array_partition variable = fifo_B_in complete\n#pragma HLS interface ap_fifo port = fifo_B_in[0]._\n#pragma HLS aggregate variable = fifo_B_in[0]._ bit\n#pragma HLS interface ap_fifo port = fifo_B_in[0]._peek\n#pragma HLS aggregate variable = fifo_B_in[0]._peek bit\nvoid(fifo_B_in[0]._.empty());\nvoid(fifo_B_in[0]._peek.empty());\n#pragma HLS interface ap_fifo port = fifo_B_in[1]._\n#pragma HLS aggregate variable = fifo_B_in[1]._ bit\n#pragma HLS interface ap_fifo port = fifo_B_in[1]._peek\n#pragma HLS aggregate variable = fifo_B_in[1]._peek bit\nvoid(fifo_B_in[1]._.empty());\nvoid(fifo_B_in[1]._peek.empty());\n#pragma HLS interface ap_fifo port = fifo_B_in[2]._\n#pragma HLS aggregate variable = fifo_B_in[2]._ bit\n#pragma HLS interface ap_fifo port = fifo_B_in[2]._peek\n#pragma HLS aggregate variable = fifo_B_in[2]._peek bit\nvoid(fifo_B_in[2]._.empty());\nvoid(fifo_B_in[2]._peek.empty());\n#pragma HLS interface ap_fifo port = fifo_B_in[3]._\n#pragma HLS aggregate variable = fifo_B_in[3]._ bit\n#pragma HLS interface ap_fifo port = fifo_B_in[3]._peek\n#pragma HLS aggregate variable = fifo_B_in[3]._peek bit\nvoid(fifo_B_in[3]._.empty());\nvoid(fifo_B_in[3]._peek.empty());\n\n#pragma HLS disaggregate variable = PE_inst_out\n#pragma HLS interface ap_fifo port = PE_inst_out._\n#pragma HLS aggregate variable = PE_inst_out._ bit\nvoid(PE_inst_out._.full());\n\n#pragma HLS disaggregate variable = fifo_inst_out\n#pragma HLS interface ap_fifo port = fifo_inst_out._\n#pragma HLS aggregate variable = fifo_inst_out._ bit\nvoid(fifo_inst_out._.full());\n\n#pragma HLS disaggregate variable = fifo_B_out\n#pragma HLS array_partition variable = fifo_B_out complete\n#pragma HLS interface ap_fifo port = fifo_B_out[0]._\n#pragma HLS aggregate variable = fifo_B_out[0]._ bit\nvoid(fifo_B_out[0]._.full());\n#pragma HLS interface ap_fifo port = fifo_B_out[1]._\n#pragma HLS aggregate variable = fifo_B_out[1]._ bit\nvoid(fifo_B_out[1]._.full());\n#pragma HLS interface ap_fifo port = fifo_B_out[2]._\n#pragma HLS aggregate variable = fifo_B_out[2]._ bit\nvoid(fifo_B_out[2]._.full());\n#pragma HLS interface ap_fifo port = fifo_B_out[3]._\n#pragma HLS aggregate variable = fifo_B_out[3]._ bit\nvoid(fifo_B_out[3]._.full());\n\n#pragma HLS disaggregate variable = PE_inst_to_Cmtx\n#pragma HLS interface ap_fifo port = PE_inst_to_Cmtx._\n#pragma HLS aggregate variable = PE_inst_to_Cmtx._ bit\nvoid(PE_inst_to_Cmtx._.full());\n\n#pragma HLS disaggregate variable = fifo_inst_out_to_Cmtx\n#pragma HLS interface ap_fifo port = fifo_inst_out_to_Cmtx._\n#pragma HLS aggregate variable = fifo_inst_out_to_Cmtx._ bit\nvoid(fifo_inst_out_to_Cmtx._.full());\n\n#pragma HLS disaggregate variable = fifo_aBvec\n#pragma HLS array_partition variable = fifo_aBvec complete\n#pragma HLS interface ap_fifo port = fifo_aBvec[0]._\n#pragma HLS aggregate variable = fifo_aBvec[0]._ bit\nvoid(fifo_aBvec[0]._.full());\n#pragma HLS interface ap_fifo port = fifo_aBvec[1]._\n#pragma HLS aggregate variable = fifo_aBvec[1]._ bit\nvoid(fifo_aBvec[1]._.full());\n#pragma HLS interface ap_fifo port = fifo_aBvec[2]._\n#pragma HLS aggregate variable = fifo_aBvec[2]._ bit\nvoid(fifo_aBvec[2]._.full());\n#pragma HLS interface ap_fifo port = fifo_aBvec[3]._\n#pragma HLS aggregate variable = fifo_aBvec[3]._ bit\nvoid(fifo_aBvec[3]._.full());\n\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n PE_inst_to_Cmtx.write(NUM_ITE);\n PE_inst_to_Cmtx.write(M);\n PE_inst_to_Cmtx.write(P_N);\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0) ? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\nl_rp:\n for (int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min = 1 max = 16\n // float local_B[8/2][8][WINDOW_SIZE];\n // float local_B[8][WINDOW_SIZE];\n float local_B[4 / 2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable = local_B latency = 2\n#pragma HLS array_partition variable = local_B complete dim = 1\n#pragma HLS array_partition variable = local_B complete dim = 2\n#pragma HLS array_partition variable = local_B cyclic factor = \\\n B_PARTITION_FACTOR dim = 3\n //#pragma HLS array_partition variable=local_B cyclic\n //factor=B_PARTITION_FACTOR dim=2\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n fifo_inst_out_to_Cmtx.write(start_32);\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min = 1 max = 49\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) &&\n (j < ((K + 7) >> 3) - i * (WINDOW_SIZE >> 3));) {\n#pragma HLS loop_tripcount min = 1 max = 512\n#pragma HLS pipeline style = stp II = 1\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n fifo_B_in[k].try_read(b_512_x[k]);\n fifo_B_out[k].try_write(b_512_x[k]);\n }\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m / 2][k + m % 2 * 8];\n }\n }\n }\n ++j;\n }\n }\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n fifo_inst_out_to_Cmtx.write(end_32);\n computation:\n for (int j = start_32; j < end_32;) {\n#pragma HLS loop_tripcount min = 1 max = 200\n#pragma HLS pipeline style = stp II = 1\n // ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n if (a_pes_ready) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n ap_uint<14> a_col = a(63, 50);\n ap_uint<18> a_row = a(49, 32);\n ap_uint<32> a_val = a(31, 0);\n MultBVec rabv;\n rabv.row = a_row;\n if (a_row[17] == 0) {\n // PE process\n PEcore_Bmtx(a_col, a_val, local_B[p / 2], rabv.abvec);\n }\n fifo_aBvec[p].write(rabv);\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n }\n}\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "PEG_Cmtx": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) {\n#pragma HLS disaggregate variable = PE_inst_in\n#pragma HLS interface ap_fifo port = PE_inst_in._\n#pragma HLS aggregate variable = PE_inst_in._ bit\n#pragma HLS interface ap_fifo port = PE_inst_in._peek\n#pragma HLS aggregate variable = PE_inst_in._peek bit\nvoid(PE_inst_in._.empty());\nvoid(PE_inst_in._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_inst_in\n#pragma HLS interface ap_fifo port = fifo_inst_in._\n#pragma HLS aggregate variable = fifo_inst_in._ bit\n#pragma HLS interface ap_fifo port = fifo_inst_in._peek\n#pragma HLS aggregate variable = fifo_inst_in._peek bit\nvoid(fifo_inst_in._.empty());\nvoid(fifo_inst_in._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_aBvec\n#pragma HLS array_partition variable = fifo_aBvec complete\n#pragma HLS interface ap_fifo port = fifo_aBvec[0]._\n#pragma HLS aggregate variable = fifo_aBvec[0]._ bit\n#pragma HLS interface ap_fifo port = fifo_aBvec[0]._peek\n#pragma HLS aggregate variable = fifo_aBvec[0]._peek bit\nvoid(fifo_aBvec[0]._.empty());\nvoid(fifo_aBvec[0]._peek.empty());\n#pragma HLS interface ap_fifo port = fifo_aBvec[1]._\n#pragma HLS aggregate variable = fifo_aBvec[1]._ bit\n#pragma HLS interface ap_fifo port = fifo_aBvec[1]._peek\n#pragma HLS aggregate variable = fifo_aBvec[1]._peek bit\nvoid(fifo_aBvec[1]._.empty());\nvoid(fifo_aBvec[1]._peek.empty());\n#pragma HLS interface ap_fifo port = fifo_aBvec[2]._\n#pragma HLS aggregate variable = fifo_aBvec[2]._ bit\n#pragma HLS interface ap_fifo port = fifo_aBvec[2]._peek\n#pragma HLS aggregate variable = fifo_aBvec[2]._peek bit\nvoid(fifo_aBvec[2]._.empty());\nvoid(fifo_aBvec[2]._peek.empty());\n#pragma HLS interface ap_fifo port = fifo_aBvec[3]._\n#pragma HLS aggregate variable = fifo_aBvec[3]._ bit\n#pragma HLS interface ap_fifo port = fifo_aBvec[3]._peek\n#pragma HLS aggregate variable = fifo_aBvec[3]._peek bit\nvoid(fifo_aBvec[3]._.empty());\nvoid(fifo_aBvec[3]._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_C_out\n#pragma HLS interface ap_fifo port = fifo_C_out._\n#pragma HLS aggregate variable = fifo_C_out._ bit\nvoid(fifo_C_out._.full());\n\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0) ? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n const int num_v_init = (M + 63) >> 6;\n // const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n // define local C buffer and pragma to URAM\n // ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable = local_C type = RAM_2P impl = \\\n URAM latency = 1\n#pragma HLS array_partition complete variable = local_C dim = 1\n#pragma HLS array_partition complete variable = local_C dim = 2\nl_rp:\n for (int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min = 1 max = 16\n // init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min = 1 max = 800\n#pragma HLS pipeline style = stp II = 1\n // for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n auto start_32 = fifo_inst_in.read();\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min = 1 max = 49\n // computation\n const auto end_32 = fifo_inst_in.read();\n computation:\n for (int j = start_32; j < end_32;) {\n#pragma HLS loop_tripcount min = 1 max = 200\n#pragma HLS pipeline style = stp II = 1\n#pragma HLS dependence true variable = local_C distance = DEP_DIST_LOAD_STORE\n bool nop_flag = false;\n for (int p = 0; p < 4; ++p) {\n nop_flag |= fifo_aBvec[p].empty();\n }\n if (!nop_flag) {\n for (int p = 0; p < 4; ++p) {\n MultBVec rabv;\n fifo_aBvec[p].try_read(rabv);\n ap_uint<18> a_row = rabv.row;\n if (a_row[17] == 0) {\n PEcore_Cmtx(a_row, rabv.abvec, local_C[p]);\n }\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n // cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min = 1 max = 1800\n#pragma HLS pipeline style = stp II = 1\n ap_uint<32> u_32_d[8];\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i >> 2];\n u_32_d[2 * d] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n switch (c_idx) { // 0,2,1,3\n case 0:\n c_idx = 2;\n break;\n case 1:\n c_idx = 3;\n break;\n case 2:\n c_idx = 1;\n break;\n case 3:\n c_idx = 0;\n break;\n }\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n // for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\n // endl;\n }\n }\n}\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "Scatter_1_2": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) {\n#pragma HLS disaggregate variable = fifo_in\n#pragma HLS interface ap_fifo port = fifo_in._\n#pragma HLS aggregate variable = fifo_in._ bit\n#pragma HLS interface ap_fifo port = fifo_in._peek\n#pragma HLS aggregate variable = fifo_in._peek bit\nvoid(fifo_in._.empty());\nvoid(fifo_in._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_out\n#pragma HLS array_partition variable = fifo_out complete\n#pragma HLS interface ap_fifo port = fifo_out[0]._\n#pragma HLS aggregate variable = fifo_out[0]._ bit\nvoid(fifo_out[0]._.full());\n#pragma HLS interface ap_fifo port = fifo_out[1]._\n#pragma HLS aggregate variable = fifo_out[1]._ bit\nvoid(fifo_out[1]._.full());\n\n for (;;) {\n#pragma HLS pipeline style = stp II = 1\n bool flag_nop = fifo_in.empty();\n for (int i = 0; i < 2; ++i) {\n flag_nop |= fifo_out[i].full();\n }\n if (!flag_nop) {\n ap_uint<512> tmp;\n fifo_in.try_read(tmp);\n for (int i = 0; i < 2; ++i) {\n fifo_out[i].try_write(tmp(255 + i * 256, i * 256));\n }\n }\n }\n}\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "Sextans": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nextern \"C\" {\n\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) {\n\n#pragma HLS interface s_axilite port = edge_list_ptr bundle = control\n{ auto val = reinterpret_cast(edge_list_ptr); }\n{ auto val = reinterpret_cast(edge_list_ptr); }\n\n#pragma HLS interface s_axilite port = edge_list_ch_0 bundle = control\n#pragma HLS interface s_axilite port = edge_list_ch_1 bundle = control\n#pragma HLS interface s_axilite port = edge_list_ch_2 bundle = control\n#pragma HLS interface s_axilite port = edge_list_ch_3 bundle = control\n#pragma HLS interface s_axilite port = edge_list_ch_4 bundle = control\n#pragma HLS interface s_axilite port = edge_list_ch_5 bundle = control\n#pragma HLS interface s_axilite port = edge_list_ch_6 bundle = control\n#pragma HLS interface s_axilite port = edge_list_ch_7 bundle = control\n{ auto val = reinterpret_cast(edge_list_ch_0); }\n{ auto val = reinterpret_cast(edge_list_ch_1); }\n{ auto val = reinterpret_cast(edge_list_ch_2); }\n{ auto val = reinterpret_cast(edge_list_ch_3); }\n{ auto val = reinterpret_cast(edge_list_ch_4); }\n{ auto val = reinterpret_cast(edge_list_ch_5); }\n{ auto val = reinterpret_cast(edge_list_ch_6); }\n{ auto val = reinterpret_cast(edge_list_ch_7); }\n\n#pragma HLS interface s_axilite port = mat_B_ch_0 bundle = control\n#pragma HLS interface s_axilite port = mat_B_ch_1 bundle = control\n#pragma HLS interface s_axilite port = mat_B_ch_2 bundle = control\n#pragma HLS interface s_axilite port = mat_B_ch_3 bundle = control\n{ auto val = reinterpret_cast(mat_B_ch_0); }\n{ auto val = reinterpret_cast(mat_B_ch_1); }\n{ auto val = reinterpret_cast(mat_B_ch_2); }\n{ auto val = reinterpret_cast(mat_B_ch_3); }\n\n#pragma HLS interface s_axilite port = mat_C_ch_in_0 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_in_1 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_in_2 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_in_3 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_in_4 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_in_5 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_in_6 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_in_7 bundle = control\n{ auto val = reinterpret_cast(mat_C_ch_in_0); }\n{ auto val = reinterpret_cast(mat_C_ch_in_1); }\n{ auto val = reinterpret_cast(mat_C_ch_in_2); }\n{ auto val = reinterpret_cast(mat_C_ch_in_3); }\n{ auto val = reinterpret_cast(mat_C_ch_in_4); }\n{ auto val = reinterpret_cast(mat_C_ch_in_5); }\n{ auto val = reinterpret_cast(mat_C_ch_in_6); }\n{ auto val = reinterpret_cast(mat_C_ch_in_7); }\n\n#pragma HLS interface s_axilite port = mat_C_ch_0 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_1 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_2 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_3 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_4 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_5 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_6 bundle = control\n#pragma HLS interface s_axilite port = mat_C_ch_7 bundle = control\n{ auto val = reinterpret_cast(mat_C_ch_0); }\n{ auto val = reinterpret_cast(mat_C_ch_1); }\n{ auto val = reinterpret_cast(mat_C_ch_2); }\n{ auto val = reinterpret_cast(mat_C_ch_3); }\n{ auto val = reinterpret_cast(mat_C_ch_4); }\n{ auto val = reinterpret_cast(mat_C_ch_5); }\n{ auto val = reinterpret_cast(mat_C_ch_6); }\n{ auto val = reinterpret_cast(mat_C_ch_7); }\n\n#pragma HLS interface s_axilite port = NUM_ITE bundle = control\n{ auto val = reinterpret_cast(NUM_ITE); }\n\n#pragma HLS interface s_axilite port = NUM_A_LEN bundle = control\n{ auto val = reinterpret_cast(NUM_A_LEN); }\n\n#pragma HLS interface s_axilite port = M bundle = control\n{ auto val = reinterpret_cast(M); }\n\n#pragma HLS interface s_axilite port = K bundle = control\n{ auto val = reinterpret_cast(K); }\n\n#pragma HLS interface s_axilite port = P_N bundle = control\n{ auto val = reinterpret_cast(P_N); }\n\n#pragma HLS interface s_axilite port = alpha_u bundle = control\n{ auto val = reinterpret_cast(alpha_u); }\n\n#pragma HLS interface s_axilite port = beta_u bundle = control\n{ auto val = reinterpret_cast(beta_u); }\n\n\n#pragma HLS interface s_axilite port = return bundle = control\n}\n\n\n} // extern \"C\"\n\n", - "fifos": { - "PE_inst_Sextans[0]": { - "consumed_by": [ - "PEG_Bmtx", - 0 - ], - "depth": 2, - "produced_by": [ - "read_edge_list_ptr", - 0 - ] - }, - "PE_inst_Sextans[10]": { - "consumed_by": [ - "PEG_Bmtx", - 10 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 9 - ] - }, - "PE_inst_Sextans[11]": { - "consumed_by": [ - "PEG_Bmtx", - 11 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 10 - ] - }, - "PE_inst_Sextans[12]": { - "consumed_by": [ - "PEG_Bmtx", - 12 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 11 - ] - }, - "PE_inst_Sextans[13]": { - "consumed_by": [ - "PEG_Bmtx", - 13 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 12 - ] - }, - "PE_inst_Sextans[14]": { - "consumed_by": [ - "PEG_Bmtx", - 14 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 13 - ] - }, - "PE_inst_Sextans[15]": { - "consumed_by": [ - "PEG_Bmtx", - 15 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 14 - ] - }, - "PE_inst_Sextans[16]": { - "consumed_by": [ - "black_hole_int", - 0 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 15 - ] - }, - "PE_inst_Sextans[1]": { - "consumed_by": [ - "PEG_Bmtx", - 1 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 0 - ] - }, - "PE_inst_Sextans[2]": { - "consumed_by": [ - "PEG_Bmtx", - 2 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 1 - ] - }, - "PE_inst_Sextans[3]": { - "consumed_by": [ - "PEG_Bmtx", - 3 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 2 - ] - }, - "PE_inst_Sextans[4]": { - "consumed_by": [ - "PEG_Bmtx", - 4 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 3 - ] - }, - "PE_inst_Sextans[5]": { - "consumed_by": [ - "PEG_Bmtx", - 5 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 4 - ] - }, - "PE_inst_Sextans[6]": { - "consumed_by": [ - "PEG_Bmtx", - 6 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 5 - ] - }, - "PE_inst_Sextans[7]": { - "consumed_by": [ - "PEG_Bmtx", - 7 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 6 - ] - }, - "PE_inst_Sextans[8]": { - "consumed_by": [ - "PEG_Bmtx", - 8 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 7 - ] - }, - "PE_inst_Sextans[9]": { - "consumed_by": [ - "PEG_Bmtx", - 9 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 8 - ] - }, - "PE_inst_to_Cmtx_Sextans[0]": { - "consumed_by": [ - "PEG_Cmtx", - 0 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 0 - ] - }, - "PE_inst_to_Cmtx_Sextans[10]": { - "consumed_by": [ - "PEG_Cmtx", - 10 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 10 - ] - }, - "PE_inst_to_Cmtx_Sextans[11]": { - "consumed_by": [ - "PEG_Cmtx", - 11 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 11 - ] - }, - "PE_inst_to_Cmtx_Sextans[12]": { - "consumed_by": [ - "PEG_Cmtx", - 12 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 12 - ] - }, - "PE_inst_to_Cmtx_Sextans[13]": { - "consumed_by": [ - "PEG_Cmtx", - 13 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 13 - ] - }, - "PE_inst_to_Cmtx_Sextans[14]": { - "consumed_by": [ - "PEG_Cmtx", - 14 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 14 - ] - }, - "PE_inst_to_Cmtx_Sextans[15]": { - "consumed_by": [ - "PEG_Cmtx", - 15 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 15 - ] - }, - "PE_inst_to_Cmtx_Sextans[1]": { - "consumed_by": [ - "PEG_Cmtx", - 1 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 1 - ] - }, - "PE_inst_to_Cmtx_Sextans[2]": { - "consumed_by": [ - "PEG_Cmtx", - 2 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 2 - ] - }, - "PE_inst_to_Cmtx_Sextans[3]": { - "consumed_by": [ - "PEG_Cmtx", - 3 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 3 - ] - }, - "PE_inst_to_Cmtx_Sextans[4]": { - "consumed_by": [ - "PEG_Cmtx", - 4 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 4 - ] - }, - "PE_inst_to_Cmtx_Sextans[5]": { - "consumed_by": [ - "PEG_Cmtx", - 5 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 5 - ] - }, - "PE_inst_to_Cmtx_Sextans[6]": { - "consumed_by": [ - "PEG_Cmtx", - 6 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 6 - ] - }, - "PE_inst_to_Cmtx_Sextans[7]": { - "consumed_by": [ - "PEG_Cmtx", - 7 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 7 - ] - }, - "PE_inst_to_Cmtx_Sextans[8]": { - "consumed_by": [ - "PEG_Cmtx", - 8 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 8 - ] - }, - "PE_inst_to_Cmtx_Sextans[9]": { - "consumed_by": [ - "PEG_Cmtx", - 9 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 9 - ] - }, - "fifo_A_Sextans[0]": { - "consumed_by": [ - "Scatter_1_2", - 0 - ], - "depth": 2, - "produced_by": [ - "read_A", - 0 - ] - }, - "fifo_A_Sextans[1]": { - "consumed_by": [ - "Scatter_1_2", - 1 - ], - "depth": 2, - "produced_by": [ - "read_A", - 1 - ] - }, - "fifo_A_Sextans[2]": { - "consumed_by": [ - "Scatter_1_2", - 2 - ], - "depth": 2, - "produced_by": [ - "read_A", - 2 - ] - }, - "fifo_A_Sextans[3]": { - "consumed_by": [ - "Scatter_1_2", - 3 - ], - "depth": 2, - "produced_by": [ - "read_A", - 3 - ] - }, - "fifo_A_Sextans[4]": { - "consumed_by": [ - "Scatter_1_2", - 4 - ], - "depth": 2, - "produced_by": [ - "read_A", - 4 - ] - }, - "fifo_A_Sextans[5]": { - "consumed_by": [ - "Scatter_1_2", - 5 - ], - "depth": 2, - "produced_by": [ - "read_A", - 5 - ] - }, - "fifo_A_Sextans[6]": { - "consumed_by": [ - "Scatter_1_2", - 6 - ], - "depth": 2, - "produced_by": [ - "read_A", - 6 - ] - }, - "fifo_A_Sextans[7]": { - "consumed_by": [ - "Scatter_1_2", - 7 - ], - "depth": 2, - "produced_by": [ - "read_A", - 7 - ] - }, - "fifo_A_pe_Sextans[0]": { - "consumed_by": [ - "PEG_Bmtx", - 0 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 0 - ] - }, - "fifo_A_pe_Sextans[10]": { - "consumed_by": [ - "PEG_Bmtx", - 10 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 5 - ] - }, - "fifo_A_pe_Sextans[11]": { - "consumed_by": [ - "PEG_Bmtx", - 11 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 5 - ] - }, - "fifo_A_pe_Sextans[12]": { - "consumed_by": [ - "PEG_Bmtx", - 12 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 6 - ] - }, - "fifo_A_pe_Sextans[13]": { - "consumed_by": [ - "PEG_Bmtx", - 13 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 6 - ] - }, - "fifo_A_pe_Sextans[14]": { - "consumed_by": [ - "PEG_Bmtx", - 14 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 7 - ] - }, - "fifo_A_pe_Sextans[15]": { - "consumed_by": [ - "PEG_Bmtx", - 15 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 7 - ] - }, - "fifo_A_pe_Sextans[1]": { - "consumed_by": [ - "PEG_Bmtx", - 1 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 0 - ] - }, - "fifo_A_pe_Sextans[2]": { - "consumed_by": [ - "PEG_Bmtx", - 2 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 1 - ] - }, - "fifo_A_pe_Sextans[3]": { - "consumed_by": [ - "PEG_Bmtx", - 3 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 1 - ] - }, - "fifo_A_pe_Sextans[4]": { - "consumed_by": [ - "PEG_Bmtx", - 4 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 2 - ] - }, - "fifo_A_pe_Sextans[5]": { - "consumed_by": [ - "PEG_Bmtx", - 5 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 2 - ] - }, - "fifo_A_pe_Sextans[6]": { - "consumed_by": [ - "PEG_Bmtx", - 6 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 3 - ] - }, - "fifo_A_pe_Sextans[7]": { - "consumed_by": [ - "PEG_Bmtx", - 7 - ], - "depth": 2, - "produced_by": [ - "Scatter_1_2", - 3 - ] - }, - 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"PEG_Cmtx", - 6 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 6 - ] - }, - "fifo_edge_list_ptr_to_Cmtx_Sextans[7]": { - "consumed_by": [ - "PEG_Cmtx", - 7 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 7 - ] - }, - "fifo_edge_list_ptr_to_Cmtx_Sextans[8]": { - "consumed_by": [ - "PEG_Cmtx", - 8 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 8 - ] - }, - "fifo_edge_list_ptr_to_Cmtx_Sextans[9]": { - "consumed_by": [ - "PEG_Cmtx", - 9 - ], - "depth": 2, - "produced_by": [ - "PEG_Bmtx", - 9 - ] - }, - "wrC_inst_Sextans[0]": { - "consumed_by": [ - "write_C", - 0 - ], - "depth": 2, - "produced_by": [ - "read_C", - 0 - ] - }, - "wrC_inst_Sextans[1]": { - "consumed_by": [ - "write_C", - 1 - ], - "depth": 2, - "produced_by": [ - "read_C", - 1 - ] - }, - "wrC_inst_Sextans[2]": { - "consumed_by": [ - "write_C", - 2 - ], - "depth": 2, - "produced_by": [ - "read_C", - 2 - ] - }, - "wrC_inst_Sextans[3]": { - "consumed_by": [ - "write_C", - 3 - ], - "depth": 2, - "produced_by": [ - "read_C", - 3 - ] - }, - "wrC_inst_Sextans[4]": { - "consumed_by": [ - "write_C", - 4 - ], - "depth": 2, - "produced_by": [ - "read_C", - 4 - ] - }, - "wrC_inst_Sextans[5]": { - "consumed_by": [ - "write_C", - 5 - ], - "depth": 2, - "produced_by": [ - "read_C", - 5 - ] - }, - "wrC_inst_Sextans[6]": { - "consumed_by": [ - "write_C", - 6 - ], - "depth": 2, - "produced_by": [ - "read_C", - 6 - ] - }, - "wrC_inst_Sextans[7]": { - "consumed_by": [ - "write_C", - 7 - ], - "depth": 2, - "produced_by": [ - "read_C", - 7 - ] - } - }, - "frt_interface": "#include \n#include \n#include \n\n\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) {\n#define TAPAB_APP \"TAPAB_Sextans\"\n#define TAPAB \"TAPAB\"\n const char* _tapa_bitstream = nullptr;\n if ((_tapa_bitstream = getenv(TAPAB_APP)) ||\n (_tapa_bitstream = getenv(TAPAB))) {\n fpga::Instance _tapa_instance(_tapa_bitstream);\n int _tapa_arg_index = 0;\n for (const auto& _tapa_arg_info : _tapa_instance.GetArgsInfo()) {\n if (false) {\n } else if (_tapa_arg_info.name == \"edge_list_ptr\") {\n auto _tapa_arg = fpga::ReadWrite(edge_list_ptr.get(), edge_list_ptr.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"edge_list_ch_0\") {\n auto _tapa_arg = fpga::ReadWrite(edge_list_ch[0].get(), edge_list_ch[0].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"edge_list_ch_1\") {\n auto _tapa_arg = fpga::ReadWrite(edge_list_ch[1].get(), edge_list_ch[1].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"edge_list_ch_2\") {\n auto _tapa_arg = fpga::ReadWrite(edge_list_ch[2].get(), edge_list_ch[2].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"edge_list_ch_3\") {\n auto _tapa_arg = fpga::ReadWrite(edge_list_ch[3].get(), edge_list_ch[3].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"edge_list_ch_4\") {\n auto _tapa_arg = fpga::ReadWrite(edge_list_ch[4].get(), edge_list_ch[4].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"edge_list_ch_5\") {\n auto _tapa_arg = fpga::ReadWrite(edge_list_ch[5].get(), edge_list_ch[5].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"edge_list_ch_6\") {\n auto _tapa_arg = fpga::ReadWrite(edge_list_ch[6].get(), edge_list_ch[6].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"edge_list_ch_7\") {\n auto _tapa_arg = fpga::ReadWrite(edge_list_ch[7].get(), edge_list_ch[7].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_B_ch_0\") {\n auto _tapa_arg = fpga::ReadWrite(mat_B_ch[0].get(), mat_B_ch[0].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_B_ch_1\") {\n auto _tapa_arg = fpga::ReadWrite(mat_B_ch[1].get(), mat_B_ch[1].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_B_ch_2\") {\n auto _tapa_arg = fpga::ReadWrite(mat_B_ch[2].get(), mat_B_ch[2].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_B_ch_3\") {\n auto _tapa_arg = fpga::ReadWrite(mat_B_ch[3].get(), mat_B_ch[3].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_in_0\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch_in[0].get(), mat_C_ch_in[0].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_in_1\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch_in[1].get(), mat_C_ch_in[1].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_in_2\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch_in[2].get(), mat_C_ch_in[2].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_in_3\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch_in[3].get(), mat_C_ch_in[3].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_in_4\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch_in[4].get(), mat_C_ch_in[4].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_in_5\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch_in[5].get(), mat_C_ch_in[5].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_in_6\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch_in[6].get(), mat_C_ch_in[6].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_in_7\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch_in[7].get(), mat_C_ch_in[7].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_0\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch[0].get(), mat_C_ch[0].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_1\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch[1].get(), mat_C_ch[1].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_2\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch[2].get(), mat_C_ch[2].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_3\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch[3].get(), mat_C_ch[3].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_4\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch[4].get(), mat_C_ch[4].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_5\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch[5].get(), mat_C_ch[5].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_6\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch[6].get(), mat_C_ch[6].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"mat_C_ch_7\") {\n auto _tapa_arg = fpga::ReadWrite(mat_C_ch[7].get(), mat_C_ch[7].size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"NUM_ITE\") {\n _tapa_instance.SetArg(_tapa_arg_index, NUM_ITE);\n } else if (_tapa_arg_info.name == \"NUM_A_LEN\") {\n _tapa_instance.SetArg(_tapa_arg_index, NUM_A_LEN);\n } else if (_tapa_arg_info.name == \"M\") {\n _tapa_instance.SetArg(_tapa_arg_index, M);\n } else if (_tapa_arg_info.name == \"K\") {\n _tapa_instance.SetArg(_tapa_arg_index, K);\n } else if (_tapa_arg_info.name == \"P_N\") {\n _tapa_instance.SetArg(_tapa_arg_index, P_N);\n } else if (_tapa_arg_info.name == \"alpha_u\") {\n _tapa_instance.SetArg(_tapa_arg_index, alpha_u);\n } else if (_tapa_arg_info.name == \"beta_u\") {\n _tapa_instance.SetArg(_tapa_arg_index, beta_u);\n } else {\n std::stringstream ss;\n ss << \"unknown argument: \" << _tapa_arg_info;\n throw std::runtime_error(ss.str());\n }\n ++_tapa_arg_index;\n }\n _tapa_instance.WriteToDevice();\n _tapa_instance.Exec();\n _tapa_instance.ReadFromDevice();\n _tapa_instance.Finish();\n } else {\n throw std::runtime_error(\"no bitstream found; please set `\" TAPAB_APP\n \"` or `\" TAPAB \"`\");\n }\n}\n", - "level": "upper", - "ports": [ - { - "cat": "mmap", - "name": "edge_list_ptr", - "type": "int*", - "width": 32 - }, - { - "cat": "mmap", - "name": "edge_list_ch[0]", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "edge_list_ch[1]", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "edge_list_ch[2]", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "edge_list_ch[3]", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "edge_list_ch[4]", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "edge_list_ch[5]", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "edge_list_ch[6]", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "edge_list_ch[7]", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_B_ch[0]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_B_ch[1]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_B_ch[2]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_B_ch[3]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch_in[0]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch_in[1]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch_in[2]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch_in[3]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch_in[4]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch_in[5]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch_in[6]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch_in[7]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch[0]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch[1]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch[2]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch[3]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch[4]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch[5]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch[6]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "mmap", - "name": "mat_C_ch[7]", - "type": "float_v16*", - "width": 512 - }, - { - "cat": "scalar", - "name": "NUM_ITE", - "type": "const int", - "width": 32 - }, - { - "cat": "scalar", - "name": "NUM_A_LEN", - "type": "const int", - "width": 32 - }, - { - "cat": "scalar", - "name": "M", - "type": "const int", - "width": 32 - }, - { - "cat": "scalar", - "name": "K", - "type": "const int", - "width": 32 - }, - { - "cat": "scalar", - "name": "P_N", - "type": "const int", - "width": 32 - }, - { - "cat": "scalar", - "name": "alpha_u", - "type": "const int", - "width": 32 - }, - { - "cat": "scalar", - "name": "beta_u", - "type": "const int", - "width": 32 - } - ], - "target": "hls", - "tasks": { - "FloatvAddFloatv": [ - { - "args": { - "fifo_in0": { - "arg": "fifo_C_ch_result_alpha_Sextans[0]", - "cat": "istream" - }, - "fifo_in1": { - "arg": "fifo_C_read_in_beta_Sextans[0]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_Sextans[0]", - "cat": "ostream" - } - }, - "step": -1 - }, - { - "args": { - "fifo_in0": { - "arg": "fifo_C_ch_result_alpha_Sextans[1]", - "cat": "istream" - }, - "fifo_in1": { - "arg": "fifo_C_read_in_beta_Sextans[1]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_Sextans[1]", - "cat": "ostream" - } - }, - "step": -1 - }, - { - "args": { - "fifo_in0": { - "arg": "fifo_C_ch_result_alpha_Sextans[2]", - "cat": "istream" - }, - "fifo_in1": { - "arg": "fifo_C_read_in_beta_Sextans[2]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_Sextans[2]", - "cat": "ostream" - } - }, - "step": -1 - }, - { - "args": { - "fifo_in0": { - "arg": "fifo_C_ch_result_alpha_Sextans[3]", - "cat": "istream" - }, - "fifo_in1": { - "arg": "fifo_C_read_in_beta_Sextans[3]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_Sextans[3]", - "cat": "ostream" - } - }, - "step": -1 - }, - { - "args": { - "fifo_in0": { - "arg": "fifo_C_ch_result_alpha_Sextans[4]", - "cat": "istream" - }, - "fifo_in1": { - "arg": "fifo_C_read_in_beta_Sextans[4]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_Sextans[4]", - "cat": "ostream" - } - }, - "step": -1 - }, - { - "args": { - "fifo_in0": { - "arg": "fifo_C_ch_result_alpha_Sextans[5]", - "cat": "istream" - }, - "fifo_in1": { - "arg": "fifo_C_read_in_beta_Sextans[5]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_Sextans[5]", - "cat": "ostream" - } - }, - "step": -1 - }, - { - "args": { - "fifo_in0": { - "arg": "fifo_C_ch_result_alpha_Sextans[6]", - "cat": "istream" - }, - "fifo_in1": { - "arg": "fifo_C_read_in_beta_Sextans[6]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_Sextans[6]", - "cat": "ostream" - } - }, - "step": -1 - }, - { - "args": { - "fifo_in0": { - "arg": "fifo_C_ch_result_alpha_Sextans[7]", - "cat": "istream" - }, - "fifo_in1": { - "arg": "fifo_C_read_in_beta_Sextans[7]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_Sextans[7]", - "cat": "ostream" - } - }, - "step": -1 - } - ], - "FloatvMultConst": [ - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "beta_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_read_in_Sextans[0]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_read_in_beta_Sextans[0]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "beta_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_read_in_Sextans[1]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_read_in_beta_Sextans[1]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "beta_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_read_in_Sextans[2]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_read_in_beta_Sextans[2]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "beta_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_read_in_Sextans[3]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_read_in_beta_Sextans[3]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "beta_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_read_in_Sextans[4]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_read_in_beta_Sextans[4]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "beta_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_read_in_Sextans[5]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_read_in_beta_Sextans[5]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "beta_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_read_in_Sextans[6]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_read_in_beta_Sextans[6]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "beta_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_read_in_Sextans[7]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_read_in_beta_Sextans[7]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "alpha_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_ch_result_Sextans[0]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_result_alpha_Sextans[0]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "alpha_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_ch_result_Sextans[1]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_result_alpha_Sextans[1]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "alpha_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_ch_result_Sextans[2]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_result_alpha_Sextans[2]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "alpha_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_ch_result_Sextans[3]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_result_alpha_Sextans[3]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "alpha_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": "fifo_C_ch_result_Sextans[4]", - "cat": "istream" - }, - "fifo_out": { - "arg": "fifo_C_ch_result_alpha_Sextans[4]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "alpha_u": { - "arg": "alpha_u", - "cat": "scalar" - }, - "fifo_in": { - "arg": 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- "B": { - "arg": "mat_B_ch[3]", - "cat": "async_mmap" - }, - "K": { - "arg": "K", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "fifo_B": { - "arg": "fifo_B_pe_Sextans[3]", - "cat": "ostream" - } - }, - "step": 0 - } - ], - "read_C": [ - { - "args": { - "C": { - "arg": "mat_C_ch_in[0]", - "cat": "async_mmap" - }, - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "fifo_C": { - "arg": "fifo_C_read_in_Sextans[0]", - "cat": "ostream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[0]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "C": { - "arg": "mat_C_ch_in[1]", - "cat": "async_mmap" - }, - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "fifo_C": { - "arg": "fifo_C_read_in_Sextans[1]", - "cat": "ostream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[1]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "C": { - "arg": "mat_C_ch_in[2]", - "cat": "async_mmap" - }, - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "fifo_C": { - "arg": "fifo_C_read_in_Sextans[2]", - "cat": "ostream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[2]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "C": { - "arg": "mat_C_ch_in[3]", - "cat": "async_mmap" - }, - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "fifo_C": { - "arg": "fifo_C_read_in_Sextans[3]", - "cat": "ostream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[3]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "C": { - "arg": "mat_C_ch_in[4]", - "cat": "async_mmap" - }, - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "fifo_C": { - "arg": "fifo_C_read_in_Sextans[4]", - "cat": "ostream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[4]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "C": { - "arg": "mat_C_ch_in[5]", - "cat": "async_mmap" - }, - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "fifo_C": { - "arg": "fifo_C_read_in_Sextans[5]", - "cat": "ostream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[5]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "C": { - "arg": "mat_C_ch_in[6]", - "cat": "async_mmap" - }, - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "fifo_C": { - "arg": "fifo_C_read_in_Sextans[6]", - "cat": "ostream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[6]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "C": { - "arg": "mat_C_ch_in[7]", - "cat": "async_mmap" - }, - "M": { - "arg": "M", - "cat": "scalar" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "fifo_C": { - "arg": "fifo_C_read_in_Sextans[7]", - "cat": "ostream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[7]", - "cat": "ostream" - } - }, - "step": 0 - } - ], - "read_edge_list_ptr": [ - { - "args": { - "K": { - "arg": "K", - "cat": "scalar" - }, - "M": { - "arg": "M", - "cat": "scalar" - }, - "PE_inst": { - "arg": "PE_inst_Sextans[0]", - "cat": "ostream" - }, - "P_N": { - "arg": "P_N", - "cat": "scalar" - }, - "edge_list_ptr": { - "arg": "edge_list_ptr", - "cat": "async_mmap" - }, - "fifo_edge_list_ptr": { - "arg": "fifo_edge_list_ptr_Sextans[0]", - "cat": "ostream" - }, - "num_ite": { - "arg": "NUM_ITE", - "cat": "scalar" - } - }, - "step": 0 - } - ], - "write_C": [ - { - "args": { - "C_out": { - "arg": "mat_C_ch[0]", - "cat": "async_mmap" - }, - "fifo_C": { - "arg": "fifo_C_ch_Sextans[0]", - "cat": "istream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[0]", - "cat": "istream" - } - }, - "step": 0 - }, - { - "args": { - "C_out": { - "arg": "mat_C_ch[1]", - "cat": "async_mmap" - }, - "fifo_C": { - "arg": "fifo_C_ch_Sextans[1]", - "cat": "istream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[1]", - "cat": "istream" - } - }, - "step": 0 - }, - { - "args": { - "C_out": { - "arg": "mat_C_ch[2]", - "cat": "async_mmap" - }, - "fifo_C": { - "arg": "fifo_C_ch_Sextans[2]", - "cat": "istream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[2]", - "cat": "istream" - } - }, - "step": 0 - }, - { - "args": { - "C_out": { - "arg": "mat_C_ch[3]", - "cat": "async_mmap" - }, - "fifo_C": { - "arg": "fifo_C_ch_Sextans[3]", - "cat": "istream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[3]", - "cat": "istream" - } - }, - "step": 0 - }, - { - "args": { - "C_out": { - "arg": "mat_C_ch[4]", - "cat": "async_mmap" - }, - "fifo_C": { - "arg": "fifo_C_ch_Sextans[4]", - "cat": "istream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[4]", - "cat": "istream" - } - }, - "step": 0 - }, - { - "args": { - "C_out": { - "arg": "mat_C_ch[5]", - "cat": "async_mmap" - }, - "fifo_C": { - "arg": "fifo_C_ch_Sextans[5]", - "cat": "istream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[5]", - "cat": "istream" - } - }, - "step": 0 - }, - { - "args": { - "C_out": { - "arg": "mat_C_ch[6]", - "cat": "async_mmap" - }, - "fifo_C": { - "arg": "fifo_C_ch_Sextans[6]", - "cat": "istream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[6]", - "cat": "istream" - } - }, - "step": 0 - }, - { - "args": { - "C_out": { - "arg": "mat_C_ch[7]", - "cat": "async_mmap" - }, - "fifo_C": { - "arg": "fifo_C_ch_Sextans[7]", - "cat": "istream" - }, - "wrC_inst": { - "arg": "wrC_inst_Sextans[7]", - "cat": "istream" - } - }, - "step": 0 - } - ] - }, - "vendor": "xilinx" - }, - "black_hole_float_v16": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) {\n#pragma HLS disaggregate variable = fifo_in\n#pragma HLS interface ap_fifo port = fifo_in._\n#pragma HLS aggregate variable = fifo_in._ bit\n#pragma HLS interface ap_fifo port = fifo_in._peek\n#pragma HLS aggregate variable = fifo_in._peek bit\nvoid(fifo_in._.empty());\nvoid(fifo_in._peek.empty());\n\n for (;;) {\n#pragma HLS pipeline style = stp II = 1\n fifo_in.read(nullptr);\n }\n}\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "black_hole_int": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) {\n#pragma HLS disaggregate variable = fifo_in\n#pragma HLS interface ap_fifo port = fifo_in._\n#pragma HLS aggregate variable = fifo_in._ bit\n#pragma HLS interface ap_fifo port = fifo_in._peek\n#pragma HLS aggregate variable = fifo_in._peek bit\nvoid(fifo_in._.empty());\nvoid(fifo_in._peek.empty());\n\n for (;;) {\n#pragma HLS pipeline style = stp II = 1\n fifo_in.read(nullptr);\n }\n}\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "read_A": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(tapa::async_mmap> &A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) {\n#pragma HLS disaggregate variable = A\n#pragma HLS interface ap_fifo port = A.read_addr._\n#pragma HLS aggregate variable = A.read_addr._ bit\n#pragma HLS interface ap_fifo port = A.read_data._\n#pragma HLS aggregate variable = A.read_data._ bit\n#pragma HLS interface ap_fifo port = A.write_addr._\n#pragma HLS aggregate variable = A.write_addr._ bit\n#pragma HLS interface ap_fifo port = A.write_data._\n#pragma HLS aggregate variable = A.write_data._ bit\n#pragma HLS interface ap_fifo port = A.write_resp._\n#pragma HLS aggregate variable = A.write_resp._ bit\n#pragma HLS disaggregate variable = A .read_data\n#pragma HLS interface ap_fifo port = A.read_data._peek\n#pragma HLS aggregate variable = A.read_data._peek bit\n#pragma HLS disaggregate variable = A .write_resp\n#pragma HLS interface ap_fifo port = A.write_resp._peek\n#pragma HLS aggregate variable = A.write_resp._peek bit\nvoid(A.read_addr._.full());\nvoid(A.read_data._.empty());\nvoid(A.read_data._peek.empty());\nvoid(A.write_addr._.full());\nvoid(A.write_data._.full());\nvoid(A.write_resp._.empty());\nvoid(A.write_resp._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_A\n#pragma HLS interface ap_fifo port = fifo_A._\n#pragma HLS aggregate variable = fifo_A._ bit\nvoid(fifo_A._.full());\n\n\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0) ? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\nl_rp:\n for (int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min = 1 max = 16\n rd_A:\n for (int i_req = 0, i_resp = 0; i_resp < A_len;) {\n#pragma HLS loop_tripcount min = 1 max = 10000\n#pragma HLS pipeline style = stp II = 1\n async_read(A, fifo_A, A_len, i_req, i_resp);\n }\n }\n}\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "read_B": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(tapa::async_mmap &B, tapa::ostream &fifo_B,\n const int K, const int P_N) {\n#pragma HLS disaggregate variable = B\n#pragma HLS interface ap_fifo port = B.read_addr._\n#pragma HLS aggregate variable = B.read_addr._ bit\n#pragma HLS interface ap_fifo port = B.read_data._\n#pragma HLS aggregate variable = B.read_data._ bit\n#pragma HLS interface ap_fifo port = B.write_addr._\n#pragma HLS aggregate variable = B.write_addr._ bit\n#pragma HLS interface ap_fifo port = B.write_data._\n#pragma HLS aggregate variable = B.write_data._ bit\n#pragma HLS interface ap_fifo port = B.write_resp._\n#pragma HLS aggregate variable = B.write_resp._ bit\n#pragma HLS disaggregate variable = B .read_data\n#pragma HLS interface ap_fifo port = B.read_data._peek\n#pragma HLS aggregate variable = B.read_data._peek bit\n#pragma HLS disaggregate variable = B .write_resp\n#pragma HLS interface ap_fifo port = B.write_resp._peek\n#pragma HLS aggregate variable = B.write_resp._peek bit\nvoid(B.read_addr._.full());\nvoid(B.read_data._.empty());\nvoid(B.read_data._peek.empty());\nvoid(B.write_addr._.full());\nvoid(B.write_data._.full());\nvoid(B.write_resp._.empty());\nvoid(B.write_resp._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_B\n#pragma HLS interface ap_fifo port = fifo_B._\n#pragma HLS aggregate variable = fifo_B._ bit\nvoid(fifo_B._.full());\n\n\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0) ? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int num_ite_B = ((K + 7) >> 3) * ((N + 7) >> 3);\nl_rp:\n for (int rp = 0; rp < rp_time; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min = 1 max = 16\n rd_B:\n for (int i_req = 0, i_resp = 0; i_resp < num_ite_B;) {\n#pragma HLS loop_tripcount min = 1 max = 500000\n#pragma HLS pipeline style = stp II = 1\n async_read(B, fifo_B, num_ite_B, i_req, i_resp);\n }\n }\n}\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "read_C": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(tapa::async_mmap &C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) {\n#pragma HLS disaggregate variable = C\n#pragma HLS interface ap_fifo port = C.read_addr._\n#pragma HLS aggregate variable = C.read_addr._ bit\n#pragma HLS interface ap_fifo port = C.read_data._\n#pragma HLS aggregate variable = C.read_data._ bit\n#pragma HLS interface ap_fifo port = C.write_addr._\n#pragma HLS aggregate variable = C.write_addr._ bit\n#pragma HLS interface ap_fifo port = C.write_data._\n#pragma HLS aggregate variable = C.write_data._ bit\n#pragma HLS interface ap_fifo port = C.write_resp._\n#pragma HLS aggregate variable = C.write_resp._ bit\n#pragma HLS disaggregate variable = C .read_data\n#pragma HLS interface ap_fifo port = C.read_data._peek\n#pragma HLS aggregate variable = C.read_data._peek bit\n#pragma HLS disaggregate variable = C .write_resp\n#pragma HLS interface ap_fifo port = C.write_resp._peek\n#pragma HLS aggregate variable = C.write_resp._peek bit\nvoid(C.read_addr._.full());\nvoid(C.read_data._.empty());\nvoid(C.read_data._peek.empty());\nvoid(C.write_addr._.full());\nvoid(C.write_data._.full());\nvoid(C.write_resp._.empty());\nvoid(C.write_resp._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_C\n#pragma HLS interface ap_fifo port = fifo_C._\n#pragma HLS aggregate variable = fifo_C._ bit\nvoid(fifo_C._.full());\n\n\n\n#pragma HLS disaggregate variable = wrC_inst\n#pragma HLS interface ap_fifo port = wrC_inst._\n#pragma HLS aggregate variable = wrC_inst._ bit\nvoid(wrC_inst._.full());\n\n wrC_inst.write(M);\n wrC_inst.write(P_N);\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0) ? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int num_ite_C = ((M + 15) >> 4) * ((N + 7) >> 3);\nl_rp:\n for (int rp = 0; rp < rp_time; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min = 1 max = 16\n rd_C:\n for (int i_req = 0, i_resp = 0; i_resp < num_ite_C;) {\n#pragma HLS loop_tripcount min = 1 max = 500000\n#pragma HLS pipeline style = stp II = 1\n async_read(C, fifo_C, num_ite_C, i_req, i_resp);\n }\n }\n}\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "read_edge_list_ptr": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, tapa::async_mmap &edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) {\n\n\n\n\n#pragma HLS disaggregate variable = edge_list_ptr\n#pragma HLS interface ap_fifo port = edge_list_ptr.read_addr._\n#pragma HLS aggregate variable = edge_list_ptr.read_addr._ bit\n#pragma HLS interface ap_fifo port = edge_list_ptr.read_data._\n#pragma HLS aggregate variable = edge_list_ptr.read_data._ bit\n#pragma HLS interface ap_fifo port = edge_list_ptr.write_addr._\n#pragma HLS aggregate variable = edge_list_ptr.write_addr._ bit\n#pragma HLS interface ap_fifo port = edge_list_ptr.write_data._\n#pragma HLS aggregate variable = edge_list_ptr.write_data._ bit\n#pragma HLS interface ap_fifo port = edge_list_ptr.write_resp._\n#pragma HLS aggregate variable = edge_list_ptr.write_resp._ bit\n#pragma HLS disaggregate variable = edge_list_ptr .read_data\n#pragma HLS interface ap_fifo port = edge_list_ptr.read_data._peek\n#pragma HLS aggregate variable = edge_list_ptr.read_data._peek bit\n#pragma HLS disaggregate variable = edge_list_ptr .write_resp\n#pragma HLS interface ap_fifo port = edge_list_ptr.write_resp._peek\n#pragma HLS aggregate variable = edge_list_ptr.write_resp._peek bit\nvoid(edge_list_ptr.read_addr._.full());\nvoid(edge_list_ptr.read_data._.empty());\nvoid(edge_list_ptr.read_data._peek.empty());\nvoid(edge_list_ptr.write_addr._.full());\nvoid(edge_list_ptr.write_data._.full());\nvoid(edge_list_ptr.write_resp._.empty());\nvoid(edge_list_ptr.write_resp._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_edge_list_ptr\n#pragma HLS interface ap_fifo port = fifo_edge_list_ptr._\n#pragma HLS aggregate variable = fifo_edge_list_ptr._ bit\nvoid(fifo_edge_list_ptr._.full());\n\n#pragma HLS disaggregate variable = PE_inst\n#pragma HLS interface ap_fifo port = PE_inst._\n#pragma HLS aggregate variable = PE_inst._ bit\nvoid(PE_inst._.full());\n\n PE_inst.write(num_ite);\n PE_inst.write(M);\n PE_inst.write(P_N);\n PE_inst.write(K);\n const int N = P_N & 0xFFFF;\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0) ? 1 : N16;\n const int num_ite_plus1 = num_ite + 1;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\nl_rp:\n for (int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min = 1 max = 16\n rd_ptr:\n for (int i_req = 0, i_resp = 0; i_resp < num_ite_plus1;) {\n#pragma HLS loop_tripcount min = 1 max = 800\n#pragma HLS pipeline style = stp II = 1\n async_read(edge_list_ptr, fifo_edge_list_ptr, num_ite_plus1, i_req,\n i_resp);\n }\n }\n}\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n uint64_t C_out) ;\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "write_C": { - "code": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \nconstexpr int NUM_CH_SPARSE = 8;\nconstexpr int NUM_CH_B = 4;\nconstexpr int NUM_CH_C = 8;\nconst int WINDOW_SIZE = 4096;\nconst int DEP_DIST_LOAD_STORE = 10;\nconst int B_PARTITION_FACTOR = 4;\nconst int URAM_DEPTH = 8192;\nusing float_v16 = tapa::vec_t;\nusing float_v8 = tapa::vec_t;\nvoid Sextans(tapa::mmap edge_list_ptr,\n tapa::mmaps, NUM_CH_SPARSE> edge_list_ch,\n tapa::mmaps mat_B_ch,\n tapa::mmaps mat_C_ch_in,\n tapa::mmaps mat_C_ch, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, int beta_u);\n//#include \"modules.h\"\nconstexpr int FIFO_DEPTH = 2;\nconstexpr int PEG_PER_A = 512 / 256;\nstruct MultBVec {\n ap_uint<18> row;\n float_v8 abvec;\n};\ntemplate \ninline void async_read(tapa::async_mmap &A, tapa::ostream &fifo_A,\n const R A_len, R &i_req, R &i_resp) {\n#pragma HLS inline\n if ((i_req < A_len) & !A.read_addr.full()) {\n A.read_addr.try_write(i_req);\n ++i_req;\n }\n if (!fifo_A.full() & !A.read_data.empty()) {\n T tmp;\n A.read_data.try_read(tmp);\n fifo_A.try_write(tmp);\n ++i_resp;\n }\n}\nvoid read_edge_list_ptr(\n const int num_ite, const int M,\n const int P_N, // bit 31 - 16: repeat time, bit 15 - 0: N\n const int K, uint64_t edge_list_ptr,\n tapa::ostream &fifo_edge_list_ptr, tapa::ostream &PE_inst) ;\nvoid read_A(uint64_t A,\n tapa::ostream> &fifo_A, const int A_len,\n const int P_N) ;\nvoid read_B(uint64_t B, tapa::ostream &fifo_B,\n const int K, const int P_N) ;\nvoid read_C(uint64_t C, tapa::ostream &fifo_C,\n const int M, const int P_N, tapa::ostream &wrC_inst) ;\nvoid write_C(tapa::istream &wrC_inst, tapa::istream &fifo_C,\n tapa::async_mmap &C_out) {\n#pragma HLS disaggregate variable = wrC_inst\n#pragma HLS interface ap_fifo port = wrC_inst._\n#pragma HLS aggregate variable = wrC_inst._ bit\n#pragma HLS interface ap_fifo port = wrC_inst._peek\n#pragma HLS aggregate variable = wrC_inst._peek bit\nvoid(wrC_inst._.empty());\nvoid(wrC_inst._peek.empty());\n\n#pragma HLS disaggregate variable = fifo_C\n#pragma HLS interface ap_fifo port = fifo_C._\n#pragma HLS aggregate variable = fifo_C._ bit\n#pragma HLS interface ap_fifo port = fifo_C._peek\n#pragma HLS aggregate variable = fifo_C._peek bit\nvoid(fifo_C._.empty());\nvoid(fifo_C._peek.empty());\n\n#pragma HLS disaggregate variable = C_out\n#pragma HLS interface ap_fifo port = C_out.read_addr._\n#pragma HLS aggregate variable = C_out.read_addr._ bit\n#pragma HLS interface ap_fifo port = C_out.read_data._\n#pragma HLS aggregate variable = C_out.read_data._ bit\n#pragma HLS interface ap_fifo port = C_out.write_addr._\n#pragma HLS aggregate variable = C_out.write_addr._ bit\n#pragma HLS interface ap_fifo port = C_out.write_data._\n#pragma HLS aggregate variable = C_out.write_data._ bit\n#pragma HLS interface ap_fifo port = C_out.write_resp._\n#pragma HLS aggregate variable = C_out.write_resp._ bit\n#pragma HLS disaggregate variable = C_out .read_data\n#pragma HLS interface ap_fifo port = C_out.read_data._peek\n#pragma HLS aggregate variable = C_out.read_data._peek bit\n#pragma HLS disaggregate variable = C_out .write_resp\n#pragma HLS interface ap_fifo port = C_out.write_resp._peek\n#pragma HLS aggregate variable = C_out.write_resp._peek bit\nvoid(C_out.read_addr._.full());\nvoid(C_out.read_data._.empty());\nvoid(C_out.read_data._peek.empty());\nvoid(C_out.write_addr._.full());\nvoid(C_out.write_data._.full());\nvoid(C_out.write_resp._.empty());\nvoid(C_out.write_resp._peek.empty());\n\n int M = wrC_inst.read();\n int P_N = wrC_inst.read();\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0) ? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int num_ite_C = ((M + 15) >> 4) * ((N + 7) >> 3);\nl_rp:\n for (int rp = 0; rp < rp_time; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min = 1 max = 16\n wr_C:\n for (int i_req = 0, i_resp = 0; i_resp < num_ite_C;) {\n#pragma HLS loop_tripcount min = 1 max = 500000\n#pragma HLS pipeline style = stp II = 1\n if ((i_req < num_ite_C) & !fifo_C.empty() & !C_out.write_addr.full() &\n !C_out.write_data.full()) {\n C_out.write_addr.try_write(i_req);\n float_v16 tmpv;\n fifo_C.try_read(tmpv);\n C_out.write_data.try_write(tmpv);\n ++i_req;\n }\n uint8_t n_resp;\n if (C_out.write_resp.try_read(n_resp)) {\n i_resp += int(n_resp) + 1;\n }\n }\n }\n}\nvoid FloatvMultConst(const int alpha_u, const int M, const int P_N,\n tapa::istream &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid FloatvAddFloatv(tapa::istream &fifo_in0,\n tapa::istream &fifo_in1,\n tapa::ostream &fifo_out) ;\n/*\nvoid PU2core(ap_uint<18> & addr_c,\n float a_val_f,\n float b_val_d0_f,\n float b_val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]\n ) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u);\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u);\n\n c_val_d0_f += tapa::reg(a_val_f) * b_val_d0_f;\n c_val_d1_f += tapa::reg(a_val_f) * b_val_d1_f;\n\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\n\nvoid PEcore(ap_uint<14> & addr_b,\n ap_uint<18> & addr_c,\n ap_uint<32> & a_val_u,\n ap_uint<64> local_C[4][URAM_DEPTH],\n float local_B[8][WINDOW_SIZE]\n ) {\n#pragma HLS inline\n //if (addr_c != ((ap_uint<18>) 0x3FFFF)) {\n if (addr_c[17] == 0) {\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 4; ++i) {\n PU2core(addr_c,\n a_val_f,\n local_B[i*2+0][addr_b],\n local_B[i*2+1][addr_b],\n local_C[i]\n );\n }\n }\n}\n*/\nvoid PEcore_Bmtx(ap_uint<14> addr_b, ap_uint<32> a_val_u,\n float local_B[8][WINDOW_SIZE], float_v8 &abv) {\n#pragma HLS inline\n float a_val_f = tapa::bit_cast(a_val_u);\n for (int i = 0; i < 8; ++i) {\n abv[i] = a_val_f * local_B[i][addr_b];\n }\n}\nvoid PEG_Bmtx(\n tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n // tapa::istream> & fifo_A,\n tapa::istream> &fifo_A,\n tapa::istreams &fifo_B_in, // [256(16)] * 2, 2: dim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream &PE_inst_out, tapa::ostream &fifo_inst_out,\n tapa::ostreams &fifo_B_out,\n // to PEG_Cmtx\n tapa::ostream &PE_inst_to_Cmtx,\n tapa::ostream &fifo_inst_out_to_Cmtx,\n tapa::ostreams &fifo_aBvec) ;\nvoid PU2core_Cmtx(ap_uint<18> addr_c, float val_d0_f, float val_d1_f,\n ap_uint<64> local_C_pe0_d0_d1[URAM_DEPTH]) {\n#pragma HLS inline\n ap_uint<64> c_val_d0_d1_u64 = local_C_pe0_d0_d1[addr_c];\n ap_uint<32> c_val_d0_u = c_val_d0_d1_u64(31, 0);\n ap_uint<32> c_val_d1_u = c_val_d0_d1_u64(63, 32);\n float c_val_d0_f = tapa::bit_cast(c_val_d0_u) + val_d0_f;\n float c_val_d1_f = tapa::bit_cast(c_val_d1_u) + val_d1_f;\n c_val_d0_u = tapa::bit_cast>(c_val_d0_f);\n c_val_d1_u = tapa::bit_cast>(c_val_d1_f);\n c_val_d0_d1_u64(31, 0) = c_val_d0_u;\n c_val_d0_d1_u64(63, 32) = c_val_d1_u;\n local_C_pe0_d0_d1[addr_c] = c_val_d0_d1_u64;\n}\nvoid PEcore_Cmtx(ap_uint<18> addr_c, float_v8 &abvec,\n ap_uint<64> local_C[4][URAM_DEPTH]) {\n#pragma HLS inline\n for (int i = 0; i < 4; ++i) {\n PU2core_Cmtx(addr_c, abvec[i * 2 + 0], abvec[i * 2 + 1], local_C[i]);\n }\n}\nvoid PEG_Cmtx(tapa::istream &PE_inst_in, tapa::istream &fifo_inst_in,\n tapa::istreams &fifo_aBvec,\n tapa::ostream &fifo_C_out) ;\n/*\nvoid PEG(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n tapa::streams fifo_aBvec(\"fifo_aBvec\");\n tapa::stream PE_inst_to_Cmtx(\"PE_inst_to_Cmtx\");\n tapa::stream\nfifo_inst_out_to_Cmtx(\"fifo_inst_out_to_Cmtx\");\n\n tapa::task()\n .invoke(PEG_Bmtx,\n PE_inst_in,\n fifo_inst_in,\n fifo_A,\n fifo_B_in,\n PE_inst_out,\n fifo_inst_out,\n fifo_B_out,\n // to PEG_Cmtx\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec)\n\n .invoke(PEG_Cmtx,\n PE_inst_to_Cmtx,\n fifo_inst_out_to_Cmtx,\n fifo_aBvec,\n fifo_C_out)\n ;\n}\n\nvoid PEG_c(tapa::istream & PE_inst_in,\n tapa::istream & fifo_inst_in,\n //tapa::istream> & fifo_A,\n tapa::istream> & fifo_A,\n tapa::istreams & fifo_B_in, // [256(16)] * 2, 2:\ndim d\n // [64(32bits * 2.0)] * 8 dim\n tapa::ostream & PE_inst_out,\n tapa::ostream & fifo_inst_out,\n tapa::ostreams & fifo_B_out,\n tapa::ostream & fifo_C_out\n ) {\n const int NUM_ITE = PE_inst_in.read();\n const int M = PE_inst_in.read();\n const int P_N = PE_inst_in.read();\n const int K = PE_inst_in.read();\n\n PE_inst_out.write(NUM_ITE);\n PE_inst_out.write(M);\n PE_inst_out.write(P_N);\n PE_inst_out.write(K);\n\n const int N16 = P_N >> 16;\n const int rp_time = (N16 == 0)? 1 : N16;\n const int N = P_N & 0xFFFF;\n const int rp_time_N = rp_time * ((N + 7) >> 3);\n\n const int num_v_init = (M + 63) >> 6;\n //const int num_v_out = (M + 31) >> 5;\n const int num_v_out = (M + 15) >> 4;\n\n //define local C buffer and pragma to URAM\n //ap_uint<64> local_C[2][8 / 2][URAM_DEPTH];\n ap_uint<64> local_C[4][8 / 2][URAM_DEPTH];\n#pragma HLS bind_storage variable=local_C type=RAM_2P impl=URAM latency=1\n#pragma HLS array_partition complete variable=local_C dim=1\n#pragma HLS array_partition complete variable=local_C dim=2\n\nl_rp:\n for(int rp = 0; rp < rp_time_N; rp++) {\n#pragma HLS loop_flatten off\n#pragma HLS loop_tripcount min=1 max=16\n\n //init local C\n init_C:\n for (int i = 0; i < num_v_init; ++i) {\n#pragma HLS loop_tripcount min=1 max=800\n#pragma HLS pipeline style=stp II=1\n //for (int j = 0; j < 2; ++j) {\n for (int j = 0; j < 4; ++j) {\n for (int k = 0; k < 8 / 2; ++k) {\n local_C[j][k][i] = 0;\n }\n }\n }\n //define local B buffer and pragma local B buffer if partition factor >\n1\n\n //float local_B[8/2][8][WINDOW_SIZE];\n //float local_B[8][WINDOW_SIZE];\n float local_B[4/2][8][WINDOW_SIZE];\n#pragma HLS bind_storage variable=local_B latency=2\n#pragma HLS array_partition variable=local_B complete dim=1\n#pragma HLS array_partition variable=local_B complete dim=2\n#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=3\n//#pragma HLS array_partition variable=local_B cyclic factor=B_PARTITION_FACTOR\ndim=2\n\n auto start_32 = fifo_inst_in.read();\n fifo_inst_out.write(start_32);\n\n main:\n for (int i = 0; i < NUM_ITE; ++i) {\n#pragma HLS loop_tripcount min=1 max=49\n\n // fill onchip B\n read_B:\n for (int j = 0; (j < (WINDOW_SIZE >> 3)) && (j < ((K + 7) >> 3) - i\n* (WINDOW_SIZE >> 3)); ) { #pragma HLS loop_tripcount min=1 max=512 #pragma HLS\npipeline style=stp II = 1\n\n bool b_2048_ready = true;\n bool b_2048_out_not_full = true;\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_2048_ready &= !fifo_B_in[k].empty();\n b_2048_out_not_full &= !fifo_B_out[k].full();\n }\n\n if (b_2048_ready & b_2048_out_not_full) {\n float_v16 b_512_x[NUM_CH_B];\n for (int k = 0; k < NUM_CH_B; ++k) {\n b_512_x[k] = fifo_B_in[k].read();\n fifo_B_out[k].write(b_512_x[k]);\n }\n\n for (int k = 0; k < 8; ++k) {\n for (int m = 0; m < 8; ++m) {\n for (int l = 0; l < 2; ++l) {\n local_B[l][m][j * 8 + k] = b_512_x[m/2][k + m %\n2 * 8];\n }\n }\n }\n ++j;\n }\n }\n\n // computation\n const auto end_32 = fifo_inst_in.read();\n fifo_inst_out.write(end_32);\n\n computation:\n for (int j = start_32; j < end_32; ) {\n#pragma HLS loop_tripcount min=1 max=200\n#pragma HLS pipeline style=stp II=1\n#pragma HLS dependence true variable=local_C distance=DEP_DIST_LOAD_STORE\n\n //ap_uint<128> a_pes;\n ap_uint<256> a_pes;\n bool a_pes_ready = fifo_A.try_read(a_pes);\n\n if (a_pes_ready) {\n //for (int p = 0; p < 2; ++p) {\n for (int p = 0; p < 4; ++p) {\n ap_uint<14> a_col;\n ap_uint<18> a_row;\n ap_uint<32> a_val;\n\n ap_uint<64> a = a_pes(63 + p * 64, p * 64);\n a_col = a(63, 50);\n a_row = a(49, 32);\n a_val = a(31, 0);\n\n // PE process\n PEcore(a_col,\n a_row,\n a_val,\n local_C[p],\n //local_B\n local_B[p/2]\n );\n }\n ++j;\n }\n }\n start_32 = end_32;\n }\n\n //cout << \"PE = \" << pe_idx << endl;\n write_C_outer:\n for (int i = 0, c_idx = 0; i < num_v_out; ++i) {\n#pragma HLS loop_tripcount min=1 max=1800\n#pragma HLS pipeline style=stp II=1\n ap_uint<32> u_32_d[8];\n\n for (int d = 0; d < 4; ++d) {\n ap_uint<64> u_64 = local_C[c_idx][d][i>>2];\n u_32_d[2 * d ] = u_64(31, 0);\n u_32_d[2 * d + 1] = u_64(63, 32);\n }\n\n switch (c_idx) { //0,2,1,3\n case 0: c_idx = 2; break;\n case 1: c_idx = 3; break;\n case 2: c_idx = 1; break;\n case 3: c_idx = 0; break;\n }\n\n float_v8 out_v;\n for (int d = 0; d < 8; ++d) {\n out_v[d] = tapa::bit_cast(u_32_d[d]);\n }\n fifo_C_out.write(out_v);\n //for (int ii = 0; ii < 8; ++ii) {cout << out_v[ii] << \" \";} cout <<\nendl;\n }\n }\n}\n*/\nvoid Scatter_1_2(tapa::istream> &fifo_in,\n tapa::ostreams, 2> &fifo_out) ;\nvoid Merger(tapa::istreams &fifo_in,\n tapa::ostream &fifo_out) ;\nvoid black_hole_int(tapa::istream &fifo_in) ;\nvoid black_hole_float_v16(tapa::istream &fifo_in) ;\nvoid Sextans(uint64_t edge_list_ptr,\n uint64_t edge_list_ch_0, uint64_t edge_list_ch_1, uint64_t edge_list_ch_2, uint64_t edge_list_ch_3, uint64_t edge_list_ch_4, uint64_t edge_list_ch_5, uint64_t edge_list_ch_6, uint64_t edge_list_ch_7,\n uint64_t mat_B_ch_0, uint64_t mat_B_ch_1, uint64_t mat_B_ch_2, uint64_t mat_B_ch_3,\n uint64_t mat_C_ch_in_0, uint64_t mat_C_ch_in_1, uint64_t mat_C_ch_in_2, uint64_t mat_C_ch_in_3, uint64_t mat_C_ch_in_4, uint64_t mat_C_ch_in_5, uint64_t mat_C_ch_in_6, uint64_t mat_C_ch_in_7,\n uint64_t mat_C_ch_0, uint64_t mat_C_ch_1, uint64_t mat_C_ch_2, uint64_t mat_C_ch_3, uint64_t mat_C_ch_4, uint64_t mat_C_ch_5, uint64_t mat_C_ch_6, uint64_t mat_C_ch_7, const int NUM_ITE,\n const int NUM_A_LEN, const int M, const int K, const int P_N,\n const int alpha_u, const int beta_u) ;\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - } - }, - "top": "Sextans" -} diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv.v deleted file mode 100644 index 886ab0ac..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv.v +++ /dev/null @@ -1,242 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="FloatvAddFloatv_FloatvAddFloatv,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.342000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=6704,HLS_SYN_LUT=3644,HLS_VERSION=2022_2}" *) - -module FloatvAddFloatv ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_in0_s_dout, - fifo_in0_s_empty_n, - fifo_in0_s_read, - fifo_in0_peek_dout, - fifo_in0_peek_empty_n, - fifo_in0_peek_read, - fifo_in1_s_dout, - fifo_in1_s_empty_n, - fifo_in1_s_read, - fifo_in1_peek_dout, - fifo_in1_peek_empty_n, - fifo_in1_peek_read, - fifo_out_din, - fifo_out_full_n, - fifo_out_write -); - -parameter ap_ST_fsm_state1 = 3'd1; -parameter ap_ST_fsm_state2 = 3'd2; -parameter ap_ST_fsm_state3 = 3'd4; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [512:0] fifo_in0_s_dout; -input fifo_in0_s_empty_n; -output fifo_in0_s_read; -input [512:0] fifo_in0_peek_dout; -input fifo_in0_peek_empty_n; -output fifo_in0_peek_read; -input [512:0] fifo_in1_s_dout; -input fifo_in1_s_empty_n; -output fifo_in1_s_read; -input [512:0] fifo_in1_peek_dout; -input fifo_in1_peek_empty_n; -output fifo_in1_peek_read; -output [512:0] fifo_out_din; -input fifo_out_full_n; -output fifo_out_write; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg fifo_in0_s_read; -reg fifo_in1_s_read; -reg fifo_out_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_start; -wire grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_done; -wire grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_idle; -wire grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_ready; -wire grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_in0_s_read; -wire grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_in1_s_read; -wire [512:0] grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_out_din; -wire grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_out_write; -reg grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_start_reg; -wire ap_CS_fsm_state2; -wire ap_CS_fsm_state3; -reg [2:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 3'd1; -#0 grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_start_reg = 1'b0; -end - -FloatvAddFloatv_FloatvAddFloatv_Pipeline_cc grp_FloatvAddFloatv_Pipeline_cc_fu_76( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_start), - .ap_done(grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_done), - .ap_idle(grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_idle), - .ap_ready(grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_ready), - .fifo_in0_s_dout(fifo_in0_s_dout), - .fifo_in0_s_empty_n(fifo_in0_s_empty_n), - .fifo_in0_s_read(grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_in0_s_read), - .fifo_in1_s_dout(fifo_in1_s_dout), - .fifo_in1_s_empty_n(fifo_in1_s_empty_n), - .fifo_in1_s_read(grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_in1_s_read), - .fifo_out_din(grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_out_din), - .fifo_out_full_n(fifo_out_full_n), - .fifo_out_write(grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_out_write) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state2)) begin - grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_start_reg <= 1'b1; - end else if ((grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_ready == 1'b1)) begin - grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_start_reg <= 1'b0; - end - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if ((grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_done == 1'b0)) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -always @ (*) begin - if (((grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_in0_s_read = grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_in0_s_read; - end else begin - fifo_in0_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_in1_s_read = grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_in1_s_read; - end else begin - fifo_in1_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_out_write = grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_out_write; - end else begin - fifo_out_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state3; - end - ap_ST_fsm_state3 : begin - if (((grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign fifo_in0_peek_read = 1'b0; - -assign fifo_in1_peek_read = 1'b0; - -assign fifo_out_din = grp_FloatvAddFloatv_Pipeline_cc_fu_76_fifo_out_din; - -assign grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_start = grp_FloatvAddFloatv_Pipeline_cc_fu_76_ap_start_reg; - -endmodule //FloatvAddFloatv diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv_FloatvAddFloatv_Pipeline_cc.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv_FloatvAddFloatv_Pipeline_cc.v deleted file mode 100644 index 4a57b40b..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv_FloatvAddFloatv_Pipeline_cc.v +++ /dev/null @@ -1,1516 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module FloatvAddFloatv_FloatvAddFloatv_Pipeline_cc ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_in0_s_dout, - fifo_in0_s_empty_n, - fifo_in0_s_read, - fifo_in1_s_dout, - fifo_in1_s_empty_n, - fifo_in1_s_read, - fifo_out_din, - fifo_out_full_n, - fifo_out_write -); - -parameter ap_ST_fsm_state1 = 2'd1; -parameter ap_ST_fsm_pp0_stage0 = 2'd2; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [512:0] fifo_in0_s_dout; -input fifo_in0_s_empty_n; -output fifo_in0_s_read; -input [512:0] fifo_in1_s_dout; -input fifo_in1_s_empty_n; -output fifo_in1_s_read; -output [512:0] fifo_out_din; -input fifo_out_full_n; -output fifo_out_write; - -reg ap_done; -reg ap_idle; -reg fifo_in0_s_read; -reg fifo_in1_s_read; -reg fifo_out_write; - -(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -reg fifo_out_blk_n; -reg ap_enable_reg_pp0_iter8; -wire ap_block_pp0_stage0; -reg [0:0] and_ln97_reg_1158; -reg [0:0] and_ln97_reg_1158_pp0_iter7_reg; -wire ap_block_state2_pp0_stage0_iter0; -wire ap_block_state3_pp0_stage0_iter1; -wire ap_block_state4_pp0_stage0_iter2; -wire ap_block_state5_pp0_stage0_iter3; -wire ap_block_state6_pp0_stage0_iter4; -wire ap_block_state7_pp0_stage0_iter5; -wire ap_block_state8_pp0_stage0_iter6; -wire ap_block_state9_pp0_stage0_iter7; -reg ap_block_state10_pp0_stage0_iter8; -reg ap_block_pp0_stage0_11001; -wire [0:0] and_ln97_fu_613_p2; -wire ap_CS_fsm_pp0_stage0; -reg [0:0] and_ln97_reg_1158_pp0_iter1_reg; -reg [0:0] and_ln97_reg_1158_pp0_iter2_reg; -reg [0:0] and_ln97_reg_1158_pp0_iter3_reg; -reg [0:0] and_ln97_reg_1158_pp0_iter4_reg; -reg [0:0] and_ln97_reg_1158_pp0_iter5_reg; -reg [0:0] and_ln97_reg_1158_pp0_iter6_reg; -wire [0:0] p_vld2_fu_619_p1; -wire [31:0] elem_val_M_elems_fu_661_p1; -wire [31:0] elem_val_M_elems_1_fu_675_p1; -wire [31:0] bitcast_ln78_fu_689_p1; -wire [31:0] bitcast_ln78_1_fu_703_p1; -wire [31:0] bitcast_ln78_2_fu_717_p1; -wire [31:0] bitcast_ln78_3_fu_731_p1; -wire [31:0] bitcast_ln78_4_fu_745_p1; -wire [31:0] bitcast_ln78_5_fu_759_p1; -wire [31:0] bitcast_ln78_6_fu_773_p1; -wire [31:0] bitcast_ln78_7_fu_787_p1; -wire [31:0] bitcast_ln78_8_fu_801_p1; -wire [31:0] bitcast_ln78_9_fu_815_p1; -wire [31:0] bitcast_ln78_10_fu_829_p1; -wire [31:0] bitcast_ln78_11_fu_833_p1; -wire [31:0] bitcast_ln78_12_fu_837_p1; -wire [31:0] bitcast_ln78_13_fu_841_p1; -wire [0:0] p_vld_fu_845_p1; -wire [31:0] elem_val_M_elems_4_fu_887_p1; -wire [31:0] elem_val_M_elems_5_fu_901_p1; -wire [31:0] bitcast_ln78_16_fu_915_p1; -wire [31:0] bitcast_ln78_17_fu_929_p1; -wire [31:0] bitcast_ln78_18_fu_943_p1; -wire [31:0] bitcast_ln78_19_fu_957_p1; -wire [31:0] bitcast_ln78_20_fu_971_p1; -wire [31:0] bitcast_ln78_21_fu_985_p1; -wire [31:0] bitcast_ln78_22_fu_999_p1; -wire [31:0] bitcast_ln78_23_fu_1013_p1; -wire [31:0] bitcast_ln78_24_fu_1027_p1; -wire [31:0] bitcast_ln78_25_fu_1041_p1; -wire [31:0] bitcast_ln78_26_fu_1055_p1; -wire [31:0] bitcast_ln78_27_fu_1059_p1; -wire [31:0] bitcast_ln78_28_fu_1063_p1; -wire [31:0] bitcast_ln78_29_fu_1067_p1; -wire [31:0] grp_fu_517_p2; -reg [31:0] add_i_reg_1330; -wire [31:0] grp_fu_523_p2; -reg [31:0] add_i_1_reg_1335; -wire [31:0] grp_fu_529_p2; -reg [31:0] add_i_2_reg_1340; -wire [31:0] grp_fu_535_p2; -reg [31:0] add_i_3_reg_1345; -wire [31:0] grp_fu_541_p2; -reg [31:0] add_i_4_reg_1350; -wire [31:0] grp_fu_547_p2; -reg [31:0] add_i_5_reg_1355; -wire [31:0] grp_fu_553_p2; -reg [31:0] add_i_6_reg_1360; -wire [31:0] grp_fu_559_p2; -reg [31:0] add_i_7_reg_1365; -wire [31:0] grp_fu_565_p2; -reg [31:0] add_i_8_reg_1370; -wire [31:0] grp_fu_571_p2; -reg [31:0] add_i_9_reg_1375; -wire [31:0] grp_fu_577_p2; -reg [31:0] add_i_s_reg_1380; -wire [31:0] grp_fu_583_p2; -reg [31:0] add_i_10_reg_1385; -wire [31:0] grp_fu_589_p2; -reg [31:0] add_i_11_reg_1390; -wire [31:0] grp_fu_595_p2; -reg [31:0] add_i_12_reg_1395; -wire [31:0] grp_fu_601_p2; -reg [31:0] add_i_13_reg_1400; -wire [31:0] grp_fu_607_p2; -reg [31:0] add_i_14_reg_1405; -reg ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_block_pp0_stage0_subdone; -reg ap_enable_reg_pp0_iter2; -reg ap_enable_reg_pp0_iter3; -reg ap_enable_reg_pp0_iter4; -reg ap_enable_reg_pp0_iter5; -reg ap_enable_reg_pp0_iter6; -reg ap_enable_reg_pp0_iter7; -wire [31:0] ap_phi_reg_pp0_iter0_elem_val_M_elems_3_reg_133; -reg [31:0] ap_phi_reg_pp0_iter1_elem_val_M_elems_3_reg_133; -wire [31:0] ap_phi_reg_pp0_iter0_elem_val_M_elems_2_reg_145; -reg [31:0] ap_phi_reg_pp0_iter1_elem_val_M_elems_2_reg_145; -wire [31:0] ap_phi_reg_pp0_iter0_empty_reg_157; -reg [31:0] ap_phi_reg_pp0_iter1_empty_reg_157; -wire [31:0] ap_phi_reg_pp0_iter0_empty_75_reg_169; -reg [31:0] ap_phi_reg_pp0_iter1_empty_75_reg_169; -wire [31:0] ap_phi_reg_pp0_iter0_empty_76_reg_181; -reg [31:0] ap_phi_reg_pp0_iter1_empty_76_reg_181; -wire [31:0] ap_phi_reg_pp0_iter0_empty_77_reg_193; -reg [31:0] ap_phi_reg_pp0_iter1_empty_77_reg_193; -wire [31:0] ap_phi_reg_pp0_iter0_empty_78_reg_205; -reg [31:0] ap_phi_reg_pp0_iter1_empty_78_reg_205; -wire [31:0] ap_phi_reg_pp0_iter0_empty_79_reg_217; -reg [31:0] ap_phi_reg_pp0_iter1_empty_79_reg_217; -wire [31:0] ap_phi_reg_pp0_iter0_empty_80_reg_229; -reg [31:0] ap_phi_reg_pp0_iter1_empty_80_reg_229; -wire [31:0] ap_phi_reg_pp0_iter0_empty_81_reg_241; -reg [31:0] ap_phi_reg_pp0_iter1_empty_81_reg_241; -wire [31:0] ap_phi_reg_pp0_iter0_empty_82_reg_253; -reg [31:0] ap_phi_reg_pp0_iter1_empty_82_reg_253; -wire [31:0] ap_phi_reg_pp0_iter0_empty_83_reg_265; -reg [31:0] ap_phi_reg_pp0_iter1_empty_83_reg_265; -wire [31:0] ap_phi_reg_pp0_iter0_empty_84_reg_277; -reg [31:0] ap_phi_reg_pp0_iter1_empty_84_reg_277; -wire [31:0] ap_phi_reg_pp0_iter0_empty_85_reg_289; -reg [31:0] ap_phi_reg_pp0_iter1_empty_85_reg_289; -wire [31:0] ap_phi_reg_pp0_iter0_empty_86_reg_301; -reg [31:0] ap_phi_reg_pp0_iter1_empty_86_reg_301; -wire [31:0] ap_phi_reg_pp0_iter0_empty_87_reg_313; -reg [31:0] ap_phi_reg_pp0_iter1_empty_87_reg_313; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_32_0_reg_325; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_32_0_reg_325; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_30_0_reg_337; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_30_0_reg_337; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_28_0_reg_349; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_28_0_reg_349; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_26_0_reg_361; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_26_0_reg_361; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_24_0_reg_373; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_24_0_reg_373; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_22_0_reg_385; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_22_0_reg_385; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_20_0_reg_397; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_20_0_reg_397; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_18_0_reg_409; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_18_0_reg_409; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_16_0_reg_421; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_16_0_reg_421; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_14_0_reg_433; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_14_0_reg_433; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_12_0_reg_445; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_12_0_reg_445; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_10_0_reg_457; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_10_0_reg_457; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_8_0_reg_469; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_8_0_reg_469; -wire [31:0] ap_phi_reg_pp0_iter0_elem_i_val_sroa_6_0_reg_481; -reg [31:0] ap_phi_reg_pp0_iter1_elem_i_val_sroa_6_0_reg_481; -wire [31:0] ap_phi_reg_pp0_iter0_elem_val_M_elems_7_reg_493; -reg [31:0] ap_phi_reg_pp0_iter1_elem_val_M_elems_7_reg_493; -wire [31:0] ap_phi_reg_pp0_iter0_elem_val_M_elems_6_reg_505; -reg [31:0] ap_phi_reg_pp0_iter1_elem_val_M_elems_6_reg_505; -wire [0:0] tmp_nbreadreq_fu_98_p3; -wire [0:0] tmp_1_nbreadreq_fu_106_p3; -wire [0:0] fifo_in0_s_read_nbread_fu_114_p2_0; -wire [0:0] fifo_in1_s_read_nbread_fu_120_p2_0; -reg ap_block_pp0_stage0_01001; -wire [31:0] trunc_ln78_fu_627_p1; -wire [31:0] tmp_3_fu_665_p4; -wire [31:0] tmp_4_fu_679_p4; -wire [31:0] tmp_5_fu_693_p4; -wire [31:0] tmp_6_fu_707_p4; -wire [31:0] tmp_7_fu_721_p4; -wire [31:0] tmp_8_fu_735_p4; -wire [31:0] tmp_9_fu_749_p4; -wire [31:0] tmp_s_fu_763_p4; -wire [31:0] tmp_2_fu_777_p4; -wire [31:0] tmp_10_fu_791_p4; -wire [31:0] tmp_11_fu_805_p4; -wire [31:0] tmp_12_fu_819_p4; -wire [31:0] tmp_13_fu_631_p4; -wire [31:0] trunc_ln_fu_641_p4; -wire [31:0] trunc_ln78_2_fu_651_p4; -wire [31:0] trunc_ln78_1_fu_853_p1; -wire [31:0] tmp_15_fu_891_p4; -wire [31:0] tmp_16_fu_905_p4; -wire [31:0] tmp_17_fu_919_p4; -wire [31:0] tmp_18_fu_933_p4; -wire [31:0] tmp_19_fu_947_p4; -wire [31:0] tmp_20_fu_961_p4; -wire [31:0] tmp_21_fu_975_p4; -wire [31:0] tmp_22_fu_989_p4; -wire [31:0] tmp_23_fu_1003_p4; -wire [31:0] tmp_24_fu_1017_p4; -wire [31:0] tmp_25_fu_1031_p4; -wire [31:0] tmp_26_fu_1045_p4; -wire [31:0] tmp_14_fu_857_p4; -wire [31:0] trunc_ln78_4_fu_867_p4; -wire [31:0] trunc_ln78_5_fu_877_p4; -wire [31:0] bitcast_ln151_15_fu_1116_p1; -wire [31:0] bitcast_ln151_14_fu_1113_p1; -wire [31:0] bitcast_ln151_13_fu_1110_p1; -wire [31:0] bitcast_ln151_12_fu_1107_p1; -wire [31:0] bitcast_ln151_11_fu_1104_p1; -wire [31:0] bitcast_ln151_10_fu_1101_p1; -wire [31:0] bitcast_ln151_9_fu_1098_p1; -wire [31:0] bitcast_ln151_8_fu_1095_p1; -wire [31:0] bitcast_ln151_7_fu_1092_p1; -wire [31:0] bitcast_ln151_6_fu_1089_p1; -wire [31:0] bitcast_ln151_5_fu_1086_p1; -wire [31:0] bitcast_ln151_4_fu_1083_p1; -wire [31:0] bitcast_ln151_3_fu_1080_p1; -wire [31:0] bitcast_ln151_2_fu_1077_p1; -wire [31:0] bitcast_ln151_1_fu_1074_p1; -wire [31:0] bitcast_ln151_fu_1071_p1; -reg grp_fu_517_ce; -reg grp_fu_523_ce; -reg grp_fu_529_ce; -reg grp_fu_535_ce; -reg grp_fu_541_ce; -reg grp_fu_547_ce; -reg grp_fu_553_ce; -reg grp_fu_559_ce; -reg grp_fu_565_ce; -reg grp_fu_571_ce; -reg grp_fu_577_ce; -reg grp_fu_583_ce; -reg grp_fu_589_ce; -reg grp_fu_595_ce; -reg grp_fu_601_ce; -reg grp_fu_607_ce; -reg [1:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -reg ap_idle_pp0; -wire ap_enable_pp0; -reg ap_condition_444; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 2'd1; -#0 ap_enable_reg_pp0_iter8 = 1'b0; -#0 ap_enable_reg_pp0_iter0 = 1'b0; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_enable_reg_pp0_iter2 = 1'b0; -#0 ap_enable_reg_pp0_iter3 = 1'b0; -#0 ap_enable_reg_pp0_iter4 = 1'b0; -#0 ap_enable_reg_pp0_iter5 = 1'b0; -#0 ap_enable_reg_pp0_iter6 = 1'b0; -#0 ap_enable_reg_pp0_iter7 = 1'b0; -end - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U1( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_elem_val_M_elems_3_reg_133), - .din1(ap_phi_reg_pp0_iter1_elem_val_M_elems_6_reg_505), - .ce(grp_fu_517_ce), - .dout(grp_fu_517_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U2( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_elem_val_M_elems_2_reg_145), - .din1(ap_phi_reg_pp0_iter1_elem_val_M_elems_7_reg_493), - .ce(grp_fu_523_ce), - .dout(grp_fu_523_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U3( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_reg_157), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_6_0_reg_481), - .ce(grp_fu_529_ce), - .dout(grp_fu_529_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U4( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_75_reg_169), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_8_0_reg_469), - .ce(grp_fu_535_ce), - .dout(grp_fu_535_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U5( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_76_reg_181), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_10_0_reg_457), - .ce(grp_fu_541_ce), - .dout(grp_fu_541_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U6( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_77_reg_193), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_12_0_reg_445), - .ce(grp_fu_547_ce), - .dout(grp_fu_547_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U7( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_78_reg_205), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_14_0_reg_433), - .ce(grp_fu_553_ce), - .dout(grp_fu_553_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U8( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_79_reg_217), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_16_0_reg_421), - .ce(grp_fu_559_ce), - .dout(grp_fu_559_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U9( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_80_reg_229), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_18_0_reg_409), - .ce(grp_fu_565_ce), - .dout(grp_fu_565_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U10( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_81_reg_241), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_20_0_reg_397), - .ce(grp_fu_571_ce), - .dout(grp_fu_571_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U11( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_82_reg_253), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_22_0_reg_385), - .ce(grp_fu_577_ce), - .dout(grp_fu_577_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U12( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_83_reg_265), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_24_0_reg_373), - .ce(grp_fu_583_ce), - .dout(grp_fu_583_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U13( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_84_reg_277), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_26_0_reg_361), - .ce(grp_fu_589_ce), - .dout(grp_fu_589_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U14( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_85_reg_289), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_28_0_reg_349), - .ce(grp_fu_595_ce), - .dout(grp_fu_595_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U15( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_86_reg_301), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_30_0_reg_337), - .ce(grp_fu_601_ce), - .dout(grp_fu_601_p2) -); - -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U16( - .clk(ap_clk), - .reset(ap_rst), - .din0(ap_phi_reg_pp0_iter1_empty_87_reg_313), - .din1(ap_phi_reg_pp0_iter1_elem_i_val_sroa_32_0_reg_325), - .ce(grp_fu_607_ce), - .dout(grp_fu_607_p2) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter0 <= 1'b0; - end else begin - if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_enable_reg_pp0_iter0 <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; - end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter2 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; - end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_enable_reg_pp0_iter2 <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter3 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; - end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_enable_reg_pp0_iter3 <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter4 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; - end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_enable_reg_pp0_iter4 <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter5 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; - end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_enable_reg_pp0_iter5 <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter6 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; - end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_enable_reg_pp0_iter6 <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter7 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; - end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_enable_reg_pp0_iter7 <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter8 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; - end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_enable_reg_pp0_iter8 <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_10_0_reg_457 <= bitcast_ln78_18_fu_943_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_10_0_reg_457 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_10_0_reg_457; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_12_0_reg_445 <= bitcast_ln78_19_fu_957_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_12_0_reg_445 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_12_0_reg_445; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_14_0_reg_433 <= bitcast_ln78_20_fu_971_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_14_0_reg_433 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_14_0_reg_433; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_16_0_reg_421 <= bitcast_ln78_21_fu_985_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_16_0_reg_421 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_16_0_reg_421; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_18_0_reg_409 <= bitcast_ln78_22_fu_999_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_18_0_reg_409 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_18_0_reg_409; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_20_0_reg_397 <= bitcast_ln78_23_fu_1013_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_20_0_reg_397 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_20_0_reg_397; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_22_0_reg_385 <= bitcast_ln78_24_fu_1027_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_22_0_reg_385 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_22_0_reg_385; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_24_0_reg_373 <= bitcast_ln78_25_fu_1041_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_24_0_reg_373 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_24_0_reg_373; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_26_0_reg_361 <= bitcast_ln78_26_fu_1055_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_26_0_reg_361 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_26_0_reg_361; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_28_0_reg_349 <= bitcast_ln78_27_fu_1059_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_28_0_reg_349 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_28_0_reg_349; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_30_0_reg_337 <= bitcast_ln78_28_fu_1063_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_30_0_reg_337 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_30_0_reg_337; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_32_0_reg_325 <= bitcast_ln78_29_fu_1067_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_32_0_reg_325 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_32_0_reg_325; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_6_0_reg_481 <= bitcast_ln78_16_fu_915_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_6_0_reg_481 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_6_0_reg_481; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_8_0_reg_469 <= bitcast_ln78_17_fu_929_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_i_val_sroa_8_0_reg_469 <= ap_phi_reg_pp0_iter0_elem_i_val_sroa_8_0_reg_469; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_val_M_elems_2_reg_145 <= elem_val_M_elems_1_fu_675_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_val_M_elems_2_reg_145 <= ap_phi_reg_pp0_iter0_elem_val_M_elems_2_reg_145; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_val_M_elems_3_reg_133 <= elem_val_M_elems_fu_661_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_val_M_elems_3_reg_133 <= ap_phi_reg_pp0_iter0_elem_val_M_elems_3_reg_133; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_val_M_elems_6_reg_505 <= elem_val_M_elems_4_fu_887_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_val_M_elems_6_reg_505 <= ap_phi_reg_pp0_iter0_elem_val_M_elems_6_reg_505; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld_fu_845_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_elem_val_M_elems_7_reg_493 <= elem_val_M_elems_5_fu_901_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_elem_val_M_elems_7_reg_493 <= ap_phi_reg_pp0_iter0_elem_val_M_elems_7_reg_493; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_75_reg_169 <= bitcast_ln78_1_fu_703_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_75_reg_169 <= ap_phi_reg_pp0_iter0_empty_75_reg_169; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_76_reg_181 <= bitcast_ln78_2_fu_717_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_76_reg_181 <= ap_phi_reg_pp0_iter0_empty_76_reg_181; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_77_reg_193 <= bitcast_ln78_3_fu_731_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_77_reg_193 <= ap_phi_reg_pp0_iter0_empty_77_reg_193; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_78_reg_205 <= bitcast_ln78_4_fu_745_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_78_reg_205 <= ap_phi_reg_pp0_iter0_empty_78_reg_205; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_79_reg_217 <= bitcast_ln78_5_fu_759_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_79_reg_217 <= ap_phi_reg_pp0_iter0_empty_79_reg_217; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_80_reg_229 <= bitcast_ln78_6_fu_773_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_80_reg_229 <= ap_phi_reg_pp0_iter0_empty_80_reg_229; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_81_reg_241 <= bitcast_ln78_7_fu_787_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_81_reg_241 <= ap_phi_reg_pp0_iter0_empty_81_reg_241; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_82_reg_253 <= bitcast_ln78_8_fu_801_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_82_reg_253 <= ap_phi_reg_pp0_iter0_empty_82_reg_253; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_83_reg_265 <= bitcast_ln78_9_fu_815_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_83_reg_265 <= ap_phi_reg_pp0_iter0_empty_83_reg_265; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_84_reg_277 <= bitcast_ln78_10_fu_829_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_84_reg_277 <= ap_phi_reg_pp0_iter0_empty_84_reg_277; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_85_reg_289 <= bitcast_ln78_11_fu_833_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_85_reg_289 <= ap_phi_reg_pp0_iter0_empty_85_reg_289; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_86_reg_301 <= bitcast_ln78_12_fu_837_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_86_reg_301 <= ap_phi_reg_pp0_iter0_empty_86_reg_301; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_87_reg_313 <= bitcast_ln78_13_fu_841_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_87_reg_313 <= ap_phi_reg_pp0_iter0_empty_87_reg_313; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_condition_444)) begin - if (((1'd1 == and_ln97_fu_613_p2) & (p_vld2_fu_619_p1 == 1'd1))) begin - ap_phi_reg_pp0_iter1_empty_reg_157 <= bitcast_ln78_fu_689_p1; - end else if ((1'b1 == 1'b1)) begin - ap_phi_reg_pp0_iter1_empty_reg_157 <= ap_phi_reg_pp0_iter0_empty_reg_157; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'd1 == and_ln97_reg_1158_pp0_iter6_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin - add_i_10_reg_1385 <= grp_fu_583_p2; - add_i_11_reg_1390 <= grp_fu_589_p2; - add_i_12_reg_1395 <= grp_fu_595_p2; - add_i_13_reg_1400 <= grp_fu_601_p2; - add_i_14_reg_1405 <= grp_fu_607_p2; - add_i_1_reg_1335 <= grp_fu_523_p2; - add_i_2_reg_1340 <= grp_fu_529_p2; - add_i_3_reg_1345 <= grp_fu_535_p2; - add_i_4_reg_1350 <= grp_fu_541_p2; - add_i_5_reg_1355 <= grp_fu_547_p2; - add_i_6_reg_1360 <= grp_fu_553_p2; - add_i_7_reg_1365 <= grp_fu_559_p2; - add_i_8_reg_1370 <= grp_fu_565_p2; - add_i_9_reg_1375 <= grp_fu_571_p2; - add_i_reg_1330 <= grp_fu_517_p2; - add_i_s_reg_1380 <= grp_fu_577_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - and_ln97_reg_1158 <= and_ln97_fu_613_p2; - and_ln97_reg_1158_pp0_iter1_reg <= and_ln97_reg_1158; - end -end - -always @ (posedge ap_clk) begin - if ((1'b0 == ap_block_pp0_stage0_11001)) begin - and_ln97_reg_1158_pp0_iter2_reg <= and_ln97_reg_1158_pp0_iter1_reg; - and_ln97_reg_1158_pp0_iter3_reg <= and_ln97_reg_1158_pp0_iter2_reg; - and_ln97_reg_1158_pp0_iter4_reg <= and_ln97_reg_1158_pp0_iter3_reg; - and_ln97_reg_1158_pp0_iter5_reg <= and_ln97_reg_1158_pp0_iter4_reg; - and_ln97_reg_1158_pp0_iter6_reg <= and_ln97_reg_1158_pp0_iter5_reg; - and_ln97_reg_1158_pp0_iter7_reg <= and_ln97_reg_1158_pp0_iter6_reg; - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln97_fu_613_p2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (fifo_in0_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_in0_s_read = 1'b1; - end else begin - fifo_in0_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln97_fu_613_p2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (fifo_in1_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_in1_s_read = 1'b1; - end else begin - fifo_in1_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln97_reg_1158_pp0_iter7_reg) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter8 == 1'b1))) begin - fifo_out_blk_n = fifo_out_full_n; - end else begin - fifo_out_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'd1 == and_ln97_reg_1158_pp0_iter7_reg) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter8 == 1'b1))) begin - fifo_out_write = 1'b1; - end else begin - fifo_out_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_517_ce = 1'b1; - end else begin - grp_fu_517_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_523_ce = 1'b1; - end else begin - grp_fu_523_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_529_ce = 1'b1; - end else begin - grp_fu_529_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_535_ce = 1'b1; - end else begin - grp_fu_535_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_541_ce = 1'b1; - end else begin - grp_fu_541_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_547_ce = 1'b1; - end else begin - grp_fu_547_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_553_ce = 1'b1; - end else begin - grp_fu_553_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_559_ce = 1'b1; - end else begin - grp_fu_559_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_565_ce = 1'b1; - end else begin - grp_fu_565_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_571_ce = 1'b1; - end else begin - grp_fu_571_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_577_ce = 1'b1; - end else begin - grp_fu_577_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_583_ce = 1'b1; - end else begin - grp_fu_583_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_589_ce = 1'b1; - end else begin - grp_fu_589_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_595_ce = 1'b1; - end else begin - grp_fu_595_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_601_ce = 1'b1; - end else begin - grp_fu_601_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_607_ce = 1'b1; - end else begin - grp_fu_607_ce = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign and_ln97_fu_613_p2 = (tmp_nbreadreq_fu_98_p3 & tmp_1_nbreadreq_fu_106_p3); - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage0_01001 = ((1'd1 == and_ln97_reg_1158_pp0_iter7_reg) & (ap_enable_reg_pp0_iter8 == 1'b1) & (fifo_out_full_n == 1'b0)); -end - -always @ (*) begin - ap_block_pp0_stage0_11001 = ((1'd1 == and_ln97_reg_1158_pp0_iter7_reg) & (ap_enable_reg_pp0_iter8 == 1'b1) & (fifo_out_full_n == 1'b0)); -end - -always @ (*) begin - ap_block_pp0_stage0_subdone = ((1'd1 == and_ln97_reg_1158_pp0_iter7_reg) & (ap_enable_reg_pp0_iter8 == 1'b1) & (fifo_out_full_n == 1'b0)); -end - -always @ (*) begin - ap_block_state10_pp0_stage0_iter8 = ((1'd1 == and_ln97_reg_1158_pp0_iter7_reg) & (fifo_out_full_n == 1'b0)); -end - -assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_condition_444 = ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_10_0_reg_457 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_12_0_reg_445 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_14_0_reg_433 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_16_0_reg_421 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_18_0_reg_409 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_20_0_reg_397 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_22_0_reg_385 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_24_0_reg_373 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_26_0_reg_361 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_28_0_reg_349 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_30_0_reg_337 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_32_0_reg_325 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_6_0_reg_481 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_i_val_sroa_8_0_reg_469 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_val_M_elems_2_reg_145 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_val_M_elems_3_reg_133 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_val_M_elems_6_reg_505 = 'bx; - -assign ap_phi_reg_pp0_iter0_elem_val_M_elems_7_reg_493 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_75_reg_169 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_76_reg_181 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_77_reg_193 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_78_reg_205 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_79_reg_217 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_80_reg_229 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_81_reg_241 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_82_reg_253 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_83_reg_265 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_84_reg_277 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_85_reg_289 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_86_reg_301 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_87_reg_313 = 'bx; - -assign ap_phi_reg_pp0_iter0_empty_reg_157 = 'bx; - -assign ap_ready = 1'b0; - -assign bitcast_ln151_10_fu_1101_p1 = add_i_s_reg_1380; - -assign bitcast_ln151_11_fu_1104_p1 = add_i_10_reg_1385; - -assign bitcast_ln151_12_fu_1107_p1 = add_i_11_reg_1390; - -assign bitcast_ln151_13_fu_1110_p1 = add_i_12_reg_1395; - -assign bitcast_ln151_14_fu_1113_p1 = add_i_13_reg_1400; - -assign bitcast_ln151_15_fu_1116_p1 = add_i_14_reg_1405; - -assign bitcast_ln151_1_fu_1074_p1 = add_i_1_reg_1335; - -assign bitcast_ln151_2_fu_1077_p1 = add_i_2_reg_1340; - -assign bitcast_ln151_3_fu_1080_p1 = add_i_3_reg_1345; - -assign bitcast_ln151_4_fu_1083_p1 = add_i_4_reg_1350; - -assign bitcast_ln151_5_fu_1086_p1 = add_i_5_reg_1355; - -assign bitcast_ln151_6_fu_1089_p1 = add_i_6_reg_1360; - -assign bitcast_ln151_7_fu_1092_p1 = add_i_7_reg_1365; - -assign bitcast_ln151_8_fu_1095_p1 = add_i_8_reg_1370; - -assign bitcast_ln151_9_fu_1098_p1 = add_i_9_reg_1375; - -assign bitcast_ln151_fu_1071_p1 = add_i_reg_1330; - -assign bitcast_ln78_10_fu_829_p1 = tmp_12_fu_819_p4; - -assign bitcast_ln78_11_fu_833_p1 = tmp_13_fu_631_p4; - -assign bitcast_ln78_12_fu_837_p1 = trunc_ln_fu_641_p4; - -assign bitcast_ln78_13_fu_841_p1 = trunc_ln78_2_fu_651_p4; - -assign bitcast_ln78_16_fu_915_p1 = tmp_16_fu_905_p4; - -assign bitcast_ln78_17_fu_929_p1 = tmp_17_fu_919_p4; - -assign bitcast_ln78_18_fu_943_p1 = tmp_18_fu_933_p4; - -assign bitcast_ln78_19_fu_957_p1 = tmp_19_fu_947_p4; - -assign bitcast_ln78_1_fu_703_p1 = tmp_5_fu_693_p4; - -assign bitcast_ln78_20_fu_971_p1 = tmp_20_fu_961_p4; - -assign bitcast_ln78_21_fu_985_p1 = tmp_21_fu_975_p4; - -assign bitcast_ln78_22_fu_999_p1 = tmp_22_fu_989_p4; - -assign bitcast_ln78_23_fu_1013_p1 = tmp_23_fu_1003_p4; - -assign bitcast_ln78_24_fu_1027_p1 = tmp_24_fu_1017_p4; - -assign bitcast_ln78_25_fu_1041_p1 = tmp_25_fu_1031_p4; - -assign bitcast_ln78_26_fu_1055_p1 = tmp_26_fu_1045_p4; - -assign bitcast_ln78_27_fu_1059_p1 = tmp_14_fu_857_p4; - -assign bitcast_ln78_28_fu_1063_p1 = trunc_ln78_4_fu_867_p4; - -assign bitcast_ln78_29_fu_1067_p1 = trunc_ln78_5_fu_877_p4; - -assign bitcast_ln78_2_fu_717_p1 = tmp_6_fu_707_p4; - -assign bitcast_ln78_3_fu_731_p1 = tmp_7_fu_721_p4; - -assign bitcast_ln78_4_fu_745_p1 = tmp_8_fu_735_p4; - -assign bitcast_ln78_5_fu_759_p1 = tmp_9_fu_749_p4; - -assign bitcast_ln78_6_fu_773_p1 = tmp_s_fu_763_p4; - -assign bitcast_ln78_7_fu_787_p1 = tmp_2_fu_777_p4; - -assign bitcast_ln78_8_fu_801_p1 = tmp_10_fu_791_p4; - -assign bitcast_ln78_9_fu_815_p1 = tmp_11_fu_805_p4; - -assign bitcast_ln78_fu_689_p1 = tmp_4_fu_679_p4; - -assign elem_val_M_elems_1_fu_675_p1 = tmp_3_fu_665_p4; - -assign elem_val_M_elems_4_fu_887_p1 = trunc_ln78_1_fu_853_p1; - -assign elem_val_M_elems_5_fu_901_p1 = tmp_15_fu_891_p4; - -assign elem_val_M_elems_fu_661_p1 = trunc_ln78_fu_627_p1; - -assign fifo_in0_s_read_nbread_fu_114_p2_0 = fifo_in0_s_empty_n; - -assign fifo_in1_s_read_nbread_fu_120_p2_0 = fifo_in1_s_empty_n; - -assign fifo_out_din = {{{{{{{{{{{{{{{{{{{{{{{{{{{{{{{{1'd0}, {bitcast_ln151_15_fu_1116_p1}}}, {bitcast_ln151_14_fu_1113_p1}}}, {bitcast_ln151_13_fu_1110_p1}}}, {bitcast_ln151_12_fu_1107_p1}}}, {bitcast_ln151_11_fu_1104_p1}}}, {bitcast_ln151_10_fu_1101_p1}}}, {bitcast_ln151_9_fu_1098_p1}}}, {bitcast_ln151_8_fu_1095_p1}}}, {bitcast_ln151_7_fu_1092_p1}}}, {bitcast_ln151_6_fu_1089_p1}}}, {bitcast_ln151_5_fu_1086_p1}}}, {bitcast_ln151_4_fu_1083_p1}}}, {bitcast_ln151_3_fu_1080_p1}}}, {bitcast_ln151_2_fu_1077_p1}}}, {bitcast_ln151_1_fu_1074_p1}}}, {bitcast_ln151_fu_1071_p1}}; - -assign p_vld2_fu_619_p1 = fifo_in0_s_read_nbread_fu_114_p2_0; - -assign p_vld_fu_845_p1 = fifo_in1_s_read_nbread_fu_120_p2_0; - -assign tmp_10_fu_791_p4 = {{fifo_in0_s_dout[351:320]}}; - -assign tmp_11_fu_805_p4 = {{fifo_in0_s_dout[383:352]}}; - -assign tmp_12_fu_819_p4 = {{fifo_in0_s_dout[415:384]}}; - -assign tmp_13_fu_631_p4 = {{fifo_in0_s_dout[447:416]}}; - -assign tmp_14_fu_857_p4 = {{fifo_in1_s_dout[447:416]}}; - -assign tmp_15_fu_891_p4 = {{fifo_in1_s_dout[63:32]}}; - -assign tmp_16_fu_905_p4 = {{fifo_in1_s_dout[95:64]}}; - -assign tmp_17_fu_919_p4 = {{fifo_in1_s_dout[127:96]}}; - -assign tmp_18_fu_933_p4 = {{fifo_in1_s_dout[159:128]}}; - -assign tmp_19_fu_947_p4 = {{fifo_in1_s_dout[191:160]}}; - -assign tmp_1_nbreadreq_fu_106_p3 = fifo_in1_s_empty_n; - -assign tmp_20_fu_961_p4 = {{fifo_in1_s_dout[223:192]}}; - -assign tmp_21_fu_975_p4 = {{fifo_in1_s_dout[255:224]}}; - -assign tmp_22_fu_989_p4 = {{fifo_in1_s_dout[287:256]}}; - -assign tmp_23_fu_1003_p4 = {{fifo_in1_s_dout[319:288]}}; - -assign tmp_24_fu_1017_p4 = {{fifo_in1_s_dout[351:320]}}; - -assign tmp_25_fu_1031_p4 = {{fifo_in1_s_dout[383:352]}}; - -assign tmp_26_fu_1045_p4 = {{fifo_in1_s_dout[415:384]}}; - -assign tmp_2_fu_777_p4 = {{fifo_in0_s_dout[319:288]}}; - -assign tmp_3_fu_665_p4 = {{fifo_in0_s_dout[63:32]}}; - -assign tmp_4_fu_679_p4 = {{fifo_in0_s_dout[95:64]}}; - -assign tmp_5_fu_693_p4 = {{fifo_in0_s_dout[127:96]}}; - -assign tmp_6_fu_707_p4 = {{fifo_in0_s_dout[159:128]}}; - -assign tmp_7_fu_721_p4 = {{fifo_in0_s_dout[191:160]}}; - -assign tmp_8_fu_735_p4 = {{fifo_in0_s_dout[223:192]}}; - -assign tmp_9_fu_749_p4 = {{fifo_in0_s_dout[255:224]}}; - -assign tmp_nbreadreq_fu_98_p3 = fifo_in0_s_empty_n; - -assign tmp_s_fu_763_p4 = {{fifo_in0_s_dout[287:256]}}; - -assign trunc_ln78_1_fu_853_p1 = fifo_in1_s_dout[31:0]; - -assign trunc_ln78_2_fu_651_p4 = {{fifo_in0_s_dout[511:480]}}; - -assign trunc_ln78_4_fu_867_p4 = {{fifo_in1_s_dout[479:448]}}; - -assign trunc_ln78_5_fu_877_p4 = {{fifo_in1_s_dout[511:480]}}; - -assign trunc_ln78_fu_627_p1 = fifo_in0_s_dout[31:0]; - -assign trunc_ln_fu_641_p4 = {{fifo_in0_s_dout[479:448]}}; - -endmodule //FloatvAddFloatv_FloatvAddFloatv_Pipeline_cc diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1.v deleted file mode 100644 index 97ee3100..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1.v +++ /dev/null @@ -1,76 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1ns/1ps - -module FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1 -#(parameter - ID = 1, - NUM_STAGE = 3, - din0_WIDTH = 32, - din1_WIDTH = 32, - dout_WIDTH = 32 -)( - input wire clk, - input wire reset, - input wire ce, - input wire [din0_WIDTH-1:0] din0, - input wire [din1_WIDTH-1:0] din1, - output wire [dout_WIDTH-1:0] dout -); -//------------------------Local signal------------------- -wire aclk; -wire aclken; -wire a_tvalid; -wire [31:0] a_tdata; -wire b_tvalid; -wire [31:0] b_tdata; -wire r_tvalid; -wire [31:0] r_tdata; -reg [din0_WIDTH-1:0] din0_buf1; -reg [din1_WIDTH-1:0] din1_buf1; -reg ce_r; -wire [dout_WIDTH-1:0] dout_i; -reg [dout_WIDTH-1:0] dout_r; -//------------------------Instantiation------------------ -FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip_u ( - .aclk ( aclk ), - .aclken ( aclken ), - .s_axis_a_tvalid ( a_tvalid ), - .s_axis_a_tdata ( a_tdata ), - .s_axis_b_tvalid ( b_tvalid ), - .s_axis_b_tdata ( b_tdata ), - .m_axis_result_tvalid ( r_tvalid ), - .m_axis_result_tdata ( r_tdata ) -); -//------------------------Body--------------------------- -assign aclk = clk; -assign aclken = ce_r; -assign a_tvalid = 1'b1; -assign a_tdata = din0_buf1; -assign b_tvalid = 1'b1; -assign b_tdata = din1_buf1; -assign dout_i = r_tdata; - -always @(posedge clk) begin - if (ce) begin - din0_buf1 <= din0; - din1_buf1 <= din1; - end -end - -always @ (posedge clk) begin - ce_r <= ce; -end - -always @ (posedge clk) begin - if (ce_r) begin - dout_r <= dout_i; - end -end - -assign dout = ce_r?dout_i:dout_r; -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip.tcl b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip.tcl deleted file mode 100644 index 0be3ee19..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip.tcl +++ /dev/null @@ -1,45 +0,0 @@ -# BEGIN Vivado Commands -set vivado_ver [version -short] -set fpo_ver 7.1 -if {[regexp -nocase {2015\.1.*} $vivado_ver match]} { - set fpo_ver 7.0 -} -create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip -# BEGIN Vivado Commands -# BEGIN Vivado Parameters -set_property -dict [list CONFIG.a_precision_type Single \ - CONFIG.a_tuser_width 1 \ - CONFIG.add_sub_value Add \ - CONFIG.b_tuser_width 1 \ - CONFIG.c_a_exponent_width 8 \ - CONFIG.c_a_fraction_width 24 \ - CONFIG.c_compare_operation Programmable \ - CONFIG.c_has_divide_by_zero false \ - CONFIG.c_has_invalid_op false \ - CONFIG.c_has_overflow false \ - CONFIG.c_has_underflow false \ - CONFIG.c_latency 5 \ - CONFIG.c_mult_usage Full_Usage \ - CONFIG.c_optimization Speed_Optimized \ - CONFIG.c_rate 1 \ - CONFIG.c_result_exponent_width 8 \ - CONFIG.c_result_fraction_width 24 \ - CONFIG.component_name FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip \ - CONFIG.flow_control NonBlocking \ - CONFIG.has_a_tlast false \ - CONFIG.has_a_tuser false \ - CONFIG.has_aclken true \ - CONFIG.has_aresetn false \ - CONFIG.has_b_tlast false \ - CONFIG.has_b_tuser false \ - CONFIG.has_operation_tlast false \ - CONFIG.has_operation_tuser false \ - CONFIG.has_result_tready false \ - CONFIG.maximum_latency false \ - CONFIG.operation_tuser_width 1 \ - CONFIG.operation_type Add_Subtract \ - CONFIG.result_precision_type Single \ - CONFIG.result_tlast_behv Null] -objects [get_ips FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip] -quiet -# END Vivado Parameters -set_property generate_synth_checkpoint false [get_files FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip.xci] -generate_target {synthesis simulation} [get_files FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip.xci] diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst.v deleted file mode 100644 index f9be348e..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst.v +++ /dev/null @@ -1,360 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="FloatvMultConst_FloatvMultConst,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.461450,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=3704,HLS_SYN_LUT=1602,HLS_VERSION=2022_2}" *) - -module FloatvMultConst ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - alpha_u, - M, - P_N, - fifo_in_s_dout, - fifo_in_s_empty_n, - fifo_in_s_read, - fifo_in_peek_dout, - fifo_in_peek_empty_n, - fifo_in_peek_read, - fifo_out_din, - fifo_out_full_n, - fifo_out_write -); - -parameter ap_ST_fsm_state1 = 8'd1; -parameter ap_ST_fsm_state2 = 8'd2; -parameter ap_ST_fsm_state3 = 8'd4; -parameter ap_ST_fsm_state4 = 8'd8; -parameter ap_ST_fsm_state5 = 8'd16; -parameter ap_ST_fsm_state6 = 8'd32; -parameter ap_ST_fsm_state7 = 8'd64; -parameter ap_ST_fsm_state8 = 8'd128; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [31:0] alpha_u; -input [31:0] M; -input [31:0] P_N; -input [512:0] fifo_in_s_dout; -input fifo_in_s_empty_n; -output fifo_in_s_read; -input [512:0] fifo_in_peek_dout; -input fifo_in_peek_empty_n; -output fifo_in_peek_read; -output [512:0] fifo_out_din; -input fifo_out_full_n; -output fifo_out_write; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg fifo_in_s_read; -reg fifo_out_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [7:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -reg [13:0] lshr_ln_reg_216; -wire signed [31:0] grp_fu_200_p2; -reg signed [31:0] mul_ln88_reg_221; -wire ap_CS_fsm_state4; -wire ap_CS_fsm_state5; -wire ap_CS_fsm_state6; -wire [31:0] grp_fu_191_p2; -reg [31:0] num_ite_reg_236; -wire [31:0] empty_86_fu_196_p1; -reg [31:0] empty_86_reg_241; -wire ap_CS_fsm_state7; -wire grp_FloatvMultConst_Pipeline_cc_fu_106_ap_start; -wire grp_FloatvMultConst_Pipeline_cc_fu_106_ap_done; -wire grp_FloatvMultConst_Pipeline_cc_fu_106_ap_idle; -wire grp_FloatvMultConst_Pipeline_cc_fu_106_ap_ready; -wire [512:0] grp_FloatvMultConst_Pipeline_cc_fu_106_fifo_out_din; -wire grp_FloatvMultConst_Pipeline_cc_fu_106_fifo_out_write; -wire grp_FloatvMultConst_Pipeline_cc_fu_106_fifo_in_s_read; -reg grp_FloatvMultConst_Pipeline_cc_fu_106_ap_start_reg; -wire ap_CS_fsm_state8; -wire [15:0] N16_fu_120_p4; -wire [0:0] icmp_ln86_fu_130_p2; -wire signed [15:0] rp_time_fu_136_p3; -wire [15:0] N_fu_116_p1; -wire [31:0] add_ln88_fu_152_p2; -wire signed [27:0] trunc_ln_fu_158_p4; -wire [16:0] zext_ln87_fu_148_p1; -wire [16:0] add_ln88_1_fu_172_p2; -wire [13:0] grp_fu_191_p1; -reg [7:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -wire ap_ST_fsm_state3_blk; -wire ap_ST_fsm_state4_blk; -wire ap_ST_fsm_state5_blk; -wire ap_ST_fsm_state6_blk; -wire ap_ST_fsm_state7_blk; -reg ap_ST_fsm_state8_blk; -wire [31:0] grp_fu_191_p10; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 8'd1; -#0 grp_FloatvMultConst_Pipeline_cc_fu_106_ap_start_reg = 1'b0; -end - -FloatvMultConst_FloatvMultConst_Pipeline_cc grp_FloatvMultConst_Pipeline_cc_fu_106( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_FloatvMultConst_Pipeline_cc_fu_106_ap_start), - .ap_done(grp_FloatvMultConst_Pipeline_cc_fu_106_ap_done), - .ap_idle(grp_FloatvMultConst_Pipeline_cc_fu_106_ap_idle), - .ap_ready(grp_FloatvMultConst_Pipeline_cc_fu_106_ap_ready), - .fifo_out_din(grp_FloatvMultConst_Pipeline_cc_fu_106_fifo_out_din), - .fifo_out_full_n(fifo_out_full_n), - .fifo_out_write(grp_FloatvMultConst_Pipeline_cc_fu_106_fifo_out_write), - .num_ite(num_ite_reg_236), - .fifo_in_s_dout(fifo_in_s_dout), - .fifo_in_s_empty_n(fifo_in_s_empty_n), - .fifo_in_s_read(grp_FloatvMultConst_Pipeline_cc_fu_106_fifo_in_s_read), - .empty(empty_86_reg_241) -); - -FloatvMultConst_mul_32s_14ns_32_2_1 #( - .ID( 1 ), - .NUM_STAGE( 2 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 14 ), - .dout_WIDTH( 32 )) -mul_32s_14ns_32_2_1_U22( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .din0(mul_ln88_reg_221), - .din1(grp_fu_191_p1), - .ce(1'b1), - .dout(grp_fu_191_p2) -); - -FloatvMultConst_mul_mul_16s_28s_32_4_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 16 ), - .din1_WIDTH( 28 ), - .dout_WIDTH( 32 )) -mul_mul_16s_28s_32_4_1_U23( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .din0(rp_time_fu_136_p3), - .din1(trunc_ln_fu_158_p4), - .ce(1'b1), - .dout(grp_fu_200_p2) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_FloatvMultConst_Pipeline_cc_fu_106_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state7)) begin - grp_FloatvMultConst_Pipeline_cc_fu_106_ap_start_reg <= 1'b1; - end else if ((grp_FloatvMultConst_Pipeline_cc_fu_106_ap_ready == 1'b1)) begin - grp_FloatvMultConst_Pipeline_cc_fu_106_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state7)) begin - empty_86_reg_241 <= empty_86_fu_196_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state1)) begin - lshr_ln_reg_216 <= {{add_ln88_1_fu_172_p2[16:3]}}; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state4)) begin - mul_ln88_reg_221 <= grp_fu_200_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - num_ite_reg_236 <= grp_fu_191_p2; - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -assign ap_ST_fsm_state3_blk = 1'b0; - -assign ap_ST_fsm_state4_blk = 1'b0; - -assign ap_ST_fsm_state5_blk = 1'b0; - -assign ap_ST_fsm_state6_blk = 1'b0; - -assign ap_ST_fsm_state7_blk = 1'b0; - -always @ (*) begin - if ((grp_FloatvMultConst_Pipeline_cc_fu_106_ap_done == 1'b0)) begin - ap_ST_fsm_state8_blk = 1'b1; - end else begin - ap_ST_fsm_state8_blk = 1'b0; - end -end - -always @ (*) begin - if (((grp_FloatvMultConst_Pipeline_cc_fu_106_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((grp_FloatvMultConst_Pipeline_cc_fu_106_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state8)) begin - fifo_in_s_read = grp_FloatvMultConst_Pipeline_cc_fu_106_fifo_in_s_read; - end else begin - fifo_in_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state8)) begin - fifo_out_write = grp_FloatvMultConst_Pipeline_cc_fu_106_fifo_out_write; - end else begin - fifo_out_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state3; - end - ap_ST_fsm_state3 : begin - ap_NS_fsm = ap_ST_fsm_state4; - end - ap_ST_fsm_state4 : begin - ap_NS_fsm = ap_ST_fsm_state5; - end - ap_ST_fsm_state5 : begin - ap_NS_fsm = ap_ST_fsm_state6; - end - ap_ST_fsm_state6 : begin - ap_NS_fsm = ap_ST_fsm_state7; - end - ap_ST_fsm_state7 : begin - ap_NS_fsm = ap_ST_fsm_state8; - end - ap_ST_fsm_state8 : begin - if (((grp_FloatvMultConst_Pipeline_cc_fu_106_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state8; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign N16_fu_120_p4 = {{P_N[31:16]}}; - -assign N_fu_116_p1 = P_N[15:0]; - -assign add_ln88_1_fu_172_p2 = (zext_ln87_fu_148_p1 + 17'd7); - -assign add_ln88_fu_152_p2 = (M + 32'd15); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; - -assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; - -assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; - -assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; - -assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign empty_86_fu_196_p1 = alpha_u; - -assign fifo_in_peek_read = 1'b0; - -assign fifo_out_din = grp_FloatvMultConst_Pipeline_cc_fu_106_fifo_out_din; - -assign grp_FloatvMultConst_Pipeline_cc_fu_106_ap_start = grp_FloatvMultConst_Pipeline_cc_fu_106_ap_start_reg; - -assign grp_fu_191_p1 = grp_fu_191_p10; - -assign grp_fu_191_p10 = lshr_ln_reg_216; - -assign icmp_ln86_fu_130_p2 = ((N16_fu_120_p4 == 16'd0) ? 1'b1 : 1'b0); - -assign rp_time_fu_136_p3 = ((icmp_ln86_fu_130_p2[0:0] == 1'b1) ? 16'd1 : N16_fu_120_p4); - -assign trunc_ln_fu_158_p4 = {{add_ln88_fu_152_p2[31:4]}}; - -assign zext_ln87_fu_148_p1 = N_fu_116_p1; - -endmodule //FloatvMultConst diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_FloatvMultConst_Pipeline_cc.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_FloatvMultConst_Pipeline_cc.v deleted file mode 100644 index bb956c4e..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_FloatvMultConst_Pipeline_cc.v +++ /dev/null @@ -1,934 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module FloatvMultConst_FloatvMultConst_Pipeline_cc ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_out_din, - fifo_out_full_n, - fifo_out_write, - num_ite, - fifo_in_s_dout, - fifo_in_s_empty_n, - fifo_in_s_read, - empty -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -output [512:0] fifo_out_din; -input fifo_out_full_n; -output fifo_out_write; -input [31:0] num_ite; -input [512:0] fifo_in_s_dout; -input fifo_in_s_empty_n; -output fifo_in_s_read; -input [31:0] empty; - -reg ap_idle; -reg fifo_out_write; -reg fifo_in_s_read; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_enable_reg_pp0_iter2; -reg ap_enable_reg_pp0_iter3; -reg ap_enable_reg_pp0_iter4; -reg ap_enable_reg_pp0_iter5; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -wire ap_block_state3_pp0_stage0_iter2; -wire ap_block_state4_pp0_stage0_iter3; -wire ap_block_state5_pp0_stage0_iter4; -reg [0:0] p_vld_reg_562; -reg [0:0] p_vld_reg_562_pp0_iter4_reg; -reg ap_block_state6_pp0_stage0_iter5; -reg ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln90_fu_201_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -reg fifo_out_blk_n; -wire ap_block_pp0_stage0; -reg ap_block_pp0_stage0_11001; -wire [0:0] p_vld_fu_207_p1; -reg [0:0] p_vld_reg_562_pp0_iter1_reg; -reg [0:0] p_vld_reg_562_pp0_iter2_reg; -reg [0:0] p_vld_reg_562_pp0_iter3_reg; -wire [31:0] trunc_ln78_fu_215_p1; -reg [31:0] trunc_ln78_reg_566; -reg [31:0] tmp_reg_571; -reg [31:0] trunc_ln1_reg_576; -reg [31:0] trunc_ln78_2_reg_581; -reg [31:0] tmp_1_reg_586; -reg [31:0] tmp_2_reg_591; -reg [31:0] tmp_3_reg_596; -reg [31:0] tmp_4_reg_601; -reg [31:0] tmp_5_reg_606; -reg [31:0] tmp_6_reg_611; -reg [31:0] tmp_7_reg_616; -reg [31:0] tmp_8_reg_621; -reg [31:0] tmp_9_reg_626; -reg [31:0] tmp_s_reg_631; -reg [31:0] tmp_10_reg_636; -reg [31:0] tmp_11_reg_641; -wire [31:0] grp_fu_129_p2; -reg [31:0] mul_i_reg_726; -wire [31:0] grp_fu_133_p2; -reg [31:0] mul_i_1_reg_731; -wire [31:0] grp_fu_137_p2; -reg [31:0] mul_i_2_reg_736; -wire [31:0] grp_fu_141_p2; -reg [31:0] mul_i_3_reg_741; -wire [31:0] grp_fu_145_p2; -reg [31:0] mul_i_4_reg_746; -wire [31:0] grp_fu_149_p2; -reg [31:0] mul_i_5_reg_751; -wire [31:0] grp_fu_153_p2; -reg [31:0] mul_i_6_reg_756; -wire [31:0] grp_fu_157_p2; -reg [31:0] mul_i_7_reg_761; -wire [31:0] grp_fu_161_p2; -reg [31:0] mul_i_8_reg_766; -wire [31:0] grp_fu_165_p2; -reg [31:0] mul_i_9_reg_771; -wire [31:0] grp_fu_169_p2; -reg [31:0] mul_i_s_reg_776; -wire [31:0] grp_fu_173_p2; -reg [31:0] mul_i_10_reg_781; -wire [31:0] grp_fu_177_p2; -reg [31:0] mul_i_11_reg_786; -wire [31:0] grp_fu_181_p2; -reg [31:0] mul_i_12_reg_791; -wire [31:0] grp_fu_185_p2; -reg [31:0] mul_i_13_reg_796; -wire [31:0] grp_fu_189_p2; -reg [31:0] mul_i_14_reg_801; -reg [31:0] i_fu_100; -wire [31:0] i_2_fu_369_p2; -wire ap_loop_init; -reg [31:0] ap_sig_allocacmp_i_1; -wire [0:0] fifo_in_s_read_nbread_fu_116_p2_0; -reg ap_block_pp0_stage0_01001; -wire [31:0] grp_fu_129_p0; -wire [31:0] grp_fu_133_p0; -wire [31:0] grp_fu_137_p0; -wire [31:0] grp_fu_141_p0; -wire [31:0] grp_fu_145_p0; -wire [31:0] grp_fu_149_p0; -wire [31:0] grp_fu_153_p0; -wire [31:0] grp_fu_157_p0; -wire [31:0] grp_fu_161_p0; -wire [31:0] grp_fu_165_p0; -wire [31:0] grp_fu_169_p0; -wire [31:0] grp_fu_173_p0; -wire [31:0] grp_fu_177_p0; -wire [31:0] grp_fu_181_p0; -wire [31:0] grp_fu_185_p0; -wire [31:0] grp_fu_189_p0; -wire [31:0] bitcast_ln151_15_fu_489_p1; -wire [31:0] bitcast_ln151_14_fu_486_p1; -wire [31:0] bitcast_ln151_13_fu_483_p1; -wire [31:0] bitcast_ln151_12_fu_480_p1; -wire [31:0] bitcast_ln151_11_fu_477_p1; -wire [31:0] bitcast_ln151_10_fu_474_p1; -wire [31:0] bitcast_ln151_9_fu_471_p1; -wire [31:0] bitcast_ln151_8_fu_468_p1; -wire [31:0] bitcast_ln151_7_fu_465_p1; -wire [31:0] bitcast_ln151_6_fu_462_p1; -wire [31:0] bitcast_ln151_5_fu_459_p1; -wire [31:0] bitcast_ln151_4_fu_456_p1; -wire [31:0] bitcast_ln151_3_fu_453_p1; -wire [31:0] bitcast_ln151_2_fu_450_p1; -wire [31:0] bitcast_ln151_1_fu_447_p1; -wire [31:0] bitcast_ln151_fu_444_p1; -reg grp_fu_129_ce; -reg grp_fu_133_ce; -reg grp_fu_137_ce; -reg grp_fu_141_ce; -reg grp_fu_145_ce; -reg grp_fu_149_ce; -reg grp_fu_153_ce; -reg grp_fu_157_ce; -reg grp_fu_161_ce; -reg grp_fu_165_ce; -reg grp_fu_169_ce; -reg grp_fu_173_ce; -reg grp_fu_177_ce; -reg grp_fu_181_ce; -reg grp_fu_185_ce; -reg grp_fu_189_ce; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg ap_loop_exit_ready_pp0_iter1_reg; -reg ap_loop_exit_ready_pp0_iter2_reg; -reg ap_loop_exit_ready_pp0_iter3_reg; -reg ap_loop_exit_ready_pp0_iter4_reg; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -reg ap_condition_622; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_enable_reg_pp0_iter2 = 1'b0; -#0 ap_enable_reg_pp0_iter3 = 1'b0; -#0 ap_enable_reg_pp0_iter4 = 1'b0; -#0 ap_enable_reg_pp0_iter5 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U1( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_129_p0), - .din1(empty), - .ce(grp_fu_129_ce), - .dout(grp_fu_129_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U2( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_133_p0), - .din1(empty), - .ce(grp_fu_133_ce), - .dout(grp_fu_133_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U3( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_137_p0), - .din1(empty), - .ce(grp_fu_137_ce), - .dout(grp_fu_137_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U4( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_141_p0), - .din1(empty), - .ce(grp_fu_141_ce), - .dout(grp_fu_141_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U5( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_145_p0), - .din1(empty), - .ce(grp_fu_145_ce), - .dout(grp_fu_145_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U6( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_149_p0), - .din1(empty), - .ce(grp_fu_149_ce), - .dout(grp_fu_149_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U7( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_153_p0), - .din1(empty), - .ce(grp_fu_153_ce), - .dout(grp_fu_153_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U8( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_157_p0), - .din1(empty), - .ce(grp_fu_157_ce), - .dout(grp_fu_157_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U9( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_161_p0), - .din1(empty), - .ce(grp_fu_161_ce), - .dout(grp_fu_161_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U10( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_165_p0), - .din1(empty), - .ce(grp_fu_165_ce), - .dout(grp_fu_165_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U11( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_169_p0), - .din1(empty), - .ce(grp_fu_169_ce), - .dout(grp_fu_169_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U12( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_173_p0), - .din1(empty), - .ce(grp_fu_173_ce), - .dout(grp_fu_173_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U13( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_177_p0), - .din1(empty), - .ce(grp_fu_177_ce), - .dout(grp_fu_177_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U14( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_181_p0), - .din1(empty), - .ce(grp_fu_181_ce), - .dout(grp_fu_181_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U15( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_185_p0), - .din1(empty), - .ce(grp_fu_185_ce), - .dout(grp_fu_185_p2) -); - -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U16( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_189_p0), - .din1(empty), - .ce(grp_fu_189_ce), - .dout(grp_fu_189_p2) -); - -FloatvMultConst_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter4_reg == 1'b1))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter2 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter3 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter4 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter5 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((1'b1 == ap_condition_622)) begin - i_fu_100 <= i_2_fu_369_p2; - end else if ((ap_loop_init == 1'b1)) begin - i_fu_100 <= 32'd0; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_loop_exit_ready_pp0_iter1_reg <= ap_loop_exit_ready; - ap_loop_exit_ready_pp0_iter2_reg <= ap_loop_exit_ready_pp0_iter1_reg; - p_vld_reg_562_pp0_iter1_reg <= p_vld_reg_562; - end -end - -always @ (posedge ap_clk) begin - if ((1'b0 == ap_block_pp0_stage0_11001)) begin - ap_loop_exit_ready_pp0_iter3_reg <= ap_loop_exit_ready_pp0_iter2_reg; - ap_loop_exit_ready_pp0_iter4_reg <= ap_loop_exit_ready_pp0_iter3_reg; - p_vld_reg_562_pp0_iter2_reg <= p_vld_reg_562_pp0_iter1_reg; - p_vld_reg_562_pp0_iter3_reg <= p_vld_reg_562_pp0_iter2_reg; - p_vld_reg_562_pp0_iter4_reg <= p_vld_reg_562_pp0_iter3_reg; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_vld_reg_562_pp0_iter3_reg == 1'd1))) begin - mul_i_10_reg_781 <= grp_fu_173_p2; - mul_i_11_reg_786 <= grp_fu_177_p2; - mul_i_12_reg_791 <= grp_fu_181_p2; - mul_i_13_reg_796 <= grp_fu_185_p2; - mul_i_14_reg_801 <= grp_fu_189_p2; - mul_i_1_reg_731 <= grp_fu_133_p2; - mul_i_2_reg_736 <= grp_fu_137_p2; - mul_i_3_reg_741 <= grp_fu_141_p2; - mul_i_4_reg_746 <= grp_fu_145_p2; - mul_i_5_reg_751 <= grp_fu_149_p2; - mul_i_6_reg_756 <= grp_fu_153_p2; - mul_i_7_reg_761 <= grp_fu_157_p2; - mul_i_8_reg_766 <= grp_fu_161_p2; - mul_i_9_reg_771 <= grp_fu_165_p2; - mul_i_reg_726 <= grp_fu_129_p2; - mul_i_s_reg_776 <= grp_fu_169_p2; - end -end - -always @ (posedge ap_clk) begin - if (((icmp_ln90_fu_201_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - p_vld_reg_562 <= fifo_in_s_read_nbread_fu_116_p2_0; - tmp_reg_571 <= {{fifo_in_s_dout[447:416]}}; - trunc_ln1_reg_576 <= {{fifo_in_s_dout[479:448]}}; - trunc_ln78_2_reg_581 <= {{fifo_in_s_dout[511:480]}}; - trunc_ln78_reg_566 <= trunc_ln78_fu_215_p1; - end -end - -always @ (posedge ap_clk) begin - if (((icmp_ln90_fu_201_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (p_vld_fu_207_p1 == 1'd1))) begin - tmp_10_reg_636 <= {{fifo_in_s_dout[383:352]}}; - tmp_11_reg_641 <= {{fifo_in_s_dout[415:384]}}; - tmp_1_reg_586 <= {{fifo_in_s_dout[63:32]}}; - tmp_2_reg_591 <= {{fifo_in_s_dout[95:64]}}; - tmp_3_reg_596 <= {{fifo_in_s_dout[127:96]}}; - tmp_4_reg_601 <= {{fifo_in_s_dout[159:128]}}; - tmp_5_reg_606 <= {{fifo_in_s_dout[191:160]}}; - tmp_6_reg_611 <= {{fifo_in_s_dout[223:192]}}; - tmp_7_reg_616 <= {{fifo_in_s_dout[255:224]}}; - tmp_8_reg_621 <= {{fifo_in_s_dout[287:256]}}; - tmp_9_reg_626 <= {{fifo_in_s_dout[319:288]}}; - tmp_s_reg_631 <= {{fifo_in_s_dout[351:320]}}; - end -end - -always @ (*) begin - if (((icmp_ln90_fu_201_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter4_reg == 1'b1))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_start_int == 1'b0) & (ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_loop_init == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_sig_allocacmp_i_1 = 32'd0; - end else begin - ap_sig_allocacmp_i_1 = i_fu_100; - end -end - -always @ (*) begin - if (((fifo_in_s_empty_n == 1'b1) & (icmp_ln90_fu_201_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_in_s_read = 1'b1; - end else begin - fifo_in_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (p_vld_reg_562_pp0_iter4_reg == 1'd1) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin - fifo_out_blk_n = fifo_out_full_n; - end else begin - fifo_out_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_vld_reg_562_pp0_iter4_reg == 1'd1) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin - fifo_out_write = 1'b1; - end else begin - fifo_out_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_129_ce = 1'b1; - end else begin - grp_fu_129_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_133_ce = 1'b1; - end else begin - grp_fu_133_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_137_ce = 1'b1; - end else begin - grp_fu_137_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_141_ce = 1'b1; - end else begin - grp_fu_141_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_145_ce = 1'b1; - end else begin - grp_fu_145_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_149_ce = 1'b1; - end else begin - grp_fu_149_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_153_ce = 1'b1; - end else begin - grp_fu_153_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_157_ce = 1'b1; - end else begin - grp_fu_157_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_161_ce = 1'b1; - end else begin - grp_fu_161_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_165_ce = 1'b1; - end else begin - grp_fu_165_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_169_ce = 1'b1; - end else begin - grp_fu_169_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_173_ce = 1'b1; - end else begin - grp_fu_173_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_177_ce = 1'b1; - end else begin - grp_fu_177_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_181_ce = 1'b1; - end else begin - grp_fu_181_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_185_ce = 1'b1; - end else begin - grp_fu_185_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_189_ce = 1'b1; - end else begin - grp_fu_189_ce = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage0_01001 = ((p_vld_reg_562_pp0_iter4_reg == 1'd1) & (fifo_out_full_n == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b1)); -end - -always @ (*) begin - ap_block_pp0_stage0_11001 = ((p_vld_reg_562_pp0_iter4_reg == 1'd1) & (fifo_out_full_n == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b1)); -end - -always @ (*) begin - ap_block_pp0_stage0_subdone = ((p_vld_reg_562_pp0_iter4_reg == 1'd1) & (fifo_out_full_n == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b1)); -end - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_state6_pp0_stage0_iter5 = ((p_vld_reg_562_pp0_iter4_reg == 1'd1) & (fifo_out_full_n == 1'b0)); -end - -always @ (*) begin - ap_condition_622 = ((icmp_ln90_fu_201_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (p_vld_fu_207_p1 == 1'd1)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -assign bitcast_ln151_10_fu_474_p1 = mul_i_s_reg_776; - -assign bitcast_ln151_11_fu_477_p1 = mul_i_10_reg_781; - -assign bitcast_ln151_12_fu_480_p1 = mul_i_11_reg_786; - -assign bitcast_ln151_13_fu_483_p1 = mul_i_12_reg_791; - -assign bitcast_ln151_14_fu_486_p1 = mul_i_13_reg_796; - -assign bitcast_ln151_15_fu_489_p1 = mul_i_14_reg_801; - -assign bitcast_ln151_1_fu_447_p1 = mul_i_1_reg_731; - -assign bitcast_ln151_2_fu_450_p1 = mul_i_2_reg_736; - -assign bitcast_ln151_3_fu_453_p1 = mul_i_3_reg_741; - -assign bitcast_ln151_4_fu_456_p1 = mul_i_4_reg_746; - -assign bitcast_ln151_5_fu_459_p1 = mul_i_5_reg_751; - -assign bitcast_ln151_6_fu_462_p1 = mul_i_6_reg_756; - -assign bitcast_ln151_7_fu_465_p1 = mul_i_7_reg_761; - -assign bitcast_ln151_8_fu_468_p1 = mul_i_8_reg_766; - -assign bitcast_ln151_9_fu_471_p1 = mul_i_9_reg_771; - -assign bitcast_ln151_fu_444_p1 = mul_i_reg_726; - -assign fifo_in_s_read_nbread_fu_116_p2_0 = fifo_in_s_empty_n; - -assign fifo_out_din = {{{{{{{{{{{{{{{{{{{{{{{{{{{{{{{{1'd0}, {bitcast_ln151_15_fu_489_p1}}}, {bitcast_ln151_14_fu_486_p1}}}, {bitcast_ln151_13_fu_483_p1}}}, {bitcast_ln151_12_fu_480_p1}}}, {bitcast_ln151_11_fu_477_p1}}}, {bitcast_ln151_10_fu_474_p1}}}, {bitcast_ln151_9_fu_471_p1}}}, {bitcast_ln151_8_fu_468_p1}}}, {bitcast_ln151_7_fu_465_p1}}}, {bitcast_ln151_6_fu_462_p1}}}, {bitcast_ln151_5_fu_459_p1}}}, {bitcast_ln151_4_fu_456_p1}}}, {bitcast_ln151_3_fu_453_p1}}}, {bitcast_ln151_2_fu_450_p1}}}, {bitcast_ln151_1_fu_447_p1}}}, {bitcast_ln151_fu_444_p1}}; - -assign grp_fu_129_p0 = trunc_ln78_reg_566; - -assign grp_fu_133_p0 = tmp_1_reg_586; - -assign grp_fu_137_p0 = tmp_2_reg_591; - -assign grp_fu_141_p0 = tmp_3_reg_596; - -assign grp_fu_145_p0 = tmp_4_reg_601; - -assign grp_fu_149_p0 = tmp_5_reg_606; - -assign grp_fu_153_p0 = tmp_6_reg_611; - -assign grp_fu_157_p0 = tmp_7_reg_616; - -assign grp_fu_161_p0 = tmp_8_reg_621; - -assign grp_fu_165_p0 = tmp_9_reg_626; - -assign grp_fu_169_p0 = tmp_s_reg_631; - -assign grp_fu_173_p0 = tmp_10_reg_636; - -assign grp_fu_177_p0 = tmp_11_reg_641; - -assign grp_fu_181_p0 = tmp_reg_571; - -assign grp_fu_185_p0 = trunc_ln1_reg_576; - -assign grp_fu_189_p0 = trunc_ln78_2_reg_581; - -assign i_2_fu_369_p2 = (ap_sig_allocacmp_i_1 + 32'd1); - -assign icmp_ln90_fu_201_p2 = (($signed(ap_sig_allocacmp_i_1) < $signed(num_ite)) ? 1'b1 : 1'b0); - -assign p_vld_fu_207_p1 = fifo_in_s_read_nbread_fu_116_p2_0; - -assign trunc_ln78_fu_215_p1 = fifo_in_s_dout[31:0]; - -endmodule //FloatvMultConst_FloatvMultConst_Pipeline_cc diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_flow_control_loop_pipe_sequential_init.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_flow_control_loop_pipe_sequential_init.v deleted file mode 100644 index 48cebe90..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_flow_control_loop_pipe_sequential_init.v +++ /dev/null @@ -1,104 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module FloatvMultConst_flow_control_loop_pipe_sequential_init( - ap_clk, - ap_rst, - ap_start, - ap_ready, - ap_done, - ap_start_int, - ap_ready_int, - ap_done_int, - ap_continue_int, - ap_loop_init, - ap_loop_exit_ready, - ap_loop_exit_done -); - -input ap_clk; -input ap_rst; - -//Block level handshake with outside loop -input ap_start; -output ap_ready; -output ap_done; - -//Block level handshake with loop body -output ap_start_int; -input ap_ready_int; -input ap_done_int; -output ap_continue_int; - -//Init live in variables -output ap_loop_init; -wire ap_loop_init; -reg ap_loop_init_int; -reg ap_done; -reg ap_done_cache; - -//Exit signal from loop body -input ap_loop_exit_ready; -input ap_loop_exit_done; - -// power-on initialization -initial begin -#0 ap_loop_init_int = 1'b1; -#0 ap_done_cache = 1'b0; -end - -assign ap_start_int = ap_start; - -assign ap_continue_int = 1'b1; - -assign ap_ready = ap_loop_exit_ready; - -//ap_loop_init is valid for the first II -//of the first loop run so as to enable -//the init block ops which are pushed into -//the first state of the pipeline region -always @ (posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_loop_exit_done == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_ready_int == 1'b1) begin - ap_loop_init_int <= 1'b0; - end -end - -assign ap_loop_init = ap_loop_init_int & ap_start; - -// if no ap_continue port and current module is not top module, -// ap_done handshakes with ap_start. Internally, flow control sends out -// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle. -// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int -// is asserted, so DUT can start the next run -always @(posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_done_cache <= 1'b0; - end else if (ap_done_int == 1'b1) begin - ap_done_cache <= 1'b1; - end else if (ap_start_int == 1'b1) begin - ap_done_cache <= 1'b0; - end -end - -// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start -always @(*) -begin - if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1.v deleted file mode 100644 index a379d041..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1.v +++ /dev/null @@ -1,76 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1ns/1ps - -module FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1 -#(parameter - ID = 1, - NUM_STAGE = 3, - din0_WIDTH = 32, - din1_WIDTH = 32, - dout_WIDTH = 32 -)( - input wire clk, - input wire reset, - input wire ce, - input wire [din0_WIDTH-1:0] din0, - input wire [din1_WIDTH-1:0] din1, - output wire [dout_WIDTH-1:0] dout -); -//------------------------Local signal------------------- -wire aclk; -wire aclken; -wire a_tvalid; -wire [31:0] a_tdata; -wire b_tvalid; -wire [31:0] b_tdata; -wire r_tvalid; -wire [31:0] r_tdata; -reg [din0_WIDTH-1:0] din0_buf1; -reg [din1_WIDTH-1:0] din1_buf1; -reg ce_r; -wire [dout_WIDTH-1:0] dout_i; -reg [dout_WIDTH-1:0] dout_r; -//------------------------Instantiation------------------ -FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip_u ( - .aclk ( aclk ), - .aclken ( aclken ), - .s_axis_a_tvalid ( a_tvalid ), - .s_axis_a_tdata ( a_tdata ), - .s_axis_b_tvalid ( b_tvalid ), - .s_axis_b_tdata ( b_tdata ), - .m_axis_result_tvalid ( r_tvalid ), - .m_axis_result_tdata ( r_tdata ) -); -//------------------------Body--------------------------- -assign aclk = clk; -assign aclken = ce_r; -assign a_tvalid = 1'b1; -assign a_tdata = din0_buf1; -assign b_tvalid = 1'b1; -assign b_tdata = din1_buf1; -assign dout_i = r_tdata; - -always @(posedge clk) begin - if (ce) begin - din0_buf1 <= din0; - din1_buf1 <= din1; - end -end - -always @ (posedge clk) begin - ce_r <= ce; -end - -always @ (posedge clk) begin - if (ce_r) begin - dout_r <= dout_i; - end -end - -assign dout = ce_r?dout_i:dout_r; -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip.tcl b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip.tcl deleted file mode 100644 index 533dd906..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip.tcl +++ /dev/null @@ -1,45 +0,0 @@ -# BEGIN Vivado Commands -set vivado_ver [version -short] -set fpo_ver 7.1 -if {[regexp -nocase {2015\.1.*} $vivado_ver match]} { - set fpo_ver 7.0 -} -create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip -# BEGIN Vivado Commands -# BEGIN Vivado Parameters -set_property -dict [list CONFIG.a_precision_type Single \ - CONFIG.a_tuser_width 1 \ - CONFIG.add_sub_value Both \ - CONFIG.b_tuser_width 1 \ - CONFIG.c_a_exponent_width 8 \ - CONFIG.c_a_fraction_width 24 \ - CONFIG.c_compare_operation Programmable \ - CONFIG.c_has_divide_by_zero false \ - CONFIG.c_has_invalid_op false \ - CONFIG.c_has_overflow false \ - CONFIG.c_has_underflow false \ - CONFIG.c_latency 2 \ - CONFIG.c_mult_usage Max_Usage \ - CONFIG.c_optimization Speed_Optimized \ - CONFIG.c_rate 1 \ - CONFIG.c_result_exponent_width 8 \ - CONFIG.c_result_fraction_width 24 \ - CONFIG.component_name FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip \ - CONFIG.flow_control NonBlocking \ - CONFIG.has_a_tlast false \ - CONFIG.has_a_tuser false \ - CONFIG.has_aclken true \ - CONFIG.has_aresetn false \ - CONFIG.has_b_tlast false \ - CONFIG.has_b_tuser false \ - CONFIG.has_operation_tlast false \ - CONFIG.has_operation_tuser false \ - CONFIG.has_result_tready false \ - CONFIG.maximum_latency false \ - CONFIG.operation_tuser_width 1 \ - CONFIG.operation_type Multiply \ - CONFIG.result_precision_type Single \ - CONFIG.result_tlast_behv Null] -objects [get_ips FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip] -quiet -# END Vivado Parameters -set_property generate_synth_checkpoint false [get_files FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip.xci] -generate_target {synthesis simulation} [get_files FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip.xci] diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_mul_32s_14ns_32_2_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_mul_32s_14ns_32_2_1.v deleted file mode 100644 index 1afab8d0..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_mul_32s_14ns_32_2_1.v +++ /dev/null @@ -1,30 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module FloatvMultConst_mul_32s_14ns_32_2_1(clk, ce, reset, din0, din1, dout); -parameter ID = 1; -parameter NUM_STAGE = 1; -parameter din0_WIDTH = 14; -parameter din1_WIDTH = 12; -parameter dout_WIDTH = 26; -input clk; -input ce; -input reset; -input signed [din0_WIDTH - 1 : 0] din0; -input [din1_WIDTH - 1 : 0] din1; -output[dout_WIDTH - 1 : 0] dout; -reg signed [dout_WIDTH - 1 : 0] dout; -wire signed [dout_WIDTH - 1 : 0] tmp_product; - -assign tmp_product = $signed(din0) * $signed({1'b0, din1}); -always @ (posedge clk) begin - if (ce) begin - dout <= tmp_product; - end -end -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_mul_mul_16s_28s_32_4_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_mul_mul_16s_28s_32_4_1.v deleted file mode 100644 index 95ae7130..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/FloatvMultConst_mul_mul_16s_28s_32_4_1.v +++ /dev/null @@ -1,62 +0,0 @@ - -`timescale 1 ns / 1 ps - - module FloatvMultConst_mul_mul_16s_28s_32_4_1_DSP48_0(clk, rst, ce, a, b, p); -input clk; -input rst; -input ce; -input signed [16 - 1 : 0] a; -input signed [28 - 1 : 0] b; -output signed [32 - 1 : 0] p; - -reg signed [32 - 1 : 0] p_reg; - -reg signed [16 - 1 : 0] a_reg; -reg signed [28 - 1 : 0] b_reg; - -reg signed [32 - 1 : 0] p_reg_tmp; - -always @ (posedge clk) begin - if (ce) begin - a_reg <= a; - b_reg <= b; - p_reg_tmp <= a_reg * b_reg; - p_reg <= p_reg_tmp; - end -end - -assign p = p_reg; - -endmodule -`timescale 1 ns / 1 ps -module FloatvMultConst_mul_mul_16s_28s_32_4_1( - clk, - reset, - ce, - din0, - din1, - dout); - -parameter ID = 32'd1; -parameter NUM_STAGE = 32'd1; -parameter din0_WIDTH = 32'd1; -parameter din1_WIDTH = 32'd1; -parameter dout_WIDTH = 32'd1; -input clk; -input reset; -input ce; -input[din0_WIDTH - 1:0] din0; -input[din1_WIDTH - 1:0] din1; -output[dout_WIDTH - 1:0] dout; - - - -FloatvMultConst_mul_mul_16s_28s_32_4_1_DSP48_0 FloatvMultConst_mul_mul_16s_28s_32_4_1_DSP48_0_U( - .clk( clk ), - .rst( reset ), - .ce( ce ), - .a( din0 ), - .b( din1 ), - .p( dout )); - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/Merger.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/Merger.v deleted file mode 100644 index c568291c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/Merger.v +++ /dev/null @@ -1,242 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="Merger_Merger,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=6,HLS_SYN_LUT=69,HLS_VERSION=2022_2}" *) - -module Merger ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_in_0_dout, - fifo_in_0_empty_n, - fifo_in_0_read, - fifo_in_1_dout, - fifo_in_1_empty_n, - fifo_in_1_read, - fifo_in_peek_0_dout, - fifo_in_peek_0_empty_n, - fifo_in_peek_0_read, - fifo_in_peek_1_dout, - fifo_in_peek_1_empty_n, - fifo_in_peek_1_read, - fifo_out_din, - fifo_out_full_n, - fifo_out_write -); - -parameter ap_ST_fsm_state1 = 3'd1; -parameter ap_ST_fsm_state2 = 3'd2; -parameter ap_ST_fsm_state3 = 3'd4; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [256:0] fifo_in_0_dout; -input fifo_in_0_empty_n; -output fifo_in_0_read; -input [256:0] fifo_in_1_dout; -input fifo_in_1_empty_n; -output fifo_in_1_read; -input [256:0] fifo_in_peek_0_dout; -input fifo_in_peek_0_empty_n; -output fifo_in_peek_0_read; -input [256:0] fifo_in_peek_1_dout; -input fifo_in_peek_1_empty_n; -output fifo_in_peek_1_read; -output [512:0] fifo_out_din; -input fifo_out_full_n; -output fifo_out_write; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg fifo_in_0_read; -reg fifo_in_1_read; -reg fifo_out_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_start; -wire grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_done; -wire grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_idle; -wire grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_ready; -wire [512:0] grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_out_din; -wire grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_out_write; -wire grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_in_0_read; -wire grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_in_1_read; -reg grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_start_reg; -wire ap_CS_fsm_state2; -wire ap_CS_fsm_state3; -reg [2:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 3'd1; -#0 grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_start_reg = 1'b0; -end - -Merger_Merger_Pipeline_VITIS_LOOP_410_1 grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_start), - .ap_done(grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_done), - .ap_idle(grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_idle), - .ap_ready(grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_ready), - .fifo_out_din(grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_out_din), - .fifo_out_full_n(fifo_out_full_n), - .fifo_out_write(grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_out_write), - .fifo_in_0_dout(fifo_in_0_dout), - .fifo_in_0_empty_n(fifo_in_0_empty_n), - .fifo_in_0_read(grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_in_0_read), - .fifo_in_1_dout(fifo_in_1_dout), - .fifo_in_1_empty_n(fifo_in_1_empty_n), - .fifo_in_1_read(grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_in_1_read) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state2)) begin - grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_start_reg <= 1'b1; - end else if ((grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_ready == 1'b1)) begin - grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_start_reg <= 1'b0; - end - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if ((grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_done == 1'b0)) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -always @ (*) begin - if (((grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_in_0_read = grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_in_0_read; - end else begin - fifo_in_0_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_in_1_read = grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_in_1_read; - end else begin - fifo_in_1_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_out_write = grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_out_write; - end else begin - fifo_out_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state3; - end - ap_ST_fsm_state3 : begin - if (((grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign fifo_in_peek_0_read = 1'b0; - -assign fifo_in_peek_1_read = 1'b0; - -assign fifo_out_din = grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_fifo_out_din; - -assign grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_start = grp_Merger_Pipeline_VITIS_LOOP_410_1_fu_76_ap_start_reg; - -endmodule //Merger diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/Merger_Merger_Pipeline_VITIS_LOOP_410_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/Merger_Merger_Pipeline_VITIS_LOOP_410_1.v deleted file mode 100644 index 1494cf80..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/Merger_Merger_Pipeline_VITIS_LOOP_410_1.v +++ /dev/null @@ -1,201 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module Merger_Merger_Pipeline_VITIS_LOOP_410_1 ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_out_din, - fifo_out_full_n, - fifo_out_write, - fifo_in_0_dout, - fifo_in_0_empty_n, - fifo_in_0_read, - fifo_in_1_dout, - fifo_in_1_empty_n, - fifo_in_1_read -); - -parameter ap_ST_fsm_state1 = 2'd1; -parameter ap_ST_fsm_state2 = 2'd2; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -output [512:0] fifo_out_din; -input fifo_out_full_n; -output fifo_out_write; -input [256:0] fifo_in_0_dout; -input fifo_in_0_empty_n; -output fifo_in_0_read; -input [256:0] fifo_in_1_dout; -input fifo_in_1_empty_n; -output fifo_in_1_read; - -reg ap_done; -reg ap_idle; -reg fifo_out_write; -reg fifo_in_0_read; -reg fifo_in_1_read; - -(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire [31:0] elem_val_M_elems_1_fu_209_p4; -wire ap_CS_fsm_state2; -wire [0:0] and_ln412_1_fu_191_p2; -wire [31:0] tmp_5_fu_220_p4; -wire [31:0] tmp_6_fu_231_p4; -wire [31:0] tmp_7_fu_242_p4; -wire [31:0] elem_val_M_elems_3_fu_265_p4; -wire [31:0] tmp_3_fu_276_p4; -wire [31:0] tmp_4_fu_287_p4; -wire [31:0] tmp_s_fu_298_p4; -wire [0:0] tmp_1_nbreadreq_fu_70_p3; -wire [0:0] tmp_2_nbreadreq_fu_78_p3; -wire [0:0] and_ln412_fu_185_p2; -wire [0:0] and_ln412_1_fu_191_p1; -wire [95:0] tmp_8_fu_309_p4; -wire [31:0] elem_val_M_elems_2_fu_261_p1; -wire [95:0] tmp_9_fu_319_p4; -wire [31:0] elem_val_M_elems_fu_205_p1; -reg [1:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 2'd1; -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln412_1_fu_191_p2) & (fifo_in_0_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - fifo_in_0_read = 1'b1; - end else begin - fifo_in_0_read = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln412_1_fu_191_p2) & (fifo_in_1_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - fifo_in_1_read = 1'b1; - end else begin - fifo_in_1_read = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln412_1_fu_191_p2) & (fifo_out_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - fifo_out_write = 1'b1; - end else begin - fifo_out_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state2; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign and_ln412_1_fu_191_p1 = fifo_out_full_n; - -assign and_ln412_1_fu_191_p2 = (and_ln412_fu_185_p2 & and_ln412_1_fu_191_p1); - -assign and_ln412_fu_185_p2 = (tmp_2_nbreadreq_fu_78_p3 & tmp_1_nbreadreq_fu_70_p3); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_ready = 1'b0; - -assign elem_val_M_elems_1_fu_209_p4 = {{fifo_in_0_dout[63:32]}}; - -assign elem_val_M_elems_2_fu_261_p1 = fifo_in_1_dout[31:0]; - -assign elem_val_M_elems_3_fu_265_p4 = {{fifo_in_1_dout[63:32]}}; - -assign elem_val_M_elems_fu_205_p1 = fifo_in_0_dout[31:0]; - -assign fifo_out_din = {{{{{{{{{{{{{{{{{{{{{{{{1'd0}, {tmp_8_fu_309_p4}}}, {tmp_s_fu_298_p4}}}, {tmp_4_fu_287_p4}}}, {tmp_3_fu_276_p4}}}, {elem_val_M_elems_3_fu_265_p4}}}, {elem_val_M_elems_2_fu_261_p1}}}, {tmp_9_fu_319_p4}}}, {tmp_7_fu_242_p4}}}, {tmp_6_fu_231_p4}}}, {tmp_5_fu_220_p4}}}, {elem_val_M_elems_1_fu_209_p4}}}, {elem_val_M_elems_fu_205_p1}}; - -assign tmp_1_nbreadreq_fu_70_p3 = fifo_in_0_empty_n; - -assign tmp_2_nbreadreq_fu_78_p3 = fifo_in_1_empty_n; - -assign tmp_3_fu_276_p4 = {{fifo_in_1_dout[95:64]}}; - -assign tmp_4_fu_287_p4 = {{fifo_in_1_dout[127:96]}}; - -assign tmp_5_fu_220_p4 = {{fifo_in_0_dout[95:64]}}; - -assign tmp_6_fu_231_p4 = {{fifo_in_0_dout[127:96]}}; - -assign tmp_7_fu_242_p4 = {{fifo_in_0_dout[159:128]}}; - -assign tmp_8_fu_309_p4 = {{fifo_in_1_dout[255:160]}}; - -assign tmp_9_fu_319_p4 = {{fifo_in_0_dout[255:160]}}; - -assign tmp_s_fu_298_p4 = {{fifo_in_1_dout[159:128]}}; - -endmodule //Merger_Merger_Pipeline_VITIS_LOOP_410_1 diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx.v deleted file mode 100644 index eee6491b..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx.v +++ /dev/null @@ -1,8124 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="PEG_Bmtx_PEG_Bmtx,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.655900,HLS_SYN_LAT=74431,HLS_SYN_TPT=none,HLS_SYN_MEM=128,HLS_SYN_DSP=0,HLS_SYN_FF=8088,HLS_SYN_LUT=9745,HLS_VERSION=2022_2}" *) - -module PEG_Bmtx ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - PE_inst_in_s_dout, - PE_inst_in_s_empty_n, - PE_inst_in_s_read, - PE_inst_in_peek_dout, - PE_inst_in_peek_empty_n, - PE_inst_in_peek_read, - fifo_inst_in_s_dout, - fifo_inst_in_s_empty_n, - fifo_inst_in_s_read, - fifo_inst_in_peek_dout, - fifo_inst_in_peek_empty_n, - fifo_inst_in_peek_read, - fifo_A_s_dout, - fifo_A_s_empty_n, - fifo_A_s_read, - fifo_A_peek_dout, - fifo_A_peek_empty_n, - fifo_A_peek_read, - fifo_B_in_0_dout, - fifo_B_in_0_empty_n, - fifo_B_in_0_read, - fifo_B_in_1_dout, - fifo_B_in_1_empty_n, - fifo_B_in_1_read, - fifo_B_in_2_dout, - fifo_B_in_2_empty_n, - fifo_B_in_2_read, - fifo_B_in_3_dout, - fifo_B_in_3_empty_n, - fifo_B_in_3_read, - fifo_B_in_peek_0_dout, - fifo_B_in_peek_0_empty_n, - fifo_B_in_peek_0_read, - fifo_B_in_peek_1_dout, - fifo_B_in_peek_1_empty_n, - fifo_B_in_peek_1_read, - fifo_B_in_peek_2_dout, - fifo_B_in_peek_2_empty_n, - fifo_B_in_peek_2_read, - fifo_B_in_peek_3_dout, - fifo_B_in_peek_3_empty_n, - fifo_B_in_peek_3_read, - PE_inst_out_din, - PE_inst_out_full_n, - PE_inst_out_write, - fifo_inst_out_din, - fifo_inst_out_full_n, - fifo_inst_out_write, - fifo_B_out_0_din, - fifo_B_out_0_full_n, - fifo_B_out_0_write, - fifo_B_out_1_din, - fifo_B_out_1_full_n, - fifo_B_out_1_write, - fifo_B_out_2_din, - fifo_B_out_2_full_n, - fifo_B_out_2_write, - fifo_B_out_3_din, - fifo_B_out_3_full_n, - fifo_B_out_3_write, - PE_inst_to_Cmtx_din, - PE_inst_to_Cmtx_full_n, - PE_inst_to_Cmtx_write, - fifo_inst_out_to_Cmtx_din, - fifo_inst_out_to_Cmtx_full_n, - fifo_inst_out_to_Cmtx_write, - fifo_aBvec_0_din, - fifo_aBvec_0_full_n, - fifo_aBvec_0_write, - fifo_aBvec_1_din, - fifo_aBvec_1_full_n, - fifo_aBvec_1_write, - fifo_aBvec_2_din, - fifo_aBvec_2_full_n, - fifo_aBvec_2_write, - fifo_aBvec_3_din, - fifo_aBvec_3_full_n, - fifo_aBvec_3_write -); - -parameter ap_ST_fsm_state1 = 15'd1; -parameter ap_ST_fsm_state2 = 15'd2; -parameter ap_ST_fsm_state3 = 15'd4; -parameter ap_ST_fsm_state4 = 15'd8; -parameter ap_ST_fsm_state5 = 15'd16; -parameter ap_ST_fsm_state6 = 15'd32; -parameter ap_ST_fsm_state7 = 15'd64; -parameter ap_ST_fsm_state8 = 15'd128; -parameter ap_ST_fsm_state9 = 15'd256; -parameter ap_ST_fsm_state10 = 15'd512; -parameter ap_ST_fsm_state11 = 15'd1024; -parameter ap_ST_fsm_state12 = 15'd2048; -parameter ap_ST_fsm_state13 = 15'd4096; -parameter ap_ST_fsm_state14 = 15'd8192; -parameter ap_ST_fsm_state15 = 15'd16384; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [32:0] PE_inst_in_s_dout; -input PE_inst_in_s_empty_n; -output PE_inst_in_s_read; -input [32:0] PE_inst_in_peek_dout; -input PE_inst_in_peek_empty_n; -output PE_inst_in_peek_read; -input [32:0] fifo_inst_in_s_dout; -input fifo_inst_in_s_empty_n; -output fifo_inst_in_s_read; -input [32:0] fifo_inst_in_peek_dout; -input fifo_inst_in_peek_empty_n; -output fifo_inst_in_peek_read; -input [256:0] fifo_A_s_dout; -input fifo_A_s_empty_n; -output fifo_A_s_read; -input [256:0] fifo_A_peek_dout; -input fifo_A_peek_empty_n; -output fifo_A_peek_read; -input [512:0] fifo_B_in_0_dout; -input fifo_B_in_0_empty_n; -output fifo_B_in_0_read; -input [512:0] fifo_B_in_1_dout; -input fifo_B_in_1_empty_n; -output fifo_B_in_1_read; -input [512:0] fifo_B_in_2_dout; -input fifo_B_in_2_empty_n; -output fifo_B_in_2_read; -input [512:0] fifo_B_in_3_dout; -input fifo_B_in_3_empty_n; -output fifo_B_in_3_read; -input [512:0] fifo_B_in_peek_0_dout; -input fifo_B_in_peek_0_empty_n; -output fifo_B_in_peek_0_read; -input [512:0] fifo_B_in_peek_1_dout; -input fifo_B_in_peek_1_empty_n; -output fifo_B_in_peek_1_read; -input [512:0] fifo_B_in_peek_2_dout; -input fifo_B_in_peek_2_empty_n; -output fifo_B_in_peek_2_read; -input [512:0] fifo_B_in_peek_3_dout; -input fifo_B_in_peek_3_empty_n; -output fifo_B_in_peek_3_read; -output [32:0] PE_inst_out_din; -input PE_inst_out_full_n; -output PE_inst_out_write; -output [32:0] fifo_inst_out_din; -input fifo_inst_out_full_n; -output fifo_inst_out_write; -output [512:0] fifo_B_out_0_din; -input fifo_B_out_0_full_n; -output fifo_B_out_0_write; -output [512:0] fifo_B_out_1_din; -input fifo_B_out_1_full_n; -output fifo_B_out_1_write; -output [512:0] fifo_B_out_2_din; -input fifo_B_out_2_full_n; -output fifo_B_out_2_write; -output [512:0] fifo_B_out_3_din; -input fifo_B_out_3_full_n; -output fifo_B_out_3_write; -output [32:0] PE_inst_to_Cmtx_din; -input PE_inst_to_Cmtx_full_n; -output PE_inst_to_Cmtx_write; -output [32:0] fifo_inst_out_to_Cmtx_din; -input fifo_inst_out_to_Cmtx_full_n; -output fifo_inst_out_to_Cmtx_write; -output [274:0] fifo_aBvec_0_din; -input fifo_aBvec_0_full_n; -output fifo_aBvec_0_write; -output [274:0] fifo_aBvec_1_din; -input fifo_aBvec_1_full_n; -output fifo_aBvec_1_write; -output [274:0] fifo_aBvec_2_din; -input fifo_aBvec_2_full_n; -output fifo_aBvec_2_write; -output [274:0] fifo_aBvec_3_din; -input fifo_aBvec_3_full_n; -output fifo_aBvec_3_write; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg PE_inst_in_s_read; -reg fifo_inst_in_s_read; -reg fifo_A_s_read; -reg fifo_B_in_0_read; -reg fifo_B_in_1_read; -reg fifo_B_in_2_read; -reg fifo_B_in_3_read; -reg[32:0] PE_inst_out_din; -reg PE_inst_out_write; -reg[32:0] fifo_inst_out_din; -reg fifo_inst_out_write; -reg fifo_B_out_0_write; -reg fifo_B_out_1_write; -reg fifo_B_out_2_write; -reg fifo_B_out_3_write; -reg[32:0] PE_inst_to_Cmtx_din; -reg PE_inst_to_Cmtx_write; -reg[32:0] fifo_inst_out_to_Cmtx_din; -reg fifo_inst_out_to_Cmtx_write; -reg fifo_aBvec_0_write; -reg fifo_aBvec_1_write; -reg fifo_aBvec_2_write; -reg fifo_aBvec_3_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [14:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -reg PE_inst_in_s_blk_n; -wire ap_CS_fsm_state2; -wire ap_CS_fsm_state3; -wire ap_CS_fsm_state7; -reg fifo_inst_in_s_blk_n; -wire ap_CS_fsm_state9; -wire ap_CS_fsm_state13; -reg PE_inst_out_blk_n; -reg fifo_inst_out_blk_n; -reg PE_inst_to_Cmtx_blk_n; -reg fifo_inst_out_to_Cmtx_blk_n; -wire [31:0] NUM_ITE_fu_841_p1; -reg [31:0] NUM_ITE_reg_1069; -reg [15:0] N16_reg_1074; -reg [13:0] lshr_ln_reg_1080; -wire ap_CS_fsm_state4; -wire signed [29:0] grp_fu_1056_p2; -reg signed [29:0] rp_time_N_reg_1095; -wire signed [31:0] shr79_fu_970_p1; -reg signed [31:0] shr79_reg_1100; -wire [27:0] rp_2_fu_986_p2; -reg [27:0] rp_2_reg_1108; -wire ap_CS_fsm_state8; -wire [31:0] start_32_fu_992_p1; -wire [30:0] i_1_fu_1015_p2; -reg [30:0] i_1_reg_1121; -wire ap_CS_fsm_state10; -wire [31:0] sub_fu_1033_p2; -reg [31:0] sub_reg_1126; -wire [0:0] icmp_ln276_fu_1010_p2; -wire [31:0] end_32_fu_1042_p1; -reg [31:0] end_32_reg_1131; -reg [9:0] local_B_address0; -reg local_B_ce0; -reg local_B_we0; -wire [31:0] local_B_q0; -reg [9:0] local_B_address1; -reg local_B_ce1; -reg local_B_we1; -wire [31:0] local_B_q1; -reg [9:0] local_B_1_address0; -reg local_B_1_ce0; -reg local_B_1_we0; -wire [31:0] local_B_1_q0; -reg [9:0] local_B_1_address1; -reg local_B_1_ce1; -reg local_B_1_we1; -wire [31:0] local_B_1_q1; -reg [9:0] local_B_2_address0; -reg local_B_2_ce0; -reg local_B_2_we0; -wire [31:0] local_B_2_q0; -reg [9:0] local_B_2_address1; -reg local_B_2_ce1; -reg local_B_2_we1; -wire [31:0] local_B_2_q1; -reg [9:0] local_B_3_address0; -reg local_B_3_ce0; -reg local_B_3_we0; -wire [31:0] local_B_3_q0; -reg [9:0] local_B_3_address1; -reg local_B_3_ce1; -reg local_B_3_we1; -wire [31:0] local_B_3_q1; -reg [9:0] local_B_4_address0; -reg local_B_4_ce0; -reg local_B_4_we0; -wire [31:0] local_B_4_q0; -reg [9:0] local_B_4_address1; -reg local_B_4_ce1; -reg local_B_4_we1; -wire [31:0] local_B_4_q1; -reg [9:0] local_B_5_address0; -reg local_B_5_ce0; -reg local_B_5_we0; -wire [31:0] local_B_5_q0; -reg [9:0] local_B_5_address1; -reg local_B_5_ce1; -reg local_B_5_we1; -wire [31:0] local_B_5_q1; -reg [9:0] local_B_6_address0; -reg local_B_6_ce0; -reg local_B_6_we0; -wire [31:0] local_B_6_q0; -reg [9:0] local_B_6_address1; -reg local_B_6_ce1; -reg local_B_6_we1; -wire [31:0] local_B_6_q1; -reg [9:0] local_B_7_address0; -reg local_B_7_ce0; -reg local_B_7_we0; -wire [31:0] local_B_7_q0; -reg [9:0] local_B_7_address1; -reg local_B_7_ce1; -reg local_B_7_we1; -wire [31:0] local_B_7_q1; -reg [9:0] local_B_8_address0; -reg local_B_8_ce0; -reg local_B_8_we0; -wire [31:0] local_B_8_q0; -reg [9:0] local_B_8_address1; -reg local_B_8_ce1; -reg local_B_8_we1; -wire [31:0] local_B_8_q1; -reg [9:0] local_B_9_address0; -reg local_B_9_ce0; -reg local_B_9_we0; -wire [31:0] local_B_9_q0; -reg [9:0] local_B_9_address1; -reg local_B_9_ce1; -reg local_B_9_we1; -wire [31:0] local_B_9_q1; -reg [9:0] local_B_10_address0; -reg local_B_10_ce0; -reg local_B_10_we0; -wire [31:0] local_B_10_q0; -reg [9:0] local_B_10_address1; -reg local_B_10_ce1; -reg local_B_10_we1; -wire [31:0] local_B_10_q1; -reg [9:0] local_B_11_address0; -reg local_B_11_ce0; -reg local_B_11_we0; -wire [31:0] local_B_11_q0; -reg [9:0] local_B_11_address1; -reg local_B_11_ce1; -reg local_B_11_we1; -wire [31:0] local_B_11_q1; -reg [9:0] local_B_12_address0; -reg local_B_12_ce0; -reg local_B_12_we0; -wire [31:0] local_B_12_q0; -reg [9:0] local_B_12_address1; -reg local_B_12_ce1; -reg local_B_12_we1; -wire [31:0] local_B_12_q1; -reg [9:0] local_B_13_address0; -reg local_B_13_ce0; -reg local_B_13_we0; -wire [31:0] local_B_13_q0; -reg [9:0] local_B_13_address1; -reg local_B_13_ce1; -reg local_B_13_we1; -wire [31:0] local_B_13_q1; -reg [9:0] local_B_14_address0; -reg local_B_14_ce0; -reg local_B_14_we0; -wire [31:0] local_B_14_q0; -reg [9:0] local_B_14_address1; -reg local_B_14_ce1; -reg local_B_14_we1; -wire [31:0] local_B_14_q1; -reg [9:0] local_B_15_address0; -reg local_B_15_ce0; -reg local_B_15_we0; -wire [31:0] local_B_15_q0; -reg [9:0] local_B_15_address1; -reg local_B_15_ce1; -reg local_B_15_we1; -wire [31:0] local_B_15_q1; -reg [9:0] local_B_16_address0; -reg local_B_16_ce0; -reg local_B_16_we0; -wire [31:0] local_B_16_q0; -reg [9:0] local_B_16_address1; -reg local_B_16_ce1; -reg local_B_16_we1; -wire [31:0] local_B_16_q1; -reg [9:0] local_B_17_address0; -reg local_B_17_ce0; -reg local_B_17_we0; -wire [31:0] local_B_17_q0; -reg [9:0] local_B_17_address1; -reg local_B_17_ce1; -reg local_B_17_we1; -wire [31:0] local_B_17_q1; -reg [9:0] local_B_18_address0; -reg local_B_18_ce0; -reg local_B_18_we0; -wire [31:0] local_B_18_q0; -reg [9:0] local_B_18_address1; -reg local_B_18_ce1; -reg local_B_18_we1; -wire [31:0] local_B_18_q1; -reg [9:0] local_B_19_address0; -reg local_B_19_ce0; -reg local_B_19_we0; -wire [31:0] local_B_19_q0; -reg [9:0] local_B_19_address1; -reg local_B_19_ce1; -reg local_B_19_we1; -wire [31:0] local_B_19_q1; -reg [9:0] local_B_20_address0; -reg local_B_20_ce0; -reg local_B_20_we0; -wire [31:0] local_B_20_q0; -reg [9:0] local_B_20_address1; -reg local_B_20_ce1; -reg local_B_20_we1; -wire [31:0] local_B_20_q1; -reg [9:0] local_B_21_address0; -reg local_B_21_ce0; -reg local_B_21_we0; -wire [31:0] local_B_21_q0; -reg [9:0] local_B_21_address1; -reg local_B_21_ce1; -reg local_B_21_we1; -wire [31:0] local_B_21_q1; -reg [9:0] local_B_22_address0; -reg local_B_22_ce0; -reg local_B_22_we0; -wire [31:0] local_B_22_q0; -reg [9:0] local_B_22_address1; -reg local_B_22_ce1; -reg local_B_22_we1; -wire [31:0] local_B_22_q1; -reg [9:0] local_B_23_address0; -reg local_B_23_ce0; -reg local_B_23_we0; -wire [31:0] local_B_23_q0; -reg [9:0] local_B_23_address1; -reg local_B_23_ce1; -reg local_B_23_we1; -wire [31:0] local_B_23_q1; -reg [9:0] local_B_24_address0; -reg local_B_24_ce0; -reg local_B_24_we0; -wire [31:0] local_B_24_q0; -reg [9:0] local_B_24_address1; -reg local_B_24_ce1; -reg local_B_24_we1; -wire [31:0] local_B_24_q1; -reg [9:0] local_B_25_address0; -reg local_B_25_ce0; -reg local_B_25_we0; -wire [31:0] local_B_25_q0; -reg [9:0] local_B_25_address1; -reg local_B_25_ce1; -reg local_B_25_we1; -wire [31:0] local_B_25_q1; -reg [9:0] local_B_26_address0; -reg local_B_26_ce0; -reg local_B_26_we0; -wire [31:0] local_B_26_q0; -reg [9:0] local_B_26_address1; -reg local_B_26_ce1; -reg local_B_26_we1; -wire [31:0] local_B_26_q1; -reg [9:0] local_B_27_address0; -reg local_B_27_ce0; -reg local_B_27_we0; -wire [31:0] local_B_27_q0; -reg [9:0] local_B_27_address1; -reg local_B_27_ce1; -reg local_B_27_we1; -wire [31:0] local_B_27_q1; -reg [9:0] local_B_28_address0; -reg local_B_28_ce0; -reg local_B_28_we0; -wire [31:0] local_B_28_q0; -reg [9:0] local_B_28_address1; -reg local_B_28_ce1; -reg local_B_28_we1; -wire [31:0] local_B_28_q1; -reg [9:0] local_B_29_address0; -reg local_B_29_ce0; -reg local_B_29_we0; -wire [31:0] local_B_29_q0; -reg [9:0] local_B_29_address1; -reg local_B_29_ce1; -reg local_B_29_we1; -wire [31:0] local_B_29_q1; -reg [9:0] local_B_30_address0; -reg local_B_30_ce0; -reg local_B_30_we0; -wire [31:0] local_B_30_q0; -reg [9:0] local_B_30_address1; -reg local_B_30_ce1; -reg local_B_30_we1; -wire [31:0] local_B_30_q1; -reg [9:0] local_B_31_address0; -reg local_B_31_ce0; -reg local_B_31_we0; -wire [31:0] local_B_31_q0; -reg [9:0] local_B_31_address1; -reg local_B_31_ce1; -reg local_B_31_we1; -wire [31:0] local_B_31_q1; -reg [9:0] local_B_32_address0; -reg local_B_32_ce0; -reg local_B_32_we0; -wire [31:0] local_B_32_q0; -reg [9:0] local_B_32_address1; -reg local_B_32_ce1; -reg local_B_32_we1; -wire [31:0] local_B_32_q1; -reg [9:0] local_B_33_address0; -reg local_B_33_ce0; -reg local_B_33_we0; -wire [31:0] local_B_33_q0; -reg [9:0] local_B_33_address1; -reg local_B_33_ce1; -reg local_B_33_we1; -wire [31:0] local_B_33_q1; -reg [9:0] local_B_34_address0; -reg local_B_34_ce0; -reg local_B_34_we0; -wire [31:0] local_B_34_q0; -reg [9:0] local_B_34_address1; -reg local_B_34_ce1; -reg local_B_34_we1; -wire [31:0] local_B_34_q1; -reg [9:0] local_B_35_address0; -reg local_B_35_ce0; -reg local_B_35_we0; -wire [31:0] local_B_35_q0; -reg [9:0] local_B_35_address1; -reg local_B_35_ce1; -reg local_B_35_we1; -wire [31:0] local_B_35_q1; -reg [9:0] local_B_36_address0; -reg local_B_36_ce0; -reg local_B_36_we0; -wire [31:0] local_B_36_q0; -reg [9:0] local_B_36_address1; -reg local_B_36_ce1; -reg local_B_36_we1; -wire [31:0] local_B_36_q1; -reg [9:0] local_B_37_address0; -reg local_B_37_ce0; -reg local_B_37_we0; -wire [31:0] local_B_37_q0; -reg [9:0] local_B_37_address1; -reg local_B_37_ce1; -reg local_B_37_we1; -wire [31:0] local_B_37_q1; -reg [9:0] local_B_38_address0; -reg local_B_38_ce0; -reg local_B_38_we0; -wire [31:0] local_B_38_q0; -reg [9:0] local_B_38_address1; -reg local_B_38_ce1; -reg local_B_38_we1; -wire [31:0] local_B_38_q1; -reg [9:0] local_B_39_address0; -reg local_B_39_ce0; -reg local_B_39_we0; -wire [31:0] local_B_39_q0; -reg [9:0] local_B_39_address1; -reg local_B_39_ce1; -reg local_B_39_we1; -wire [31:0] local_B_39_q1; -reg [9:0] local_B_40_address0; -reg local_B_40_ce0; -reg local_B_40_we0; -wire [31:0] local_B_40_q0; -reg [9:0] local_B_40_address1; -reg local_B_40_ce1; -reg local_B_40_we1; -wire [31:0] local_B_40_q1; -reg [9:0] local_B_41_address0; -reg local_B_41_ce0; -reg local_B_41_we0; -wire [31:0] local_B_41_q0; -reg [9:0] local_B_41_address1; -reg local_B_41_ce1; -reg local_B_41_we1; -wire [31:0] local_B_41_q1; -reg [9:0] local_B_42_address0; -reg local_B_42_ce0; -reg local_B_42_we0; -wire [31:0] local_B_42_q0; -reg [9:0] local_B_42_address1; -reg local_B_42_ce1; -reg local_B_42_we1; -wire [31:0] local_B_42_q1; -reg [9:0] local_B_43_address0; -reg local_B_43_ce0; -reg local_B_43_we0; -wire [31:0] local_B_43_q0; -reg [9:0] local_B_43_address1; -reg local_B_43_ce1; -reg local_B_43_we1; -wire [31:0] local_B_43_q1; -reg [9:0] local_B_44_address0; -reg local_B_44_ce0; -reg local_B_44_we0; -wire [31:0] local_B_44_q0; -reg [9:0] local_B_44_address1; -reg local_B_44_ce1; -reg local_B_44_we1; -wire [31:0] local_B_44_q1; -reg [9:0] local_B_45_address0; -reg local_B_45_ce0; -reg local_B_45_we0; -wire [31:0] local_B_45_q0; -reg [9:0] local_B_45_address1; -reg local_B_45_ce1; -reg local_B_45_we1; -wire [31:0] local_B_45_q1; -reg [9:0] local_B_46_address0; -reg local_B_46_ce0; -reg local_B_46_we0; -wire [31:0] local_B_46_q0; -reg [9:0] local_B_46_address1; -reg local_B_46_ce1; -reg local_B_46_we1; -wire [31:0] local_B_46_q1; -reg [9:0] local_B_47_address0; -reg local_B_47_ce0; -reg local_B_47_we0; -wire [31:0] local_B_47_q0; -reg [9:0] local_B_47_address1; -reg local_B_47_ce1; -reg local_B_47_we1; -wire [31:0] local_B_47_q1; -reg [9:0] local_B_48_address0; -reg local_B_48_ce0; -reg local_B_48_we0; -wire [31:0] local_B_48_q0; -reg [9:0] local_B_48_address1; -reg local_B_48_ce1; -reg local_B_48_we1; -wire [31:0] local_B_48_q1; -reg [9:0] local_B_49_address0; -reg local_B_49_ce0; -reg local_B_49_we0; -wire [31:0] local_B_49_q0; -reg [9:0] local_B_49_address1; -reg local_B_49_ce1; -reg local_B_49_we1; -wire [31:0] local_B_49_q1; -reg [9:0] local_B_50_address0; -reg local_B_50_ce0; -reg local_B_50_we0; -wire [31:0] local_B_50_q0; -reg [9:0] local_B_50_address1; -reg local_B_50_ce1; -reg local_B_50_we1; -wire [31:0] local_B_50_q1; -reg [9:0] local_B_51_address0; -reg local_B_51_ce0; -reg local_B_51_we0; -wire [31:0] local_B_51_q0; -reg [9:0] local_B_51_address1; -reg local_B_51_ce1; -reg local_B_51_we1; -wire [31:0] local_B_51_q1; -reg [9:0] local_B_52_address0; -reg local_B_52_ce0; -reg local_B_52_we0; -wire [31:0] local_B_52_q0; -reg [9:0] local_B_52_address1; -reg local_B_52_ce1; -reg local_B_52_we1; -wire [31:0] local_B_52_q1; -reg [9:0] local_B_53_address0; -reg local_B_53_ce0; -reg local_B_53_we0; -wire [31:0] local_B_53_q0; -reg [9:0] local_B_53_address1; -reg local_B_53_ce1; -reg local_B_53_we1; -wire [31:0] local_B_53_q1; -reg [9:0] local_B_54_address0; -reg local_B_54_ce0; -reg local_B_54_we0; -wire [31:0] local_B_54_q0; -reg [9:0] local_B_54_address1; -reg local_B_54_ce1; -reg local_B_54_we1; -wire [31:0] local_B_54_q1; -reg [9:0] local_B_55_address0; -reg local_B_55_ce0; -reg local_B_55_we0; -wire [31:0] local_B_55_q0; -reg [9:0] local_B_55_address1; -reg local_B_55_ce1; -reg local_B_55_we1; -wire [31:0] local_B_55_q1; -reg [9:0] local_B_56_address0; -reg local_B_56_ce0; -reg local_B_56_we0; -wire [31:0] local_B_56_q0; -reg [9:0] local_B_56_address1; -reg local_B_56_ce1; -reg local_B_56_we1; -wire [31:0] local_B_56_q1; -reg [9:0] local_B_57_address0; -reg local_B_57_ce0; -reg local_B_57_we0; -wire [31:0] local_B_57_q0; -reg [9:0] local_B_57_address1; -reg local_B_57_ce1; -reg local_B_57_we1; -wire [31:0] local_B_57_q1; -reg [9:0] local_B_58_address0; -reg local_B_58_ce0; -reg local_B_58_we0; -wire [31:0] local_B_58_q0; -reg [9:0] local_B_58_address1; -reg local_B_58_ce1; -reg local_B_58_we1; -wire [31:0] local_B_58_q1; -reg [9:0] local_B_59_address0; -reg local_B_59_ce0; -reg local_B_59_we0; -wire [31:0] local_B_59_q0; -reg [9:0] local_B_59_address1; -reg local_B_59_ce1; -reg local_B_59_we1; -wire [31:0] local_B_59_q1; -reg [9:0] local_B_60_address0; -reg local_B_60_ce0; -reg local_B_60_we0; -wire [31:0] local_B_60_q0; -reg [9:0] local_B_60_address1; -reg local_B_60_ce1; -reg local_B_60_we1; -wire [31:0] local_B_60_q1; -reg [9:0] local_B_61_address0; -reg local_B_61_ce0; -reg local_B_61_we0; -wire [31:0] local_B_61_q0; -reg [9:0] local_B_61_address1; -reg local_B_61_ce1; -reg local_B_61_we1; -wire [31:0] local_B_61_q1; -reg [9:0] local_B_62_address0; -reg local_B_62_ce0; -reg local_B_62_we0; -wire [31:0] local_B_62_q0; -reg [9:0] local_B_62_address1; -reg local_B_62_ce1; -reg local_B_62_we1; -wire [31:0] local_B_62_q1; -reg [9:0] local_B_63_address0; -reg local_B_63_ce0; -reg local_B_63_we0; -wire [31:0] local_B_63_q0; -reg [9:0] local_B_63_address1; -reg local_B_63_ce1; -reg local_B_63_we1; -wire [31:0] local_B_63_q1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_start; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_done; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_idle; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_ready; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_d1; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_address0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_ce0; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_we0; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_d0; -wire [9:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_address1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_ce1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_we1; -wire [31:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_d1; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_0_read; -wire [512:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_0_din; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_0_write; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_1_read; -wire [512:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_1_din; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_1_write; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_2_read; -wire [512:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_2_din; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_2_write; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_3_read; -wire [512:0] grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_3_din; -wire grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_3_write; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_start; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_done; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_idle; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_ready; -wire [274:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_0_din; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_0_write; -wire [274:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_1_din; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_1_write; -wire [274:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_2_din; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_2_write; -wire [274:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_3_din; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_3_write; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_A_s_read; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_ce1; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_address0; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_ce0; -wire [9:0] grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_address1; -wire grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_ce1; -reg [30:0] i_reg_654; -reg ap_block_state9; -wire ap_CS_fsm_state15; -reg [31:0] start_32_3_reg_665; -reg grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_start_reg; -wire ap_CS_fsm_state11; -wire ap_CS_fsm_state12; -reg grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_start_reg; -wire ap_CS_fsm_state14; -reg [27:0] rp_fu_146; -reg ap_block_state1; -reg ap_block_state2; -reg ap_block_state3; -reg ap_block_state7; -wire [32:0] p_s_fu_845_p3; -wire [32:0] p_10_fu_864_p3; -wire [32:0] p_0_fu_882_p3; -wire [32:0] p_11_fu_945_p3; -reg ap_block_state13; -wire [32:0] tmp_9_fu_996_p3; -wire [32:0] tmp_11_fu_1046_p3; -wire [31:0] trunc_ln85_fu_860_p1; -wire [31:0] P_N_fu_874_p1; -wire [15:0] N_fu_878_p1; -wire [16:0] zext_ln256_fu_902_p1; -wire [16:0] add_ln257_fu_906_p2; -wire [0:0] icmp_ln255_fu_922_p2; -wire signed [15:0] rp_time_fu_927_p3; -wire [31:0] K_fu_941_p1; -wire [31:0] add78_fu_954_p2; -wire [28:0] p_cast_fu_960_p4; -wire [29:0] zext_ln259_fu_977_p1; -wire [31:0] zext_ln276_fu_1006_p1; -wire [22:0] empty_155_fu_1021_p1; -wire [31:0] mul_fu_1025_p3; -wire [13:0] grp_fu_1056_p1; -wire [0:0] icmp_ln259_fu_981_p2; -reg grp_fu_1056_ce; -wire ap_CS_fsm_state5; -wire ap_CS_fsm_state6; -reg [14:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -reg ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -wire ap_ST_fsm_state4_blk; -wire ap_ST_fsm_state5_blk; -wire ap_ST_fsm_state6_blk; -reg ap_ST_fsm_state7_blk; -wire ap_ST_fsm_state8_blk; -reg ap_ST_fsm_state9_blk; -wire ap_ST_fsm_state10_blk; -wire ap_ST_fsm_state11_blk; -reg ap_ST_fsm_state12_blk; -reg ap_ST_fsm_state13_blk; -wire ap_ST_fsm_state14_blk; -reg ap_ST_fsm_state15_blk; -wire [29:0] grp_fu_1056_p10; -reg ap_condition_2077; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 15'd1; -#0 grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_start_reg = 1'b0; -#0 grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_start_reg = 1'b0; -end - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_address0), - .ce0(local_B_ce0), - .we0(local_B_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_d0), - .q0(local_B_q0), - .address1(local_B_address1), - .ce1(local_B_ce1), - .we1(local_B_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_d1), - .q1(local_B_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_1_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_1_address0), - .ce0(local_B_1_ce0), - .we0(local_B_1_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_d0), - .q0(local_B_1_q0), - .address1(local_B_1_address1), - .ce1(local_B_1_ce1), - .we1(local_B_1_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_d1), - .q1(local_B_1_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_2_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_2_address0), - .ce0(local_B_2_ce0), - .we0(local_B_2_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_d0), - .q0(local_B_2_q0), - .address1(local_B_2_address1), - .ce1(local_B_2_ce1), - .we1(local_B_2_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_d1), - .q1(local_B_2_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_3_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_3_address0), - .ce0(local_B_3_ce0), - .we0(local_B_3_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_d0), - .q0(local_B_3_q0), - .address1(local_B_3_address1), - .ce1(local_B_3_ce1), - .we1(local_B_3_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_d1), - .q1(local_B_3_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_4_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_4_address0), - .ce0(local_B_4_ce0), - .we0(local_B_4_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_d0), - .q0(local_B_4_q0), - .address1(local_B_4_address1), - .ce1(local_B_4_ce1), - .we1(local_B_4_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_d1), - .q1(local_B_4_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_5_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_5_address0), - .ce0(local_B_5_ce0), - .we0(local_B_5_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_d0), - .q0(local_B_5_q0), - .address1(local_B_5_address1), - .ce1(local_B_5_ce1), - .we1(local_B_5_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_d1), - .q1(local_B_5_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_6_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_6_address0), - .ce0(local_B_6_ce0), - .we0(local_B_6_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_d0), - .q0(local_B_6_q0), - .address1(local_B_6_address1), - .ce1(local_B_6_ce1), - .we1(local_B_6_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_d1), - .q1(local_B_6_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_7_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_7_address0), - .ce0(local_B_7_ce0), - .we0(local_B_7_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_d0), - .q0(local_B_7_q0), - .address1(local_B_7_address1), - .ce1(local_B_7_ce1), - .we1(local_B_7_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_d1), - .q1(local_B_7_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_8_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_8_address0), - .ce0(local_B_8_ce0), - .we0(local_B_8_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_d0), - .q0(local_B_8_q0), - .address1(local_B_8_address1), - .ce1(local_B_8_ce1), - .we1(local_B_8_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_d1), - .q1(local_B_8_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_9_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_9_address0), - .ce0(local_B_9_ce0), - .we0(local_B_9_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_d0), - .q0(local_B_9_q0), - .address1(local_B_9_address1), - .ce1(local_B_9_ce1), - .we1(local_B_9_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_d1), - .q1(local_B_9_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_10_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_10_address0), - .ce0(local_B_10_ce0), - .we0(local_B_10_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_d0), - .q0(local_B_10_q0), - .address1(local_B_10_address1), - .ce1(local_B_10_ce1), - .we1(local_B_10_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_d1), - .q1(local_B_10_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_11_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_11_address0), - .ce0(local_B_11_ce0), - .we0(local_B_11_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_d0), - .q0(local_B_11_q0), - .address1(local_B_11_address1), - .ce1(local_B_11_ce1), - .we1(local_B_11_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_d1), - .q1(local_B_11_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_12_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_12_address0), - .ce0(local_B_12_ce0), - .we0(local_B_12_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_d0), - .q0(local_B_12_q0), - .address1(local_B_12_address1), - .ce1(local_B_12_ce1), - .we1(local_B_12_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_d1), - .q1(local_B_12_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_13_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_13_address0), - .ce0(local_B_13_ce0), - .we0(local_B_13_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_d0), - .q0(local_B_13_q0), - .address1(local_B_13_address1), - .ce1(local_B_13_ce1), - .we1(local_B_13_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_d1), - .q1(local_B_13_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_14_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_14_address0), - .ce0(local_B_14_ce0), - .we0(local_B_14_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_d0), - .q0(local_B_14_q0), - .address1(local_B_14_address1), - .ce1(local_B_14_ce1), - .we1(local_B_14_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_d1), - .q1(local_B_14_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_15_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_15_address0), - .ce0(local_B_15_ce0), - .we0(local_B_15_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_d0), - .q0(local_B_15_q0), - .address1(local_B_15_address1), - .ce1(local_B_15_ce1), - .we1(local_B_15_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_d1), - .q1(local_B_15_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_16_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_16_address0), - .ce0(local_B_16_ce0), - .we0(local_B_16_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_d0), - .q0(local_B_16_q0), - .address1(local_B_16_address1), - .ce1(local_B_16_ce1), - .we1(local_B_16_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_d1), - .q1(local_B_16_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_17_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_17_address0), - .ce0(local_B_17_ce0), - .we0(local_B_17_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_d0), - .q0(local_B_17_q0), - .address1(local_B_17_address1), - .ce1(local_B_17_ce1), - .we1(local_B_17_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_d1), - .q1(local_B_17_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_18_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_18_address0), - .ce0(local_B_18_ce0), - .we0(local_B_18_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_d0), - .q0(local_B_18_q0), - .address1(local_B_18_address1), - .ce1(local_B_18_ce1), - .we1(local_B_18_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_d1), - .q1(local_B_18_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_19_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_19_address0), - .ce0(local_B_19_ce0), - .we0(local_B_19_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_d0), - .q0(local_B_19_q0), - .address1(local_B_19_address1), - .ce1(local_B_19_ce1), - .we1(local_B_19_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_d1), - .q1(local_B_19_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_20_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_20_address0), - .ce0(local_B_20_ce0), - .we0(local_B_20_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_d0), - .q0(local_B_20_q0), - .address1(local_B_20_address1), - .ce1(local_B_20_ce1), - .we1(local_B_20_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_d1), - .q1(local_B_20_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_21_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_21_address0), - .ce0(local_B_21_ce0), - .we0(local_B_21_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_d0), - .q0(local_B_21_q0), - .address1(local_B_21_address1), - .ce1(local_B_21_ce1), - .we1(local_B_21_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_d1), - .q1(local_B_21_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_22_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_22_address0), - .ce0(local_B_22_ce0), - .we0(local_B_22_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_d0), - .q0(local_B_22_q0), - .address1(local_B_22_address1), - .ce1(local_B_22_ce1), - .we1(local_B_22_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_d1), - .q1(local_B_22_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_23_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_23_address0), - .ce0(local_B_23_ce0), - .we0(local_B_23_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_d0), - .q0(local_B_23_q0), - .address1(local_B_23_address1), - .ce1(local_B_23_ce1), - .we1(local_B_23_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_d1), - .q1(local_B_23_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_24_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_24_address0), - .ce0(local_B_24_ce0), - .we0(local_B_24_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_d0), - .q0(local_B_24_q0), - .address1(local_B_24_address1), - .ce1(local_B_24_ce1), - .we1(local_B_24_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_d1), - .q1(local_B_24_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_25_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_25_address0), - .ce0(local_B_25_ce0), - .we0(local_B_25_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_d0), - .q0(local_B_25_q0), - .address1(local_B_25_address1), - .ce1(local_B_25_ce1), - .we1(local_B_25_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_d1), - .q1(local_B_25_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_26_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_26_address0), - .ce0(local_B_26_ce0), - .we0(local_B_26_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_d0), - .q0(local_B_26_q0), - .address1(local_B_26_address1), - .ce1(local_B_26_ce1), - .we1(local_B_26_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_d1), - .q1(local_B_26_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_27_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_27_address0), - .ce0(local_B_27_ce0), - .we0(local_B_27_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_d0), - .q0(local_B_27_q0), - .address1(local_B_27_address1), - .ce1(local_B_27_ce1), - .we1(local_B_27_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_d1), - .q1(local_B_27_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_28_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_28_address0), - .ce0(local_B_28_ce0), - .we0(local_B_28_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_d0), - .q0(local_B_28_q0), - .address1(local_B_28_address1), - .ce1(local_B_28_ce1), - .we1(local_B_28_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_d1), - .q1(local_B_28_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_29_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_29_address0), - .ce0(local_B_29_ce0), - .we0(local_B_29_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_d0), - .q0(local_B_29_q0), - .address1(local_B_29_address1), - .ce1(local_B_29_ce1), - .we1(local_B_29_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_d1), - .q1(local_B_29_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_30_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_30_address0), - .ce0(local_B_30_ce0), - .we0(local_B_30_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_d0), - .q0(local_B_30_q0), - .address1(local_B_30_address1), - .ce1(local_B_30_ce1), - .we1(local_B_30_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_d1), - .q1(local_B_30_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_31_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_31_address0), - .ce0(local_B_31_ce0), - .we0(local_B_31_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_d0), - .q0(local_B_31_q0), - .address1(local_B_31_address1), - .ce1(local_B_31_ce1), - .we1(local_B_31_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_d1), - .q1(local_B_31_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_32_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_32_address0), - .ce0(local_B_32_ce0), - .we0(local_B_32_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_d0), - .q0(local_B_32_q0), - .address1(local_B_32_address1), - .ce1(local_B_32_ce1), - .we1(local_B_32_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_d1), - .q1(local_B_32_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_33_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_33_address0), - .ce0(local_B_33_ce0), - .we0(local_B_33_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_d0), - .q0(local_B_33_q0), - .address1(local_B_33_address1), - .ce1(local_B_33_ce1), - .we1(local_B_33_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_d1), - .q1(local_B_33_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_34_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_34_address0), - .ce0(local_B_34_ce0), - .we0(local_B_34_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_d0), - .q0(local_B_34_q0), - .address1(local_B_34_address1), - .ce1(local_B_34_ce1), - .we1(local_B_34_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_d1), - .q1(local_B_34_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_35_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_35_address0), - .ce0(local_B_35_ce0), - .we0(local_B_35_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_d0), - .q0(local_B_35_q0), - .address1(local_B_35_address1), - .ce1(local_B_35_ce1), - .we1(local_B_35_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_d1), - .q1(local_B_35_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_36_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_36_address0), - .ce0(local_B_36_ce0), - .we0(local_B_36_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_d0), - .q0(local_B_36_q0), - .address1(local_B_36_address1), - .ce1(local_B_36_ce1), - .we1(local_B_36_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_d1), - .q1(local_B_36_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_37_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_37_address0), - .ce0(local_B_37_ce0), - .we0(local_B_37_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_d0), - .q0(local_B_37_q0), - .address1(local_B_37_address1), - .ce1(local_B_37_ce1), - .we1(local_B_37_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_d1), - .q1(local_B_37_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_38_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_38_address0), - .ce0(local_B_38_ce0), - .we0(local_B_38_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_d0), - .q0(local_B_38_q0), - .address1(local_B_38_address1), - .ce1(local_B_38_ce1), - .we1(local_B_38_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_d1), - .q1(local_B_38_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_39_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_39_address0), - .ce0(local_B_39_ce0), - .we0(local_B_39_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_d0), - .q0(local_B_39_q0), - .address1(local_B_39_address1), - .ce1(local_B_39_ce1), - .we1(local_B_39_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_d1), - .q1(local_B_39_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_40_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_40_address0), - .ce0(local_B_40_ce0), - .we0(local_B_40_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_d0), - .q0(local_B_40_q0), - .address1(local_B_40_address1), - .ce1(local_B_40_ce1), - .we1(local_B_40_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_d1), - .q1(local_B_40_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_41_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_41_address0), - .ce0(local_B_41_ce0), - .we0(local_B_41_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_d0), - .q0(local_B_41_q0), - .address1(local_B_41_address1), - .ce1(local_B_41_ce1), - .we1(local_B_41_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_d1), - .q1(local_B_41_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_42_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_42_address0), - .ce0(local_B_42_ce0), - .we0(local_B_42_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_d0), - .q0(local_B_42_q0), - .address1(local_B_42_address1), - .ce1(local_B_42_ce1), - .we1(local_B_42_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_d1), - .q1(local_B_42_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_43_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_43_address0), - .ce0(local_B_43_ce0), - .we0(local_B_43_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_d0), - .q0(local_B_43_q0), - .address1(local_B_43_address1), - .ce1(local_B_43_ce1), - .we1(local_B_43_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_d1), - .q1(local_B_43_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_44_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_44_address0), - .ce0(local_B_44_ce0), - .we0(local_B_44_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_d0), - .q0(local_B_44_q0), - .address1(local_B_44_address1), - .ce1(local_B_44_ce1), - .we1(local_B_44_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_d1), - .q1(local_B_44_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_45_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_45_address0), - .ce0(local_B_45_ce0), - .we0(local_B_45_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_d0), - .q0(local_B_45_q0), - .address1(local_B_45_address1), - .ce1(local_B_45_ce1), - .we1(local_B_45_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_d1), - .q1(local_B_45_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_46_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_46_address0), - .ce0(local_B_46_ce0), - .we0(local_B_46_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_d0), - .q0(local_B_46_q0), - .address1(local_B_46_address1), - .ce1(local_B_46_ce1), - .we1(local_B_46_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_d1), - .q1(local_B_46_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_47_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_47_address0), - .ce0(local_B_47_ce0), - .we0(local_B_47_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_d0), - .q0(local_B_47_q0), - .address1(local_B_47_address1), - .ce1(local_B_47_ce1), - .we1(local_B_47_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_d1), - .q1(local_B_47_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_48_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_48_address0), - .ce0(local_B_48_ce0), - .we0(local_B_48_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_d0), - .q0(local_B_48_q0), - .address1(local_B_48_address1), - .ce1(local_B_48_ce1), - .we1(local_B_48_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_d1), - .q1(local_B_48_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_49_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_49_address0), - .ce0(local_B_49_ce0), - .we0(local_B_49_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_d0), - .q0(local_B_49_q0), - .address1(local_B_49_address1), - .ce1(local_B_49_ce1), - .we1(local_B_49_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_d1), - .q1(local_B_49_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_50_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_50_address0), - .ce0(local_B_50_ce0), - .we0(local_B_50_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_d0), - .q0(local_B_50_q0), - .address1(local_B_50_address1), - .ce1(local_B_50_ce1), - .we1(local_B_50_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_d1), - .q1(local_B_50_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_51_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_51_address0), - .ce0(local_B_51_ce0), - .we0(local_B_51_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_d0), - .q0(local_B_51_q0), - .address1(local_B_51_address1), - .ce1(local_B_51_ce1), - .we1(local_B_51_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_d1), - .q1(local_B_51_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_52_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_52_address0), - .ce0(local_B_52_ce0), - .we0(local_B_52_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_d0), - .q0(local_B_52_q0), - .address1(local_B_52_address1), - .ce1(local_B_52_ce1), - .we1(local_B_52_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_d1), - .q1(local_B_52_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_53_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_53_address0), - .ce0(local_B_53_ce0), - .we0(local_B_53_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_d0), - .q0(local_B_53_q0), - .address1(local_B_53_address1), - .ce1(local_B_53_ce1), - .we1(local_B_53_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_d1), - .q1(local_B_53_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_54_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_54_address0), - .ce0(local_B_54_ce0), - .we0(local_B_54_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_d0), - .q0(local_B_54_q0), - .address1(local_B_54_address1), - .ce1(local_B_54_ce1), - .we1(local_B_54_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_d1), - .q1(local_B_54_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_55_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_55_address0), - .ce0(local_B_55_ce0), - .we0(local_B_55_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_d0), - .q0(local_B_55_q0), - .address1(local_B_55_address1), - .ce1(local_B_55_ce1), - .we1(local_B_55_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_d1), - .q1(local_B_55_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_56_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_56_address0), - .ce0(local_B_56_ce0), - .we0(local_B_56_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_d0), - .q0(local_B_56_q0), - .address1(local_B_56_address1), - .ce1(local_B_56_ce1), - .we1(local_B_56_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_d1), - .q1(local_B_56_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_57_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_57_address0), - .ce0(local_B_57_ce0), - .we0(local_B_57_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_d0), - .q0(local_B_57_q0), - .address1(local_B_57_address1), - .ce1(local_B_57_ce1), - .we1(local_B_57_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_d1), - .q1(local_B_57_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_58_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_58_address0), - .ce0(local_B_58_ce0), - .we0(local_B_58_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_d0), - .q0(local_B_58_q0), - .address1(local_B_58_address1), - .ce1(local_B_58_ce1), - .we1(local_B_58_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_d1), - .q1(local_B_58_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_59_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_59_address0), - .ce0(local_B_59_ce0), - .we0(local_B_59_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_d0), - .q0(local_B_59_q0), - .address1(local_B_59_address1), - .ce1(local_B_59_ce1), - .we1(local_B_59_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_d1), - .q1(local_B_59_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_60_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_60_address0), - .ce0(local_B_60_ce0), - .we0(local_B_60_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_d0), - .q0(local_B_60_q0), - .address1(local_B_60_address1), - .ce1(local_B_60_ce1), - .we1(local_B_60_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_d1), - .q1(local_B_60_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_61_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_61_address0), - .ce0(local_B_61_ce0), - .we0(local_B_61_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_d0), - .q0(local_B_61_q0), - .address1(local_B_61_address1), - .ce1(local_B_61_ce1), - .we1(local_B_61_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_d1), - .q1(local_B_61_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_62_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_62_address0), - .ce0(local_B_62_ce0), - .we0(local_B_62_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_d0), - .q0(local_B_62_q0), - .address1(local_B_62_address1), - .ce1(local_B_62_ce1), - .we1(local_B_62_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_d1), - .q1(local_B_62_q1) -); - -PEG_Bmtx_local_B_RAM_AUTO_1R1W #( - .DataWidth( 32 ), - .AddressRange( 1024 ), - .AddressWidth( 10 )) -local_B_63_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_B_63_address0), - .ce0(local_B_63_ce0), - .we0(local_B_63_we0), - .d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_d0), - .q0(local_B_63_q0), - .address1(local_B_63_address1), - .ce1(local_B_63_ce1), - .we1(local_B_63_we1), - .d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_d1), - .q1(local_B_63_q1) -); - -PEG_Bmtx_PEG_Bmtx_Pipeline_read_B grp_PEG_Bmtx_Pipeline_read_B_fu_675( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_start), - .ap_done(grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_done), - .ap_idle(grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_idle), - .ap_ready(grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_ready), - .local_B_63_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_address0), - .local_B_63_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_ce0), - .local_B_63_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_we0), - .local_B_63_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_d0), - .local_B_63_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_address1), - .local_B_63_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_ce1), - .local_B_63_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_we1), - .local_B_63_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_d1), - .local_B_62_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_address0), - .local_B_62_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_ce0), - .local_B_62_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_we0), - .local_B_62_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_d0), - .local_B_62_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_address1), - .local_B_62_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_ce1), - .local_B_62_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_we1), - .local_B_62_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_d1), - .local_B_61_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_address0), - .local_B_61_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_ce0), - .local_B_61_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_we0), - .local_B_61_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_d0), - .local_B_61_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_address1), - .local_B_61_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_ce1), - .local_B_61_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_we1), - .local_B_61_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_d1), - .local_B_60_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_address0), - .local_B_60_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_ce0), - .local_B_60_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_we0), - .local_B_60_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_d0), - .local_B_60_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_address1), - .local_B_60_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_ce1), - .local_B_60_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_we1), - .local_B_60_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_d1), - .local_B_59_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_address0), - .local_B_59_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_ce0), - .local_B_59_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_we0), - .local_B_59_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_d0), - .local_B_59_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_address1), - .local_B_59_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_ce1), - .local_B_59_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_we1), - .local_B_59_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_d1), - .local_B_58_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_address0), - .local_B_58_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_ce0), - .local_B_58_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_we0), - .local_B_58_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_d0), - .local_B_58_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_address1), - .local_B_58_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_ce1), - .local_B_58_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_we1), - .local_B_58_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_d1), - .local_B_57_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_address0), - .local_B_57_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_ce0), - .local_B_57_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_we0), - .local_B_57_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_d0), - .local_B_57_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_address1), - .local_B_57_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_ce1), - .local_B_57_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_we1), - .local_B_57_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_d1), - .local_B_56_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_address0), - .local_B_56_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_ce0), - .local_B_56_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_we0), - .local_B_56_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_d0), - .local_B_56_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_address1), - .local_B_56_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_ce1), - .local_B_56_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_we1), - .local_B_56_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_d1), - .local_B_55_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_address0), - .local_B_55_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_ce0), - .local_B_55_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_we0), - .local_B_55_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_d0), - .local_B_55_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_address1), - .local_B_55_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_ce1), - .local_B_55_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_we1), - .local_B_55_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_d1), - .local_B_54_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_address0), - .local_B_54_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_ce0), - .local_B_54_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_we0), - .local_B_54_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_d0), - .local_B_54_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_address1), - .local_B_54_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_ce1), - .local_B_54_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_we1), - .local_B_54_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_d1), - .local_B_53_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_address0), - .local_B_53_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_ce0), - .local_B_53_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_we0), - .local_B_53_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_d0), - .local_B_53_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_address1), - .local_B_53_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_ce1), - .local_B_53_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_we1), - .local_B_53_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_d1), - .local_B_52_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_address0), - .local_B_52_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_ce0), - .local_B_52_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_we0), - .local_B_52_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_d0), - .local_B_52_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_address1), - .local_B_52_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_ce1), - .local_B_52_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_we1), - .local_B_52_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_d1), - .local_B_51_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_address0), - .local_B_51_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_ce0), - .local_B_51_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_we0), - .local_B_51_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_d0), - .local_B_51_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_address1), - .local_B_51_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_ce1), - .local_B_51_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_we1), - .local_B_51_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_d1), - .local_B_50_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_address0), - .local_B_50_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_ce0), - .local_B_50_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_we0), - .local_B_50_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_d0), - .local_B_50_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_address1), - .local_B_50_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_ce1), - .local_B_50_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_we1), - .local_B_50_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_d1), - .local_B_49_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_address0), - .local_B_49_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_ce0), - .local_B_49_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_we0), - .local_B_49_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_d0), - .local_B_49_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_address1), - .local_B_49_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_ce1), - .local_B_49_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_we1), - .local_B_49_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_d1), - .local_B_48_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_address0), - .local_B_48_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_ce0), - .local_B_48_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_we0), - .local_B_48_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_d0), - .local_B_48_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_address1), - .local_B_48_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_ce1), - .local_B_48_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_we1), - .local_B_48_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_d1), - .local_B_47_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_address0), - .local_B_47_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_ce0), - .local_B_47_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_we0), - .local_B_47_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_d0), - .local_B_47_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_address1), - .local_B_47_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_ce1), - .local_B_47_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_we1), - .local_B_47_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_d1), - .local_B_46_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_address0), - .local_B_46_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_ce0), - .local_B_46_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_we0), - .local_B_46_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_d0), - .local_B_46_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_address1), - .local_B_46_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_ce1), - .local_B_46_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_we1), - .local_B_46_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_d1), - .local_B_45_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_address0), - .local_B_45_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_ce0), - .local_B_45_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_we0), - .local_B_45_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_d0), - .local_B_45_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_address1), - .local_B_45_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_ce1), - .local_B_45_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_we1), - .local_B_45_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_d1), - .local_B_44_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_address0), - .local_B_44_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_ce0), - .local_B_44_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_we0), - .local_B_44_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_d0), - .local_B_44_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_address1), - .local_B_44_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_ce1), - .local_B_44_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_we1), - .local_B_44_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_d1), - .local_B_43_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_address0), - .local_B_43_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_ce0), - .local_B_43_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_we0), - .local_B_43_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_d0), - .local_B_43_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_address1), - .local_B_43_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_ce1), - .local_B_43_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_we1), - .local_B_43_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_d1), - .local_B_42_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_address0), - .local_B_42_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_ce0), - .local_B_42_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_we0), - .local_B_42_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_d0), - .local_B_42_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_address1), - .local_B_42_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_ce1), - .local_B_42_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_we1), - .local_B_42_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_d1), - .local_B_41_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_address0), - .local_B_41_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_ce0), - .local_B_41_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_we0), - .local_B_41_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_d0), - .local_B_41_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_address1), - .local_B_41_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_ce1), - .local_B_41_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_we1), - .local_B_41_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_d1), - .local_B_40_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_address0), - .local_B_40_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_ce0), - .local_B_40_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_we0), - .local_B_40_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_d0), - .local_B_40_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_address1), - .local_B_40_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_ce1), - .local_B_40_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_we1), - .local_B_40_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_d1), - .local_B_39_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_address0), - .local_B_39_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_ce0), - .local_B_39_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_we0), - .local_B_39_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_d0), - .local_B_39_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_address1), - .local_B_39_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_ce1), - .local_B_39_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_we1), - .local_B_39_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_d1), - .local_B_38_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_address0), - .local_B_38_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_ce0), - .local_B_38_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_we0), - .local_B_38_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_d0), - .local_B_38_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_address1), - .local_B_38_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_ce1), - .local_B_38_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_we1), - .local_B_38_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_d1), - .local_B_37_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_address0), - .local_B_37_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_ce0), - .local_B_37_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_we0), - .local_B_37_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_d0), - .local_B_37_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_address1), - .local_B_37_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_ce1), - .local_B_37_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_we1), - .local_B_37_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_d1), - .local_B_36_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_address0), - .local_B_36_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_ce0), - .local_B_36_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_we0), - .local_B_36_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_d0), - .local_B_36_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_address1), - .local_B_36_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_ce1), - .local_B_36_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_we1), - .local_B_36_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_d1), - .local_B_35_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_address0), - .local_B_35_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_ce0), - .local_B_35_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_we0), - .local_B_35_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_d0), - .local_B_35_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_address1), - .local_B_35_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_ce1), - .local_B_35_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_we1), - .local_B_35_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_d1), - .local_B_34_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_address0), - .local_B_34_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_ce0), - .local_B_34_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_we0), - .local_B_34_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_d0), - .local_B_34_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_address1), - .local_B_34_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_ce1), - .local_B_34_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_we1), - .local_B_34_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_d1), - .local_B_33_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_address0), - .local_B_33_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_ce0), - .local_B_33_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_we0), - .local_B_33_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_d0), - .local_B_33_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_address1), - .local_B_33_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_ce1), - .local_B_33_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_we1), - .local_B_33_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_d1), - .local_B_32_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_address0), - .local_B_32_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_ce0), - .local_B_32_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_we0), - .local_B_32_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_d0), - .local_B_32_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_address1), - .local_B_32_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_ce1), - .local_B_32_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_we1), - .local_B_32_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_d1), - .local_B_31_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_address0), - .local_B_31_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_ce0), - .local_B_31_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_we0), - .local_B_31_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_d0), - .local_B_31_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_address1), - .local_B_31_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_ce1), - .local_B_31_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_we1), - .local_B_31_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_d1), - .local_B_30_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_address0), - .local_B_30_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_ce0), - .local_B_30_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_we0), - .local_B_30_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_d0), - .local_B_30_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_address1), - .local_B_30_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_ce1), - .local_B_30_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_we1), - .local_B_30_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_d1), - .local_B_29_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_address0), - .local_B_29_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_ce0), - .local_B_29_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_we0), - .local_B_29_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_d0), - .local_B_29_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_address1), - .local_B_29_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_ce1), - .local_B_29_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_we1), - .local_B_29_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_d1), - .local_B_28_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_address0), - .local_B_28_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_ce0), - .local_B_28_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_we0), - .local_B_28_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_d0), - .local_B_28_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_address1), - .local_B_28_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_ce1), - .local_B_28_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_we1), - .local_B_28_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_d1), - .local_B_27_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_address0), - .local_B_27_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_ce0), - .local_B_27_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_we0), - .local_B_27_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_d0), - .local_B_27_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_address1), - .local_B_27_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_ce1), - .local_B_27_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_we1), - .local_B_27_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_d1), - .local_B_26_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_address0), - .local_B_26_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_ce0), - .local_B_26_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_we0), - .local_B_26_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_d0), - .local_B_26_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_address1), - .local_B_26_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_ce1), - .local_B_26_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_we1), - .local_B_26_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_d1), - .local_B_25_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_address0), - .local_B_25_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_ce0), - .local_B_25_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_we0), - .local_B_25_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_d0), - .local_B_25_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_address1), - .local_B_25_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_ce1), - .local_B_25_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_we1), - .local_B_25_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_d1), - .local_B_24_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_address0), - .local_B_24_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_ce0), - .local_B_24_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_we0), - .local_B_24_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_d0), - .local_B_24_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_address1), - .local_B_24_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_ce1), - .local_B_24_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_we1), - .local_B_24_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_d1), - .local_B_23_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_address0), - .local_B_23_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_ce0), - .local_B_23_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_we0), - .local_B_23_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_d0), - .local_B_23_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_address1), - .local_B_23_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_ce1), - .local_B_23_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_we1), - .local_B_23_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_d1), - .local_B_22_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_address0), - .local_B_22_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_ce0), - .local_B_22_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_we0), - .local_B_22_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_d0), - .local_B_22_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_address1), - .local_B_22_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_ce1), - .local_B_22_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_we1), - .local_B_22_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_d1), - .local_B_21_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_address0), - .local_B_21_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_ce0), - .local_B_21_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_we0), - .local_B_21_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_d0), - .local_B_21_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_address1), - .local_B_21_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_ce1), - .local_B_21_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_we1), - .local_B_21_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_d1), - .local_B_20_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_address0), - .local_B_20_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_ce0), - .local_B_20_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_we0), - .local_B_20_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_d0), - .local_B_20_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_address1), - .local_B_20_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_ce1), - .local_B_20_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_we1), - .local_B_20_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_d1), - .local_B_19_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_address0), - .local_B_19_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_ce0), - .local_B_19_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_we0), - .local_B_19_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_d0), - .local_B_19_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_address1), - .local_B_19_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_ce1), - .local_B_19_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_we1), - .local_B_19_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_d1), - .local_B_18_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_address0), - .local_B_18_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_ce0), - .local_B_18_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_we0), - .local_B_18_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_d0), - .local_B_18_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_address1), - .local_B_18_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_ce1), - .local_B_18_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_we1), - .local_B_18_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_d1), - .local_B_17_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_address0), - .local_B_17_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_ce0), - .local_B_17_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_we0), - .local_B_17_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_d0), - .local_B_17_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_address1), - .local_B_17_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_ce1), - .local_B_17_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_we1), - .local_B_17_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_d1), - .local_B_16_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_address0), - .local_B_16_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_ce0), - .local_B_16_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_we0), - .local_B_16_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_d0), - .local_B_16_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_address1), - .local_B_16_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_ce1), - .local_B_16_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_we1), - .local_B_16_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_d1), - .local_B_15_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_address0), - .local_B_15_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_ce0), - .local_B_15_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_we0), - .local_B_15_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_d0), - .local_B_15_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_address1), - .local_B_15_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_ce1), - .local_B_15_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_we1), - .local_B_15_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_d1), - .local_B_14_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_address0), - .local_B_14_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_ce0), - .local_B_14_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_we0), - .local_B_14_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_d0), - .local_B_14_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_address1), - .local_B_14_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_ce1), - .local_B_14_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_we1), - .local_B_14_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_d1), - .local_B_13_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_address0), - .local_B_13_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_ce0), - .local_B_13_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_we0), - .local_B_13_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_d0), - .local_B_13_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_address1), - .local_B_13_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_ce1), - .local_B_13_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_we1), - .local_B_13_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_d1), - .local_B_12_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_address0), - .local_B_12_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_ce0), - .local_B_12_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_we0), - .local_B_12_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_d0), - .local_B_12_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_address1), - .local_B_12_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_ce1), - .local_B_12_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_we1), - .local_B_12_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_d1), - .local_B_11_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_address0), - .local_B_11_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_ce0), - .local_B_11_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_we0), - .local_B_11_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_d0), - .local_B_11_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_address1), - .local_B_11_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_ce1), - .local_B_11_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_we1), - .local_B_11_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_d1), - .local_B_10_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_address0), - .local_B_10_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_ce0), - .local_B_10_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_we0), - .local_B_10_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_d0), - .local_B_10_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_address1), - .local_B_10_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_ce1), - .local_B_10_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_we1), - .local_B_10_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_d1), - .local_B_9_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_address0), - .local_B_9_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_ce0), - .local_B_9_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_we0), - .local_B_9_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_d0), - .local_B_9_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_address1), - .local_B_9_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_ce1), - .local_B_9_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_we1), - .local_B_9_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_d1), - .local_B_8_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_address0), - .local_B_8_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_ce0), - .local_B_8_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_we0), - .local_B_8_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_d0), - .local_B_8_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_address1), - .local_B_8_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_ce1), - .local_B_8_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_we1), - .local_B_8_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_d1), - .local_B_7_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_address0), - .local_B_7_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_ce0), - .local_B_7_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_we0), - .local_B_7_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_d0), - .local_B_7_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_address1), - .local_B_7_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_ce1), - .local_B_7_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_we1), - .local_B_7_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_d1), - .local_B_6_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_address0), - .local_B_6_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_ce0), - .local_B_6_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_we0), - .local_B_6_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_d0), - .local_B_6_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_address1), - .local_B_6_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_ce1), - .local_B_6_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_we1), - .local_B_6_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_d1), - .local_B_5_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_address0), - .local_B_5_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_ce0), - .local_B_5_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_we0), - .local_B_5_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_d0), - .local_B_5_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_address1), - .local_B_5_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_ce1), - .local_B_5_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_we1), - .local_B_5_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_d1), - .local_B_4_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_address0), - .local_B_4_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_ce0), - .local_B_4_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_we0), - .local_B_4_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_d0), - .local_B_4_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_address1), - .local_B_4_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_ce1), - .local_B_4_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_we1), - .local_B_4_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_d1), - .local_B_3_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_address0), - .local_B_3_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_ce0), - .local_B_3_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_we0), - .local_B_3_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_d0), - .local_B_3_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_address1), - .local_B_3_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_ce1), - .local_B_3_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_we1), - .local_B_3_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_d1), - .local_B_2_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_address0), - .local_B_2_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_ce0), - .local_B_2_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_we0), - .local_B_2_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_d0), - .local_B_2_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_address1), - .local_B_2_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_ce1), - .local_B_2_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_we1), - .local_B_2_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_d1), - .local_B_1_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_address0), - .local_B_1_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_ce0), - .local_B_1_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_we0), - .local_B_1_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_d0), - .local_B_1_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_address1), - .local_B_1_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_ce1), - .local_B_1_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_we1), - .local_B_1_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_d1), - .local_B_address0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_address0), - .local_B_ce0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_ce0), - .local_B_we0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_we0), - .local_B_d0(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_d0), - .local_B_address1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_address1), - .local_B_ce1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_ce1), - .local_B_we1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_we1), - .local_B_d1(grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_d1), - .sub(sub_reg_1126), - .fifo_B_in_0_dout(fifo_B_in_0_dout), - .fifo_B_in_0_empty_n(fifo_B_in_0_empty_n), - .fifo_B_in_0_read(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_0_read), - .fifo_B_out_0_din(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_0_din), - .fifo_B_out_0_full_n(fifo_B_out_0_full_n), - .fifo_B_out_0_write(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_0_write), - .fifo_B_in_1_dout(fifo_B_in_1_dout), - .fifo_B_in_1_empty_n(fifo_B_in_1_empty_n), - .fifo_B_in_1_read(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_1_read), - .fifo_B_out_1_din(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_1_din), - .fifo_B_out_1_full_n(fifo_B_out_1_full_n), - .fifo_B_out_1_write(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_1_write), - .fifo_B_in_2_dout(fifo_B_in_2_dout), - .fifo_B_in_2_empty_n(fifo_B_in_2_empty_n), - .fifo_B_in_2_read(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_2_read), - .fifo_B_out_2_din(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_2_din), - .fifo_B_out_2_full_n(fifo_B_out_2_full_n), - .fifo_B_out_2_write(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_2_write), - .fifo_B_in_3_dout(fifo_B_in_3_dout), - .fifo_B_in_3_empty_n(fifo_B_in_3_empty_n), - .fifo_B_in_3_read(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_3_read), - .fifo_B_out_3_din(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_3_din), - .fifo_B_out_3_full_n(fifo_B_out_3_full_n), - .fifo_B_out_3_write(grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_3_write) -); - -PEG_Bmtx_PEG_Bmtx_Pipeline_computation grp_PEG_Bmtx_Pipeline_computation_fu_760( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_start), - .ap_done(grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_done), - .ap_idle(grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_idle), - .ap_ready(grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_ready), - .fifo_aBvec_0_din(grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_0_din), - .fifo_aBvec_0_full_n(fifo_aBvec_0_full_n), - .fifo_aBvec_0_write(grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_0_write), - .fifo_aBvec_1_din(grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_1_din), - .fifo_aBvec_1_full_n(fifo_aBvec_1_full_n), - .fifo_aBvec_1_write(grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_1_write), - .fifo_aBvec_2_din(grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_2_din), - .fifo_aBvec_2_full_n(fifo_aBvec_2_full_n), - .fifo_aBvec_2_write(grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_2_write), - .fifo_aBvec_3_din(grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_3_din), - .fifo_aBvec_3_full_n(fifo_aBvec_3_full_n), - .fifo_aBvec_3_write(grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_3_write), - .start_32_3(start_32_3_reg_665), - .end_32(end_32_reg_1131), - .fifo_A_s_dout(fifo_A_s_dout), - .fifo_A_s_empty_n(fifo_A_s_empty_n), - .fifo_A_s_read(grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_A_s_read), - .local_B_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_address0), - .local_B_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_ce0), - .local_B_q0(local_B_q0), - .local_B_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_address1), - .local_B_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_ce1), - .local_B_q1(local_B_q1), - .local_B_1_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_address0), - .local_B_1_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_ce0), - .local_B_1_q0(local_B_1_q0), - .local_B_1_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_address1), - .local_B_1_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_ce1), - .local_B_1_q1(local_B_1_q1), - .local_B_2_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_address0), - .local_B_2_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_ce0), - .local_B_2_q0(local_B_2_q0), - .local_B_2_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_address1), - .local_B_2_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_ce1), - .local_B_2_q1(local_B_2_q1), - .local_B_3_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_address0), - .local_B_3_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_ce0), - .local_B_3_q0(local_B_3_q0), - .local_B_3_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_address1), - .local_B_3_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_ce1), - .local_B_3_q1(local_B_3_q1), - .local_B_4_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_address0), - .local_B_4_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_ce0), - .local_B_4_q0(local_B_4_q0), - .local_B_4_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_address1), - .local_B_4_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_ce1), - .local_B_4_q1(local_B_4_q1), - .local_B_5_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_address0), - .local_B_5_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_ce0), - .local_B_5_q0(local_B_5_q0), - .local_B_5_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_address1), - .local_B_5_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_ce1), - .local_B_5_q1(local_B_5_q1), - .local_B_6_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_address0), - .local_B_6_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_ce0), - .local_B_6_q0(local_B_6_q0), - .local_B_6_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_address1), - .local_B_6_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_ce1), - .local_B_6_q1(local_B_6_q1), - .local_B_7_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_address0), - .local_B_7_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_ce0), - .local_B_7_q0(local_B_7_q0), - .local_B_7_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_address1), - .local_B_7_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_ce1), - .local_B_7_q1(local_B_7_q1), - .local_B_8_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_address0), - .local_B_8_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_ce0), - .local_B_8_q0(local_B_8_q0), - .local_B_8_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_address1), - .local_B_8_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_ce1), - .local_B_8_q1(local_B_8_q1), - .local_B_9_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_address0), - .local_B_9_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_ce0), - .local_B_9_q0(local_B_9_q0), - .local_B_9_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_address1), - .local_B_9_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_ce1), - .local_B_9_q1(local_B_9_q1), - .local_B_10_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_address0), - .local_B_10_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_ce0), - .local_B_10_q0(local_B_10_q0), - .local_B_10_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_address1), - .local_B_10_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_ce1), - .local_B_10_q1(local_B_10_q1), - .local_B_11_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_address0), - .local_B_11_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_ce0), - .local_B_11_q0(local_B_11_q0), - .local_B_11_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_address1), - .local_B_11_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_ce1), - .local_B_11_q1(local_B_11_q1), - .local_B_12_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_address0), - .local_B_12_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_ce0), - .local_B_12_q0(local_B_12_q0), - .local_B_12_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_address1), - .local_B_12_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_ce1), - .local_B_12_q1(local_B_12_q1), - .local_B_13_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_address0), - .local_B_13_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_ce0), - .local_B_13_q0(local_B_13_q0), - .local_B_13_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_address1), - .local_B_13_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_ce1), - .local_B_13_q1(local_B_13_q1), - .local_B_14_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_address0), - .local_B_14_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_ce0), - .local_B_14_q0(local_B_14_q0), - .local_B_14_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_address1), - .local_B_14_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_ce1), - .local_B_14_q1(local_B_14_q1), - .local_B_15_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_address0), - .local_B_15_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_ce0), - .local_B_15_q0(local_B_15_q0), - .local_B_15_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_address1), - .local_B_15_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_ce1), - .local_B_15_q1(local_B_15_q1), - .local_B_16_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_address0), - .local_B_16_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_ce0), - .local_B_16_q0(local_B_16_q0), - .local_B_16_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_address1), - .local_B_16_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_ce1), - .local_B_16_q1(local_B_16_q1), - .local_B_17_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_address0), - .local_B_17_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_ce0), - .local_B_17_q0(local_B_17_q0), - .local_B_17_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_address1), - .local_B_17_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_ce1), - .local_B_17_q1(local_B_17_q1), - .local_B_18_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_address0), - .local_B_18_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_ce0), - .local_B_18_q0(local_B_18_q0), - .local_B_18_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_address1), - .local_B_18_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_ce1), - .local_B_18_q1(local_B_18_q1), - .local_B_19_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_address0), - .local_B_19_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_ce0), - .local_B_19_q0(local_B_19_q0), - .local_B_19_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_address1), - .local_B_19_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_ce1), - .local_B_19_q1(local_B_19_q1), - .local_B_20_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_address0), - .local_B_20_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_ce0), - .local_B_20_q0(local_B_20_q0), - .local_B_20_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_address1), - .local_B_20_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_ce1), - .local_B_20_q1(local_B_20_q1), - .local_B_21_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_address0), - .local_B_21_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_ce0), - .local_B_21_q0(local_B_21_q0), - .local_B_21_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_address1), - .local_B_21_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_ce1), - .local_B_21_q1(local_B_21_q1), - .local_B_22_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_address0), - .local_B_22_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_ce0), - .local_B_22_q0(local_B_22_q0), - .local_B_22_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_address1), - .local_B_22_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_ce1), - .local_B_22_q1(local_B_22_q1), - .local_B_23_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_address0), - .local_B_23_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_ce0), - .local_B_23_q0(local_B_23_q0), - .local_B_23_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_address1), - .local_B_23_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_ce1), - .local_B_23_q1(local_B_23_q1), - .local_B_24_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_address0), - .local_B_24_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_ce0), - .local_B_24_q0(local_B_24_q0), - .local_B_24_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_address1), - .local_B_24_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_ce1), - .local_B_24_q1(local_B_24_q1), - .local_B_25_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_address0), - .local_B_25_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_ce0), - .local_B_25_q0(local_B_25_q0), - .local_B_25_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_address1), - .local_B_25_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_ce1), - .local_B_25_q1(local_B_25_q1), - .local_B_26_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_address0), - .local_B_26_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_ce0), - .local_B_26_q0(local_B_26_q0), - .local_B_26_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_address1), - .local_B_26_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_ce1), - .local_B_26_q1(local_B_26_q1), - .local_B_27_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_address0), - .local_B_27_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_ce0), - .local_B_27_q0(local_B_27_q0), - .local_B_27_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_address1), - .local_B_27_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_ce1), - .local_B_27_q1(local_B_27_q1), - .local_B_28_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_address0), - .local_B_28_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_ce0), - .local_B_28_q0(local_B_28_q0), - .local_B_28_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_address1), - .local_B_28_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_ce1), - .local_B_28_q1(local_B_28_q1), - .local_B_29_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_address0), - .local_B_29_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_ce0), - .local_B_29_q0(local_B_29_q0), - .local_B_29_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_address1), - .local_B_29_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_ce1), - .local_B_29_q1(local_B_29_q1), - .local_B_30_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_address0), - .local_B_30_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_ce0), - .local_B_30_q0(local_B_30_q0), - .local_B_30_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_address1), - .local_B_30_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_ce1), - .local_B_30_q1(local_B_30_q1), - .local_B_31_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_address0), - .local_B_31_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_ce0), - .local_B_31_q0(local_B_31_q0), - .local_B_31_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_address1), - .local_B_31_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_ce1), - .local_B_31_q1(local_B_31_q1), - .local_B_32_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_address0), - .local_B_32_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_ce0), - .local_B_32_q0(local_B_32_q0), - .local_B_32_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_address1), - .local_B_32_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_ce1), - .local_B_32_q1(local_B_32_q1), - .local_B_33_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_address0), - .local_B_33_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_ce0), - .local_B_33_q0(local_B_33_q0), - .local_B_33_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_address1), - .local_B_33_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_ce1), - .local_B_33_q1(local_B_33_q1), - .local_B_34_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_address0), - .local_B_34_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_ce0), - .local_B_34_q0(local_B_34_q0), - .local_B_34_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_address1), - .local_B_34_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_ce1), - .local_B_34_q1(local_B_34_q1), - .local_B_35_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_address0), - .local_B_35_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_ce0), - .local_B_35_q0(local_B_35_q0), - .local_B_35_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_address1), - .local_B_35_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_ce1), - .local_B_35_q1(local_B_35_q1), - .local_B_36_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_address0), - .local_B_36_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_ce0), - .local_B_36_q0(local_B_36_q0), - .local_B_36_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_address1), - .local_B_36_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_ce1), - .local_B_36_q1(local_B_36_q1), - .local_B_37_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_address0), - .local_B_37_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_ce0), - .local_B_37_q0(local_B_37_q0), - .local_B_37_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_address1), - .local_B_37_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_ce1), - .local_B_37_q1(local_B_37_q1), - .local_B_38_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_address0), - .local_B_38_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_ce0), - .local_B_38_q0(local_B_38_q0), - .local_B_38_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_address1), - .local_B_38_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_ce1), - .local_B_38_q1(local_B_38_q1), - .local_B_39_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_address0), - .local_B_39_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_ce0), - .local_B_39_q0(local_B_39_q0), - .local_B_39_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_address1), - .local_B_39_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_ce1), - .local_B_39_q1(local_B_39_q1), - .local_B_40_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_address0), - .local_B_40_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_ce0), - .local_B_40_q0(local_B_40_q0), - .local_B_40_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_address1), - .local_B_40_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_ce1), - .local_B_40_q1(local_B_40_q1), - .local_B_41_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_address0), - .local_B_41_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_ce0), - .local_B_41_q0(local_B_41_q0), - .local_B_41_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_address1), - .local_B_41_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_ce1), - .local_B_41_q1(local_B_41_q1), - .local_B_42_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_address0), - .local_B_42_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_ce0), - .local_B_42_q0(local_B_42_q0), - .local_B_42_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_address1), - .local_B_42_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_ce1), - .local_B_42_q1(local_B_42_q1), - .local_B_43_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_address0), - .local_B_43_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_ce0), - .local_B_43_q0(local_B_43_q0), - .local_B_43_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_address1), - .local_B_43_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_ce1), - .local_B_43_q1(local_B_43_q1), - .local_B_44_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_address0), - .local_B_44_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_ce0), - .local_B_44_q0(local_B_44_q0), - .local_B_44_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_address1), - .local_B_44_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_ce1), - .local_B_44_q1(local_B_44_q1), - .local_B_45_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_address0), - .local_B_45_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_ce0), - .local_B_45_q0(local_B_45_q0), - .local_B_45_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_address1), - .local_B_45_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_ce1), - .local_B_45_q1(local_B_45_q1), - .local_B_46_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_address0), - .local_B_46_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_ce0), - .local_B_46_q0(local_B_46_q0), - .local_B_46_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_address1), - .local_B_46_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_ce1), - .local_B_46_q1(local_B_46_q1), - .local_B_47_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_address0), - .local_B_47_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_ce0), - .local_B_47_q0(local_B_47_q0), - .local_B_47_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_address1), - .local_B_47_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_ce1), - .local_B_47_q1(local_B_47_q1), - .local_B_48_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_address0), - .local_B_48_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_ce0), - .local_B_48_q0(local_B_48_q0), - .local_B_48_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_address1), - .local_B_48_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_ce1), - .local_B_48_q1(local_B_48_q1), - .local_B_49_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_address0), - .local_B_49_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_ce0), - .local_B_49_q0(local_B_49_q0), - .local_B_49_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_address1), - .local_B_49_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_ce1), - .local_B_49_q1(local_B_49_q1), - .local_B_50_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_address0), - .local_B_50_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_ce0), - .local_B_50_q0(local_B_50_q0), - .local_B_50_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_address1), - .local_B_50_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_ce1), - .local_B_50_q1(local_B_50_q1), - .local_B_51_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_address0), - .local_B_51_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_ce0), - .local_B_51_q0(local_B_51_q0), - .local_B_51_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_address1), - .local_B_51_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_ce1), - .local_B_51_q1(local_B_51_q1), - .local_B_52_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_address0), - .local_B_52_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_ce0), - .local_B_52_q0(local_B_52_q0), - .local_B_52_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_address1), - .local_B_52_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_ce1), - .local_B_52_q1(local_B_52_q1), - .local_B_53_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_address0), - .local_B_53_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_ce0), - .local_B_53_q0(local_B_53_q0), - .local_B_53_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_address1), - .local_B_53_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_ce1), - .local_B_53_q1(local_B_53_q1), - .local_B_54_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_address0), - .local_B_54_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_ce0), - .local_B_54_q0(local_B_54_q0), - .local_B_54_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_address1), - .local_B_54_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_ce1), - .local_B_54_q1(local_B_54_q1), - .local_B_55_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_address0), - .local_B_55_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_ce0), - .local_B_55_q0(local_B_55_q0), - .local_B_55_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_address1), - .local_B_55_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_ce1), - .local_B_55_q1(local_B_55_q1), - .local_B_56_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_address0), - .local_B_56_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_ce0), - .local_B_56_q0(local_B_56_q0), - .local_B_56_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_address1), - .local_B_56_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_ce1), - .local_B_56_q1(local_B_56_q1), - .local_B_57_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_address0), - .local_B_57_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_ce0), - .local_B_57_q0(local_B_57_q0), - .local_B_57_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_address1), - .local_B_57_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_ce1), - .local_B_57_q1(local_B_57_q1), - .local_B_58_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_address0), - .local_B_58_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_ce0), - .local_B_58_q0(local_B_58_q0), - .local_B_58_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_address1), - .local_B_58_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_ce1), - .local_B_58_q1(local_B_58_q1), - .local_B_59_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_address0), - .local_B_59_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_ce0), - .local_B_59_q0(local_B_59_q0), - .local_B_59_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_address1), - .local_B_59_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_ce1), - .local_B_59_q1(local_B_59_q1), - .local_B_60_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_address0), - .local_B_60_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_ce0), - .local_B_60_q0(local_B_60_q0), - .local_B_60_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_address1), - .local_B_60_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_ce1), - .local_B_60_q1(local_B_60_q1), - .local_B_61_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_address0), - .local_B_61_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_ce0), - .local_B_61_q0(local_B_61_q0), - .local_B_61_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_address1), - .local_B_61_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_ce1), - .local_B_61_q1(local_B_61_q1), - .local_B_62_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_address0), - .local_B_62_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_ce0), - .local_B_62_q0(local_B_62_q0), - .local_B_62_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_address1), - .local_B_62_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_ce1), - .local_B_62_q1(local_B_62_q1), - .local_B_63_address0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_address0), - .local_B_63_ce0(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_ce0), - .local_B_63_q0(local_B_63_q0), - .local_B_63_address1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_address1), - .local_B_63_ce1(grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_ce1), - .local_B_63_q1(local_B_63_q1) -); - -PEG_Bmtx_mul_mul_16s_14ns_30_4_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 16 ), - .din1_WIDTH( 14 ), - .dout_WIDTH( 30 )) -mul_mul_16s_14ns_30_4_1_U211( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .din0(rp_time_fu_927_p3), - .din1(grp_fu_1056_p1), - .ce(grp_fu_1056_ce), - .dout(grp_fu_1056_p2) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state14)) begin - grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_start_reg <= 1'b1; - end else if ((grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_ready == 1'b1)) begin - grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state11)) begin - grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_start_reg <= 1'b1; - end else if ((grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_ready == 1'b1)) begin - grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_CS_fsm_state15) & (grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_done == 1'b1))) begin - i_reg_654 <= i_1_reg_1121; - end else if ((~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)) & (1'b1 == ap_CS_fsm_state9))) begin - i_reg_654 <= 31'd0; - end -end - -always @ (posedge ap_clk) begin - if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - rp_fu_146 <= 28'd0; - end else if (((icmp_ln276_fu_1010_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state10))) begin - rp_fu_146 <= rp_2_reg_1108; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_CS_fsm_state15) & (grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_done == 1'b1))) begin - start_32_3_reg_665 <= end_32_reg_1131; - end else if ((~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)) & (1'b1 == ap_CS_fsm_state9))) begin - start_32_3_reg_665 <= start_32_fu_992_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - N16_reg_1074 <= {{PE_inst_in_s_dout[31:16]}}; - lshr_ln_reg_1080 <= {{add_ln257_fu_906_p2[16:3]}}; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state1)) begin - NUM_ITE_reg_1069 <= NUM_ITE_fu_841_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state13)) begin - end_32_reg_1131 <= end_32_fu_1042_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state10)) begin - i_1_reg_1121 <= i_1_fu_1015_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state8)) begin - rp_2_reg_1108 <= rp_2_fu_986_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state7)) begin - rp_time_N_reg_1095 <= grp_fu_1056_p2; - shr79_reg_1100 <= shr79_fu_970_p1; - end -end - -always @ (posedge ap_clk) begin - if (((icmp_ln276_fu_1010_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state10))) begin - sub_reg_1126 <= sub_fu_1033_p2; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state7) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1)))) begin - PE_inst_in_s_blk_n = PE_inst_in_s_empty_n; - end else begin - PE_inst_in_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n)) & (1'b1 == ap_CS_fsm_state7)) | (~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state3)) | (~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state2)) | (~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin - PE_inst_in_s_read = 1'b1; - end else begin - PE_inst_in_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state7) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1)))) begin - PE_inst_out_blk_n = PE_inst_out_full_n; - end else begin - PE_inst_out_blk_n = 1'b1; - end -end - -always @ (*) begin - if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n)) & (1'b1 == ap_CS_fsm_state7))) begin - PE_inst_out_din = p_11_fu_945_p3; - end else if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state3))) begin - PE_inst_out_din = p_0_fu_882_p3; - end else if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state2))) begin - PE_inst_out_din = p_10_fu_864_p3; - end else if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - PE_inst_out_din = p_s_fu_845_p3; - end else begin - PE_inst_out_din = 'bx; - end -end - -always @ (*) begin - if (((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n)) & (1'b1 == ap_CS_fsm_state7)) | (~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state3)) | (~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state2)) | (~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin - PE_inst_out_write = 1'b1; - end else begin - PE_inst_out_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1)))) begin - PE_inst_to_Cmtx_blk_n = PE_inst_to_Cmtx_full_n; - end else begin - PE_inst_to_Cmtx_blk_n = 1'b1; - end -end - -always @ (*) begin - if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state3))) begin - PE_inst_to_Cmtx_din = p_0_fu_882_p3; - end else if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state2))) begin - PE_inst_to_Cmtx_din = p_10_fu_864_p3; - end else if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - PE_inst_to_Cmtx_din = p_s_fu_845_p3; - end else begin - PE_inst_to_Cmtx_din = 'bx; - end -end - -always @ (*) begin - if (((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state3)) | (~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state2)) | (~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin - PE_inst_to_Cmtx_write = 1'b1; - end else begin - PE_inst_to_Cmtx_write = 1'b0; - end -end - -assign ap_ST_fsm_state10_blk = 1'b0; - -assign ap_ST_fsm_state11_blk = 1'b0; - -always @ (*) begin - if ((grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_done == 1'b0)) begin - ap_ST_fsm_state12_blk = 1'b1; - end else begin - ap_ST_fsm_state12_blk = 1'b0; - end -end - -always @ (*) begin - if (((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0))) begin - ap_ST_fsm_state13_blk = 1'b1; - end else begin - ap_ST_fsm_state13_blk = 1'b0; - end -end - -assign ap_ST_fsm_state14_blk = 1'b0; - -always @ (*) begin - if ((grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_done == 1'b0)) begin - ap_ST_fsm_state15_blk = 1'b1; - end else begin - ap_ST_fsm_state15_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n) | (ap_start == 1'b0))) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n))) begin - ap_ST_fsm_state2_blk = 1'b1; - end else begin - ap_ST_fsm_state2_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n))) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -assign ap_ST_fsm_state4_blk = 1'b0; - -assign ap_ST_fsm_state5_blk = 1'b0; - -assign ap_ST_fsm_state6_blk = 1'b0; - -always @ (*) begin - if (((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n))) begin - ap_ST_fsm_state7_blk = 1'b1; - end else begin - ap_ST_fsm_state7_blk = 1'b0; - end -end - -assign ap_ST_fsm_state8_blk = 1'b0; - -always @ (*) begin - if (((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0))) begin - ap_ST_fsm_state9_blk = 1'b1; - end else begin - ap_ST_fsm_state9_blk = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln259_fu_981_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state8))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln259_fu_981_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state8))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - fifo_A_s_read = grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_A_s_read; - end else begin - fifo_A_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_B_in_0_read = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_0_read; - end else begin - fifo_B_in_0_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_B_in_1_read = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_1_read; - end else begin - fifo_B_in_1_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_B_in_2_read = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_2_read; - end else begin - fifo_B_in_2_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_B_in_3_read = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_in_3_read; - end else begin - fifo_B_in_3_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_B_out_0_write = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_0_write; - end else begin - fifo_B_out_0_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_B_out_1_write = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_1_write; - end else begin - fifo_B_out_1_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_B_out_2_write = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_2_write; - end else begin - fifo_B_out_2_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_B_out_3_write = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_3_write; - end else begin - fifo_B_out_3_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - fifo_aBvec_0_write = grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_0_write; - end else begin - fifo_aBvec_0_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - fifo_aBvec_1_write = grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_1_write; - end else begin - fifo_aBvec_1_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - fifo_aBvec_2_write = grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_2_write; - end else begin - fifo_aBvec_2_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - fifo_aBvec_3_write = grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_3_write; - end else begin - fifo_aBvec_3_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state13) | (1'b1 == ap_CS_fsm_state9))) begin - fifo_inst_in_s_blk_n = fifo_inst_in_s_empty_n; - end else begin - fifo_inst_in_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)) & (1'b1 == ap_CS_fsm_state13)) | (~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)) & (1'b1 == ap_CS_fsm_state9)))) begin - fifo_inst_in_s_read = 1'b1; - end else begin - fifo_inst_in_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state13) | (1'b1 == ap_CS_fsm_state9))) begin - fifo_inst_out_blk_n = fifo_inst_out_full_n; - end else begin - fifo_inst_out_blk_n = 1'b1; - end -end - -always @ (*) begin - if ((1'b1 == ap_condition_2077)) begin - if ((1'b1 == ap_CS_fsm_state13)) begin - fifo_inst_out_din = tmp_11_fu_1046_p3; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - fifo_inst_out_din = tmp_9_fu_996_p3; - end else begin - fifo_inst_out_din = 'bx; - end - end else begin - fifo_inst_out_din = 'bx; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state13) | (1'b1 == ap_CS_fsm_state9))) begin - fifo_inst_out_to_Cmtx_blk_n = fifo_inst_out_to_Cmtx_full_n; - end else begin - fifo_inst_out_to_Cmtx_blk_n = 1'b1; - end -end - -always @ (*) begin - if ((1'b1 == ap_condition_2077)) begin - if ((1'b1 == ap_CS_fsm_state13)) begin - fifo_inst_out_to_Cmtx_din = tmp_11_fu_1046_p3; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - fifo_inst_out_to_Cmtx_din = tmp_9_fu_996_p3; - end else begin - fifo_inst_out_to_Cmtx_din = 'bx; - end - end else begin - fifo_inst_out_to_Cmtx_din = 'bx; - end -end - -always @ (*) begin - if (((~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)) & (1'b1 == ap_CS_fsm_state13)) | (~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)) & (1'b1 == ap_CS_fsm_state9)))) begin - fifo_inst_out_to_Cmtx_write = 1'b1; - end else begin - fifo_inst_out_to_Cmtx_write = 1'b0; - end -end - -always @ (*) begin - if (((~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)) & (1'b1 == ap_CS_fsm_state13)) | (~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)) & (1'b1 == ap_CS_fsm_state9)))) begin - fifo_inst_out_write = 1'b1; - end else begin - fifo_inst_out_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state5) | (1'b1 == ap_CS_fsm_state4) | (~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n)) & (1'b1 == ap_CS_fsm_state7)))) begin - grp_fu_1056_ce = 1'b1; - end else begin - grp_fu_1056_ce = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_10_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_10_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_address0; - end else begin - local_B_10_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_10_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_10_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_address1; - end else begin - local_B_10_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_10_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_10_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_ce0; - end else begin - local_B_10_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_10_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_10_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_10_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_ce1; - end else begin - local_B_10_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_10_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_we0; - end else begin - local_B_10_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_10_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_10_we1; - end else begin - local_B_10_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_11_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_11_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_address0; - end else begin - local_B_11_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_11_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_11_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_address1; - end else begin - local_B_11_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_11_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_11_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_ce0; - end else begin - local_B_11_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_11_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_11_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_11_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_ce1; - end else begin - local_B_11_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_11_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_we0; - end else begin - local_B_11_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_11_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_11_we1; - end else begin - local_B_11_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_12_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_12_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_address0; - end else begin - local_B_12_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_12_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_12_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_address1; - end else begin - local_B_12_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_12_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_12_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_ce0; - end else begin - local_B_12_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_12_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_12_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_12_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_ce1; - end else begin - local_B_12_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_12_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_we0; - end else begin - local_B_12_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_12_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_12_we1; - end else begin - local_B_12_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_13_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_13_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_address0; - end else begin - local_B_13_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_13_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_13_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_address1; - end else begin - local_B_13_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_13_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_13_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_ce0; - end else begin - local_B_13_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_13_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_13_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_13_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_ce1; - end else begin - local_B_13_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_13_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_we0; - end else begin - local_B_13_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_13_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_13_we1; - end else begin - local_B_13_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_14_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_14_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_address0; - end else begin - local_B_14_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_14_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_14_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_address1; - end else begin - local_B_14_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_14_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_14_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_ce0; - end else begin - local_B_14_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_14_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_14_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_14_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_ce1; - end else begin - local_B_14_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_14_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_we0; - end else begin - local_B_14_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_14_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_14_we1; - end else begin - local_B_14_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_15_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_15_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_address0; - end else begin - local_B_15_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_15_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_15_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_address1; - end else begin - local_B_15_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_15_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_15_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_ce0; - end else begin - local_B_15_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_15_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_15_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_15_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_ce1; - end else begin - local_B_15_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_15_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_we0; - end else begin - local_B_15_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_15_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_15_we1; - end else begin - local_B_15_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_16_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_16_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_address0; - end else begin - local_B_16_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_16_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_16_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_address1; - end else begin - local_B_16_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_16_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_16_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_ce0; - end else begin - local_B_16_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_16_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_16_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_16_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_ce1; - end else begin - local_B_16_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_16_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_we0; - end else begin - local_B_16_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_16_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_16_we1; - end else begin - local_B_16_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_17_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_17_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_address0; - end else begin - local_B_17_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_17_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_17_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_address1; - end else begin - local_B_17_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_17_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_17_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_ce0; - end else begin - local_B_17_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_17_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_17_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_17_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_ce1; - end else begin - local_B_17_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_17_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_we0; - end else begin - local_B_17_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_17_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_17_we1; - end else begin - local_B_17_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_18_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_18_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_address0; - end else begin - local_B_18_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_18_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_18_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_address1; - end else begin - local_B_18_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_18_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_18_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_ce0; - end else begin - local_B_18_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_18_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_18_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_18_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_ce1; - end else begin - local_B_18_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_18_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_we0; - end else begin - local_B_18_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_18_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_18_we1; - end else begin - local_B_18_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_19_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_19_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_address0; - end else begin - local_B_19_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_19_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_19_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_address1; - end else begin - local_B_19_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_19_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_19_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_ce0; - end else begin - local_B_19_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_19_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_19_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_19_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_ce1; - end else begin - local_B_19_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_19_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_we0; - end else begin - local_B_19_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_19_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_19_we1; - end else begin - local_B_19_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_1_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_1_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_address0; - end else begin - local_B_1_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_1_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_1_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_address1; - end else begin - local_B_1_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_1_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_1_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_ce0; - end else begin - local_B_1_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_1_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_1_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_1_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_ce1; - end else begin - local_B_1_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_1_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_we0; - end else begin - local_B_1_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_1_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_1_we1; - end else begin - local_B_1_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_20_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_20_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_address0; - end else begin - local_B_20_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_20_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_20_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_address1; - end else begin - local_B_20_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_20_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_20_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_ce0; - end else begin - local_B_20_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_20_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_20_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_20_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_ce1; - end else begin - local_B_20_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_20_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_we0; - end else begin - local_B_20_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_20_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_20_we1; - end else begin - local_B_20_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_21_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_21_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_address0; - end else begin - local_B_21_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_21_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_21_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_address1; - end else begin - local_B_21_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_21_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_21_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_ce0; - end else begin - local_B_21_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_21_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_21_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_21_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_ce1; - end else begin - local_B_21_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_21_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_we0; - end else begin - local_B_21_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_21_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_21_we1; - end else begin - local_B_21_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_22_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_22_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_address0; - end else begin - local_B_22_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_22_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_22_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_address1; - end else begin - local_B_22_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_22_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_22_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_ce0; - end else begin - local_B_22_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_22_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_22_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_22_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_ce1; - end else begin - local_B_22_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_22_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_we0; - end else begin - local_B_22_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_22_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_22_we1; - end else begin - local_B_22_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_23_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_23_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_address0; - end else begin - local_B_23_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_23_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_23_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_address1; - end else begin - local_B_23_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_23_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_23_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_ce0; - end else begin - local_B_23_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_23_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_23_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_23_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_ce1; - end else begin - local_B_23_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_23_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_we0; - end else begin - local_B_23_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_23_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_23_we1; - end else begin - local_B_23_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_24_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_24_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_address0; - end else begin - local_B_24_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_24_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_24_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_address1; - end else begin - local_B_24_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_24_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_24_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_ce0; - end else begin - local_B_24_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_24_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_24_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_24_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_ce1; - end else begin - local_B_24_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_24_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_we0; - end else begin - local_B_24_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_24_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_24_we1; - end else begin - local_B_24_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_25_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_25_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_address0; - end else begin - local_B_25_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_25_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_25_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_address1; - end else begin - local_B_25_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_25_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_25_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_ce0; - end else begin - local_B_25_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_25_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_25_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_25_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_ce1; - end else begin - local_B_25_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_25_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_we0; - end else begin - local_B_25_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_25_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_25_we1; - end else begin - local_B_25_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_26_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_26_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_address0; - end else begin - local_B_26_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_26_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_26_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_address1; - end else begin - local_B_26_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_26_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_26_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_ce0; - end else begin - local_B_26_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_26_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_26_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_26_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_ce1; - end else begin - local_B_26_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_26_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_we0; - end else begin - local_B_26_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_26_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_26_we1; - end else begin - local_B_26_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_27_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_27_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_address0; - end else begin - local_B_27_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_27_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_27_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_address1; - end else begin - local_B_27_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_27_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_27_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_ce0; - end else begin - local_B_27_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_27_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_27_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_27_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_ce1; - end else begin - local_B_27_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_27_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_we0; - end else begin - local_B_27_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_27_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_27_we1; - end else begin - local_B_27_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_28_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_28_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_address0; - end else begin - local_B_28_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_28_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_28_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_address1; - end else begin - local_B_28_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_28_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_28_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_ce0; - end else begin - local_B_28_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_28_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_28_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_28_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_ce1; - end else begin - local_B_28_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_28_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_we0; - end else begin - local_B_28_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_28_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_28_we1; - end else begin - local_B_28_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_29_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_29_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_address0; - end else begin - local_B_29_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_29_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_29_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_address1; - end else begin - local_B_29_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_29_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_29_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_ce0; - end else begin - local_B_29_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_29_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_29_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_29_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_ce1; - end else begin - local_B_29_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_29_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_we0; - end else begin - local_B_29_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_29_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_29_we1; - end else begin - local_B_29_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_2_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_2_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_address0; - end else begin - local_B_2_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_2_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_2_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_address1; - end else begin - local_B_2_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_2_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_2_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_ce0; - end else begin - local_B_2_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_2_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_2_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_2_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_ce1; - end else begin - local_B_2_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_2_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_we0; - end else begin - local_B_2_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_2_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_2_we1; - end else begin - local_B_2_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_30_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_30_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_address0; - end else begin - local_B_30_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_30_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_30_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_address1; - end else begin - local_B_30_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_30_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_30_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_ce0; - end else begin - local_B_30_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_30_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_30_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_30_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_ce1; - end else begin - local_B_30_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_30_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_we0; - end else begin - local_B_30_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_30_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_30_we1; - end else begin - local_B_30_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_31_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_31_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_address0; - end else begin - local_B_31_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_31_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_31_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_address1; - end else begin - local_B_31_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_31_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_31_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_ce0; - end else begin - local_B_31_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_31_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_31_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_31_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_ce1; - end else begin - local_B_31_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_31_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_we0; - end else begin - local_B_31_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_31_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_31_we1; - end else begin - local_B_31_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_32_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_32_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_address0; - end else begin - local_B_32_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_32_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_32_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_address1; - end else begin - local_B_32_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_32_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_32_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_ce0; - end else begin - local_B_32_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_32_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_32_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_32_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_ce1; - end else begin - local_B_32_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_32_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_we0; - end else begin - local_B_32_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_32_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_32_we1; - end else begin - local_B_32_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_33_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_33_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_address0; - end else begin - local_B_33_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_33_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_33_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_address1; - end else begin - local_B_33_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_33_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_33_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_ce0; - end else begin - local_B_33_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_33_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_33_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_33_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_ce1; - end else begin - local_B_33_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_33_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_we0; - end else begin - local_B_33_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_33_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_33_we1; - end else begin - local_B_33_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_34_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_34_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_address0; - end else begin - local_B_34_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_34_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_34_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_address1; - end else begin - local_B_34_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_34_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_34_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_ce0; - end else begin - local_B_34_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_34_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_34_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_34_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_ce1; - end else begin - local_B_34_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_34_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_we0; - end else begin - local_B_34_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_34_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_34_we1; - end else begin - local_B_34_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_35_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_35_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_address0; - end else begin - local_B_35_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_35_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_35_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_address1; - end else begin - local_B_35_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_35_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_35_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_ce0; - end else begin - local_B_35_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_35_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_35_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_35_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_ce1; - end else begin - local_B_35_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_35_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_we0; - end else begin - local_B_35_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_35_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_35_we1; - end else begin - local_B_35_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_36_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_36_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_address0; - end else begin - local_B_36_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_36_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_36_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_address1; - end else begin - local_B_36_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_36_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_36_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_ce0; - end else begin - local_B_36_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_36_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_36_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_36_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_ce1; - end else begin - local_B_36_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_36_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_we0; - end else begin - local_B_36_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_36_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_36_we1; - end else begin - local_B_36_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_37_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_37_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_address0; - end else begin - local_B_37_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_37_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_37_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_address1; - end else begin - local_B_37_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_37_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_37_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_ce0; - end else begin - local_B_37_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_37_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_37_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_37_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_ce1; - end else begin - local_B_37_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_37_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_we0; - end else begin - local_B_37_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_37_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_37_we1; - end else begin - local_B_37_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_38_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_38_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_address0; - end else begin - local_B_38_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_38_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_38_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_address1; - end else begin - local_B_38_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_38_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_38_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_ce0; - end else begin - local_B_38_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_38_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_38_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_38_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_ce1; - end else begin - local_B_38_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_38_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_we0; - end else begin - local_B_38_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_38_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_38_we1; - end else begin - local_B_38_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_39_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_39_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_address0; - end else begin - local_B_39_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_39_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_39_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_address1; - end else begin - local_B_39_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_39_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_39_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_ce0; - end else begin - local_B_39_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_39_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_39_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_39_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_ce1; - end else begin - local_B_39_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_39_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_we0; - end else begin - local_B_39_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_39_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_39_we1; - end else begin - local_B_39_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_3_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_3_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_address0; - end else begin - local_B_3_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_3_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_3_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_address1; - end else begin - local_B_3_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_3_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_3_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_ce0; - end else begin - local_B_3_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_3_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_3_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_3_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_ce1; - end else begin - local_B_3_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_3_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_we0; - end else begin - local_B_3_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_3_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_3_we1; - end else begin - local_B_3_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_40_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_40_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_address0; - end else begin - local_B_40_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_40_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_40_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_address1; - end else begin - local_B_40_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_40_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_40_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_ce0; - end else begin - local_B_40_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_40_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_40_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_40_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_ce1; - end else begin - local_B_40_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_40_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_we0; - end else begin - local_B_40_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_40_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_40_we1; - end else begin - local_B_40_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_41_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_41_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_address0; - end else begin - local_B_41_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_41_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_41_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_address1; - end else begin - local_B_41_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_41_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_41_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_ce0; - end else begin - local_B_41_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_41_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_41_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_41_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_ce1; - end else begin - local_B_41_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_41_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_we0; - end else begin - local_B_41_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_41_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_41_we1; - end else begin - local_B_41_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_42_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_42_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_address0; - end else begin - local_B_42_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_42_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_42_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_address1; - end else begin - local_B_42_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_42_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_42_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_ce0; - end else begin - local_B_42_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_42_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_42_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_42_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_ce1; - end else begin - local_B_42_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_42_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_we0; - end else begin - local_B_42_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_42_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_42_we1; - end else begin - local_B_42_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_43_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_43_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_address0; - end else begin - local_B_43_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_43_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_43_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_address1; - end else begin - local_B_43_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_43_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_43_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_ce0; - end else begin - local_B_43_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_43_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_43_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_43_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_ce1; - end else begin - local_B_43_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_43_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_we0; - end else begin - local_B_43_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_43_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_43_we1; - end else begin - local_B_43_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_44_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_44_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_address0; - end else begin - local_B_44_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_44_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_44_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_address1; - end else begin - local_B_44_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_44_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_44_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_ce0; - end else begin - local_B_44_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_44_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_44_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_44_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_ce1; - end else begin - local_B_44_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_44_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_we0; - end else begin - local_B_44_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_44_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_44_we1; - end else begin - local_B_44_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_45_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_45_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_address0; - end else begin - local_B_45_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_45_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_45_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_address1; - end else begin - local_B_45_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_45_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_45_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_ce0; - end else begin - local_B_45_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_45_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_45_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_45_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_ce1; - end else begin - local_B_45_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_45_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_we0; - end else begin - local_B_45_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_45_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_45_we1; - end else begin - local_B_45_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_46_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_46_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_address0; - end else begin - local_B_46_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_46_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_46_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_address1; - end else begin - local_B_46_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_46_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_46_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_ce0; - end else begin - local_B_46_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_46_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_46_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_46_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_ce1; - end else begin - local_B_46_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_46_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_we0; - end else begin - local_B_46_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_46_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_46_we1; - end else begin - local_B_46_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_47_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_47_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_address0; - end else begin - local_B_47_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_47_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_47_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_address1; - end else begin - local_B_47_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_47_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_47_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_ce0; - end else begin - local_B_47_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_47_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_47_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_47_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_ce1; - end else begin - local_B_47_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_47_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_we0; - end else begin - local_B_47_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_47_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_47_we1; - end else begin - local_B_47_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_48_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_48_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_address0; - end else begin - local_B_48_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_48_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_48_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_address1; - end else begin - local_B_48_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_48_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_48_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_ce0; - end else begin - local_B_48_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_48_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_48_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_48_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_ce1; - end else begin - local_B_48_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_48_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_we0; - end else begin - local_B_48_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_48_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_48_we1; - end else begin - local_B_48_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_49_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_49_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_address0; - end else begin - local_B_49_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_49_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_49_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_address1; - end else begin - local_B_49_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_49_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_49_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_ce0; - end else begin - local_B_49_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_49_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_49_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_49_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_ce1; - end else begin - local_B_49_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_49_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_we0; - end else begin - local_B_49_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_49_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_49_we1; - end else begin - local_B_49_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_4_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_4_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_address0; - end else begin - local_B_4_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_4_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_4_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_address1; - end else begin - local_B_4_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_4_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_4_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_ce0; - end else begin - local_B_4_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_4_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_4_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_4_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_ce1; - end else begin - local_B_4_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_4_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_we0; - end else begin - local_B_4_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_4_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_4_we1; - end else begin - local_B_4_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_50_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_50_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_address0; - end else begin - local_B_50_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_50_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_50_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_address1; - end else begin - local_B_50_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_50_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_50_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_ce0; - end else begin - local_B_50_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_50_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_50_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_50_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_ce1; - end else begin - local_B_50_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_50_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_we0; - end else begin - local_B_50_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_50_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_50_we1; - end else begin - local_B_50_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_51_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_51_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_address0; - end else begin - local_B_51_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_51_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_51_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_address1; - end else begin - local_B_51_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_51_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_51_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_ce0; - end else begin - local_B_51_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_51_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_51_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_51_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_ce1; - end else begin - local_B_51_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_51_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_we0; - end else begin - local_B_51_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_51_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_51_we1; - end else begin - local_B_51_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_52_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_52_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_address0; - end else begin - local_B_52_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_52_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_52_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_address1; - end else begin - local_B_52_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_52_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_52_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_ce0; - end else begin - local_B_52_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_52_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_52_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_52_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_ce1; - end else begin - local_B_52_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_52_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_we0; - end else begin - local_B_52_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_52_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_52_we1; - end else begin - local_B_52_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_53_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_53_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_address0; - end else begin - local_B_53_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_53_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_53_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_address1; - end else begin - local_B_53_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_53_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_53_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_ce0; - end else begin - local_B_53_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_53_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_53_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_53_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_ce1; - end else begin - local_B_53_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_53_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_we0; - end else begin - local_B_53_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_53_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_53_we1; - end else begin - local_B_53_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_54_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_54_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_address0; - end else begin - local_B_54_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_54_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_54_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_address1; - end else begin - local_B_54_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_54_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_54_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_ce0; - end else begin - local_B_54_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_54_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_54_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_54_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_ce1; - end else begin - local_B_54_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_54_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_we0; - end else begin - local_B_54_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_54_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_54_we1; - end else begin - local_B_54_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_55_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_55_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_address0; - end else begin - local_B_55_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_55_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_55_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_address1; - end else begin - local_B_55_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_55_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_55_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_ce0; - end else begin - local_B_55_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_55_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_55_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_55_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_ce1; - end else begin - local_B_55_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_55_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_we0; - end else begin - local_B_55_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_55_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_55_we1; - end else begin - local_B_55_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_56_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_56_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_address0; - end else begin - local_B_56_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_56_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_56_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_address1; - end else begin - local_B_56_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_56_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_56_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_ce0; - end else begin - local_B_56_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_56_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_56_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_56_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_ce1; - end else begin - local_B_56_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_56_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_we0; - end else begin - local_B_56_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_56_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_56_we1; - end else begin - local_B_56_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_57_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_57_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_address0; - end else begin - local_B_57_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_57_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_57_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_address1; - end else begin - local_B_57_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_57_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_57_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_ce0; - end else begin - local_B_57_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_57_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_57_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_57_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_ce1; - end else begin - local_B_57_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_57_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_we0; - end else begin - local_B_57_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_57_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_57_we1; - end else begin - local_B_57_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_58_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_58_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_address0; - end else begin - local_B_58_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_58_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_58_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_address1; - end else begin - local_B_58_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_58_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_58_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_ce0; - end else begin - local_B_58_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_58_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_58_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_58_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_ce1; - end else begin - local_B_58_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_58_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_we0; - end else begin - local_B_58_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_58_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_58_we1; - end else begin - local_B_58_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_59_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_59_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_address0; - end else begin - local_B_59_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_59_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_59_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_address1; - end else begin - local_B_59_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_59_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_59_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_ce0; - end else begin - local_B_59_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_59_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_59_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_59_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_ce1; - end else begin - local_B_59_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_59_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_we0; - end else begin - local_B_59_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_59_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_59_we1; - end else begin - local_B_59_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_5_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_5_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_address0; - end else begin - local_B_5_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_5_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_5_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_address1; - end else begin - local_B_5_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_5_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_5_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_ce0; - end else begin - local_B_5_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_5_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_5_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_5_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_ce1; - end else begin - local_B_5_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_5_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_we0; - end else begin - local_B_5_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_5_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_5_we1; - end else begin - local_B_5_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_60_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_60_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_address0; - end else begin - local_B_60_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_60_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_60_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_address1; - end else begin - local_B_60_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_60_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_60_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_ce0; - end else begin - local_B_60_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_60_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_60_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_60_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_ce1; - end else begin - local_B_60_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_60_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_we0; - end else begin - local_B_60_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_60_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_60_we1; - end else begin - local_B_60_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_61_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_61_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_address0; - end else begin - local_B_61_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_61_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_61_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_address1; - end else begin - local_B_61_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_61_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_61_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_ce0; - end else begin - local_B_61_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_61_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_61_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_61_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_ce1; - end else begin - local_B_61_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_61_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_we0; - end else begin - local_B_61_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_61_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_61_we1; - end else begin - local_B_61_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_62_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_62_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_address0; - end else begin - local_B_62_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_62_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_62_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_address1; - end else begin - local_B_62_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_62_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_62_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_ce0; - end else begin - local_B_62_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_62_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_62_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_62_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_ce1; - end else begin - local_B_62_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_62_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_we0; - end else begin - local_B_62_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_62_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_62_we1; - end else begin - local_B_62_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_63_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_63_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_address0; - end else begin - local_B_63_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_63_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_63_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_address1; - end else begin - local_B_63_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_63_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_63_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_ce0; - end else begin - local_B_63_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_63_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_63_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_63_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_ce1; - end else begin - local_B_63_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_63_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_we0; - end else begin - local_B_63_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_63_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_63_we1; - end else begin - local_B_63_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_6_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_6_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_address0; - end else begin - local_B_6_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_6_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_6_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_address1; - end else begin - local_B_6_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_6_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_6_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_ce0; - end else begin - local_B_6_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_6_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_6_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_6_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_ce1; - end else begin - local_B_6_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_6_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_we0; - end else begin - local_B_6_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_6_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_6_we1; - end else begin - local_B_6_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_7_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_7_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_address0; - end else begin - local_B_7_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_7_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_7_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_address1; - end else begin - local_B_7_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_7_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_7_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_ce0; - end else begin - local_B_7_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_7_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_7_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_7_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_ce1; - end else begin - local_B_7_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_7_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_we0; - end else begin - local_B_7_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_7_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_7_we1; - end else begin - local_B_7_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_8_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_8_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_address0; - end else begin - local_B_8_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_8_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_8_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_address1; - end else begin - local_B_8_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_8_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_8_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_ce0; - end else begin - local_B_8_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_8_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_8_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_8_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_ce1; - end else begin - local_B_8_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_8_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_we0; - end else begin - local_B_8_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_8_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_8_we1; - end else begin - local_B_8_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_9_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_9_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_address0; - end else begin - local_B_9_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_9_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_9_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_address1; - end else begin - local_B_9_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_9_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_9_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_ce0; - end else begin - local_B_9_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_9_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_9_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_9_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_ce1; - end else begin - local_B_9_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_9_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_we0; - end else begin - local_B_9_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_9_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_9_we1; - end else begin - local_B_9_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_address0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_address0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_address0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_address0; - end else begin - local_B_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_address1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_address1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_address1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_address1; - end else begin - local_B_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_ce0 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_ce0; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_ce0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_ce0; - end else begin - local_B_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state15)) begin - local_B_ce1 = grp_PEG_Bmtx_Pipeline_computation_fu_760_local_B_ce1; - end else if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_ce1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_ce1; - end else begin - local_B_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_we0 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_we0; - end else begin - local_B_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_B_we1 = grp_PEG_Bmtx_Pipeline_read_B_fu_675_local_B_we1; - end else begin - local_B_we1 = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state2))) begin - ap_NS_fsm = ap_ST_fsm_state3; - end else begin - ap_NS_fsm = ap_ST_fsm_state2; - end - end - ap_ST_fsm_state3 : begin - if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)) & (1'b1 == ap_CS_fsm_state3))) begin - ap_NS_fsm = ap_ST_fsm_state4; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - ap_ST_fsm_state4 : begin - ap_NS_fsm = ap_ST_fsm_state5; - end - ap_ST_fsm_state5 : begin - ap_NS_fsm = ap_ST_fsm_state6; - end - ap_ST_fsm_state6 : begin - ap_NS_fsm = ap_ST_fsm_state7; - end - ap_ST_fsm_state7 : begin - if ((~((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n)) & (1'b1 == ap_CS_fsm_state7))) begin - ap_NS_fsm = ap_ST_fsm_state8; - end else begin - ap_NS_fsm = ap_ST_fsm_state7; - end - end - ap_ST_fsm_state8 : begin - if (((icmp_ln259_fu_981_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state8))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state9; - end - end - ap_ST_fsm_state9 : begin - if ((~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)) & (1'b1 == ap_CS_fsm_state9))) begin - ap_NS_fsm = ap_ST_fsm_state10; - end else begin - ap_NS_fsm = ap_ST_fsm_state9; - end - end - ap_ST_fsm_state10 : begin - if (((icmp_ln276_fu_1010_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state10))) begin - ap_NS_fsm = ap_ST_fsm_state8; - end else begin - ap_NS_fsm = ap_ST_fsm_state11; - end - end - ap_ST_fsm_state11 : begin - ap_NS_fsm = ap_ST_fsm_state12; - end - ap_ST_fsm_state12 : begin - if (((1'b1 == ap_CS_fsm_state12) & (grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_done == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state13; - end else begin - ap_NS_fsm = ap_ST_fsm_state12; - end - end - ap_ST_fsm_state13 : begin - if ((~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)) & (1'b1 == ap_CS_fsm_state13))) begin - ap_NS_fsm = ap_ST_fsm_state14; - end else begin - ap_NS_fsm = ap_ST_fsm_state13; - end - end - ap_ST_fsm_state14 : begin - ap_NS_fsm = ap_ST_fsm_state15; - end - ap_ST_fsm_state15 : begin - if (((1'b1 == ap_CS_fsm_state15) & (grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_done == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state10; - end else begin - ap_NS_fsm = ap_ST_fsm_state15; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign K_fu_941_p1 = PE_inst_in_s_dout[31:0]; - -assign NUM_ITE_fu_841_p1 = PE_inst_in_s_dout[31:0]; - -assign N_fu_878_p1 = PE_inst_in_s_dout[15:0]; - -assign PE_inst_in_peek_read = 1'b0; - -assign P_N_fu_874_p1 = PE_inst_in_s_dout[31:0]; - -assign add78_fu_954_p2 = (K_fu_941_p1 + 32'd7); - -assign add_ln257_fu_906_p2 = (zext_ln256_fu_902_p1 + 17'd7); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; - -assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; - -assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; - -assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; - -assign ap_CS_fsm_state14 = ap_CS_fsm[32'd13]; - -assign ap_CS_fsm_state15 = ap_CS_fsm[32'd14]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; - -assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; - -assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; - -assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; - -assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; - -assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; - -always @ (*) begin - ap_block_state1 = ((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n) | (ap_start == 1'b0)); -end - -always @ (*) begin - ap_block_state13 = ((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2 = ((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)); -end - -always @ (*) begin - ap_block_state3 = ((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n) | (1'b0 == PE_inst_to_Cmtx_full_n)); -end - -always @ (*) begin - ap_block_state7 = ((1'b0 == PE_inst_out_full_n) | (1'b0 == PE_inst_in_s_empty_n)); -end - -always @ (*) begin - ap_block_state9 = ((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)); -end - -always @ (*) begin - ap_condition_2077 = ~((fifo_inst_out_full_n == 1'b0) | (fifo_inst_in_s_empty_n == 1'b0) | (fifo_inst_out_to_Cmtx_full_n == 1'b0)); -end - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign empty_155_fu_1021_p1 = i_reg_654[22:0]; - -assign end_32_fu_1042_p1 = fifo_inst_in_s_dout[31:0]; - -assign fifo_A_peek_read = 1'b0; - -assign fifo_B_in_peek_0_read = 1'b0; - -assign fifo_B_in_peek_1_read = 1'b0; - -assign fifo_B_in_peek_2_read = 1'b0; - -assign fifo_B_in_peek_3_read = 1'b0; - -assign fifo_B_out_0_din = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_0_din; - -assign fifo_B_out_1_din = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_1_din; - -assign fifo_B_out_2_din = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_2_din; - -assign fifo_B_out_3_din = grp_PEG_Bmtx_Pipeline_read_B_fu_675_fifo_B_out_3_din; - -assign fifo_aBvec_0_din = grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_0_din; - -assign fifo_aBvec_1_din = grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_1_din; - -assign fifo_aBvec_2_din = grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_2_din; - -assign fifo_aBvec_3_din = grp_PEG_Bmtx_Pipeline_computation_fu_760_fifo_aBvec_3_din; - -assign fifo_inst_in_peek_read = 1'b0; - -assign grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_start = grp_PEG_Bmtx_Pipeline_computation_fu_760_ap_start_reg; - -assign grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_start = grp_PEG_Bmtx_Pipeline_read_B_fu_675_ap_start_reg; - -assign grp_fu_1056_p1 = grp_fu_1056_p10; - -assign grp_fu_1056_p10 = lshr_ln_reg_1080; - -assign i_1_fu_1015_p2 = (i_reg_654 + 31'd1); - -assign icmp_ln255_fu_922_p2 = ((N16_reg_1074 == 16'd0) ? 1'b1 : 1'b0); - -assign icmp_ln259_fu_981_p2 = (($signed(zext_ln259_fu_977_p1) < $signed(rp_time_N_reg_1095)) ? 1'b1 : 1'b0); - -assign icmp_ln276_fu_1010_p2 = (($signed(zext_ln276_fu_1006_p1) < $signed(NUM_ITE_reg_1069)) ? 1'b1 : 1'b0); - -assign mul_fu_1025_p3 = {{empty_155_fu_1021_p1}, {9'd0}}; - -assign p_0_fu_882_p3 = {{1'd0}, {P_N_fu_874_p1}}; - -assign p_10_fu_864_p3 = {{1'd0}, {trunc_ln85_fu_860_p1}}; - -assign p_11_fu_945_p3 = {{1'd0}, {K_fu_941_p1}}; - -assign p_cast_fu_960_p4 = {{add78_fu_954_p2[31:3]}}; - -assign p_s_fu_845_p3 = {{1'd0}, {NUM_ITE_fu_841_p1}}; - -assign rp_2_fu_986_p2 = (rp_fu_146 + 28'd1); - -assign rp_time_fu_927_p3 = ((icmp_ln255_fu_922_p2[0:0] == 1'b1) ? 16'd1 : N16_reg_1074); - -assign shr79_fu_970_p1 = $signed(p_cast_fu_960_p4); - -assign start_32_fu_992_p1 = fifo_inst_in_s_dout[31:0]; - -assign sub_fu_1033_p2 = ($signed(shr79_reg_1100) - $signed(mul_fu_1025_p3)); - -assign tmp_11_fu_1046_p3 = {{1'd0}, {end_32_fu_1042_p1}}; - -assign tmp_9_fu_996_p3 = {{1'd0}, {start_32_fu_992_p1}}; - -assign trunc_ln85_fu_860_p1 = PE_inst_in_s_dout[31:0]; - -assign zext_ln256_fu_902_p1 = N_fu_878_p1; - -assign zext_ln259_fu_977_p1 = rp_fu_146; - -assign zext_ln276_fu_1006_p1 = i_reg_654; - -endmodule //PEG_Bmtx diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_PEG_Bmtx_Pipeline_computation.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_PEG_Bmtx_Pipeline_computation.v deleted file mode 100644 index fe98f90e..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_PEG_Bmtx_Pipeline_computation.v +++ /dev/null @@ -1,4524 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module PEG_Bmtx_PEG_Bmtx_Pipeline_computation ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_aBvec_0_din, - fifo_aBvec_0_full_n, - fifo_aBvec_0_write, - fifo_aBvec_1_din, - fifo_aBvec_1_full_n, - fifo_aBvec_1_write, - fifo_aBvec_2_din, - fifo_aBvec_2_full_n, - fifo_aBvec_2_write, - fifo_aBvec_3_din, - fifo_aBvec_3_full_n, - fifo_aBvec_3_write, - start_32_3, - end_32, - fifo_A_s_dout, - fifo_A_s_empty_n, - fifo_A_s_read, - local_B_address0, - local_B_ce0, - local_B_q0, - local_B_address1, - local_B_ce1, - local_B_q1, - local_B_1_address0, - local_B_1_ce0, - local_B_1_q0, - local_B_1_address1, - local_B_1_ce1, - local_B_1_q1, - local_B_2_address0, - local_B_2_ce0, - local_B_2_q0, - local_B_2_address1, - local_B_2_ce1, - local_B_2_q1, - local_B_3_address0, - local_B_3_ce0, - local_B_3_q0, - local_B_3_address1, - local_B_3_ce1, - local_B_3_q1, - local_B_4_address0, - local_B_4_ce0, - local_B_4_q0, - local_B_4_address1, - local_B_4_ce1, - local_B_4_q1, - local_B_5_address0, - local_B_5_ce0, - local_B_5_q0, - local_B_5_address1, - local_B_5_ce1, - local_B_5_q1, - local_B_6_address0, - local_B_6_ce0, - local_B_6_q0, - local_B_6_address1, - local_B_6_ce1, - local_B_6_q1, - local_B_7_address0, - local_B_7_ce0, - local_B_7_q0, - local_B_7_address1, - local_B_7_ce1, - local_B_7_q1, - local_B_8_address0, - local_B_8_ce0, - local_B_8_q0, - local_B_8_address1, - local_B_8_ce1, - local_B_8_q1, - local_B_9_address0, - local_B_9_ce0, - local_B_9_q0, - local_B_9_address1, - local_B_9_ce1, - local_B_9_q1, - local_B_10_address0, - local_B_10_ce0, - local_B_10_q0, - local_B_10_address1, - local_B_10_ce1, - local_B_10_q1, - local_B_11_address0, - local_B_11_ce0, - local_B_11_q0, - local_B_11_address1, - local_B_11_ce1, - local_B_11_q1, - local_B_12_address0, - local_B_12_ce0, - local_B_12_q0, - local_B_12_address1, - local_B_12_ce1, - local_B_12_q1, - local_B_13_address0, - local_B_13_ce0, - local_B_13_q0, - local_B_13_address1, - local_B_13_ce1, - local_B_13_q1, - local_B_14_address0, - local_B_14_ce0, - local_B_14_q0, - local_B_14_address1, - local_B_14_ce1, - local_B_14_q1, - local_B_15_address0, - local_B_15_ce0, - local_B_15_q0, - local_B_15_address1, - local_B_15_ce1, - local_B_15_q1, - local_B_16_address0, - local_B_16_ce0, - local_B_16_q0, - local_B_16_address1, - local_B_16_ce1, - local_B_16_q1, - local_B_17_address0, - local_B_17_ce0, - local_B_17_q0, - local_B_17_address1, - local_B_17_ce1, - local_B_17_q1, - local_B_18_address0, - local_B_18_ce0, - local_B_18_q0, - local_B_18_address1, - local_B_18_ce1, - local_B_18_q1, - local_B_19_address0, - local_B_19_ce0, - local_B_19_q0, - local_B_19_address1, - local_B_19_ce1, - local_B_19_q1, - local_B_20_address0, - local_B_20_ce0, - local_B_20_q0, - local_B_20_address1, - local_B_20_ce1, - local_B_20_q1, - local_B_21_address0, - local_B_21_ce0, - local_B_21_q0, - local_B_21_address1, - local_B_21_ce1, - local_B_21_q1, - local_B_22_address0, - local_B_22_ce0, - local_B_22_q0, - local_B_22_address1, - local_B_22_ce1, - local_B_22_q1, - local_B_23_address0, - local_B_23_ce0, - local_B_23_q0, - local_B_23_address1, - local_B_23_ce1, - local_B_23_q1, - local_B_24_address0, - local_B_24_ce0, - local_B_24_q0, - local_B_24_address1, - local_B_24_ce1, - local_B_24_q1, - local_B_25_address0, - local_B_25_ce0, - local_B_25_q0, - local_B_25_address1, - local_B_25_ce1, - local_B_25_q1, - local_B_26_address0, - local_B_26_ce0, - local_B_26_q0, - local_B_26_address1, - local_B_26_ce1, - local_B_26_q1, - local_B_27_address0, - local_B_27_ce0, - local_B_27_q0, - local_B_27_address1, - local_B_27_ce1, - local_B_27_q1, - local_B_28_address0, - local_B_28_ce0, - local_B_28_q0, - local_B_28_address1, - local_B_28_ce1, - local_B_28_q1, - local_B_29_address0, - local_B_29_ce0, - local_B_29_q0, - local_B_29_address1, - local_B_29_ce1, - local_B_29_q1, - local_B_30_address0, - local_B_30_ce0, - local_B_30_q0, - local_B_30_address1, - local_B_30_ce1, - local_B_30_q1, - local_B_31_address0, - local_B_31_ce0, - local_B_31_q0, - local_B_31_address1, - local_B_31_ce1, - local_B_31_q1, - local_B_32_address0, - local_B_32_ce0, - local_B_32_q0, - local_B_32_address1, - local_B_32_ce1, - local_B_32_q1, - local_B_33_address0, - local_B_33_ce0, - local_B_33_q0, - local_B_33_address1, - local_B_33_ce1, - local_B_33_q1, - local_B_34_address0, - local_B_34_ce0, - local_B_34_q0, - local_B_34_address1, - local_B_34_ce1, - local_B_34_q1, - local_B_35_address0, - local_B_35_ce0, - local_B_35_q0, - local_B_35_address1, - local_B_35_ce1, - local_B_35_q1, - local_B_36_address0, - local_B_36_ce0, - local_B_36_q0, - local_B_36_address1, - local_B_36_ce1, - local_B_36_q1, - local_B_37_address0, - local_B_37_ce0, - local_B_37_q0, - local_B_37_address1, - local_B_37_ce1, - local_B_37_q1, - local_B_38_address0, - local_B_38_ce0, - local_B_38_q0, - local_B_38_address1, - local_B_38_ce1, - local_B_38_q1, - local_B_39_address0, - local_B_39_ce0, - local_B_39_q0, - local_B_39_address1, - local_B_39_ce1, - local_B_39_q1, - local_B_40_address0, - local_B_40_ce0, - local_B_40_q0, - local_B_40_address1, - local_B_40_ce1, - local_B_40_q1, - local_B_41_address0, - local_B_41_ce0, - local_B_41_q0, - local_B_41_address1, - local_B_41_ce1, - local_B_41_q1, - local_B_42_address0, - local_B_42_ce0, - local_B_42_q0, - local_B_42_address1, - local_B_42_ce1, - local_B_42_q1, - local_B_43_address0, - local_B_43_ce0, - local_B_43_q0, - local_B_43_address1, - local_B_43_ce1, - local_B_43_q1, - local_B_44_address0, - local_B_44_ce0, - local_B_44_q0, - local_B_44_address1, - local_B_44_ce1, - local_B_44_q1, - local_B_45_address0, - local_B_45_ce0, - local_B_45_q0, - local_B_45_address1, - local_B_45_ce1, - local_B_45_q1, - local_B_46_address0, - local_B_46_ce0, - local_B_46_q0, - local_B_46_address1, - local_B_46_ce1, - local_B_46_q1, - local_B_47_address0, - local_B_47_ce0, - local_B_47_q0, - local_B_47_address1, - local_B_47_ce1, - local_B_47_q1, - local_B_48_address0, - local_B_48_ce0, - local_B_48_q0, - local_B_48_address1, - local_B_48_ce1, - local_B_48_q1, - local_B_49_address0, - local_B_49_ce0, - local_B_49_q0, - local_B_49_address1, - local_B_49_ce1, - local_B_49_q1, - local_B_50_address0, - local_B_50_ce0, - local_B_50_q0, - local_B_50_address1, - local_B_50_ce1, - local_B_50_q1, - local_B_51_address0, - local_B_51_ce0, - local_B_51_q0, - local_B_51_address1, - local_B_51_ce1, - local_B_51_q1, - local_B_52_address0, - local_B_52_ce0, - local_B_52_q0, - local_B_52_address1, - local_B_52_ce1, - local_B_52_q1, - local_B_53_address0, - local_B_53_ce0, - local_B_53_q0, - local_B_53_address1, - local_B_53_ce1, - local_B_53_q1, - local_B_54_address0, - local_B_54_ce0, - local_B_54_q0, - local_B_54_address1, - local_B_54_ce1, - local_B_54_q1, - local_B_55_address0, - local_B_55_ce0, - local_B_55_q0, - local_B_55_address1, - local_B_55_ce1, - local_B_55_q1, - local_B_56_address0, - local_B_56_ce0, - local_B_56_q0, - local_B_56_address1, - local_B_56_ce1, - local_B_56_q1, - local_B_57_address0, - local_B_57_ce0, - local_B_57_q0, - local_B_57_address1, - local_B_57_ce1, - local_B_57_q1, - local_B_58_address0, - local_B_58_ce0, - local_B_58_q0, - local_B_58_address1, - local_B_58_ce1, - local_B_58_q1, - local_B_59_address0, - local_B_59_ce0, - local_B_59_q0, - local_B_59_address1, - local_B_59_ce1, - local_B_59_q1, - local_B_60_address0, - local_B_60_ce0, - local_B_60_q0, - local_B_60_address1, - local_B_60_ce1, - local_B_60_q1, - local_B_61_address0, - local_B_61_ce0, - local_B_61_q0, - local_B_61_address1, - local_B_61_ce1, - local_B_61_q1, - local_B_62_address0, - local_B_62_ce0, - local_B_62_q0, - local_B_62_address1, - local_B_62_ce1, - local_B_62_q1, - local_B_63_address0, - local_B_63_ce0, - local_B_63_q0, - local_B_63_address1, - local_B_63_ce1, - local_B_63_q1 -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -output [274:0] fifo_aBvec_0_din; -input fifo_aBvec_0_full_n; -output fifo_aBvec_0_write; -output [274:0] fifo_aBvec_1_din; -input fifo_aBvec_1_full_n; -output fifo_aBvec_1_write; -output [274:0] fifo_aBvec_2_din; -input fifo_aBvec_2_full_n; -output fifo_aBvec_2_write; -output [274:0] fifo_aBvec_3_din; -input fifo_aBvec_3_full_n; -output fifo_aBvec_3_write; -input [31:0] start_32_3; -input [31:0] end_32; -input [256:0] fifo_A_s_dout; -input fifo_A_s_empty_n; -output fifo_A_s_read; -output [9:0] local_B_address0; -output local_B_ce0; -input [31:0] local_B_q0; -output [9:0] local_B_address1; -output local_B_ce1; -input [31:0] local_B_q1; -output [9:0] local_B_1_address0; -output local_B_1_ce0; -input [31:0] local_B_1_q0; -output [9:0] local_B_1_address1; -output local_B_1_ce1; -input [31:0] local_B_1_q1; -output [9:0] local_B_2_address0; -output local_B_2_ce0; -input [31:0] local_B_2_q0; -output [9:0] local_B_2_address1; -output local_B_2_ce1; -input [31:0] local_B_2_q1; -output [9:0] local_B_3_address0; -output local_B_3_ce0; -input [31:0] local_B_3_q0; -output [9:0] local_B_3_address1; -output local_B_3_ce1; -input [31:0] local_B_3_q1; -output [9:0] local_B_4_address0; -output local_B_4_ce0; -input [31:0] local_B_4_q0; -output [9:0] local_B_4_address1; -output local_B_4_ce1; -input [31:0] local_B_4_q1; -output [9:0] local_B_5_address0; -output local_B_5_ce0; -input [31:0] local_B_5_q0; -output [9:0] local_B_5_address1; -output local_B_5_ce1; -input [31:0] local_B_5_q1; -output [9:0] local_B_6_address0; -output local_B_6_ce0; -input [31:0] local_B_6_q0; -output [9:0] local_B_6_address1; -output local_B_6_ce1; -input [31:0] local_B_6_q1; -output [9:0] local_B_7_address0; -output local_B_7_ce0; -input [31:0] local_B_7_q0; -output [9:0] local_B_7_address1; -output local_B_7_ce1; -input [31:0] local_B_7_q1; -output [9:0] local_B_8_address0; -output local_B_8_ce0; -input [31:0] local_B_8_q0; -output [9:0] local_B_8_address1; -output local_B_8_ce1; -input [31:0] local_B_8_q1; -output [9:0] local_B_9_address0; -output local_B_9_ce0; -input [31:0] local_B_9_q0; -output [9:0] local_B_9_address1; -output local_B_9_ce1; -input [31:0] local_B_9_q1; -output [9:0] local_B_10_address0; -output local_B_10_ce0; -input [31:0] local_B_10_q0; -output [9:0] local_B_10_address1; -output local_B_10_ce1; -input [31:0] local_B_10_q1; -output [9:0] local_B_11_address0; -output local_B_11_ce0; -input [31:0] local_B_11_q0; -output [9:0] local_B_11_address1; -output local_B_11_ce1; -input [31:0] local_B_11_q1; -output [9:0] local_B_12_address0; -output local_B_12_ce0; -input [31:0] local_B_12_q0; -output [9:0] local_B_12_address1; -output local_B_12_ce1; -input [31:0] local_B_12_q1; -output [9:0] local_B_13_address0; -output local_B_13_ce0; -input [31:0] local_B_13_q0; -output [9:0] local_B_13_address1; -output local_B_13_ce1; -input [31:0] local_B_13_q1; -output [9:0] local_B_14_address0; -output local_B_14_ce0; -input [31:0] local_B_14_q0; -output [9:0] local_B_14_address1; -output local_B_14_ce1; -input [31:0] local_B_14_q1; -output [9:0] local_B_15_address0; -output local_B_15_ce0; -input [31:0] local_B_15_q0; -output [9:0] local_B_15_address1; -output local_B_15_ce1; -input [31:0] local_B_15_q1; -output [9:0] local_B_16_address0; -output local_B_16_ce0; -input [31:0] local_B_16_q0; -output [9:0] local_B_16_address1; -output local_B_16_ce1; -input [31:0] local_B_16_q1; -output [9:0] local_B_17_address0; -output local_B_17_ce0; -input [31:0] local_B_17_q0; -output [9:0] local_B_17_address1; -output local_B_17_ce1; -input [31:0] local_B_17_q1; -output [9:0] local_B_18_address0; -output local_B_18_ce0; -input [31:0] local_B_18_q0; -output [9:0] local_B_18_address1; -output local_B_18_ce1; -input [31:0] local_B_18_q1; -output [9:0] local_B_19_address0; -output local_B_19_ce0; -input [31:0] local_B_19_q0; -output [9:0] local_B_19_address1; -output local_B_19_ce1; -input [31:0] local_B_19_q1; -output [9:0] local_B_20_address0; -output local_B_20_ce0; -input [31:0] local_B_20_q0; -output [9:0] local_B_20_address1; -output local_B_20_ce1; -input [31:0] local_B_20_q1; -output [9:0] local_B_21_address0; -output local_B_21_ce0; -input [31:0] local_B_21_q0; -output [9:0] local_B_21_address1; -output local_B_21_ce1; -input [31:0] local_B_21_q1; -output [9:0] local_B_22_address0; -output local_B_22_ce0; -input [31:0] local_B_22_q0; -output [9:0] local_B_22_address1; -output local_B_22_ce1; -input [31:0] local_B_22_q1; -output [9:0] local_B_23_address0; -output local_B_23_ce0; -input [31:0] local_B_23_q0; -output [9:0] local_B_23_address1; -output local_B_23_ce1; -input [31:0] local_B_23_q1; -output [9:0] local_B_24_address0; -output local_B_24_ce0; -input [31:0] local_B_24_q0; -output [9:0] local_B_24_address1; -output local_B_24_ce1; -input [31:0] local_B_24_q1; -output [9:0] local_B_25_address0; -output local_B_25_ce0; -input [31:0] local_B_25_q0; -output [9:0] local_B_25_address1; -output local_B_25_ce1; -input [31:0] local_B_25_q1; -output [9:0] local_B_26_address0; -output local_B_26_ce0; -input [31:0] local_B_26_q0; -output [9:0] local_B_26_address1; -output local_B_26_ce1; -input [31:0] local_B_26_q1; -output [9:0] local_B_27_address0; -output local_B_27_ce0; -input [31:0] local_B_27_q0; -output [9:0] local_B_27_address1; -output local_B_27_ce1; -input [31:0] local_B_27_q1; -output [9:0] local_B_28_address0; -output local_B_28_ce0; -input [31:0] local_B_28_q0; -output [9:0] local_B_28_address1; -output local_B_28_ce1; -input [31:0] local_B_28_q1; -output [9:0] local_B_29_address0; -output local_B_29_ce0; -input [31:0] local_B_29_q0; -output [9:0] local_B_29_address1; -output local_B_29_ce1; -input [31:0] local_B_29_q1; -output [9:0] local_B_30_address0; -output local_B_30_ce0; -input [31:0] local_B_30_q0; -output [9:0] local_B_30_address1; -output local_B_30_ce1; -input [31:0] local_B_30_q1; -output [9:0] local_B_31_address0; -output local_B_31_ce0; -input [31:0] local_B_31_q0; -output [9:0] local_B_31_address1; -output local_B_31_ce1; -input [31:0] local_B_31_q1; -output [9:0] local_B_32_address0; -output local_B_32_ce0; -input [31:0] local_B_32_q0; -output [9:0] local_B_32_address1; -output local_B_32_ce1; -input [31:0] local_B_32_q1; -output [9:0] local_B_33_address0; -output local_B_33_ce0; -input [31:0] local_B_33_q0; -output [9:0] local_B_33_address1; -output local_B_33_ce1; -input [31:0] local_B_33_q1; -output [9:0] local_B_34_address0; -output local_B_34_ce0; -input [31:0] local_B_34_q0; -output [9:0] local_B_34_address1; -output local_B_34_ce1; -input [31:0] local_B_34_q1; -output [9:0] local_B_35_address0; -output local_B_35_ce0; -input [31:0] local_B_35_q0; -output [9:0] local_B_35_address1; -output local_B_35_ce1; -input [31:0] local_B_35_q1; -output [9:0] local_B_36_address0; -output local_B_36_ce0; -input [31:0] local_B_36_q0; -output [9:0] local_B_36_address1; -output local_B_36_ce1; -input [31:0] local_B_36_q1; -output [9:0] local_B_37_address0; -output local_B_37_ce0; -input [31:0] local_B_37_q0; -output [9:0] local_B_37_address1; -output local_B_37_ce1; -input [31:0] local_B_37_q1; -output [9:0] local_B_38_address0; -output local_B_38_ce0; -input [31:0] local_B_38_q0; -output [9:0] local_B_38_address1; -output local_B_38_ce1; -input [31:0] local_B_38_q1; -output [9:0] local_B_39_address0; -output local_B_39_ce0; -input [31:0] local_B_39_q0; -output [9:0] local_B_39_address1; -output local_B_39_ce1; -input [31:0] local_B_39_q1; -output [9:0] local_B_40_address0; -output local_B_40_ce0; -input [31:0] local_B_40_q0; -output [9:0] local_B_40_address1; -output local_B_40_ce1; -input [31:0] local_B_40_q1; -output [9:0] local_B_41_address0; -output local_B_41_ce0; -input [31:0] local_B_41_q0; -output [9:0] local_B_41_address1; -output local_B_41_ce1; -input [31:0] local_B_41_q1; -output [9:0] local_B_42_address0; -output local_B_42_ce0; -input [31:0] local_B_42_q0; -output [9:0] local_B_42_address1; -output local_B_42_ce1; -input [31:0] local_B_42_q1; -output [9:0] local_B_43_address0; -output local_B_43_ce0; -input [31:0] local_B_43_q0; -output [9:0] local_B_43_address1; -output local_B_43_ce1; -input [31:0] local_B_43_q1; -output [9:0] local_B_44_address0; -output local_B_44_ce0; -input [31:0] local_B_44_q0; -output [9:0] local_B_44_address1; -output local_B_44_ce1; -input [31:0] local_B_44_q1; -output [9:0] local_B_45_address0; -output local_B_45_ce0; -input [31:0] local_B_45_q0; -output [9:0] local_B_45_address1; -output local_B_45_ce1; -input [31:0] local_B_45_q1; -output [9:0] local_B_46_address0; -output local_B_46_ce0; -input [31:0] local_B_46_q0; -output [9:0] local_B_46_address1; -output local_B_46_ce1; -input [31:0] local_B_46_q1; -output [9:0] local_B_47_address0; -output local_B_47_ce0; -input [31:0] local_B_47_q0; -output [9:0] local_B_47_address1; -output local_B_47_ce1; -input [31:0] local_B_47_q1; -output [9:0] local_B_48_address0; -output local_B_48_ce0; -input [31:0] local_B_48_q0; -output [9:0] local_B_48_address1; -output local_B_48_ce1; -input [31:0] local_B_48_q1; -output [9:0] local_B_49_address0; -output local_B_49_ce0; -input [31:0] local_B_49_q0; -output [9:0] local_B_49_address1; -output local_B_49_ce1; -input [31:0] local_B_49_q1; -output [9:0] local_B_50_address0; -output local_B_50_ce0; -input [31:0] local_B_50_q0; -output [9:0] local_B_50_address1; -output local_B_50_ce1; -input [31:0] local_B_50_q1; -output [9:0] local_B_51_address0; -output local_B_51_ce0; -input [31:0] local_B_51_q0; -output [9:0] local_B_51_address1; -output local_B_51_ce1; -input [31:0] local_B_51_q1; -output [9:0] local_B_52_address0; -output local_B_52_ce0; -input [31:0] local_B_52_q0; -output [9:0] local_B_52_address1; -output local_B_52_ce1; -input [31:0] local_B_52_q1; -output [9:0] local_B_53_address0; -output local_B_53_ce0; -input [31:0] local_B_53_q0; -output [9:0] local_B_53_address1; -output local_B_53_ce1; -input [31:0] local_B_53_q1; -output [9:0] local_B_54_address0; -output local_B_54_ce0; -input [31:0] local_B_54_q0; -output [9:0] local_B_54_address1; -output local_B_54_ce1; -input [31:0] local_B_54_q1; -output [9:0] local_B_55_address0; -output local_B_55_ce0; -input [31:0] local_B_55_q0; -output [9:0] local_B_55_address1; -output local_B_55_ce1; -input [31:0] local_B_55_q1; -output [9:0] local_B_56_address0; -output local_B_56_ce0; -input [31:0] local_B_56_q0; -output [9:0] local_B_56_address1; -output local_B_56_ce1; -input [31:0] local_B_56_q1; -output [9:0] local_B_57_address0; -output local_B_57_ce0; -input [31:0] local_B_57_q0; -output [9:0] local_B_57_address1; -output local_B_57_ce1; -input [31:0] local_B_57_q1; -output [9:0] local_B_58_address0; -output local_B_58_ce0; -input [31:0] local_B_58_q0; -output [9:0] local_B_58_address1; -output local_B_58_ce1; -input [31:0] local_B_58_q1; -output [9:0] local_B_59_address0; -output local_B_59_ce0; -input [31:0] local_B_59_q0; -output [9:0] local_B_59_address1; -output local_B_59_ce1; -input [31:0] local_B_59_q1; -output [9:0] local_B_60_address0; -output local_B_60_ce0; -input [31:0] local_B_60_q0; -output [9:0] local_B_60_address1; -output local_B_60_ce1; -input [31:0] local_B_60_q1; -output [9:0] local_B_61_address0; -output local_B_61_ce0; -input [31:0] local_B_61_q0; -output [9:0] local_B_61_address1; -output local_B_61_ce1; -input [31:0] local_B_61_q1; -output [9:0] local_B_62_address0; -output local_B_62_ce0; -input [31:0] local_B_62_q0; -output [9:0] local_B_62_address1; -output local_B_62_ce1; -input [31:0] local_B_62_q1; -output [9:0] local_B_63_address0; -output local_B_63_ce0; -input [31:0] local_B_63_q0; -output [9:0] local_B_63_address1; -output local_B_63_ce1; -input [31:0] local_B_63_q1; - -reg ap_idle; -reg fifo_aBvec_0_write; -reg fifo_aBvec_1_write; -reg fifo_aBvec_2_write; -reg fifo_aBvec_3_write; -reg fifo_A_s_read; -reg local_B_ce0; -reg local_B_ce1; -reg local_B_1_ce0; -reg local_B_1_ce1; -reg local_B_2_ce0; -reg local_B_2_ce1; -reg local_B_3_ce0; -reg local_B_3_ce1; -reg local_B_4_ce0; -reg local_B_4_ce1; -reg local_B_5_ce0; -reg local_B_5_ce1; -reg local_B_6_ce0; -reg local_B_6_ce1; -reg local_B_7_ce0; -reg local_B_7_ce1; -reg local_B_8_ce0; -reg local_B_8_ce1; -reg local_B_9_ce0; -reg local_B_9_ce1; -reg local_B_10_ce0; -reg local_B_10_ce1; -reg local_B_11_ce0; -reg local_B_11_ce1; -reg local_B_12_ce0; -reg local_B_12_ce1; -reg local_B_13_ce0; -reg local_B_13_ce1; -reg local_B_14_ce0; -reg local_B_14_ce1; -reg local_B_15_ce0; -reg local_B_15_ce1; -reg local_B_16_ce0; -reg local_B_16_ce1; -reg local_B_17_ce0; -reg local_B_17_ce1; -reg local_B_18_ce0; -reg local_B_18_ce1; -reg local_B_19_ce0; -reg local_B_19_ce1; -reg local_B_20_ce0; -reg local_B_20_ce1; -reg local_B_21_ce0; -reg local_B_21_ce1; -reg local_B_22_ce0; -reg local_B_22_ce1; -reg local_B_23_ce0; -reg local_B_23_ce1; -reg local_B_24_ce0; -reg local_B_24_ce1; -reg local_B_25_ce0; -reg local_B_25_ce1; -reg local_B_26_ce0; -reg local_B_26_ce1; -reg local_B_27_ce0; -reg local_B_27_ce1; -reg local_B_28_ce0; -reg local_B_28_ce1; -reg local_B_29_ce0; -reg local_B_29_ce1; -reg local_B_30_ce0; -reg local_B_30_ce1; -reg local_B_31_ce0; -reg local_B_31_ce1; -reg local_B_32_ce0; -reg local_B_32_ce1; -reg local_B_33_ce0; -reg local_B_33_ce1; -reg local_B_34_ce0; -reg local_B_34_ce1; -reg local_B_35_ce0; -reg local_B_35_ce1; -reg local_B_36_ce0; -reg local_B_36_ce1; -reg local_B_37_ce0; -reg local_B_37_ce1; -reg local_B_38_ce0; -reg local_B_38_ce1; -reg local_B_39_ce0; -reg local_B_39_ce1; -reg local_B_40_ce0; -reg local_B_40_ce1; -reg local_B_41_ce0; -reg local_B_41_ce1; -reg local_B_42_ce0; -reg local_B_42_ce1; -reg local_B_43_ce0; -reg local_B_43_ce1; -reg local_B_44_ce0; -reg local_B_44_ce1; -reg local_B_45_ce0; -reg local_B_45_ce1; -reg local_B_46_ce0; -reg local_B_46_ce1; -reg local_B_47_ce0; -reg local_B_47_ce1; -reg local_B_48_ce0; -reg local_B_48_ce1; -reg local_B_49_ce0; -reg local_B_49_ce1; -reg local_B_50_ce0; -reg local_B_50_ce1; -reg local_B_51_ce0; -reg local_B_51_ce1; -reg local_B_52_ce0; -reg local_B_52_ce1; -reg local_B_53_ce0; -reg local_B_53_ce1; -reg local_B_54_ce0; -reg local_B_54_ce1; -reg local_B_55_ce0; -reg local_B_55_ce1; -reg local_B_56_ce0; -reg local_B_56_ce1; -reg local_B_57_ce0; -reg local_B_57_ce1; -reg local_B_58_ce0; -reg local_B_58_ce1; -reg local_B_59_ce0; -reg local_B_59_ce1; -reg local_B_60_ce0; -reg local_B_60_ce1; -reg local_B_61_ce0; -reg local_B_61_ce1; -reg local_B_62_ce0; -reg local_B_62_ce1; -reg local_B_63_ce0; -reg local_B_63_ce1; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_enable_reg_pp0_iter2; -reg ap_enable_reg_pp0_iter3; -reg ap_enable_reg_pp0_iter4; -reg ap_enable_reg_pp0_iter5; -reg ap_enable_reg_pp0_iter6; -reg ap_enable_reg_pp0_iter7; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -wire ap_block_state3_pp0_stage0_iter2; -wire ap_block_state4_pp0_stage0_iter3; -wire ap_block_state5_pp0_stage0_iter4; -wire ap_block_state6_pp0_stage0_iter5; -wire ap_block_state7_pp0_stage0_iter6; -reg [0:0] is_success_reg_3105; -reg [0:0] is_success_reg_3105_pp0_iter6_reg; -reg ap_block_state8_pp0_stage0_iter7; -reg ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln311_fu_2042_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -reg fifo_aBvec_0_blk_n; -wire ap_block_pp0_stage0; -reg fifo_aBvec_1_blk_n; -reg fifo_aBvec_2_blk_n; -reg fifo_aBvec_3_blk_n; -reg ap_block_pp0_stage0_11001; -wire [0:0] is_success_fu_2048_p1; -reg [0:0] is_success_reg_3105_pp0_iter1_reg; -reg [0:0] is_success_reg_3105_pp0_iter2_reg; -reg [0:0] is_success_reg_3105_pp0_iter3_reg; -reg [0:0] is_success_reg_3105_pp0_iter4_reg; -reg [0:0] is_success_reg_3105_pp0_iter5_reg; -reg [17:0] a_row_V_reg_3109; -reg [17:0] a_row_V_reg_3109_pp0_iter1_reg; -reg [17:0] a_row_V_reg_3109_pp0_iter2_reg; -reg [17:0] a_row_V_reg_3109_pp0_iter3_reg; -reg [17:0] a_row_V_reg_3109_pp0_iter4_reg; -reg [17:0] a_row_V_reg_3109_pp0_iter5_reg; -reg [17:0] a_row_V_reg_3109_pp0_iter6_reg; -wire [31:0] a_val_V_fu_2066_p1; -reg [31:0] a_val_V_reg_3114; -reg [31:0] a_val_V_reg_3114_pp0_iter1_reg; -reg [31:0] a_val_V_reg_3114_pp0_iter2_reg; -reg [9:0] lshr_ln1_reg_3119; -reg [1:0] trunc_ln1_reg_3124; -reg [1:0] trunc_ln1_reg_3124_pp0_iter1_reg; -reg [17:0] a_row_V_1_reg_3136; -reg [17:0] a_row_V_1_reg_3136_pp0_iter1_reg; -reg [17:0] a_row_V_1_reg_3136_pp0_iter2_reg; -reg [17:0] a_row_V_1_reg_3136_pp0_iter3_reg; -reg [17:0] a_row_V_1_reg_3136_pp0_iter4_reg; -reg [17:0] a_row_V_1_reg_3136_pp0_iter5_reg; -reg [17:0] a_row_V_1_reg_3136_pp0_iter6_reg; -reg [31:0] a_val_V_1_reg_3141; -reg [31:0] a_val_V_1_reg_3141_pp0_iter1_reg; -reg [31:0] a_val_V_1_reg_3141_pp0_iter2_reg; -reg [0:0] p_Result_s_reg_3146; -reg [0:0] p_Result_s_reg_3146_pp0_iter1_reg; -reg [0:0] p_Result_s_reg_3146_pp0_iter2_reg; -reg [0:0] p_Result_s_reg_3146_pp0_iter3_reg; -reg [0:0] p_Result_s_reg_3146_pp0_iter4_reg; -reg [0:0] p_Result_s_reg_3146_pp0_iter5_reg; -reg [0:0] p_Result_s_reg_3146_pp0_iter6_reg; -reg [9:0] lshr_ln127_1_reg_3151; -reg [1:0] trunc_ln127_1_reg_3156; -reg [1:0] trunc_ln127_1_reg_3156_pp0_iter1_reg; -reg [17:0] a_row_V_2_reg_3168; -reg [17:0] a_row_V_2_reg_3168_pp0_iter1_reg; -reg [17:0] a_row_V_2_reg_3168_pp0_iter2_reg; -reg [17:0] a_row_V_2_reg_3168_pp0_iter3_reg; -reg [17:0] a_row_V_2_reg_3168_pp0_iter4_reg; -reg [17:0] a_row_V_2_reg_3168_pp0_iter5_reg; -reg [17:0] a_row_V_2_reg_3168_pp0_iter6_reg; -reg [31:0] a_val_V_2_reg_3173; -reg [31:0] a_val_V_2_reg_3173_pp0_iter1_reg; -reg [31:0] a_val_V_2_reg_3173_pp0_iter2_reg; -reg [0:0] p_Result_1_reg_3178; -reg [0:0] p_Result_1_reg_3178_pp0_iter1_reg; -reg [0:0] p_Result_1_reg_3178_pp0_iter2_reg; -reg [0:0] p_Result_1_reg_3178_pp0_iter3_reg; -reg [0:0] p_Result_1_reg_3178_pp0_iter4_reg; -reg [0:0] p_Result_1_reg_3178_pp0_iter5_reg; -reg [0:0] p_Result_1_reg_3178_pp0_iter6_reg; -reg [9:0] lshr_ln127_2_reg_3183; -reg [1:0] trunc_ln127_2_reg_3188; -reg [1:0] trunc_ln127_2_reg_3188_pp0_iter1_reg; -reg [17:0] a_row_V_3_reg_3200; -reg [17:0] a_row_V_3_reg_3200_pp0_iter1_reg; -reg [17:0] a_row_V_3_reg_3200_pp0_iter2_reg; -reg [17:0] a_row_V_3_reg_3200_pp0_iter3_reg; -reg [17:0] a_row_V_3_reg_3200_pp0_iter4_reg; -reg [17:0] a_row_V_3_reg_3200_pp0_iter5_reg; -reg [17:0] a_row_V_3_reg_3200_pp0_iter6_reg; -reg [31:0] a_val_V_3_reg_3205; -reg [31:0] a_val_V_3_reg_3205_pp0_iter1_reg; -reg [31:0] a_val_V_3_reg_3205_pp0_iter2_reg; -reg [0:0] p_Result_2_reg_3210; -reg [0:0] p_Result_2_reg_3210_pp0_iter1_reg; -reg [0:0] p_Result_2_reg_3210_pp0_iter2_reg; -reg [0:0] p_Result_2_reg_3210_pp0_iter3_reg; -reg [0:0] p_Result_2_reg_3210_pp0_iter4_reg; -reg [0:0] p_Result_2_reg_3210_pp0_iter5_reg; -reg [0:0] p_Result_2_reg_3210_pp0_iter6_reg; -reg [9:0] lshr_ln127_3_reg_3215; -reg [1:0] trunc_ln127_3_reg_3220; -reg [1:0] trunc_ln127_3_reg_3220_pp0_iter1_reg; -wire [31:0] tmp_s_fu_2385_p6; -reg [31:0] tmp_s_reg_3872; -wire [31:0] tmp_58_fu_2398_p6; -reg [31:0] tmp_58_reg_3877; -wire [31:0] tmp_59_fu_2411_p6; -reg [31:0] tmp_59_reg_3882; -wire [31:0] tmp_60_fu_2424_p6; -reg [31:0] tmp_60_reg_3887; -wire [31:0] tmp_61_fu_2437_p6; -reg [31:0] tmp_61_reg_3892; -wire [31:0] tmp_62_fu_2450_p6; -reg [31:0] tmp_62_reg_3897; -wire [31:0] tmp_63_fu_2463_p6; -reg [31:0] tmp_63_reg_3902; -wire [31:0] tmp_64_fu_2476_p6; -reg [31:0] tmp_64_reg_3907; -wire [31:0] tmp_65_fu_2489_p6; -reg [31:0] tmp_65_reg_3912; -wire [31:0] tmp_66_fu_2502_p6; -reg [31:0] tmp_66_reg_3917; -wire [31:0] tmp_67_fu_2515_p6; -reg [31:0] tmp_67_reg_3922; -wire [31:0] tmp_68_fu_2528_p6; -reg [31:0] tmp_68_reg_3927; -wire [31:0] tmp_69_fu_2541_p6; -reg [31:0] tmp_69_reg_3932; -wire [31:0] tmp_70_fu_2554_p6; -reg [31:0] tmp_70_reg_3937; -wire [31:0] tmp_71_fu_2567_p6; -reg [31:0] tmp_71_reg_3942; -wire [31:0] tmp_72_fu_2580_p6; -reg [31:0] tmp_72_reg_3947; -wire [31:0] tmp_73_fu_2593_p6; -reg [31:0] tmp_73_reg_3952; -wire [31:0] tmp_74_fu_2606_p6; -reg [31:0] tmp_74_reg_3957; -wire [31:0] tmp_75_fu_2619_p6; -reg [31:0] tmp_75_reg_3962; -wire [31:0] tmp_76_fu_2632_p6; -reg [31:0] tmp_76_reg_3967; -wire [31:0] tmp_77_fu_2645_p6; -reg [31:0] tmp_77_reg_3972; -wire [31:0] tmp_78_fu_2658_p6; -reg [31:0] tmp_78_reg_3977; -wire [31:0] tmp_79_fu_2671_p6; -reg [31:0] tmp_79_reg_3982; -wire [31:0] tmp_80_fu_2684_p6; -reg [31:0] tmp_80_reg_3987; -wire [31:0] tmp_81_fu_2697_p6; -reg [31:0] tmp_81_reg_3992; -wire [31:0] tmp_82_fu_2710_p6; -reg [31:0] tmp_82_reg_3997; -wire [31:0] tmp_83_fu_2723_p6; -reg [31:0] tmp_83_reg_4002; -wire [31:0] tmp_84_fu_2736_p6; -reg [31:0] tmp_84_reg_4007; -wire [31:0] tmp_85_fu_2749_p6; -reg [31:0] tmp_85_reg_4012; -wire [31:0] tmp_86_fu_2762_p6; -reg [31:0] tmp_86_reg_4017; -wire [31:0] tmp_87_fu_2775_p6; -reg [31:0] tmp_87_reg_4022; -wire [31:0] tmp_88_fu_2788_p6; -reg [31:0] tmp_88_reg_4027; -wire [31:0] empty_fu_2801_p1; -wire [31:0] empty_127_fu_2812_p1; -wire [31:0] empty_128_fu_2823_p1; -wire [31:0] empty_129_fu_2834_p1; -wire [31:0] grp_fu_1906_p2; -reg [31:0] mul_i_reg_4080; -wire [31:0] grp_fu_1910_p2; -reg [31:0] mul_i_s_reg_4085; -wire [31:0] grp_fu_1914_p2; -reg [31:0] mul_i_8_reg_4090; -wire [31:0] grp_fu_1918_p2; -reg [31:0] mul_i_9_reg_4095; -wire [31:0] grp_fu_1922_p2; -reg [31:0] mul_i_4_reg_4100; -wire [31:0] grp_fu_1926_p2; -reg [31:0] mul_i_5_reg_4105; -wire [31:0] grp_fu_1930_p2; -reg [31:0] mul_i_6_reg_4110; -wire [31:0] grp_fu_1934_p2; -reg [31:0] mul_i_7_reg_4115; -wire [31:0] grp_fu_1938_p2; -reg [31:0] mul_i_1_reg_4120; -wire [31:0] grp_fu_1942_p2; -reg [31:0] mul_i_1_1_reg_4125; -wire [31:0] grp_fu_1946_p2; -reg [31:0] mul_i_1_2_reg_4130; -wire [31:0] grp_fu_1950_p2; -reg [31:0] mul_i_1_3_reg_4135; -wire [31:0] grp_fu_1954_p2; -reg [31:0] mul_i_1_4_reg_4140; -wire [31:0] grp_fu_1958_p2; -reg [31:0] mul_i_1_5_reg_4145; -wire [31:0] grp_fu_1962_p2; -reg [31:0] mul_i_1_6_reg_4150; -wire [31:0] grp_fu_1966_p2; -reg [31:0] mul_i_1_7_reg_4155; -wire [31:0] grp_fu_1970_p2; -reg [31:0] mul_i_2_reg_4160; -wire [31:0] grp_fu_1974_p2; -reg [31:0] mul_i_2_1_reg_4165; -wire [31:0] grp_fu_1978_p2; -reg [31:0] mul_i_2_2_reg_4170; -wire [31:0] grp_fu_1982_p2; -reg [31:0] mul_i_2_3_reg_4175; -wire [31:0] grp_fu_1986_p2; -reg [31:0] mul_i_2_4_reg_4180; -wire [31:0] grp_fu_1990_p2; -reg [31:0] mul_i_2_5_reg_4185; -wire [31:0] grp_fu_1994_p2; -reg [31:0] mul_i_2_6_reg_4190; -wire [31:0] grp_fu_1998_p2; -reg [31:0] mul_i_2_7_reg_4195; -wire [31:0] grp_fu_2002_p2; -reg [31:0] mul_i_3_reg_4200; -wire [31:0] grp_fu_2006_p2; -reg [31:0] mul_i_3_1_reg_4205; -wire [31:0] grp_fu_2010_p2; -reg [31:0] mul_i_3_2_reg_4210; -wire [31:0] grp_fu_2014_p2; -reg [31:0] mul_i_3_3_reg_4215; -wire [31:0] grp_fu_2018_p2; -reg [31:0] mul_i_3_4_reg_4220; -wire [31:0] grp_fu_2022_p2; -reg [31:0] mul_i_3_5_reg_4225; -wire [31:0] grp_fu_2026_p2; -reg [31:0] mul_i_3_6_reg_4230; -wire [31:0] grp_fu_2030_p2; -reg [31:0] mul_i_3_7_reg_4235; -wire [63:0] zext_ln127_fu_2245_p1; -wire [63:0] zext_ln127_1_fu_2280_p1; -wire [63:0] zext_ln127_2_fu_2315_p1; -wire [63:0] zext_ln127_3_fu_2350_p1; -reg [31:0] j_fu_256; -wire [31:0] j_4_fu_2234_p2; -wire ap_loop_init; -reg [31:0] ap_sig_allocacmp_j_3; -wire [0:0] fifo_A_s_read_nbread_fu_272_p2_0; -reg ap_block_pp0_stage0_01001; -wire [31:0] bitcast_ln127_7_fu_2866_p1; -wire [31:0] bitcast_ln127_6_fu_2863_p1; -wire [31:0] bitcast_ln127_5_fu_2860_p1; -wire [31:0] bitcast_ln127_4_fu_2857_p1; -wire [31:0] bitcast_ln127_3_fu_2854_p1; -wire [31:0] bitcast_ln127_2_fu_2851_p1; -wire [31:0] bitcast_ln127_1_fu_2848_p1; -wire [31:0] bitcast_ln127_fu_2845_p1; -wire [31:0] bitcast_ln127_15_fu_2914_p1; -wire [31:0] bitcast_ln127_14_fu_2911_p1; -wire [31:0] bitcast_ln127_13_fu_2908_p1; -wire [31:0] bitcast_ln127_12_fu_2905_p1; -wire [31:0] bitcast_ln127_11_fu_2902_p1; -wire [31:0] bitcast_ln127_10_fu_2899_p1; -wire [31:0] bitcast_ln127_9_fu_2896_p1; -wire [223:0] tmp_fu_2917_p8; -wire [223:0] tmp_1_fu_2935_p8; -wire [223:0] select_ln779_fu_2953_p3; -wire [31:0] bitcast_ln127_8_fu_2893_p1; -wire [31:0] bitcast_ln127_23_fu_2993_p1; -wire [31:0] bitcast_ln127_22_fu_2990_p1; -wire [31:0] bitcast_ln127_21_fu_2987_p1; -wire [31:0] bitcast_ln127_20_fu_2984_p1; -wire [31:0] bitcast_ln127_19_fu_2981_p1; -wire [31:0] bitcast_ln127_18_fu_2978_p1; -wire [31:0] bitcast_ln127_17_fu_2975_p1; -wire [223:0] tmp_3_fu_2996_p8; -wire [223:0] select_ln779_1_fu_3014_p3; -wire [31:0] bitcast_ln127_16_fu_2972_p1; -wire [31:0] bitcast_ln127_31_fu_3054_p1; -wire [31:0] bitcast_ln127_30_fu_3051_p1; -wire [31:0] bitcast_ln127_29_fu_3048_p1; -wire [31:0] bitcast_ln127_28_fu_3045_p1; -wire [31:0] bitcast_ln127_27_fu_3042_p1; -wire [31:0] bitcast_ln127_26_fu_3039_p1; -wire [31:0] bitcast_ln127_25_fu_3036_p1; -wire [223:0] tmp_89_fu_3057_p8; -wire [223:0] select_ln779_2_fu_3075_p3; -wire [31:0] bitcast_ln127_24_fu_3033_p1; -reg grp_fu_1906_ce; -reg grp_fu_1910_ce; -reg grp_fu_1914_ce; -reg grp_fu_1918_ce; -reg grp_fu_1922_ce; -reg grp_fu_1926_ce; -reg grp_fu_1930_ce; -reg grp_fu_1934_ce; -reg grp_fu_1938_ce; -reg grp_fu_1942_ce; -reg grp_fu_1946_ce; -reg grp_fu_1950_ce; -reg grp_fu_1954_ce; -reg grp_fu_1958_ce; -reg grp_fu_1962_ce; -reg grp_fu_1966_ce; -reg grp_fu_1970_ce; -reg grp_fu_1974_ce; -reg grp_fu_1978_ce; -reg grp_fu_1982_ce; -reg grp_fu_1986_ce; -reg grp_fu_1990_ce; -reg grp_fu_1994_ce; -reg grp_fu_1998_ce; -reg grp_fu_2002_ce; -reg grp_fu_2006_ce; -reg grp_fu_2010_ce; -reg grp_fu_2014_ce; -reg grp_fu_2018_ce; -reg grp_fu_2022_ce; -reg grp_fu_2026_ce; -reg grp_fu_2030_ce; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg ap_loop_exit_ready_pp0_iter1_reg; -reg ap_loop_exit_ready_pp0_iter2_reg; -reg ap_loop_exit_ready_pp0_iter3_reg; -reg ap_loop_exit_ready_pp0_iter4_reg; -reg ap_loop_exit_ready_pp0_iter5_reg; -reg ap_loop_exit_ready_pp0_iter6_reg; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -reg ap_condition_2402; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_enable_reg_pp0_iter2 = 1'b0; -#0 ap_enable_reg_pp0_iter3 = 1'b0; -#0 ap_enable_reg_pp0_iter4 = 1'b0; -#0 ap_enable_reg_pp0_iter5 = 1'b0; -#0 ap_enable_reg_pp0_iter6 = 1'b0; -#0 ap_enable_reg_pp0_iter7 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U74( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_fu_2801_p1), - .din1(tmp_s_reg_3872), - .ce(grp_fu_1906_ce), - .dout(grp_fu_1906_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U75( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_fu_2801_p1), - .din1(tmp_58_reg_3877), - .ce(grp_fu_1910_ce), - .dout(grp_fu_1910_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U76( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_fu_2801_p1), - .din1(tmp_59_reg_3882), - .ce(grp_fu_1914_ce), - .dout(grp_fu_1914_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U77( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_fu_2801_p1), - .din1(tmp_60_reg_3887), - .ce(grp_fu_1918_ce), - .dout(grp_fu_1918_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U78( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_fu_2801_p1), - .din1(tmp_61_reg_3892), - .ce(grp_fu_1922_ce), - .dout(grp_fu_1922_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U79( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_fu_2801_p1), - .din1(tmp_62_reg_3897), - .ce(grp_fu_1926_ce), - .dout(grp_fu_1926_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U80( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_fu_2801_p1), - .din1(tmp_63_reg_3902), - .ce(grp_fu_1930_ce), - .dout(grp_fu_1930_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U81( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_fu_2801_p1), - .din1(tmp_64_reg_3907), - .ce(grp_fu_1934_ce), - .dout(grp_fu_1934_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U82( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_127_fu_2812_p1), - .din1(tmp_65_reg_3912), - .ce(grp_fu_1938_ce), - .dout(grp_fu_1938_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U83( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_127_fu_2812_p1), - .din1(tmp_66_reg_3917), - .ce(grp_fu_1942_ce), - .dout(grp_fu_1942_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U84( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_127_fu_2812_p1), - .din1(tmp_67_reg_3922), - .ce(grp_fu_1946_ce), - .dout(grp_fu_1946_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U85( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_127_fu_2812_p1), - .din1(tmp_68_reg_3927), - .ce(grp_fu_1950_ce), - .dout(grp_fu_1950_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U86( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_127_fu_2812_p1), - .din1(tmp_69_reg_3932), - .ce(grp_fu_1954_ce), - .dout(grp_fu_1954_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U87( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_127_fu_2812_p1), - .din1(tmp_70_reg_3937), - .ce(grp_fu_1958_ce), - .dout(grp_fu_1958_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U88( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_127_fu_2812_p1), - .din1(tmp_71_reg_3942), - .ce(grp_fu_1962_ce), - .dout(grp_fu_1962_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U89( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_127_fu_2812_p1), - .din1(tmp_72_reg_3947), - .ce(grp_fu_1966_ce), - .dout(grp_fu_1966_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U90( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_128_fu_2823_p1), - .din1(tmp_73_reg_3952), - .ce(grp_fu_1970_ce), - .dout(grp_fu_1970_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U91( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_128_fu_2823_p1), - .din1(tmp_74_reg_3957), - .ce(grp_fu_1974_ce), - .dout(grp_fu_1974_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U92( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_128_fu_2823_p1), - .din1(tmp_75_reg_3962), - .ce(grp_fu_1978_ce), - .dout(grp_fu_1978_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U93( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_128_fu_2823_p1), - .din1(tmp_76_reg_3967), - .ce(grp_fu_1982_ce), - .dout(grp_fu_1982_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U94( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_128_fu_2823_p1), - .din1(tmp_77_reg_3972), - .ce(grp_fu_1986_ce), - .dout(grp_fu_1986_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U95( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_128_fu_2823_p1), - .din1(tmp_78_reg_3977), - .ce(grp_fu_1990_ce), - .dout(grp_fu_1990_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U96( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_128_fu_2823_p1), - .din1(tmp_79_reg_3982), - .ce(grp_fu_1994_ce), - .dout(grp_fu_1994_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U97( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_128_fu_2823_p1), - .din1(tmp_80_reg_3987), - .ce(grp_fu_1998_ce), - .dout(grp_fu_1998_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U98( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_129_fu_2834_p1), - .din1(tmp_81_reg_3992), - .ce(grp_fu_2002_ce), - .dout(grp_fu_2002_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U99( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_129_fu_2834_p1), - .din1(tmp_82_reg_3997), - .ce(grp_fu_2006_ce), - .dout(grp_fu_2006_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U100( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_129_fu_2834_p1), - .din1(tmp_83_reg_4002), - .ce(grp_fu_2010_ce), - .dout(grp_fu_2010_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U101( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_129_fu_2834_p1), - .din1(tmp_84_reg_4007), - .ce(grp_fu_2014_ce), - .dout(grp_fu_2014_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U102( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_129_fu_2834_p1), - .din1(tmp_85_reg_4012), - .ce(grp_fu_2018_ce), - .dout(grp_fu_2018_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U103( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_129_fu_2834_p1), - .din1(tmp_86_reg_4017), - .ce(grp_fu_2022_ce), - .dout(grp_fu_2022_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U104( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_129_fu_2834_p1), - .din1(tmp_87_reg_4022), - .ce(grp_fu_2026_ce), - .dout(grp_fu_2026_p2) -); - -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_1_U105( - .clk(ap_clk), - .reset(ap_rst), - .din0(empty_129_fu_2834_p1), - .din1(tmp_88_reg_4027), - .ce(grp_fu_2030_ce), - .dout(grp_fu_2030_p2) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U106( - .din0(local_B_q1), - .din1(local_B_1_q1), - .din2(local_B_2_q1), - .din3(local_B_3_q1), - .din4(trunc_ln1_reg_3124_pp0_iter1_reg), - .dout(tmp_s_fu_2385_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U107( - .din0(local_B_4_q1), - .din1(local_B_5_q1), - .din2(local_B_6_q1), - .din3(local_B_7_q1), - .din4(trunc_ln1_reg_3124_pp0_iter1_reg), - .dout(tmp_58_fu_2398_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U108( - .din0(local_B_8_q1), - .din1(local_B_9_q1), - .din2(local_B_10_q1), - .din3(local_B_11_q1), - .din4(trunc_ln1_reg_3124_pp0_iter1_reg), - .dout(tmp_59_fu_2411_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U109( - .din0(local_B_12_q1), - .din1(local_B_13_q1), - .din2(local_B_14_q1), - .din3(local_B_15_q1), - .din4(trunc_ln1_reg_3124_pp0_iter1_reg), - .dout(tmp_60_fu_2424_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U110( - .din0(local_B_16_q1), - .din1(local_B_17_q1), - .din2(local_B_18_q1), - .din3(local_B_19_q1), - .din4(trunc_ln1_reg_3124_pp0_iter1_reg), - .dout(tmp_61_fu_2437_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U111( - .din0(local_B_20_q1), - .din1(local_B_21_q1), - .din2(local_B_22_q1), - .din3(local_B_23_q1), - .din4(trunc_ln1_reg_3124_pp0_iter1_reg), - .dout(tmp_62_fu_2450_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U112( - .din0(local_B_24_q1), - .din1(local_B_25_q1), - .din2(local_B_26_q1), - .din3(local_B_27_q1), - .din4(trunc_ln1_reg_3124_pp0_iter1_reg), - .dout(tmp_63_fu_2463_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U113( - .din0(local_B_28_q1), - .din1(local_B_29_q1), - .din2(local_B_30_q1), - .din3(local_B_31_q1), - .din4(trunc_ln1_reg_3124_pp0_iter1_reg), - .dout(tmp_64_fu_2476_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U114( - .din0(local_B_q0), - .din1(local_B_1_q0), - .din2(local_B_2_q0), - .din3(local_B_3_q0), - .din4(trunc_ln127_1_reg_3156_pp0_iter1_reg), - .dout(tmp_65_fu_2489_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U115( - .din0(local_B_4_q0), - .din1(local_B_5_q0), - .din2(local_B_6_q0), - .din3(local_B_7_q0), - .din4(trunc_ln127_1_reg_3156_pp0_iter1_reg), - .dout(tmp_66_fu_2502_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U116( - .din0(local_B_8_q0), - .din1(local_B_9_q0), - .din2(local_B_10_q0), - .din3(local_B_11_q0), - .din4(trunc_ln127_1_reg_3156_pp0_iter1_reg), - .dout(tmp_67_fu_2515_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U117( - .din0(local_B_12_q0), - .din1(local_B_13_q0), - .din2(local_B_14_q0), - .din3(local_B_15_q0), - .din4(trunc_ln127_1_reg_3156_pp0_iter1_reg), - .dout(tmp_68_fu_2528_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U118( - .din0(local_B_16_q0), - .din1(local_B_17_q0), - .din2(local_B_18_q0), - .din3(local_B_19_q0), - .din4(trunc_ln127_1_reg_3156_pp0_iter1_reg), - .dout(tmp_69_fu_2541_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U119( - .din0(local_B_20_q0), - .din1(local_B_21_q0), - .din2(local_B_22_q0), - .din3(local_B_23_q0), - .din4(trunc_ln127_1_reg_3156_pp0_iter1_reg), - .dout(tmp_70_fu_2554_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U120( - .din0(local_B_24_q0), - .din1(local_B_25_q0), - .din2(local_B_26_q0), - .din3(local_B_27_q0), - .din4(trunc_ln127_1_reg_3156_pp0_iter1_reg), - .dout(tmp_71_fu_2567_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U121( - .din0(local_B_28_q0), - .din1(local_B_29_q0), - .din2(local_B_30_q0), - .din3(local_B_31_q0), - .din4(trunc_ln127_1_reg_3156_pp0_iter1_reg), - .dout(tmp_72_fu_2580_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U122( - .din0(local_B_32_q1), - .din1(local_B_33_q1), - .din2(local_B_34_q1), - .din3(local_B_35_q1), - .din4(trunc_ln127_2_reg_3188_pp0_iter1_reg), - .dout(tmp_73_fu_2593_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U123( - .din0(local_B_36_q1), - .din1(local_B_37_q1), - .din2(local_B_38_q1), - .din3(local_B_39_q1), - .din4(trunc_ln127_2_reg_3188_pp0_iter1_reg), - .dout(tmp_74_fu_2606_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U124( - .din0(local_B_40_q1), - .din1(local_B_41_q1), - .din2(local_B_42_q1), - .din3(local_B_43_q1), - .din4(trunc_ln127_2_reg_3188_pp0_iter1_reg), - .dout(tmp_75_fu_2619_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U125( - .din0(local_B_44_q1), - .din1(local_B_45_q1), - .din2(local_B_46_q1), - .din3(local_B_47_q1), - .din4(trunc_ln127_2_reg_3188_pp0_iter1_reg), - .dout(tmp_76_fu_2632_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U126( - .din0(local_B_48_q1), - .din1(local_B_49_q1), - .din2(local_B_50_q1), - .din3(local_B_51_q1), - .din4(trunc_ln127_2_reg_3188_pp0_iter1_reg), - .dout(tmp_77_fu_2645_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U127( - .din0(local_B_52_q1), - .din1(local_B_53_q1), - .din2(local_B_54_q1), - .din3(local_B_55_q1), - .din4(trunc_ln127_2_reg_3188_pp0_iter1_reg), - .dout(tmp_78_fu_2658_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U128( - .din0(local_B_56_q1), - .din1(local_B_57_q1), - .din2(local_B_58_q1), - .din3(local_B_59_q1), - .din4(trunc_ln127_2_reg_3188_pp0_iter1_reg), - .dout(tmp_79_fu_2671_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U129( - .din0(local_B_60_q1), - .din1(local_B_61_q1), - .din2(local_B_62_q1), - .din3(local_B_63_q1), - .din4(trunc_ln127_2_reg_3188_pp0_iter1_reg), - .dout(tmp_80_fu_2684_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U130( - .din0(local_B_32_q0), - .din1(local_B_33_q0), - .din2(local_B_34_q0), - .din3(local_B_35_q0), - .din4(trunc_ln127_3_reg_3220_pp0_iter1_reg), - .dout(tmp_81_fu_2697_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U131( - .din0(local_B_36_q0), - .din1(local_B_37_q0), - .din2(local_B_38_q0), - .din3(local_B_39_q0), - .din4(trunc_ln127_3_reg_3220_pp0_iter1_reg), - .dout(tmp_82_fu_2710_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U132( - .din0(local_B_40_q0), - .din1(local_B_41_q0), - .din2(local_B_42_q0), - .din3(local_B_43_q0), - .din4(trunc_ln127_3_reg_3220_pp0_iter1_reg), - .dout(tmp_83_fu_2723_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U133( - .din0(local_B_44_q0), - .din1(local_B_45_q0), - .din2(local_B_46_q0), - .din3(local_B_47_q0), - .din4(trunc_ln127_3_reg_3220_pp0_iter1_reg), - .dout(tmp_84_fu_2736_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U134( - .din0(local_B_48_q0), - .din1(local_B_49_q0), - .din2(local_B_50_q0), - .din3(local_B_51_q0), - .din4(trunc_ln127_3_reg_3220_pp0_iter1_reg), - .dout(tmp_85_fu_2749_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U135( - .din0(local_B_52_q0), - .din1(local_B_53_q0), - .din2(local_B_54_q0), - .din3(local_B_55_q0), - .din4(trunc_ln127_3_reg_3220_pp0_iter1_reg), - .dout(tmp_86_fu_2762_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U136( - .din0(local_B_56_q0), - .din1(local_B_57_q0), - .din2(local_B_58_q0), - .din3(local_B_59_q0), - .din4(trunc_ln127_3_reg_3220_pp0_iter1_reg), - .dout(tmp_87_fu_2775_p6) -); - -PEG_Bmtx_mux_42_32_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .din2_WIDTH( 32 ), - .din3_WIDTH( 32 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 32 )) -mux_42_32_1_1_U137( - .din0(local_B_60_q0), - .din1(local_B_61_q0), - .din2(local_B_62_q0), - .din3(local_B_63_q0), - .din4(trunc_ln127_3_reg_3220_pp0_iter1_reg), - .dout(tmp_88_fu_2788_p6) -); - -PEG_Bmtx_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter6_reg == 1'b1))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter2 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter3 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter4 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter5 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter6 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter7 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((1'b1 == ap_condition_2402)) begin - j_fu_256 <= j_4_fu_2234_p2; - end else if ((ap_loop_init == 1'b1)) begin - j_fu_256 <= start_32_3; - end - end -end - -always @ (posedge ap_clk) begin - if (((icmp_ln311_fu_2042_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (is_success_fu_2048_p1 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - a_row_V_1_reg_3136 <= {{fifo_A_s_dout[113:96]}}; - a_row_V_2_reg_3168 <= {{fifo_A_s_dout[177:160]}}; - a_row_V_3_reg_3200 <= {{fifo_A_s_dout[241:224]}}; - a_row_V_reg_3109 <= {{fifo_A_s_dout[49:32]}}; - a_val_V_1_reg_3141 <= {{fifo_A_s_dout[95:64]}}; - a_val_V_2_reg_3173 <= {{fifo_A_s_dout[159:128]}}; - a_val_V_3_reg_3205 <= {{fifo_A_s_dout[223:192]}}; - a_val_V_reg_3114 <= a_val_V_fu_2066_p1; - lshr_ln127_1_reg_3151 <= {{fifo_A_s_dout[125:116]}}; - lshr_ln127_2_reg_3183 <= {{fifo_A_s_dout[189:180]}}; - lshr_ln127_3_reg_3215 <= {{fifo_A_s_dout[253:244]}}; - lshr_ln1_reg_3119 <= {{fifo_A_s_dout[61:52]}}; - p_Result_1_reg_3178 <= fifo_A_s_dout[32'd177]; - p_Result_2_reg_3210 <= fifo_A_s_dout[32'd241]; - p_Result_s_reg_3146 <= fifo_A_s_dout[32'd113]; - trunc_ln127_1_reg_3156 <= {{fifo_A_s_dout[115:114]}}; - trunc_ln127_2_reg_3188 <= {{fifo_A_s_dout[179:178]}}; - trunc_ln127_3_reg_3220 <= {{fifo_A_s_dout[243:242]}}; - trunc_ln1_reg_3124 <= {{fifo_A_s_dout[51:50]}}; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - a_row_V_1_reg_3136_pp0_iter1_reg <= a_row_V_1_reg_3136; - a_row_V_2_reg_3168_pp0_iter1_reg <= a_row_V_2_reg_3168; - a_row_V_3_reg_3200_pp0_iter1_reg <= a_row_V_3_reg_3200; - a_row_V_reg_3109_pp0_iter1_reg <= a_row_V_reg_3109; - a_val_V_1_reg_3141_pp0_iter1_reg <= a_val_V_1_reg_3141; - a_val_V_2_reg_3173_pp0_iter1_reg <= a_val_V_2_reg_3173; - a_val_V_3_reg_3205_pp0_iter1_reg <= a_val_V_3_reg_3205; - a_val_V_reg_3114_pp0_iter1_reg <= a_val_V_reg_3114; - ap_loop_exit_ready_pp0_iter1_reg <= ap_loop_exit_ready; - ap_loop_exit_ready_pp0_iter2_reg <= ap_loop_exit_ready_pp0_iter1_reg; - is_success_reg_3105_pp0_iter1_reg <= is_success_reg_3105; - p_Result_1_reg_3178_pp0_iter1_reg <= p_Result_1_reg_3178; - p_Result_2_reg_3210_pp0_iter1_reg <= p_Result_2_reg_3210; - p_Result_s_reg_3146_pp0_iter1_reg <= p_Result_s_reg_3146; - trunc_ln127_1_reg_3156_pp0_iter1_reg <= trunc_ln127_1_reg_3156; - trunc_ln127_2_reg_3188_pp0_iter1_reg <= trunc_ln127_2_reg_3188; - trunc_ln127_3_reg_3220_pp0_iter1_reg <= trunc_ln127_3_reg_3220; - trunc_ln1_reg_3124_pp0_iter1_reg <= trunc_ln1_reg_3124; - end -end - -always @ (posedge ap_clk) begin - if ((1'b0 == ap_block_pp0_stage0_11001)) begin - a_row_V_1_reg_3136_pp0_iter2_reg <= a_row_V_1_reg_3136_pp0_iter1_reg; - a_row_V_1_reg_3136_pp0_iter3_reg <= a_row_V_1_reg_3136_pp0_iter2_reg; - a_row_V_1_reg_3136_pp0_iter4_reg <= a_row_V_1_reg_3136_pp0_iter3_reg; - a_row_V_1_reg_3136_pp0_iter5_reg <= a_row_V_1_reg_3136_pp0_iter4_reg; - a_row_V_1_reg_3136_pp0_iter6_reg <= a_row_V_1_reg_3136_pp0_iter5_reg; - a_row_V_2_reg_3168_pp0_iter2_reg <= a_row_V_2_reg_3168_pp0_iter1_reg; - a_row_V_2_reg_3168_pp0_iter3_reg <= a_row_V_2_reg_3168_pp0_iter2_reg; - a_row_V_2_reg_3168_pp0_iter4_reg <= a_row_V_2_reg_3168_pp0_iter3_reg; - a_row_V_2_reg_3168_pp0_iter5_reg <= a_row_V_2_reg_3168_pp0_iter4_reg; - a_row_V_2_reg_3168_pp0_iter6_reg <= a_row_V_2_reg_3168_pp0_iter5_reg; - a_row_V_3_reg_3200_pp0_iter2_reg <= a_row_V_3_reg_3200_pp0_iter1_reg; - a_row_V_3_reg_3200_pp0_iter3_reg <= a_row_V_3_reg_3200_pp0_iter2_reg; - a_row_V_3_reg_3200_pp0_iter4_reg <= a_row_V_3_reg_3200_pp0_iter3_reg; - a_row_V_3_reg_3200_pp0_iter5_reg <= a_row_V_3_reg_3200_pp0_iter4_reg; - a_row_V_3_reg_3200_pp0_iter6_reg <= a_row_V_3_reg_3200_pp0_iter5_reg; - a_row_V_reg_3109_pp0_iter2_reg <= a_row_V_reg_3109_pp0_iter1_reg; - a_row_V_reg_3109_pp0_iter3_reg <= a_row_V_reg_3109_pp0_iter2_reg; - a_row_V_reg_3109_pp0_iter4_reg <= a_row_V_reg_3109_pp0_iter3_reg; - a_row_V_reg_3109_pp0_iter5_reg <= a_row_V_reg_3109_pp0_iter4_reg; - a_row_V_reg_3109_pp0_iter6_reg <= a_row_V_reg_3109_pp0_iter5_reg; - a_val_V_1_reg_3141_pp0_iter2_reg <= a_val_V_1_reg_3141_pp0_iter1_reg; - a_val_V_2_reg_3173_pp0_iter2_reg <= a_val_V_2_reg_3173_pp0_iter1_reg; - a_val_V_3_reg_3205_pp0_iter2_reg <= a_val_V_3_reg_3205_pp0_iter1_reg; - a_val_V_reg_3114_pp0_iter2_reg <= a_val_V_reg_3114_pp0_iter1_reg; - ap_loop_exit_ready_pp0_iter3_reg <= ap_loop_exit_ready_pp0_iter2_reg; - ap_loop_exit_ready_pp0_iter4_reg <= ap_loop_exit_ready_pp0_iter3_reg; - ap_loop_exit_ready_pp0_iter5_reg <= ap_loop_exit_ready_pp0_iter4_reg; - ap_loop_exit_ready_pp0_iter6_reg <= ap_loop_exit_ready_pp0_iter5_reg; - is_success_reg_3105_pp0_iter2_reg <= is_success_reg_3105_pp0_iter1_reg; - is_success_reg_3105_pp0_iter3_reg <= is_success_reg_3105_pp0_iter2_reg; - is_success_reg_3105_pp0_iter4_reg <= is_success_reg_3105_pp0_iter3_reg; - is_success_reg_3105_pp0_iter5_reg <= is_success_reg_3105_pp0_iter4_reg; - is_success_reg_3105_pp0_iter6_reg <= is_success_reg_3105_pp0_iter5_reg; - p_Result_1_reg_3178_pp0_iter2_reg <= p_Result_1_reg_3178_pp0_iter1_reg; - p_Result_1_reg_3178_pp0_iter3_reg <= p_Result_1_reg_3178_pp0_iter2_reg; - p_Result_1_reg_3178_pp0_iter4_reg <= p_Result_1_reg_3178_pp0_iter3_reg; - p_Result_1_reg_3178_pp0_iter5_reg <= p_Result_1_reg_3178_pp0_iter4_reg; - p_Result_1_reg_3178_pp0_iter6_reg <= p_Result_1_reg_3178_pp0_iter5_reg; - p_Result_2_reg_3210_pp0_iter2_reg <= p_Result_2_reg_3210_pp0_iter1_reg; - p_Result_2_reg_3210_pp0_iter3_reg <= p_Result_2_reg_3210_pp0_iter2_reg; - p_Result_2_reg_3210_pp0_iter4_reg <= p_Result_2_reg_3210_pp0_iter3_reg; - p_Result_2_reg_3210_pp0_iter5_reg <= p_Result_2_reg_3210_pp0_iter4_reg; - p_Result_2_reg_3210_pp0_iter6_reg <= p_Result_2_reg_3210_pp0_iter5_reg; - p_Result_s_reg_3146_pp0_iter2_reg <= p_Result_s_reg_3146_pp0_iter1_reg; - p_Result_s_reg_3146_pp0_iter3_reg <= p_Result_s_reg_3146_pp0_iter2_reg; - p_Result_s_reg_3146_pp0_iter4_reg <= p_Result_s_reg_3146_pp0_iter3_reg; - p_Result_s_reg_3146_pp0_iter5_reg <= p_Result_s_reg_3146_pp0_iter4_reg; - p_Result_s_reg_3146_pp0_iter6_reg <= p_Result_s_reg_3146_pp0_iter5_reg; - end -end - -always @ (posedge ap_clk) begin - if (((icmp_ln311_fu_2042_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - is_success_reg_3105 <= fifo_A_s_read_nbread_fu_272_p2_0; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_s_reg_3146_pp0_iter5_reg == 1'd0) & (is_success_reg_3105_pp0_iter5_reg == 1'd1))) begin - mul_i_1_1_reg_4125 <= grp_fu_1942_p2; - mul_i_1_2_reg_4130 <= grp_fu_1946_p2; - mul_i_1_3_reg_4135 <= grp_fu_1950_p2; - mul_i_1_4_reg_4140 <= grp_fu_1954_p2; - mul_i_1_5_reg_4145 <= grp_fu_1958_p2; - mul_i_1_6_reg_4150 <= grp_fu_1962_p2; - mul_i_1_7_reg_4155 <= grp_fu_1966_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (is_success_reg_3105_pp0_iter5_reg == 1'd1))) begin - mul_i_1_reg_4120 <= grp_fu_1938_p2; - mul_i_2_reg_4160 <= grp_fu_1970_p2; - mul_i_3_reg_4200 <= grp_fu_2002_p2; - mul_i_4_reg_4100 <= grp_fu_1922_p2; - mul_i_5_reg_4105 <= grp_fu_1926_p2; - mul_i_6_reg_4110 <= grp_fu_1930_p2; - mul_i_7_reg_4115 <= grp_fu_1934_p2; - mul_i_8_reg_4090 <= grp_fu_1914_p2; - mul_i_9_reg_4095 <= grp_fu_1918_p2; - mul_i_reg_4080 <= grp_fu_1906_p2; - mul_i_s_reg_4085 <= grp_fu_1910_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_1_reg_3178_pp0_iter5_reg == 1'd0) & (is_success_reg_3105_pp0_iter5_reg == 1'd1))) begin - mul_i_2_1_reg_4165 <= grp_fu_1974_p2; - mul_i_2_2_reg_4170 <= grp_fu_1978_p2; - mul_i_2_3_reg_4175 <= grp_fu_1982_p2; - mul_i_2_4_reg_4180 <= grp_fu_1986_p2; - mul_i_2_5_reg_4185 <= grp_fu_1990_p2; - mul_i_2_6_reg_4190 <= grp_fu_1994_p2; - mul_i_2_7_reg_4195 <= grp_fu_1998_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_2_reg_3210_pp0_iter5_reg == 1'd0) & (is_success_reg_3105_pp0_iter5_reg == 1'd1))) begin - mul_i_3_1_reg_4205 <= grp_fu_2006_p2; - mul_i_3_2_reg_4210 <= grp_fu_2010_p2; - mul_i_3_3_reg_4215 <= grp_fu_2014_p2; - mul_i_3_4_reg_4220 <= grp_fu_2018_p2; - mul_i_3_5_reg_4225 <= grp_fu_2022_p2; - mul_i_3_6_reg_4230 <= grp_fu_2026_p2; - mul_i_3_7_reg_4235 <= grp_fu_2030_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (is_success_reg_3105_pp0_iter1_reg == 1'd1))) begin - tmp_58_reg_3877 <= tmp_58_fu_2398_p6; - tmp_59_reg_3882 <= tmp_59_fu_2411_p6; - tmp_60_reg_3887 <= tmp_60_fu_2424_p6; - tmp_61_reg_3892 <= tmp_61_fu_2437_p6; - tmp_62_reg_3897 <= tmp_62_fu_2450_p6; - tmp_63_reg_3902 <= tmp_63_fu_2463_p6; - tmp_64_reg_3907 <= tmp_64_fu_2476_p6; - tmp_65_reg_3912 <= tmp_65_fu_2489_p6; - tmp_73_reg_3952 <= tmp_73_fu_2593_p6; - tmp_81_reg_3992 <= tmp_81_fu_2697_p6; - tmp_s_reg_3872 <= tmp_s_fu_2385_p6; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_s_reg_3146_pp0_iter1_reg == 1'd0) & (is_success_reg_3105_pp0_iter1_reg == 1'd1))) begin - tmp_66_reg_3917 <= tmp_66_fu_2502_p6; - tmp_67_reg_3922 <= tmp_67_fu_2515_p6; - tmp_68_reg_3927 <= tmp_68_fu_2528_p6; - tmp_69_reg_3932 <= tmp_69_fu_2541_p6; - tmp_70_reg_3937 <= tmp_70_fu_2554_p6; - tmp_71_reg_3942 <= tmp_71_fu_2567_p6; - tmp_72_reg_3947 <= tmp_72_fu_2580_p6; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_1_reg_3178_pp0_iter1_reg == 1'd0) & (is_success_reg_3105_pp0_iter1_reg == 1'd1))) begin - tmp_74_reg_3957 <= tmp_74_fu_2606_p6; - tmp_75_reg_3962 <= tmp_75_fu_2619_p6; - tmp_76_reg_3967 <= tmp_76_fu_2632_p6; - tmp_77_reg_3972 <= tmp_77_fu_2645_p6; - tmp_78_reg_3977 <= tmp_78_fu_2658_p6; - tmp_79_reg_3982 <= tmp_79_fu_2671_p6; - tmp_80_reg_3987 <= tmp_80_fu_2684_p6; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_2_reg_3210_pp0_iter1_reg == 1'd0) & (is_success_reg_3105_pp0_iter1_reg == 1'd1))) begin - tmp_82_reg_3997 <= tmp_82_fu_2710_p6; - tmp_83_reg_4002 <= tmp_83_fu_2723_p6; - tmp_84_reg_4007 <= tmp_84_fu_2736_p6; - tmp_85_reg_4012 <= tmp_85_fu_2749_p6; - tmp_86_reg_4017 <= tmp_86_fu_2762_p6; - tmp_87_reg_4022 <= tmp_87_fu_2775_p6; - tmp_88_reg_4027 <= tmp_88_fu_2788_p6; - end -end - -always @ (*) begin - if (((icmp_ln311_fu_2042_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter6_reg == 1'b1))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (ap_start_int == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1))) begin - ap_sig_allocacmp_j_3 = start_32_3; - end else begin - ap_sig_allocacmp_j_3 = j_fu_256; - end -end - -always @ (*) begin - if (((icmp_ln311_fu_2042_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (fifo_A_s_empty_n == 1'b1))) begin - fifo_A_s_read = 1'b1; - end else begin - fifo_A_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin - fifo_aBvec_0_blk_n = fifo_aBvec_0_full_n; - end else begin - fifo_aBvec_0_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (is_success_reg_3105_pp0_iter6_reg == 1'd1) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin - fifo_aBvec_0_write = 1'b1; - end else begin - fifo_aBvec_0_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin - fifo_aBvec_1_blk_n = fifo_aBvec_1_full_n; - end else begin - fifo_aBvec_1_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (is_success_reg_3105_pp0_iter6_reg == 1'd1) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin - fifo_aBvec_1_write = 1'b1; - end else begin - fifo_aBvec_1_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin - fifo_aBvec_2_blk_n = fifo_aBvec_2_full_n; - end else begin - fifo_aBvec_2_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (is_success_reg_3105_pp0_iter6_reg == 1'd1) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin - fifo_aBvec_2_write = 1'b1; - end else begin - fifo_aBvec_2_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin - fifo_aBvec_3_blk_n = fifo_aBvec_3_full_n; - end else begin - fifo_aBvec_3_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (is_success_reg_3105_pp0_iter6_reg == 1'd1) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin - fifo_aBvec_3_write = 1'b1; - end else begin - fifo_aBvec_3_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1906_ce = 1'b1; - end else begin - grp_fu_1906_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1910_ce = 1'b1; - end else begin - grp_fu_1910_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1914_ce = 1'b1; - end else begin - grp_fu_1914_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1918_ce = 1'b1; - end else begin - grp_fu_1918_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1922_ce = 1'b1; - end else begin - grp_fu_1922_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1926_ce = 1'b1; - end else begin - grp_fu_1926_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1930_ce = 1'b1; - end else begin - grp_fu_1930_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1934_ce = 1'b1; - end else begin - grp_fu_1934_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1938_ce = 1'b1; - end else begin - grp_fu_1938_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1942_ce = 1'b1; - end else begin - grp_fu_1942_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1946_ce = 1'b1; - end else begin - grp_fu_1946_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1950_ce = 1'b1; - end else begin - grp_fu_1950_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1954_ce = 1'b1; - end else begin - grp_fu_1954_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1958_ce = 1'b1; - end else begin - grp_fu_1958_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1962_ce = 1'b1; - end else begin - grp_fu_1962_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1966_ce = 1'b1; - end else begin - grp_fu_1966_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1970_ce = 1'b1; - end else begin - grp_fu_1970_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1974_ce = 1'b1; - end else begin - grp_fu_1974_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1978_ce = 1'b1; - end else begin - grp_fu_1978_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1982_ce = 1'b1; - end else begin - grp_fu_1982_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1986_ce = 1'b1; - end else begin - grp_fu_1986_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1990_ce = 1'b1; - end else begin - grp_fu_1990_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1994_ce = 1'b1; - end else begin - grp_fu_1994_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_1998_ce = 1'b1; - end else begin - grp_fu_1998_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_2002_ce = 1'b1; - end else begin - grp_fu_2002_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_2006_ce = 1'b1; - end else begin - grp_fu_2006_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_2010_ce = 1'b1; - end else begin - grp_fu_2010_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_2014_ce = 1'b1; - end else begin - grp_fu_2014_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_2018_ce = 1'b1; - end else begin - grp_fu_2018_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_2022_ce = 1'b1; - end else begin - grp_fu_2022_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_2026_ce = 1'b1; - end else begin - grp_fu_2026_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_fu_2030_ce = 1'b1; - end else begin - grp_fu_2030_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_10_ce0 = 1'b1; - end else begin - local_B_10_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_10_ce1 = 1'b1; - end else begin - local_B_10_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_11_ce0 = 1'b1; - end else begin - local_B_11_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_11_ce1 = 1'b1; - end else begin - local_B_11_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_12_ce0 = 1'b1; - end else begin - local_B_12_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_12_ce1 = 1'b1; - end else begin - local_B_12_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_13_ce0 = 1'b1; - end else begin - local_B_13_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_13_ce1 = 1'b1; - end else begin - local_B_13_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_14_ce0 = 1'b1; - end else begin - local_B_14_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_14_ce1 = 1'b1; - end else begin - local_B_14_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_15_ce0 = 1'b1; - end else begin - local_B_15_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_15_ce1 = 1'b1; - end else begin - local_B_15_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_16_ce0 = 1'b1; - end else begin - local_B_16_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_16_ce1 = 1'b1; - end else begin - local_B_16_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_17_ce0 = 1'b1; - end else begin - local_B_17_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_17_ce1 = 1'b1; - end else begin - local_B_17_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_18_ce0 = 1'b1; - end else begin - local_B_18_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_18_ce1 = 1'b1; - end else begin - local_B_18_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_19_ce0 = 1'b1; - end else begin - local_B_19_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_19_ce1 = 1'b1; - end else begin - local_B_19_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_1_ce0 = 1'b1; - end else begin - local_B_1_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_1_ce1 = 1'b1; - end else begin - local_B_1_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_20_ce0 = 1'b1; - end else begin - local_B_20_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_20_ce1 = 1'b1; - end else begin - local_B_20_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_21_ce0 = 1'b1; - end else begin - local_B_21_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_21_ce1 = 1'b1; - end else begin - local_B_21_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_22_ce0 = 1'b1; - end else begin - local_B_22_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_22_ce1 = 1'b1; - end else begin - local_B_22_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_23_ce0 = 1'b1; - end else begin - local_B_23_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_23_ce1 = 1'b1; - end else begin - local_B_23_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_24_ce0 = 1'b1; - end else begin - local_B_24_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_24_ce1 = 1'b1; - end else begin - local_B_24_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_25_ce0 = 1'b1; - end else begin - local_B_25_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_25_ce1 = 1'b1; - end else begin - local_B_25_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_26_ce0 = 1'b1; - end else begin - local_B_26_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_26_ce1 = 1'b1; - end else begin - local_B_26_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_27_ce0 = 1'b1; - end else begin - local_B_27_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_27_ce1 = 1'b1; - end else begin - local_B_27_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_28_ce0 = 1'b1; - end else begin - local_B_28_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_28_ce1 = 1'b1; - end else begin - local_B_28_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_29_ce0 = 1'b1; - end else begin - local_B_29_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_29_ce1 = 1'b1; - end else begin - local_B_29_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_2_ce0 = 1'b1; - end else begin - local_B_2_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_2_ce1 = 1'b1; - end else begin - local_B_2_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_30_ce0 = 1'b1; - end else begin - local_B_30_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_30_ce1 = 1'b1; - end else begin - local_B_30_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_31_ce0 = 1'b1; - end else begin - local_B_31_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_31_ce1 = 1'b1; - end else begin - local_B_31_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_32_ce0 = 1'b1; - end else begin - local_B_32_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_32_ce1 = 1'b1; - end else begin - local_B_32_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == 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= 1'b1; - end else begin - local_B_35_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_35_ce1 = 1'b1; - end else begin - local_B_35_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_36_ce0 = 1'b1; - end else begin - local_B_36_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_36_ce1 = 1'b1; - end else begin - local_B_36_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_37_ce0 = 1'b1; - end else begin - local_B_37_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == 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= 1'b1; - end else begin - local_B_39_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_3_ce0 = 1'b1; - end else begin - local_B_3_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_3_ce1 = 1'b1; - end else begin - local_B_3_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_40_ce0 = 1'b1; - end else begin - local_B_40_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_40_ce1 = 1'b1; - end else begin - local_B_40_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == 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= 1'b1; - end else begin - local_B_43_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_43_ce1 = 1'b1; - end else begin - local_B_43_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_44_ce0 = 1'b1; - end else begin - local_B_44_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_44_ce1 = 1'b1; - end else begin - local_B_44_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_45_ce0 = 1'b1; - end else begin - local_B_45_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == 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= 1'b1; - end else begin - local_B_47_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_48_ce0 = 1'b1; - end else begin - local_B_48_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_48_ce1 = 1'b1; - end else begin - local_B_48_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_49_ce0 = 1'b1; - end else begin - local_B_49_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_49_ce1 = 1'b1; - end else begin - local_B_49_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == 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1'b1; - end else begin - local_B_51_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_51_ce1 = 1'b1; - end else begin - local_B_51_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_52_ce0 = 1'b1; - end else begin - local_B_52_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_52_ce1 = 1'b1; - end else begin - local_B_52_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_53_ce0 = 1'b1; - end else begin - local_B_53_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == 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= 1'b1; - end else begin - local_B_55_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_56_ce0 = 1'b1; - end else begin - local_B_56_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_56_ce1 = 1'b1; - end else begin - local_B_56_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_57_ce0 = 1'b1; - end else begin - local_B_57_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_57_ce1 = 1'b1; - end else begin - local_B_57_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_58_ce0 = 1'b1; - end else begin - local_B_58_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_58_ce1 = 1'b1; - end else begin - local_B_58_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_59_ce0 = 1'b1; - end else begin - local_B_59_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_59_ce1 = 1'b1; - end else begin - local_B_59_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_5_ce0 = 1'b1; - end else begin - local_B_5_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_5_ce1 = 1'b1; - end else begin - local_B_5_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_60_ce0 = 1'b1; - end else begin - local_B_60_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_60_ce1 = 1'b1; - end else begin - local_B_60_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_61_ce0 = 1'b1; - end else begin - local_B_61_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_61_ce1 = 1'b1; - end else begin - local_B_61_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_62_ce0 = 1'b1; - end else begin - local_B_62_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_62_ce1 = 1'b1; - end else begin - local_B_62_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_63_ce0 = 1'b1; - end else begin - local_B_63_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_63_ce1 = 1'b1; - end else begin - local_B_63_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_6_ce0 = 1'b1; - end else begin - local_B_6_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_6_ce1 = 1'b1; - end else begin - local_B_6_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_7_ce0 = 1'b1; - end else begin - local_B_7_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_7_ce1 = 1'b1; - end else begin - local_B_7_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_8_ce0 = 1'b1; - end else begin - local_B_8_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_8_ce1 = 1'b1; - end else begin - local_B_8_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_9_ce0 = 1'b1; - end else begin - local_B_9_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_9_ce1 = 1'b1; - end else begin - local_B_9_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_ce0 = 1'b1; - end else begin - local_B_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_B_ce1 = 1'b1; - end else begin - local_B_ce1 = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign a_val_V_fu_2066_p1 = fifo_A_s_dout[31:0]; - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage0_01001 = ((ap_enable_reg_pp0_iter7 == 1'b1) & (((fifo_aBvec_3_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((fifo_aBvec_2_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((fifo_aBvec_1_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((is_success_reg_3105_pp0_iter6_reg == 1'd1) & (fifo_aBvec_0_full_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001 = ((ap_enable_reg_pp0_iter7 == 1'b1) & (((fifo_aBvec_3_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((fifo_aBvec_2_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((fifo_aBvec_1_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((is_success_reg_3105_pp0_iter6_reg == 1'd1) & (fifo_aBvec_0_full_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_subdone = ((ap_enable_reg_pp0_iter7 == 1'b1) & (((fifo_aBvec_3_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((fifo_aBvec_2_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((fifo_aBvec_1_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((is_success_reg_3105_pp0_iter6_reg == 1'd1) & (fifo_aBvec_0_full_n == 1'b0)))); -end - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_state8_pp0_stage0_iter7 = (((fifo_aBvec_3_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((fifo_aBvec_2_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((fifo_aBvec_1_full_n == 1'b0) & (is_success_reg_3105_pp0_iter6_reg == 1'd1)) | ((is_success_reg_3105_pp0_iter6_reg == 1'd1) & (fifo_aBvec_0_full_n == 1'b0))); -end - -always @ (*) begin - ap_condition_2402 = ((icmp_ln311_fu_2042_p2 == 1'd1) & (is_success_fu_2048_p1 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -assign bitcast_ln127_10_fu_2899_p1 = mul_i_1_2_reg_4130; - -assign bitcast_ln127_11_fu_2902_p1 = mul_i_1_3_reg_4135; - -assign bitcast_ln127_12_fu_2905_p1 = mul_i_1_4_reg_4140; - -assign bitcast_ln127_13_fu_2908_p1 = mul_i_1_5_reg_4145; - -assign bitcast_ln127_14_fu_2911_p1 = mul_i_1_6_reg_4150; - -assign bitcast_ln127_15_fu_2914_p1 = mul_i_1_7_reg_4155; - -assign bitcast_ln127_16_fu_2972_p1 = mul_i_2_reg_4160; - -assign bitcast_ln127_17_fu_2975_p1 = mul_i_2_1_reg_4165; - -assign bitcast_ln127_18_fu_2978_p1 = mul_i_2_2_reg_4170; - -assign bitcast_ln127_19_fu_2981_p1 = mul_i_2_3_reg_4175; - -assign bitcast_ln127_1_fu_2848_p1 = mul_i_s_reg_4085; - -assign bitcast_ln127_20_fu_2984_p1 = mul_i_2_4_reg_4180; - -assign bitcast_ln127_21_fu_2987_p1 = mul_i_2_5_reg_4185; - -assign bitcast_ln127_22_fu_2990_p1 = mul_i_2_6_reg_4190; - -assign bitcast_ln127_23_fu_2993_p1 = mul_i_2_7_reg_4195; - -assign bitcast_ln127_24_fu_3033_p1 = mul_i_3_reg_4200; - -assign bitcast_ln127_25_fu_3036_p1 = mul_i_3_1_reg_4205; - -assign bitcast_ln127_26_fu_3039_p1 = mul_i_3_2_reg_4210; - -assign bitcast_ln127_27_fu_3042_p1 = mul_i_3_3_reg_4215; - -assign bitcast_ln127_28_fu_3045_p1 = mul_i_3_4_reg_4220; - -assign bitcast_ln127_29_fu_3048_p1 = mul_i_3_5_reg_4225; - -assign bitcast_ln127_2_fu_2851_p1 = mul_i_8_reg_4090; - -assign bitcast_ln127_30_fu_3051_p1 = mul_i_3_6_reg_4230; - -assign bitcast_ln127_31_fu_3054_p1 = mul_i_3_7_reg_4235; - -assign bitcast_ln127_3_fu_2854_p1 = mul_i_9_reg_4095; - -assign bitcast_ln127_4_fu_2857_p1 = mul_i_4_reg_4100; - -assign bitcast_ln127_5_fu_2860_p1 = mul_i_5_reg_4105; - -assign bitcast_ln127_6_fu_2863_p1 = mul_i_6_reg_4110; - -assign bitcast_ln127_7_fu_2866_p1 = mul_i_7_reg_4115; - -assign bitcast_ln127_8_fu_2893_p1 = mul_i_1_reg_4120; - -assign bitcast_ln127_9_fu_2896_p1 = mul_i_1_1_reg_4125; - -assign bitcast_ln127_fu_2845_p1 = mul_i_reg_4080; - -assign empty_127_fu_2812_p1 = a_val_V_1_reg_3141_pp0_iter2_reg; - -assign empty_128_fu_2823_p1 = a_val_V_2_reg_3173_pp0_iter2_reg; - -assign empty_129_fu_2834_p1 = a_val_V_3_reg_3205_pp0_iter2_reg; - -assign empty_fu_2801_p1 = a_val_V_reg_3114_pp0_iter2_reg; - -assign fifo_A_s_read_nbread_fu_272_p2_0 = fifo_A_s_empty_n; - -assign fifo_aBvec_0_din = {{{{{{{{{{{{{{{{{{1'd0}, {bitcast_ln127_7_fu_2866_p1}}}, {bitcast_ln127_6_fu_2863_p1}}}, {bitcast_ln127_5_fu_2860_p1}}}, {bitcast_ln127_4_fu_2857_p1}}}, {bitcast_ln127_3_fu_2854_p1}}}, {bitcast_ln127_2_fu_2851_p1}}}, {bitcast_ln127_1_fu_2848_p1}}}, {bitcast_ln127_fu_2845_p1}}}, {a_row_V_reg_3109_pp0_iter6_reg}}; - -assign fifo_aBvec_1_din = {{{{{{1'd0}, {select_ln779_fu_2953_p3}}}, {bitcast_ln127_8_fu_2893_p1}}}, {a_row_V_1_reg_3136_pp0_iter6_reg}}; - -assign fifo_aBvec_2_din = {{{{{{1'd0}, {select_ln779_1_fu_3014_p3}}}, {bitcast_ln127_16_fu_2972_p1}}}, {a_row_V_2_reg_3168_pp0_iter6_reg}}; - -assign fifo_aBvec_3_din = {{{{{{1'd0}, {select_ln779_2_fu_3075_p3}}}, {bitcast_ln127_24_fu_3033_p1}}}, {a_row_V_3_reg_3200_pp0_iter6_reg}}; - -assign icmp_ln311_fu_2042_p2 = (($signed(ap_sig_allocacmp_j_3) < $signed(end_32)) ? 1'b1 : 1'b0); - -assign is_success_fu_2048_p1 = fifo_A_s_read_nbread_fu_272_p2_0; - -assign j_4_fu_2234_p2 = (ap_sig_allocacmp_j_3 + 32'd1); - -assign local_B_10_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_10_address1 = zext_ln127_fu_2245_p1; - -assign local_B_11_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_11_address1 = zext_ln127_fu_2245_p1; - -assign local_B_12_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_12_address1 = zext_ln127_fu_2245_p1; - -assign local_B_13_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_13_address1 = zext_ln127_fu_2245_p1; - -assign local_B_14_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_14_address1 = zext_ln127_fu_2245_p1; - -assign local_B_15_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_15_address1 = zext_ln127_fu_2245_p1; - -assign local_B_16_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_16_address1 = zext_ln127_fu_2245_p1; - -assign local_B_17_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_17_address1 = zext_ln127_fu_2245_p1; - -assign local_B_18_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_18_address1 = zext_ln127_fu_2245_p1; - -assign local_B_19_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_19_address1 = zext_ln127_fu_2245_p1; - -assign local_B_1_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_1_address1 = zext_ln127_fu_2245_p1; - -assign local_B_20_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_20_address1 = zext_ln127_fu_2245_p1; - -assign local_B_21_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_21_address1 = zext_ln127_fu_2245_p1; - -assign local_B_22_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_22_address1 = zext_ln127_fu_2245_p1; - -assign local_B_23_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_23_address1 = zext_ln127_fu_2245_p1; - -assign local_B_24_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_24_address1 = zext_ln127_fu_2245_p1; - -assign local_B_25_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_25_address1 = zext_ln127_fu_2245_p1; - -assign local_B_26_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_26_address1 = zext_ln127_fu_2245_p1; - -assign local_B_27_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_27_address1 = zext_ln127_fu_2245_p1; - -assign local_B_28_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_28_address1 = zext_ln127_fu_2245_p1; - -assign local_B_29_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_29_address1 = zext_ln127_fu_2245_p1; - -assign local_B_2_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_2_address1 = zext_ln127_fu_2245_p1; - -assign local_B_30_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_30_address1 = zext_ln127_fu_2245_p1; - -assign local_B_31_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_31_address1 = zext_ln127_fu_2245_p1; - -assign local_B_32_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_32_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_33_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_33_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_34_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_34_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_35_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_35_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_36_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_36_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_37_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_37_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_38_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_38_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_39_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_39_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_3_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_3_address1 = zext_ln127_fu_2245_p1; - -assign local_B_40_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_40_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_41_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_41_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_42_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_42_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_43_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_43_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_44_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_44_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_45_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_45_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_46_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_46_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_47_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_47_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_48_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_48_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_49_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_49_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_4_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_4_address1 = zext_ln127_fu_2245_p1; - -assign local_B_50_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_50_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_51_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_51_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_52_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_52_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_53_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_53_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_54_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_54_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_55_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_55_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_56_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_56_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_57_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_57_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_58_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_58_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_59_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_59_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_5_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_5_address1 = zext_ln127_fu_2245_p1; - -assign local_B_60_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_60_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_61_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_61_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_62_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_62_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_63_address0 = zext_ln127_3_fu_2350_p1; - -assign local_B_63_address1 = zext_ln127_2_fu_2315_p1; - -assign local_B_6_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_6_address1 = zext_ln127_fu_2245_p1; - -assign local_B_7_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_7_address1 = zext_ln127_fu_2245_p1; - -assign local_B_8_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_8_address1 = zext_ln127_fu_2245_p1; - -assign local_B_9_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_9_address1 = zext_ln127_fu_2245_p1; - -assign local_B_address0 = zext_ln127_1_fu_2280_p1; - -assign local_B_address1 = zext_ln127_fu_2245_p1; - -assign select_ln779_1_fu_3014_p3 = ((p_Result_1_reg_3178_pp0_iter6_reg[0:0] == 1'b1) ? select_ln779_fu_2953_p3 : tmp_3_fu_2996_p8); - -assign select_ln779_2_fu_3075_p3 = ((p_Result_2_reg_3210_pp0_iter6_reg[0:0] == 1'b1) ? select_ln779_1_fu_3014_p3 : tmp_89_fu_3057_p8); - -assign select_ln779_fu_2953_p3 = ((p_Result_s_reg_3146_pp0_iter6_reg[0:0] == 1'b1) ? tmp_fu_2917_p8 : tmp_1_fu_2935_p8); - -assign tmp_1_fu_2935_p8 = {{{{{{{bitcast_ln127_15_fu_2914_p1}, {bitcast_ln127_14_fu_2911_p1}}, {bitcast_ln127_13_fu_2908_p1}}, {bitcast_ln127_12_fu_2905_p1}}, {bitcast_ln127_11_fu_2902_p1}}, {bitcast_ln127_10_fu_2899_p1}}, {bitcast_ln127_9_fu_2896_p1}}; - -assign tmp_3_fu_2996_p8 = {{{{{{{bitcast_ln127_23_fu_2993_p1}, {bitcast_ln127_22_fu_2990_p1}}, {bitcast_ln127_21_fu_2987_p1}}, {bitcast_ln127_20_fu_2984_p1}}, {bitcast_ln127_19_fu_2981_p1}}, {bitcast_ln127_18_fu_2978_p1}}, {bitcast_ln127_17_fu_2975_p1}}; - -assign tmp_89_fu_3057_p8 = {{{{{{{bitcast_ln127_31_fu_3054_p1}, {bitcast_ln127_30_fu_3051_p1}}, {bitcast_ln127_29_fu_3048_p1}}, {bitcast_ln127_28_fu_3045_p1}}, {bitcast_ln127_27_fu_3042_p1}}, {bitcast_ln127_26_fu_3039_p1}}, {bitcast_ln127_25_fu_3036_p1}}; - -assign tmp_fu_2917_p8 = {{{{{{{bitcast_ln127_7_fu_2866_p1}, {bitcast_ln127_6_fu_2863_p1}}, {bitcast_ln127_5_fu_2860_p1}}, {bitcast_ln127_4_fu_2857_p1}}, {bitcast_ln127_3_fu_2854_p1}}, {bitcast_ln127_2_fu_2851_p1}}, {bitcast_ln127_1_fu_2848_p1}}; - -assign zext_ln127_1_fu_2280_p1 = lshr_ln127_1_reg_3151; - -assign zext_ln127_2_fu_2315_p1 = lshr_ln127_2_reg_3183; - -assign zext_ln127_3_fu_2350_p1 = lshr_ln127_3_reg_3215; - -assign zext_ln127_fu_2245_p1 = lshr_ln1_reg_3119; - -endmodule //PEG_Bmtx_PEG_Bmtx_Pipeline_computation diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_PEG_Bmtx_Pipeline_read_B.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_PEG_Bmtx_Pipeline_read_B.v deleted file mode 100644 index 9538f493..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_PEG_Bmtx_Pipeline_read_B.v +++ /dev/null @@ -1,4606 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module PEG_Bmtx_PEG_Bmtx_Pipeline_read_B ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - local_B_63_address0, - local_B_63_ce0, - local_B_63_we0, - local_B_63_d0, - local_B_63_address1, - local_B_63_ce1, - local_B_63_we1, - local_B_63_d1, - local_B_62_address0, - local_B_62_ce0, - local_B_62_we0, - local_B_62_d0, - local_B_62_address1, - local_B_62_ce1, - local_B_62_we1, - local_B_62_d1, - local_B_61_address0, - local_B_61_ce0, - local_B_61_we0, - local_B_61_d0, - local_B_61_address1, - local_B_61_ce1, - local_B_61_we1, - local_B_61_d1, - local_B_60_address0, - local_B_60_ce0, - local_B_60_we0, - local_B_60_d0, - local_B_60_address1, - local_B_60_ce1, - local_B_60_we1, - local_B_60_d1, - local_B_59_address0, - local_B_59_ce0, - local_B_59_we0, - local_B_59_d0, - local_B_59_address1, - local_B_59_ce1, - local_B_59_we1, - local_B_59_d1, - local_B_58_address0, - local_B_58_ce0, - local_B_58_we0, - local_B_58_d0, - local_B_58_address1, - local_B_58_ce1, - local_B_58_we1, - local_B_58_d1, - local_B_57_address0, - local_B_57_ce0, - local_B_57_we0, - local_B_57_d0, - local_B_57_address1, - local_B_57_ce1, - local_B_57_we1, - local_B_57_d1, - local_B_56_address0, - local_B_56_ce0, - local_B_56_we0, - local_B_56_d0, - local_B_56_address1, - local_B_56_ce1, - local_B_56_we1, - local_B_56_d1, - local_B_55_address0, - local_B_55_ce0, - local_B_55_we0, - local_B_55_d0, - local_B_55_address1, - local_B_55_ce1, - local_B_55_we1, - local_B_55_d1, - local_B_54_address0, - local_B_54_ce0, - local_B_54_we0, - local_B_54_d0, - local_B_54_address1, - local_B_54_ce1, - local_B_54_we1, - local_B_54_d1, - local_B_53_address0, - local_B_53_ce0, - local_B_53_we0, - local_B_53_d0, - local_B_53_address1, - local_B_53_ce1, - local_B_53_we1, - local_B_53_d1, - local_B_52_address0, - local_B_52_ce0, - local_B_52_we0, - local_B_52_d0, - local_B_52_address1, - local_B_52_ce1, - local_B_52_we1, - local_B_52_d1, - local_B_51_address0, - local_B_51_ce0, - local_B_51_we0, - local_B_51_d0, - local_B_51_address1, - local_B_51_ce1, - local_B_51_we1, - local_B_51_d1, - local_B_50_address0, - local_B_50_ce0, - local_B_50_we0, - local_B_50_d0, - local_B_50_address1, - local_B_50_ce1, - local_B_50_we1, - local_B_50_d1, - local_B_49_address0, - local_B_49_ce0, - local_B_49_we0, - local_B_49_d0, - local_B_49_address1, - local_B_49_ce1, - local_B_49_we1, - local_B_49_d1, - local_B_48_address0, - local_B_48_ce0, - local_B_48_we0, - local_B_48_d0, - local_B_48_address1, - local_B_48_ce1, - local_B_48_we1, - local_B_48_d1, - local_B_47_address0, - local_B_47_ce0, - local_B_47_we0, - local_B_47_d0, - local_B_47_address1, - local_B_47_ce1, - local_B_47_we1, - local_B_47_d1, - local_B_46_address0, - local_B_46_ce0, - local_B_46_we0, - local_B_46_d0, - local_B_46_address1, - local_B_46_ce1, - local_B_46_we1, - local_B_46_d1, - local_B_45_address0, - local_B_45_ce0, - local_B_45_we0, - local_B_45_d0, - local_B_45_address1, - local_B_45_ce1, - local_B_45_we1, - local_B_45_d1, - local_B_44_address0, - local_B_44_ce0, - local_B_44_we0, - local_B_44_d0, - local_B_44_address1, - local_B_44_ce1, - local_B_44_we1, - local_B_44_d1, - local_B_43_address0, - local_B_43_ce0, - local_B_43_we0, - local_B_43_d0, - local_B_43_address1, - local_B_43_ce1, - local_B_43_we1, - local_B_43_d1, - local_B_42_address0, - local_B_42_ce0, - local_B_42_we0, - local_B_42_d0, - local_B_42_address1, - local_B_42_ce1, - local_B_42_we1, - local_B_42_d1, - local_B_41_address0, - local_B_41_ce0, - local_B_41_we0, - local_B_41_d0, - local_B_41_address1, - local_B_41_ce1, - local_B_41_we1, - local_B_41_d1, - local_B_40_address0, - local_B_40_ce0, - local_B_40_we0, - local_B_40_d0, - local_B_40_address1, - local_B_40_ce1, - local_B_40_we1, - local_B_40_d1, - local_B_39_address0, - local_B_39_ce0, - local_B_39_we0, - local_B_39_d0, - local_B_39_address1, - local_B_39_ce1, - local_B_39_we1, - local_B_39_d1, - local_B_38_address0, - local_B_38_ce0, - local_B_38_we0, - local_B_38_d0, - local_B_38_address1, - local_B_38_ce1, - local_B_38_we1, - local_B_38_d1, - local_B_37_address0, - local_B_37_ce0, - local_B_37_we0, - local_B_37_d0, - local_B_37_address1, - local_B_37_ce1, - local_B_37_we1, - local_B_37_d1, - local_B_36_address0, - local_B_36_ce0, - local_B_36_we0, - local_B_36_d0, - local_B_36_address1, - local_B_36_ce1, - local_B_36_we1, - local_B_36_d1, - local_B_35_address0, - local_B_35_ce0, - local_B_35_we0, - local_B_35_d0, - local_B_35_address1, - local_B_35_ce1, - local_B_35_we1, - local_B_35_d1, - local_B_34_address0, - local_B_34_ce0, - local_B_34_we0, - local_B_34_d0, - local_B_34_address1, - local_B_34_ce1, - local_B_34_we1, - local_B_34_d1, - local_B_33_address0, - local_B_33_ce0, - local_B_33_we0, - local_B_33_d0, - local_B_33_address1, - local_B_33_ce1, - local_B_33_we1, - local_B_33_d1, - local_B_32_address0, - local_B_32_ce0, - local_B_32_we0, - local_B_32_d0, - local_B_32_address1, - local_B_32_ce1, - local_B_32_we1, - local_B_32_d1, - local_B_31_address0, - local_B_31_ce0, - local_B_31_we0, - local_B_31_d0, - local_B_31_address1, - local_B_31_ce1, - local_B_31_we1, - local_B_31_d1, - local_B_30_address0, - local_B_30_ce0, - local_B_30_we0, - local_B_30_d0, - local_B_30_address1, - local_B_30_ce1, - local_B_30_we1, - local_B_30_d1, - local_B_29_address0, - local_B_29_ce0, - local_B_29_we0, - local_B_29_d0, - local_B_29_address1, - local_B_29_ce1, - local_B_29_we1, - local_B_29_d1, - local_B_28_address0, - local_B_28_ce0, - local_B_28_we0, - local_B_28_d0, - local_B_28_address1, - local_B_28_ce1, - local_B_28_we1, - local_B_28_d1, - local_B_27_address0, - local_B_27_ce0, - local_B_27_we0, - local_B_27_d0, - local_B_27_address1, - local_B_27_ce1, - local_B_27_we1, - local_B_27_d1, - local_B_26_address0, - local_B_26_ce0, - local_B_26_we0, - local_B_26_d0, - local_B_26_address1, - local_B_26_ce1, - local_B_26_we1, - local_B_26_d1, - local_B_25_address0, - local_B_25_ce0, - local_B_25_we0, - local_B_25_d0, - local_B_25_address1, - local_B_25_ce1, - local_B_25_we1, - local_B_25_d1, - local_B_24_address0, - local_B_24_ce0, - local_B_24_we0, - local_B_24_d0, - local_B_24_address1, - local_B_24_ce1, - local_B_24_we1, - local_B_24_d1, - local_B_23_address0, - local_B_23_ce0, - local_B_23_we0, - local_B_23_d0, - local_B_23_address1, - local_B_23_ce1, - local_B_23_we1, - local_B_23_d1, - local_B_22_address0, - local_B_22_ce0, - local_B_22_we0, - local_B_22_d0, - local_B_22_address1, - local_B_22_ce1, - local_B_22_we1, - local_B_22_d1, - local_B_21_address0, - local_B_21_ce0, - local_B_21_we0, - local_B_21_d0, - local_B_21_address1, - local_B_21_ce1, - local_B_21_we1, - local_B_21_d1, - local_B_20_address0, - local_B_20_ce0, - local_B_20_we0, - local_B_20_d0, - local_B_20_address1, - local_B_20_ce1, - local_B_20_we1, - local_B_20_d1, - local_B_19_address0, - local_B_19_ce0, - local_B_19_we0, - local_B_19_d0, - local_B_19_address1, - local_B_19_ce1, - local_B_19_we1, - local_B_19_d1, - local_B_18_address0, - local_B_18_ce0, - local_B_18_we0, - local_B_18_d0, - local_B_18_address1, - local_B_18_ce1, - local_B_18_we1, - local_B_18_d1, - local_B_17_address0, - local_B_17_ce0, - local_B_17_we0, - local_B_17_d0, - local_B_17_address1, - local_B_17_ce1, - local_B_17_we1, - local_B_17_d1, - local_B_16_address0, - local_B_16_ce0, - local_B_16_we0, - local_B_16_d0, - local_B_16_address1, - local_B_16_ce1, - local_B_16_we1, - local_B_16_d1, - local_B_15_address0, - local_B_15_ce0, - local_B_15_we0, - local_B_15_d0, - local_B_15_address1, - local_B_15_ce1, - local_B_15_we1, - local_B_15_d1, - local_B_14_address0, - local_B_14_ce0, - local_B_14_we0, - local_B_14_d0, - local_B_14_address1, - local_B_14_ce1, - local_B_14_we1, - local_B_14_d1, - local_B_13_address0, - local_B_13_ce0, - local_B_13_we0, - local_B_13_d0, - local_B_13_address1, - local_B_13_ce1, - local_B_13_we1, - local_B_13_d1, - local_B_12_address0, - local_B_12_ce0, - local_B_12_we0, - local_B_12_d0, - local_B_12_address1, - local_B_12_ce1, - local_B_12_we1, - local_B_12_d1, - local_B_11_address0, - local_B_11_ce0, - local_B_11_we0, - local_B_11_d0, - local_B_11_address1, - local_B_11_ce1, - local_B_11_we1, - local_B_11_d1, - local_B_10_address0, - local_B_10_ce0, - local_B_10_we0, - local_B_10_d0, - local_B_10_address1, - local_B_10_ce1, - local_B_10_we1, - local_B_10_d1, - local_B_9_address0, - local_B_9_ce0, - local_B_9_we0, - local_B_9_d0, - local_B_9_address1, - local_B_9_ce1, - local_B_9_we1, - local_B_9_d1, - local_B_8_address0, - local_B_8_ce0, - local_B_8_we0, - local_B_8_d0, - local_B_8_address1, - local_B_8_ce1, - local_B_8_we1, - local_B_8_d1, - local_B_7_address0, - local_B_7_ce0, - local_B_7_we0, - local_B_7_d0, - local_B_7_address1, - local_B_7_ce1, - local_B_7_we1, - local_B_7_d1, - local_B_6_address0, - local_B_6_ce0, - local_B_6_we0, - local_B_6_d0, - local_B_6_address1, - local_B_6_ce1, - local_B_6_we1, - local_B_6_d1, - local_B_5_address0, - local_B_5_ce0, - local_B_5_we0, - local_B_5_d0, - local_B_5_address1, - local_B_5_ce1, - local_B_5_we1, - local_B_5_d1, - local_B_4_address0, - local_B_4_ce0, - local_B_4_we0, - local_B_4_d0, - local_B_4_address1, - local_B_4_ce1, - local_B_4_we1, - local_B_4_d1, - local_B_3_address0, - local_B_3_ce0, - local_B_3_we0, - local_B_3_d0, - local_B_3_address1, - local_B_3_ce1, - local_B_3_we1, - local_B_3_d1, - local_B_2_address0, - local_B_2_ce0, - local_B_2_we0, - local_B_2_d0, - local_B_2_address1, - local_B_2_ce1, - local_B_2_we1, - local_B_2_d1, - local_B_1_address0, - local_B_1_ce0, - local_B_1_we0, - local_B_1_d0, - local_B_1_address1, - local_B_1_ce1, - local_B_1_we1, - local_B_1_d1, - local_B_address0, - local_B_ce0, - local_B_we0, - local_B_d0, - local_B_address1, - local_B_ce1, - local_B_we1, - local_B_d1, - sub, - fifo_B_in_0_dout, - fifo_B_in_0_empty_n, - fifo_B_in_0_read, - fifo_B_out_0_din, - fifo_B_out_0_full_n, - fifo_B_out_0_write, - fifo_B_in_1_dout, - fifo_B_in_1_empty_n, - fifo_B_in_1_read, - fifo_B_out_1_din, - fifo_B_out_1_full_n, - fifo_B_out_1_write, - fifo_B_in_2_dout, - fifo_B_in_2_empty_n, - fifo_B_in_2_read, - fifo_B_out_2_din, - fifo_B_out_2_full_n, - fifo_B_out_2_write, - fifo_B_in_3_dout, - fifo_B_in_3_empty_n, - fifo_B_in_3_read, - fifo_B_out_3_din, - fifo_B_out_3_full_n, - fifo_B_out_3_write -); - -parameter ap_ST_fsm_state1 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -output [9:0] local_B_63_address0; -output local_B_63_ce0; -output local_B_63_we0; -output [31:0] local_B_63_d0; -output [9:0] local_B_63_address1; -output local_B_63_ce1; -output local_B_63_we1; -output [31:0] local_B_63_d1; -output [9:0] local_B_62_address0; -output local_B_62_ce0; -output local_B_62_we0; -output [31:0] local_B_62_d0; -output [9:0] local_B_62_address1; -output local_B_62_ce1; -output local_B_62_we1; -output [31:0] local_B_62_d1; -output [9:0] local_B_61_address0; -output local_B_61_ce0; -output local_B_61_we0; -output [31:0] local_B_61_d0; -output [9:0] local_B_61_address1; -output local_B_61_ce1; -output local_B_61_we1; -output [31:0] local_B_61_d1; -output [9:0] local_B_60_address0; -output local_B_60_ce0; -output local_B_60_we0; -output [31:0] local_B_60_d0; -output [9:0] local_B_60_address1; -output local_B_60_ce1; -output local_B_60_we1; -output [31:0] local_B_60_d1; -output [9:0] local_B_59_address0; -output local_B_59_ce0; -output local_B_59_we0; -output [31:0] local_B_59_d0; -output [9:0] local_B_59_address1; -output local_B_59_ce1; -output local_B_59_we1; -output [31:0] local_B_59_d1; -output [9:0] local_B_58_address0; -output local_B_58_ce0; -output local_B_58_we0; -output [31:0] local_B_58_d0; -output [9:0] local_B_58_address1; -output local_B_58_ce1; -output local_B_58_we1; -output [31:0] local_B_58_d1; -output [9:0] local_B_57_address0; -output local_B_57_ce0; -output local_B_57_we0; -output [31:0] local_B_57_d0; -output [9:0] local_B_57_address1; -output local_B_57_ce1; -output local_B_57_we1; -output [31:0] local_B_57_d1; -output [9:0] local_B_56_address0; -output local_B_56_ce0; -output local_B_56_we0; -output [31:0] local_B_56_d0; -output [9:0] local_B_56_address1; -output local_B_56_ce1; -output local_B_56_we1; -output [31:0] local_B_56_d1; -output [9:0] local_B_55_address0; -output local_B_55_ce0; -output local_B_55_we0; -output [31:0] local_B_55_d0; -output [9:0] local_B_55_address1; -output local_B_55_ce1; -output local_B_55_we1; -output [31:0] local_B_55_d1; -output [9:0] local_B_54_address0; -output local_B_54_ce0; -output local_B_54_we0; -output [31:0] local_B_54_d0; -output [9:0] local_B_54_address1; -output local_B_54_ce1; -output local_B_54_we1; -output [31:0] local_B_54_d1; -output [9:0] local_B_53_address0; -output local_B_53_ce0; -output local_B_53_we0; -output [31:0] local_B_53_d0; -output [9:0] local_B_53_address1; -output local_B_53_ce1; -output local_B_53_we1; -output [31:0] local_B_53_d1; -output [9:0] local_B_52_address0; -output local_B_52_ce0; -output local_B_52_we0; -output [31:0] local_B_52_d0; -output [9:0] local_B_52_address1; -output local_B_52_ce1; -output local_B_52_we1; -output [31:0] local_B_52_d1; -output [9:0] local_B_51_address0; -output local_B_51_ce0; -output local_B_51_we0; -output [31:0] local_B_51_d0; -output [9:0] local_B_51_address1; -output local_B_51_ce1; -output local_B_51_we1; -output [31:0] local_B_51_d1; -output [9:0] local_B_50_address0; -output local_B_50_ce0; -output local_B_50_we0; -output [31:0] local_B_50_d0; -output [9:0] local_B_50_address1; -output local_B_50_ce1; -output local_B_50_we1; -output [31:0] local_B_50_d1; -output [9:0] local_B_49_address0; -output local_B_49_ce0; -output local_B_49_we0; -output [31:0] local_B_49_d0; -output [9:0] local_B_49_address1; -output local_B_49_ce1; -output local_B_49_we1; -output [31:0] local_B_49_d1; -output [9:0] local_B_48_address0; -output local_B_48_ce0; -output local_B_48_we0; -output [31:0] local_B_48_d0; -output [9:0] local_B_48_address1; -output local_B_48_ce1; -output local_B_48_we1; -output [31:0] local_B_48_d1; -output [9:0] local_B_47_address0; -output local_B_47_ce0; -output local_B_47_we0; -output [31:0] local_B_47_d0; -output [9:0] local_B_47_address1; -output local_B_47_ce1; -output local_B_47_we1; -output [31:0] local_B_47_d1; -output [9:0] local_B_46_address0; -output local_B_46_ce0; -output local_B_46_we0; -output [31:0] local_B_46_d0; -output [9:0] local_B_46_address1; -output local_B_46_ce1; -output local_B_46_we1; -output [31:0] local_B_46_d1; -output [9:0] local_B_45_address0; -output local_B_45_ce0; -output local_B_45_we0; -output [31:0] local_B_45_d0; -output [9:0] local_B_45_address1; -output local_B_45_ce1; -output local_B_45_we1; -output [31:0] local_B_45_d1; -output [9:0] local_B_44_address0; -output local_B_44_ce0; -output local_B_44_we0; -output [31:0] local_B_44_d0; -output [9:0] local_B_44_address1; -output local_B_44_ce1; -output local_B_44_we1; -output [31:0] local_B_44_d1; -output [9:0] local_B_43_address0; -output local_B_43_ce0; -output local_B_43_we0; -output [31:0] local_B_43_d0; -output [9:0] local_B_43_address1; -output local_B_43_ce1; -output local_B_43_we1; -output [31:0] local_B_43_d1; -output [9:0] local_B_42_address0; -output local_B_42_ce0; -output local_B_42_we0; -output [31:0] local_B_42_d0; -output [9:0] local_B_42_address1; -output local_B_42_ce1; -output local_B_42_we1; -output [31:0] local_B_42_d1; -output [9:0] local_B_41_address0; -output local_B_41_ce0; -output local_B_41_we0; -output [31:0] local_B_41_d0; -output [9:0] local_B_41_address1; -output local_B_41_ce1; -output local_B_41_we1; -output [31:0] local_B_41_d1; -output [9:0] local_B_40_address0; -output local_B_40_ce0; -output local_B_40_we0; -output [31:0] local_B_40_d0; -output [9:0] local_B_40_address1; -output local_B_40_ce1; -output local_B_40_we1; -output [31:0] local_B_40_d1; -output [9:0] local_B_39_address0; -output local_B_39_ce0; -output local_B_39_we0; -output [31:0] local_B_39_d0; -output [9:0] local_B_39_address1; -output local_B_39_ce1; -output local_B_39_we1; -output [31:0] local_B_39_d1; -output [9:0] local_B_38_address0; -output local_B_38_ce0; -output local_B_38_we0; -output [31:0] local_B_38_d0; -output [9:0] local_B_38_address1; -output local_B_38_ce1; -output local_B_38_we1; -output [31:0] local_B_38_d1; -output [9:0] local_B_37_address0; -output local_B_37_ce0; -output local_B_37_we0; -output [31:0] local_B_37_d0; -output [9:0] local_B_37_address1; -output local_B_37_ce1; -output local_B_37_we1; -output [31:0] local_B_37_d1; -output [9:0] local_B_36_address0; -output local_B_36_ce0; -output local_B_36_we0; -output [31:0] local_B_36_d0; -output [9:0] local_B_36_address1; -output local_B_36_ce1; -output local_B_36_we1; -output [31:0] local_B_36_d1; -output [9:0] local_B_35_address0; -output local_B_35_ce0; -output local_B_35_we0; -output [31:0] local_B_35_d0; -output [9:0] local_B_35_address1; -output local_B_35_ce1; -output local_B_35_we1; -output [31:0] local_B_35_d1; -output [9:0] local_B_34_address0; -output local_B_34_ce0; -output local_B_34_we0; -output [31:0] local_B_34_d0; -output [9:0] local_B_34_address1; -output local_B_34_ce1; -output local_B_34_we1; -output [31:0] local_B_34_d1; -output [9:0] local_B_33_address0; -output local_B_33_ce0; -output local_B_33_we0; -output [31:0] local_B_33_d0; -output [9:0] local_B_33_address1; -output local_B_33_ce1; -output local_B_33_we1; -output [31:0] local_B_33_d1; -output [9:0] local_B_32_address0; -output local_B_32_ce0; -output local_B_32_we0; -output [31:0] local_B_32_d0; -output [9:0] local_B_32_address1; -output local_B_32_ce1; -output local_B_32_we1; -output [31:0] local_B_32_d1; -output [9:0] local_B_31_address0; -output local_B_31_ce0; -output local_B_31_we0; -output [31:0] local_B_31_d0; -output [9:0] local_B_31_address1; -output local_B_31_ce1; -output local_B_31_we1; -output [31:0] local_B_31_d1; -output [9:0] local_B_30_address0; -output local_B_30_ce0; -output local_B_30_we0; -output [31:0] local_B_30_d0; -output [9:0] local_B_30_address1; -output local_B_30_ce1; -output local_B_30_we1; -output [31:0] local_B_30_d1; -output [9:0] local_B_29_address0; -output local_B_29_ce0; -output local_B_29_we0; -output [31:0] local_B_29_d0; -output [9:0] local_B_29_address1; -output local_B_29_ce1; -output local_B_29_we1; -output [31:0] local_B_29_d1; -output [9:0] local_B_28_address0; -output local_B_28_ce0; -output local_B_28_we0; -output [31:0] local_B_28_d0; -output [9:0] local_B_28_address1; -output local_B_28_ce1; -output local_B_28_we1; -output [31:0] local_B_28_d1; -output [9:0] local_B_27_address0; -output local_B_27_ce0; -output local_B_27_we0; -output [31:0] local_B_27_d0; -output [9:0] local_B_27_address1; -output local_B_27_ce1; -output local_B_27_we1; -output [31:0] local_B_27_d1; -output [9:0] local_B_26_address0; -output local_B_26_ce0; -output local_B_26_we0; -output [31:0] local_B_26_d0; -output [9:0] local_B_26_address1; -output local_B_26_ce1; -output local_B_26_we1; -output [31:0] local_B_26_d1; -output [9:0] local_B_25_address0; -output local_B_25_ce0; -output local_B_25_we0; -output [31:0] local_B_25_d0; -output [9:0] local_B_25_address1; -output local_B_25_ce1; -output local_B_25_we1; -output [31:0] local_B_25_d1; -output [9:0] local_B_24_address0; -output local_B_24_ce0; -output local_B_24_we0; -output [31:0] local_B_24_d0; -output [9:0] local_B_24_address1; -output local_B_24_ce1; -output local_B_24_we1; -output [31:0] local_B_24_d1; -output [9:0] local_B_23_address0; -output local_B_23_ce0; -output local_B_23_we0; -output [31:0] local_B_23_d0; -output [9:0] local_B_23_address1; -output local_B_23_ce1; -output local_B_23_we1; -output [31:0] local_B_23_d1; -output [9:0] local_B_22_address0; -output local_B_22_ce0; -output local_B_22_we0; -output [31:0] local_B_22_d0; -output [9:0] local_B_22_address1; -output local_B_22_ce1; -output local_B_22_we1; -output [31:0] local_B_22_d1; -output [9:0] local_B_21_address0; -output local_B_21_ce0; -output local_B_21_we0; -output [31:0] local_B_21_d0; -output [9:0] local_B_21_address1; -output local_B_21_ce1; -output local_B_21_we1; -output [31:0] local_B_21_d1; -output [9:0] local_B_20_address0; -output local_B_20_ce0; -output local_B_20_we0; -output [31:0] local_B_20_d0; -output [9:0] local_B_20_address1; -output local_B_20_ce1; -output local_B_20_we1; -output [31:0] local_B_20_d1; -output [9:0] local_B_19_address0; -output local_B_19_ce0; -output local_B_19_we0; -output [31:0] local_B_19_d0; -output [9:0] local_B_19_address1; -output local_B_19_ce1; -output local_B_19_we1; -output [31:0] local_B_19_d1; -output [9:0] local_B_18_address0; -output local_B_18_ce0; -output local_B_18_we0; -output [31:0] local_B_18_d0; -output [9:0] local_B_18_address1; -output local_B_18_ce1; -output local_B_18_we1; -output [31:0] local_B_18_d1; -output [9:0] local_B_17_address0; -output local_B_17_ce0; -output local_B_17_we0; -output [31:0] local_B_17_d0; -output [9:0] local_B_17_address1; -output local_B_17_ce1; -output local_B_17_we1; -output [31:0] local_B_17_d1; -output [9:0] local_B_16_address0; -output local_B_16_ce0; -output local_B_16_we0; -output [31:0] local_B_16_d0; -output [9:0] local_B_16_address1; -output local_B_16_ce1; -output local_B_16_we1; -output [31:0] local_B_16_d1; -output [9:0] local_B_15_address0; -output local_B_15_ce0; -output local_B_15_we0; -output [31:0] local_B_15_d0; -output [9:0] local_B_15_address1; -output local_B_15_ce1; -output local_B_15_we1; -output [31:0] local_B_15_d1; -output [9:0] local_B_14_address0; -output local_B_14_ce0; -output local_B_14_we0; -output [31:0] local_B_14_d0; -output [9:0] local_B_14_address1; -output local_B_14_ce1; -output local_B_14_we1; -output [31:0] local_B_14_d1; -output [9:0] local_B_13_address0; -output local_B_13_ce0; -output local_B_13_we0; -output [31:0] local_B_13_d0; -output [9:0] local_B_13_address1; -output local_B_13_ce1; -output local_B_13_we1; -output [31:0] local_B_13_d1; -output [9:0] local_B_12_address0; -output local_B_12_ce0; -output local_B_12_we0; -output [31:0] local_B_12_d0; -output [9:0] local_B_12_address1; -output local_B_12_ce1; -output local_B_12_we1; -output [31:0] local_B_12_d1; -output [9:0] local_B_11_address0; -output local_B_11_ce0; -output local_B_11_we0; -output [31:0] local_B_11_d0; -output [9:0] local_B_11_address1; -output local_B_11_ce1; -output local_B_11_we1; -output [31:0] local_B_11_d1; -output [9:0] local_B_10_address0; -output local_B_10_ce0; -output local_B_10_we0; -output [31:0] local_B_10_d0; -output [9:0] local_B_10_address1; -output local_B_10_ce1; -output local_B_10_we1; -output [31:0] local_B_10_d1; -output [9:0] local_B_9_address0; -output local_B_9_ce0; -output local_B_9_we0; -output [31:0] local_B_9_d0; -output [9:0] local_B_9_address1; -output local_B_9_ce1; -output local_B_9_we1; -output [31:0] local_B_9_d1; -output [9:0] local_B_8_address0; -output local_B_8_ce0; -output local_B_8_we0; -output [31:0] local_B_8_d0; -output [9:0] local_B_8_address1; -output local_B_8_ce1; -output local_B_8_we1; -output [31:0] local_B_8_d1; -output [9:0] local_B_7_address0; -output local_B_7_ce0; -output local_B_7_we0; -output [31:0] local_B_7_d0; -output [9:0] local_B_7_address1; -output local_B_7_ce1; -output local_B_7_we1; -output [31:0] local_B_7_d1; -output [9:0] local_B_6_address0; -output local_B_6_ce0; -output local_B_6_we0; -output [31:0] local_B_6_d0; -output [9:0] local_B_6_address1; -output local_B_6_ce1; -output local_B_6_we1; -output [31:0] local_B_6_d1; -output [9:0] local_B_5_address0; -output local_B_5_ce0; -output local_B_5_we0; -output [31:0] local_B_5_d0; -output [9:0] local_B_5_address1; -output local_B_5_ce1; -output local_B_5_we1; -output [31:0] local_B_5_d1; -output [9:0] local_B_4_address0; -output local_B_4_ce0; -output local_B_4_we0; -output [31:0] local_B_4_d0; -output [9:0] local_B_4_address1; -output local_B_4_ce1; -output local_B_4_we1; -output [31:0] local_B_4_d1; -output [9:0] local_B_3_address0; -output local_B_3_ce0; -output local_B_3_we0; -output [31:0] local_B_3_d0; -output [9:0] local_B_3_address1; -output local_B_3_ce1; -output local_B_3_we1; -output [31:0] local_B_3_d1; -output [9:0] local_B_2_address0; -output local_B_2_ce0; -output local_B_2_we0; -output [31:0] local_B_2_d0; -output [9:0] local_B_2_address1; -output local_B_2_ce1; -output local_B_2_we1; -output [31:0] local_B_2_d1; -output [9:0] local_B_1_address0; -output local_B_1_ce0; -output local_B_1_we0; -output [31:0] local_B_1_d0; -output [9:0] local_B_1_address1; -output local_B_1_ce1; -output local_B_1_we1; -output [31:0] local_B_1_d1; -output [9:0] local_B_address0; -output local_B_ce0; -output local_B_we0; -output [31:0] local_B_d0; -output [9:0] local_B_address1; -output local_B_ce1; -output local_B_we1; -output [31:0] local_B_d1; -input [31:0] sub; -input [512:0] fifo_B_in_0_dout; -input fifo_B_in_0_empty_n; -output fifo_B_in_0_read; -output [512:0] fifo_B_out_0_din; -input fifo_B_out_0_full_n; -output fifo_B_out_0_write; -input [512:0] fifo_B_in_1_dout; -input fifo_B_in_1_empty_n; -output fifo_B_in_1_read; -output [512:0] fifo_B_out_1_din; -input fifo_B_out_1_full_n; -output fifo_B_out_1_write; -input [512:0] fifo_B_in_2_dout; -input fifo_B_in_2_empty_n; -output fifo_B_in_2_read; -output [512:0] fifo_B_out_2_din; -input fifo_B_out_2_full_n; -output fifo_B_out_2_write; -input [512:0] fifo_B_in_3_dout; -input fifo_B_in_3_empty_n; -output fifo_B_in_3_read; -output [512:0] fifo_B_out_3_din; -input fifo_B_out_3_full_n; -output fifo_B_out_3_write; - -reg ap_idle; -reg local_B_63_ce0; -reg local_B_63_we0; -reg local_B_63_ce1; -reg local_B_63_we1; -reg local_B_62_ce0; -reg local_B_62_we0; -reg local_B_62_ce1; -reg local_B_62_we1; -reg local_B_61_ce0; -reg local_B_61_we0; -reg local_B_61_ce1; -reg local_B_61_we1; -reg local_B_60_ce0; -reg local_B_60_we0; -reg local_B_60_ce1; -reg local_B_60_we1; -reg local_B_59_ce0; -reg local_B_59_we0; -reg local_B_59_ce1; -reg local_B_59_we1; -reg local_B_58_ce0; -reg local_B_58_we0; -reg local_B_58_ce1; -reg local_B_58_we1; -reg local_B_57_ce0; -reg local_B_57_we0; -reg local_B_57_ce1; -reg local_B_57_we1; -reg local_B_56_ce0; -reg local_B_56_we0; -reg local_B_56_ce1; -reg local_B_56_we1; -reg local_B_55_ce0; -reg local_B_55_we0; -reg local_B_55_ce1; -reg local_B_55_we1; -reg local_B_54_ce0; -reg local_B_54_we0; -reg local_B_54_ce1; -reg local_B_54_we1; -reg local_B_53_ce0; -reg local_B_53_we0; -reg local_B_53_ce1; -reg local_B_53_we1; -reg local_B_52_ce0; -reg local_B_52_we0; -reg local_B_52_ce1; -reg local_B_52_we1; -reg local_B_51_ce0; -reg local_B_51_we0; -reg local_B_51_ce1; -reg local_B_51_we1; -reg local_B_50_ce0; -reg local_B_50_we0; -reg local_B_50_ce1; -reg local_B_50_we1; -reg local_B_49_ce0; -reg local_B_49_we0; -reg local_B_49_ce1; -reg local_B_49_we1; -reg local_B_48_ce0; -reg local_B_48_we0; -reg local_B_48_ce1; -reg local_B_48_we1; -reg local_B_47_ce0; -reg local_B_47_we0; -reg local_B_47_ce1; -reg local_B_47_we1; -reg local_B_46_ce0; -reg local_B_46_we0; -reg local_B_46_ce1; -reg local_B_46_we1; -reg local_B_45_ce0; -reg local_B_45_we0; -reg local_B_45_ce1; -reg local_B_45_we1; -reg local_B_44_ce0; -reg local_B_44_we0; -reg local_B_44_ce1; -reg local_B_44_we1; -reg local_B_43_ce0; -reg local_B_43_we0; -reg local_B_43_ce1; -reg local_B_43_we1; -reg local_B_42_ce0; -reg local_B_42_we0; -reg local_B_42_ce1; -reg local_B_42_we1; -reg local_B_41_ce0; -reg local_B_41_we0; -reg local_B_41_ce1; -reg local_B_41_we1; -reg local_B_40_ce0; -reg local_B_40_we0; -reg local_B_40_ce1; -reg local_B_40_we1; -reg local_B_39_ce0; -reg local_B_39_we0; -reg local_B_39_ce1; -reg local_B_39_we1; -reg local_B_38_ce0; -reg local_B_38_we0; -reg local_B_38_ce1; -reg local_B_38_we1; -reg local_B_37_ce0; -reg local_B_37_we0; -reg local_B_37_ce1; -reg local_B_37_we1; -reg local_B_36_ce0; -reg local_B_36_we0; -reg local_B_36_ce1; -reg local_B_36_we1; -reg local_B_35_ce0; -reg local_B_35_we0; -reg local_B_35_ce1; -reg local_B_35_we1; -reg local_B_34_ce0; -reg local_B_34_we0; -reg local_B_34_ce1; -reg local_B_34_we1; -reg local_B_33_ce0; -reg local_B_33_we0; -reg local_B_33_ce1; -reg local_B_33_we1; -reg local_B_32_ce0; -reg local_B_32_we0; -reg local_B_32_ce1; -reg local_B_32_we1; -reg local_B_31_ce0; -reg local_B_31_we0; -reg local_B_31_ce1; -reg local_B_31_we1; -reg local_B_30_ce0; -reg local_B_30_we0; -reg local_B_30_ce1; -reg local_B_30_we1; -reg local_B_29_ce0; -reg local_B_29_we0; -reg local_B_29_ce1; -reg local_B_29_we1; -reg local_B_28_ce0; -reg local_B_28_we0; -reg local_B_28_ce1; -reg local_B_28_we1; -reg local_B_27_ce0; -reg local_B_27_we0; -reg local_B_27_ce1; -reg local_B_27_we1; -reg local_B_26_ce0; -reg local_B_26_we0; -reg local_B_26_ce1; -reg local_B_26_we1; -reg local_B_25_ce0; -reg local_B_25_we0; -reg local_B_25_ce1; -reg local_B_25_we1; -reg local_B_24_ce0; -reg local_B_24_we0; -reg local_B_24_ce1; -reg local_B_24_we1; -reg local_B_23_ce0; -reg local_B_23_we0; -reg local_B_23_ce1; -reg local_B_23_we1; -reg local_B_22_ce0; -reg local_B_22_we0; -reg local_B_22_ce1; -reg local_B_22_we1; -reg local_B_21_ce0; -reg local_B_21_we0; -reg local_B_21_ce1; -reg local_B_21_we1; -reg local_B_20_ce0; -reg local_B_20_we0; -reg local_B_20_ce1; -reg local_B_20_we1; -reg local_B_19_ce0; -reg local_B_19_we0; -reg local_B_19_ce1; -reg local_B_19_we1; -reg local_B_18_ce0; -reg local_B_18_we0; -reg local_B_18_ce1; -reg local_B_18_we1; -reg local_B_17_ce0; -reg local_B_17_we0; -reg local_B_17_ce1; -reg local_B_17_we1; -reg local_B_16_ce0; -reg local_B_16_we0; -reg local_B_16_ce1; -reg local_B_16_we1; -reg local_B_15_ce0; -reg local_B_15_we0; -reg local_B_15_ce1; -reg local_B_15_we1; -reg local_B_14_ce0; -reg local_B_14_we0; -reg local_B_14_ce1; -reg local_B_14_we1; -reg local_B_13_ce0; -reg local_B_13_we0; -reg local_B_13_ce1; -reg local_B_13_we1; -reg local_B_12_ce0; -reg local_B_12_we0; -reg local_B_12_ce1; -reg local_B_12_we1; -reg local_B_11_ce0; -reg local_B_11_we0; -reg local_B_11_ce1; -reg local_B_11_we1; -reg local_B_10_ce0; -reg local_B_10_we0; -reg local_B_10_ce1; -reg local_B_10_we1; -reg local_B_9_ce0; -reg local_B_9_we0; -reg local_B_9_ce1; -reg local_B_9_we1; -reg local_B_8_ce0; -reg local_B_8_we0; -reg local_B_8_ce1; -reg local_B_8_we1; -reg local_B_7_ce0; -reg local_B_7_we0; -reg local_B_7_ce1; -reg local_B_7_we1; -reg local_B_6_ce0; -reg local_B_6_we0; -reg local_B_6_ce1; -reg local_B_6_we1; -reg local_B_5_ce0; -reg local_B_5_we0; -reg local_B_5_ce1; -reg local_B_5_we1; -reg local_B_4_ce0; -reg local_B_4_we0; -reg local_B_4_ce1; -reg local_B_4_we1; -reg local_B_3_ce0; -reg local_B_3_we0; -reg local_B_3_ce1; -reg local_B_3_we1; -reg local_B_2_ce0; -reg local_B_2_we0; -reg local_B_2_ce1; -reg local_B_2_we1; -reg local_B_1_ce0; -reg local_B_1_we0; -reg local_B_1_ce1; -reg local_B_1_we1; -reg local_B_ce0; -reg local_B_we0; -reg local_B_ce1; -reg local_B_we1; -reg fifo_B_in_0_read; -reg fifo_B_out_0_write; -reg fifo_B_in_1_read; -reg fifo_B_out_1_write; -reg fifo_B_in_2_read; -reg fifo_B_out_2_write; -reg fifo_B_in_3_read; -reg fifo_B_out_3_write; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -reg ap_block_state1_pp0_stage0_iter0; -wire [0:0] and_ln280_fu_2018_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -wire [63:0] zext_ln299_fu_3146_p1; -wire [0:0] and_ln290_fu_2060_p2; -wire [63:0] zext_ln299_1_fu_3220_p1; -reg [31:0] j_fu_262; -wire [31:0] j_2_fu_3288_p2; -wire ap_loop_init; -reg [31:0] ap_sig_allocacmp_j_1; -wire [0:0] b_2048_ready_nbreadreq_fu_272_p3; -wire [0:0] tmp_s_nbreadreq_fu_288_p3; -wire [0:0] tmp_4_nbreadreq_fu_304_p3; -wire [0:0] tmp_8_nbreadreq_fu_320_p3; -wire [31:0] elem_val_M_elems_fu_2134_p1; -wire [31:0] bitcast_ln78_2_fu_2178_p1; -wire [31:0] bitcast_ln78_6_fu_2232_p1; -wire [31:0] bitcast_ln78_10_fu_2296_p1; -wire [31:0] elem_val_M_elems_2_fu_2401_p1; -wire [31:0] bitcast_ln78_18_fu_2445_p1; -wire [31:0] bitcast_ln78_22_fu_2499_p1; -wire [31:0] bitcast_ln78_26_fu_2563_p1; -wire [31:0] elem_val_M_elems_4_fu_2668_p1; -wire [31:0] bitcast_ln78_34_fu_2712_p1; -wire [31:0] bitcast_ln78_38_fu_2766_p1; -wire [31:0] bitcast_ln78_42_fu_2830_p1; -wire [31:0] elem_val_M_elems_6_fu_2935_p1; -wire [31:0] bitcast_ln78_50_fu_2979_p1; -wire [31:0] bitcast_ln78_54_fu_3033_p1; -wire [31:0] bitcast_ln78_58_fu_3097_p1; -wire [31:0] elem_val_M_elems_1_fu_2150_p1; -wire [31:0] bitcast_ln78_3_fu_2184_p1; -wire [31:0] bitcast_ln78_7_fu_2248_p1; -wire [31:0] bitcast_ln78_11_fu_2302_p1; -wire [31:0] elem_val_M_elems_3_fu_2417_p1; -wire [31:0] bitcast_ln78_19_fu_2451_p1; -wire [31:0] bitcast_ln78_23_fu_2515_p1; -wire [31:0] bitcast_ln78_27_fu_2569_p1; -wire [31:0] elem_val_M_elems_5_fu_2684_p1; -wire [31:0] bitcast_ln78_35_fu_2718_p1; -wire [31:0] bitcast_ln78_39_fu_2782_p1; -wire [31:0] bitcast_ln78_43_fu_2836_p1; -wire [31:0] elem_val_M_elems_7_fu_2951_p1; -wire [31:0] bitcast_ln78_51_fu_2985_p1; -wire [31:0] bitcast_ln78_55_fu_3049_p1; -wire [31:0] bitcast_ln78_59_fu_3103_p1; -wire [31:0] bitcast_ln78_fu_2166_p1; -wire [31:0] bitcast_ln78_4_fu_2200_p1; -wire [31:0] bitcast_ln78_8_fu_2264_p1; -wire [31:0] bitcast_ln78_12_fu_2308_p1; -wire [31:0] bitcast_ln78_16_fu_2433_p1; -wire [31:0] bitcast_ln78_20_fu_2467_p1; -wire [31:0] bitcast_ln78_24_fu_2531_p1; -wire [31:0] bitcast_ln78_28_fu_2575_p1; -wire [31:0] bitcast_ln78_32_fu_2700_p1; -wire [31:0] bitcast_ln78_36_fu_2734_p1; -wire [31:0] bitcast_ln78_40_fu_2798_p1; -wire [31:0] bitcast_ln78_44_fu_2842_p1; -wire [31:0] bitcast_ln78_48_fu_2967_p1; -wire [31:0] bitcast_ln78_52_fu_3001_p1; -wire [31:0] bitcast_ln78_56_fu_3065_p1; -wire [31:0] bitcast_ln78_60_fu_3109_p1; -wire [31:0] bitcast_ln78_1_fu_2172_p1; -wire [31:0] bitcast_ln78_5_fu_2216_p1; -wire [31:0] bitcast_ln78_9_fu_2280_p1; -wire [31:0] bitcast_ln78_13_fu_2314_p1; -wire [31:0] bitcast_ln78_17_fu_2439_p1; -wire [31:0] bitcast_ln78_21_fu_2483_p1; -wire [31:0] bitcast_ln78_25_fu_2547_p1; -wire [31:0] bitcast_ln78_29_fu_2581_p1; -wire [31:0] bitcast_ln78_33_fu_2706_p1; -wire [31:0] bitcast_ln78_37_fu_2750_p1; -wire [31:0] bitcast_ln78_41_fu_2814_p1; -wire [31:0] bitcast_ln78_45_fu_2848_p1; -wire [31:0] bitcast_ln78_49_fu_2973_p1; -wire [31:0] bitcast_ln78_53_fu_3017_p1; -wire [31:0] bitcast_ln78_57_fu_3081_p1; -wire [31:0] bitcast_ln78_61_fu_3115_p1; -wire [22:0] tmp_fu_1996_p4; -wire [0:0] icmp_ln280_fu_2006_p2; -wire [0:0] icmp_ln281_fu_2012_p2; -wire [0:0] and_ln290_4_fu_2030_p0; -wire [0:0] and_ln290_4_fu_2030_p1; -wire [0:0] and_ln290_5_fu_2036_p0; -wire [0:0] and_ln290_5_fu_2036_p1; -wire [0:0] and_ln290_5_fu_2036_p2; -wire [0:0] and_ln290_4_fu_2030_p2; -wire [0:0] and_ln290_2_fu_2024_p2; -wire [0:0] and_ln290_1_fu_2048_p2; -wire [0:0] and_ln290_3_fu_2054_p2; -wire [0:0] and_ln290_6_fu_2042_p2; -wire [31:0] trunc_ln78_fu_2070_p1; -wire [31:0] tmp_10_fu_2140_p4; -wire [31:0] tmp_11_fu_2156_p4; -wire [31:0] tmp_3_fu_2074_p4; -wire [31:0] tmp_5_fu_2084_p4; -wire [31:0] tmp_7_fu_2094_p4; -wire [31:0] tmp_12_fu_2190_p4; -wire [31:0] tmp_13_fu_2206_p4; -wire [31:0] tmp_14_fu_2222_p4; -wire [31:0] tmp_15_fu_2238_p4; -wire [31:0] tmp_16_fu_2254_p4; -wire [31:0] tmp_17_fu_2270_p4; -wire [31:0] tmp_18_fu_2286_p4; -wire [31:0] tmp_9_fu_2104_p4; -wire [31:0] trunc_ln2_fu_2114_p4; -wire [31:0] trunc_ln78_2_fu_2124_p4; -wire [511:0] trunc_ln146_fu_2320_p1; -wire [31:0] trunc_ln78_1_fu_2337_p1; -wire [31:0] tmp_23_fu_2407_p4; -wire [31:0] tmp_24_fu_2423_p4; -wire [31:0] tmp_19_fu_2341_p4; -wire [31:0] tmp_20_fu_2351_p4; -wire [31:0] tmp_21_fu_2361_p4; -wire [31:0] tmp_25_fu_2457_p4; -wire [31:0] tmp_26_fu_2473_p4; -wire [31:0] tmp_27_fu_2489_p4; -wire [31:0] tmp_28_fu_2505_p4; -wire [31:0] tmp_29_fu_2521_p4; -wire [31:0] tmp_30_fu_2537_p4; -wire [31:0] tmp_31_fu_2553_p4; -wire [31:0] tmp_22_fu_2371_p4; -wire [31:0] trunc_ln78_4_fu_2381_p4; -wire [31:0] trunc_ln78_5_fu_2391_p4; -wire [511:0] trunc_ln146_1_fu_2587_p1; -wire [31:0] trunc_ln78_3_fu_2604_p1; -wire [31:0] tmp_36_fu_2674_p4; -wire [31:0] tmp_37_fu_2690_p4; -wire [31:0] tmp_32_fu_2608_p4; -wire [31:0] tmp_33_fu_2618_p4; -wire [31:0] tmp_34_fu_2628_p4; -wire [31:0] tmp_38_fu_2724_p4; -wire [31:0] tmp_39_fu_2740_p4; -wire [31:0] tmp_40_fu_2756_p4; -wire [31:0] tmp_41_fu_2772_p4; -wire [31:0] tmp_42_fu_2788_p4; -wire [31:0] tmp_43_fu_2804_p4; -wire [31:0] tmp_44_fu_2820_p4; -wire [31:0] tmp_35_fu_2638_p4; -wire [31:0] trunc_ln78_8_fu_2648_p4; -wire [31:0] trunc_ln78_9_fu_2658_p4; -wire [511:0] trunc_ln146_2_fu_2854_p1; -wire [31:0] trunc_ln78_7_fu_2871_p1; -wire [31:0] tmp_49_fu_2941_p4; -wire [31:0] tmp_50_fu_2957_p4; -wire [31:0] tmp_45_fu_2875_p4; -wire [31:0] tmp_46_fu_2885_p4; -wire [31:0] tmp_47_fu_2895_p4; -wire [31:0] tmp_51_fu_2991_p4; -wire [31:0] tmp_52_fu_3007_p4; -wire [31:0] tmp_53_fu_3023_p4; -wire [31:0] tmp_54_fu_3039_p4; -wire [31:0] tmp_55_fu_3055_p4; -wire [31:0] tmp_56_fu_3071_p4; -wire [31:0] tmp_57_fu_3087_p4; -wire [31:0] tmp_48_fu_2905_p4; -wire [31:0] trunc_ln78_6_fu_2915_p4; -wire [31:0] trunc_ln78_s_fu_2925_p4; -wire [511:0] trunc_ln146_3_fu_3121_p1; -wire [8:0] trunc_ln299_fu_3134_p1; -wire [9:0] shl_ln_fu_3138_p3; -wire [9:0] or_ln299_fu_3214_p2; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_start_int; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_done_reg = 1'b0; -end - -PEG_Bmtx_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2))) begin - j_fu_262 <= j_2_fu_3288_p2; - end else if ((ap_loop_init == 1'b1)) begin - j_fu_262 <= 32'd0; - end - end -end - -always @ (*) begin - if ((ap_start_int == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'd0 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_init == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_sig_allocacmp_j_1 = 32'd0; - end else begin - ap_sig_allocacmp_j_1 = j_fu_262; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (fifo_B_in_0_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - fifo_B_in_0_read = 1'b1; - end else begin - fifo_B_in_0_read = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (fifo_B_in_1_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - fifo_B_in_1_read = 1'b1; - end else begin - fifo_B_in_1_read = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (fifo_B_in_2_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - fifo_B_in_2_read = 1'b1; - end else begin - fifo_B_in_2_read = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (fifo_B_in_3_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - fifo_B_in_3_read = 1'b1; - end else begin - fifo_B_in_3_read = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (fifo_B_out_0_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - fifo_B_out_0_write = 1'b1; - end else begin - fifo_B_out_0_write = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (fifo_B_out_1_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - fifo_B_out_1_write = 1'b1; - end else begin - fifo_B_out_1_write = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (fifo_B_out_2_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - fifo_B_out_2_write = 1'b1; - end else begin - fifo_B_out_2_write = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (fifo_B_out_3_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - fifo_B_out_3_write = 1'b1; - end else begin - fifo_B_out_3_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_10_ce0 = 1'b1; - end else begin - local_B_10_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_10_ce1 = 1'b1; - end else begin - local_B_10_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_10_we0 = 1'b1; - end else begin - local_B_10_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_10_we1 = 1'b1; - end else begin - local_B_10_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_11_ce0 = 1'b1; - end else begin - local_B_11_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_11_ce1 = 1'b1; - end else begin - local_B_11_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_11_we0 = 1'b1; - end else begin - local_B_11_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_11_we1 = 1'b1; - end else begin - local_B_11_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_12_ce0 = 1'b1; - end else begin - local_B_12_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_12_ce1 = 1'b1; - end else begin - local_B_12_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_12_we0 = 1'b1; - end else begin - local_B_12_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_12_we1 = 1'b1; - end else begin - local_B_12_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_13_ce0 = 1'b1; - end else begin - local_B_13_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_13_ce1 = 1'b1; - end else begin - local_B_13_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_13_we0 = 1'b1; - end else begin - local_B_13_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_13_we1 = 1'b1; - end else begin - local_B_13_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_14_ce0 = 1'b1; - end else begin - local_B_14_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_14_ce1 = 1'b1; - end else begin - local_B_14_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_14_we0 = 1'b1; - end else begin - local_B_14_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_14_we1 = 1'b1; - end else begin - local_B_14_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_15_ce0 = 1'b1; - end else begin - local_B_15_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_15_ce1 = 1'b1; - end else begin - local_B_15_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_15_we0 = 1'b1; - end else begin - local_B_15_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_15_we1 = 1'b1; - end else begin - local_B_15_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_16_ce0 = 1'b1; - end else begin - local_B_16_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_16_ce1 = 1'b1; - end else begin - local_B_16_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_16_we0 = 1'b1; - end else begin - local_B_16_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_16_we1 = 1'b1; - end else begin - local_B_16_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_17_ce0 = 1'b1; - end else begin - local_B_17_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_17_ce1 = 1'b1; - end else begin - local_B_17_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_17_we0 = 1'b1; - end else begin - local_B_17_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_17_we1 = 1'b1; - end else begin - local_B_17_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_18_ce0 = 1'b1; - end else begin - local_B_18_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_18_ce1 = 1'b1; - end else begin - local_B_18_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_18_we0 = 1'b1; - end else begin - local_B_18_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_18_we1 = 1'b1; - end else begin - local_B_18_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_19_ce0 = 1'b1; - end else begin - local_B_19_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_19_ce1 = 1'b1; - end else begin - local_B_19_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_19_we0 = 1'b1; - end else begin - local_B_19_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_19_we1 = 1'b1; - end else begin - local_B_19_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_1_ce0 = 1'b1; - end else begin - local_B_1_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_1_ce1 = 1'b1; - end else begin - local_B_1_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_1_we0 = 1'b1; - end else begin - local_B_1_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_1_we1 = 1'b1; - end else begin - local_B_1_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_20_ce0 = 1'b1; - end else begin - local_B_20_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_20_ce1 = 1'b1; - end else begin - local_B_20_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_20_we0 = 1'b1; - end else begin - local_B_20_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_20_we1 = 1'b1; - end else begin - local_B_20_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_21_ce0 = 1'b1; - end else begin - local_B_21_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_21_ce1 = 1'b1; - end else begin - local_B_21_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_21_we0 = 1'b1; - end else begin - local_B_21_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_21_we1 = 1'b1; - end else begin - local_B_21_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_22_ce0 = 1'b1; - end else begin - local_B_22_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_22_ce1 = 1'b1; - end else begin - local_B_22_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_22_we0 = 1'b1; - end else begin - local_B_22_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_22_we1 = 1'b1; - end else begin - local_B_22_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_23_ce0 = 1'b1; - end else begin - local_B_23_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_23_ce1 = 1'b1; - end else begin - local_B_23_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_23_we0 = 1'b1; - end else begin - local_B_23_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_23_we1 = 1'b1; - end else begin - local_B_23_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_24_ce0 = 1'b1; - end else begin - local_B_24_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_24_ce1 = 1'b1; - end else begin - local_B_24_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_24_we0 = 1'b1; - end else begin - local_B_24_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_24_we1 = 1'b1; - end else begin - local_B_24_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_25_ce0 = 1'b1; - end else begin - local_B_25_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_25_ce1 = 1'b1; - end else begin - local_B_25_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_25_we0 = 1'b1; - end else begin - local_B_25_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_25_we1 = 1'b1; - end else begin - local_B_25_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_26_ce0 = 1'b1; - end else begin - local_B_26_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_26_ce1 = 1'b1; - end else begin - local_B_26_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_26_we0 = 1'b1; - end else begin - local_B_26_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_26_we1 = 1'b1; - end else begin - local_B_26_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_27_ce0 = 1'b1; - end else begin - local_B_27_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_27_ce1 = 1'b1; - end else begin - local_B_27_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_27_we0 = 1'b1; - end else begin - local_B_27_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_27_we1 = 1'b1; - end else begin - local_B_27_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_28_ce0 = 1'b1; - end else begin - local_B_28_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_28_ce1 = 1'b1; - end else begin - local_B_28_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_28_we0 = 1'b1; - end else begin - local_B_28_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_28_we1 = 1'b1; - end else begin - local_B_28_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_29_ce0 = 1'b1; - end else begin - local_B_29_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_29_ce1 = 1'b1; - end else begin - local_B_29_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_29_we0 = 1'b1; - end else begin - local_B_29_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_29_we1 = 1'b1; - end else begin - local_B_29_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_2_ce0 = 1'b1; - end else begin - local_B_2_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_2_ce1 = 1'b1; - end else begin - local_B_2_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_2_we0 = 1'b1; - end else begin - local_B_2_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_2_we1 = 1'b1; - end else begin - local_B_2_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_30_ce0 = 1'b1; - end else begin - local_B_30_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_30_ce1 = 1'b1; - end else begin - local_B_30_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_30_we0 = 1'b1; - end else begin - local_B_30_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_30_we1 = 1'b1; - end else begin - local_B_30_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_31_ce0 = 1'b1; - end else begin - local_B_31_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_31_ce1 = 1'b1; - end else begin - local_B_31_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_31_we0 = 1'b1; - end else begin - local_B_31_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_31_we1 = 1'b1; - end else begin - local_B_31_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_32_ce0 = 1'b1; - end else begin - local_B_32_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_32_ce1 = 1'b1; - end else begin - local_B_32_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_32_we0 = 1'b1; - end else begin - local_B_32_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_32_we1 = 1'b1; - end else begin - local_B_32_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_33_ce0 = 1'b1; - end else begin - local_B_33_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_33_ce1 = 1'b1; - end else begin - local_B_33_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_33_we0 = 1'b1; - end else begin - local_B_33_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_33_we1 = 1'b1; - end else begin - local_B_33_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_34_ce0 = 1'b1; - end else begin - local_B_34_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_34_ce1 = 1'b1; - end else begin - local_B_34_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_34_we0 = 1'b1; - end else begin - local_B_34_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_34_we1 = 1'b1; - end else begin - local_B_34_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_35_ce0 = 1'b1; - end else begin - local_B_35_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_35_ce1 = 1'b1; - end else begin - local_B_35_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_35_we0 = 1'b1; - end else begin - local_B_35_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_35_we1 = 1'b1; - end else begin - local_B_35_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_36_ce0 = 1'b1; - end else begin - local_B_36_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_36_ce1 = 1'b1; - end else begin - local_B_36_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_36_we0 = 1'b1; - end else begin - local_B_36_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_36_we1 = 1'b1; - end else begin - local_B_36_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_37_ce0 = 1'b1; - end else begin - local_B_37_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_37_ce1 = 1'b1; - end else begin - local_B_37_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_37_we0 = 1'b1; - end else begin - local_B_37_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_37_we1 = 1'b1; - end else begin - local_B_37_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_38_ce0 = 1'b1; - end else begin - local_B_38_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_38_ce1 = 1'b1; - end else begin - local_B_38_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_38_we0 = 1'b1; - end else begin - local_B_38_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_38_we1 = 1'b1; - end else begin - local_B_38_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_39_ce0 = 1'b1; - end else begin - local_B_39_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_39_ce1 = 1'b1; - end else begin - local_B_39_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_39_we0 = 1'b1; - end else begin - local_B_39_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_39_we1 = 1'b1; - end else begin - local_B_39_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_3_ce0 = 1'b1; - end else begin - local_B_3_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_3_ce1 = 1'b1; - end else begin - local_B_3_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_3_we0 = 1'b1; - end else begin - local_B_3_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_3_we1 = 1'b1; - end else begin - local_B_3_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_40_ce0 = 1'b1; - end else begin - local_B_40_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_40_ce1 = 1'b1; - end else begin - local_B_40_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_40_we0 = 1'b1; - end else begin - local_B_40_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_40_we1 = 1'b1; - end else begin - local_B_40_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_41_ce0 = 1'b1; - end else begin - local_B_41_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_41_ce1 = 1'b1; - end else begin - local_B_41_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_41_we0 = 1'b1; - end else begin - local_B_41_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_41_we1 = 1'b1; - end else begin - local_B_41_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_42_ce0 = 1'b1; - end else begin - local_B_42_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_42_ce1 = 1'b1; - end else begin - local_B_42_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_42_we0 = 1'b1; - end else begin - local_B_42_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_42_we1 = 1'b1; - end else begin - local_B_42_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_43_ce0 = 1'b1; - end else begin - local_B_43_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_43_ce1 = 1'b1; - end else begin - local_B_43_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_43_we0 = 1'b1; - end else begin - local_B_43_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_43_we1 = 1'b1; - end else begin - local_B_43_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_44_ce0 = 1'b1; - end else begin - local_B_44_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_44_ce1 = 1'b1; - end else begin - local_B_44_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_44_we0 = 1'b1; - end else begin - local_B_44_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_44_we1 = 1'b1; - end else begin - local_B_44_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_45_ce0 = 1'b1; - end else begin - local_B_45_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_45_ce1 = 1'b1; - end else begin - local_B_45_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_45_we0 = 1'b1; - end else begin - local_B_45_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_45_we1 = 1'b1; - end else begin - local_B_45_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_46_ce0 = 1'b1; - end else begin - local_B_46_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_46_ce1 = 1'b1; - end else begin - local_B_46_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_46_we0 = 1'b1; - end else begin - local_B_46_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_46_we1 = 1'b1; - end else begin - local_B_46_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_47_ce0 = 1'b1; - end else begin - local_B_47_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_47_ce1 = 1'b1; - end else begin - local_B_47_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_47_we0 = 1'b1; - end else begin - local_B_47_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_47_we1 = 1'b1; - end else begin - local_B_47_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_48_ce0 = 1'b1; - end else begin - local_B_48_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_48_ce1 = 1'b1; - end else begin - local_B_48_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_48_we0 = 1'b1; - end else begin - local_B_48_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_48_we1 = 1'b1; - end else begin - local_B_48_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_49_ce0 = 1'b1; - end else begin - local_B_49_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_49_ce1 = 1'b1; - end else begin - local_B_49_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_49_we0 = 1'b1; - end else begin - local_B_49_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_49_we1 = 1'b1; - end else begin - local_B_49_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_4_ce0 = 1'b1; - end else begin - local_B_4_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_4_ce1 = 1'b1; - end else begin - local_B_4_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_4_we0 = 1'b1; - end else begin - local_B_4_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_4_we1 = 1'b1; - end else begin - local_B_4_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_50_ce0 = 1'b1; - end else begin - local_B_50_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_50_ce1 = 1'b1; - end else begin - local_B_50_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_50_we0 = 1'b1; - end else begin - local_B_50_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_50_we1 = 1'b1; - end else begin - local_B_50_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_51_ce0 = 1'b1; - end else begin - local_B_51_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_51_ce1 = 1'b1; - end else begin - local_B_51_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_51_we0 = 1'b1; - end else begin - local_B_51_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_51_we1 = 1'b1; - end else begin - local_B_51_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_52_ce0 = 1'b1; - end else begin - local_B_52_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_52_ce1 = 1'b1; - end else begin - local_B_52_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_52_we0 = 1'b1; - end else begin - local_B_52_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_52_we1 = 1'b1; - end else begin - local_B_52_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_53_ce0 = 1'b1; - end else begin - local_B_53_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_53_ce1 = 1'b1; - end else begin - local_B_53_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_53_we0 = 1'b1; - end else begin - local_B_53_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_53_we1 = 1'b1; - end else begin - local_B_53_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_54_ce0 = 1'b1; - end else begin - local_B_54_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_54_ce1 = 1'b1; - end else begin - local_B_54_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_54_we0 = 1'b1; - end else begin - local_B_54_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_54_we1 = 1'b1; - end else begin - local_B_54_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_55_ce0 = 1'b1; - end else begin - local_B_55_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_55_ce1 = 1'b1; - end else begin - local_B_55_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_55_we0 = 1'b1; - end else begin - local_B_55_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_55_we1 = 1'b1; - end else begin - local_B_55_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_56_ce0 = 1'b1; - end else begin - local_B_56_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_56_ce1 = 1'b1; - end else begin - local_B_56_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_56_we0 = 1'b1; - end else begin - local_B_56_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_56_we1 = 1'b1; - end else begin - local_B_56_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_57_ce0 = 1'b1; - end else begin - local_B_57_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_57_ce1 = 1'b1; - end else begin - local_B_57_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_57_we0 = 1'b1; - end else begin - local_B_57_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_57_we1 = 1'b1; - end else begin - local_B_57_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_58_ce0 = 1'b1; - end else begin - local_B_58_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_58_ce1 = 1'b1; - end else begin - local_B_58_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_58_we0 = 1'b1; - end else begin - local_B_58_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_58_we1 = 1'b1; - end else begin - local_B_58_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_59_ce0 = 1'b1; - end else begin - local_B_59_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_59_ce1 = 1'b1; - end else begin - local_B_59_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_59_we0 = 1'b1; - end else begin - local_B_59_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_59_we1 = 1'b1; - end else begin - local_B_59_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_5_ce0 = 1'b1; - end else begin - local_B_5_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_5_ce1 = 1'b1; - end else begin - local_B_5_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_5_we0 = 1'b1; - end else begin - local_B_5_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_5_we1 = 1'b1; - end else begin - local_B_5_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_60_ce0 = 1'b1; - end else begin - local_B_60_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_60_ce1 = 1'b1; - end else begin - local_B_60_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_60_we0 = 1'b1; - end else begin - local_B_60_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_60_we1 = 1'b1; - end else begin - local_B_60_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_61_ce0 = 1'b1; - end else begin - local_B_61_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_61_ce1 = 1'b1; - end else begin - local_B_61_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_61_we0 = 1'b1; - end else begin - local_B_61_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_61_we1 = 1'b1; - end else begin - local_B_61_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_62_ce0 = 1'b1; - end else begin - local_B_62_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_62_ce1 = 1'b1; - end else begin - local_B_62_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_62_we0 = 1'b1; - end else begin - local_B_62_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_62_we1 = 1'b1; - end else begin - local_B_62_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_63_ce0 = 1'b1; - end else begin - local_B_63_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_63_ce1 = 1'b1; - end else begin - local_B_63_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_63_we0 = 1'b1; - end else begin - local_B_63_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_63_we1 = 1'b1; - end else begin - local_B_63_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_6_ce0 = 1'b1; - end else begin - local_B_6_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_6_ce1 = 1'b1; - end else begin - local_B_6_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_6_we0 = 1'b1; - end else begin - local_B_6_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_6_we1 = 1'b1; - end else begin - local_B_6_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_7_ce0 = 1'b1; - end else begin - local_B_7_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_7_ce1 = 1'b1; - end else begin - local_B_7_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_7_we0 = 1'b1; - end else begin - local_B_7_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_7_we1 = 1'b1; - end else begin - local_B_7_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_8_ce0 = 1'b1; - end else begin - local_B_8_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_8_ce1 = 1'b1; - end else begin - local_B_8_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_8_we0 = 1'b1; - end else begin - local_B_8_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_8_we1 = 1'b1; - end else begin - local_B_8_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_9_ce0 = 1'b1; - end else begin - local_B_9_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_9_ce1 = 1'b1; - end else begin - local_B_9_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_9_we0 = 1'b1; - end else begin - local_B_9_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_9_we1 = 1'b1; - end else begin - local_B_9_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_ce0 = 1'b1; - end else begin - local_B_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_ce1 = 1'b1; - end else begin - local_B_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_we0 = 1'b1; - end else begin - local_B_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln290_fu_2060_p2) & (1'd1 == and_ln280_fu_2018_p2) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin - local_B_we1 = 1'b1; - end else begin - local_B_we1 = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - ap_NS_fsm = ap_ST_fsm_state1; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign and_ln280_fu_2018_p2 = (icmp_ln281_fu_2012_p2 & icmp_ln280_fu_2006_p2); - -assign and_ln290_1_fu_2048_p2 = (tmp_4_nbreadreq_fu_304_p3 & and_ln290_2_fu_2024_p2); - -assign and_ln290_2_fu_2024_p2 = (tmp_s_nbreadreq_fu_288_p3 & tmp_8_nbreadreq_fu_320_p3); - -assign and_ln290_3_fu_2054_p2 = (b_2048_ready_nbreadreq_fu_272_p3 & and_ln290_1_fu_2048_p2); - -assign and_ln290_4_fu_2030_p0 = fifo_B_out_3_full_n; - -assign and_ln290_4_fu_2030_p1 = fifo_B_out_2_full_n; - -assign and_ln290_4_fu_2030_p2 = (and_ln290_4_fu_2030_p1 & and_ln290_4_fu_2030_p0); - -assign and_ln290_5_fu_2036_p0 = fifo_B_out_1_full_n; - -assign and_ln290_5_fu_2036_p1 = fifo_B_out_0_full_n; - -assign and_ln290_5_fu_2036_p2 = (and_ln290_5_fu_2036_p1 & and_ln290_5_fu_2036_p0); - -assign and_ln290_6_fu_2042_p2 = (and_ln290_5_fu_2036_p2 & and_ln290_4_fu_2030_p2); - -assign and_ln290_fu_2060_p2 = (and_ln290_6_fu_2042_p2 & and_ln290_3_fu_2054_p2); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -always @ (*) begin - ap_block_state1_pp0_stage0_iter0 = (ap_start_int == 1'b0); -end - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -assign b_2048_ready_nbreadreq_fu_272_p3 = fifo_B_in_0_empty_n; - -assign bitcast_ln78_10_fu_2296_p1 = tmp_18_fu_2286_p4; - -assign bitcast_ln78_11_fu_2302_p1 = tmp_9_fu_2104_p4; - -assign bitcast_ln78_12_fu_2308_p1 = trunc_ln2_fu_2114_p4; - -assign bitcast_ln78_13_fu_2314_p1 = trunc_ln78_2_fu_2124_p4; - -assign bitcast_ln78_16_fu_2433_p1 = tmp_24_fu_2423_p4; - -assign bitcast_ln78_17_fu_2439_p1 = tmp_19_fu_2341_p4; - -assign bitcast_ln78_18_fu_2445_p1 = tmp_20_fu_2351_p4; - -assign bitcast_ln78_19_fu_2451_p1 = tmp_21_fu_2361_p4; - -assign bitcast_ln78_1_fu_2172_p1 = tmp_3_fu_2074_p4; - -assign bitcast_ln78_20_fu_2467_p1 = tmp_25_fu_2457_p4; - -assign bitcast_ln78_21_fu_2483_p1 = tmp_26_fu_2473_p4; - -assign bitcast_ln78_22_fu_2499_p1 = tmp_27_fu_2489_p4; - -assign bitcast_ln78_23_fu_2515_p1 = tmp_28_fu_2505_p4; - -assign bitcast_ln78_24_fu_2531_p1 = tmp_29_fu_2521_p4; - -assign bitcast_ln78_25_fu_2547_p1 = tmp_30_fu_2537_p4; - -assign bitcast_ln78_26_fu_2563_p1 = tmp_31_fu_2553_p4; - -assign bitcast_ln78_27_fu_2569_p1 = tmp_22_fu_2371_p4; - -assign bitcast_ln78_28_fu_2575_p1 = trunc_ln78_4_fu_2381_p4; - -assign bitcast_ln78_29_fu_2581_p1 = trunc_ln78_5_fu_2391_p4; - -assign bitcast_ln78_2_fu_2178_p1 = tmp_5_fu_2084_p4; - -assign bitcast_ln78_32_fu_2700_p1 = tmp_37_fu_2690_p4; - -assign bitcast_ln78_33_fu_2706_p1 = tmp_32_fu_2608_p4; - -assign bitcast_ln78_34_fu_2712_p1 = tmp_33_fu_2618_p4; - -assign bitcast_ln78_35_fu_2718_p1 = tmp_34_fu_2628_p4; - -assign bitcast_ln78_36_fu_2734_p1 = tmp_38_fu_2724_p4; - -assign bitcast_ln78_37_fu_2750_p1 = tmp_39_fu_2740_p4; - -assign bitcast_ln78_38_fu_2766_p1 = tmp_40_fu_2756_p4; - -assign bitcast_ln78_39_fu_2782_p1 = tmp_41_fu_2772_p4; - -assign bitcast_ln78_3_fu_2184_p1 = tmp_7_fu_2094_p4; - -assign bitcast_ln78_40_fu_2798_p1 = tmp_42_fu_2788_p4; - -assign bitcast_ln78_41_fu_2814_p1 = tmp_43_fu_2804_p4; - -assign bitcast_ln78_42_fu_2830_p1 = tmp_44_fu_2820_p4; - -assign bitcast_ln78_43_fu_2836_p1 = tmp_35_fu_2638_p4; - -assign bitcast_ln78_44_fu_2842_p1 = trunc_ln78_8_fu_2648_p4; - -assign bitcast_ln78_45_fu_2848_p1 = trunc_ln78_9_fu_2658_p4; - -assign bitcast_ln78_48_fu_2967_p1 = tmp_50_fu_2957_p4; - -assign bitcast_ln78_49_fu_2973_p1 = tmp_45_fu_2875_p4; - -assign bitcast_ln78_4_fu_2200_p1 = tmp_12_fu_2190_p4; - -assign bitcast_ln78_50_fu_2979_p1 = tmp_46_fu_2885_p4; - -assign bitcast_ln78_51_fu_2985_p1 = tmp_47_fu_2895_p4; - -assign bitcast_ln78_52_fu_3001_p1 = tmp_51_fu_2991_p4; - -assign bitcast_ln78_53_fu_3017_p1 = tmp_52_fu_3007_p4; - -assign bitcast_ln78_54_fu_3033_p1 = tmp_53_fu_3023_p4; - -assign bitcast_ln78_55_fu_3049_p1 = tmp_54_fu_3039_p4; - -assign bitcast_ln78_56_fu_3065_p1 = tmp_55_fu_3055_p4; - -assign bitcast_ln78_57_fu_3081_p1 = tmp_56_fu_3071_p4; - -assign bitcast_ln78_58_fu_3097_p1 = tmp_57_fu_3087_p4; - -assign bitcast_ln78_59_fu_3103_p1 = tmp_48_fu_2905_p4; - -assign bitcast_ln78_5_fu_2216_p1 = tmp_13_fu_2206_p4; - -assign bitcast_ln78_60_fu_3109_p1 = trunc_ln78_6_fu_2915_p4; - -assign bitcast_ln78_61_fu_3115_p1 = trunc_ln78_s_fu_2925_p4; - -assign bitcast_ln78_6_fu_2232_p1 = tmp_14_fu_2222_p4; - -assign bitcast_ln78_7_fu_2248_p1 = tmp_15_fu_2238_p4; - -assign bitcast_ln78_8_fu_2264_p1 = tmp_16_fu_2254_p4; - -assign bitcast_ln78_9_fu_2280_p1 = tmp_17_fu_2270_p4; - -assign bitcast_ln78_fu_2166_p1 = tmp_11_fu_2156_p4; - -assign elem_val_M_elems_1_fu_2150_p1 = tmp_10_fu_2140_p4; - -assign elem_val_M_elems_2_fu_2401_p1 = trunc_ln78_1_fu_2337_p1; - -assign elem_val_M_elems_3_fu_2417_p1 = tmp_23_fu_2407_p4; - -assign elem_val_M_elems_4_fu_2668_p1 = trunc_ln78_3_fu_2604_p1; - -assign elem_val_M_elems_5_fu_2684_p1 = tmp_36_fu_2674_p4; - -assign elem_val_M_elems_6_fu_2935_p1 = trunc_ln78_7_fu_2871_p1; - -assign elem_val_M_elems_7_fu_2951_p1 = tmp_49_fu_2941_p4; - -assign elem_val_M_elems_fu_2134_p1 = trunc_ln78_fu_2070_p1; - -assign fifo_B_out_0_din = {{1'd0}, {trunc_ln146_fu_2320_p1}}; - -assign fifo_B_out_1_din = {{1'd0}, {trunc_ln146_1_fu_2587_p1}}; - -assign fifo_B_out_2_din = {{1'd0}, {trunc_ln146_2_fu_2854_p1}}; - -assign fifo_B_out_3_din = {{1'd0}, {trunc_ln146_3_fu_3121_p1}}; - -assign icmp_ln280_fu_2006_p2 = (($signed(tmp_fu_1996_p4) < $signed(23'd1)) ? 1'b1 : 1'b0); - -assign icmp_ln281_fu_2012_p2 = (($signed(ap_sig_allocacmp_j_1) < $signed(sub)) ? 1'b1 : 1'b0); - -assign j_2_fu_3288_p2 = (ap_sig_allocacmp_j_1 + 32'd1); - -assign local_B_10_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_10_address1 = zext_ln299_fu_3146_p1; - -assign local_B_10_d0 = bitcast_ln78_20_fu_2467_p1; - -assign local_B_10_d1 = bitcast_ln78_16_fu_2433_p1; - -assign local_B_11_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_11_address1 = zext_ln299_fu_3146_p1; - -assign local_B_11_d0 = bitcast_ln78_21_fu_2483_p1; - -assign local_B_11_d1 = bitcast_ln78_17_fu_2439_p1; - -assign local_B_12_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_12_address1 = zext_ln299_fu_3146_p1; - -assign local_B_12_d0 = bitcast_ln78_26_fu_2563_p1; - -assign local_B_12_d1 = bitcast_ln78_22_fu_2499_p1; - -assign local_B_13_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_13_address1 = zext_ln299_fu_3146_p1; - -assign local_B_13_d0 = bitcast_ln78_27_fu_2569_p1; - -assign local_B_13_d1 = bitcast_ln78_23_fu_2515_p1; - -assign local_B_14_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_14_address1 = zext_ln299_fu_3146_p1; - -assign local_B_14_d0 = bitcast_ln78_28_fu_2575_p1; - -assign local_B_14_d1 = bitcast_ln78_24_fu_2531_p1; - -assign local_B_15_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_15_address1 = zext_ln299_fu_3146_p1; - -assign local_B_15_d0 = bitcast_ln78_29_fu_2581_p1; - -assign local_B_15_d1 = bitcast_ln78_25_fu_2547_p1; - -assign local_B_16_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_16_address1 = zext_ln299_fu_3146_p1; - -assign local_B_16_d0 = bitcast_ln78_34_fu_2712_p1; - -assign local_B_16_d1 = elem_val_M_elems_4_fu_2668_p1; - -assign local_B_17_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_17_address1 = zext_ln299_fu_3146_p1; - -assign local_B_17_d0 = bitcast_ln78_35_fu_2718_p1; - -assign local_B_17_d1 = elem_val_M_elems_5_fu_2684_p1; - -assign local_B_18_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_18_address1 = zext_ln299_fu_3146_p1; - -assign local_B_18_d0 = bitcast_ln78_36_fu_2734_p1; - -assign local_B_18_d1 = bitcast_ln78_32_fu_2700_p1; - -assign local_B_19_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_19_address1 = zext_ln299_fu_3146_p1; - -assign local_B_19_d0 = bitcast_ln78_37_fu_2750_p1; - -assign local_B_19_d1 = bitcast_ln78_33_fu_2706_p1; - -assign local_B_1_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_1_address1 = zext_ln299_fu_3146_p1; - -assign local_B_1_d0 = bitcast_ln78_3_fu_2184_p1; - -assign local_B_1_d1 = elem_val_M_elems_1_fu_2150_p1; - -assign local_B_20_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_20_address1 = zext_ln299_fu_3146_p1; - -assign local_B_20_d0 = bitcast_ln78_42_fu_2830_p1; - -assign local_B_20_d1 = bitcast_ln78_38_fu_2766_p1; - -assign local_B_21_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_21_address1 = zext_ln299_fu_3146_p1; - -assign local_B_21_d0 = bitcast_ln78_43_fu_2836_p1; - -assign local_B_21_d1 = bitcast_ln78_39_fu_2782_p1; - -assign local_B_22_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_22_address1 = zext_ln299_fu_3146_p1; - -assign local_B_22_d0 = bitcast_ln78_44_fu_2842_p1; - -assign local_B_22_d1 = bitcast_ln78_40_fu_2798_p1; - -assign local_B_23_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_23_address1 = zext_ln299_fu_3146_p1; - -assign local_B_23_d0 = bitcast_ln78_45_fu_2848_p1; - -assign local_B_23_d1 = bitcast_ln78_41_fu_2814_p1; - -assign local_B_24_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_24_address1 = zext_ln299_fu_3146_p1; - -assign local_B_24_d0 = bitcast_ln78_50_fu_2979_p1; - -assign local_B_24_d1 = elem_val_M_elems_6_fu_2935_p1; - -assign local_B_25_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_25_address1 = zext_ln299_fu_3146_p1; - -assign local_B_25_d0 = bitcast_ln78_51_fu_2985_p1; - -assign local_B_25_d1 = elem_val_M_elems_7_fu_2951_p1; - -assign local_B_26_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_26_address1 = zext_ln299_fu_3146_p1; - -assign local_B_26_d0 = bitcast_ln78_52_fu_3001_p1; - -assign local_B_26_d1 = bitcast_ln78_48_fu_2967_p1; - -assign local_B_27_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_27_address1 = zext_ln299_fu_3146_p1; - -assign local_B_27_d0 = bitcast_ln78_53_fu_3017_p1; - -assign local_B_27_d1 = bitcast_ln78_49_fu_2973_p1; - -assign local_B_28_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_28_address1 = zext_ln299_fu_3146_p1; - -assign local_B_28_d0 = bitcast_ln78_58_fu_3097_p1; - -assign local_B_28_d1 = bitcast_ln78_54_fu_3033_p1; - -assign local_B_29_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_29_address1 = zext_ln299_fu_3146_p1; - -assign local_B_29_d0 = bitcast_ln78_59_fu_3103_p1; - -assign local_B_29_d1 = bitcast_ln78_55_fu_3049_p1; - -assign local_B_2_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_2_address1 = zext_ln299_fu_3146_p1; - -assign local_B_2_d0 = bitcast_ln78_4_fu_2200_p1; - -assign local_B_2_d1 = bitcast_ln78_fu_2166_p1; - -assign local_B_30_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_30_address1 = zext_ln299_fu_3146_p1; - -assign local_B_30_d0 = bitcast_ln78_60_fu_3109_p1; - -assign local_B_30_d1 = bitcast_ln78_56_fu_3065_p1; - -assign local_B_31_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_31_address1 = zext_ln299_fu_3146_p1; - -assign local_B_31_d0 = bitcast_ln78_61_fu_3115_p1; - -assign local_B_31_d1 = bitcast_ln78_57_fu_3081_p1; - -assign local_B_32_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_32_address1 = zext_ln299_fu_3146_p1; - -assign local_B_32_d0 = bitcast_ln78_2_fu_2178_p1; - -assign local_B_32_d1 = elem_val_M_elems_fu_2134_p1; - -assign local_B_33_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_33_address1 = zext_ln299_fu_3146_p1; - -assign local_B_33_d0 = bitcast_ln78_3_fu_2184_p1; - -assign local_B_33_d1 = elem_val_M_elems_1_fu_2150_p1; - -assign local_B_34_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_34_address1 = zext_ln299_fu_3146_p1; - -assign local_B_34_d0 = bitcast_ln78_4_fu_2200_p1; - -assign local_B_34_d1 = bitcast_ln78_fu_2166_p1; - -assign local_B_35_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_35_address1 = zext_ln299_fu_3146_p1; - -assign local_B_35_d0 = bitcast_ln78_5_fu_2216_p1; - -assign local_B_35_d1 = bitcast_ln78_1_fu_2172_p1; - -assign local_B_36_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_36_address1 = zext_ln299_fu_3146_p1; - -assign local_B_36_d0 = bitcast_ln78_10_fu_2296_p1; - -assign local_B_36_d1 = bitcast_ln78_6_fu_2232_p1; - -assign local_B_37_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_37_address1 = zext_ln299_fu_3146_p1; - -assign local_B_37_d0 = bitcast_ln78_11_fu_2302_p1; - -assign local_B_37_d1 = bitcast_ln78_7_fu_2248_p1; - -assign local_B_38_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_38_address1 = zext_ln299_fu_3146_p1; - -assign local_B_38_d0 = bitcast_ln78_12_fu_2308_p1; - -assign local_B_38_d1 = bitcast_ln78_8_fu_2264_p1; - -assign local_B_39_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_39_address1 = zext_ln299_fu_3146_p1; - -assign local_B_39_d0 = bitcast_ln78_13_fu_2314_p1; - -assign local_B_39_d1 = bitcast_ln78_9_fu_2280_p1; - -assign local_B_3_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_3_address1 = zext_ln299_fu_3146_p1; - -assign local_B_3_d0 = bitcast_ln78_5_fu_2216_p1; - -assign local_B_3_d1 = bitcast_ln78_1_fu_2172_p1; - -assign local_B_40_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_40_address1 = zext_ln299_fu_3146_p1; - -assign local_B_40_d0 = bitcast_ln78_18_fu_2445_p1; - -assign local_B_40_d1 = elem_val_M_elems_2_fu_2401_p1; - -assign local_B_41_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_41_address1 = zext_ln299_fu_3146_p1; - -assign local_B_41_d0 = bitcast_ln78_19_fu_2451_p1; - -assign local_B_41_d1 = elem_val_M_elems_3_fu_2417_p1; - -assign local_B_42_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_42_address1 = zext_ln299_fu_3146_p1; - -assign local_B_42_d0 = bitcast_ln78_20_fu_2467_p1; - -assign local_B_42_d1 = bitcast_ln78_16_fu_2433_p1; - -assign local_B_43_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_43_address1 = zext_ln299_fu_3146_p1; - -assign local_B_43_d0 = bitcast_ln78_21_fu_2483_p1; - -assign local_B_43_d1 = bitcast_ln78_17_fu_2439_p1; - -assign local_B_44_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_44_address1 = zext_ln299_fu_3146_p1; - -assign local_B_44_d0 = bitcast_ln78_26_fu_2563_p1; - -assign local_B_44_d1 = bitcast_ln78_22_fu_2499_p1; - -assign local_B_45_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_45_address1 = zext_ln299_fu_3146_p1; - -assign local_B_45_d0 = bitcast_ln78_27_fu_2569_p1; - -assign local_B_45_d1 = bitcast_ln78_23_fu_2515_p1; - -assign local_B_46_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_46_address1 = zext_ln299_fu_3146_p1; - -assign local_B_46_d0 = bitcast_ln78_28_fu_2575_p1; - -assign local_B_46_d1 = bitcast_ln78_24_fu_2531_p1; - -assign local_B_47_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_47_address1 = zext_ln299_fu_3146_p1; - -assign local_B_47_d0 = bitcast_ln78_29_fu_2581_p1; - -assign local_B_47_d1 = bitcast_ln78_25_fu_2547_p1; - -assign local_B_48_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_48_address1 = zext_ln299_fu_3146_p1; - -assign local_B_48_d0 = bitcast_ln78_34_fu_2712_p1; - -assign local_B_48_d1 = elem_val_M_elems_4_fu_2668_p1; - -assign local_B_49_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_49_address1 = zext_ln299_fu_3146_p1; - -assign local_B_49_d0 = bitcast_ln78_35_fu_2718_p1; - -assign local_B_49_d1 = elem_val_M_elems_5_fu_2684_p1; - -assign local_B_4_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_4_address1 = zext_ln299_fu_3146_p1; - -assign local_B_4_d0 = bitcast_ln78_10_fu_2296_p1; - -assign local_B_4_d1 = bitcast_ln78_6_fu_2232_p1; - -assign local_B_50_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_50_address1 = zext_ln299_fu_3146_p1; - -assign local_B_50_d0 = bitcast_ln78_36_fu_2734_p1; - -assign local_B_50_d1 = bitcast_ln78_32_fu_2700_p1; - -assign local_B_51_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_51_address1 = zext_ln299_fu_3146_p1; - -assign local_B_51_d0 = bitcast_ln78_37_fu_2750_p1; - -assign local_B_51_d1 = bitcast_ln78_33_fu_2706_p1; - -assign local_B_52_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_52_address1 = zext_ln299_fu_3146_p1; - -assign local_B_52_d0 = bitcast_ln78_42_fu_2830_p1; - -assign local_B_52_d1 = bitcast_ln78_38_fu_2766_p1; - -assign local_B_53_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_53_address1 = zext_ln299_fu_3146_p1; - -assign local_B_53_d0 = bitcast_ln78_43_fu_2836_p1; - -assign local_B_53_d1 = bitcast_ln78_39_fu_2782_p1; - -assign local_B_54_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_54_address1 = zext_ln299_fu_3146_p1; - -assign local_B_54_d0 = bitcast_ln78_44_fu_2842_p1; - -assign local_B_54_d1 = bitcast_ln78_40_fu_2798_p1; - -assign local_B_55_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_55_address1 = zext_ln299_fu_3146_p1; - -assign local_B_55_d0 = bitcast_ln78_45_fu_2848_p1; - -assign local_B_55_d1 = bitcast_ln78_41_fu_2814_p1; - -assign local_B_56_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_56_address1 = zext_ln299_fu_3146_p1; - -assign local_B_56_d0 = bitcast_ln78_50_fu_2979_p1; - -assign local_B_56_d1 = elem_val_M_elems_6_fu_2935_p1; - -assign local_B_57_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_57_address1 = zext_ln299_fu_3146_p1; - -assign local_B_57_d0 = bitcast_ln78_51_fu_2985_p1; - -assign local_B_57_d1 = elem_val_M_elems_7_fu_2951_p1; - -assign local_B_58_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_58_address1 = zext_ln299_fu_3146_p1; - -assign local_B_58_d0 = bitcast_ln78_52_fu_3001_p1; - -assign local_B_58_d1 = bitcast_ln78_48_fu_2967_p1; - -assign local_B_59_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_59_address1 = zext_ln299_fu_3146_p1; - -assign local_B_59_d0 = bitcast_ln78_53_fu_3017_p1; - -assign local_B_59_d1 = bitcast_ln78_49_fu_2973_p1; - -assign local_B_5_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_5_address1 = zext_ln299_fu_3146_p1; - -assign local_B_5_d0 = bitcast_ln78_11_fu_2302_p1; - -assign local_B_5_d1 = bitcast_ln78_7_fu_2248_p1; - -assign local_B_60_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_60_address1 = zext_ln299_fu_3146_p1; - -assign local_B_60_d0 = bitcast_ln78_58_fu_3097_p1; - -assign local_B_60_d1 = bitcast_ln78_54_fu_3033_p1; - -assign local_B_61_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_61_address1 = zext_ln299_fu_3146_p1; - -assign local_B_61_d0 = bitcast_ln78_59_fu_3103_p1; - -assign local_B_61_d1 = bitcast_ln78_55_fu_3049_p1; - -assign local_B_62_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_62_address1 = zext_ln299_fu_3146_p1; - -assign local_B_62_d0 = bitcast_ln78_60_fu_3109_p1; - -assign local_B_62_d1 = bitcast_ln78_56_fu_3065_p1; - -assign local_B_63_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_63_address1 = zext_ln299_fu_3146_p1; - -assign local_B_63_d0 = bitcast_ln78_61_fu_3115_p1; - -assign local_B_63_d1 = bitcast_ln78_57_fu_3081_p1; - -assign local_B_6_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_6_address1 = zext_ln299_fu_3146_p1; - -assign local_B_6_d0 = bitcast_ln78_12_fu_2308_p1; - -assign local_B_6_d1 = bitcast_ln78_8_fu_2264_p1; - -assign local_B_7_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_7_address1 = zext_ln299_fu_3146_p1; - -assign local_B_7_d0 = bitcast_ln78_13_fu_2314_p1; - -assign local_B_7_d1 = bitcast_ln78_9_fu_2280_p1; - -assign local_B_8_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_8_address1 = zext_ln299_fu_3146_p1; - -assign local_B_8_d0 = bitcast_ln78_18_fu_2445_p1; - -assign local_B_8_d1 = elem_val_M_elems_2_fu_2401_p1; - -assign local_B_9_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_9_address1 = zext_ln299_fu_3146_p1; - -assign local_B_9_d0 = bitcast_ln78_19_fu_2451_p1; - -assign local_B_9_d1 = elem_val_M_elems_3_fu_2417_p1; - -assign local_B_address0 = zext_ln299_1_fu_3220_p1; - -assign local_B_address1 = zext_ln299_fu_3146_p1; - -assign local_B_d0 = bitcast_ln78_2_fu_2178_p1; - -assign local_B_d1 = elem_val_M_elems_fu_2134_p1; - -assign or_ln299_fu_3214_p2 = (shl_ln_fu_3138_p3 | 10'd1); - -assign shl_ln_fu_3138_p3 = {{trunc_ln299_fu_3134_p1}, {1'd0}}; - -assign tmp_10_fu_2140_p4 = {{fifo_B_in_0_dout[63:32]}}; - -assign tmp_11_fu_2156_p4 = {{fifo_B_in_0_dout[95:64]}}; - -assign tmp_12_fu_2190_p4 = {{fifo_B_in_0_dout[223:192]}}; - -assign tmp_13_fu_2206_p4 = {{fifo_B_in_0_dout[255:224]}}; - -assign tmp_14_fu_2222_p4 = {{fifo_B_in_0_dout[287:256]}}; - -assign tmp_15_fu_2238_p4 = {{fifo_B_in_0_dout[319:288]}}; - -assign tmp_16_fu_2254_p4 = {{fifo_B_in_0_dout[351:320]}}; - -assign tmp_17_fu_2270_p4 = {{fifo_B_in_0_dout[383:352]}}; - -assign tmp_18_fu_2286_p4 = {{fifo_B_in_0_dout[415:384]}}; - -assign tmp_19_fu_2341_p4 = {{fifo_B_in_1_dout[127:96]}}; - -assign tmp_20_fu_2351_p4 = {{fifo_B_in_1_dout[159:128]}}; - -assign tmp_21_fu_2361_p4 = {{fifo_B_in_1_dout[191:160]}}; - -assign tmp_22_fu_2371_p4 = {{fifo_B_in_1_dout[447:416]}}; - -assign tmp_23_fu_2407_p4 = {{fifo_B_in_1_dout[63:32]}}; - -assign tmp_24_fu_2423_p4 = {{fifo_B_in_1_dout[95:64]}}; - -assign tmp_25_fu_2457_p4 = {{fifo_B_in_1_dout[223:192]}}; - -assign tmp_26_fu_2473_p4 = {{fifo_B_in_1_dout[255:224]}}; - -assign tmp_27_fu_2489_p4 = {{fifo_B_in_1_dout[287:256]}}; - -assign tmp_28_fu_2505_p4 = {{fifo_B_in_1_dout[319:288]}}; - -assign tmp_29_fu_2521_p4 = {{fifo_B_in_1_dout[351:320]}}; - -assign tmp_30_fu_2537_p4 = {{fifo_B_in_1_dout[383:352]}}; - -assign tmp_31_fu_2553_p4 = {{fifo_B_in_1_dout[415:384]}}; - -assign tmp_32_fu_2608_p4 = {{fifo_B_in_2_dout[127:96]}}; - -assign tmp_33_fu_2618_p4 = {{fifo_B_in_2_dout[159:128]}}; - -assign tmp_34_fu_2628_p4 = {{fifo_B_in_2_dout[191:160]}}; - -assign tmp_35_fu_2638_p4 = {{fifo_B_in_2_dout[447:416]}}; - -assign tmp_36_fu_2674_p4 = {{fifo_B_in_2_dout[63:32]}}; - -assign tmp_37_fu_2690_p4 = {{fifo_B_in_2_dout[95:64]}}; - -assign tmp_38_fu_2724_p4 = {{fifo_B_in_2_dout[223:192]}}; - -assign tmp_39_fu_2740_p4 = {{fifo_B_in_2_dout[255:224]}}; - -assign tmp_3_fu_2074_p4 = {{fifo_B_in_0_dout[127:96]}}; - -assign tmp_40_fu_2756_p4 = {{fifo_B_in_2_dout[287:256]}}; - -assign tmp_41_fu_2772_p4 = {{fifo_B_in_2_dout[319:288]}}; - -assign tmp_42_fu_2788_p4 = {{fifo_B_in_2_dout[351:320]}}; - -assign tmp_43_fu_2804_p4 = {{fifo_B_in_2_dout[383:352]}}; - -assign tmp_44_fu_2820_p4 = {{fifo_B_in_2_dout[415:384]}}; - -assign tmp_45_fu_2875_p4 = {{fifo_B_in_3_dout[127:96]}}; - -assign tmp_46_fu_2885_p4 = {{fifo_B_in_3_dout[159:128]}}; - -assign tmp_47_fu_2895_p4 = {{fifo_B_in_3_dout[191:160]}}; - -assign tmp_48_fu_2905_p4 = {{fifo_B_in_3_dout[447:416]}}; - -assign tmp_49_fu_2941_p4 = {{fifo_B_in_3_dout[63:32]}}; - -assign tmp_4_nbreadreq_fu_304_p3 = fifo_B_in_2_empty_n; - -assign tmp_50_fu_2957_p4 = {{fifo_B_in_3_dout[95:64]}}; - -assign tmp_51_fu_2991_p4 = {{fifo_B_in_3_dout[223:192]}}; - -assign tmp_52_fu_3007_p4 = {{fifo_B_in_3_dout[255:224]}}; - -assign tmp_53_fu_3023_p4 = {{fifo_B_in_3_dout[287:256]}}; - -assign tmp_54_fu_3039_p4 = {{fifo_B_in_3_dout[319:288]}}; - -assign tmp_55_fu_3055_p4 = {{fifo_B_in_3_dout[351:320]}}; - -assign tmp_56_fu_3071_p4 = {{fifo_B_in_3_dout[383:352]}}; - -assign tmp_57_fu_3087_p4 = {{fifo_B_in_3_dout[415:384]}}; - -assign tmp_5_fu_2084_p4 = {{fifo_B_in_0_dout[159:128]}}; - -assign tmp_7_fu_2094_p4 = {{fifo_B_in_0_dout[191:160]}}; - -assign tmp_8_nbreadreq_fu_320_p3 = fifo_B_in_3_empty_n; - -assign tmp_9_fu_2104_p4 = {{fifo_B_in_0_dout[447:416]}}; - -assign tmp_fu_1996_p4 = {{ap_sig_allocacmp_j_1[31:9]}}; - -assign tmp_s_nbreadreq_fu_288_p3 = fifo_B_in_1_empty_n; - -assign trunc_ln146_1_fu_2587_p1 = fifo_B_in_1_dout[511:0]; - -assign trunc_ln146_2_fu_2854_p1 = fifo_B_in_2_dout[511:0]; - -assign trunc_ln146_3_fu_3121_p1 = fifo_B_in_3_dout[511:0]; - -assign trunc_ln146_fu_2320_p1 = fifo_B_in_0_dout[511:0]; - -assign trunc_ln299_fu_3134_p1 = ap_sig_allocacmp_j_1[8:0]; - -assign trunc_ln2_fu_2114_p4 = {{fifo_B_in_0_dout[479:448]}}; - -assign trunc_ln78_1_fu_2337_p1 = fifo_B_in_1_dout[31:0]; - -assign trunc_ln78_2_fu_2124_p4 = {{fifo_B_in_0_dout[511:480]}}; - -assign trunc_ln78_3_fu_2604_p1 = fifo_B_in_2_dout[31:0]; - -assign trunc_ln78_4_fu_2381_p4 = {{fifo_B_in_1_dout[479:448]}}; - -assign trunc_ln78_5_fu_2391_p4 = {{fifo_B_in_1_dout[511:480]}}; - -assign trunc_ln78_6_fu_2915_p4 = {{fifo_B_in_3_dout[479:448]}}; - -assign trunc_ln78_7_fu_2871_p1 = fifo_B_in_3_dout[31:0]; - -assign trunc_ln78_8_fu_2648_p4 = {{fifo_B_in_2_dout[479:448]}}; - -assign trunc_ln78_9_fu_2658_p4 = {{fifo_B_in_2_dout[511:480]}}; - -assign trunc_ln78_fu_2070_p1 = fifo_B_in_0_dout[31:0]; - -assign trunc_ln78_s_fu_2925_p4 = {{fifo_B_in_3_dout[511:480]}}; - -assign zext_ln299_1_fu_3220_p1 = or_ln299_fu_3214_p2; - -assign zext_ln299_fu_3146_p1 = shl_ln_fu_3138_p3; - -endmodule //PEG_Bmtx_PEG_Bmtx_Pipeline_read_B diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_flow_control_loop_pipe_sequential_init.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_flow_control_loop_pipe_sequential_init.v deleted file mode 100644 index ae17c999..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_flow_control_loop_pipe_sequential_init.v +++ /dev/null @@ -1,104 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module PEG_Bmtx_flow_control_loop_pipe_sequential_init( - ap_clk, - ap_rst, - ap_start, - ap_ready, - ap_done, - ap_start_int, - ap_ready_int, - ap_done_int, - ap_continue_int, - ap_loop_init, - ap_loop_exit_ready, - ap_loop_exit_done -); - -input ap_clk; -input ap_rst; - -//Block level handshake with outside loop -input ap_start; -output ap_ready; -output ap_done; - -//Block level handshake with loop body -output ap_start_int; -input ap_ready_int; -input ap_done_int; -output ap_continue_int; - -//Init live in variables -output ap_loop_init; -wire ap_loop_init; -reg ap_loop_init_int; -reg ap_done; -reg ap_done_cache; - -//Exit signal from loop body -input ap_loop_exit_ready; -input ap_loop_exit_done; - -// power-on initialization -initial begin -#0 ap_loop_init_int = 1'b1; -#0 ap_done_cache = 1'b0; -end - -assign ap_start_int = ap_start; - -assign ap_continue_int = 1'b1; - -assign ap_ready = ap_loop_exit_ready; - -//ap_loop_init is valid for the first II -//of the first loop run so as to enable -//the init block ops which are pushed into -//the first state of the pipeline region -always @ (posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_loop_exit_done == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_ready_int == 1'b1) begin - ap_loop_init_int <= 1'b0; - end -end - -assign ap_loop_init = ap_loop_init_int & ap_start; - -// if no ap_continue port and current module is not top module, -// ap_done handshakes with ap_start. Internally, flow control sends out -// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle. -// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int -// is asserted, so DUT can start the next run -always @(posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_done_cache <= 1'b0; - end else if (ap_done_int == 1'b1) begin - ap_done_cache <= 1'b1; - end else if (ap_start_int == 1'b1) begin - ap_done_cache <= 1'b0; - end -end - -// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start -always @(*) -begin - if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1.v deleted file mode 100644 index 130001ef..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1.v +++ /dev/null @@ -1,76 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1ns/1ps - -module PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1 -#(parameter - ID = 1, - NUM_STAGE = 3, - din0_WIDTH = 32, - din1_WIDTH = 32, - dout_WIDTH = 32 -)( - input wire clk, - input wire reset, - input wire ce, - input wire [din0_WIDTH-1:0] din0, - input wire [din1_WIDTH-1:0] din1, - output wire [dout_WIDTH-1:0] dout -); -//------------------------Local signal------------------- -wire aclk; -wire aclken; -wire a_tvalid; -wire [31:0] a_tdata; -wire b_tvalid; -wire [31:0] b_tdata; -wire r_tvalid; -wire [31:0] r_tdata; -reg [din0_WIDTH-1:0] din0_buf1; -reg [din1_WIDTH-1:0] din1_buf1; -reg ce_r; -wire [dout_WIDTH-1:0] dout_i; -reg [dout_WIDTH-1:0] dout_r; -//------------------------Instantiation------------------ -PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip_u ( - .aclk ( aclk ), - .aclken ( aclken ), - .s_axis_a_tvalid ( a_tvalid ), - .s_axis_a_tdata ( a_tdata ), - .s_axis_b_tvalid ( b_tvalid ), - .s_axis_b_tdata ( b_tdata ), - .m_axis_result_tvalid ( r_tvalid ), - .m_axis_result_tdata ( r_tdata ) -); -//------------------------Body--------------------------- -assign aclk = clk; -assign aclken = ce_r; -assign a_tvalid = 1'b1; -assign a_tdata = din0_buf1; -assign b_tvalid = 1'b1; -assign b_tdata = din1_buf1; -assign dout_i = r_tdata; - -always @(posedge clk) begin - if (ce) begin - din0_buf1 <= din0; - din1_buf1 <= din1; - end -end - -always @ (posedge clk) begin - ce_r <= ce; -end - -always @ (posedge clk) begin - if (ce_r) begin - dout_r <= dout_i; - end -end - -assign dout = ce_r?dout_i:dout_r; -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip.tcl b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip.tcl deleted file mode 100644 index e3567bba..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip.tcl +++ /dev/null @@ -1,45 +0,0 @@ -# BEGIN Vivado Commands -set vivado_ver [version -short] -set fpo_ver 7.1 -if {[regexp -nocase {2015\.1.*} $vivado_ver match]} { - set fpo_ver 7.0 -} -create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip -# BEGIN Vivado Commands -# BEGIN Vivado Parameters -set_property -dict [list CONFIG.a_precision_type Single \ - CONFIG.a_tuser_width 1 \ - CONFIG.add_sub_value Both \ - CONFIG.b_tuser_width 1 \ - CONFIG.c_a_exponent_width 8 \ - CONFIG.c_a_fraction_width 24 \ - CONFIG.c_compare_operation Programmable \ - CONFIG.c_has_divide_by_zero false \ - CONFIG.c_has_invalid_op false \ - CONFIG.c_has_overflow false \ - CONFIG.c_has_underflow false \ - CONFIG.c_latency 2 \ - CONFIG.c_mult_usage Max_Usage \ - CONFIG.c_optimization Speed_Optimized \ - CONFIG.c_rate 1 \ - CONFIG.c_result_exponent_width 8 \ - CONFIG.c_result_fraction_width 24 \ - CONFIG.component_name PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip \ - CONFIG.flow_control NonBlocking \ - CONFIG.has_a_tlast false \ - CONFIG.has_a_tuser false \ - CONFIG.has_aclken true \ - CONFIG.has_aresetn false \ - CONFIG.has_b_tlast false \ - CONFIG.has_b_tuser false \ - CONFIG.has_operation_tlast false \ - CONFIG.has_operation_tuser false \ - CONFIG.has_result_tready false \ - CONFIG.maximum_latency false \ - CONFIG.operation_tuser_width 1 \ - CONFIG.operation_type Multiply \ - CONFIG.result_precision_type Single \ - CONFIG.result_tlast_behv Null] -objects [get_ips PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip] -quiet -# END Vivado Parameters -set_property generate_synth_checkpoint false [get_files PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip.xci] -generate_target {synthesis simulation} [get_files PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip.xci] diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_local_B_RAM_AUTO_1R1W.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_local_B_RAM_AUTO_1R1W.v deleted file mode 100644 index a8f4f09c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_local_B_RAM_AUTO_1R1W.v +++ /dev/null @@ -1,77 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== -`timescale 1 ns / 1 ps -module PEG_Bmtx_local_B_RAM_AUTO_1R1W ( - - address0, ce0, - d0, we0, - q0, - - address1, ce1, - d1, we1, - q1, - - reset, clk); - -parameter DataWidth = 32; -parameter AddressWidth = 10; -parameter AddressRange = 1024; - -input[AddressWidth-1:0] address0; -input ce0; -input[DataWidth-1:0] d0; -input we0; -output reg[DataWidth-1:0] q0; - -input[AddressWidth-1:0] address1; -input ce1; -input[DataWidth-1:0] d1; -input we1; -output reg[DataWidth-1:0] q1; - -input reset; -input clk; - -(* ram_style = "auto" *)reg [DataWidth-1:0] ram[0:AddressRange-1]; - - - - - - - - -//read first -always @(posedge clk) -begin - if (ce0) begin - if (we0) - ram[address0] <= d0; - q0 <= ram[address0]; - - end -end - - - - - - - -//read first -always @(posedge clk) -begin - if (ce1) begin - if (we1) - ram[address1] <= d1; - q1 <= ram[address1]; - - end -end - - - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_mul_mul_16s_14ns_30_4_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_mul_mul_16s_14ns_30_4_1.v deleted file mode 100644 index 28f5282f..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_mul_mul_16s_14ns_30_4_1.v +++ /dev/null @@ -1,62 +0,0 @@ - -`timescale 1 ns / 1 ps - - module PEG_Bmtx_mul_mul_16s_14ns_30_4_1_DSP48_0(clk, rst, ce, a, b, p); -input clk; -input rst; -input ce; -input signed [16 - 1 : 0] a; -input [14 - 1 : 0] b; -output signed [30 - 1 : 0] p; - -reg signed [30 - 1 : 0] p_reg; - -reg signed [16 - 1 : 0] a_reg; -reg [14 - 1 : 0] b_reg; - -reg signed [30 - 1 : 0] p_reg_tmp; - -always @ (posedge clk) begin - if (ce) begin - a_reg <= a; - b_reg <= b; - p_reg_tmp <= a_reg * $signed({1'b0, b_reg}); - p_reg <= p_reg_tmp; - end -end - -assign p = p_reg; - -endmodule -`timescale 1 ns / 1 ps -module PEG_Bmtx_mul_mul_16s_14ns_30_4_1( - clk, - reset, - ce, - din0, - din1, - dout); - -parameter ID = 32'd1; -parameter NUM_STAGE = 32'd1; -parameter din0_WIDTH = 32'd1; -parameter din1_WIDTH = 32'd1; -parameter dout_WIDTH = 32'd1; -input clk; -input reset; -input ce; -input[din0_WIDTH - 1:0] din0; -input[din1_WIDTH - 1:0] din1; -output[dout_WIDTH - 1:0] dout; - - - -PEG_Bmtx_mul_mul_16s_14ns_30_4_1_DSP48_0 PEG_Bmtx_mul_mul_16s_14ns_30_4_1_DSP48_0_U( - .clk( clk ), - .rst( reset ), - .ce( ce ), - .a( din0 ), - .b( din1 ), - .p( dout )); - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_mux_42_32_1_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_mux_42_32_1_1.v deleted file mode 100644 index a69b5d70..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Bmtx_mux_42_32_1_1.v +++ /dev/null @@ -1,47 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1ns/1ps - -module PEG_Bmtx_mux_42_32_1_1 #( -parameter - ID = 0, - NUM_STAGE = 1, - din0_WIDTH = 32, - din1_WIDTH = 32, - din2_WIDTH = 32, - din3_WIDTH = 32, - din4_WIDTH = 32, - dout_WIDTH = 32 -)( - input [31 : 0] din0, - input [31 : 0] din1, - input [31 : 0] din2, - input [31 : 0] din3, - input [1 : 0] din4, - output [31 : 0] dout); - -// puts internal signals -wire [1 : 0] sel; -// level 1 signals -wire [31 : 0] mux_1_0; -wire [31 : 0] mux_1_1; -// level 2 signals -wire [31 : 0] mux_2_0; - -assign sel = din4; - -// Generate level 1 logic -assign mux_1_0 = (sel[0] == 0)? din0 : din1; -assign mux_1_1 = (sel[0] == 0)? din2 : din3; - -// Generate level 2 logic -assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1; - -// output logic -assign dout = mux_2_0; - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx.v deleted file mode 100644 index 21deaa48..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx.v +++ /dev/null @@ -1,2486 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="PEG_Cmtx_PEG_Cmtx,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.583450,HLS_SYN_LAT=33279,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=17721,HLS_SYN_LUT=11573,HLS_VERSION=2022_2}" *) - -module PEG_Cmtx ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - PE_inst_in_s_dout, - PE_inst_in_s_empty_n, - PE_inst_in_s_read, - PE_inst_in_peek_dout, - PE_inst_in_peek_empty_n, - PE_inst_in_peek_read, - fifo_inst_in_s_dout, - fifo_inst_in_s_empty_n, - fifo_inst_in_s_read, - fifo_inst_in_peek_dout, - fifo_inst_in_peek_empty_n, - fifo_inst_in_peek_read, - fifo_aBvec_0_dout, - fifo_aBvec_0_empty_n, - fifo_aBvec_0_read, - fifo_aBvec_1_dout, - fifo_aBvec_1_empty_n, - fifo_aBvec_1_read, - fifo_aBvec_2_dout, - fifo_aBvec_2_empty_n, - fifo_aBvec_2_read, - fifo_aBvec_3_dout, - fifo_aBvec_3_empty_n, - fifo_aBvec_3_read, - fifo_aBvec_peek_0_dout, - fifo_aBvec_peek_0_empty_n, - fifo_aBvec_peek_0_read, - fifo_aBvec_peek_1_dout, - fifo_aBvec_peek_1_empty_n, - fifo_aBvec_peek_1_read, - fifo_aBvec_peek_2_dout, - fifo_aBvec_peek_2_empty_n, - fifo_aBvec_peek_2_read, - fifo_aBvec_peek_3_dout, - fifo_aBvec_peek_3_empty_n, - fifo_aBvec_peek_3_read, - fifo_C_out_din, - fifo_C_out_full_n, - fifo_C_out_write -); - -parameter ap_ST_fsm_state1 = 13'd1; -parameter ap_ST_fsm_state2 = 13'd2; -parameter ap_ST_fsm_state3 = 13'd4; -parameter ap_ST_fsm_state4 = 13'd8; -parameter ap_ST_fsm_state5 = 13'd16; -parameter ap_ST_fsm_state6 = 13'd32; -parameter ap_ST_fsm_state7 = 13'd64; -parameter ap_ST_fsm_state8 = 13'd128; -parameter ap_ST_fsm_state9 = 13'd256; -parameter ap_ST_fsm_state10 = 13'd512; -parameter ap_ST_fsm_state11 = 13'd1024; -parameter ap_ST_fsm_state12 = 13'd2048; -parameter ap_ST_fsm_state13 = 13'd4096; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [32:0] PE_inst_in_s_dout; -input PE_inst_in_s_empty_n; -output PE_inst_in_s_read; -input [32:0] PE_inst_in_peek_dout; -input PE_inst_in_peek_empty_n; -output PE_inst_in_peek_read; -input [32:0] fifo_inst_in_s_dout; -input fifo_inst_in_s_empty_n; -output fifo_inst_in_s_read; -input [32:0] fifo_inst_in_peek_dout; -input fifo_inst_in_peek_empty_n; -output fifo_inst_in_peek_read; -input [274:0] fifo_aBvec_0_dout; -input fifo_aBvec_0_empty_n; -output fifo_aBvec_0_read; -input [274:0] fifo_aBvec_1_dout; -input fifo_aBvec_1_empty_n; -output fifo_aBvec_1_read; -input [274:0] fifo_aBvec_2_dout; -input fifo_aBvec_2_empty_n; -output fifo_aBvec_2_read; -input [274:0] fifo_aBvec_3_dout; -input fifo_aBvec_3_empty_n; -output fifo_aBvec_3_read; -input [274:0] fifo_aBvec_peek_0_dout; -input fifo_aBvec_peek_0_empty_n; -output fifo_aBvec_peek_0_read; -input [274:0] fifo_aBvec_peek_1_dout; -input fifo_aBvec_peek_1_empty_n; -output fifo_aBvec_peek_1_read; -input [274:0] fifo_aBvec_peek_2_dout; -input fifo_aBvec_peek_2_empty_n; -output fifo_aBvec_peek_2_read; -input [274:0] fifo_aBvec_peek_3_dout; -input fifo_aBvec_peek_3_empty_n; -output fifo_aBvec_peek_3_read; -output [256:0] fifo_C_out_din; -input fifo_C_out_full_n; -output fifo_C_out_write; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg PE_inst_in_s_read; -reg fifo_inst_in_s_read; -reg fifo_aBvec_0_read; -reg fifo_aBvec_1_read; -reg fifo_aBvec_2_read; -reg fifo_aBvec_3_read; -reg fifo_C_out_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [12:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -reg PE_inst_in_s_blk_n; -wire ap_CS_fsm_state2; -wire ap_CS_fsm_state3; -reg fifo_inst_in_s_blk_n; -wire ap_CS_fsm_state9; -wire ap_CS_fsm_state10; -wire [0:0] icmp_ln249_fu_522_p2; -wire [31:0] NUM_ITE_fu_400_p1; -reg [31:0] NUM_ITE_reg_554; -wire [31:0] M_fu_409_p1; -reg [31:0] M_reg_559; -reg [15:0] N16_reg_565; -reg [13:0] lshr_ln_reg_571; -wire ap_CS_fsm_state4; -wire signed [29:0] grp_fu_541_p2; -reg signed [29:0] rp_time_N_reg_586; -wire ap_CS_fsm_state7; -reg [25:0] trunc_ln_reg_591; -reg [27:0] num_v_out_reg_596; -wire [27:0] rp_2_fu_508_p2; -reg [27:0] rp_2_reg_604; -wire ap_CS_fsm_state8; -wire [31:0] start_32_fu_514_p1; -wire [30:0] add_ln249_fu_527_p2; -reg [30:0] add_ln249_reg_617; -reg ap_block_state10; -wire [31:0] end_32_fu_533_p1; -reg [31:0] end_32_reg_622; -reg [12:0] local_C_V_address0; -reg local_C_V_ce0; -wire [63:0] local_C_V_q0; -reg [12:0] local_C_V_address1; -reg local_C_V_ce1; -reg local_C_V_we1; -reg [63:0] local_C_V_d1; -reg [12:0] local_C_V_1_address0; -reg local_C_V_1_ce0; -wire [63:0] local_C_V_1_q0; -reg [12:0] local_C_V_1_address1; -reg local_C_V_1_ce1; -reg local_C_V_1_we1; -reg [63:0] local_C_V_1_d1; -reg [12:0] local_C_V_2_address0; -reg local_C_V_2_ce0; -wire [63:0] local_C_V_2_q0; -reg [12:0] local_C_V_2_address1; -reg local_C_V_2_ce1; -reg local_C_V_2_we1; -reg [63:0] local_C_V_2_d1; -reg [12:0] local_C_V_3_address0; -reg local_C_V_3_ce0; -wire [63:0] local_C_V_3_q0; -reg [12:0] local_C_V_3_address1; -reg local_C_V_3_ce1; -reg local_C_V_3_we1; -reg [63:0] local_C_V_3_d1; -reg [12:0] local_C_V_4_address0; -reg local_C_V_4_ce0; -wire [63:0] local_C_V_4_q0; -reg [12:0] local_C_V_4_address1; -reg local_C_V_4_ce1; -reg local_C_V_4_we1; -reg [63:0] local_C_V_4_d1; -reg [12:0] local_C_V_5_address0; -reg local_C_V_5_ce0; -wire [63:0] local_C_V_5_q0; -reg [12:0] local_C_V_5_address1; -reg local_C_V_5_ce1; -reg local_C_V_5_we1; -reg [63:0] local_C_V_5_d1; -reg [12:0] local_C_V_6_address0; -reg local_C_V_6_ce0; -wire [63:0] local_C_V_6_q0; -reg [12:0] local_C_V_6_address1; -reg local_C_V_6_ce1; -reg local_C_V_6_we1; -reg [63:0] local_C_V_6_d1; -reg [12:0] local_C_V_7_address0; -reg local_C_V_7_ce0; -wire [63:0] local_C_V_7_q0; -reg [12:0] local_C_V_7_address1; -reg local_C_V_7_ce1; -reg local_C_V_7_we1; -reg [63:0] local_C_V_7_d1; -reg [12:0] local_C_V_8_address0; -reg local_C_V_8_ce0; -wire [63:0] local_C_V_8_q0; -reg [12:0] local_C_V_8_address1; -reg local_C_V_8_ce1; -reg local_C_V_8_we1; -reg [63:0] local_C_V_8_d1; -reg [12:0] local_C_V_9_address0; -reg local_C_V_9_ce0; -wire [63:0] local_C_V_9_q0; -reg [12:0] local_C_V_9_address1; -reg local_C_V_9_ce1; -reg local_C_V_9_we1; -reg [63:0] local_C_V_9_d1; -reg [12:0] local_C_V_10_address0; -reg local_C_V_10_ce0; -wire [63:0] local_C_V_10_q0; -reg [12:0] local_C_V_10_address1; -reg local_C_V_10_ce1; -reg local_C_V_10_we1; -reg [63:0] local_C_V_10_d1; -reg [12:0] local_C_V_11_address0; -reg local_C_V_11_ce0; -wire [63:0] local_C_V_11_q0; -reg [12:0] local_C_V_11_address1; -reg local_C_V_11_ce1; -reg local_C_V_11_we1; -reg [63:0] local_C_V_11_d1; -reg [12:0] local_C_V_12_address0; -reg local_C_V_12_ce0; -wire [63:0] local_C_V_12_q0; -reg [12:0] local_C_V_12_address1; -reg local_C_V_12_ce1; -reg local_C_V_12_we1; -reg [63:0] local_C_V_12_d1; -reg [12:0] local_C_V_13_address0; -reg local_C_V_13_ce0; -wire [63:0] local_C_V_13_q0; -reg [12:0] local_C_V_13_address1; -reg local_C_V_13_ce1; -reg local_C_V_13_we1; -reg [63:0] local_C_V_13_d1; -reg [12:0] local_C_V_14_address0; -reg local_C_V_14_ce0; -wire [63:0] local_C_V_14_q0; -reg [12:0] local_C_V_14_address1; -reg local_C_V_14_ce1; -reg local_C_V_14_we1; -reg [63:0] local_C_V_14_d1; -reg [12:0] local_C_V_15_address0; -reg local_C_V_15_ce0; -wire [63:0] local_C_V_15_q0; -reg [12:0] local_C_V_15_address1; -reg local_C_V_15_ce1; -reg local_C_V_15_we1; -reg [63:0] local_C_V_15_d1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_start; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_done; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_idle; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_ready; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_address1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_ce1; -wire grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_d1; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_start; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_done; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_idle; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_ready; -wire [256:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_fifo_C_out_din; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_fifo_C_out_write; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_4_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_4_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_8_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_8_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_12_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_12_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_1_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_1_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_5_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_5_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_9_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_9_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_13_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_13_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_2_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_2_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_6_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_6_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_10_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_10_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_14_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_14_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_3_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_3_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_7_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_7_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_11_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_11_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_15_address0; -wire grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_15_ce0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_start; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_done; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_idle; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_ready; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_d1; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_address0; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_ce0; -wire [12:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_address1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_ce1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_we1; -wire [63:0] grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_d1; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_0_read; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_1_read; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_2_read; -wire grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_3_read; -reg [30:0] i_1_reg_304; -wire ap_CS_fsm_state12; -reg [31:0] start_32_3_reg_315; -reg grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_start_reg; -wire [0:0] icmp_ln232_fu_503_p2; -reg grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_start_reg; -reg ap_block_state10_ignore_call1; -wire ap_CS_fsm_state13; -reg grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_start_reg; -wire ap_CS_fsm_state11; -reg [27:0] rp_fu_120; -reg ap_block_state1; -wire [15:0] N_fu_413_p1; -wire [16:0] zext_ln219_fu_427_p1; -wire [16:0] add_ln220_fu_431_p2; -wire [0:0] icmp_ln218_fu_447_p2; -wire signed [15:0] rp_time_fu_452_p3; -wire [31:0] add_ln221_fu_466_p2; -wire [31:0] add_ln223_fu_481_p2; -wire [29:0] zext_ln232_fu_499_p1; -wire [31:0] zext_ln249_fu_518_p1; -wire [13:0] grp_fu_541_p1; -reg [12:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -reg ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -wire ap_ST_fsm_state4_blk; -wire ap_ST_fsm_state5_blk; -wire ap_ST_fsm_state6_blk; -wire ap_ST_fsm_state7_blk; -wire ap_ST_fsm_state8_blk; -reg ap_ST_fsm_state9_blk; -reg ap_ST_fsm_state10_blk; -wire ap_ST_fsm_state11_blk; -reg ap_ST_fsm_state12_blk; -reg ap_ST_fsm_state13_blk; -wire [29:0] grp_fu_541_p10; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 13'd1; -#0 grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_start_reg = 1'b0; -#0 grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_start_reg = 1'b0; -#0 grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_start_reg = 1'b0; -end - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_address0), - .ce0(local_C_V_ce0), - .q0(local_C_V_q0), - .address1(local_C_V_address1), - .ce1(local_C_V_ce1), - .we1(local_C_V_we1), - .d1(local_C_V_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_1_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_1_address0), - .ce0(local_C_V_1_ce0), - .q0(local_C_V_1_q0), - .address1(local_C_V_1_address1), - .ce1(local_C_V_1_ce1), - .we1(local_C_V_1_we1), - .d1(local_C_V_1_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_2_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_2_address0), - .ce0(local_C_V_2_ce0), - .q0(local_C_V_2_q0), - .address1(local_C_V_2_address1), - .ce1(local_C_V_2_ce1), - .we1(local_C_V_2_we1), - .d1(local_C_V_2_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_3_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_3_address0), - .ce0(local_C_V_3_ce0), - .q0(local_C_V_3_q0), - .address1(local_C_V_3_address1), - .ce1(local_C_V_3_ce1), - .we1(local_C_V_3_we1), - .d1(local_C_V_3_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_4_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_4_address0), - .ce0(local_C_V_4_ce0), - .q0(local_C_V_4_q0), - .address1(local_C_V_4_address1), - .ce1(local_C_V_4_ce1), - .we1(local_C_V_4_we1), - .d1(local_C_V_4_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_5_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_5_address0), - .ce0(local_C_V_5_ce0), - .q0(local_C_V_5_q0), - .address1(local_C_V_5_address1), - .ce1(local_C_V_5_ce1), - .we1(local_C_V_5_we1), - .d1(local_C_V_5_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_6_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_6_address0), - .ce0(local_C_V_6_ce0), - .q0(local_C_V_6_q0), - .address1(local_C_V_6_address1), - .ce1(local_C_V_6_ce1), - .we1(local_C_V_6_we1), - .d1(local_C_V_6_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_7_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_7_address0), - .ce0(local_C_V_7_ce0), - .q0(local_C_V_7_q0), - .address1(local_C_V_7_address1), - .ce1(local_C_V_7_ce1), - .we1(local_C_V_7_we1), - .d1(local_C_V_7_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_8_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_8_address0), - .ce0(local_C_V_8_ce0), - .q0(local_C_V_8_q0), - .address1(local_C_V_8_address1), - .ce1(local_C_V_8_ce1), - .we1(local_C_V_8_we1), - .d1(local_C_V_8_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_9_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_9_address0), - .ce0(local_C_V_9_ce0), - .q0(local_C_V_9_q0), - .address1(local_C_V_9_address1), - .ce1(local_C_V_9_ce1), - .we1(local_C_V_9_we1), - .d1(local_C_V_9_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_10_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_10_address0), - .ce0(local_C_V_10_ce0), - .q0(local_C_V_10_q0), - .address1(local_C_V_10_address1), - .ce1(local_C_V_10_ce1), - .we1(local_C_V_10_we1), - .d1(local_C_V_10_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_11_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_11_address0), - .ce0(local_C_V_11_ce0), - .q0(local_C_V_11_q0), - .address1(local_C_V_11_address1), - .ce1(local_C_V_11_ce1), - .we1(local_C_V_11_we1), - .d1(local_C_V_11_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_12_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_12_address0), - .ce0(local_C_V_12_ce0), - .q0(local_C_V_12_q0), - .address1(local_C_V_12_address1), - .ce1(local_C_V_12_ce1), - .we1(local_C_V_12_we1), - .d1(local_C_V_12_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_13_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_13_address0), - .ce0(local_C_V_13_ce0), - .q0(local_C_V_13_q0), - .address1(local_C_V_13_address1), - .ce1(local_C_V_13_ce1), - .we1(local_C_V_13_we1), - .d1(local_C_V_13_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_14_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_14_address0), - .ce0(local_C_V_14_ce0), - .q0(local_C_V_14_q0), - .address1(local_C_V_14_address1), - .ce1(local_C_V_14_ce1), - .we1(local_C_V_14_we1), - .d1(local_C_V_14_d1) -); - -PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W #( - .DataWidth( 64 ), - .AddressRange( 8192 ), - .AddressWidth( 13 )) -local_C_V_15_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(local_C_V_15_address0), - .ce0(local_C_V_15_ce0), - .q0(local_C_V_15_q0), - .address1(local_C_V_15_address1), - .ce1(local_C_V_15_ce1), - .we1(local_C_V_15_we1), - .d1(local_C_V_15_d1) -); - -PEG_Cmtx_PEG_Cmtx_Pipeline_init_C grp_PEG_Cmtx_Pipeline_init_C_fu_325( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_start), - .ap_done(grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_done), - .ap_idle(grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_idle), - .ap_ready(grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_ready), - .trunc_ln(trunc_ln_reg_591), - .local_C_V_15_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_address1), - .local_C_V_15_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_ce1), - .local_C_V_15_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_we1), - .local_C_V_15_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_d1), - .local_C_V_14_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_address1), - .local_C_V_14_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_ce1), - .local_C_V_14_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_we1), - .local_C_V_14_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_d1), - .local_C_V_13_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_address1), - .local_C_V_13_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_ce1), - .local_C_V_13_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_we1), - .local_C_V_13_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_d1), - .local_C_V_12_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_address1), - .local_C_V_12_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_ce1), - .local_C_V_12_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_we1), - .local_C_V_12_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_d1), - .local_C_V_11_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_address1), - .local_C_V_11_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_ce1), - .local_C_V_11_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_we1), - .local_C_V_11_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_d1), - .local_C_V_10_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_address1), - .local_C_V_10_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_ce1), - .local_C_V_10_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_we1), - .local_C_V_10_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_d1), - .local_C_V_9_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_address1), - .local_C_V_9_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_ce1), - .local_C_V_9_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_we1), - .local_C_V_9_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_d1), - .local_C_V_8_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_address1), - .local_C_V_8_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_ce1), - .local_C_V_8_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_we1), - .local_C_V_8_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_d1), - .local_C_V_7_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_address1), - .local_C_V_7_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_ce1), - .local_C_V_7_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_we1), - .local_C_V_7_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_d1), - .local_C_V_6_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_address1), - .local_C_V_6_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_ce1), - .local_C_V_6_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_we1), - .local_C_V_6_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_d1), - .local_C_V_5_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_address1), - .local_C_V_5_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_ce1), - .local_C_V_5_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_we1), - .local_C_V_5_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_d1), - .local_C_V_4_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_address1), - .local_C_V_4_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_ce1), - .local_C_V_4_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_we1), - .local_C_V_4_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_d1), - .local_C_V_3_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_address1), - .local_C_V_3_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_ce1), - .local_C_V_3_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_we1), - .local_C_V_3_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_d1), - .local_C_V_2_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_address1), - .local_C_V_2_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_ce1), - .local_C_V_2_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_we1), - .local_C_V_2_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_d1), - .local_C_V_1_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_address1), - .local_C_V_1_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_ce1), - .local_C_V_1_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_we1), - .local_C_V_1_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_d1), - .local_C_V_address1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_address1), - .local_C_V_ce1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_ce1), - .local_C_V_we1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_we1), - .local_C_V_d1(grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_d1) -); - -PEG_Cmtx_PEG_Cmtx_Pipeline_write_C_outer grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_start), - .ap_done(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_done), - .ap_idle(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_idle), - .ap_ready(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_ready), - .fifo_C_out_din(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_fifo_C_out_din), - .fifo_C_out_full_n(fifo_C_out_full_n), - .fifo_C_out_write(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_fifo_C_out_write), - .num_v_out(num_v_out_reg_596), - .local_C_V_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_address0), - .local_C_V_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_ce0), - .local_C_V_q0(local_C_V_q0), - .local_C_V_4_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_4_address0), - .local_C_V_4_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_4_ce0), - .local_C_V_4_q0(local_C_V_4_q0), - .local_C_V_8_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_8_address0), - .local_C_V_8_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_8_ce0), - .local_C_V_8_q0(local_C_V_8_q0), - .local_C_V_12_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_12_address0), - .local_C_V_12_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_12_ce0), - .local_C_V_12_q0(local_C_V_12_q0), - .local_C_V_1_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_1_address0), - .local_C_V_1_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_1_ce0), - .local_C_V_1_q0(local_C_V_1_q0), - .local_C_V_5_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_5_address0), - .local_C_V_5_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_5_ce0), - .local_C_V_5_q0(local_C_V_5_q0), - .local_C_V_9_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_9_address0), - .local_C_V_9_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_9_ce0), - .local_C_V_9_q0(local_C_V_9_q0), - .local_C_V_13_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_13_address0), - .local_C_V_13_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_13_ce0), - .local_C_V_13_q0(local_C_V_13_q0), - .local_C_V_2_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_2_address0), - .local_C_V_2_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_2_ce0), - .local_C_V_2_q0(local_C_V_2_q0), - .local_C_V_6_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_6_address0), - .local_C_V_6_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_6_ce0), - .local_C_V_6_q0(local_C_V_6_q0), - .local_C_V_10_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_10_address0), - .local_C_V_10_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_10_ce0), - .local_C_V_10_q0(local_C_V_10_q0), - .local_C_V_14_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_14_address0), - .local_C_V_14_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_14_ce0), - .local_C_V_14_q0(local_C_V_14_q0), - .local_C_V_3_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_3_address0), - .local_C_V_3_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_3_ce0), - .local_C_V_3_q0(local_C_V_3_q0), - .local_C_V_7_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_7_address0), - .local_C_V_7_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_7_ce0), - .local_C_V_7_q0(local_C_V_7_q0), - .local_C_V_11_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_11_address0), - .local_C_V_11_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_11_ce0), - .local_C_V_11_q0(local_C_V_11_q0), - .local_C_V_15_address0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_15_address0), - .local_C_V_15_ce0(grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_15_ce0), - .local_C_V_15_q0(local_C_V_15_q0) -); - -PEG_Cmtx_PEG_Cmtx_Pipeline_computation grp_PEG_Cmtx_Pipeline_computation_fu_369( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_start), - .ap_done(grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_done), - .ap_idle(grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_idle), - .ap_ready(grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_ready), - .start_32_3(start_32_3_reg_315), - .end_32(end_32_reg_622), - .local_C_V_15_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_address0), - .local_C_V_15_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_ce0), - .local_C_V_15_q0(local_C_V_15_q0), - .local_C_V_15_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_address1), - .local_C_V_15_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_ce1), - .local_C_V_15_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_we1), - .local_C_V_15_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_d1), - .local_C_V_14_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_address0), - .local_C_V_14_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_ce0), - .local_C_V_14_q0(local_C_V_14_q0), - .local_C_V_14_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_address1), - .local_C_V_14_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_ce1), - .local_C_V_14_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_we1), - .local_C_V_14_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_d1), - .local_C_V_13_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_address0), - .local_C_V_13_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_ce0), - .local_C_V_13_q0(local_C_V_13_q0), - .local_C_V_13_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_address1), - .local_C_V_13_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_ce1), - .local_C_V_13_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_we1), - .local_C_V_13_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_d1), - .local_C_V_12_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_address0), - .local_C_V_12_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_ce0), - .local_C_V_12_q0(local_C_V_12_q0), - .local_C_V_12_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_address1), - .local_C_V_12_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_ce1), - .local_C_V_12_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_we1), - .local_C_V_12_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_d1), - .local_C_V_11_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_address0), - .local_C_V_11_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_ce0), - .local_C_V_11_q0(local_C_V_11_q0), - .local_C_V_11_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_address1), - .local_C_V_11_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_ce1), - .local_C_V_11_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_we1), - .local_C_V_11_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_d1), - .local_C_V_10_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_address0), - .local_C_V_10_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_ce0), - .local_C_V_10_q0(local_C_V_10_q0), - .local_C_V_10_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_address1), - .local_C_V_10_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_ce1), - .local_C_V_10_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_we1), - .local_C_V_10_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_d1), - .local_C_V_9_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_address0), - .local_C_V_9_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_ce0), - .local_C_V_9_q0(local_C_V_9_q0), - .local_C_V_9_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_address1), - .local_C_V_9_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_ce1), - .local_C_V_9_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_we1), - .local_C_V_9_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_d1), - .local_C_V_8_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_address0), - .local_C_V_8_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_ce0), - .local_C_V_8_q0(local_C_V_8_q0), - .local_C_V_8_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_address1), - .local_C_V_8_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_ce1), - .local_C_V_8_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_we1), - .local_C_V_8_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_d1), - .local_C_V_7_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_address0), - .local_C_V_7_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_ce0), - .local_C_V_7_q0(local_C_V_7_q0), - .local_C_V_7_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_address1), - .local_C_V_7_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_ce1), - .local_C_V_7_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_we1), - .local_C_V_7_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_d1), - .local_C_V_6_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_address0), - .local_C_V_6_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_ce0), - .local_C_V_6_q0(local_C_V_6_q0), - .local_C_V_6_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_address1), - .local_C_V_6_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_ce1), - .local_C_V_6_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_we1), - .local_C_V_6_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_d1), - .local_C_V_5_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_address0), - .local_C_V_5_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_ce0), - .local_C_V_5_q0(local_C_V_5_q0), - .local_C_V_5_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_address1), - .local_C_V_5_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_ce1), - .local_C_V_5_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_we1), - .local_C_V_5_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_d1), - .local_C_V_4_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_address0), - .local_C_V_4_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_ce0), - .local_C_V_4_q0(local_C_V_4_q0), - .local_C_V_4_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_address1), - .local_C_V_4_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_ce1), - .local_C_V_4_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_we1), - .local_C_V_4_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_d1), - .local_C_V_3_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_address0), - .local_C_V_3_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_ce0), - .local_C_V_3_q0(local_C_V_3_q0), - .local_C_V_3_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_address1), - .local_C_V_3_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_ce1), - .local_C_V_3_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_we1), - .local_C_V_3_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_d1), - .local_C_V_2_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_address0), - .local_C_V_2_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_ce0), - .local_C_V_2_q0(local_C_V_2_q0), - .local_C_V_2_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_address1), - .local_C_V_2_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_ce1), - .local_C_V_2_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_we1), - .local_C_V_2_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_d1), - .local_C_V_1_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_address0), - .local_C_V_1_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_ce0), - .local_C_V_1_q0(local_C_V_1_q0), - .local_C_V_1_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_address1), - .local_C_V_1_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_ce1), - .local_C_V_1_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_we1), - .local_C_V_1_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_d1), - .local_C_V_address0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_address0), - .local_C_V_ce0(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_ce0), - .local_C_V_q0(local_C_V_q0), - .local_C_V_address1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_address1), - .local_C_V_ce1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_ce1), - .local_C_V_we1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_we1), - .local_C_V_d1(grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_d1), - .fifo_aBvec_0_dout(fifo_aBvec_0_dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_0_empty_n), - .fifo_aBvec_0_read(grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_0_read), - .fifo_aBvec_1_dout(fifo_aBvec_1_dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_1_empty_n), - .fifo_aBvec_1_read(grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_1_read), - .fifo_aBvec_2_dout(fifo_aBvec_2_dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_2_empty_n), - .fifo_aBvec_2_read(grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_2_read), - .fifo_aBvec_3_dout(fifo_aBvec_3_dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_3_empty_n), - .fifo_aBvec_3_read(grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_3_read) -); - -PEG_Cmtx_mul_mul_16s_14ns_30_4_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 16 ), - .din1_WIDTH( 14 ), - .dout_WIDTH( 30 )) -mul_mul_16s_14ns_30_4_1_U96( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .din0(rp_time_fu_452_p3), - .din1(grp_fu_541_p1), - .ce(1'b1), - .dout(grp_fu_541_p2) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state11)) begin - grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_start_reg <= 1'b1; - end else if ((grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_ready == 1'b1)) begin - grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_start_reg <= 1'b0; - end else begin - if (((icmp_ln232_fu_503_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state8))) begin - grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_start_reg <= 1'b1; - end else if ((grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_ready == 1'b1)) begin - grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_start_reg <= 1'b0; - end else begin - if ((~((fifo_inst_in_s_empty_n == 1'b0) & (icmp_ln249_fu_522_p2 == 1'd1)) & (1'b1 == ap_CS_fsm_state10) & (icmp_ln249_fu_522_p2 == 1'd0))) begin - grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_start_reg <= 1'b1; - end else if ((grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_ready == 1'b1)) begin - grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (((grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin - i_1_reg_304 <= add_ln249_reg_617; - end else if ((~((fifo_inst_in_s_empty_n == 1'b0) | (grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_done == 1'b0)) & (1'b1 == ap_CS_fsm_state9))) begin - i_1_reg_304 <= 31'd0; - end -end - -always @ (posedge ap_clk) begin - if ((~((1'b0 == PE_inst_in_s_empty_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - rp_fu_120 <= 28'd0; - end else if ((~((fifo_inst_in_s_empty_n == 1'b0) & (icmp_ln249_fu_522_p2 == 1'd1)) & (1'b1 == ap_CS_fsm_state10) & (icmp_ln249_fu_522_p2 == 1'd0))) begin - rp_fu_120 <= rp_2_reg_604; - end -end - -always @ (posedge ap_clk) begin - if (((grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin - start_32_3_reg_315 <= end_32_reg_622; - end else if ((~((fifo_inst_in_s_empty_n == 1'b0) | (grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_done == 1'b0)) & (1'b1 == ap_CS_fsm_state9))) begin - start_32_3_reg_315 <= start_32_fu_514_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state2)) begin - M_reg_559 <= M_fu_409_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - N16_reg_565 <= {{PE_inst_in_s_dout[31:16]}}; - lshr_ln_reg_571 <= {{add_ln220_fu_431_p2[16:3]}}; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state1)) begin - NUM_ITE_reg_554 <= NUM_ITE_fu_400_p1; - end -end - -always @ (posedge ap_clk) begin - if ((~((fifo_inst_in_s_empty_n == 1'b0) & (icmp_ln249_fu_522_p2 == 1'd1)) & (1'b1 == ap_CS_fsm_state10))) begin - add_ln249_reg_617 <= add_ln249_fu_527_p2; - end -end - -always @ (posedge ap_clk) begin - if ((~((fifo_inst_in_s_empty_n == 1'b0) & (icmp_ln249_fu_522_p2 == 1'd1)) & (1'b1 == ap_CS_fsm_state10) & (icmp_ln249_fu_522_p2 == 1'd1))) begin - end_32_reg_622 <= end_32_fu_533_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state7)) begin - num_v_out_reg_596 <= {{add_ln223_fu_481_p2[31:4]}}; - rp_time_N_reg_586 <= grp_fu_541_p2; - trunc_ln_reg_591 <= {{add_ln221_fu_466_p2[31:6]}}; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state8)) begin - rp_2_reg_604 <= rp_2_fu_508_p2; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1)))) begin - PE_inst_in_s_blk_n = PE_inst_in_s_empty_n; - end else begin - PE_inst_in_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if ((((1'b1 == ap_CS_fsm_state2) & (1'b1 == PE_inst_in_s_empty_n)) | (~((1'b0 == PE_inst_in_s_empty_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)) | ((1'b1 == ap_CS_fsm_state3) & (1'b1 == PE_inst_in_s_empty_n)))) begin - PE_inst_in_s_read = 1'b1; - end else begin - PE_inst_in_s_read = 1'b0; - end -end - -always @ (*) begin - if (((fifo_inst_in_s_empty_n == 1'b0) & (icmp_ln249_fu_522_p2 == 1'd1))) begin - ap_ST_fsm_state10_blk = 1'b1; - end else begin - ap_ST_fsm_state10_blk = 1'b0; - end -end - -assign ap_ST_fsm_state11_blk = 1'b0; - -always @ (*) begin - if ((grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_done == 1'b0)) begin - ap_ST_fsm_state12_blk = 1'b1; - end else begin - ap_ST_fsm_state12_blk = 1'b0; - end -end - -always @ (*) begin - if ((grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_done == 1'b0)) begin - ap_ST_fsm_state13_blk = 1'b1; - end else begin - ap_ST_fsm_state13_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == PE_inst_in_s_empty_n) | (ap_start == 1'b0))) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -always @ (*) begin - if ((1'b0 == PE_inst_in_s_empty_n)) begin - ap_ST_fsm_state2_blk = 1'b1; - end else begin - ap_ST_fsm_state2_blk = 1'b0; - end -end - -always @ (*) begin - if ((1'b0 == PE_inst_in_s_empty_n)) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -assign ap_ST_fsm_state4_blk = 1'b0; - -assign ap_ST_fsm_state5_blk = 1'b0; - -assign ap_ST_fsm_state6_blk = 1'b0; - -assign ap_ST_fsm_state7_blk = 1'b0; - -assign ap_ST_fsm_state8_blk = 1'b0; - -always @ (*) begin - if (((fifo_inst_in_s_empty_n == 1'b0) | (grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_done == 1'b0))) begin - ap_ST_fsm_state9_blk = 1'b1; - end else begin - ap_ST_fsm_state9_blk = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln232_fu_503_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state8))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln232_fu_503_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state8))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state13)) begin - fifo_C_out_write = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_fifo_C_out_write; - end else begin - fifo_C_out_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_aBvec_0_read = grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_0_read; - end else begin - fifo_aBvec_0_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_aBvec_1_read = grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_1_read; - end else begin - fifo_aBvec_1_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_aBvec_2_read = grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_2_read; - end else begin - fifo_aBvec_2_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - fifo_aBvec_3_read = grp_PEG_Cmtx_Pipeline_computation_fu_369_fifo_aBvec_3_read; - end else begin - fifo_aBvec_3_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state9) | ((1'b1 == ap_CS_fsm_state10) & (icmp_ln249_fu_522_p2 == 1'd1)))) begin - fifo_inst_in_s_blk_n = fifo_inst_in_s_empty_n; - end else begin - fifo_inst_in_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((~((fifo_inst_in_s_empty_n == 1'b0) | (grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_done == 1'b0)) & (1'b1 == ap_CS_fsm_state9)) | (~((fifo_inst_in_s_empty_n == 1'b0) & (icmp_ln249_fu_522_p2 == 1'd1)) & (1'b1 == ap_CS_fsm_state10) & (icmp_ln249_fu_522_p2 == 1'd1)))) begin - fifo_inst_in_s_read = 1'b1; - end else begin - fifo_inst_in_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_10_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_10_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_10_address0; - end else begin - local_C_V_10_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_10_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_10_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_address1; - end else begin - local_C_V_10_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_10_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_10_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_10_ce0; - end else begin - local_C_V_10_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_10_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_10_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_ce1; - end else begin - local_C_V_10_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_10_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_10_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_d1; - end else begin - local_C_V_10_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_10_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_10_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_10_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_10_we1; - end else begin - local_C_V_10_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_11_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_11_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_11_address0; - end else begin - local_C_V_11_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_11_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_11_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_address1; - end else begin - local_C_V_11_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_11_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_11_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_11_ce0; - end else begin - local_C_V_11_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_11_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_11_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_ce1; - end else begin - local_C_V_11_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_11_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_11_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_d1; - end else begin - local_C_V_11_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_11_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_11_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_11_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_11_we1; - end else begin - local_C_V_11_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_12_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_12_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_12_address0; - end else begin - local_C_V_12_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_12_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_12_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_address1; - end else begin - local_C_V_12_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_12_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_12_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_12_ce0; - end else begin - local_C_V_12_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_12_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_12_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_ce1; - end else begin - local_C_V_12_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_12_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_12_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_d1; - end else begin - local_C_V_12_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_12_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_12_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_12_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_12_we1; - end else begin - local_C_V_12_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_13_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_13_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_13_address0; - end else begin - local_C_V_13_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_13_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_13_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_address1; - end else begin - local_C_V_13_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_13_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_13_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_13_ce0; - end else begin - local_C_V_13_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_13_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_13_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_ce1; - end else begin - local_C_V_13_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_13_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_13_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_d1; - end else begin - local_C_V_13_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_13_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_13_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_13_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_13_we1; - end else begin - local_C_V_13_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_14_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_14_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_14_address0; - end else begin - local_C_V_14_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_14_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_14_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_address1; - end else begin - local_C_V_14_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_14_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_14_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_14_ce0; - end else begin - local_C_V_14_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_14_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_14_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_ce1; - end else begin - local_C_V_14_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_14_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_14_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_d1; - end else begin - local_C_V_14_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_14_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_14_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_14_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_14_we1; - end else begin - local_C_V_14_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_15_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_15_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_15_address0; - end else begin - local_C_V_15_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_15_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_15_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_address1; - end else begin - local_C_V_15_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_15_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_15_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_15_ce0; - end else begin - local_C_V_15_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_15_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_15_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_ce1; - end else begin - local_C_V_15_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_15_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_15_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_d1; - end else begin - local_C_V_15_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_15_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_15_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_15_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_15_we1; - end else begin - local_C_V_15_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_1_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_1_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_1_address0; - end else begin - local_C_V_1_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_1_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_1_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_address1; - end else begin - local_C_V_1_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_1_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_1_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_1_ce0; - end else begin - local_C_V_1_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_1_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_1_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_ce1; - end else begin - local_C_V_1_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_1_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_1_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_d1; - end else begin - local_C_V_1_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_1_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_1_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_1_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_1_we1; - end else begin - local_C_V_1_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_2_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_2_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_2_address0; - end else begin - local_C_V_2_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_2_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_2_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_address1; - end else begin - local_C_V_2_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_2_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_2_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_2_ce0; - end else begin - local_C_V_2_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_2_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_2_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_ce1; - end else begin - local_C_V_2_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_2_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_2_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_d1; - end else begin - local_C_V_2_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_2_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_2_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_2_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_2_we1; - end else begin - local_C_V_2_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_3_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_3_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_3_address0; - end else begin - local_C_V_3_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_3_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_3_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_address1; - end else begin - local_C_V_3_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_3_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_3_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_3_ce0; - end else begin - local_C_V_3_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_3_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_3_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_ce1; - end else begin - local_C_V_3_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_3_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_3_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_d1; - end else begin - local_C_V_3_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_3_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_3_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_3_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_3_we1; - end else begin - local_C_V_3_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_4_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_4_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_4_address0; - end else begin - local_C_V_4_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_4_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_4_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_address1; - end else begin - local_C_V_4_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_4_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_4_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_4_ce0; - end else begin - local_C_V_4_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_4_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_4_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_ce1; - end else begin - local_C_V_4_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_4_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_4_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_d1; - end else begin - local_C_V_4_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_4_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_4_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_4_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_4_we1; - end else begin - local_C_V_4_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_5_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_5_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_5_address0; - end else begin - local_C_V_5_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_5_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_5_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_address1; - end else begin - local_C_V_5_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_5_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_5_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_5_ce0; - end else begin - local_C_V_5_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_5_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_5_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_ce1; - end else begin - local_C_V_5_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_5_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_5_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_d1; - end else begin - local_C_V_5_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_5_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_5_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_5_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_5_we1; - end else begin - local_C_V_5_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_6_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_6_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_6_address0; - end else begin - local_C_V_6_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_6_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_6_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_address1; - end else begin - local_C_V_6_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_6_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_6_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_6_ce0; - end else begin - local_C_V_6_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_6_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_6_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_ce1; - end else begin - local_C_V_6_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_6_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_6_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_d1; - end else begin - local_C_V_6_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_6_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_6_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_6_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_6_we1; - end else begin - local_C_V_6_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_7_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_7_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_7_address0; - end else begin - local_C_V_7_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_7_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_7_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_address1; - end else begin - local_C_V_7_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_7_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_7_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_7_ce0; - end else begin - local_C_V_7_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_7_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_7_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_ce1; - end else begin - local_C_V_7_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_7_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_7_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_d1; - end else begin - local_C_V_7_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_7_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_7_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_7_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_7_we1; - end else begin - local_C_V_7_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_8_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_8_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_8_address0; - end else begin - local_C_V_8_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_8_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_8_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_address1; - end else begin - local_C_V_8_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_8_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_8_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_8_ce0; - end else begin - local_C_V_8_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_8_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_8_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_ce1; - end else begin - local_C_V_8_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_8_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_8_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_d1; - end else begin - local_C_V_8_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_8_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_8_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_8_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_8_we1; - end else begin - local_C_V_8_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_9_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_9_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_9_address0; - end else begin - local_C_V_9_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_9_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_9_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_address1; - end else begin - local_C_V_9_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_9_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_9_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_9_ce0; - end else begin - local_C_V_9_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_9_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_9_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_ce1; - end else begin - local_C_V_9_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_9_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_9_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_d1; - end else begin - local_C_V_9_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_9_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_9_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_9_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_9_we1; - end else begin - local_C_V_9_we1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_address0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_address0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_address0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_address0; - end else begin - local_C_V_address0 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_address1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_address1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_address1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_address1; - end else begin - local_C_V_address1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_ce0 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_ce0; - end else if ((1'b1 == ap_CS_fsm_state13)) begin - local_C_V_ce0 = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_local_C_V_ce0; - end else begin - local_C_V_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_ce1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_ce1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_ce1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_ce1; - end else begin - local_C_V_ce1 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_d1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_d1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_d1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_d1; - end else begin - local_C_V_d1 = 'bx; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state12)) begin - local_C_V_we1 = grp_PEG_Cmtx_Pipeline_computation_fu_369_local_C_V_we1; - end else if ((1'b1 == ap_CS_fsm_state9)) begin - local_C_V_we1 = grp_PEG_Cmtx_Pipeline_init_C_fu_325_local_C_V_we1; - end else begin - local_C_V_we1 = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if ((~((1'b0 == PE_inst_in_s_empty_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - if (((1'b1 == ap_CS_fsm_state2) & (1'b1 == PE_inst_in_s_empty_n))) begin - ap_NS_fsm = ap_ST_fsm_state3; - end else begin - ap_NS_fsm = ap_ST_fsm_state2; - end - end - ap_ST_fsm_state3 : begin - if (((1'b1 == ap_CS_fsm_state3) & (1'b1 == PE_inst_in_s_empty_n))) begin - ap_NS_fsm = ap_ST_fsm_state4; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - ap_ST_fsm_state4 : begin - ap_NS_fsm = ap_ST_fsm_state5; - end - ap_ST_fsm_state5 : begin - ap_NS_fsm = ap_ST_fsm_state6; - end - ap_ST_fsm_state6 : begin - ap_NS_fsm = ap_ST_fsm_state7; - end - ap_ST_fsm_state7 : begin - ap_NS_fsm = ap_ST_fsm_state8; - end - ap_ST_fsm_state8 : begin - if (((icmp_ln232_fu_503_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state8))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state9; - end - end - ap_ST_fsm_state9 : begin - if ((~((fifo_inst_in_s_empty_n == 1'b0) | (grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_done == 1'b0)) & (1'b1 == ap_CS_fsm_state9))) begin - ap_NS_fsm = ap_ST_fsm_state10; - end else begin - ap_NS_fsm = ap_ST_fsm_state9; - end - end - ap_ST_fsm_state10 : begin - if ((~((fifo_inst_in_s_empty_n == 1'b0) & (icmp_ln249_fu_522_p2 == 1'd1)) & (1'b1 == ap_CS_fsm_state10) & (icmp_ln249_fu_522_p2 == 1'd0))) begin - ap_NS_fsm = ap_ST_fsm_state13; - end else if ((~((fifo_inst_in_s_empty_n == 1'b0) & (icmp_ln249_fu_522_p2 == 1'd1)) & (1'b1 == ap_CS_fsm_state10) & (icmp_ln249_fu_522_p2 == 1'd1))) begin - ap_NS_fsm = ap_ST_fsm_state11; - end else begin - ap_NS_fsm = ap_ST_fsm_state10; - end - end - ap_ST_fsm_state11 : begin - ap_NS_fsm = ap_ST_fsm_state12; - end - ap_ST_fsm_state12 : begin - if (((grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin - ap_NS_fsm = ap_ST_fsm_state10; - end else begin - ap_NS_fsm = ap_ST_fsm_state12; - end - end - ap_ST_fsm_state13 : begin - if (((grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state13))) begin - ap_NS_fsm = ap_ST_fsm_state8; - end else begin - ap_NS_fsm = ap_ST_fsm_state13; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign M_fu_409_p1 = PE_inst_in_s_dout[31:0]; - -assign NUM_ITE_fu_400_p1 = PE_inst_in_s_dout[31:0]; - -assign N_fu_413_p1 = PE_inst_in_s_dout[15:0]; - -assign PE_inst_in_peek_read = 1'b0; - -assign add_ln220_fu_431_p2 = (zext_ln219_fu_427_p1 + 17'd7); - -assign add_ln221_fu_466_p2 = (M_reg_559 + 32'd63); - -assign add_ln223_fu_481_p2 = (M_reg_559 + 32'd15); - -assign add_ln249_fu_527_p2 = (i_1_reg_304 + 31'd1); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; - -assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; - -assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; - -assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; - -assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; - -assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; - -assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; - -always @ (*) begin - ap_block_state1 = ((1'b0 == PE_inst_in_s_empty_n) | (ap_start == 1'b0)); -end - -always @ (*) begin - ap_block_state10 = ((fifo_inst_in_s_empty_n == 1'b0) & (icmp_ln249_fu_522_p2 == 1'd1)); -end - -always @ (*) begin - ap_block_state10_ignore_call1 = ((fifo_inst_in_s_empty_n == 1'b0) & (icmp_ln249_fu_522_p2 == 1'd1)); -end - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign end_32_fu_533_p1 = fifo_inst_in_s_dout[31:0]; - -assign fifo_C_out_din = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_fifo_C_out_din; - -assign fifo_aBvec_peek_0_read = 1'b0; - -assign fifo_aBvec_peek_1_read = 1'b0; - -assign fifo_aBvec_peek_2_read = 1'b0; - -assign fifo_aBvec_peek_3_read = 1'b0; - -assign fifo_inst_in_peek_read = 1'b0; - -assign grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_start = grp_PEG_Cmtx_Pipeline_computation_fu_369_ap_start_reg; - -assign grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_start = grp_PEG_Cmtx_Pipeline_init_C_fu_325_ap_start_reg; - -assign grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_start = grp_PEG_Cmtx_Pipeline_write_C_outer_fu_346_ap_start_reg; - -assign grp_fu_541_p1 = grp_fu_541_p10; - -assign grp_fu_541_p10 = lshr_ln_reg_571; - -assign icmp_ln218_fu_447_p2 = ((N16_reg_565 == 16'd0) ? 1'b1 : 1'b0); - -assign icmp_ln232_fu_503_p2 = (($signed(zext_ln232_fu_499_p1) < $signed(rp_time_N_reg_586)) ? 1'b1 : 1'b0); - -assign icmp_ln249_fu_522_p2 = (($signed(zext_ln249_fu_518_p1) < $signed(NUM_ITE_reg_554)) ? 1'b1 : 1'b0); - -assign rp_2_fu_508_p2 = (rp_fu_120 + 28'd1); - -assign rp_time_fu_452_p3 = ((icmp_ln218_fu_447_p2[0:0] == 1'b1) ? 16'd1 : N16_reg_565); - -assign start_32_fu_514_p1 = fifo_inst_in_s_dout[31:0]; - -assign zext_ln219_fu_427_p1 = N_fu_413_p1; - -assign zext_ln232_fu_499_p1 = rp_fu_120; - -assign zext_ln249_fu_518_p1 = i_1_reg_304; - -endmodule //PEG_Cmtx diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_PEG_Cmtx_Pipeline_computation.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_PEG_Cmtx_Pipeline_computation.v deleted file mode 100644 index bc9f8616..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_PEG_Cmtx_Pipeline_computation.v +++ /dev/null @@ -1,3460 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module PEG_Cmtx_PEG_Cmtx_Pipeline_computation ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - start_32_3, - end_32, - local_C_V_15_address0, - local_C_V_15_ce0, - local_C_V_15_q0, - local_C_V_15_address1, - local_C_V_15_ce1, - local_C_V_15_we1, - local_C_V_15_d1, - local_C_V_14_address0, - local_C_V_14_ce0, - local_C_V_14_q0, - local_C_V_14_address1, - local_C_V_14_ce1, - local_C_V_14_we1, - local_C_V_14_d1, - local_C_V_13_address0, - local_C_V_13_ce0, - local_C_V_13_q0, - local_C_V_13_address1, - local_C_V_13_ce1, - local_C_V_13_we1, - local_C_V_13_d1, - local_C_V_12_address0, - local_C_V_12_ce0, - local_C_V_12_q0, - local_C_V_12_address1, - local_C_V_12_ce1, - local_C_V_12_we1, - local_C_V_12_d1, - local_C_V_11_address0, - local_C_V_11_ce0, - local_C_V_11_q0, - local_C_V_11_address1, - local_C_V_11_ce1, - local_C_V_11_we1, - local_C_V_11_d1, - local_C_V_10_address0, - local_C_V_10_ce0, - local_C_V_10_q0, - local_C_V_10_address1, - local_C_V_10_ce1, - local_C_V_10_we1, - local_C_V_10_d1, - local_C_V_9_address0, - local_C_V_9_ce0, - local_C_V_9_q0, - local_C_V_9_address1, - local_C_V_9_ce1, - local_C_V_9_we1, - local_C_V_9_d1, - local_C_V_8_address0, - local_C_V_8_ce0, - local_C_V_8_q0, - local_C_V_8_address1, - local_C_V_8_ce1, - local_C_V_8_we1, - local_C_V_8_d1, - local_C_V_7_address0, - local_C_V_7_ce0, - local_C_V_7_q0, - local_C_V_7_address1, - local_C_V_7_ce1, - local_C_V_7_we1, - local_C_V_7_d1, - local_C_V_6_address0, - local_C_V_6_ce0, - local_C_V_6_q0, - local_C_V_6_address1, - local_C_V_6_ce1, - local_C_V_6_we1, - local_C_V_6_d1, - local_C_V_5_address0, - local_C_V_5_ce0, - local_C_V_5_q0, - local_C_V_5_address1, - local_C_V_5_ce1, - local_C_V_5_we1, - local_C_V_5_d1, - local_C_V_4_address0, - local_C_V_4_ce0, - local_C_V_4_q0, - local_C_V_4_address1, - local_C_V_4_ce1, - local_C_V_4_we1, - local_C_V_4_d1, - local_C_V_3_address0, - local_C_V_3_ce0, - local_C_V_3_q0, - local_C_V_3_address1, - local_C_V_3_ce1, - local_C_V_3_we1, - local_C_V_3_d1, - local_C_V_2_address0, - local_C_V_2_ce0, - local_C_V_2_q0, - local_C_V_2_address1, - local_C_V_2_ce1, - local_C_V_2_we1, - local_C_V_2_d1, - local_C_V_1_address0, - local_C_V_1_ce0, - local_C_V_1_q0, - local_C_V_1_address1, - local_C_V_1_ce1, - local_C_V_1_we1, - local_C_V_1_d1, - local_C_V_address0, - local_C_V_ce0, - local_C_V_q0, - local_C_V_address1, - local_C_V_ce1, - local_C_V_we1, - local_C_V_d1, - fifo_aBvec_0_dout, - fifo_aBvec_0_empty_n, - fifo_aBvec_0_read, - fifo_aBvec_1_dout, - fifo_aBvec_1_empty_n, - fifo_aBvec_1_read, - fifo_aBvec_2_dout, - fifo_aBvec_2_empty_n, - fifo_aBvec_2_read, - fifo_aBvec_3_dout, - fifo_aBvec_3_empty_n, - fifo_aBvec_3_read -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [31:0] start_32_3; -input [31:0] end_32; -output [12:0] local_C_V_15_address0; -output local_C_V_15_ce0; -input [63:0] local_C_V_15_q0; -output [12:0] local_C_V_15_address1; -output local_C_V_15_ce1; -output local_C_V_15_we1; -output [63:0] local_C_V_15_d1; -output [12:0] local_C_V_14_address0; -output local_C_V_14_ce0; -input [63:0] local_C_V_14_q0; -output [12:0] local_C_V_14_address1; -output local_C_V_14_ce1; -output local_C_V_14_we1; -output [63:0] local_C_V_14_d1; -output [12:0] local_C_V_13_address0; -output local_C_V_13_ce0; -input [63:0] local_C_V_13_q0; -output [12:0] local_C_V_13_address1; -output local_C_V_13_ce1; -output local_C_V_13_we1; -output [63:0] local_C_V_13_d1; -output [12:0] local_C_V_12_address0; -output local_C_V_12_ce0; -input [63:0] local_C_V_12_q0; -output [12:0] local_C_V_12_address1; -output local_C_V_12_ce1; -output local_C_V_12_we1; -output [63:0] local_C_V_12_d1; -output [12:0] local_C_V_11_address0; -output local_C_V_11_ce0; -input [63:0] local_C_V_11_q0; -output [12:0] local_C_V_11_address1; -output local_C_V_11_ce1; -output local_C_V_11_we1; -output [63:0] local_C_V_11_d1; -output [12:0] local_C_V_10_address0; -output local_C_V_10_ce0; -input [63:0] local_C_V_10_q0; -output [12:0] local_C_V_10_address1; -output local_C_V_10_ce1; -output local_C_V_10_we1; -output [63:0] local_C_V_10_d1; -output [12:0] local_C_V_9_address0; -output local_C_V_9_ce0; -input [63:0] local_C_V_9_q0; -output [12:0] local_C_V_9_address1; -output local_C_V_9_ce1; -output local_C_V_9_we1; -output [63:0] local_C_V_9_d1; -output [12:0] local_C_V_8_address0; -output local_C_V_8_ce0; -input [63:0] local_C_V_8_q0; -output [12:0] local_C_V_8_address1; -output local_C_V_8_ce1; -output local_C_V_8_we1; -output [63:0] local_C_V_8_d1; -output [12:0] local_C_V_7_address0; -output local_C_V_7_ce0; -input [63:0] local_C_V_7_q0; -output [12:0] local_C_V_7_address1; -output local_C_V_7_ce1; -output local_C_V_7_we1; -output [63:0] local_C_V_7_d1; -output [12:0] local_C_V_6_address0; -output local_C_V_6_ce0; -input [63:0] local_C_V_6_q0; -output [12:0] local_C_V_6_address1; -output local_C_V_6_ce1; -output local_C_V_6_we1; -output [63:0] local_C_V_6_d1; -output [12:0] local_C_V_5_address0; -output local_C_V_5_ce0; -input [63:0] local_C_V_5_q0; -output [12:0] local_C_V_5_address1; -output local_C_V_5_ce1; -output local_C_V_5_we1; -output [63:0] local_C_V_5_d1; -output [12:0] local_C_V_4_address0; -output local_C_V_4_ce0; -input [63:0] local_C_V_4_q0; -output [12:0] local_C_V_4_address1; -output local_C_V_4_ce1; -output local_C_V_4_we1; -output [63:0] local_C_V_4_d1; -output [12:0] local_C_V_3_address0; -output local_C_V_3_ce0; -input [63:0] local_C_V_3_q0; -output [12:0] local_C_V_3_address1; -output local_C_V_3_ce1; -output local_C_V_3_we1; -output [63:0] local_C_V_3_d1; -output [12:0] local_C_V_2_address0; -output local_C_V_2_ce0; -input [63:0] local_C_V_2_q0; -output [12:0] local_C_V_2_address1; -output local_C_V_2_ce1; -output local_C_V_2_we1; -output [63:0] local_C_V_2_d1; -output [12:0] local_C_V_1_address0; -output local_C_V_1_ce0; -input [63:0] local_C_V_1_q0; -output [12:0] local_C_V_1_address1; -output local_C_V_1_ce1; -output local_C_V_1_we1; -output [63:0] local_C_V_1_d1; -output [12:0] local_C_V_address0; -output local_C_V_ce0; -input [63:0] local_C_V_q0; -output [12:0] local_C_V_address1; -output local_C_V_ce1; -output local_C_V_we1; -output [63:0] local_C_V_d1; -input [274:0] fifo_aBvec_0_dout; -input fifo_aBvec_0_empty_n; -output fifo_aBvec_0_read; -input [274:0] fifo_aBvec_1_dout; -input fifo_aBvec_1_empty_n; -output fifo_aBvec_1_read; -input [274:0] fifo_aBvec_2_dout; -input fifo_aBvec_2_empty_n; -output fifo_aBvec_2_read; -input [274:0] fifo_aBvec_3_dout; -input fifo_aBvec_3_empty_n; -output fifo_aBvec_3_read; - -reg ap_idle; -reg local_C_V_15_ce0; -reg local_C_V_15_ce1; -reg local_C_V_15_we1; -reg local_C_V_14_ce0; -reg local_C_V_14_ce1; -reg local_C_V_14_we1; -reg local_C_V_13_ce0; -reg local_C_V_13_ce1; -reg local_C_V_13_we1; -reg local_C_V_12_ce0; -reg local_C_V_12_ce1; -reg local_C_V_12_we1; -reg local_C_V_11_ce0; -reg local_C_V_11_ce1; -reg local_C_V_11_we1; -reg local_C_V_10_ce0; -reg local_C_V_10_ce1; -reg local_C_V_10_we1; -reg local_C_V_9_ce0; -reg local_C_V_9_ce1; -reg local_C_V_9_we1; -reg local_C_V_8_ce0; -reg local_C_V_8_ce1; -reg local_C_V_8_we1; -reg local_C_V_7_ce0; -reg local_C_V_7_ce1; -reg local_C_V_7_we1; -reg local_C_V_6_ce0; -reg local_C_V_6_ce1; -reg local_C_V_6_we1; -reg local_C_V_5_ce0; -reg local_C_V_5_ce1; -reg local_C_V_5_we1; -reg local_C_V_4_ce0; -reg local_C_V_4_ce1; -reg local_C_V_4_we1; -reg local_C_V_3_ce0; -reg local_C_V_3_ce1; -reg local_C_V_3_we1; -reg local_C_V_2_ce0; -reg local_C_V_2_ce1; -reg local_C_V_2_we1; -reg local_C_V_1_ce0; -reg local_C_V_1_ce1; -reg local_C_V_1_we1; -reg local_C_V_ce0; -reg local_C_V_ce1; -reg local_C_V_we1; -reg fifo_aBvec_0_read; -reg fifo_aBvec_1_read; -reg fifo_aBvec_2_read; -reg fifo_aBvec_3_read; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_enable_reg_pp0_iter2; -reg ap_enable_reg_pp0_iter3; -reg ap_enable_reg_pp0_iter4; -reg ap_enable_reg_pp0_iter5; -reg ap_enable_reg_pp0_iter6; -reg ap_enable_reg_pp0_iter7; -reg ap_enable_reg_pp0_iter8; -reg ap_enable_reg_pp0_iter9; -reg ap_enable_reg_pp0_iter10; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -wire ap_block_state3_pp0_stage0_iter2; -wire ap_block_state4_pp0_stage0_iter3; -wire ap_block_state5_pp0_stage0_iter4; -wire ap_block_state6_pp0_stage0_iter5; -wire ap_block_state7_pp0_stage0_iter6; -wire ap_block_state8_pp0_stage0_iter7; -wire ap_block_state9_pp0_stage0_iter8; -wire ap_block_state10_pp0_stage0_iter9; -wire ap_block_state11_pp0_stage0_iter10; -wire ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln254_fu_610_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -wire ap_block_pp0_stage0_11001; -wire [0:0] and_ln260_2_fu_628_p2; -reg [0:0] and_ln260_2_reg_1788; -reg [0:0] and_ln260_2_reg_1788_pp0_iter1_reg; -reg [0:0] and_ln260_2_reg_1788_pp0_iter2_reg; -reg [0:0] and_ln260_2_reg_1788_pp0_iter3_reg; -reg [0:0] and_ln260_2_reg_1788_pp0_iter4_reg; -reg [0:0] and_ln260_2_reg_1788_pp0_iter5_reg; -reg [0:0] and_ln260_2_reg_1788_pp0_iter6_reg; -reg [0:0] and_ln260_2_reg_1788_pp0_iter7_reg; -reg [0:0] and_ln260_2_reg_1788_pp0_iter8_reg; -reg [0:0] and_ln260_2_reg_1788_pp0_iter9_reg; -wire [17:0] elem_val_row_V_3_fu_638_p1; -reg [17:0] elem_val_row_V_3_reg_1792; -wire [31:0] elem_val_abvec_M_elems_fu_722_p1; -reg [31:0] elem_val_abvec_M_elems_reg_1797; -reg [31:0] elem_val_abvec_M_elems_reg_1797_pp0_iter1_reg; -reg [31:0] elem_val_abvec_M_elems_reg_1797_pp0_iter2_reg; -wire [31:0] elem_val_abvec_M_elems_1_fu_726_p1; -reg [31:0] elem_val_abvec_M_elems_1_reg_1802; -reg [31:0] elem_val_abvec_M_elems_1_reg_1802_pp0_iter1_reg; -reg [31:0] elem_val_abvec_M_elems_1_reg_1802_pp0_iter2_reg; -wire [31:0] bitcast_ln78_fu_730_p1; -reg [31:0] bitcast_ln78_reg_1807; -reg [31:0] bitcast_ln78_reg_1807_pp0_iter1_reg; -reg [31:0] bitcast_ln78_reg_1807_pp0_iter2_reg; -wire [31:0] bitcast_ln78_1_fu_734_p1; -reg [31:0] bitcast_ln78_1_reg_1812; -reg [31:0] bitcast_ln78_1_reg_1812_pp0_iter1_reg; -reg [31:0] bitcast_ln78_1_reg_1812_pp0_iter2_reg; -wire [31:0] bitcast_ln78_2_fu_738_p1; -reg [31:0] bitcast_ln78_2_reg_1817; -reg [31:0] bitcast_ln78_2_reg_1817_pp0_iter1_reg; -reg [31:0] bitcast_ln78_2_reg_1817_pp0_iter2_reg; -wire [31:0] bitcast_ln78_3_fu_742_p1; -reg [31:0] bitcast_ln78_3_reg_1822; -reg [31:0] bitcast_ln78_3_reg_1822_pp0_iter1_reg; -reg [31:0] bitcast_ln78_3_reg_1822_pp0_iter2_reg; -wire [31:0] bitcast_ln78_4_fu_746_p1; -reg [31:0] bitcast_ln78_4_reg_1827; -reg [31:0] bitcast_ln78_4_reg_1827_pp0_iter1_reg; -reg [31:0] bitcast_ln78_4_reg_1827_pp0_iter2_reg; -wire [31:0] bitcast_ln78_5_fu_750_p1; -reg [31:0] bitcast_ln78_5_reg_1832; -reg [31:0] bitcast_ln78_5_reg_1832_pp0_iter1_reg; -reg [31:0] bitcast_ln78_5_reg_1832_pp0_iter2_reg; -reg [0:0] p_Result_s_reg_1837; -reg [0:0] p_Result_s_reg_1837_pp0_iter1_reg; -reg [0:0] p_Result_s_reg_1837_pp0_iter2_reg; -reg [0:0] p_Result_s_reg_1837_pp0_iter3_reg; -reg [0:0] p_Result_s_reg_1837_pp0_iter4_reg; -reg [0:0] p_Result_s_reg_1837_pp0_iter5_reg; -reg [0:0] p_Result_s_reg_1837_pp0_iter6_reg; -reg [0:0] p_Result_s_reg_1837_pp0_iter7_reg; -reg [0:0] p_Result_s_reg_1837_pp0_iter8_reg; -reg [0:0] p_Result_s_reg_1837_pp0_iter9_reg; -wire [17:0] elem_val_row_V_2_fu_766_p1; -reg [17:0] elem_val_row_V_2_reg_1841; -wire [31:0] elem_val_abvec_M_elems_2_fu_850_p1; -reg [31:0] elem_val_abvec_M_elems_2_reg_1846; -reg [31:0] elem_val_abvec_M_elems_2_reg_1846_pp0_iter1_reg; -reg [31:0] elem_val_abvec_M_elems_2_reg_1846_pp0_iter2_reg; -wire [31:0] elem_val_abvec_M_elems_3_fu_854_p1; -reg [31:0] elem_val_abvec_M_elems_3_reg_1851; -reg [31:0] elem_val_abvec_M_elems_3_reg_1851_pp0_iter1_reg; -reg [31:0] elem_val_abvec_M_elems_3_reg_1851_pp0_iter2_reg; -wire [31:0] bitcast_ln78_8_fu_858_p1; -reg [31:0] bitcast_ln78_8_reg_1856; -reg [31:0] bitcast_ln78_8_reg_1856_pp0_iter1_reg; -reg [31:0] bitcast_ln78_8_reg_1856_pp0_iter2_reg; -wire [31:0] bitcast_ln78_9_fu_862_p1; -reg [31:0] bitcast_ln78_9_reg_1861; -reg [31:0] bitcast_ln78_9_reg_1861_pp0_iter1_reg; -reg [31:0] bitcast_ln78_9_reg_1861_pp0_iter2_reg; -wire [31:0] bitcast_ln78_10_fu_866_p1; -reg [31:0] bitcast_ln78_10_reg_1866; -reg [31:0] bitcast_ln78_10_reg_1866_pp0_iter1_reg; -reg [31:0] bitcast_ln78_10_reg_1866_pp0_iter2_reg; -wire [31:0] bitcast_ln78_11_fu_870_p1; -reg [31:0] bitcast_ln78_11_reg_1871; -reg [31:0] bitcast_ln78_11_reg_1871_pp0_iter1_reg; -reg [31:0] bitcast_ln78_11_reg_1871_pp0_iter2_reg; -wire [31:0] bitcast_ln78_12_fu_874_p1; -reg [31:0] bitcast_ln78_12_reg_1876; -reg [31:0] bitcast_ln78_12_reg_1876_pp0_iter1_reg; -reg [31:0] bitcast_ln78_12_reg_1876_pp0_iter2_reg; -wire [31:0] bitcast_ln78_13_fu_878_p1; -reg [31:0] bitcast_ln78_13_reg_1881; -reg [31:0] bitcast_ln78_13_reg_1881_pp0_iter1_reg; -reg [31:0] bitcast_ln78_13_reg_1881_pp0_iter2_reg; -reg [0:0] p_Result_5_reg_1886; -reg [0:0] p_Result_5_reg_1886_pp0_iter1_reg; -reg [0:0] p_Result_5_reg_1886_pp0_iter2_reg; -reg [0:0] p_Result_5_reg_1886_pp0_iter3_reg; -reg [0:0] p_Result_5_reg_1886_pp0_iter4_reg; -reg [0:0] p_Result_5_reg_1886_pp0_iter5_reg; -reg [0:0] p_Result_5_reg_1886_pp0_iter6_reg; -reg [0:0] p_Result_5_reg_1886_pp0_iter7_reg; -reg [0:0] p_Result_5_reg_1886_pp0_iter8_reg; -reg [0:0] p_Result_5_reg_1886_pp0_iter9_reg; -wire [17:0] elem_val_row_V_1_fu_894_p1; -reg [17:0] elem_val_row_V_1_reg_1890; -wire [31:0] elem_val_abvec_M_elems_4_fu_978_p1; -reg [31:0] elem_val_abvec_M_elems_4_reg_1895; -reg [31:0] elem_val_abvec_M_elems_4_reg_1895_pp0_iter1_reg; -reg [31:0] elem_val_abvec_M_elems_4_reg_1895_pp0_iter2_reg; -wire [31:0] elem_val_abvec_M_elems_5_fu_982_p1; -reg [31:0] elem_val_abvec_M_elems_5_reg_1900; -reg [31:0] elem_val_abvec_M_elems_5_reg_1900_pp0_iter1_reg; -reg [31:0] elem_val_abvec_M_elems_5_reg_1900_pp0_iter2_reg; -wire [31:0] bitcast_ln78_16_fu_986_p1; -reg [31:0] bitcast_ln78_16_reg_1905; -reg [31:0] bitcast_ln78_16_reg_1905_pp0_iter1_reg; -reg [31:0] bitcast_ln78_16_reg_1905_pp0_iter2_reg; -wire [31:0] bitcast_ln78_17_fu_990_p1; -reg [31:0] bitcast_ln78_17_reg_1910; -reg [31:0] bitcast_ln78_17_reg_1910_pp0_iter1_reg; -reg [31:0] bitcast_ln78_17_reg_1910_pp0_iter2_reg; -wire [31:0] bitcast_ln78_18_fu_994_p1; -reg [31:0] bitcast_ln78_18_reg_1915; -reg [31:0] bitcast_ln78_18_reg_1915_pp0_iter1_reg; -reg [31:0] bitcast_ln78_18_reg_1915_pp0_iter2_reg; -wire [31:0] bitcast_ln78_19_fu_998_p1; -reg [31:0] bitcast_ln78_19_reg_1920; -reg [31:0] bitcast_ln78_19_reg_1920_pp0_iter1_reg; -reg [31:0] bitcast_ln78_19_reg_1920_pp0_iter2_reg; -wire [31:0] bitcast_ln78_20_fu_1002_p1; -reg [31:0] bitcast_ln78_20_reg_1925; -reg [31:0] bitcast_ln78_20_reg_1925_pp0_iter1_reg; -reg [31:0] bitcast_ln78_20_reg_1925_pp0_iter2_reg; -wire [31:0] bitcast_ln78_21_fu_1006_p1; -reg [31:0] bitcast_ln78_21_reg_1930; -reg [31:0] bitcast_ln78_21_reg_1930_pp0_iter1_reg; -reg [31:0] bitcast_ln78_21_reg_1930_pp0_iter2_reg; -reg [0:0] p_Result_10_reg_1935; -reg [0:0] p_Result_10_reg_1935_pp0_iter1_reg; -reg [0:0] p_Result_10_reg_1935_pp0_iter2_reg; -reg [0:0] p_Result_10_reg_1935_pp0_iter3_reg; -reg [0:0] p_Result_10_reg_1935_pp0_iter4_reg; -reg [0:0] p_Result_10_reg_1935_pp0_iter5_reg; -reg [0:0] p_Result_10_reg_1935_pp0_iter6_reg; -reg [0:0] p_Result_10_reg_1935_pp0_iter7_reg; -reg [0:0] p_Result_10_reg_1935_pp0_iter8_reg; -reg [0:0] p_Result_10_reg_1935_pp0_iter9_reg; -wire [17:0] elem_val_row_V_fu_1022_p1; -reg [17:0] elem_val_row_V_reg_1939; -wire [31:0] elem_val_abvec_M_elems_6_fu_1106_p1; -reg [31:0] elem_val_abvec_M_elems_6_reg_1944; -reg [31:0] elem_val_abvec_M_elems_6_reg_1944_pp0_iter1_reg; -reg [31:0] elem_val_abvec_M_elems_6_reg_1944_pp0_iter2_reg; -wire [31:0] elem_val_abvec_M_elems_7_fu_1110_p1; -reg [31:0] elem_val_abvec_M_elems_7_reg_1949; -reg [31:0] elem_val_abvec_M_elems_7_reg_1949_pp0_iter1_reg; -reg [31:0] elem_val_abvec_M_elems_7_reg_1949_pp0_iter2_reg; -wire [31:0] bitcast_ln78_24_fu_1114_p1; -reg [31:0] bitcast_ln78_24_reg_1954; -reg [31:0] bitcast_ln78_24_reg_1954_pp0_iter1_reg; -reg [31:0] bitcast_ln78_24_reg_1954_pp0_iter2_reg; -wire [31:0] bitcast_ln78_25_fu_1118_p1; -reg [31:0] bitcast_ln78_25_reg_1959; -reg [31:0] bitcast_ln78_25_reg_1959_pp0_iter1_reg; -reg [31:0] bitcast_ln78_25_reg_1959_pp0_iter2_reg; -wire [31:0] bitcast_ln78_26_fu_1122_p1; -reg [31:0] bitcast_ln78_26_reg_1964; -reg [31:0] bitcast_ln78_26_reg_1964_pp0_iter1_reg; -reg [31:0] bitcast_ln78_26_reg_1964_pp0_iter2_reg; -wire [31:0] bitcast_ln78_27_fu_1126_p1; -reg [31:0] bitcast_ln78_27_reg_1969; -reg [31:0] bitcast_ln78_27_reg_1969_pp0_iter1_reg; -reg [31:0] bitcast_ln78_27_reg_1969_pp0_iter2_reg; -wire [31:0] bitcast_ln78_28_fu_1130_p1; -reg [31:0] bitcast_ln78_28_reg_1974; -reg [31:0] bitcast_ln78_28_reg_1974_pp0_iter1_reg; -reg [31:0] bitcast_ln78_28_reg_1974_pp0_iter2_reg; -wire [31:0] bitcast_ln78_29_fu_1134_p1; -reg [31:0] bitcast_ln78_29_reg_1979; -reg [31:0] bitcast_ln78_29_reg_1979_pp0_iter1_reg; -reg [31:0] bitcast_ln78_29_reg_1979_pp0_iter2_reg; -reg [0:0] p_Result_15_reg_1984; -reg [0:0] p_Result_15_reg_1984_pp0_iter1_reg; -reg [0:0] p_Result_15_reg_1984_pp0_iter2_reg; -reg [0:0] p_Result_15_reg_1984_pp0_iter3_reg; -reg [0:0] p_Result_15_reg_1984_pp0_iter4_reg; -reg [0:0] p_Result_15_reg_1984_pp0_iter5_reg; -reg [0:0] p_Result_15_reg_1984_pp0_iter6_reg; -reg [0:0] p_Result_15_reg_1984_pp0_iter7_reg; -reg [0:0] p_Result_15_reg_1984_pp0_iter8_reg; -reg [0:0] p_Result_15_reg_1984_pp0_iter9_reg; -reg [12:0] local_C_V_addr_reg_1988; -reg [12:0] local_C_V_addr_reg_1988_pp0_iter2_reg; -reg [12:0] local_C_V_addr_reg_1988_pp0_iter3_reg; -reg [12:0] local_C_V_addr_reg_1988_pp0_iter4_reg; -reg [12:0] local_C_V_addr_reg_1988_pp0_iter5_reg; -reg [12:0] local_C_V_addr_reg_1988_pp0_iter6_reg; -reg [12:0] local_C_V_addr_reg_1988_pp0_iter7_reg; -reg [12:0] local_C_V_addr_reg_1988_pp0_iter8_reg; -reg [12:0] local_C_V_addr_reg_1988_pp0_iter9_reg; -reg [12:0] local_C_V_1_addr_reg_1994; -reg [12:0] local_C_V_1_addr_reg_1994_pp0_iter2_reg; -reg [12:0] local_C_V_1_addr_reg_1994_pp0_iter3_reg; -reg [12:0] local_C_V_1_addr_reg_1994_pp0_iter4_reg; -reg [12:0] local_C_V_1_addr_reg_1994_pp0_iter5_reg; -reg [12:0] local_C_V_1_addr_reg_1994_pp0_iter6_reg; -reg [12:0] local_C_V_1_addr_reg_1994_pp0_iter7_reg; -reg [12:0] local_C_V_1_addr_reg_1994_pp0_iter8_reg; -reg [12:0] local_C_V_1_addr_reg_1994_pp0_iter9_reg; -reg [12:0] local_C_V_2_addr_reg_2000; -reg [12:0] local_C_V_2_addr_reg_2000_pp0_iter2_reg; -reg [12:0] local_C_V_2_addr_reg_2000_pp0_iter3_reg; -reg [12:0] local_C_V_2_addr_reg_2000_pp0_iter4_reg; -reg [12:0] local_C_V_2_addr_reg_2000_pp0_iter5_reg; -reg [12:0] local_C_V_2_addr_reg_2000_pp0_iter6_reg; -reg [12:0] local_C_V_2_addr_reg_2000_pp0_iter7_reg; -reg [12:0] local_C_V_2_addr_reg_2000_pp0_iter8_reg; -reg [12:0] local_C_V_2_addr_reg_2000_pp0_iter9_reg; -reg [12:0] local_C_V_3_addr_reg_2006; -reg [12:0] local_C_V_3_addr_reg_2006_pp0_iter2_reg; -reg [12:0] local_C_V_3_addr_reg_2006_pp0_iter3_reg; -reg [12:0] local_C_V_3_addr_reg_2006_pp0_iter4_reg; -reg [12:0] local_C_V_3_addr_reg_2006_pp0_iter5_reg; -reg [12:0] local_C_V_3_addr_reg_2006_pp0_iter6_reg; -reg [12:0] local_C_V_3_addr_reg_2006_pp0_iter7_reg; -reg [12:0] local_C_V_3_addr_reg_2006_pp0_iter8_reg; -reg [12:0] local_C_V_3_addr_reg_2006_pp0_iter9_reg; -reg [12:0] local_C_V_4_addr_reg_2012; -reg [12:0] local_C_V_4_addr_reg_2012_pp0_iter2_reg; -reg [12:0] local_C_V_4_addr_reg_2012_pp0_iter3_reg; -reg [12:0] local_C_V_4_addr_reg_2012_pp0_iter4_reg; -reg [12:0] local_C_V_4_addr_reg_2012_pp0_iter5_reg; -reg [12:0] local_C_V_4_addr_reg_2012_pp0_iter6_reg; -reg [12:0] local_C_V_4_addr_reg_2012_pp0_iter7_reg; -reg [12:0] local_C_V_4_addr_reg_2012_pp0_iter8_reg; -reg [12:0] local_C_V_4_addr_reg_2012_pp0_iter9_reg; -reg [12:0] local_C_V_5_addr_reg_2018; -reg [12:0] local_C_V_5_addr_reg_2018_pp0_iter2_reg; -reg [12:0] local_C_V_5_addr_reg_2018_pp0_iter3_reg; -reg [12:0] local_C_V_5_addr_reg_2018_pp0_iter4_reg; -reg [12:0] local_C_V_5_addr_reg_2018_pp0_iter5_reg; -reg [12:0] local_C_V_5_addr_reg_2018_pp0_iter6_reg; -reg [12:0] local_C_V_5_addr_reg_2018_pp0_iter7_reg; -reg [12:0] local_C_V_5_addr_reg_2018_pp0_iter8_reg; -reg [12:0] local_C_V_5_addr_reg_2018_pp0_iter9_reg; -reg [12:0] local_C_V_6_addr_reg_2024; -reg [12:0] local_C_V_6_addr_reg_2024_pp0_iter2_reg; -reg [12:0] local_C_V_6_addr_reg_2024_pp0_iter3_reg; -reg [12:0] local_C_V_6_addr_reg_2024_pp0_iter4_reg; -reg [12:0] local_C_V_6_addr_reg_2024_pp0_iter5_reg; -reg [12:0] local_C_V_6_addr_reg_2024_pp0_iter6_reg; -reg [12:0] local_C_V_6_addr_reg_2024_pp0_iter7_reg; -reg [12:0] local_C_V_6_addr_reg_2024_pp0_iter8_reg; -reg [12:0] local_C_V_6_addr_reg_2024_pp0_iter9_reg; -reg [12:0] local_C_V_7_addr_reg_2030; -reg [12:0] local_C_V_7_addr_reg_2030_pp0_iter2_reg; -reg [12:0] local_C_V_7_addr_reg_2030_pp0_iter3_reg; -reg [12:0] local_C_V_7_addr_reg_2030_pp0_iter4_reg; -reg [12:0] local_C_V_7_addr_reg_2030_pp0_iter5_reg; -reg [12:0] local_C_V_7_addr_reg_2030_pp0_iter6_reg; -reg [12:0] local_C_V_7_addr_reg_2030_pp0_iter7_reg; -reg [12:0] local_C_V_7_addr_reg_2030_pp0_iter8_reg; -reg [12:0] local_C_V_7_addr_reg_2030_pp0_iter9_reg; -reg [12:0] local_C_V_8_addr_reg_2036; -reg [12:0] local_C_V_8_addr_reg_2036_pp0_iter2_reg; -reg [12:0] local_C_V_8_addr_reg_2036_pp0_iter3_reg; -reg [12:0] local_C_V_8_addr_reg_2036_pp0_iter4_reg; -reg [12:0] local_C_V_8_addr_reg_2036_pp0_iter5_reg; -reg [12:0] local_C_V_8_addr_reg_2036_pp0_iter6_reg; -reg [12:0] local_C_V_8_addr_reg_2036_pp0_iter7_reg; -reg [12:0] local_C_V_8_addr_reg_2036_pp0_iter8_reg; -reg [12:0] local_C_V_8_addr_reg_2036_pp0_iter9_reg; -reg [12:0] local_C_V_9_addr_reg_2042; -reg [12:0] local_C_V_9_addr_reg_2042_pp0_iter2_reg; -reg [12:0] local_C_V_9_addr_reg_2042_pp0_iter3_reg; -reg [12:0] local_C_V_9_addr_reg_2042_pp0_iter4_reg; -reg [12:0] local_C_V_9_addr_reg_2042_pp0_iter5_reg; -reg [12:0] local_C_V_9_addr_reg_2042_pp0_iter6_reg; -reg [12:0] local_C_V_9_addr_reg_2042_pp0_iter7_reg; -reg [12:0] local_C_V_9_addr_reg_2042_pp0_iter8_reg; -reg [12:0] local_C_V_9_addr_reg_2042_pp0_iter9_reg; -reg [12:0] local_C_V_10_addr_reg_2048; -reg [12:0] local_C_V_10_addr_reg_2048_pp0_iter2_reg; -reg [12:0] local_C_V_10_addr_reg_2048_pp0_iter3_reg; -reg [12:0] local_C_V_10_addr_reg_2048_pp0_iter4_reg; -reg [12:0] local_C_V_10_addr_reg_2048_pp0_iter5_reg; -reg [12:0] local_C_V_10_addr_reg_2048_pp0_iter6_reg; -reg [12:0] local_C_V_10_addr_reg_2048_pp0_iter7_reg; -reg [12:0] local_C_V_10_addr_reg_2048_pp0_iter8_reg; -reg [12:0] local_C_V_10_addr_reg_2048_pp0_iter9_reg; -reg [12:0] local_C_V_11_addr_reg_2054; -reg [12:0] local_C_V_11_addr_reg_2054_pp0_iter2_reg; -reg [12:0] local_C_V_11_addr_reg_2054_pp0_iter3_reg; -reg [12:0] local_C_V_11_addr_reg_2054_pp0_iter4_reg; -reg [12:0] local_C_V_11_addr_reg_2054_pp0_iter5_reg; -reg [12:0] local_C_V_11_addr_reg_2054_pp0_iter6_reg; -reg [12:0] local_C_V_11_addr_reg_2054_pp0_iter7_reg; -reg [12:0] local_C_V_11_addr_reg_2054_pp0_iter8_reg; -reg [12:0] local_C_V_11_addr_reg_2054_pp0_iter9_reg; -reg [12:0] local_C_V_12_addr_reg_2060; -reg [12:0] local_C_V_12_addr_reg_2060_pp0_iter2_reg; -reg [12:0] local_C_V_12_addr_reg_2060_pp0_iter3_reg; -reg [12:0] local_C_V_12_addr_reg_2060_pp0_iter4_reg; -reg [12:0] local_C_V_12_addr_reg_2060_pp0_iter5_reg; -reg [12:0] local_C_V_12_addr_reg_2060_pp0_iter6_reg; -reg [12:0] local_C_V_12_addr_reg_2060_pp0_iter7_reg; -reg [12:0] local_C_V_12_addr_reg_2060_pp0_iter8_reg; -reg [12:0] local_C_V_12_addr_reg_2060_pp0_iter9_reg; -reg [12:0] local_C_V_13_addr_reg_2066; -reg [12:0] local_C_V_13_addr_reg_2066_pp0_iter2_reg; -reg [12:0] local_C_V_13_addr_reg_2066_pp0_iter3_reg; -reg [12:0] local_C_V_13_addr_reg_2066_pp0_iter4_reg; -reg [12:0] local_C_V_13_addr_reg_2066_pp0_iter5_reg; -reg [12:0] local_C_V_13_addr_reg_2066_pp0_iter6_reg; -reg [12:0] local_C_V_13_addr_reg_2066_pp0_iter7_reg; -reg [12:0] local_C_V_13_addr_reg_2066_pp0_iter8_reg; -reg [12:0] local_C_V_13_addr_reg_2066_pp0_iter9_reg; -reg [12:0] local_C_V_14_addr_reg_2072; -reg [12:0] local_C_V_14_addr_reg_2072_pp0_iter2_reg; -reg [12:0] local_C_V_14_addr_reg_2072_pp0_iter3_reg; -reg [12:0] local_C_V_14_addr_reg_2072_pp0_iter4_reg; -reg [12:0] local_C_V_14_addr_reg_2072_pp0_iter5_reg; -reg [12:0] local_C_V_14_addr_reg_2072_pp0_iter6_reg; -reg [12:0] local_C_V_14_addr_reg_2072_pp0_iter7_reg; -reg [12:0] local_C_V_14_addr_reg_2072_pp0_iter8_reg; -reg [12:0] local_C_V_14_addr_reg_2072_pp0_iter9_reg; -reg [12:0] local_C_V_15_addr_reg_2078; -reg [12:0] local_C_V_15_addr_reg_2078_pp0_iter2_reg; -reg [12:0] local_C_V_15_addr_reg_2078_pp0_iter3_reg; -reg [12:0] local_C_V_15_addr_reg_2078_pp0_iter4_reg; -reg [12:0] local_C_V_15_addr_reg_2078_pp0_iter5_reg; -reg [12:0] local_C_V_15_addr_reg_2078_pp0_iter6_reg; -reg [12:0] local_C_V_15_addr_reg_2078_pp0_iter7_reg; -reg [12:0] local_C_V_15_addr_reg_2078_pp0_iter8_reg; -reg [12:0] local_C_V_15_addr_reg_2078_pp0_iter9_reg; -wire [31:0] c_val_d0_u_V_fu_1185_p1; -reg [31:0] c_val_d0_u_V_reg_2084; -reg [31:0] c_val_d1_u_V_reg_2089; -wire [31:0] c_val_d0_u_V_1_fu_1199_p1; -reg [31:0] c_val_d0_u_V_1_reg_2094; -reg [31:0] c_val_d1_u_V_1_reg_2099; -wire [31:0] c_val_d0_u_V_2_fu_1213_p1; -reg [31:0] c_val_d0_u_V_2_reg_2104; -reg [31:0] c_val_d1_u_V_2_reg_2109; -wire [31:0] c_val_d0_u_V_3_fu_1227_p1; -reg [31:0] c_val_d0_u_V_3_reg_2114; -reg [31:0] c_val_d1_u_V_3_reg_2119; -wire [31:0] c_val_d0_u_V_4_fu_1241_p1; -reg [31:0] c_val_d0_u_V_4_reg_2124; -reg [31:0] c_val_d1_u_V_4_reg_2129; -wire [31:0] c_val_d0_u_V_5_fu_1255_p1; -reg [31:0] c_val_d0_u_V_5_reg_2134; -reg [31:0] c_val_d1_u_V_5_reg_2139; -wire [31:0] c_val_d0_u_V_6_fu_1269_p1; -reg [31:0] c_val_d0_u_V_6_reg_2144; -reg [31:0] c_val_d1_u_V_6_reg_2149; -wire [31:0] c_val_d0_u_V_7_fu_1283_p1; -reg [31:0] c_val_d0_u_V_7_reg_2154; -reg [31:0] c_val_d1_u_V_7_reg_2159; -wire [31:0] c_val_d0_u_V_8_fu_1297_p1; -reg [31:0] c_val_d0_u_V_8_reg_2164; -reg [31:0] c_val_d1_u_V_8_reg_2169; -wire [31:0] c_val_d0_u_V_9_fu_1311_p1; -reg [31:0] c_val_d0_u_V_9_reg_2174; -reg [31:0] c_val_d1_u_V_9_reg_2179; -wire [31:0] c_val_d0_u_V_10_fu_1325_p1; -reg [31:0] c_val_d0_u_V_10_reg_2184; -reg [31:0] c_val_d1_u_V_10_reg_2189; -wire [31:0] c_val_d0_u_V_11_fu_1339_p1; -reg [31:0] c_val_d0_u_V_11_reg_2194; -reg [31:0] c_val_d1_u_V_11_reg_2199; -wire [31:0] c_val_d0_u_V_12_fu_1353_p1; -reg [31:0] c_val_d0_u_V_12_reg_2204; -reg [31:0] c_val_d1_u_V_12_reg_2209; -wire [31:0] c_val_d0_u_V_13_fu_1367_p1; -reg [31:0] c_val_d0_u_V_13_reg_2214; -reg [31:0] c_val_d1_u_V_13_reg_2219; -wire [31:0] c_val_d0_u_V_14_fu_1381_p1; -reg [31:0] c_val_d0_u_V_14_reg_2224; -reg [31:0] c_val_d1_u_V_14_reg_2229; -wire [31:0] c_val_d0_u_V_15_fu_1395_p1; -reg [31:0] c_val_d0_u_V_15_reg_2234; -reg [31:0] c_val_d1_u_V_15_reg_2239; -wire [31:0] grp_fu_474_p2; -reg [31:0] c_val_d0_f_reg_2404; -wire [31:0] grp_fu_478_p2; -reg [31:0] c_val_d1_f_reg_2409; -wire [31:0] grp_fu_482_p2; -reg [31:0] c_val_d0_f_1_reg_2414; -wire [31:0] grp_fu_486_p2; -reg [31:0] c_val_d1_f_1_reg_2419; -wire [31:0] grp_fu_490_p2; -reg [31:0] c_val_d0_f_2_reg_2424; -wire [31:0] grp_fu_494_p2; -reg [31:0] c_val_d1_f_2_reg_2429; -wire [31:0] grp_fu_498_p2; -reg [31:0] c_val_d0_f_3_reg_2434; -wire [31:0] grp_fu_502_p2; -reg [31:0] c_val_d1_f_3_reg_2439; -wire [31:0] grp_fu_506_p2; -reg [31:0] c_val_d0_f_4_reg_2444; -wire [31:0] grp_fu_510_p2; -reg [31:0] c_val_d1_f_4_reg_2449; -wire [31:0] grp_fu_514_p2; -reg [31:0] c_val_d0_f_5_reg_2454; -wire [31:0] grp_fu_518_p2; -reg [31:0] c_val_d1_f_5_reg_2459; -wire [31:0] grp_fu_522_p2; -reg [31:0] c_val_d0_f_6_reg_2464; -wire [31:0] grp_fu_526_p2; -reg [31:0] c_val_d1_f_6_reg_2469; -wire [31:0] grp_fu_530_p2; -reg [31:0] c_val_d0_f_7_reg_2474; -wire [31:0] grp_fu_534_p2; -reg [31:0] c_val_d1_f_7_reg_2479; -wire [31:0] grp_fu_538_p2; -reg [31:0] c_val_d0_f_8_reg_2484; -wire [31:0] grp_fu_542_p2; -reg [31:0] c_val_d1_f_8_reg_2489; -wire [31:0] grp_fu_546_p2; -reg [31:0] c_val_d0_f_9_reg_2494; -wire [31:0] grp_fu_550_p2; -reg [31:0] c_val_d1_f_9_reg_2499; -wire [31:0] grp_fu_554_p2; -reg [31:0] c_val_d0_f_10_reg_2504; -wire [31:0] grp_fu_558_p2; -reg [31:0] c_val_d1_f_10_reg_2509; -wire [31:0] grp_fu_562_p2; -reg [31:0] c_val_d0_f_11_reg_2514; -wire [31:0] grp_fu_566_p2; -reg [31:0] c_val_d1_f_11_reg_2519; -wire [31:0] grp_fu_570_p2; -reg [31:0] c_val_d0_f_12_reg_2524; -wire [31:0] grp_fu_574_p2; -reg [31:0] c_val_d1_f_12_reg_2529; -wire [31:0] grp_fu_578_p2; -reg [31:0] c_val_d0_f_13_reg_2534; -wire [31:0] grp_fu_582_p2; -reg [31:0] c_val_d1_f_13_reg_2539; -wire [31:0] grp_fu_586_p2; -reg [31:0] c_val_d0_f_14_reg_2544; -wire [31:0] grp_fu_590_p2; -reg [31:0] c_val_d1_f_14_reg_2549; -wire [31:0] grp_fu_594_p2; -reg [31:0] c_val_d0_f_15_reg_2554; -wire [31:0] grp_fu_598_p2; -reg [31:0] c_val_d1_f_15_reg_2559; -wire [63:0] conv_i_i_i_fu_1157_p1; -wire ap_block_pp0_stage0; -wire [63:0] conv_i_i_i_1_fu_1164_p1; -wire [63:0] conv_i_i_i_2_fu_1171_p1; -wire [63:0] conv_i_i_i_3_fu_1178_p1; -reg [31:0] j_fu_130; -wire [31:0] j_2_fu_1146_p2; -wire ap_loop_init; -reg [31:0] ap_sig_allocacmp_j_1; -wire [0:0] tmp_nbreadreq_fu_146_p3; -wire [0:0] tmp_1_nbreadreq_fu_154_p3; -wire [0:0] tmp_2_nbreadreq_fu_162_p3; -wire [0:0] tmp_3_nbreadreq_fu_170_p3; -wire [31:0] grp_fu_474_p0; -wire [31:0] grp_fu_478_p0; -wire [31:0] grp_fu_482_p0; -wire [31:0] grp_fu_486_p0; -wire [31:0] grp_fu_490_p0; -wire [31:0] grp_fu_494_p0; -wire [31:0] grp_fu_498_p0; -wire [31:0] grp_fu_502_p0; -wire [31:0] grp_fu_506_p0; -wire [31:0] grp_fu_510_p0; -wire [31:0] grp_fu_514_p0; -wire [31:0] grp_fu_518_p0; -wire [31:0] grp_fu_522_p0; -wire [31:0] grp_fu_526_p0; -wire [31:0] grp_fu_530_p0; -wire [31:0] grp_fu_534_p0; -wire [31:0] grp_fu_538_p0; -wire [31:0] grp_fu_542_p0; -wire [31:0] grp_fu_546_p0; -wire [31:0] grp_fu_550_p0; -wire [31:0] grp_fu_554_p0; -wire [31:0] grp_fu_558_p0; -wire [31:0] grp_fu_562_p0; -wire [31:0] grp_fu_566_p0; -wire [31:0] grp_fu_570_p0; -wire [31:0] grp_fu_574_p0; -wire [31:0] grp_fu_578_p0; -wire [31:0] grp_fu_582_p0; -wire [31:0] grp_fu_586_p0; -wire [31:0] grp_fu_590_p0; -wire [31:0] grp_fu_594_p0; -wire [31:0] grp_fu_598_p0; -wire [0:0] and_ln260_1_fu_616_p2; -wire [0:0] and_ln260_fu_622_p2; -wire [31:0] trunc_ln2_fu_642_p4; -wire [31:0] trunc_ln78_1_fu_652_p4; -wire [31:0] trunc_ln78_2_fu_662_p4; -wire [31:0] trunc_ln78_3_fu_672_p4; -wire [31:0] trunc_ln78_4_fu_682_p4; -wire [31:0] trunc_ln78_5_fu_692_p4; -wire [31:0] trunc_ln78_6_fu_702_p4; -wire [31:0] trunc_ln78_7_fu_712_p4; -wire [31:0] trunc_ln78_8_fu_770_p4; -wire [31:0] trunc_ln78_9_fu_780_p4; -wire [31:0] trunc_ln78_s_fu_790_p4; -wire [31:0] trunc_ln78_10_fu_800_p4; -wire [31:0] trunc_ln78_11_fu_810_p4; -wire [31:0] trunc_ln78_12_fu_820_p4; -wire [31:0] trunc_ln78_13_fu_830_p4; -wire [31:0] trunc_ln78_14_fu_840_p4; -wire [31:0] trunc_ln78_15_fu_898_p4; -wire [31:0] trunc_ln78_16_fu_908_p4; -wire [31:0] trunc_ln78_17_fu_918_p4; -wire [31:0] trunc_ln78_18_fu_928_p4; -wire [31:0] trunc_ln78_19_fu_938_p4; -wire [31:0] trunc_ln78_20_fu_948_p4; -wire [31:0] trunc_ln78_21_fu_958_p4; -wire [31:0] trunc_ln78_22_fu_968_p4; -wire [31:0] trunc_ln78_23_fu_1026_p4; -wire [31:0] trunc_ln78_24_fu_1036_p4; -wire [31:0] trunc_ln78_25_fu_1046_p4; -wire [31:0] trunc_ln78_26_fu_1056_p4; -wire [31:0] trunc_ln78_27_fu_1066_p4; -wire [31:0] trunc_ln78_28_fu_1076_p4; -wire [31:0] trunc_ln78_29_fu_1086_p4; -wire [31:0] trunc_ln78_30_fu_1096_p4; -wire [31:0] empty_60_fu_1540_p1; -wire [31:0] empty_59_fu_1537_p1; -wire [31:0] empty_64_fu_1555_p1; -wire [31:0] empty_63_fu_1552_p1; -wire [31:0] empty_68_fu_1570_p1; -wire [31:0] empty_67_fu_1567_p1; -wire [31:0] empty_72_fu_1585_p1; -wire [31:0] empty_71_fu_1582_p1; -wire [31:0] empty_76_fu_1600_p1; -wire [31:0] empty_75_fu_1597_p1; -wire [31:0] empty_80_fu_1615_p1; -wire [31:0] empty_79_fu_1612_p1; -wire [31:0] empty_84_fu_1630_p1; -wire [31:0] empty_83_fu_1627_p1; -wire [31:0] empty_88_fu_1645_p1; -wire [31:0] empty_87_fu_1642_p1; -wire [31:0] empty_92_fu_1660_p1; -wire [31:0] empty_91_fu_1657_p1; -wire [31:0] empty_96_fu_1675_p1; -wire [31:0] empty_95_fu_1672_p1; -wire [31:0] empty_100_fu_1690_p1; -wire [31:0] empty_99_fu_1687_p1; -wire [31:0] empty_104_fu_1705_p1; -wire [31:0] empty_103_fu_1702_p1; -wire [31:0] empty_108_fu_1720_p1; -wire [31:0] empty_107_fu_1717_p1; -wire [31:0] empty_112_fu_1735_p1; -wire [31:0] empty_111_fu_1732_p1; -wire [31:0] empty_116_fu_1750_p1; -wire [31:0] empty_115_fu_1747_p1; -wire [31:0] empty_120_fu_1765_p1; -wire [31:0] empty_119_fu_1762_p1; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg ap_loop_exit_ready_pp0_iter1_reg; -reg ap_loop_exit_ready_pp0_iter2_reg; -reg ap_loop_exit_ready_pp0_iter3_reg; -reg ap_loop_exit_ready_pp0_iter4_reg; -reg ap_loop_exit_ready_pp0_iter5_reg; -reg ap_loop_exit_ready_pp0_iter6_reg; -reg ap_loop_exit_ready_pp0_iter7_reg; -reg ap_loop_exit_ready_pp0_iter8_reg; -reg ap_loop_exit_ready_pp0_iter9_reg; -reg [0:0] ap_NS_fsm; -reg ap_block_pp0; -reg ap_predicate_op143_load_state2; -reg ap_enable_operation_143; -reg ap_enable_state2_pp0_iter1_stage0; -reg ap_predicate_op177_load_state3; -reg ap_enable_operation_177; -reg ap_enable_state3_pp0_iter2_stage0; -reg ap_predicate_op484_store_state11; -reg ap_enable_operation_484; -reg ap_enable_state11_pp0_iter10_stage0; -reg ap_predicate_op145_load_state2; -reg ap_enable_operation_145; -reg ap_predicate_op180_load_state3; -reg ap_enable_operation_180; -reg ap_predicate_op488_store_state11; -reg ap_enable_operation_488; -reg ap_predicate_op147_load_state2; -reg ap_enable_operation_147; -reg ap_predicate_op183_load_state3; -reg ap_enable_operation_183; -reg ap_predicate_op492_store_state11; -reg ap_enable_operation_492; -reg ap_predicate_op149_load_state2; -reg ap_enable_operation_149; -reg ap_predicate_op186_load_state3; -reg ap_enable_operation_186; -reg ap_predicate_op496_store_state11; -reg ap_enable_operation_496; -reg ap_predicate_op152_load_state2; -reg ap_enable_operation_152; -reg ap_predicate_op189_load_state3; -reg ap_enable_operation_189; -reg ap_predicate_op501_store_state11; -reg ap_enable_operation_501; -reg ap_predicate_op154_load_state2; -reg ap_enable_operation_154; -reg ap_predicate_op192_load_state3; -reg ap_enable_operation_192; -reg ap_predicate_op505_store_state11; -reg ap_enable_operation_505; -reg ap_predicate_op156_load_state2; -reg ap_enable_operation_156; -reg ap_predicate_op195_load_state3; -reg ap_enable_operation_195; -reg ap_predicate_op509_store_state11; -reg ap_enable_operation_509; -reg ap_predicate_op158_load_state2; -reg ap_enable_operation_158; -reg ap_predicate_op198_load_state3; -reg ap_enable_operation_198; -reg ap_predicate_op513_store_state11; -reg ap_enable_operation_513; -reg ap_predicate_op161_load_state2; -reg ap_enable_operation_161; -reg ap_predicate_op201_load_state3; -reg ap_enable_operation_201; -reg ap_predicate_op518_store_state11; -reg ap_enable_operation_518; -reg ap_predicate_op163_load_state2; -reg ap_enable_operation_163; -reg ap_predicate_op204_load_state3; -reg ap_enable_operation_204; -reg ap_predicate_op522_store_state11; -reg ap_enable_operation_522; -reg ap_predicate_op165_load_state2; -reg ap_enable_operation_165; -reg ap_predicate_op207_load_state3; -reg ap_enable_operation_207; -reg ap_predicate_op526_store_state11; -reg ap_enable_operation_526; -reg ap_predicate_op167_load_state2; -reg ap_enable_operation_167; -reg ap_predicate_op210_load_state3; -reg ap_enable_operation_210; -reg ap_predicate_op530_store_state11; -reg ap_enable_operation_530; -reg ap_predicate_op170_load_state2; -reg ap_enable_operation_170; -reg ap_predicate_op213_load_state3; -reg ap_enable_operation_213; -reg ap_predicate_op535_store_state11; -reg ap_enable_operation_535; -reg ap_predicate_op172_load_state2; -reg ap_enable_operation_172; -reg ap_predicate_op216_load_state3; -reg ap_enable_operation_216; -reg ap_predicate_op539_store_state11; -reg ap_enable_operation_539; -reg ap_predicate_op174_load_state2; -reg ap_enable_operation_174; -reg ap_predicate_op219_load_state3; -reg ap_enable_operation_219; -reg ap_predicate_op543_store_state11; -reg ap_enable_operation_543; -reg ap_predicate_op176_load_state2; -reg ap_enable_operation_176; -reg ap_predicate_op222_load_state3; -reg ap_enable_operation_222; -reg ap_predicate_op547_store_state11; -reg ap_enable_operation_547; -wire ap_enable_pp0; -wire ap_start_int; -reg ap_condition_2344; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_enable_reg_pp0_iter2 = 1'b0; -#0 ap_enable_reg_pp0_iter3 = 1'b0; -#0 ap_enable_reg_pp0_iter4 = 1'b0; -#0 ap_enable_reg_pp0_iter5 = 1'b0; -#0 ap_enable_reg_pp0_iter6 = 1'b0; -#0 ap_enable_reg_pp0_iter7 = 1'b0; -#0 ap_enable_reg_pp0_iter8 = 1'b0; -#0 ap_enable_reg_pp0_iter9 = 1'b0; -#0 ap_enable_reg_pp0_iter10 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U18( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_474_p0), - .din1(elem_val_abvec_M_elems_reg_1797_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_474_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U19( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_478_p0), - .din1(elem_val_abvec_M_elems_1_reg_1802_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_478_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U20( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_482_p0), - .din1(bitcast_ln78_reg_1807_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_482_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U21( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_486_p0), - .din1(bitcast_ln78_1_reg_1812_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_486_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U22( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_490_p0), - .din1(bitcast_ln78_2_reg_1817_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_490_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U23( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_494_p0), - .din1(bitcast_ln78_3_reg_1822_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_494_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U24( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_498_p0), - .din1(bitcast_ln78_4_reg_1827_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_498_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U25( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_502_p0), - .din1(bitcast_ln78_5_reg_1832_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_502_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U26( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_506_p0), - .din1(elem_val_abvec_M_elems_2_reg_1846_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_506_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U27( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_510_p0), - .din1(elem_val_abvec_M_elems_3_reg_1851_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_510_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U28( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_514_p0), - .din1(bitcast_ln78_8_reg_1856_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_514_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U29( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_518_p0), - .din1(bitcast_ln78_9_reg_1861_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_518_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U30( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_522_p0), - .din1(bitcast_ln78_10_reg_1866_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_522_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U31( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_526_p0), - .din1(bitcast_ln78_11_reg_1871_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_526_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U32( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_530_p0), - .din1(bitcast_ln78_12_reg_1876_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_530_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U33( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_534_p0), - .din1(bitcast_ln78_13_reg_1881_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_534_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U34( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_538_p0), - .din1(elem_val_abvec_M_elems_4_reg_1895_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_538_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U35( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_542_p0), - .din1(elem_val_abvec_M_elems_5_reg_1900_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_542_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U36( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_546_p0), - .din1(bitcast_ln78_16_reg_1905_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_546_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U37( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_550_p0), - .din1(bitcast_ln78_17_reg_1910_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_550_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U38( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_554_p0), - .din1(bitcast_ln78_18_reg_1915_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_554_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U39( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_558_p0), - .din1(bitcast_ln78_19_reg_1920_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_558_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U40( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_562_p0), - .din1(bitcast_ln78_20_reg_1925_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_562_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U41( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_566_p0), - .din1(bitcast_ln78_21_reg_1930_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_566_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U42( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_570_p0), - .din1(elem_val_abvec_M_elems_6_reg_1944_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_570_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U43( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_574_p0), - .din1(elem_val_abvec_M_elems_7_reg_1949_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_574_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U44( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_578_p0), - .din1(bitcast_ln78_24_reg_1954_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_578_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U45( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_582_p0), - .din1(bitcast_ln78_25_reg_1959_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_582_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U46( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_586_p0), - .din1(bitcast_ln78_26_reg_1964_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_586_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U47( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_590_p0), - .din1(bitcast_ln78_27_reg_1969_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_590_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U48( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_594_p0), - .din1(bitcast_ln78_28_reg_1974_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_594_p2) -); - -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_1_U49( - .clk(ap_clk), - .reset(ap_rst), - .din0(grp_fu_598_p0), - .din1(bitcast_ln78_29_reg_1979_pp0_iter2_reg), - .ce(1'b1), - .dout(grp_fu_598_p2) -); - -PEG_Cmtx_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter9_reg == 1'b1))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter10 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter2 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter3 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter4 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter5 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter6 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter7 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter8 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter9 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((1'b1 == ap_condition_2344)) begin - j_fu_130 <= j_2_fu_1146_p2; - end else if ((ap_loop_init == 1'b1)) begin - j_fu_130 <= start_32_3; - end - end -end - -always @ (posedge ap_clk) begin - if (((icmp_ln254_fu_610_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - and_ln260_2_reg_1788 <= and_ln260_2_fu_628_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - and_ln260_2_reg_1788_pp0_iter1_reg <= and_ln260_2_reg_1788; - ap_loop_exit_ready_pp0_iter1_reg <= ap_loop_exit_ready; - ap_loop_exit_ready_pp0_iter2_reg <= ap_loop_exit_ready_pp0_iter1_reg; - bitcast_ln78_10_reg_1866_pp0_iter1_reg <= bitcast_ln78_10_reg_1866; - bitcast_ln78_11_reg_1871_pp0_iter1_reg <= bitcast_ln78_11_reg_1871; - bitcast_ln78_12_reg_1876_pp0_iter1_reg <= bitcast_ln78_12_reg_1876; - bitcast_ln78_13_reg_1881_pp0_iter1_reg <= bitcast_ln78_13_reg_1881; - bitcast_ln78_16_reg_1905_pp0_iter1_reg <= bitcast_ln78_16_reg_1905; - bitcast_ln78_17_reg_1910_pp0_iter1_reg <= bitcast_ln78_17_reg_1910; - bitcast_ln78_18_reg_1915_pp0_iter1_reg <= bitcast_ln78_18_reg_1915; - bitcast_ln78_19_reg_1920_pp0_iter1_reg <= bitcast_ln78_19_reg_1920; - bitcast_ln78_1_reg_1812_pp0_iter1_reg <= bitcast_ln78_1_reg_1812; - bitcast_ln78_20_reg_1925_pp0_iter1_reg <= bitcast_ln78_20_reg_1925; - bitcast_ln78_21_reg_1930_pp0_iter1_reg <= bitcast_ln78_21_reg_1930; - bitcast_ln78_24_reg_1954_pp0_iter1_reg <= bitcast_ln78_24_reg_1954; - bitcast_ln78_25_reg_1959_pp0_iter1_reg <= bitcast_ln78_25_reg_1959; - bitcast_ln78_26_reg_1964_pp0_iter1_reg <= bitcast_ln78_26_reg_1964; - bitcast_ln78_27_reg_1969_pp0_iter1_reg <= bitcast_ln78_27_reg_1969; - bitcast_ln78_28_reg_1974_pp0_iter1_reg <= bitcast_ln78_28_reg_1974; - bitcast_ln78_29_reg_1979_pp0_iter1_reg <= bitcast_ln78_29_reg_1979; - bitcast_ln78_2_reg_1817_pp0_iter1_reg <= bitcast_ln78_2_reg_1817; - bitcast_ln78_3_reg_1822_pp0_iter1_reg <= bitcast_ln78_3_reg_1822; - bitcast_ln78_4_reg_1827_pp0_iter1_reg <= bitcast_ln78_4_reg_1827; - bitcast_ln78_5_reg_1832_pp0_iter1_reg <= bitcast_ln78_5_reg_1832; - bitcast_ln78_8_reg_1856_pp0_iter1_reg <= bitcast_ln78_8_reg_1856; - bitcast_ln78_9_reg_1861_pp0_iter1_reg <= bitcast_ln78_9_reg_1861; - bitcast_ln78_reg_1807_pp0_iter1_reg <= bitcast_ln78_reg_1807; - elem_val_abvec_M_elems_1_reg_1802_pp0_iter1_reg <= elem_val_abvec_M_elems_1_reg_1802; - elem_val_abvec_M_elems_2_reg_1846_pp0_iter1_reg <= elem_val_abvec_M_elems_2_reg_1846; - elem_val_abvec_M_elems_3_reg_1851_pp0_iter1_reg <= elem_val_abvec_M_elems_3_reg_1851; - elem_val_abvec_M_elems_4_reg_1895_pp0_iter1_reg <= elem_val_abvec_M_elems_4_reg_1895; - elem_val_abvec_M_elems_5_reg_1900_pp0_iter1_reg <= elem_val_abvec_M_elems_5_reg_1900; - elem_val_abvec_M_elems_6_reg_1944_pp0_iter1_reg <= elem_val_abvec_M_elems_6_reg_1944; - elem_val_abvec_M_elems_7_reg_1949_pp0_iter1_reg <= elem_val_abvec_M_elems_7_reg_1949; - elem_val_abvec_M_elems_reg_1797_pp0_iter1_reg <= elem_val_abvec_M_elems_reg_1797; - p_Result_10_reg_1935_pp0_iter1_reg <= p_Result_10_reg_1935; - p_Result_15_reg_1984_pp0_iter1_reg <= p_Result_15_reg_1984; - p_Result_5_reg_1886_pp0_iter1_reg <= p_Result_5_reg_1886; - p_Result_s_reg_1837_pp0_iter1_reg <= p_Result_s_reg_1837; - end -end - -always @ (posedge ap_clk) begin - if ((1'b0 == ap_block_pp0_stage0_11001)) begin - and_ln260_2_reg_1788_pp0_iter2_reg <= and_ln260_2_reg_1788_pp0_iter1_reg; - and_ln260_2_reg_1788_pp0_iter3_reg <= and_ln260_2_reg_1788_pp0_iter2_reg; - and_ln260_2_reg_1788_pp0_iter4_reg <= and_ln260_2_reg_1788_pp0_iter3_reg; - and_ln260_2_reg_1788_pp0_iter5_reg <= and_ln260_2_reg_1788_pp0_iter4_reg; - and_ln260_2_reg_1788_pp0_iter6_reg <= and_ln260_2_reg_1788_pp0_iter5_reg; - and_ln260_2_reg_1788_pp0_iter7_reg <= and_ln260_2_reg_1788_pp0_iter6_reg; - and_ln260_2_reg_1788_pp0_iter8_reg <= and_ln260_2_reg_1788_pp0_iter7_reg; - and_ln260_2_reg_1788_pp0_iter9_reg <= and_ln260_2_reg_1788_pp0_iter8_reg; - ap_loop_exit_ready_pp0_iter3_reg <= ap_loop_exit_ready_pp0_iter2_reg; - ap_loop_exit_ready_pp0_iter4_reg <= ap_loop_exit_ready_pp0_iter3_reg; - ap_loop_exit_ready_pp0_iter5_reg <= ap_loop_exit_ready_pp0_iter4_reg; - ap_loop_exit_ready_pp0_iter6_reg <= ap_loop_exit_ready_pp0_iter5_reg; - ap_loop_exit_ready_pp0_iter7_reg <= ap_loop_exit_ready_pp0_iter6_reg; - ap_loop_exit_ready_pp0_iter8_reg <= ap_loop_exit_ready_pp0_iter7_reg; - ap_loop_exit_ready_pp0_iter9_reg <= ap_loop_exit_ready_pp0_iter8_reg; - bitcast_ln78_10_reg_1866_pp0_iter2_reg <= bitcast_ln78_10_reg_1866_pp0_iter1_reg; - bitcast_ln78_11_reg_1871_pp0_iter2_reg <= bitcast_ln78_11_reg_1871_pp0_iter1_reg; - bitcast_ln78_12_reg_1876_pp0_iter2_reg <= bitcast_ln78_12_reg_1876_pp0_iter1_reg; - bitcast_ln78_13_reg_1881_pp0_iter2_reg <= bitcast_ln78_13_reg_1881_pp0_iter1_reg; - bitcast_ln78_16_reg_1905_pp0_iter2_reg <= bitcast_ln78_16_reg_1905_pp0_iter1_reg; - bitcast_ln78_17_reg_1910_pp0_iter2_reg <= bitcast_ln78_17_reg_1910_pp0_iter1_reg; - bitcast_ln78_18_reg_1915_pp0_iter2_reg <= bitcast_ln78_18_reg_1915_pp0_iter1_reg; - bitcast_ln78_19_reg_1920_pp0_iter2_reg <= bitcast_ln78_19_reg_1920_pp0_iter1_reg; - bitcast_ln78_1_reg_1812_pp0_iter2_reg <= bitcast_ln78_1_reg_1812_pp0_iter1_reg; - bitcast_ln78_20_reg_1925_pp0_iter2_reg <= bitcast_ln78_20_reg_1925_pp0_iter1_reg; - bitcast_ln78_21_reg_1930_pp0_iter2_reg <= bitcast_ln78_21_reg_1930_pp0_iter1_reg; - bitcast_ln78_24_reg_1954_pp0_iter2_reg <= bitcast_ln78_24_reg_1954_pp0_iter1_reg; - bitcast_ln78_25_reg_1959_pp0_iter2_reg <= bitcast_ln78_25_reg_1959_pp0_iter1_reg; - bitcast_ln78_26_reg_1964_pp0_iter2_reg <= bitcast_ln78_26_reg_1964_pp0_iter1_reg; - bitcast_ln78_27_reg_1969_pp0_iter2_reg <= bitcast_ln78_27_reg_1969_pp0_iter1_reg; - bitcast_ln78_28_reg_1974_pp0_iter2_reg <= bitcast_ln78_28_reg_1974_pp0_iter1_reg; - bitcast_ln78_29_reg_1979_pp0_iter2_reg <= bitcast_ln78_29_reg_1979_pp0_iter1_reg; - bitcast_ln78_2_reg_1817_pp0_iter2_reg <= bitcast_ln78_2_reg_1817_pp0_iter1_reg; - bitcast_ln78_3_reg_1822_pp0_iter2_reg <= bitcast_ln78_3_reg_1822_pp0_iter1_reg; - bitcast_ln78_4_reg_1827_pp0_iter2_reg <= bitcast_ln78_4_reg_1827_pp0_iter1_reg; - bitcast_ln78_5_reg_1832_pp0_iter2_reg <= bitcast_ln78_5_reg_1832_pp0_iter1_reg; - bitcast_ln78_8_reg_1856_pp0_iter2_reg <= bitcast_ln78_8_reg_1856_pp0_iter1_reg; - bitcast_ln78_9_reg_1861_pp0_iter2_reg <= bitcast_ln78_9_reg_1861_pp0_iter1_reg; - bitcast_ln78_reg_1807_pp0_iter2_reg <= bitcast_ln78_reg_1807_pp0_iter1_reg; - elem_val_abvec_M_elems_1_reg_1802_pp0_iter2_reg <= elem_val_abvec_M_elems_1_reg_1802_pp0_iter1_reg; - elem_val_abvec_M_elems_2_reg_1846_pp0_iter2_reg <= elem_val_abvec_M_elems_2_reg_1846_pp0_iter1_reg; - elem_val_abvec_M_elems_3_reg_1851_pp0_iter2_reg <= elem_val_abvec_M_elems_3_reg_1851_pp0_iter1_reg; - elem_val_abvec_M_elems_4_reg_1895_pp0_iter2_reg <= elem_val_abvec_M_elems_4_reg_1895_pp0_iter1_reg; - elem_val_abvec_M_elems_5_reg_1900_pp0_iter2_reg <= elem_val_abvec_M_elems_5_reg_1900_pp0_iter1_reg; - elem_val_abvec_M_elems_6_reg_1944_pp0_iter2_reg <= elem_val_abvec_M_elems_6_reg_1944_pp0_iter1_reg; - elem_val_abvec_M_elems_7_reg_1949_pp0_iter2_reg <= elem_val_abvec_M_elems_7_reg_1949_pp0_iter1_reg; - elem_val_abvec_M_elems_reg_1797_pp0_iter2_reg <= elem_val_abvec_M_elems_reg_1797_pp0_iter1_reg; - local_C_V_10_addr_reg_2048_pp0_iter2_reg <= local_C_V_10_addr_reg_2048; - local_C_V_10_addr_reg_2048_pp0_iter3_reg <= local_C_V_10_addr_reg_2048_pp0_iter2_reg; - local_C_V_10_addr_reg_2048_pp0_iter4_reg <= local_C_V_10_addr_reg_2048_pp0_iter3_reg; - local_C_V_10_addr_reg_2048_pp0_iter5_reg <= local_C_V_10_addr_reg_2048_pp0_iter4_reg; - local_C_V_10_addr_reg_2048_pp0_iter6_reg <= local_C_V_10_addr_reg_2048_pp0_iter5_reg; - local_C_V_10_addr_reg_2048_pp0_iter7_reg <= local_C_V_10_addr_reg_2048_pp0_iter6_reg; - local_C_V_10_addr_reg_2048_pp0_iter8_reg <= local_C_V_10_addr_reg_2048_pp0_iter7_reg; - local_C_V_10_addr_reg_2048_pp0_iter9_reg <= local_C_V_10_addr_reg_2048_pp0_iter8_reg; - local_C_V_11_addr_reg_2054_pp0_iter2_reg <= local_C_V_11_addr_reg_2054; - local_C_V_11_addr_reg_2054_pp0_iter3_reg <= local_C_V_11_addr_reg_2054_pp0_iter2_reg; - local_C_V_11_addr_reg_2054_pp0_iter4_reg <= local_C_V_11_addr_reg_2054_pp0_iter3_reg; - local_C_V_11_addr_reg_2054_pp0_iter5_reg <= local_C_V_11_addr_reg_2054_pp0_iter4_reg; - local_C_V_11_addr_reg_2054_pp0_iter6_reg <= local_C_V_11_addr_reg_2054_pp0_iter5_reg; - local_C_V_11_addr_reg_2054_pp0_iter7_reg <= local_C_V_11_addr_reg_2054_pp0_iter6_reg; - local_C_V_11_addr_reg_2054_pp0_iter8_reg <= local_C_V_11_addr_reg_2054_pp0_iter7_reg; - local_C_V_11_addr_reg_2054_pp0_iter9_reg <= local_C_V_11_addr_reg_2054_pp0_iter8_reg; - local_C_V_12_addr_reg_2060_pp0_iter2_reg <= local_C_V_12_addr_reg_2060; - local_C_V_12_addr_reg_2060_pp0_iter3_reg <= local_C_V_12_addr_reg_2060_pp0_iter2_reg; - local_C_V_12_addr_reg_2060_pp0_iter4_reg <= local_C_V_12_addr_reg_2060_pp0_iter3_reg; - local_C_V_12_addr_reg_2060_pp0_iter5_reg <= local_C_V_12_addr_reg_2060_pp0_iter4_reg; - local_C_V_12_addr_reg_2060_pp0_iter6_reg <= local_C_V_12_addr_reg_2060_pp0_iter5_reg; - local_C_V_12_addr_reg_2060_pp0_iter7_reg <= local_C_V_12_addr_reg_2060_pp0_iter6_reg; - local_C_V_12_addr_reg_2060_pp0_iter8_reg <= local_C_V_12_addr_reg_2060_pp0_iter7_reg; - local_C_V_12_addr_reg_2060_pp0_iter9_reg <= local_C_V_12_addr_reg_2060_pp0_iter8_reg; - local_C_V_13_addr_reg_2066_pp0_iter2_reg <= local_C_V_13_addr_reg_2066; - local_C_V_13_addr_reg_2066_pp0_iter3_reg <= local_C_V_13_addr_reg_2066_pp0_iter2_reg; - local_C_V_13_addr_reg_2066_pp0_iter4_reg <= local_C_V_13_addr_reg_2066_pp0_iter3_reg; - local_C_V_13_addr_reg_2066_pp0_iter5_reg <= local_C_V_13_addr_reg_2066_pp0_iter4_reg; - local_C_V_13_addr_reg_2066_pp0_iter6_reg <= local_C_V_13_addr_reg_2066_pp0_iter5_reg; - local_C_V_13_addr_reg_2066_pp0_iter7_reg <= local_C_V_13_addr_reg_2066_pp0_iter6_reg; - local_C_V_13_addr_reg_2066_pp0_iter8_reg <= local_C_V_13_addr_reg_2066_pp0_iter7_reg; - local_C_V_13_addr_reg_2066_pp0_iter9_reg <= local_C_V_13_addr_reg_2066_pp0_iter8_reg; - local_C_V_14_addr_reg_2072_pp0_iter2_reg <= local_C_V_14_addr_reg_2072; - local_C_V_14_addr_reg_2072_pp0_iter3_reg <= local_C_V_14_addr_reg_2072_pp0_iter2_reg; - local_C_V_14_addr_reg_2072_pp0_iter4_reg <= local_C_V_14_addr_reg_2072_pp0_iter3_reg; - local_C_V_14_addr_reg_2072_pp0_iter5_reg <= local_C_V_14_addr_reg_2072_pp0_iter4_reg; - local_C_V_14_addr_reg_2072_pp0_iter6_reg <= local_C_V_14_addr_reg_2072_pp0_iter5_reg; - local_C_V_14_addr_reg_2072_pp0_iter7_reg <= local_C_V_14_addr_reg_2072_pp0_iter6_reg; - local_C_V_14_addr_reg_2072_pp0_iter8_reg <= local_C_V_14_addr_reg_2072_pp0_iter7_reg; - local_C_V_14_addr_reg_2072_pp0_iter9_reg <= local_C_V_14_addr_reg_2072_pp0_iter8_reg; - local_C_V_15_addr_reg_2078_pp0_iter2_reg <= local_C_V_15_addr_reg_2078; - local_C_V_15_addr_reg_2078_pp0_iter3_reg <= local_C_V_15_addr_reg_2078_pp0_iter2_reg; - local_C_V_15_addr_reg_2078_pp0_iter4_reg <= local_C_V_15_addr_reg_2078_pp0_iter3_reg; - local_C_V_15_addr_reg_2078_pp0_iter5_reg <= local_C_V_15_addr_reg_2078_pp0_iter4_reg; - local_C_V_15_addr_reg_2078_pp0_iter6_reg <= local_C_V_15_addr_reg_2078_pp0_iter5_reg; - local_C_V_15_addr_reg_2078_pp0_iter7_reg <= local_C_V_15_addr_reg_2078_pp0_iter6_reg; - local_C_V_15_addr_reg_2078_pp0_iter8_reg <= local_C_V_15_addr_reg_2078_pp0_iter7_reg; - local_C_V_15_addr_reg_2078_pp0_iter9_reg <= local_C_V_15_addr_reg_2078_pp0_iter8_reg; - local_C_V_1_addr_reg_1994_pp0_iter2_reg <= local_C_V_1_addr_reg_1994; - local_C_V_1_addr_reg_1994_pp0_iter3_reg <= local_C_V_1_addr_reg_1994_pp0_iter2_reg; - local_C_V_1_addr_reg_1994_pp0_iter4_reg <= local_C_V_1_addr_reg_1994_pp0_iter3_reg; - local_C_V_1_addr_reg_1994_pp0_iter5_reg <= local_C_V_1_addr_reg_1994_pp0_iter4_reg; - local_C_V_1_addr_reg_1994_pp0_iter6_reg <= local_C_V_1_addr_reg_1994_pp0_iter5_reg; - local_C_V_1_addr_reg_1994_pp0_iter7_reg <= local_C_V_1_addr_reg_1994_pp0_iter6_reg; - local_C_V_1_addr_reg_1994_pp0_iter8_reg <= local_C_V_1_addr_reg_1994_pp0_iter7_reg; - local_C_V_1_addr_reg_1994_pp0_iter9_reg <= local_C_V_1_addr_reg_1994_pp0_iter8_reg; - local_C_V_2_addr_reg_2000_pp0_iter2_reg <= local_C_V_2_addr_reg_2000; - local_C_V_2_addr_reg_2000_pp0_iter3_reg <= local_C_V_2_addr_reg_2000_pp0_iter2_reg; - local_C_V_2_addr_reg_2000_pp0_iter4_reg <= local_C_V_2_addr_reg_2000_pp0_iter3_reg; - local_C_V_2_addr_reg_2000_pp0_iter5_reg <= local_C_V_2_addr_reg_2000_pp0_iter4_reg; - local_C_V_2_addr_reg_2000_pp0_iter6_reg <= local_C_V_2_addr_reg_2000_pp0_iter5_reg; - local_C_V_2_addr_reg_2000_pp0_iter7_reg <= local_C_V_2_addr_reg_2000_pp0_iter6_reg; - local_C_V_2_addr_reg_2000_pp0_iter8_reg <= local_C_V_2_addr_reg_2000_pp0_iter7_reg; - local_C_V_2_addr_reg_2000_pp0_iter9_reg <= local_C_V_2_addr_reg_2000_pp0_iter8_reg; - local_C_V_3_addr_reg_2006_pp0_iter2_reg <= local_C_V_3_addr_reg_2006; - local_C_V_3_addr_reg_2006_pp0_iter3_reg <= local_C_V_3_addr_reg_2006_pp0_iter2_reg; - local_C_V_3_addr_reg_2006_pp0_iter4_reg <= local_C_V_3_addr_reg_2006_pp0_iter3_reg; - local_C_V_3_addr_reg_2006_pp0_iter5_reg <= local_C_V_3_addr_reg_2006_pp0_iter4_reg; - local_C_V_3_addr_reg_2006_pp0_iter6_reg <= local_C_V_3_addr_reg_2006_pp0_iter5_reg; - local_C_V_3_addr_reg_2006_pp0_iter7_reg <= local_C_V_3_addr_reg_2006_pp0_iter6_reg; - local_C_V_3_addr_reg_2006_pp0_iter8_reg <= local_C_V_3_addr_reg_2006_pp0_iter7_reg; - local_C_V_3_addr_reg_2006_pp0_iter9_reg <= local_C_V_3_addr_reg_2006_pp0_iter8_reg; - local_C_V_4_addr_reg_2012_pp0_iter2_reg <= local_C_V_4_addr_reg_2012; - local_C_V_4_addr_reg_2012_pp0_iter3_reg <= local_C_V_4_addr_reg_2012_pp0_iter2_reg; - local_C_V_4_addr_reg_2012_pp0_iter4_reg <= local_C_V_4_addr_reg_2012_pp0_iter3_reg; - local_C_V_4_addr_reg_2012_pp0_iter5_reg <= local_C_V_4_addr_reg_2012_pp0_iter4_reg; - local_C_V_4_addr_reg_2012_pp0_iter6_reg <= local_C_V_4_addr_reg_2012_pp0_iter5_reg; - local_C_V_4_addr_reg_2012_pp0_iter7_reg <= local_C_V_4_addr_reg_2012_pp0_iter6_reg; - local_C_V_4_addr_reg_2012_pp0_iter8_reg <= local_C_V_4_addr_reg_2012_pp0_iter7_reg; - local_C_V_4_addr_reg_2012_pp0_iter9_reg <= local_C_V_4_addr_reg_2012_pp0_iter8_reg; - local_C_V_5_addr_reg_2018_pp0_iter2_reg <= local_C_V_5_addr_reg_2018; - local_C_V_5_addr_reg_2018_pp0_iter3_reg <= local_C_V_5_addr_reg_2018_pp0_iter2_reg; - local_C_V_5_addr_reg_2018_pp0_iter4_reg <= local_C_V_5_addr_reg_2018_pp0_iter3_reg; - local_C_V_5_addr_reg_2018_pp0_iter5_reg <= local_C_V_5_addr_reg_2018_pp0_iter4_reg; - local_C_V_5_addr_reg_2018_pp0_iter6_reg <= local_C_V_5_addr_reg_2018_pp0_iter5_reg; - local_C_V_5_addr_reg_2018_pp0_iter7_reg <= local_C_V_5_addr_reg_2018_pp0_iter6_reg; - local_C_V_5_addr_reg_2018_pp0_iter8_reg <= local_C_V_5_addr_reg_2018_pp0_iter7_reg; - local_C_V_5_addr_reg_2018_pp0_iter9_reg <= local_C_V_5_addr_reg_2018_pp0_iter8_reg; - local_C_V_6_addr_reg_2024_pp0_iter2_reg <= local_C_V_6_addr_reg_2024; - local_C_V_6_addr_reg_2024_pp0_iter3_reg <= local_C_V_6_addr_reg_2024_pp0_iter2_reg; - local_C_V_6_addr_reg_2024_pp0_iter4_reg <= local_C_V_6_addr_reg_2024_pp0_iter3_reg; - local_C_V_6_addr_reg_2024_pp0_iter5_reg <= local_C_V_6_addr_reg_2024_pp0_iter4_reg; - local_C_V_6_addr_reg_2024_pp0_iter6_reg <= local_C_V_6_addr_reg_2024_pp0_iter5_reg; - local_C_V_6_addr_reg_2024_pp0_iter7_reg <= local_C_V_6_addr_reg_2024_pp0_iter6_reg; - local_C_V_6_addr_reg_2024_pp0_iter8_reg <= local_C_V_6_addr_reg_2024_pp0_iter7_reg; - local_C_V_6_addr_reg_2024_pp0_iter9_reg <= local_C_V_6_addr_reg_2024_pp0_iter8_reg; - local_C_V_7_addr_reg_2030_pp0_iter2_reg <= local_C_V_7_addr_reg_2030; - local_C_V_7_addr_reg_2030_pp0_iter3_reg <= local_C_V_7_addr_reg_2030_pp0_iter2_reg; - local_C_V_7_addr_reg_2030_pp0_iter4_reg <= local_C_V_7_addr_reg_2030_pp0_iter3_reg; - local_C_V_7_addr_reg_2030_pp0_iter5_reg <= local_C_V_7_addr_reg_2030_pp0_iter4_reg; - local_C_V_7_addr_reg_2030_pp0_iter6_reg <= local_C_V_7_addr_reg_2030_pp0_iter5_reg; - local_C_V_7_addr_reg_2030_pp0_iter7_reg <= local_C_V_7_addr_reg_2030_pp0_iter6_reg; - local_C_V_7_addr_reg_2030_pp0_iter8_reg <= local_C_V_7_addr_reg_2030_pp0_iter7_reg; - local_C_V_7_addr_reg_2030_pp0_iter9_reg <= local_C_V_7_addr_reg_2030_pp0_iter8_reg; - local_C_V_8_addr_reg_2036_pp0_iter2_reg <= local_C_V_8_addr_reg_2036; - local_C_V_8_addr_reg_2036_pp0_iter3_reg <= local_C_V_8_addr_reg_2036_pp0_iter2_reg; - local_C_V_8_addr_reg_2036_pp0_iter4_reg <= local_C_V_8_addr_reg_2036_pp0_iter3_reg; - local_C_V_8_addr_reg_2036_pp0_iter5_reg <= local_C_V_8_addr_reg_2036_pp0_iter4_reg; - local_C_V_8_addr_reg_2036_pp0_iter6_reg <= local_C_V_8_addr_reg_2036_pp0_iter5_reg; - local_C_V_8_addr_reg_2036_pp0_iter7_reg <= local_C_V_8_addr_reg_2036_pp0_iter6_reg; - local_C_V_8_addr_reg_2036_pp0_iter8_reg <= local_C_V_8_addr_reg_2036_pp0_iter7_reg; - local_C_V_8_addr_reg_2036_pp0_iter9_reg <= local_C_V_8_addr_reg_2036_pp0_iter8_reg; - local_C_V_9_addr_reg_2042_pp0_iter2_reg <= local_C_V_9_addr_reg_2042; - local_C_V_9_addr_reg_2042_pp0_iter3_reg <= local_C_V_9_addr_reg_2042_pp0_iter2_reg; - local_C_V_9_addr_reg_2042_pp0_iter4_reg <= local_C_V_9_addr_reg_2042_pp0_iter3_reg; - local_C_V_9_addr_reg_2042_pp0_iter5_reg <= local_C_V_9_addr_reg_2042_pp0_iter4_reg; - local_C_V_9_addr_reg_2042_pp0_iter6_reg <= local_C_V_9_addr_reg_2042_pp0_iter5_reg; - local_C_V_9_addr_reg_2042_pp0_iter7_reg <= local_C_V_9_addr_reg_2042_pp0_iter6_reg; - local_C_V_9_addr_reg_2042_pp0_iter8_reg <= local_C_V_9_addr_reg_2042_pp0_iter7_reg; - local_C_V_9_addr_reg_2042_pp0_iter9_reg <= local_C_V_9_addr_reg_2042_pp0_iter8_reg; - local_C_V_addr_reg_1988_pp0_iter2_reg <= local_C_V_addr_reg_1988; - local_C_V_addr_reg_1988_pp0_iter3_reg <= local_C_V_addr_reg_1988_pp0_iter2_reg; - local_C_V_addr_reg_1988_pp0_iter4_reg <= local_C_V_addr_reg_1988_pp0_iter3_reg; - local_C_V_addr_reg_1988_pp0_iter5_reg <= local_C_V_addr_reg_1988_pp0_iter4_reg; - local_C_V_addr_reg_1988_pp0_iter6_reg <= local_C_V_addr_reg_1988_pp0_iter5_reg; - local_C_V_addr_reg_1988_pp0_iter7_reg <= local_C_V_addr_reg_1988_pp0_iter6_reg; - local_C_V_addr_reg_1988_pp0_iter8_reg <= local_C_V_addr_reg_1988_pp0_iter7_reg; - local_C_V_addr_reg_1988_pp0_iter9_reg <= local_C_V_addr_reg_1988_pp0_iter8_reg; - p_Result_10_reg_1935_pp0_iter2_reg <= p_Result_10_reg_1935_pp0_iter1_reg; - p_Result_10_reg_1935_pp0_iter3_reg <= p_Result_10_reg_1935_pp0_iter2_reg; - p_Result_10_reg_1935_pp0_iter4_reg <= p_Result_10_reg_1935_pp0_iter3_reg; - p_Result_10_reg_1935_pp0_iter5_reg <= p_Result_10_reg_1935_pp0_iter4_reg; - p_Result_10_reg_1935_pp0_iter6_reg <= p_Result_10_reg_1935_pp0_iter5_reg; - p_Result_10_reg_1935_pp0_iter7_reg <= p_Result_10_reg_1935_pp0_iter6_reg; - p_Result_10_reg_1935_pp0_iter8_reg <= p_Result_10_reg_1935_pp0_iter7_reg; - p_Result_10_reg_1935_pp0_iter9_reg <= p_Result_10_reg_1935_pp0_iter8_reg; - p_Result_15_reg_1984_pp0_iter2_reg <= p_Result_15_reg_1984_pp0_iter1_reg; - p_Result_15_reg_1984_pp0_iter3_reg <= p_Result_15_reg_1984_pp0_iter2_reg; - p_Result_15_reg_1984_pp0_iter4_reg <= p_Result_15_reg_1984_pp0_iter3_reg; - p_Result_15_reg_1984_pp0_iter5_reg <= p_Result_15_reg_1984_pp0_iter4_reg; - p_Result_15_reg_1984_pp0_iter6_reg <= p_Result_15_reg_1984_pp0_iter5_reg; - p_Result_15_reg_1984_pp0_iter7_reg <= p_Result_15_reg_1984_pp0_iter6_reg; - p_Result_15_reg_1984_pp0_iter8_reg <= p_Result_15_reg_1984_pp0_iter7_reg; - p_Result_15_reg_1984_pp0_iter9_reg <= p_Result_15_reg_1984_pp0_iter8_reg; - p_Result_5_reg_1886_pp0_iter2_reg <= p_Result_5_reg_1886_pp0_iter1_reg; - p_Result_5_reg_1886_pp0_iter3_reg <= p_Result_5_reg_1886_pp0_iter2_reg; - p_Result_5_reg_1886_pp0_iter4_reg <= p_Result_5_reg_1886_pp0_iter3_reg; - p_Result_5_reg_1886_pp0_iter5_reg <= p_Result_5_reg_1886_pp0_iter4_reg; - p_Result_5_reg_1886_pp0_iter6_reg <= p_Result_5_reg_1886_pp0_iter5_reg; - p_Result_5_reg_1886_pp0_iter7_reg <= p_Result_5_reg_1886_pp0_iter6_reg; - p_Result_5_reg_1886_pp0_iter8_reg <= p_Result_5_reg_1886_pp0_iter7_reg; - p_Result_5_reg_1886_pp0_iter9_reg <= p_Result_5_reg_1886_pp0_iter8_reg; - p_Result_s_reg_1837_pp0_iter2_reg <= p_Result_s_reg_1837_pp0_iter1_reg; - p_Result_s_reg_1837_pp0_iter3_reg <= p_Result_s_reg_1837_pp0_iter2_reg; - p_Result_s_reg_1837_pp0_iter4_reg <= p_Result_s_reg_1837_pp0_iter3_reg; - p_Result_s_reg_1837_pp0_iter5_reg <= p_Result_s_reg_1837_pp0_iter4_reg; - p_Result_s_reg_1837_pp0_iter6_reg <= p_Result_s_reg_1837_pp0_iter5_reg; - p_Result_s_reg_1837_pp0_iter7_reg <= p_Result_s_reg_1837_pp0_iter6_reg; - p_Result_s_reg_1837_pp0_iter8_reg <= p_Result_s_reg_1837_pp0_iter7_reg; - p_Result_s_reg_1837_pp0_iter9_reg <= p_Result_s_reg_1837_pp0_iter8_reg; - end -end - -always @ (posedge ap_clk) begin - if (((icmp_ln254_fu_610_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'd1 == and_ln260_2_fu_628_p2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - bitcast_ln78_10_reg_1866 <= bitcast_ln78_10_fu_866_p1; - bitcast_ln78_11_reg_1871 <= bitcast_ln78_11_fu_870_p1; - bitcast_ln78_12_reg_1876 <= bitcast_ln78_12_fu_874_p1; - bitcast_ln78_13_reg_1881 <= bitcast_ln78_13_fu_878_p1; - bitcast_ln78_16_reg_1905 <= bitcast_ln78_16_fu_986_p1; - bitcast_ln78_17_reg_1910 <= bitcast_ln78_17_fu_990_p1; - bitcast_ln78_18_reg_1915 <= bitcast_ln78_18_fu_994_p1; - bitcast_ln78_19_reg_1920 <= bitcast_ln78_19_fu_998_p1; - bitcast_ln78_1_reg_1812 <= bitcast_ln78_1_fu_734_p1; - bitcast_ln78_20_reg_1925 <= bitcast_ln78_20_fu_1002_p1; - bitcast_ln78_21_reg_1930 <= bitcast_ln78_21_fu_1006_p1; - bitcast_ln78_24_reg_1954 <= bitcast_ln78_24_fu_1114_p1; - bitcast_ln78_25_reg_1959 <= bitcast_ln78_25_fu_1118_p1; - bitcast_ln78_26_reg_1964 <= bitcast_ln78_26_fu_1122_p1; - bitcast_ln78_27_reg_1969 <= bitcast_ln78_27_fu_1126_p1; - bitcast_ln78_28_reg_1974 <= bitcast_ln78_28_fu_1130_p1; - bitcast_ln78_29_reg_1979 <= bitcast_ln78_29_fu_1134_p1; - bitcast_ln78_2_reg_1817 <= bitcast_ln78_2_fu_738_p1; - bitcast_ln78_3_reg_1822 <= bitcast_ln78_3_fu_742_p1; - bitcast_ln78_4_reg_1827 <= bitcast_ln78_4_fu_746_p1; - bitcast_ln78_5_reg_1832 <= bitcast_ln78_5_fu_750_p1; - bitcast_ln78_8_reg_1856 <= bitcast_ln78_8_fu_858_p1; - bitcast_ln78_9_reg_1861 <= bitcast_ln78_9_fu_862_p1; - bitcast_ln78_reg_1807 <= bitcast_ln78_fu_730_p1; - elem_val_abvec_M_elems_1_reg_1802 <= elem_val_abvec_M_elems_1_fu_726_p1; - elem_val_abvec_M_elems_2_reg_1846 <= elem_val_abvec_M_elems_2_fu_850_p1; - elem_val_abvec_M_elems_3_reg_1851 <= elem_val_abvec_M_elems_3_fu_854_p1; - elem_val_abvec_M_elems_4_reg_1895 <= elem_val_abvec_M_elems_4_fu_978_p1; - elem_val_abvec_M_elems_5_reg_1900 <= elem_val_abvec_M_elems_5_fu_982_p1; - elem_val_abvec_M_elems_6_reg_1944 <= elem_val_abvec_M_elems_6_fu_1106_p1; - elem_val_abvec_M_elems_7_reg_1949 <= elem_val_abvec_M_elems_7_fu_1110_p1; - elem_val_abvec_M_elems_reg_1797 <= elem_val_abvec_M_elems_fu_722_p1; - elem_val_row_V_1_reg_1890 <= elem_val_row_V_1_fu_894_p1; - elem_val_row_V_2_reg_1841 <= elem_val_row_V_2_fu_766_p1; - elem_val_row_V_3_reg_1792 <= elem_val_row_V_3_fu_638_p1; - elem_val_row_V_reg_1939 <= elem_val_row_V_fu_1022_p1; - p_Result_10_reg_1935 <= fifo_aBvec_2_dout[32'd17]; - p_Result_15_reg_1984 <= fifo_aBvec_3_dout[32'd17]; - p_Result_5_reg_1886 <= fifo_aBvec_1_dout[32'd17]; - p_Result_s_reg_1837 <= fifo_aBvec_0_dout[32'd17]; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_10_reg_1935_pp0_iter8_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter8_reg))) begin - c_val_d0_f_10_reg_2504 <= grp_fu_554_p2; - c_val_d0_f_11_reg_2514 <= grp_fu_562_p2; - c_val_d0_f_8_reg_2484 <= grp_fu_538_p2; - c_val_d0_f_9_reg_2494 <= grp_fu_546_p2; - c_val_d1_f_10_reg_2509 <= grp_fu_558_p2; - c_val_d1_f_11_reg_2519 <= grp_fu_566_p2; - c_val_d1_f_8_reg_2489 <= grp_fu_542_p2; - c_val_d1_f_9_reg_2499 <= grp_fu_550_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_15_reg_1984_pp0_iter8_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter8_reg))) begin - c_val_d0_f_12_reg_2524 <= grp_fu_570_p2; - c_val_d0_f_13_reg_2534 <= grp_fu_578_p2; - c_val_d0_f_14_reg_2544 <= grp_fu_586_p2; - c_val_d0_f_15_reg_2554 <= grp_fu_594_p2; - c_val_d1_f_12_reg_2529 <= grp_fu_574_p2; - c_val_d1_f_13_reg_2539 <= grp_fu_582_p2; - c_val_d1_f_14_reg_2549 <= grp_fu_590_p2; - c_val_d1_f_15_reg_2559 <= grp_fu_598_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_s_reg_1837_pp0_iter8_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter8_reg))) begin - c_val_d0_f_1_reg_2414 <= grp_fu_482_p2; - c_val_d0_f_2_reg_2424 <= grp_fu_490_p2; - c_val_d0_f_3_reg_2434 <= grp_fu_498_p2; - c_val_d0_f_reg_2404 <= grp_fu_474_p2; - c_val_d1_f_1_reg_2419 <= grp_fu_486_p2; - c_val_d1_f_2_reg_2429 <= grp_fu_494_p2; - c_val_d1_f_3_reg_2439 <= grp_fu_502_p2; - c_val_d1_f_reg_2409 <= grp_fu_478_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_5_reg_1886_pp0_iter8_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter8_reg))) begin - c_val_d0_f_4_reg_2444 <= grp_fu_506_p2; - c_val_d0_f_5_reg_2454 <= grp_fu_514_p2; - c_val_d0_f_6_reg_2464 <= grp_fu_522_p2; - c_val_d0_f_7_reg_2474 <= grp_fu_530_p2; - c_val_d1_f_4_reg_2449 <= grp_fu_510_p2; - c_val_d1_f_5_reg_2459 <= grp_fu_518_p2; - c_val_d1_f_6_reg_2469 <= grp_fu_526_p2; - c_val_d1_f_7_reg_2479 <= grp_fu_534_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_10_reg_1935_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg))) begin - c_val_d0_u_V_10_reg_2184 <= c_val_d0_u_V_10_fu_1325_p1; - c_val_d0_u_V_11_reg_2194 <= c_val_d0_u_V_11_fu_1339_p1; - c_val_d0_u_V_8_reg_2164 <= c_val_d0_u_V_8_fu_1297_p1; - c_val_d0_u_V_9_reg_2174 <= c_val_d0_u_V_9_fu_1311_p1; - c_val_d1_u_V_10_reg_2189 <= {{local_C_V_10_q0[63:32]}}; - c_val_d1_u_V_11_reg_2199 <= {{local_C_V_11_q0[63:32]}}; - c_val_d1_u_V_8_reg_2169 <= {{local_C_V_8_q0[63:32]}}; - c_val_d1_u_V_9_reg_2179 <= {{local_C_V_9_q0[63:32]}}; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_15_reg_1984_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg))) begin - c_val_d0_u_V_12_reg_2204 <= c_val_d0_u_V_12_fu_1353_p1; - c_val_d0_u_V_13_reg_2214 <= c_val_d0_u_V_13_fu_1367_p1; - c_val_d0_u_V_14_reg_2224 <= c_val_d0_u_V_14_fu_1381_p1; - c_val_d0_u_V_15_reg_2234 <= c_val_d0_u_V_15_fu_1395_p1; - c_val_d1_u_V_12_reg_2209 <= {{local_C_V_12_q0[63:32]}}; - c_val_d1_u_V_13_reg_2219 <= {{local_C_V_13_q0[63:32]}}; - c_val_d1_u_V_14_reg_2229 <= {{local_C_V_14_q0[63:32]}}; - c_val_d1_u_V_15_reg_2239 <= {{local_C_V_15_q0[63:32]}}; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_s_reg_1837_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg))) begin - c_val_d0_u_V_1_reg_2094 <= c_val_d0_u_V_1_fu_1199_p1; - c_val_d0_u_V_2_reg_2104 <= c_val_d0_u_V_2_fu_1213_p1; - c_val_d0_u_V_3_reg_2114 <= c_val_d0_u_V_3_fu_1227_p1; - c_val_d0_u_V_reg_2084 <= c_val_d0_u_V_fu_1185_p1; - c_val_d1_u_V_1_reg_2099 <= {{local_C_V_1_q0[63:32]}}; - c_val_d1_u_V_2_reg_2109 <= {{local_C_V_2_q0[63:32]}}; - c_val_d1_u_V_3_reg_2119 <= {{local_C_V_3_q0[63:32]}}; - c_val_d1_u_V_reg_2089 <= {{local_C_V_q0[63:32]}}; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_5_reg_1886_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg))) begin - c_val_d0_u_V_4_reg_2124 <= c_val_d0_u_V_4_fu_1241_p1; - c_val_d0_u_V_5_reg_2134 <= c_val_d0_u_V_5_fu_1255_p1; - c_val_d0_u_V_6_reg_2144 <= c_val_d0_u_V_6_fu_1269_p1; - c_val_d0_u_V_7_reg_2154 <= c_val_d0_u_V_7_fu_1283_p1; - c_val_d1_u_V_4_reg_2129 <= {{local_C_V_4_q0[63:32]}}; - c_val_d1_u_V_5_reg_2139 <= {{local_C_V_5_q0[63:32]}}; - c_val_d1_u_V_6_reg_2149 <= {{local_C_V_6_q0[63:32]}}; - c_val_d1_u_V_7_reg_2159 <= {{local_C_V_7_q0[63:32]}}; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_10_reg_1935 == 1'd0) & (1'd1 == and_ln260_2_reg_1788) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_10_addr_reg_2048 <= conv_i_i_i_2_fu_1171_p1; - local_C_V_11_addr_reg_2054 <= conv_i_i_i_2_fu_1171_p1; - local_C_V_8_addr_reg_2036 <= conv_i_i_i_2_fu_1171_p1; - local_C_V_9_addr_reg_2042 <= conv_i_i_i_2_fu_1171_p1; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_15_reg_1984 == 1'd0) & (1'd1 == and_ln260_2_reg_1788) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_12_addr_reg_2060 <= conv_i_i_i_3_fu_1178_p1; - local_C_V_13_addr_reg_2066 <= conv_i_i_i_3_fu_1178_p1; - local_C_V_14_addr_reg_2072 <= conv_i_i_i_3_fu_1178_p1; - local_C_V_15_addr_reg_2078 <= conv_i_i_i_3_fu_1178_p1; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_s_reg_1837 == 1'd0) & (1'd1 == and_ln260_2_reg_1788) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_1_addr_reg_1994 <= conv_i_i_i_fu_1157_p1; - local_C_V_2_addr_reg_2000 <= conv_i_i_i_fu_1157_p1; - local_C_V_3_addr_reg_2006 <= conv_i_i_i_fu_1157_p1; - local_C_V_addr_reg_1988 <= conv_i_i_i_fu_1157_p1; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_5_reg_1886 == 1'd0) & (1'd1 == and_ln260_2_reg_1788) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_4_addr_reg_2012 <= conv_i_i_i_1_fu_1164_p1; - local_C_V_5_addr_reg_2018 <= conv_i_i_i_1_fu_1164_p1; - local_C_V_6_addr_reg_2024 <= conv_i_i_i_1_fu_1164_p1; - local_C_V_7_addr_reg_2030 <= conv_i_i_i_1_fu_1164_p1; - end -end - -always @ (*) begin - if (((icmp_ln254_fu_610_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter9_reg == 1'b1))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (ap_start_int == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1))) begin - ap_sig_allocacmp_j_1 = start_32_3; - end else begin - ap_sig_allocacmp_j_1 = j_fu_130; - end -end - -always @ (*) begin - if (((icmp_ln254_fu_610_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'd1 == and_ln260_2_fu_628_p2) & (fifo_aBvec_0_empty_n == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_aBvec_0_read = 1'b1; - end else begin - fifo_aBvec_0_read = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln254_fu_610_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'd1 == and_ln260_2_fu_628_p2) & (fifo_aBvec_1_empty_n == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_aBvec_1_read = 1'b1; - end else begin - fifo_aBvec_1_read = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln254_fu_610_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'd1 == and_ln260_2_fu_628_p2) & (fifo_aBvec_2_empty_n == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_aBvec_2_read = 1'b1; - end else begin - fifo_aBvec_2_read = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln254_fu_610_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'd1 == and_ln260_2_fu_628_p2) & (fifo_aBvec_3_empty_n == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_aBvec_3_read = 1'b1; - end else begin - fifo_aBvec_3_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_10_ce0 = 1'b1; - end else begin - local_C_V_10_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_10_ce1 = 1'b1; - end else begin - local_C_V_10_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_10_reg_1935_pp0_iter9_reg == 1'd0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_10_we1 = 1'b1; - end else begin - local_C_V_10_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_11_ce0 = 1'b1; - end else begin - local_C_V_11_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_11_ce1 = 1'b1; - end else begin - local_C_V_11_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_10_reg_1935_pp0_iter9_reg == 1'd0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_11_we1 = 1'b1; - end else begin - local_C_V_11_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_12_ce0 = 1'b1; - end else begin - local_C_V_12_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_12_ce1 = 1'b1; - end else begin - local_C_V_12_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_15_reg_1984_pp0_iter9_reg == 1'd0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_12_we1 = 1'b1; - end else begin - local_C_V_12_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_13_ce0 = 1'b1; - end else begin - local_C_V_13_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_13_ce1 = 1'b1; - end else begin - local_C_V_13_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_15_reg_1984_pp0_iter9_reg == 1'd0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_13_we1 = 1'b1; - end else begin - local_C_V_13_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_14_ce0 = 1'b1; - end else begin - local_C_V_14_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_14_ce1 = 1'b1; - end else begin - local_C_V_14_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_15_reg_1984_pp0_iter9_reg == 1'd0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_14_we1 = 1'b1; - end else begin - local_C_V_14_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_15_ce0 = 1'b1; - end else begin - local_C_V_15_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_15_ce1 = 1'b1; - end else begin - local_C_V_15_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_15_reg_1984_pp0_iter9_reg == 1'd0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_15_we1 = 1'b1; - end else begin - local_C_V_15_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_1_ce0 = 1'b1; - end else begin - local_C_V_1_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_1_ce1 = 1'b1; - end else begin - local_C_V_1_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1) & (p_Result_s_reg_1837_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_1_we1 = 1'b1; - end else begin - local_C_V_1_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_2_ce0 = 1'b1; - end else begin - local_C_V_2_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_2_ce1 = 1'b1; - end else begin - local_C_V_2_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1) & (p_Result_s_reg_1837_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_2_we1 = 1'b1; - end else begin - local_C_V_2_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_3_ce0 = 1'b1; - end else begin - local_C_V_3_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_3_ce1 = 1'b1; - end else begin - local_C_V_3_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1) & (p_Result_s_reg_1837_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_3_we1 = 1'b1; - end else begin - local_C_V_3_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_4_ce0 = 1'b1; - end else begin - local_C_V_4_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_4_ce1 = 1'b1; - end else begin - local_C_V_4_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1) & (p_Result_5_reg_1886_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_4_we1 = 1'b1; - end else begin - local_C_V_4_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_5_ce0 = 1'b1; - end else begin - local_C_V_5_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_5_ce1 = 1'b1; - end else begin - local_C_V_5_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1) & (p_Result_5_reg_1886_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_5_we1 = 1'b1; - end else begin - local_C_V_5_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_6_ce0 = 1'b1; - end else begin - local_C_V_6_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_6_ce1 = 1'b1; - end else begin - local_C_V_6_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1) & (p_Result_5_reg_1886_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_6_we1 = 1'b1; - end else begin - local_C_V_6_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_7_ce0 = 1'b1; - end else begin - local_C_V_7_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_7_ce1 = 1'b1; - end else begin - local_C_V_7_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1) & (p_Result_5_reg_1886_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_7_we1 = 1'b1; - end else begin - local_C_V_7_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_8_ce0 = 1'b1; - end else begin - local_C_V_8_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_8_ce1 = 1'b1; - end else begin - local_C_V_8_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_10_reg_1935_pp0_iter9_reg == 1'd0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_8_we1 = 1'b1; - end else begin - local_C_V_8_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_9_ce0 = 1'b1; - end else begin - local_C_V_9_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_9_ce1 = 1'b1; - end else begin - local_C_V_9_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (p_Result_10_reg_1935_pp0_iter9_reg == 1'd0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_9_we1 = 1'b1; - end else begin - local_C_V_9_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_ce0 = 1'b1; - end else begin - local_C_V_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin - local_C_V_ce1 = 1'b1; - end else begin - local_C_V_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1) & (p_Result_s_reg_1837_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg))) begin - local_C_V_we1 = 1'b1; - end else begin - local_C_V_we1 = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign and_ln260_1_fu_616_p2 = (tmp_3_nbreadreq_fu_170_p3 & tmp_2_nbreadreq_fu_162_p3); - -assign and_ln260_2_fu_628_p2 = (tmp_nbreadreq_fu_146_p3 & and_ln260_fu_622_p2); - -assign and_ln260_fu_622_p2 = (tmp_1_nbreadreq_fu_154_p3 & and_ln260_1_fu_616_p2); - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -always @ (*) begin - ap_block_pp0 = ((ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (1'b1 == ap_block_pp0_stage0_subdone)); -end - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_condition_2344 = ((icmp_ln254_fu_610_p2 == 1'd1) & (1'd1 == and_ln260_2_fu_628_p2) & (ap_enable_reg_pp0_iter0 == 1'b1)); -end - -always @ (*) begin - ap_enable_operation_143 = (ap_predicate_op143_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_145 = (ap_predicate_op145_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_147 = (ap_predicate_op147_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_149 = (ap_predicate_op149_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_152 = (ap_predicate_op152_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_154 = (ap_predicate_op154_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_156 = (ap_predicate_op156_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_158 = (ap_predicate_op158_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_161 = (ap_predicate_op161_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_163 = (ap_predicate_op163_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_165 = (ap_predicate_op165_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_167 = (ap_predicate_op167_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_170 = (ap_predicate_op170_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_172 = (ap_predicate_op172_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_174 = (ap_predicate_op174_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_176 = (ap_predicate_op176_load_state2 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_177 = (ap_predicate_op177_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_180 = (ap_predicate_op180_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_183 = (ap_predicate_op183_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_186 = (ap_predicate_op186_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_189 = (ap_predicate_op189_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_192 = (ap_predicate_op192_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_195 = (ap_predicate_op195_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_198 = (ap_predicate_op198_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_201 = (ap_predicate_op201_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_204 = (ap_predicate_op204_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_207 = (ap_predicate_op207_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_210 = (ap_predicate_op210_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_213 = (ap_predicate_op213_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_216 = (ap_predicate_op216_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_219 = (ap_predicate_op219_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_222 = (ap_predicate_op222_load_state3 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_484 = (ap_predicate_op484_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_488 = (ap_predicate_op488_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_492 = (ap_predicate_op492_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_496 = (ap_predicate_op496_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_501 = (ap_predicate_op501_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_505 = (ap_predicate_op505_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_509 = (ap_predicate_op509_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_513 = (ap_predicate_op513_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_518 = (ap_predicate_op518_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_522 = (ap_predicate_op522_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_526 = (ap_predicate_op526_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_530 = (ap_predicate_op530_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_535 = (ap_predicate_op535_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_539 = (ap_predicate_op539_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_543 = (ap_predicate_op543_store_state11 == 1'b1); -end - -always @ (*) begin - ap_enable_operation_547 = (ap_predicate_op547_store_state11 == 1'b1); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -always @ (*) begin - ap_enable_state11_pp0_iter10_stage0 = ((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)); -end - -always @ (*) begin - ap_enable_state2_pp0_iter1_stage0 = ((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)); -end - -always @ (*) begin - ap_enable_state3_pp0_iter2_stage0 = ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)); -end - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -always @ (*) begin - ap_predicate_op143_load_state2 = ((p_Result_s_reg_1837 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op145_load_state2 = ((p_Result_s_reg_1837 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op147_load_state2 = ((p_Result_s_reg_1837 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op149_load_state2 = ((p_Result_s_reg_1837 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op152_load_state2 = ((p_Result_5_reg_1886 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op154_load_state2 = ((p_Result_5_reg_1886 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op156_load_state2 = ((p_Result_5_reg_1886 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op158_load_state2 = ((p_Result_5_reg_1886 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op161_load_state2 = ((p_Result_10_reg_1935 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op163_load_state2 = ((p_Result_10_reg_1935 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op165_load_state2 = ((p_Result_10_reg_1935 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op167_load_state2 = ((p_Result_10_reg_1935 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op170_load_state2 = ((p_Result_15_reg_1984 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op172_load_state2 = ((p_Result_15_reg_1984 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op174_load_state2 = ((p_Result_15_reg_1984 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op176_load_state2 = ((p_Result_15_reg_1984 == 1'd0) & (1'd1 == and_ln260_2_reg_1788)); -end - -always @ (*) begin - ap_predicate_op177_load_state3 = ((p_Result_s_reg_1837_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op180_load_state3 = ((p_Result_s_reg_1837_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op183_load_state3 = ((p_Result_s_reg_1837_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op186_load_state3 = ((p_Result_s_reg_1837_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op189_load_state3 = ((p_Result_5_reg_1886_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op192_load_state3 = ((p_Result_5_reg_1886_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op195_load_state3 = ((p_Result_5_reg_1886_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op198_load_state3 = ((p_Result_5_reg_1886_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op201_load_state3 = ((p_Result_10_reg_1935_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op204_load_state3 = ((p_Result_10_reg_1935_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op207_load_state3 = ((p_Result_10_reg_1935_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op210_load_state3 = ((p_Result_10_reg_1935_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op213_load_state3 = ((p_Result_15_reg_1984_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op216_load_state3 = ((p_Result_15_reg_1984_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op219_load_state3 = ((p_Result_15_reg_1984_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op222_load_state3 = ((p_Result_15_reg_1984_pp0_iter1_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter1_reg)); -end - -always @ (*) begin - ap_predicate_op484_store_state11 = ((p_Result_s_reg_1837_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op488_store_state11 = ((p_Result_s_reg_1837_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op492_store_state11 = ((p_Result_s_reg_1837_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op496_store_state11 = ((p_Result_s_reg_1837_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op501_store_state11 = ((p_Result_5_reg_1886_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op505_store_state11 = ((p_Result_5_reg_1886_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op509_store_state11 = ((p_Result_5_reg_1886_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op513_store_state11 = ((p_Result_5_reg_1886_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op518_store_state11 = ((p_Result_10_reg_1935_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op522_store_state11 = ((p_Result_10_reg_1935_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op526_store_state11 = ((p_Result_10_reg_1935_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op530_store_state11 = ((p_Result_10_reg_1935_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op535_store_state11 = ((p_Result_15_reg_1984_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op539_store_state11 = ((p_Result_15_reg_1984_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op543_store_state11 = ((p_Result_15_reg_1984_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -always @ (*) begin - ap_predicate_op547_store_state11 = ((p_Result_15_reg_1984_pp0_iter9_reg == 1'd0) & (1'd1 == and_ln260_2_reg_1788_pp0_iter9_reg)); -end - -assign bitcast_ln78_10_fu_866_p1 = trunc_ln78_11_fu_810_p4; - -assign bitcast_ln78_11_fu_870_p1 = trunc_ln78_12_fu_820_p4; - -assign bitcast_ln78_12_fu_874_p1 = trunc_ln78_13_fu_830_p4; - -assign bitcast_ln78_13_fu_878_p1 = trunc_ln78_14_fu_840_p4; - -assign bitcast_ln78_16_fu_986_p1 = trunc_ln78_17_fu_918_p4; - -assign bitcast_ln78_17_fu_990_p1 = trunc_ln78_18_fu_928_p4; - -assign bitcast_ln78_18_fu_994_p1 = trunc_ln78_19_fu_938_p4; - -assign bitcast_ln78_19_fu_998_p1 = trunc_ln78_20_fu_948_p4; - -assign bitcast_ln78_1_fu_734_p1 = trunc_ln78_3_fu_672_p4; - -assign bitcast_ln78_20_fu_1002_p1 = trunc_ln78_21_fu_958_p4; - -assign bitcast_ln78_21_fu_1006_p1 = trunc_ln78_22_fu_968_p4; - -assign bitcast_ln78_24_fu_1114_p1 = trunc_ln78_25_fu_1046_p4; - -assign bitcast_ln78_25_fu_1118_p1 = trunc_ln78_26_fu_1056_p4; - -assign bitcast_ln78_26_fu_1122_p1 = trunc_ln78_27_fu_1066_p4; - -assign bitcast_ln78_27_fu_1126_p1 = trunc_ln78_28_fu_1076_p4; - -assign bitcast_ln78_28_fu_1130_p1 = trunc_ln78_29_fu_1086_p4; - -assign bitcast_ln78_29_fu_1134_p1 = trunc_ln78_30_fu_1096_p4; - -assign bitcast_ln78_2_fu_738_p1 = trunc_ln78_4_fu_682_p4; - -assign bitcast_ln78_3_fu_742_p1 = trunc_ln78_5_fu_692_p4; - -assign bitcast_ln78_4_fu_746_p1 = trunc_ln78_6_fu_702_p4; - -assign bitcast_ln78_5_fu_750_p1 = trunc_ln78_7_fu_712_p4; - -assign bitcast_ln78_8_fu_858_p1 = trunc_ln78_s_fu_790_p4; - -assign bitcast_ln78_9_fu_862_p1 = trunc_ln78_10_fu_800_p4; - -assign bitcast_ln78_fu_730_p1 = trunc_ln78_2_fu_662_p4; - -assign c_val_d0_u_V_10_fu_1325_p1 = local_C_V_10_q0[31:0]; - -assign c_val_d0_u_V_11_fu_1339_p1 = local_C_V_11_q0[31:0]; - -assign c_val_d0_u_V_12_fu_1353_p1 = local_C_V_12_q0[31:0]; - -assign c_val_d0_u_V_13_fu_1367_p1 = local_C_V_13_q0[31:0]; - -assign c_val_d0_u_V_14_fu_1381_p1 = local_C_V_14_q0[31:0]; - -assign c_val_d0_u_V_15_fu_1395_p1 = local_C_V_15_q0[31:0]; - -assign c_val_d0_u_V_1_fu_1199_p1 = local_C_V_1_q0[31:0]; - -assign c_val_d0_u_V_2_fu_1213_p1 = local_C_V_2_q0[31:0]; - -assign c_val_d0_u_V_3_fu_1227_p1 = local_C_V_3_q0[31:0]; - -assign c_val_d0_u_V_4_fu_1241_p1 = local_C_V_4_q0[31:0]; - -assign c_val_d0_u_V_5_fu_1255_p1 = local_C_V_5_q0[31:0]; - -assign c_val_d0_u_V_6_fu_1269_p1 = local_C_V_6_q0[31:0]; - -assign c_val_d0_u_V_7_fu_1283_p1 = local_C_V_7_q0[31:0]; - -assign c_val_d0_u_V_8_fu_1297_p1 = local_C_V_8_q0[31:0]; - -assign c_val_d0_u_V_9_fu_1311_p1 = local_C_V_9_q0[31:0]; - -assign c_val_d0_u_V_fu_1185_p1 = local_C_V_q0[31:0]; - -assign conv_i_i_i_1_fu_1164_p1 = elem_val_row_V_2_reg_1841; - -assign conv_i_i_i_2_fu_1171_p1 = elem_val_row_V_1_reg_1890; - -assign conv_i_i_i_3_fu_1178_p1 = elem_val_row_V_reg_1939; - -assign conv_i_i_i_fu_1157_p1 = elem_val_row_V_3_reg_1792; - -assign elem_val_abvec_M_elems_1_fu_726_p1 = trunc_ln78_1_fu_652_p4; - -assign elem_val_abvec_M_elems_2_fu_850_p1 = trunc_ln78_8_fu_770_p4; - -assign elem_val_abvec_M_elems_3_fu_854_p1 = trunc_ln78_9_fu_780_p4; - -assign elem_val_abvec_M_elems_4_fu_978_p1 = trunc_ln78_15_fu_898_p4; - -assign elem_val_abvec_M_elems_5_fu_982_p1 = trunc_ln78_16_fu_908_p4; - -assign elem_val_abvec_M_elems_6_fu_1106_p1 = trunc_ln78_23_fu_1026_p4; - -assign elem_val_abvec_M_elems_7_fu_1110_p1 = trunc_ln78_24_fu_1036_p4; - -assign elem_val_abvec_M_elems_fu_722_p1 = trunc_ln2_fu_642_p4; - -assign elem_val_row_V_1_fu_894_p1 = fifo_aBvec_2_dout[17:0]; - -assign elem_val_row_V_2_fu_766_p1 = fifo_aBvec_1_dout[17:0]; - -assign elem_val_row_V_3_fu_638_p1 = fifo_aBvec_0_dout[17:0]; - -assign elem_val_row_V_fu_1022_p1 = fifo_aBvec_3_dout[17:0]; - -assign empty_100_fu_1690_p1 = c_val_d1_f_10_reg_2509; - -assign empty_103_fu_1702_p1 = c_val_d0_f_11_reg_2514; - -assign empty_104_fu_1705_p1 = c_val_d1_f_11_reg_2519; - -assign empty_107_fu_1717_p1 = c_val_d0_f_12_reg_2524; - -assign empty_108_fu_1720_p1 = c_val_d1_f_12_reg_2529; - -assign empty_111_fu_1732_p1 = c_val_d0_f_13_reg_2534; - -assign empty_112_fu_1735_p1 = c_val_d1_f_13_reg_2539; - -assign empty_115_fu_1747_p1 = c_val_d0_f_14_reg_2544; - -assign empty_116_fu_1750_p1 = c_val_d1_f_14_reg_2549; - -assign empty_119_fu_1762_p1 = c_val_d0_f_15_reg_2554; - -assign empty_120_fu_1765_p1 = c_val_d1_f_15_reg_2559; - -assign empty_59_fu_1537_p1 = c_val_d0_f_reg_2404; - -assign empty_60_fu_1540_p1 = c_val_d1_f_reg_2409; - -assign empty_63_fu_1552_p1 = c_val_d0_f_1_reg_2414; - -assign empty_64_fu_1555_p1 = c_val_d1_f_1_reg_2419; - -assign empty_67_fu_1567_p1 = c_val_d0_f_2_reg_2424; - -assign empty_68_fu_1570_p1 = c_val_d1_f_2_reg_2429; - -assign empty_71_fu_1582_p1 = c_val_d0_f_3_reg_2434; - -assign empty_72_fu_1585_p1 = c_val_d1_f_3_reg_2439; - -assign empty_75_fu_1597_p1 = c_val_d0_f_4_reg_2444; - -assign empty_76_fu_1600_p1 = c_val_d1_f_4_reg_2449; - -assign empty_79_fu_1612_p1 = c_val_d0_f_5_reg_2454; - -assign empty_80_fu_1615_p1 = c_val_d1_f_5_reg_2459; - -assign empty_83_fu_1627_p1 = c_val_d0_f_6_reg_2464; - -assign empty_84_fu_1630_p1 = c_val_d1_f_6_reg_2469; - -assign empty_87_fu_1642_p1 = c_val_d0_f_7_reg_2474; - -assign empty_88_fu_1645_p1 = c_val_d1_f_7_reg_2479; - -assign empty_91_fu_1657_p1 = c_val_d0_f_8_reg_2484; - -assign empty_92_fu_1660_p1 = c_val_d1_f_8_reg_2489; - -assign empty_95_fu_1672_p1 = c_val_d0_f_9_reg_2494; - -assign empty_96_fu_1675_p1 = c_val_d1_f_9_reg_2499; - -assign empty_99_fu_1687_p1 = c_val_d0_f_10_reg_2504; - -assign grp_fu_474_p0 = c_val_d0_u_V_reg_2084; - -assign grp_fu_478_p0 = c_val_d1_u_V_reg_2089; - -assign grp_fu_482_p0 = c_val_d0_u_V_1_reg_2094; - -assign grp_fu_486_p0 = c_val_d1_u_V_1_reg_2099; - -assign grp_fu_490_p0 = c_val_d0_u_V_2_reg_2104; - -assign grp_fu_494_p0 = c_val_d1_u_V_2_reg_2109; - -assign grp_fu_498_p0 = c_val_d0_u_V_3_reg_2114; - -assign grp_fu_502_p0 = c_val_d1_u_V_3_reg_2119; - -assign grp_fu_506_p0 = c_val_d0_u_V_4_reg_2124; - -assign grp_fu_510_p0 = c_val_d1_u_V_4_reg_2129; - -assign grp_fu_514_p0 = c_val_d0_u_V_5_reg_2134; - -assign grp_fu_518_p0 = c_val_d1_u_V_5_reg_2139; - -assign grp_fu_522_p0 = c_val_d0_u_V_6_reg_2144; - -assign grp_fu_526_p0 = c_val_d1_u_V_6_reg_2149; - -assign grp_fu_530_p0 = c_val_d0_u_V_7_reg_2154; - -assign grp_fu_534_p0 = c_val_d1_u_V_7_reg_2159; - -assign grp_fu_538_p0 = c_val_d0_u_V_8_reg_2164; - -assign grp_fu_542_p0 = c_val_d1_u_V_8_reg_2169; - -assign grp_fu_546_p0 = c_val_d0_u_V_9_reg_2174; - -assign grp_fu_550_p0 = c_val_d1_u_V_9_reg_2179; - -assign grp_fu_554_p0 = c_val_d0_u_V_10_reg_2184; - -assign grp_fu_558_p0 = c_val_d1_u_V_10_reg_2189; - -assign grp_fu_562_p0 = c_val_d0_u_V_11_reg_2194; - -assign grp_fu_566_p0 = c_val_d1_u_V_11_reg_2199; - -assign grp_fu_570_p0 = c_val_d0_u_V_12_reg_2204; - -assign grp_fu_574_p0 = c_val_d1_u_V_12_reg_2209; - -assign grp_fu_578_p0 = c_val_d0_u_V_13_reg_2214; - -assign grp_fu_582_p0 = c_val_d1_u_V_13_reg_2219; - -assign grp_fu_586_p0 = c_val_d0_u_V_14_reg_2224; - -assign grp_fu_590_p0 = c_val_d1_u_V_14_reg_2229; - -assign grp_fu_594_p0 = c_val_d0_u_V_15_reg_2234; - -assign grp_fu_598_p0 = c_val_d1_u_V_15_reg_2239; - -assign icmp_ln254_fu_610_p2 = (($signed(ap_sig_allocacmp_j_1) < $signed(end_32)) ? 1'b1 : 1'b0); - -assign j_2_fu_1146_p2 = (ap_sig_allocacmp_j_1 + 32'd1); - -assign local_C_V_10_address0 = conv_i_i_i_2_fu_1171_p1; - -assign local_C_V_10_address1 = local_C_V_10_addr_reg_2048_pp0_iter9_reg; - -assign local_C_V_10_d1 = {{empty_100_fu_1690_p1}, {empty_99_fu_1687_p1}}; - -assign local_C_V_11_address0 = conv_i_i_i_2_fu_1171_p1; - -assign local_C_V_11_address1 = local_C_V_11_addr_reg_2054_pp0_iter9_reg; - -assign local_C_V_11_d1 = {{empty_104_fu_1705_p1}, {empty_103_fu_1702_p1}}; - -assign local_C_V_12_address0 = conv_i_i_i_3_fu_1178_p1; - -assign local_C_V_12_address1 = local_C_V_12_addr_reg_2060_pp0_iter9_reg; - -assign local_C_V_12_d1 = {{empty_108_fu_1720_p1}, {empty_107_fu_1717_p1}}; - -assign local_C_V_13_address0 = conv_i_i_i_3_fu_1178_p1; - -assign local_C_V_13_address1 = local_C_V_13_addr_reg_2066_pp0_iter9_reg; - -assign local_C_V_13_d1 = {{empty_112_fu_1735_p1}, {empty_111_fu_1732_p1}}; - -assign local_C_V_14_address0 = conv_i_i_i_3_fu_1178_p1; - -assign local_C_V_14_address1 = local_C_V_14_addr_reg_2072_pp0_iter9_reg; - -assign local_C_V_14_d1 = {{empty_116_fu_1750_p1}, {empty_115_fu_1747_p1}}; - -assign local_C_V_15_address0 = conv_i_i_i_3_fu_1178_p1; - -assign local_C_V_15_address1 = local_C_V_15_addr_reg_2078_pp0_iter9_reg; - -assign local_C_V_15_d1 = {{empty_120_fu_1765_p1}, {empty_119_fu_1762_p1}}; - -assign local_C_V_1_address0 = conv_i_i_i_fu_1157_p1; - -assign local_C_V_1_address1 = local_C_V_1_addr_reg_1994_pp0_iter9_reg; - -assign local_C_V_1_d1 = {{empty_64_fu_1555_p1}, {empty_63_fu_1552_p1}}; - -assign local_C_V_2_address0 = conv_i_i_i_fu_1157_p1; - -assign local_C_V_2_address1 = local_C_V_2_addr_reg_2000_pp0_iter9_reg; - -assign local_C_V_2_d1 = {{empty_68_fu_1570_p1}, {empty_67_fu_1567_p1}}; - -assign local_C_V_3_address0 = conv_i_i_i_fu_1157_p1; - -assign local_C_V_3_address1 = local_C_V_3_addr_reg_2006_pp0_iter9_reg; - -assign local_C_V_3_d1 = {{empty_72_fu_1585_p1}, {empty_71_fu_1582_p1}}; - -assign local_C_V_4_address0 = conv_i_i_i_1_fu_1164_p1; - -assign local_C_V_4_address1 = local_C_V_4_addr_reg_2012_pp0_iter9_reg; - -assign local_C_V_4_d1 = {{empty_76_fu_1600_p1}, {empty_75_fu_1597_p1}}; - -assign local_C_V_5_address0 = conv_i_i_i_1_fu_1164_p1; - -assign local_C_V_5_address1 = local_C_V_5_addr_reg_2018_pp0_iter9_reg; - -assign local_C_V_5_d1 = {{empty_80_fu_1615_p1}, {empty_79_fu_1612_p1}}; - -assign local_C_V_6_address0 = conv_i_i_i_1_fu_1164_p1; - -assign local_C_V_6_address1 = local_C_V_6_addr_reg_2024_pp0_iter9_reg; - -assign local_C_V_6_d1 = {{empty_84_fu_1630_p1}, {empty_83_fu_1627_p1}}; - -assign local_C_V_7_address0 = conv_i_i_i_1_fu_1164_p1; - -assign local_C_V_7_address1 = local_C_V_7_addr_reg_2030_pp0_iter9_reg; - -assign local_C_V_7_d1 = {{empty_88_fu_1645_p1}, {empty_87_fu_1642_p1}}; - -assign local_C_V_8_address0 = conv_i_i_i_2_fu_1171_p1; - -assign local_C_V_8_address1 = local_C_V_8_addr_reg_2036_pp0_iter9_reg; - -assign local_C_V_8_d1 = {{empty_92_fu_1660_p1}, {empty_91_fu_1657_p1}}; - -assign local_C_V_9_address0 = conv_i_i_i_2_fu_1171_p1; - -assign local_C_V_9_address1 = local_C_V_9_addr_reg_2042_pp0_iter9_reg; - -assign local_C_V_9_d1 = {{empty_96_fu_1675_p1}, {empty_95_fu_1672_p1}}; - -assign local_C_V_address0 = conv_i_i_i_fu_1157_p1; - -assign local_C_V_address1 = local_C_V_addr_reg_1988_pp0_iter9_reg; - -assign local_C_V_d1 = {{empty_60_fu_1540_p1}, {empty_59_fu_1537_p1}}; - -assign tmp_1_nbreadreq_fu_154_p3 = fifo_aBvec_1_empty_n; - -assign tmp_2_nbreadreq_fu_162_p3 = fifo_aBvec_2_empty_n; - -assign tmp_3_nbreadreq_fu_170_p3 = fifo_aBvec_3_empty_n; - -assign tmp_nbreadreq_fu_146_p3 = fifo_aBvec_0_empty_n; - -assign trunc_ln2_fu_642_p4 = {{fifo_aBvec_0_dout[49:18]}}; - -assign trunc_ln78_10_fu_800_p4 = {{fifo_aBvec_1_dout[145:114]}}; - -assign trunc_ln78_11_fu_810_p4 = {{fifo_aBvec_1_dout[177:146]}}; - -assign trunc_ln78_12_fu_820_p4 = {{fifo_aBvec_1_dout[209:178]}}; - -assign trunc_ln78_13_fu_830_p4 = {{fifo_aBvec_1_dout[241:210]}}; - -assign trunc_ln78_14_fu_840_p4 = {{fifo_aBvec_1_dout[273:242]}}; - -assign trunc_ln78_15_fu_898_p4 = {{fifo_aBvec_2_dout[49:18]}}; - -assign trunc_ln78_16_fu_908_p4 = {{fifo_aBvec_2_dout[81:50]}}; - -assign trunc_ln78_17_fu_918_p4 = {{fifo_aBvec_2_dout[113:82]}}; - -assign trunc_ln78_18_fu_928_p4 = {{fifo_aBvec_2_dout[145:114]}}; - -assign trunc_ln78_19_fu_938_p4 = {{fifo_aBvec_2_dout[177:146]}}; - -assign trunc_ln78_1_fu_652_p4 = {{fifo_aBvec_0_dout[81:50]}}; - -assign trunc_ln78_20_fu_948_p4 = {{fifo_aBvec_2_dout[209:178]}}; - -assign trunc_ln78_21_fu_958_p4 = {{fifo_aBvec_2_dout[241:210]}}; - -assign trunc_ln78_22_fu_968_p4 = {{fifo_aBvec_2_dout[273:242]}}; - -assign trunc_ln78_23_fu_1026_p4 = {{fifo_aBvec_3_dout[49:18]}}; - -assign trunc_ln78_24_fu_1036_p4 = {{fifo_aBvec_3_dout[81:50]}}; - -assign trunc_ln78_25_fu_1046_p4 = {{fifo_aBvec_3_dout[113:82]}}; - -assign trunc_ln78_26_fu_1056_p4 = {{fifo_aBvec_3_dout[145:114]}}; - -assign trunc_ln78_27_fu_1066_p4 = {{fifo_aBvec_3_dout[177:146]}}; - -assign trunc_ln78_28_fu_1076_p4 = {{fifo_aBvec_3_dout[209:178]}}; - -assign trunc_ln78_29_fu_1086_p4 = {{fifo_aBvec_3_dout[241:210]}}; - -assign trunc_ln78_2_fu_662_p4 = {{fifo_aBvec_0_dout[113:82]}}; - -assign trunc_ln78_30_fu_1096_p4 = {{fifo_aBvec_3_dout[273:242]}}; - -assign trunc_ln78_3_fu_672_p4 = {{fifo_aBvec_0_dout[145:114]}}; - -assign trunc_ln78_4_fu_682_p4 = {{fifo_aBvec_0_dout[177:146]}}; - -assign trunc_ln78_5_fu_692_p4 = {{fifo_aBvec_0_dout[209:178]}}; - -assign trunc_ln78_6_fu_702_p4 = {{fifo_aBvec_0_dout[241:210]}}; - -assign trunc_ln78_7_fu_712_p4 = {{fifo_aBvec_0_dout[273:242]}}; - -assign trunc_ln78_8_fu_770_p4 = {{fifo_aBvec_1_dout[49:18]}}; - -assign trunc_ln78_9_fu_780_p4 = {{fifo_aBvec_1_dout[81:50]}}; - -assign trunc_ln78_s_fu_790_p4 = {{fifo_aBvec_1_dout[113:82]}}; - -endmodule //PEG_Cmtx_PEG_Cmtx_Pipeline_computation diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_PEG_Cmtx_Pipeline_init_C.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_PEG_Cmtx_Pipeline_init_C.v deleted file mode 100644 index 6409e288..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_PEG_Cmtx_Pipeline_init_C.v +++ /dev/null @@ -1,696 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module PEG_Cmtx_PEG_Cmtx_Pipeline_init_C ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - trunc_ln, - local_C_V_15_address1, - local_C_V_15_ce1, - local_C_V_15_we1, - local_C_V_15_d1, - local_C_V_14_address1, - local_C_V_14_ce1, - local_C_V_14_we1, - local_C_V_14_d1, - local_C_V_13_address1, - local_C_V_13_ce1, - local_C_V_13_we1, - local_C_V_13_d1, - local_C_V_12_address1, - local_C_V_12_ce1, - local_C_V_12_we1, - local_C_V_12_d1, - local_C_V_11_address1, - local_C_V_11_ce1, - local_C_V_11_we1, - local_C_V_11_d1, - local_C_V_10_address1, - local_C_V_10_ce1, - local_C_V_10_we1, - local_C_V_10_d1, - local_C_V_9_address1, - local_C_V_9_ce1, - local_C_V_9_we1, - local_C_V_9_d1, - local_C_V_8_address1, - local_C_V_8_ce1, - local_C_V_8_we1, - local_C_V_8_d1, - local_C_V_7_address1, - local_C_V_7_ce1, - local_C_V_7_we1, - local_C_V_7_d1, - local_C_V_6_address1, - local_C_V_6_ce1, - local_C_V_6_we1, - local_C_V_6_d1, - local_C_V_5_address1, - local_C_V_5_ce1, - local_C_V_5_we1, - local_C_V_5_d1, - local_C_V_4_address1, - local_C_V_4_ce1, - local_C_V_4_we1, - local_C_V_4_d1, - local_C_V_3_address1, - local_C_V_3_ce1, - local_C_V_3_we1, - local_C_V_3_d1, - local_C_V_2_address1, - local_C_V_2_ce1, - local_C_V_2_we1, - local_C_V_2_d1, - local_C_V_1_address1, - local_C_V_1_ce1, - local_C_V_1_we1, - local_C_V_1_d1, - local_C_V_address1, - local_C_V_ce1, - local_C_V_we1, - local_C_V_d1 -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [25:0] trunc_ln; -output [12:0] local_C_V_15_address1; -output local_C_V_15_ce1; -output local_C_V_15_we1; -output [63:0] local_C_V_15_d1; -output [12:0] local_C_V_14_address1; -output local_C_V_14_ce1; -output local_C_V_14_we1; -output [63:0] local_C_V_14_d1; -output [12:0] local_C_V_13_address1; -output local_C_V_13_ce1; -output local_C_V_13_we1; -output [63:0] local_C_V_13_d1; -output [12:0] local_C_V_12_address1; -output local_C_V_12_ce1; -output local_C_V_12_we1; -output [63:0] local_C_V_12_d1; -output [12:0] local_C_V_11_address1; -output local_C_V_11_ce1; -output local_C_V_11_we1; -output [63:0] local_C_V_11_d1; -output [12:0] local_C_V_10_address1; -output local_C_V_10_ce1; -output local_C_V_10_we1; -output [63:0] local_C_V_10_d1; -output [12:0] local_C_V_9_address1; -output local_C_V_9_ce1; -output local_C_V_9_we1; -output [63:0] local_C_V_9_d1; -output [12:0] local_C_V_8_address1; -output local_C_V_8_ce1; -output local_C_V_8_we1; -output [63:0] local_C_V_8_d1; -output [12:0] local_C_V_7_address1; -output local_C_V_7_ce1; -output local_C_V_7_we1; -output [63:0] local_C_V_7_d1; -output [12:0] local_C_V_6_address1; -output local_C_V_6_ce1; -output local_C_V_6_we1; -output [63:0] local_C_V_6_d1; -output [12:0] local_C_V_5_address1; -output local_C_V_5_ce1; -output local_C_V_5_we1; -output [63:0] local_C_V_5_d1; -output [12:0] local_C_V_4_address1; -output local_C_V_4_ce1; -output local_C_V_4_we1; -output [63:0] local_C_V_4_d1; -output [12:0] local_C_V_3_address1; -output local_C_V_3_ce1; -output local_C_V_3_we1; -output [63:0] local_C_V_3_d1; -output [12:0] local_C_V_2_address1; -output local_C_V_2_ce1; -output local_C_V_2_we1; -output [63:0] local_C_V_2_d1; -output [12:0] local_C_V_1_address1; -output local_C_V_1_ce1; -output local_C_V_1_we1; -output [63:0] local_C_V_1_d1; -output [12:0] local_C_V_address1; -output local_C_V_ce1; -output local_C_V_we1; -output [63:0] local_C_V_d1; - -reg ap_idle; -reg local_C_V_15_ce1; -reg local_C_V_15_we1; -reg local_C_V_14_ce1; -reg local_C_V_14_we1; -reg local_C_V_13_ce1; -reg local_C_V_13_we1; -reg local_C_V_12_ce1; -reg local_C_V_12_we1; -reg local_C_V_11_ce1; -reg local_C_V_11_we1; -reg local_C_V_10_ce1; -reg local_C_V_10_we1; -reg local_C_V_9_ce1; -reg local_C_V_9_we1; -reg local_C_V_8_ce1; -reg local_C_V_8_we1; -reg local_C_V_7_ce1; -reg local_C_V_7_we1; -reg local_C_V_6_ce1; -reg local_C_V_6_we1; -reg local_C_V_5_ce1; -reg local_C_V_5_we1; -reg local_C_V_4_ce1; -reg local_C_V_4_we1; -reg local_C_V_3_ce1; -reg local_C_V_3_we1; -reg local_C_V_2_ce1; -reg local_C_V_2_we1; -reg local_C_V_1_ce1; -reg local_C_V_1_we1; -reg local_C_V_ce1; -reg local_C_V_we1; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -wire ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln237_fu_378_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -reg [13:0] i_3_reg_421; -wire ap_block_pp0_stage0_11001; -wire [63:0] zext_ln237_fu_395_p1; -wire ap_block_pp0_stage0; -reg [13:0] i_fu_68; -wire [13:0] add_ln237_fu_384_p2; -wire ap_loop_init; -reg [13:0] ap_sig_allocacmp_i_3; -wire [25:0] zext_ln237_1_fu_374_p1; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -PEG_Cmtx_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if (((icmp_ln237_fu_378_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin - i_fu_68 <= add_ln237_fu_384_p2; - end else if ((ap_loop_init == 1'b1)) begin - i_fu_68 <= 14'd0; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - i_3_reg_421 <= ap_sig_allocacmp_i_3; - end -end - -always @ (*) begin - if (((icmp_ln237_fu_378_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (ap_start_int == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1))) begin - ap_sig_allocacmp_i_3 = 14'd0; - end else begin - ap_sig_allocacmp_i_3 = i_fu_68; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_10_ce1 = 1'b1; - end else begin - local_C_V_10_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_10_we1 = 1'b1; - end else begin - local_C_V_10_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_11_ce1 = 1'b1; - end else begin - local_C_V_11_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_11_we1 = 1'b1; - end else begin - local_C_V_11_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_12_ce1 = 1'b1; - end else begin - local_C_V_12_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_12_we1 = 1'b1; - end else begin - local_C_V_12_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_13_ce1 = 1'b1; - end else begin - local_C_V_13_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_13_we1 = 1'b1; - end else begin - local_C_V_13_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_14_ce1 = 1'b1; - end else begin - local_C_V_14_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_14_we1 = 1'b1; - end else begin - local_C_V_14_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_15_ce1 = 1'b1; - end else begin - local_C_V_15_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_15_we1 = 1'b1; - end else begin - local_C_V_15_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_1_ce1 = 1'b1; - end else begin - local_C_V_1_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_1_we1 = 1'b1; - end else begin - local_C_V_1_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_2_ce1 = 1'b1; - end else begin - local_C_V_2_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_2_we1 = 1'b1; - end else begin - local_C_V_2_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_3_ce1 = 1'b1; - end else begin - local_C_V_3_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_3_we1 = 1'b1; - end else begin - local_C_V_3_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_4_ce1 = 1'b1; - end else begin - local_C_V_4_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_4_we1 = 1'b1; - end else begin - local_C_V_4_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_5_ce1 = 1'b1; - end else begin - local_C_V_5_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_5_we1 = 1'b1; - end else begin - local_C_V_5_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_6_ce1 = 1'b1; - end else begin - local_C_V_6_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_6_we1 = 1'b1; - end else begin - local_C_V_6_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_7_ce1 = 1'b1; - end else begin - local_C_V_7_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_7_we1 = 1'b1; - end else begin - local_C_V_7_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_8_ce1 = 1'b1; - end else begin - local_C_V_8_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_8_we1 = 1'b1; - end else begin - local_C_V_8_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_9_ce1 = 1'b1; - end else begin - local_C_V_9_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_9_we1 = 1'b1; - end else begin - local_C_V_9_we1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_ce1 = 1'b1; - end else begin - local_C_V_ce1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_we1 = 1'b1; - end else begin - local_C_V_we1 = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign add_ln237_fu_384_p2 = (ap_sig_allocacmp_i_3 + 14'd1); - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -assign icmp_ln237_fu_378_p2 = (($signed(zext_ln237_1_fu_374_p1) < $signed(trunc_ln)) ? 1'b1 : 1'b0); - -assign local_C_V_10_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_10_d1 = 64'd0; - -assign local_C_V_11_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_11_d1 = 64'd0; - -assign local_C_V_12_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_12_d1 = 64'd0; - -assign local_C_V_13_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_13_d1 = 64'd0; - -assign local_C_V_14_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_14_d1 = 64'd0; - -assign local_C_V_15_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_15_d1 = 64'd0; - -assign local_C_V_1_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_1_d1 = 64'd0; - -assign local_C_V_2_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_2_d1 = 64'd0; - -assign local_C_V_3_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_3_d1 = 64'd0; - -assign local_C_V_4_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_4_d1 = 64'd0; - -assign local_C_V_5_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_5_d1 = 64'd0; - -assign local_C_V_6_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_6_d1 = 64'd0; - -assign local_C_V_7_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_7_d1 = 64'd0; - -assign local_C_V_8_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_8_d1 = 64'd0; - -assign local_C_V_9_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_9_d1 = 64'd0; - -assign local_C_V_address1 = zext_ln237_fu_395_p1; - -assign local_C_V_d1 = 64'd0; - -assign zext_ln237_1_fu_374_p1 = ap_sig_allocacmp_i_3; - -assign zext_ln237_fu_395_p1 = i_3_reg_421; - -endmodule //PEG_Cmtx_PEG_Cmtx_Pipeline_init_C diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_PEG_Cmtx_Pipeline_write_C_outer.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_PEG_Cmtx_Pipeline_write_C_outer.v deleted file mode 100644 index b2aebcf5..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_PEG_Cmtx_Pipeline_write_C_outer.v +++ /dev/null @@ -1,671 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module PEG_Cmtx_PEG_Cmtx_Pipeline_write_C_outer ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_C_out_din, - fifo_C_out_full_n, - fifo_C_out_write, - num_v_out, - local_C_V_address0, - local_C_V_ce0, - local_C_V_q0, - local_C_V_4_address0, - local_C_V_4_ce0, - local_C_V_4_q0, - local_C_V_8_address0, - local_C_V_8_ce0, - local_C_V_8_q0, - local_C_V_12_address0, - local_C_V_12_ce0, - local_C_V_12_q0, - local_C_V_1_address0, - local_C_V_1_ce0, - local_C_V_1_q0, - local_C_V_5_address0, - local_C_V_5_ce0, - local_C_V_5_q0, - local_C_V_9_address0, - local_C_V_9_ce0, - local_C_V_9_q0, - local_C_V_13_address0, - local_C_V_13_ce0, - local_C_V_13_q0, - local_C_V_2_address0, - local_C_V_2_ce0, - local_C_V_2_q0, - local_C_V_6_address0, - local_C_V_6_ce0, - local_C_V_6_q0, - local_C_V_10_address0, - local_C_V_10_ce0, - local_C_V_10_q0, - local_C_V_14_address0, - local_C_V_14_ce0, - local_C_V_14_q0, - local_C_V_3_address0, - local_C_V_3_ce0, - local_C_V_3_q0, - local_C_V_7_address0, - local_C_V_7_ce0, - local_C_V_7_q0, - local_C_V_11_address0, - local_C_V_11_ce0, - local_C_V_11_q0, - local_C_V_15_address0, - local_C_V_15_ce0, - local_C_V_15_q0 -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -output [256:0] fifo_C_out_din; -input fifo_C_out_full_n; -output fifo_C_out_write; -input [27:0] num_v_out; -output [12:0] local_C_V_address0; -output local_C_V_ce0; -input [63:0] local_C_V_q0; -output [12:0] local_C_V_4_address0; -output local_C_V_4_ce0; -input [63:0] local_C_V_4_q0; -output [12:0] local_C_V_8_address0; -output local_C_V_8_ce0; -input [63:0] local_C_V_8_q0; -output [12:0] local_C_V_12_address0; -output local_C_V_12_ce0; -input [63:0] local_C_V_12_q0; -output [12:0] local_C_V_1_address0; -output local_C_V_1_ce0; -input [63:0] local_C_V_1_q0; -output [12:0] local_C_V_5_address0; -output local_C_V_5_ce0; -input [63:0] local_C_V_5_q0; -output [12:0] local_C_V_9_address0; -output local_C_V_9_ce0; -input [63:0] local_C_V_9_q0; -output [12:0] local_C_V_13_address0; -output local_C_V_13_ce0; -input [63:0] local_C_V_13_q0; -output [12:0] local_C_V_2_address0; -output local_C_V_2_ce0; -input [63:0] local_C_V_2_q0; -output [12:0] local_C_V_6_address0; -output local_C_V_6_ce0; -input [63:0] local_C_V_6_q0; -output [12:0] local_C_V_10_address0; -output local_C_V_10_ce0; -input [63:0] local_C_V_10_q0; -output [12:0] local_C_V_14_address0; -output local_C_V_14_ce0; -input [63:0] local_C_V_14_q0; -output [12:0] local_C_V_3_address0; -output local_C_V_3_ce0; -input [63:0] local_C_V_3_q0; -output [12:0] local_C_V_7_address0; -output local_C_V_7_ce0; -input [63:0] local_C_V_7_q0; -output [12:0] local_C_V_11_address0; -output local_C_V_11_ce0; -input [63:0] local_C_V_11_q0; -output [12:0] local_C_V_15_address0; -output local_C_V_15_ce0; -input [63:0] local_C_V_15_q0; - -reg ap_idle; -reg fifo_C_out_write; -reg local_C_V_ce0; -reg local_C_V_4_ce0; -reg local_C_V_8_ce0; -reg local_C_V_12_ce0; -reg local_C_V_1_ce0; -reg local_C_V_5_ce0; -reg local_C_V_9_ce0; -reg local_C_V_13_ce0; -reg local_C_V_2_ce0; -reg local_C_V_6_ce0; -reg local_C_V_10_ce0; -reg local_C_V_14_ce0; -reg local_C_V_3_ce0; -reg local_C_V_7_ce0; -reg local_C_V_11_ce0; -reg local_C_V_15_ce0; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_enable_reg_pp0_iter2; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -reg ap_block_state3_pp0_stage0_iter2; -reg ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln278_fu_338_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -reg fifo_C_out_blk_n; -wire ap_block_pp0_stage0; -reg ap_block_pp0_stage0_11001; -wire [63:0] u_64_V_fu_392_p6; -reg [63:0] u_64_V_reg_630; -wire [63:0] u_64_V_1_fu_406_p6; -reg [63:0] u_64_V_1_reg_635; -wire [63:0] u_64_V_2_fu_420_p6; -reg [63:0] u_64_V_2_reg_640; -wire [63:0] u_64_V_3_fu_434_p6; -reg [63:0] u_64_V_3_reg_645; -wire [63:0] idxprom1431_fu_360_p1; -reg [26:0] i_fu_92; -wire [26:0] i_2_fu_344_p2; -wire ap_loop_init; -reg [26:0] ap_sig_allocacmp_i_1; -reg [31:0] c_idx_fu_96; -wire [31:0] c_idx_1_fu_508_p3; -reg ap_block_pp0_stage0_01001; -wire [27:0] zext_ln278_fu_334_p1; -wire [12:0] tmp_4_fu_350_p4; -wire [1:0] trunc_ln283_fu_388_p1; -wire [0:0] icmp_ln287_1_fu_454_p2; -wire [0:0] icmp_ln287_fu_448_p2; -wire [0:0] or_ln287_fu_468_p2; -wire [31:0] select_ln287_fu_460_p3; -wire [0:0] icmp_ln287_3_fu_488_p2; -wire [0:0] icmp_ln287_2_fu_482_p2; -wire [0:0] empty_57_fu_502_p2; -wire [31:0] empty_fu_494_p3; -wire [31:0] select_ln287_1_fu_474_p3; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg ap_loop_exit_ready_pp0_iter1_reg; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_enable_reg_pp0_iter2 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -PEG_Cmtx_mux_42_64_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 64 ), - .din1_WIDTH( 64 ), - .din2_WIDTH( 64 ), - .din3_WIDTH( 64 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 64 )) -mux_42_64_1_1_U73( - .din0(local_C_V_q0), - .din1(local_C_V_4_q0), - .din2(local_C_V_8_q0), - .din3(local_C_V_12_q0), - .din4(trunc_ln283_fu_388_p1), - .dout(u_64_V_fu_392_p6) -); - -PEG_Cmtx_mux_42_64_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 64 ), - .din1_WIDTH( 64 ), - .din2_WIDTH( 64 ), - .din3_WIDTH( 64 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 64 )) -mux_42_64_1_1_U74( - .din0(local_C_V_1_q0), - .din1(local_C_V_5_q0), - .din2(local_C_V_9_q0), - .din3(local_C_V_13_q0), - .din4(trunc_ln283_fu_388_p1), - .dout(u_64_V_1_fu_406_p6) -); - -PEG_Cmtx_mux_42_64_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 64 ), - .din1_WIDTH( 64 ), - .din2_WIDTH( 64 ), - .din3_WIDTH( 64 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 64 )) -mux_42_64_1_1_U75( - .din0(local_C_V_2_q0), - .din1(local_C_V_6_q0), - .din2(local_C_V_10_q0), - .din3(local_C_V_14_q0), - .din4(trunc_ln283_fu_388_p1), - .dout(u_64_V_2_fu_420_p6) -); - -PEG_Cmtx_mux_42_64_1_1 #( - .ID( 1 ), - .NUM_STAGE( 1 ), - .din0_WIDTH( 64 ), - .din1_WIDTH( 64 ), - .din2_WIDTH( 64 ), - .din3_WIDTH( 64 ), - .din4_WIDTH( 2 ), - .dout_WIDTH( 64 )) -mux_42_64_1_1_U76( - .din0(local_C_V_3_q0), - .din1(local_C_V_7_q0), - .din2(local_C_V_11_q0), - .din3(local_C_V_15_q0), - .din4(trunc_ln283_fu_388_p1), - .dout(u_64_V_3_fu_434_p6) -); - -PEG_Cmtx_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter1_reg == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter2 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - c_idx_fu_96 <= 32'd0; - end else if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin - c_idx_fu_96 <= c_idx_1_fu_508_p3; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if (((icmp_ln278_fu_338_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin - i_fu_92 <= i_2_fu_344_p2; - end else if ((ap_loop_init == 1'b1)) begin - i_fu_92 <= 27'd0; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_loop_exit_ready_pp0_iter1_reg <= ap_loop_exit_ready; - u_64_V_1_reg_635 <= u_64_V_1_fu_406_p6; - u_64_V_2_reg_640 <= u_64_V_2_fu_420_p6; - u_64_V_3_reg_645 <= u_64_V_3_fu_434_p6; - u_64_V_reg_630 <= u_64_V_fu_392_p6; - end -end - -always @ (*) begin - if (((icmp_ln278_fu_338_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter1_reg == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_start_int == 1'b0) & (ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_loop_init == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_sig_allocacmp_i_1 = 27'd0; - end else begin - ap_sig_allocacmp_i_1 = i_fu_92; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin - fifo_C_out_blk_n = fifo_C_out_full_n; - end else begin - fifo_C_out_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin - fifo_C_out_write = 1'b1; - end else begin - fifo_C_out_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_10_ce0 = 1'b1; - end else begin - local_C_V_10_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_11_ce0 = 1'b1; - end else begin - local_C_V_11_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_12_ce0 = 1'b1; - end else begin - local_C_V_12_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_13_ce0 = 1'b1; - end else begin - local_C_V_13_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_14_ce0 = 1'b1; - end else begin - local_C_V_14_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_15_ce0 = 1'b1; - end else begin - local_C_V_15_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_1_ce0 = 1'b1; - end else begin - local_C_V_1_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_2_ce0 = 1'b1; - end else begin - local_C_V_2_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_3_ce0 = 1'b1; - end else begin - local_C_V_3_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_4_ce0 = 1'b1; - end else begin - local_C_V_4_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_5_ce0 = 1'b1; - end else begin - local_C_V_5_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_6_ce0 = 1'b1; - end else begin - local_C_V_6_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_7_ce0 = 1'b1; - end else begin - local_C_V_7_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_8_ce0 = 1'b1; - end else begin - local_C_V_8_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_9_ce0 = 1'b1; - end else begin - local_C_V_9_ce0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - local_C_V_ce0 = 1'b1; - end else begin - local_C_V_ce0 = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage0_01001 = ((fifo_C_out_full_n == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)); -end - -always @ (*) begin - ap_block_pp0_stage0_11001 = ((fifo_C_out_full_n == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)); -end - -always @ (*) begin - ap_block_pp0_stage0_subdone = ((fifo_C_out_full_n == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)); -end - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_state3_pp0_stage0_iter2 = (fifo_C_out_full_n == 1'b0); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -assign c_idx_1_fu_508_p3 = ((empty_57_fu_502_p2[0:0] == 1'b1) ? empty_fu_494_p3 : select_ln287_1_fu_474_p3); - -assign empty_57_fu_502_p2 = (icmp_ln287_3_fu_488_p2 | icmp_ln287_2_fu_482_p2); - -assign empty_fu_494_p3 = ((icmp_ln287_3_fu_488_p2[0:0] == 1'b1) ? 32'd0 : 32'd1); - -assign fifo_C_out_din = {{{{{{{{1'd0}, {u_64_V_3_reg_645}}}, {u_64_V_2_reg_640}}}, {u_64_V_1_reg_635}}}, {u_64_V_reg_630}}; - -assign i_2_fu_344_p2 = (ap_sig_allocacmp_i_1 + 27'd1); - -assign icmp_ln278_fu_338_p2 = (($signed(zext_ln278_fu_334_p1) < $signed(num_v_out)) ? 1'b1 : 1'b0); - -assign icmp_ln287_1_fu_454_p2 = ((c_idx_fu_96 == 32'd1) ? 1'b1 : 1'b0); - -assign icmp_ln287_2_fu_482_p2 = ((c_idx_fu_96 == 32'd2) ? 1'b1 : 1'b0); - -assign icmp_ln287_3_fu_488_p2 = ((c_idx_fu_96 == 32'd3) ? 1'b1 : 1'b0); - -assign icmp_ln287_fu_448_p2 = ((c_idx_fu_96 == 32'd0) ? 1'b1 : 1'b0); - -assign idxprom1431_fu_360_p1 = tmp_4_fu_350_p4; - -assign local_C_V_10_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_11_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_12_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_13_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_14_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_15_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_1_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_2_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_3_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_4_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_5_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_6_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_7_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_8_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_9_address0 = idxprom1431_fu_360_p1; - -assign local_C_V_address0 = idxprom1431_fu_360_p1; - -assign or_ln287_fu_468_p2 = (icmp_ln287_fu_448_p2 | icmp_ln287_1_fu_454_p2); - -assign select_ln287_1_fu_474_p3 = ((or_ln287_fu_468_p2[0:0] == 1'b1) ? select_ln287_fu_460_p3 : c_idx_fu_96); - -assign select_ln287_fu_460_p3 = ((icmp_ln287_1_fu_454_p2[0:0] == 1'b1) ? 32'd3 : 32'd2); - -assign tmp_4_fu_350_p4 = {{ap_sig_allocacmp_i_1[14:2]}}; - -assign trunc_ln283_fu_388_p1 = c_idx_fu_96[1:0]; - -assign zext_ln278_fu_334_p1 = ap_sig_allocacmp_i_1; - -endmodule //PEG_Cmtx_PEG_Cmtx_Pipeline_write_C_outer diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1.v deleted file mode 100644 index fca405e6..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1.v +++ /dev/null @@ -1,76 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1ns/1ps - -module PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1 -#(parameter - ID = 1, - NUM_STAGE = 3, - din0_WIDTH = 32, - din1_WIDTH = 32, - dout_WIDTH = 32 -)( - input wire clk, - input wire reset, - input wire ce, - input wire [din0_WIDTH-1:0] din0, - input wire [din1_WIDTH-1:0] din1, - output wire [dout_WIDTH-1:0] dout -); -//------------------------Local signal------------------- -wire aclk; -wire aclken; -wire a_tvalid; -wire [31:0] a_tdata; -wire b_tvalid; -wire [31:0] b_tdata; -wire r_tvalid; -wire [31:0] r_tdata; -reg [din0_WIDTH-1:0] din0_buf1; -reg [din1_WIDTH-1:0] din1_buf1; -reg ce_r; -wire [dout_WIDTH-1:0] dout_i; -reg [dout_WIDTH-1:0] dout_r; -//------------------------Instantiation------------------ -PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip_u ( - .aclk ( aclk ), - .aclken ( aclken ), - .s_axis_a_tvalid ( a_tvalid ), - .s_axis_a_tdata ( a_tdata ), - .s_axis_b_tvalid ( b_tvalid ), - .s_axis_b_tdata ( b_tdata ), - .m_axis_result_tvalid ( r_tvalid ), - .m_axis_result_tdata ( r_tdata ) -); -//------------------------Body--------------------------- -assign aclk = clk; -assign aclken = ce_r; -assign a_tvalid = 1'b1; -assign a_tdata = din0_buf1; -assign b_tvalid = 1'b1; -assign b_tdata = din1_buf1; -assign dout_i = r_tdata; - -always @(posedge clk) begin - if (ce) begin - din0_buf1 <= din0; - din1_buf1 <= din1; - end -end - -always @ (posedge clk) begin - ce_r <= ce; -end - -always @ (posedge clk) begin - if (ce_r) begin - dout_r <= dout_i; - end -end - -assign dout = ce_r?dout_i:dout_r; -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip.tcl b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip.tcl deleted file mode 100644 index 7340b7b7..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip.tcl +++ /dev/null @@ -1,45 +0,0 @@ -# BEGIN Vivado Commands -set vivado_ver [version -short] -set fpo_ver 7.1 -if {[regexp -nocase {2015\.1.*} $vivado_ver match]} { - set fpo_ver 7.0 -} -create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip -# BEGIN Vivado Commands -# BEGIN Vivado Parameters -set_property -dict [list CONFIG.a_precision_type Single \ - CONFIG.a_tuser_width 1 \ - CONFIG.add_sub_value Add \ - CONFIG.b_tuser_width 1 \ - CONFIG.c_a_exponent_width 8 \ - CONFIG.c_a_fraction_width 24 \ - CONFIG.c_compare_operation Programmable \ - CONFIG.c_has_divide_by_zero false \ - CONFIG.c_has_invalid_op false \ - CONFIG.c_has_overflow false \ - CONFIG.c_has_underflow false \ - CONFIG.c_latency 5 \ - CONFIG.c_mult_usage Full_Usage \ - CONFIG.c_optimization Speed_Optimized \ - CONFIG.c_rate 1 \ - CONFIG.c_result_exponent_width 8 \ - CONFIG.c_result_fraction_width 24 \ - CONFIG.component_name PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip \ - CONFIG.flow_control NonBlocking \ - CONFIG.has_a_tlast false \ - CONFIG.has_a_tuser false \ - CONFIG.has_aclken true \ - CONFIG.has_aresetn false \ - CONFIG.has_b_tlast false \ - CONFIG.has_b_tuser false \ - CONFIG.has_operation_tlast false \ - CONFIG.has_operation_tuser false \ - CONFIG.has_result_tready false \ - CONFIG.maximum_latency false \ - CONFIG.operation_tuser_width 1 \ - CONFIG.operation_type Add_Subtract \ - CONFIG.result_precision_type Single \ - CONFIG.result_tlast_behv Null] -objects [get_ips PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip] -quiet -# END Vivado Parameters -set_property generate_synth_checkpoint false [get_files PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip.xci] -generate_target {synthesis simulation} [get_files PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip.xci] diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_flow_control_loop_pipe_sequential_init.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_flow_control_loop_pipe_sequential_init.v deleted file mode 100644 index a4aae129..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_flow_control_loop_pipe_sequential_init.v +++ /dev/null @@ -1,104 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module PEG_Cmtx_flow_control_loop_pipe_sequential_init( - ap_clk, - ap_rst, - ap_start, - ap_ready, - ap_done, - ap_start_int, - ap_ready_int, - ap_done_int, - ap_continue_int, - ap_loop_init, - ap_loop_exit_ready, - ap_loop_exit_done -); - -input ap_clk; -input ap_rst; - -//Block level handshake with outside loop -input ap_start; -output ap_ready; -output ap_done; - -//Block level handshake with loop body -output ap_start_int; -input ap_ready_int; -input ap_done_int; -output ap_continue_int; - -//Init live in variables -output ap_loop_init; -wire ap_loop_init; -reg ap_loop_init_int; -reg ap_done; -reg ap_done_cache; - -//Exit signal from loop body -input ap_loop_exit_ready; -input ap_loop_exit_done; - -// power-on initialization -initial begin -#0 ap_loop_init_int = 1'b1; -#0 ap_done_cache = 1'b0; -end - -assign ap_start_int = ap_start; - -assign ap_continue_int = 1'b1; - -assign ap_ready = ap_loop_exit_ready; - -//ap_loop_init is valid for the first II -//of the first loop run so as to enable -//the init block ops which are pushed into -//the first state of the pipeline region -always @ (posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_loop_exit_done == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_ready_int == 1'b1) begin - ap_loop_init_int <= 1'b0; - end -end - -assign ap_loop_init = ap_loop_init_int & ap_start; - -// if no ap_continue port and current module is not top module, -// ap_done handshakes with ap_start. Internally, flow control sends out -// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle. -// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int -// is asserted, so DUT can start the next run -always @(posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_done_cache <= 1'b0; - end else if (ap_done_int == 1'b1) begin - ap_done_cache <= 1'b1; - end else if (ap_start_int == 1'b1) begin - ap_done_cache <= 1'b0; - end -end - -// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start -always @(*) -begin - if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W.v deleted file mode 100644 index e159c2b6..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W.v +++ /dev/null @@ -1,67 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== -`timescale 1 ns / 1 ps -module PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W ( - - address0, ce0, - - q0, - - address1, ce1, - d1, we1, - - - reset, clk); - -parameter DataWidth = 64; -parameter AddressWidth = 13; -parameter AddressRange = 8192; - -input[AddressWidth-1:0] address0; -input ce0; - -output reg[DataWidth-1:0] q0; - -input[AddressWidth-1:0] address1; -input ce1; -input[DataWidth-1:0] d1; -input we1; - - -input reset; -input clk; - -(* ram_style = "hls_ultra" , cascade_height = 1 *)reg [DataWidth-1:0] ram[0:AddressRange-1]; - - - - - - -always @(posedge clk) -begin - if (ce0) begin - q0 <= ram[address0]; - end -end - - - - -always @(posedge clk) -begin - if (ce1) begin - if (we1) - ram[address1] <= d1; - end -end - - - - - - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_mul_mul_16s_14ns_30_4_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_mul_mul_16s_14ns_30_4_1.v deleted file mode 100644 index 8e46d065..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_mul_mul_16s_14ns_30_4_1.v +++ /dev/null @@ -1,62 +0,0 @@ - -`timescale 1 ns / 1 ps - - module PEG_Cmtx_mul_mul_16s_14ns_30_4_1_DSP48_0(clk, rst, ce, a, b, p); -input clk; -input rst; -input ce; -input signed [16 - 1 : 0] a; -input [14 - 1 : 0] b; -output signed [30 - 1 : 0] p; - -reg signed [30 - 1 : 0] p_reg; - -reg signed [16 - 1 : 0] a_reg; -reg [14 - 1 : 0] b_reg; - -reg signed [30 - 1 : 0] p_reg_tmp; - -always @ (posedge clk) begin - if (ce) begin - a_reg <= a; - b_reg <= b; - p_reg_tmp <= a_reg * $signed({1'b0, b_reg}); - p_reg <= p_reg_tmp; - end -end - -assign p = p_reg; - -endmodule -`timescale 1 ns / 1 ps -module PEG_Cmtx_mul_mul_16s_14ns_30_4_1( - clk, - reset, - ce, - din0, - din1, - dout); - -parameter ID = 32'd1; -parameter NUM_STAGE = 32'd1; -parameter din0_WIDTH = 32'd1; -parameter din1_WIDTH = 32'd1; -parameter dout_WIDTH = 32'd1; -input clk; -input reset; -input ce; -input[din0_WIDTH - 1:0] din0; -input[din1_WIDTH - 1:0] din1; -output[dout_WIDTH - 1:0] dout; - - - -PEG_Cmtx_mul_mul_16s_14ns_30_4_1_DSP48_0 PEG_Cmtx_mul_mul_16s_14ns_30_4_1_DSP48_0_U( - .clk( clk ), - .rst( reset ), - .ce( ce ), - .a( din0 ), - .b( din1 ), - .p( dout )); - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_mux_42_64_1_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_mux_42_64_1_1.v deleted file mode 100644 index 42c71bc6..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/PEG_Cmtx_mux_42_64_1_1.v +++ /dev/null @@ -1,47 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1ns/1ps - -module PEG_Cmtx_mux_42_64_1_1 #( -parameter - ID = 0, - NUM_STAGE = 1, - din0_WIDTH = 32, - din1_WIDTH = 32, - din2_WIDTH = 32, - din3_WIDTH = 32, - din4_WIDTH = 32, - dout_WIDTH = 32 -)( - input [63 : 0] din0, - input [63 : 0] din1, - input [63 : 0] din2, - input [63 : 0] din3, - input [1 : 0] din4, - output [63 : 0] dout); - -// puts internal signals -wire [1 : 0] sel; -// level 1 signals -wire [63 : 0] mux_1_0; -wire [63 : 0] mux_1_1; -// level 2 signals -wire [63 : 0] mux_2_0; - -assign sel = din4; - -// Generate level 1 logic -assign mux_1_0 = (sel[0] == 0)? din0 : din1; -assign mux_1_1 = (sel[0] == 0)? din2 : din3; - -// Generate level 2 logic -assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1; - -// output logic -assign dout = mux_2_0; - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/Scatter_1_2.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/Scatter_1_2.v deleted file mode 100644 index 68ad072c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/Scatter_1_2.v +++ /dev/null @@ -1,237 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="Scatter_1_2_Scatter_1_2,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=6,HLS_SYN_LUT=67,HLS_VERSION=2022_2}" *) - -module Scatter_1_2 ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_in_s_dout, - fifo_in_s_empty_n, - fifo_in_s_read, - fifo_in_peek_dout, - fifo_in_peek_empty_n, - fifo_in_peek_read, - fifo_out_0_din, - fifo_out_0_full_n, - fifo_out_0_write, - fifo_out_1_din, - fifo_out_1_full_n, - fifo_out_1_write -); - -parameter ap_ST_fsm_state1 = 3'd1; -parameter ap_ST_fsm_state2 = 3'd2; -parameter ap_ST_fsm_state3 = 3'd4; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [512:0] fifo_in_s_dout; -input fifo_in_s_empty_n; -output fifo_in_s_read; -input [512:0] fifo_in_peek_dout; -input fifo_in_peek_empty_n; -output fifo_in_peek_read; -output [256:0] fifo_out_0_din; -input fifo_out_0_full_n; -output fifo_out_0_write; -output [256:0] fifo_out_1_din; -input fifo_out_1_full_n; -output fifo_out_1_write; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg fifo_in_s_read; -reg fifo_out_0_write; -reg fifo_out_1_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_start; -wire grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_done; -wire grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_idle; -wire grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_ready; -wire grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_in_s_read; -wire [256:0] grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_0_din; -wire grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_0_write; -wire [256:0] grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_1_din; -wire grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_1_write; -reg grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_start_reg; -wire ap_CS_fsm_state2; -wire ap_CS_fsm_state3; -reg [2:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 3'd1; -#0 grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_start_reg = 1'b0; -end - -Scatter_1_2_Scatter_1_2_Pipeline_VITIS_LOOP_405_1 grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_start), - .ap_done(grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_done), - .ap_idle(grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_idle), - .ap_ready(grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_ready), - .fifo_in_s_dout(fifo_in_s_dout), - .fifo_in_s_empty_n(fifo_in_s_empty_n), - .fifo_in_s_read(grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_in_s_read), - .fifo_out_0_din(grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_0_din), - .fifo_out_0_full_n(fifo_out_0_full_n), - .fifo_out_0_write(grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_0_write), - .fifo_out_1_din(grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_1_din), - .fifo_out_1_full_n(fifo_out_1_full_n), - .fifo_out_1_write(grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_1_write) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state2)) begin - grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_start_reg <= 1'b1; - end else if ((grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_ready == 1'b1)) begin - grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_start_reg <= 1'b0; - end - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if ((grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_done == 1'b0)) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -always @ (*) begin - if (((grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_in_s_read = grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_in_s_read; - end else begin - fifo_in_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_out_0_write = grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_0_write; - end else begin - fifo_out_0_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_out_1_write = grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_1_write; - end else begin - fifo_out_1_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state3; - end - ap_ST_fsm_state3 : begin - if (((grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign fifo_in_peek_read = 1'b0; - -assign fifo_out_0_din = grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_0_din; - -assign fifo_out_1_din = grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_fifo_out_1_din; - -assign grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_start = grp_Scatter_1_2_Pipeline_VITIS_LOOP_405_1_fu_66_ap_start_reg; - -endmodule //Scatter_1_2 diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/Scatter_1_2_Scatter_1_2_Pipeline_VITIS_LOOP_405_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/Scatter_1_2_Scatter_1_2_Pipeline_VITIS_LOOP_405_1.v deleted file mode 100644 index b8a7ae93..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/Scatter_1_2_Scatter_1_2_Pipeline_VITIS_LOOP_405_1.v +++ /dev/null @@ -1,173 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module Scatter_1_2_Scatter_1_2_Pipeline_VITIS_LOOP_405_1 ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_in_s_dout, - fifo_in_s_empty_n, - fifo_in_s_read, - fifo_out_0_din, - fifo_out_0_full_n, - fifo_out_0_write, - fifo_out_1_din, - fifo_out_1_full_n, - fifo_out_1_write -); - -parameter ap_ST_fsm_state1 = 2'd1; -parameter ap_ST_fsm_state2 = 2'd2; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [512:0] fifo_in_s_dout; -input fifo_in_s_empty_n; -output fifo_in_s_read; -output [256:0] fifo_out_0_din; -input fifo_out_0_full_n; -output fifo_out_0_write; -output [256:0] fifo_out_1_din; -input fifo_out_1_full_n; -output fifo_out_1_write; - -reg ap_done; -reg ap_idle; -reg fifo_in_s_read; -reg fifo_out_0_write; -reg fifo_out_1_write; - -(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire [0:0] tmp_nbreadreq_fu_42_p3; -wire ap_CS_fsm_state2; -wire [0:0] and_ln409_1_fu_92_p2; -wire [0:0] and_ln409_fu_86_p0; -wire [0:0] and_ln409_fu_86_p1; -wire [0:0] and_ln409_fu_86_p2; -wire [255:0] trunc_ln628_fu_102_p1; -wire [255:0] tmp_7_fu_115_p4; -reg [1:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 2'd1; -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln409_1_fu_92_p2) & (fifo_in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - fifo_in_s_read = 1'b1; - end else begin - fifo_in_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln409_1_fu_92_p2) & (fifo_out_0_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - fifo_out_0_write = 1'b1; - end else begin - fifo_out_0_write = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln409_1_fu_92_p2) & (fifo_out_1_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - fifo_out_1_write = 1'b1; - end else begin - fifo_out_1_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state2; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign and_ln409_1_fu_92_p2 = (tmp_nbreadreq_fu_42_p3 & and_ln409_fu_86_p2); - -assign and_ln409_fu_86_p0 = fifo_out_0_full_n; - -assign and_ln409_fu_86_p1 = fifo_out_1_full_n; - -assign and_ln409_fu_86_p2 = (and_ln409_fu_86_p1 & and_ln409_fu_86_p0); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_ready = 1'b0; - -assign fifo_out_0_din = {{1'd0}, {trunc_ln628_fu_102_p1}}; - -assign fifo_out_1_din = {{1'd0}, {tmp_7_fu_115_p4}}; - -assign tmp_7_fu_115_p4 = {{fifo_in_s_dout[511:256]}}; - -assign tmp_nbreadreq_fu_42_p3 = fifo_in_s_empty_n; - -assign trunc_ln628_fu_102_p1 = fifo_in_s_dout[255:0]; - -endmodule //Scatter_1_2_Scatter_1_2_Pipeline_VITIS_LOOP_405_1 diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/Sextans.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/Sextans.v deleted file mode 100644 index b877cee4..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/Sextans.v +++ /dev/null @@ -1,17991 +0,0 @@ -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO = "Sextans_Sextans,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.000000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=2332,HLS_SYN_LUT=4200,HLS_VERSION=2022_2}" *) - - -module Sextans -( - s_axi_control_AWVALID, - s_axi_control_AWREADY, - s_axi_control_AWADDR, - s_axi_control_WVALID, - s_axi_control_WREADY, - s_axi_control_WDATA, - s_axi_control_WSTRB, - s_axi_control_ARVALID, - s_axi_control_ARREADY, - s_axi_control_ARADDR, - s_axi_control_RVALID, - s_axi_control_RREADY, - s_axi_control_RDATA, - s_axi_control_RRESP, - s_axi_control_BVALID, - s_axi_control_BREADY, - s_axi_control_BRESP, - ap_clk, - ap_rst_n, - interrupt, - m_axi_edge_list_ch_0_ARADDR, - m_axi_edge_list_ch_0_ARBURST, - m_axi_edge_list_ch_0_ARCACHE, - m_axi_edge_list_ch_0_ARID, - m_axi_edge_list_ch_0_ARLEN, - m_axi_edge_list_ch_0_ARLOCK, - m_axi_edge_list_ch_0_ARPROT, - m_axi_edge_list_ch_0_ARQOS, - m_axi_edge_list_ch_0_ARREADY, - m_axi_edge_list_ch_0_ARSIZE, - m_axi_edge_list_ch_0_ARVALID, - m_axi_edge_list_ch_0_AWADDR, - m_axi_edge_list_ch_0_AWBURST, - m_axi_edge_list_ch_0_AWCACHE, - m_axi_edge_list_ch_0_AWID, - m_axi_edge_list_ch_0_AWLEN, - m_axi_edge_list_ch_0_AWLOCK, - m_axi_edge_list_ch_0_AWPROT, - m_axi_edge_list_ch_0_AWQOS, - m_axi_edge_list_ch_0_AWREADY, - m_axi_edge_list_ch_0_AWSIZE, - m_axi_edge_list_ch_0_AWVALID, - m_axi_edge_list_ch_0_BID, - m_axi_edge_list_ch_0_BREADY, - m_axi_edge_list_ch_0_BRESP, - m_axi_edge_list_ch_0_BVALID, - m_axi_edge_list_ch_0_RDATA, - m_axi_edge_list_ch_0_RID, - m_axi_edge_list_ch_0_RLAST, - m_axi_edge_list_ch_0_RREADY, - m_axi_edge_list_ch_0_RRESP, - m_axi_edge_list_ch_0_RVALID, - m_axi_edge_list_ch_0_WDATA, - m_axi_edge_list_ch_0_WLAST, - m_axi_edge_list_ch_0_WREADY, - m_axi_edge_list_ch_0_WSTRB, - m_axi_edge_list_ch_0_WVALID, - m_axi_edge_list_ch_1_ARADDR, - m_axi_edge_list_ch_1_ARBURST, - m_axi_edge_list_ch_1_ARCACHE, - m_axi_edge_list_ch_1_ARID, - m_axi_edge_list_ch_1_ARLEN, - m_axi_edge_list_ch_1_ARLOCK, - m_axi_edge_list_ch_1_ARPROT, - m_axi_edge_list_ch_1_ARQOS, - m_axi_edge_list_ch_1_ARREADY, - m_axi_edge_list_ch_1_ARSIZE, - m_axi_edge_list_ch_1_ARVALID, - m_axi_edge_list_ch_1_AWADDR, - m_axi_edge_list_ch_1_AWBURST, - m_axi_edge_list_ch_1_AWCACHE, - m_axi_edge_list_ch_1_AWID, - m_axi_edge_list_ch_1_AWLEN, - m_axi_edge_list_ch_1_AWLOCK, - m_axi_edge_list_ch_1_AWPROT, - m_axi_edge_list_ch_1_AWQOS, - m_axi_edge_list_ch_1_AWREADY, - m_axi_edge_list_ch_1_AWSIZE, - m_axi_edge_list_ch_1_AWVALID, - m_axi_edge_list_ch_1_BID, - m_axi_edge_list_ch_1_BREADY, - m_axi_edge_list_ch_1_BRESP, - m_axi_edge_list_ch_1_BVALID, - m_axi_edge_list_ch_1_RDATA, - m_axi_edge_list_ch_1_RID, - m_axi_edge_list_ch_1_RLAST, - m_axi_edge_list_ch_1_RREADY, - m_axi_edge_list_ch_1_RRESP, - m_axi_edge_list_ch_1_RVALID, - m_axi_edge_list_ch_1_WDATA, - m_axi_edge_list_ch_1_WLAST, - m_axi_edge_list_ch_1_WREADY, - m_axi_edge_list_ch_1_WSTRB, - m_axi_edge_list_ch_1_WVALID, - m_axi_edge_list_ch_2_ARADDR, - m_axi_edge_list_ch_2_ARBURST, - m_axi_edge_list_ch_2_ARCACHE, - m_axi_edge_list_ch_2_ARID, - m_axi_edge_list_ch_2_ARLEN, - m_axi_edge_list_ch_2_ARLOCK, - m_axi_edge_list_ch_2_ARPROT, - m_axi_edge_list_ch_2_ARQOS, - m_axi_edge_list_ch_2_ARREADY, - m_axi_edge_list_ch_2_ARSIZE, - m_axi_edge_list_ch_2_ARVALID, - m_axi_edge_list_ch_2_AWADDR, - m_axi_edge_list_ch_2_AWBURST, - m_axi_edge_list_ch_2_AWCACHE, - m_axi_edge_list_ch_2_AWID, - m_axi_edge_list_ch_2_AWLEN, - m_axi_edge_list_ch_2_AWLOCK, - m_axi_edge_list_ch_2_AWPROT, - m_axi_edge_list_ch_2_AWQOS, - m_axi_edge_list_ch_2_AWREADY, - m_axi_edge_list_ch_2_AWSIZE, - m_axi_edge_list_ch_2_AWVALID, - m_axi_edge_list_ch_2_BID, - m_axi_edge_list_ch_2_BREADY, - m_axi_edge_list_ch_2_BRESP, - m_axi_edge_list_ch_2_BVALID, - m_axi_edge_list_ch_2_RDATA, - m_axi_edge_list_ch_2_RID, - m_axi_edge_list_ch_2_RLAST, - m_axi_edge_list_ch_2_RREADY, - m_axi_edge_list_ch_2_RRESP, - m_axi_edge_list_ch_2_RVALID, - m_axi_edge_list_ch_2_WDATA, - m_axi_edge_list_ch_2_WLAST, - m_axi_edge_list_ch_2_WREADY, - m_axi_edge_list_ch_2_WSTRB, - m_axi_edge_list_ch_2_WVALID, - m_axi_edge_list_ch_3_ARADDR, - m_axi_edge_list_ch_3_ARBURST, - m_axi_edge_list_ch_3_ARCACHE, - m_axi_edge_list_ch_3_ARID, - m_axi_edge_list_ch_3_ARLEN, - m_axi_edge_list_ch_3_ARLOCK, - m_axi_edge_list_ch_3_ARPROT, - m_axi_edge_list_ch_3_ARQOS, - m_axi_edge_list_ch_3_ARREADY, - m_axi_edge_list_ch_3_ARSIZE, - m_axi_edge_list_ch_3_ARVALID, - m_axi_edge_list_ch_3_AWADDR, - m_axi_edge_list_ch_3_AWBURST, - m_axi_edge_list_ch_3_AWCACHE, - m_axi_edge_list_ch_3_AWID, - m_axi_edge_list_ch_3_AWLEN, - m_axi_edge_list_ch_3_AWLOCK, - m_axi_edge_list_ch_3_AWPROT, - m_axi_edge_list_ch_3_AWQOS, - m_axi_edge_list_ch_3_AWREADY, - m_axi_edge_list_ch_3_AWSIZE, - m_axi_edge_list_ch_3_AWVALID, - m_axi_edge_list_ch_3_BID, - m_axi_edge_list_ch_3_BREADY, - m_axi_edge_list_ch_3_BRESP, - m_axi_edge_list_ch_3_BVALID, - m_axi_edge_list_ch_3_RDATA, - m_axi_edge_list_ch_3_RID, - m_axi_edge_list_ch_3_RLAST, - m_axi_edge_list_ch_3_RREADY, - m_axi_edge_list_ch_3_RRESP, - m_axi_edge_list_ch_3_RVALID, - m_axi_edge_list_ch_3_WDATA, - m_axi_edge_list_ch_3_WLAST, - m_axi_edge_list_ch_3_WREADY, - m_axi_edge_list_ch_3_WSTRB, - m_axi_edge_list_ch_3_WVALID, - m_axi_edge_list_ch_4_ARADDR, - m_axi_edge_list_ch_4_ARBURST, - m_axi_edge_list_ch_4_ARCACHE, - m_axi_edge_list_ch_4_ARID, - m_axi_edge_list_ch_4_ARLEN, - m_axi_edge_list_ch_4_ARLOCK, - m_axi_edge_list_ch_4_ARPROT, - m_axi_edge_list_ch_4_ARQOS, - m_axi_edge_list_ch_4_ARREADY, - m_axi_edge_list_ch_4_ARSIZE, - m_axi_edge_list_ch_4_ARVALID, - m_axi_edge_list_ch_4_AWADDR, - m_axi_edge_list_ch_4_AWBURST, - m_axi_edge_list_ch_4_AWCACHE, - m_axi_edge_list_ch_4_AWID, - m_axi_edge_list_ch_4_AWLEN, - m_axi_edge_list_ch_4_AWLOCK, - m_axi_edge_list_ch_4_AWPROT, - m_axi_edge_list_ch_4_AWQOS, - m_axi_edge_list_ch_4_AWREADY, - m_axi_edge_list_ch_4_AWSIZE, - m_axi_edge_list_ch_4_AWVALID, - m_axi_edge_list_ch_4_BID, - m_axi_edge_list_ch_4_BREADY, - m_axi_edge_list_ch_4_BRESP, - m_axi_edge_list_ch_4_BVALID, - m_axi_edge_list_ch_4_RDATA, - m_axi_edge_list_ch_4_RID, - m_axi_edge_list_ch_4_RLAST, - m_axi_edge_list_ch_4_RREADY, - m_axi_edge_list_ch_4_RRESP, - m_axi_edge_list_ch_4_RVALID, - m_axi_edge_list_ch_4_WDATA, - m_axi_edge_list_ch_4_WLAST, - m_axi_edge_list_ch_4_WREADY, - m_axi_edge_list_ch_4_WSTRB, - m_axi_edge_list_ch_4_WVALID, - m_axi_edge_list_ch_5_ARADDR, - m_axi_edge_list_ch_5_ARBURST, - m_axi_edge_list_ch_5_ARCACHE, - m_axi_edge_list_ch_5_ARID, - m_axi_edge_list_ch_5_ARLEN, - m_axi_edge_list_ch_5_ARLOCK, - m_axi_edge_list_ch_5_ARPROT, - m_axi_edge_list_ch_5_ARQOS, - m_axi_edge_list_ch_5_ARREADY, - m_axi_edge_list_ch_5_ARSIZE, - m_axi_edge_list_ch_5_ARVALID, - m_axi_edge_list_ch_5_AWADDR, - m_axi_edge_list_ch_5_AWBURST, - m_axi_edge_list_ch_5_AWCACHE, - m_axi_edge_list_ch_5_AWID, - m_axi_edge_list_ch_5_AWLEN, - m_axi_edge_list_ch_5_AWLOCK, - m_axi_edge_list_ch_5_AWPROT, - m_axi_edge_list_ch_5_AWQOS, - m_axi_edge_list_ch_5_AWREADY, - m_axi_edge_list_ch_5_AWSIZE, - m_axi_edge_list_ch_5_AWVALID, - m_axi_edge_list_ch_5_BID, - m_axi_edge_list_ch_5_BREADY, - m_axi_edge_list_ch_5_BRESP, - m_axi_edge_list_ch_5_BVALID, - m_axi_edge_list_ch_5_RDATA, - m_axi_edge_list_ch_5_RID, - m_axi_edge_list_ch_5_RLAST, - m_axi_edge_list_ch_5_RREADY, - m_axi_edge_list_ch_5_RRESP, - m_axi_edge_list_ch_5_RVALID, - m_axi_edge_list_ch_5_WDATA, - m_axi_edge_list_ch_5_WLAST, - m_axi_edge_list_ch_5_WREADY, - m_axi_edge_list_ch_5_WSTRB, - m_axi_edge_list_ch_5_WVALID, - m_axi_edge_list_ch_6_ARADDR, - m_axi_edge_list_ch_6_ARBURST, - m_axi_edge_list_ch_6_ARCACHE, - m_axi_edge_list_ch_6_ARID, - m_axi_edge_list_ch_6_ARLEN, - m_axi_edge_list_ch_6_ARLOCK, - m_axi_edge_list_ch_6_ARPROT, - m_axi_edge_list_ch_6_ARQOS, - m_axi_edge_list_ch_6_ARREADY, - m_axi_edge_list_ch_6_ARSIZE, - m_axi_edge_list_ch_6_ARVALID, - m_axi_edge_list_ch_6_AWADDR, - m_axi_edge_list_ch_6_AWBURST, - m_axi_edge_list_ch_6_AWCACHE, - m_axi_edge_list_ch_6_AWID, - m_axi_edge_list_ch_6_AWLEN, - m_axi_edge_list_ch_6_AWLOCK, - m_axi_edge_list_ch_6_AWPROT, - m_axi_edge_list_ch_6_AWQOS, - m_axi_edge_list_ch_6_AWREADY, - m_axi_edge_list_ch_6_AWSIZE, - m_axi_edge_list_ch_6_AWVALID, - m_axi_edge_list_ch_6_BID, - m_axi_edge_list_ch_6_BREADY, - m_axi_edge_list_ch_6_BRESP, - m_axi_edge_list_ch_6_BVALID, - m_axi_edge_list_ch_6_RDATA, - m_axi_edge_list_ch_6_RID, - m_axi_edge_list_ch_6_RLAST, - m_axi_edge_list_ch_6_RREADY, - m_axi_edge_list_ch_6_RRESP, - m_axi_edge_list_ch_6_RVALID, - m_axi_edge_list_ch_6_WDATA, - m_axi_edge_list_ch_6_WLAST, - m_axi_edge_list_ch_6_WREADY, - m_axi_edge_list_ch_6_WSTRB, - m_axi_edge_list_ch_6_WVALID, - m_axi_edge_list_ch_7_ARADDR, - m_axi_edge_list_ch_7_ARBURST, - m_axi_edge_list_ch_7_ARCACHE, - m_axi_edge_list_ch_7_ARID, - m_axi_edge_list_ch_7_ARLEN, - m_axi_edge_list_ch_7_ARLOCK, - m_axi_edge_list_ch_7_ARPROT, - m_axi_edge_list_ch_7_ARQOS, - m_axi_edge_list_ch_7_ARREADY, - m_axi_edge_list_ch_7_ARSIZE, - m_axi_edge_list_ch_7_ARVALID, - m_axi_edge_list_ch_7_AWADDR, - m_axi_edge_list_ch_7_AWBURST, - m_axi_edge_list_ch_7_AWCACHE, - m_axi_edge_list_ch_7_AWID, - m_axi_edge_list_ch_7_AWLEN, - m_axi_edge_list_ch_7_AWLOCK, - m_axi_edge_list_ch_7_AWPROT, - m_axi_edge_list_ch_7_AWQOS, - m_axi_edge_list_ch_7_AWREADY, - m_axi_edge_list_ch_7_AWSIZE, - m_axi_edge_list_ch_7_AWVALID, - m_axi_edge_list_ch_7_BID, - m_axi_edge_list_ch_7_BREADY, - m_axi_edge_list_ch_7_BRESP, - m_axi_edge_list_ch_7_BVALID, - m_axi_edge_list_ch_7_RDATA, - m_axi_edge_list_ch_7_RID, - m_axi_edge_list_ch_7_RLAST, - m_axi_edge_list_ch_7_RREADY, - m_axi_edge_list_ch_7_RRESP, - m_axi_edge_list_ch_7_RVALID, - m_axi_edge_list_ch_7_WDATA, - m_axi_edge_list_ch_7_WLAST, - m_axi_edge_list_ch_7_WREADY, - m_axi_edge_list_ch_7_WSTRB, - m_axi_edge_list_ch_7_WVALID, - m_axi_mat_B_ch_0_ARADDR, - m_axi_mat_B_ch_0_ARBURST, - m_axi_mat_B_ch_0_ARCACHE, - m_axi_mat_B_ch_0_ARID, - m_axi_mat_B_ch_0_ARLEN, - m_axi_mat_B_ch_0_ARLOCK, - m_axi_mat_B_ch_0_ARPROT, - m_axi_mat_B_ch_0_ARQOS, - m_axi_mat_B_ch_0_ARREADY, - m_axi_mat_B_ch_0_ARSIZE, - m_axi_mat_B_ch_0_ARVALID, - m_axi_mat_B_ch_0_AWADDR, - m_axi_mat_B_ch_0_AWBURST, - m_axi_mat_B_ch_0_AWCACHE, - m_axi_mat_B_ch_0_AWID, - m_axi_mat_B_ch_0_AWLEN, - m_axi_mat_B_ch_0_AWLOCK, - m_axi_mat_B_ch_0_AWPROT, - m_axi_mat_B_ch_0_AWQOS, - m_axi_mat_B_ch_0_AWREADY, - m_axi_mat_B_ch_0_AWSIZE, - m_axi_mat_B_ch_0_AWVALID, - m_axi_mat_B_ch_0_BID, - m_axi_mat_B_ch_0_BREADY, - m_axi_mat_B_ch_0_BRESP, - m_axi_mat_B_ch_0_BVALID, - m_axi_mat_B_ch_0_RDATA, - m_axi_mat_B_ch_0_RID, - m_axi_mat_B_ch_0_RLAST, - m_axi_mat_B_ch_0_RREADY, - m_axi_mat_B_ch_0_RRESP, - m_axi_mat_B_ch_0_RVALID, - m_axi_mat_B_ch_0_WDATA, - m_axi_mat_B_ch_0_WLAST, - m_axi_mat_B_ch_0_WREADY, - m_axi_mat_B_ch_0_WSTRB, - m_axi_mat_B_ch_0_WVALID, - m_axi_mat_B_ch_1_ARADDR, - m_axi_mat_B_ch_1_ARBURST, - m_axi_mat_B_ch_1_ARCACHE, - m_axi_mat_B_ch_1_ARID, - m_axi_mat_B_ch_1_ARLEN, - m_axi_mat_B_ch_1_ARLOCK, - m_axi_mat_B_ch_1_ARPROT, - m_axi_mat_B_ch_1_ARQOS, - m_axi_mat_B_ch_1_ARREADY, - m_axi_mat_B_ch_1_ARSIZE, - m_axi_mat_B_ch_1_ARVALID, - m_axi_mat_B_ch_1_AWADDR, - m_axi_mat_B_ch_1_AWBURST, - m_axi_mat_B_ch_1_AWCACHE, - m_axi_mat_B_ch_1_AWID, - m_axi_mat_B_ch_1_AWLEN, - m_axi_mat_B_ch_1_AWLOCK, - m_axi_mat_B_ch_1_AWPROT, - m_axi_mat_B_ch_1_AWQOS, - m_axi_mat_B_ch_1_AWREADY, - m_axi_mat_B_ch_1_AWSIZE, - m_axi_mat_B_ch_1_AWVALID, - m_axi_mat_B_ch_1_BID, - m_axi_mat_B_ch_1_BREADY, - m_axi_mat_B_ch_1_BRESP, - m_axi_mat_B_ch_1_BVALID, - m_axi_mat_B_ch_1_RDATA, - m_axi_mat_B_ch_1_RID, - m_axi_mat_B_ch_1_RLAST, - m_axi_mat_B_ch_1_RREADY, - m_axi_mat_B_ch_1_RRESP, - m_axi_mat_B_ch_1_RVALID, - m_axi_mat_B_ch_1_WDATA, - m_axi_mat_B_ch_1_WLAST, - m_axi_mat_B_ch_1_WREADY, - m_axi_mat_B_ch_1_WSTRB, - m_axi_mat_B_ch_1_WVALID, - m_axi_mat_B_ch_2_ARADDR, - m_axi_mat_B_ch_2_ARBURST, - m_axi_mat_B_ch_2_ARCACHE, - m_axi_mat_B_ch_2_ARID, - m_axi_mat_B_ch_2_ARLEN, - m_axi_mat_B_ch_2_ARLOCK, - m_axi_mat_B_ch_2_ARPROT, - m_axi_mat_B_ch_2_ARQOS, - m_axi_mat_B_ch_2_ARREADY, - m_axi_mat_B_ch_2_ARSIZE, - m_axi_mat_B_ch_2_ARVALID, - m_axi_mat_B_ch_2_AWADDR, - m_axi_mat_B_ch_2_AWBURST, - m_axi_mat_B_ch_2_AWCACHE, - m_axi_mat_B_ch_2_AWID, - m_axi_mat_B_ch_2_AWLEN, - m_axi_mat_B_ch_2_AWLOCK, - m_axi_mat_B_ch_2_AWPROT, - m_axi_mat_B_ch_2_AWQOS, - m_axi_mat_B_ch_2_AWREADY, - m_axi_mat_B_ch_2_AWSIZE, - m_axi_mat_B_ch_2_AWVALID, - m_axi_mat_B_ch_2_BID, - m_axi_mat_B_ch_2_BREADY, - m_axi_mat_B_ch_2_BRESP, - m_axi_mat_B_ch_2_BVALID, - m_axi_mat_B_ch_2_RDATA, - m_axi_mat_B_ch_2_RID, - m_axi_mat_B_ch_2_RLAST, - m_axi_mat_B_ch_2_RREADY, - m_axi_mat_B_ch_2_RRESP, - m_axi_mat_B_ch_2_RVALID, - m_axi_mat_B_ch_2_WDATA, - m_axi_mat_B_ch_2_WLAST, - m_axi_mat_B_ch_2_WREADY, - m_axi_mat_B_ch_2_WSTRB, - m_axi_mat_B_ch_2_WVALID, - m_axi_mat_B_ch_3_ARADDR, - m_axi_mat_B_ch_3_ARBURST, - m_axi_mat_B_ch_3_ARCACHE, - m_axi_mat_B_ch_3_ARID, - m_axi_mat_B_ch_3_ARLEN, - m_axi_mat_B_ch_3_ARLOCK, - m_axi_mat_B_ch_3_ARPROT, - m_axi_mat_B_ch_3_ARQOS, - m_axi_mat_B_ch_3_ARREADY, - m_axi_mat_B_ch_3_ARSIZE, - m_axi_mat_B_ch_3_ARVALID, - m_axi_mat_B_ch_3_AWADDR, - m_axi_mat_B_ch_3_AWBURST, - m_axi_mat_B_ch_3_AWCACHE, - m_axi_mat_B_ch_3_AWID, - m_axi_mat_B_ch_3_AWLEN, - m_axi_mat_B_ch_3_AWLOCK, - m_axi_mat_B_ch_3_AWPROT, - m_axi_mat_B_ch_3_AWQOS, - m_axi_mat_B_ch_3_AWREADY, - m_axi_mat_B_ch_3_AWSIZE, - m_axi_mat_B_ch_3_AWVALID, - m_axi_mat_B_ch_3_BID, - m_axi_mat_B_ch_3_BREADY, - m_axi_mat_B_ch_3_BRESP, - m_axi_mat_B_ch_3_BVALID, - m_axi_mat_B_ch_3_RDATA, - m_axi_mat_B_ch_3_RID, - m_axi_mat_B_ch_3_RLAST, - m_axi_mat_B_ch_3_RREADY, - m_axi_mat_B_ch_3_RRESP, - m_axi_mat_B_ch_3_RVALID, - m_axi_mat_B_ch_3_WDATA, - m_axi_mat_B_ch_3_WLAST, - m_axi_mat_B_ch_3_WREADY, - m_axi_mat_B_ch_3_WSTRB, - m_axi_mat_B_ch_3_WVALID, - m_axi_mat_C_ch_in_0_ARADDR, - m_axi_mat_C_ch_in_0_ARBURST, - m_axi_mat_C_ch_in_0_ARCACHE, - m_axi_mat_C_ch_in_0_ARID, - m_axi_mat_C_ch_in_0_ARLEN, - m_axi_mat_C_ch_in_0_ARLOCK, - m_axi_mat_C_ch_in_0_ARPROT, - m_axi_mat_C_ch_in_0_ARQOS, - m_axi_mat_C_ch_in_0_ARREADY, - m_axi_mat_C_ch_in_0_ARSIZE, - m_axi_mat_C_ch_in_0_ARVALID, - m_axi_mat_C_ch_in_0_AWADDR, - m_axi_mat_C_ch_in_0_AWBURST, - m_axi_mat_C_ch_in_0_AWCACHE, - m_axi_mat_C_ch_in_0_AWID, - m_axi_mat_C_ch_in_0_AWLEN, - m_axi_mat_C_ch_in_0_AWLOCK, - m_axi_mat_C_ch_in_0_AWPROT, - m_axi_mat_C_ch_in_0_AWQOS, - m_axi_mat_C_ch_in_0_AWREADY, - m_axi_mat_C_ch_in_0_AWSIZE, - m_axi_mat_C_ch_in_0_AWVALID, - m_axi_mat_C_ch_in_0_BID, - m_axi_mat_C_ch_in_0_BREADY, - m_axi_mat_C_ch_in_0_BRESP, - m_axi_mat_C_ch_in_0_BVALID, - m_axi_mat_C_ch_in_0_RDATA, - m_axi_mat_C_ch_in_0_RID, - m_axi_mat_C_ch_in_0_RLAST, - m_axi_mat_C_ch_in_0_RREADY, - m_axi_mat_C_ch_in_0_RRESP, - m_axi_mat_C_ch_in_0_RVALID, - m_axi_mat_C_ch_in_0_WDATA, - m_axi_mat_C_ch_in_0_WLAST, - m_axi_mat_C_ch_in_0_WREADY, - m_axi_mat_C_ch_in_0_WSTRB, - m_axi_mat_C_ch_in_0_WVALID, - m_axi_mat_C_ch_in_1_ARADDR, - m_axi_mat_C_ch_in_1_ARBURST, - m_axi_mat_C_ch_in_1_ARCACHE, - m_axi_mat_C_ch_in_1_ARID, - m_axi_mat_C_ch_in_1_ARLEN, - m_axi_mat_C_ch_in_1_ARLOCK, - m_axi_mat_C_ch_in_1_ARPROT, - m_axi_mat_C_ch_in_1_ARQOS, - m_axi_mat_C_ch_in_1_ARREADY, - m_axi_mat_C_ch_in_1_ARSIZE, - m_axi_mat_C_ch_in_1_ARVALID, - m_axi_mat_C_ch_in_1_AWADDR, - m_axi_mat_C_ch_in_1_AWBURST, - m_axi_mat_C_ch_in_1_AWCACHE, - m_axi_mat_C_ch_in_1_AWID, - m_axi_mat_C_ch_in_1_AWLEN, - m_axi_mat_C_ch_in_1_AWLOCK, - m_axi_mat_C_ch_in_1_AWPROT, - m_axi_mat_C_ch_in_1_AWQOS, - m_axi_mat_C_ch_in_1_AWREADY, - m_axi_mat_C_ch_in_1_AWSIZE, - m_axi_mat_C_ch_in_1_AWVALID, - m_axi_mat_C_ch_in_1_BID, - m_axi_mat_C_ch_in_1_BREADY, - m_axi_mat_C_ch_in_1_BRESP, - m_axi_mat_C_ch_in_1_BVALID, - m_axi_mat_C_ch_in_1_RDATA, - m_axi_mat_C_ch_in_1_RID, - m_axi_mat_C_ch_in_1_RLAST, - m_axi_mat_C_ch_in_1_RREADY, - m_axi_mat_C_ch_in_1_RRESP, - m_axi_mat_C_ch_in_1_RVALID, - m_axi_mat_C_ch_in_1_WDATA, - m_axi_mat_C_ch_in_1_WLAST, - m_axi_mat_C_ch_in_1_WREADY, - m_axi_mat_C_ch_in_1_WSTRB, - m_axi_mat_C_ch_in_1_WVALID, - m_axi_mat_C_ch_in_2_ARADDR, - m_axi_mat_C_ch_in_2_ARBURST, - m_axi_mat_C_ch_in_2_ARCACHE, - m_axi_mat_C_ch_in_2_ARID, - m_axi_mat_C_ch_in_2_ARLEN, - m_axi_mat_C_ch_in_2_ARLOCK, - m_axi_mat_C_ch_in_2_ARPROT, - m_axi_mat_C_ch_in_2_ARQOS, - m_axi_mat_C_ch_in_2_ARREADY, - m_axi_mat_C_ch_in_2_ARSIZE, - m_axi_mat_C_ch_in_2_ARVALID, - m_axi_mat_C_ch_in_2_AWADDR, - m_axi_mat_C_ch_in_2_AWBURST, - m_axi_mat_C_ch_in_2_AWCACHE, - m_axi_mat_C_ch_in_2_AWID, - m_axi_mat_C_ch_in_2_AWLEN, - m_axi_mat_C_ch_in_2_AWLOCK, - m_axi_mat_C_ch_in_2_AWPROT, - m_axi_mat_C_ch_in_2_AWQOS, - m_axi_mat_C_ch_in_2_AWREADY, - m_axi_mat_C_ch_in_2_AWSIZE, - m_axi_mat_C_ch_in_2_AWVALID, - m_axi_mat_C_ch_in_2_BID, - m_axi_mat_C_ch_in_2_BREADY, - m_axi_mat_C_ch_in_2_BRESP, - m_axi_mat_C_ch_in_2_BVALID, - m_axi_mat_C_ch_in_2_RDATA, - m_axi_mat_C_ch_in_2_RID, - m_axi_mat_C_ch_in_2_RLAST, - m_axi_mat_C_ch_in_2_RREADY, - m_axi_mat_C_ch_in_2_RRESP, - m_axi_mat_C_ch_in_2_RVALID, - m_axi_mat_C_ch_in_2_WDATA, - m_axi_mat_C_ch_in_2_WLAST, - m_axi_mat_C_ch_in_2_WREADY, - m_axi_mat_C_ch_in_2_WSTRB, - m_axi_mat_C_ch_in_2_WVALID, - m_axi_mat_C_ch_in_3_ARADDR, - m_axi_mat_C_ch_in_3_ARBURST, - m_axi_mat_C_ch_in_3_ARCACHE, - m_axi_mat_C_ch_in_3_ARID, - m_axi_mat_C_ch_in_3_ARLEN, - m_axi_mat_C_ch_in_3_ARLOCK, - m_axi_mat_C_ch_in_3_ARPROT, - m_axi_mat_C_ch_in_3_ARQOS, - m_axi_mat_C_ch_in_3_ARREADY, - m_axi_mat_C_ch_in_3_ARSIZE, - m_axi_mat_C_ch_in_3_ARVALID, - m_axi_mat_C_ch_in_3_AWADDR, - m_axi_mat_C_ch_in_3_AWBURST, - m_axi_mat_C_ch_in_3_AWCACHE, - m_axi_mat_C_ch_in_3_AWID, - m_axi_mat_C_ch_in_3_AWLEN, - m_axi_mat_C_ch_in_3_AWLOCK, - m_axi_mat_C_ch_in_3_AWPROT, - m_axi_mat_C_ch_in_3_AWQOS, - m_axi_mat_C_ch_in_3_AWREADY, - m_axi_mat_C_ch_in_3_AWSIZE, - m_axi_mat_C_ch_in_3_AWVALID, - m_axi_mat_C_ch_in_3_BID, - m_axi_mat_C_ch_in_3_BREADY, - m_axi_mat_C_ch_in_3_BRESP, - m_axi_mat_C_ch_in_3_BVALID, - m_axi_mat_C_ch_in_3_RDATA, - m_axi_mat_C_ch_in_3_RID, - m_axi_mat_C_ch_in_3_RLAST, - m_axi_mat_C_ch_in_3_RREADY, - m_axi_mat_C_ch_in_3_RRESP, - m_axi_mat_C_ch_in_3_RVALID, - m_axi_mat_C_ch_in_3_WDATA, - m_axi_mat_C_ch_in_3_WLAST, - m_axi_mat_C_ch_in_3_WREADY, - m_axi_mat_C_ch_in_3_WSTRB, - m_axi_mat_C_ch_in_3_WVALID, - m_axi_mat_C_ch_in_4_ARADDR, - m_axi_mat_C_ch_in_4_ARBURST, - m_axi_mat_C_ch_in_4_ARCACHE, - m_axi_mat_C_ch_in_4_ARID, - m_axi_mat_C_ch_in_4_ARLEN, - m_axi_mat_C_ch_in_4_ARLOCK, - m_axi_mat_C_ch_in_4_ARPROT, - m_axi_mat_C_ch_in_4_ARQOS, - m_axi_mat_C_ch_in_4_ARREADY, - m_axi_mat_C_ch_in_4_ARSIZE, - m_axi_mat_C_ch_in_4_ARVALID, - m_axi_mat_C_ch_in_4_AWADDR, - m_axi_mat_C_ch_in_4_AWBURST, - m_axi_mat_C_ch_in_4_AWCACHE, - m_axi_mat_C_ch_in_4_AWID, - m_axi_mat_C_ch_in_4_AWLEN, - m_axi_mat_C_ch_in_4_AWLOCK, - m_axi_mat_C_ch_in_4_AWPROT, - m_axi_mat_C_ch_in_4_AWQOS, - m_axi_mat_C_ch_in_4_AWREADY, - m_axi_mat_C_ch_in_4_AWSIZE, - m_axi_mat_C_ch_in_4_AWVALID, - m_axi_mat_C_ch_in_4_BID, - m_axi_mat_C_ch_in_4_BREADY, - m_axi_mat_C_ch_in_4_BRESP, - m_axi_mat_C_ch_in_4_BVALID, - m_axi_mat_C_ch_in_4_RDATA, - m_axi_mat_C_ch_in_4_RID, - m_axi_mat_C_ch_in_4_RLAST, - m_axi_mat_C_ch_in_4_RREADY, - m_axi_mat_C_ch_in_4_RRESP, - m_axi_mat_C_ch_in_4_RVALID, - m_axi_mat_C_ch_in_4_WDATA, - m_axi_mat_C_ch_in_4_WLAST, - m_axi_mat_C_ch_in_4_WREADY, - m_axi_mat_C_ch_in_4_WSTRB, - m_axi_mat_C_ch_in_4_WVALID, - m_axi_mat_C_ch_in_5_ARADDR, - m_axi_mat_C_ch_in_5_ARBURST, - m_axi_mat_C_ch_in_5_ARCACHE, - m_axi_mat_C_ch_in_5_ARID, - m_axi_mat_C_ch_in_5_ARLEN, - m_axi_mat_C_ch_in_5_ARLOCK, - m_axi_mat_C_ch_in_5_ARPROT, - m_axi_mat_C_ch_in_5_ARQOS, - m_axi_mat_C_ch_in_5_ARREADY, - m_axi_mat_C_ch_in_5_ARSIZE, - m_axi_mat_C_ch_in_5_ARVALID, - m_axi_mat_C_ch_in_5_AWADDR, - m_axi_mat_C_ch_in_5_AWBURST, - m_axi_mat_C_ch_in_5_AWCACHE, - m_axi_mat_C_ch_in_5_AWID, - m_axi_mat_C_ch_in_5_AWLEN, - m_axi_mat_C_ch_in_5_AWLOCK, - m_axi_mat_C_ch_in_5_AWPROT, - m_axi_mat_C_ch_in_5_AWQOS, - m_axi_mat_C_ch_in_5_AWREADY, - m_axi_mat_C_ch_in_5_AWSIZE, - m_axi_mat_C_ch_in_5_AWVALID, - m_axi_mat_C_ch_in_5_BID, - m_axi_mat_C_ch_in_5_BREADY, - m_axi_mat_C_ch_in_5_BRESP, - m_axi_mat_C_ch_in_5_BVALID, - m_axi_mat_C_ch_in_5_RDATA, - m_axi_mat_C_ch_in_5_RID, - m_axi_mat_C_ch_in_5_RLAST, - m_axi_mat_C_ch_in_5_RREADY, - m_axi_mat_C_ch_in_5_RRESP, - m_axi_mat_C_ch_in_5_RVALID, - m_axi_mat_C_ch_in_5_WDATA, - m_axi_mat_C_ch_in_5_WLAST, - m_axi_mat_C_ch_in_5_WREADY, - m_axi_mat_C_ch_in_5_WSTRB, - m_axi_mat_C_ch_in_5_WVALID, - m_axi_mat_C_ch_in_6_ARADDR, - m_axi_mat_C_ch_in_6_ARBURST, - m_axi_mat_C_ch_in_6_ARCACHE, - m_axi_mat_C_ch_in_6_ARID, - m_axi_mat_C_ch_in_6_ARLEN, - m_axi_mat_C_ch_in_6_ARLOCK, - m_axi_mat_C_ch_in_6_ARPROT, - m_axi_mat_C_ch_in_6_ARQOS, - m_axi_mat_C_ch_in_6_ARREADY, - m_axi_mat_C_ch_in_6_ARSIZE, - m_axi_mat_C_ch_in_6_ARVALID, - m_axi_mat_C_ch_in_6_AWADDR, - m_axi_mat_C_ch_in_6_AWBURST, - m_axi_mat_C_ch_in_6_AWCACHE, - m_axi_mat_C_ch_in_6_AWID, - m_axi_mat_C_ch_in_6_AWLEN, - m_axi_mat_C_ch_in_6_AWLOCK, - m_axi_mat_C_ch_in_6_AWPROT, - m_axi_mat_C_ch_in_6_AWQOS, - m_axi_mat_C_ch_in_6_AWREADY, - m_axi_mat_C_ch_in_6_AWSIZE, - m_axi_mat_C_ch_in_6_AWVALID, - m_axi_mat_C_ch_in_6_BID, - m_axi_mat_C_ch_in_6_BREADY, - m_axi_mat_C_ch_in_6_BRESP, - m_axi_mat_C_ch_in_6_BVALID, - m_axi_mat_C_ch_in_6_RDATA, - m_axi_mat_C_ch_in_6_RID, - m_axi_mat_C_ch_in_6_RLAST, - m_axi_mat_C_ch_in_6_RREADY, - m_axi_mat_C_ch_in_6_RRESP, - m_axi_mat_C_ch_in_6_RVALID, - m_axi_mat_C_ch_in_6_WDATA, - m_axi_mat_C_ch_in_6_WLAST, - m_axi_mat_C_ch_in_6_WREADY, - m_axi_mat_C_ch_in_6_WSTRB, - m_axi_mat_C_ch_in_6_WVALID, - m_axi_mat_C_ch_in_7_ARADDR, - m_axi_mat_C_ch_in_7_ARBURST, - m_axi_mat_C_ch_in_7_ARCACHE, - m_axi_mat_C_ch_in_7_ARID, - m_axi_mat_C_ch_in_7_ARLEN, - m_axi_mat_C_ch_in_7_ARLOCK, - m_axi_mat_C_ch_in_7_ARPROT, - m_axi_mat_C_ch_in_7_ARQOS, - m_axi_mat_C_ch_in_7_ARREADY, - m_axi_mat_C_ch_in_7_ARSIZE, - m_axi_mat_C_ch_in_7_ARVALID, - m_axi_mat_C_ch_in_7_AWADDR, - m_axi_mat_C_ch_in_7_AWBURST, - m_axi_mat_C_ch_in_7_AWCACHE, - m_axi_mat_C_ch_in_7_AWID, - m_axi_mat_C_ch_in_7_AWLEN, - m_axi_mat_C_ch_in_7_AWLOCK, - m_axi_mat_C_ch_in_7_AWPROT, - m_axi_mat_C_ch_in_7_AWQOS, - m_axi_mat_C_ch_in_7_AWREADY, - m_axi_mat_C_ch_in_7_AWSIZE, - m_axi_mat_C_ch_in_7_AWVALID, - m_axi_mat_C_ch_in_7_BID, - m_axi_mat_C_ch_in_7_BREADY, - m_axi_mat_C_ch_in_7_BRESP, - m_axi_mat_C_ch_in_7_BVALID, - m_axi_mat_C_ch_in_7_RDATA, - m_axi_mat_C_ch_in_7_RID, - m_axi_mat_C_ch_in_7_RLAST, - m_axi_mat_C_ch_in_7_RREADY, - m_axi_mat_C_ch_in_7_RRESP, - m_axi_mat_C_ch_in_7_RVALID, - m_axi_mat_C_ch_in_7_WDATA, - m_axi_mat_C_ch_in_7_WLAST, - m_axi_mat_C_ch_in_7_WREADY, - m_axi_mat_C_ch_in_7_WSTRB, - m_axi_mat_C_ch_in_7_WVALID, - m_axi_edge_list_ptr_ARADDR, - m_axi_edge_list_ptr_ARBURST, - m_axi_edge_list_ptr_ARCACHE, - m_axi_edge_list_ptr_ARID, - m_axi_edge_list_ptr_ARLEN, - m_axi_edge_list_ptr_ARLOCK, - m_axi_edge_list_ptr_ARPROT, - m_axi_edge_list_ptr_ARQOS, - m_axi_edge_list_ptr_ARREADY, - m_axi_edge_list_ptr_ARSIZE, - m_axi_edge_list_ptr_ARVALID, - m_axi_edge_list_ptr_AWADDR, - m_axi_edge_list_ptr_AWBURST, - m_axi_edge_list_ptr_AWCACHE, - m_axi_edge_list_ptr_AWID, - m_axi_edge_list_ptr_AWLEN, - m_axi_edge_list_ptr_AWLOCK, - m_axi_edge_list_ptr_AWPROT, - m_axi_edge_list_ptr_AWQOS, - m_axi_edge_list_ptr_AWREADY, - m_axi_edge_list_ptr_AWSIZE, - m_axi_edge_list_ptr_AWVALID, - m_axi_edge_list_ptr_BID, - m_axi_edge_list_ptr_BREADY, - m_axi_edge_list_ptr_BRESP, - m_axi_edge_list_ptr_BVALID, - m_axi_edge_list_ptr_RDATA, - m_axi_edge_list_ptr_RID, - m_axi_edge_list_ptr_RLAST, - m_axi_edge_list_ptr_RREADY, - m_axi_edge_list_ptr_RRESP, - m_axi_edge_list_ptr_RVALID, - m_axi_edge_list_ptr_WDATA, - m_axi_edge_list_ptr_WLAST, - m_axi_edge_list_ptr_WREADY, - m_axi_edge_list_ptr_WSTRB, - m_axi_edge_list_ptr_WVALID, - m_axi_mat_C_ch_0_ARADDR, - m_axi_mat_C_ch_0_ARBURST, - m_axi_mat_C_ch_0_ARCACHE, - m_axi_mat_C_ch_0_ARID, - m_axi_mat_C_ch_0_ARLEN, - m_axi_mat_C_ch_0_ARLOCK, - m_axi_mat_C_ch_0_ARPROT, - m_axi_mat_C_ch_0_ARQOS, - m_axi_mat_C_ch_0_ARREADY, - m_axi_mat_C_ch_0_ARSIZE, - m_axi_mat_C_ch_0_ARVALID, - m_axi_mat_C_ch_0_AWADDR, - m_axi_mat_C_ch_0_AWBURST, - m_axi_mat_C_ch_0_AWCACHE, - m_axi_mat_C_ch_0_AWID, - m_axi_mat_C_ch_0_AWLEN, - m_axi_mat_C_ch_0_AWLOCK, - m_axi_mat_C_ch_0_AWPROT, - m_axi_mat_C_ch_0_AWQOS, - m_axi_mat_C_ch_0_AWREADY, - m_axi_mat_C_ch_0_AWSIZE, - m_axi_mat_C_ch_0_AWVALID, - m_axi_mat_C_ch_0_BID, - m_axi_mat_C_ch_0_BREADY, - m_axi_mat_C_ch_0_BRESP, - m_axi_mat_C_ch_0_BVALID, - m_axi_mat_C_ch_0_RDATA, - m_axi_mat_C_ch_0_RID, - m_axi_mat_C_ch_0_RLAST, - m_axi_mat_C_ch_0_RREADY, - m_axi_mat_C_ch_0_RRESP, - m_axi_mat_C_ch_0_RVALID, - m_axi_mat_C_ch_0_WDATA, - m_axi_mat_C_ch_0_WLAST, - m_axi_mat_C_ch_0_WREADY, - m_axi_mat_C_ch_0_WSTRB, - m_axi_mat_C_ch_0_WVALID, - m_axi_mat_C_ch_1_ARADDR, - m_axi_mat_C_ch_1_ARBURST, - m_axi_mat_C_ch_1_ARCACHE, - m_axi_mat_C_ch_1_ARID, - m_axi_mat_C_ch_1_ARLEN, - m_axi_mat_C_ch_1_ARLOCK, - m_axi_mat_C_ch_1_ARPROT, - m_axi_mat_C_ch_1_ARQOS, - m_axi_mat_C_ch_1_ARREADY, - m_axi_mat_C_ch_1_ARSIZE, - m_axi_mat_C_ch_1_ARVALID, - m_axi_mat_C_ch_1_AWADDR, - m_axi_mat_C_ch_1_AWBURST, - m_axi_mat_C_ch_1_AWCACHE, - m_axi_mat_C_ch_1_AWID, - m_axi_mat_C_ch_1_AWLEN, - m_axi_mat_C_ch_1_AWLOCK, - m_axi_mat_C_ch_1_AWPROT, - m_axi_mat_C_ch_1_AWQOS, - m_axi_mat_C_ch_1_AWREADY, - m_axi_mat_C_ch_1_AWSIZE, - m_axi_mat_C_ch_1_AWVALID, - m_axi_mat_C_ch_1_BID, - m_axi_mat_C_ch_1_BREADY, - m_axi_mat_C_ch_1_BRESP, - m_axi_mat_C_ch_1_BVALID, - m_axi_mat_C_ch_1_RDATA, - m_axi_mat_C_ch_1_RID, - m_axi_mat_C_ch_1_RLAST, - m_axi_mat_C_ch_1_RREADY, - m_axi_mat_C_ch_1_RRESP, - m_axi_mat_C_ch_1_RVALID, - m_axi_mat_C_ch_1_WDATA, - m_axi_mat_C_ch_1_WLAST, - m_axi_mat_C_ch_1_WREADY, - m_axi_mat_C_ch_1_WSTRB, - m_axi_mat_C_ch_1_WVALID, - m_axi_mat_C_ch_2_ARADDR, - m_axi_mat_C_ch_2_ARBURST, - m_axi_mat_C_ch_2_ARCACHE, - m_axi_mat_C_ch_2_ARID, - m_axi_mat_C_ch_2_ARLEN, - m_axi_mat_C_ch_2_ARLOCK, - m_axi_mat_C_ch_2_ARPROT, - m_axi_mat_C_ch_2_ARQOS, - m_axi_mat_C_ch_2_ARREADY, - m_axi_mat_C_ch_2_ARSIZE, - m_axi_mat_C_ch_2_ARVALID, - m_axi_mat_C_ch_2_AWADDR, - m_axi_mat_C_ch_2_AWBURST, - m_axi_mat_C_ch_2_AWCACHE, - m_axi_mat_C_ch_2_AWID, - m_axi_mat_C_ch_2_AWLEN, - m_axi_mat_C_ch_2_AWLOCK, - m_axi_mat_C_ch_2_AWPROT, - m_axi_mat_C_ch_2_AWQOS, - m_axi_mat_C_ch_2_AWREADY, - m_axi_mat_C_ch_2_AWSIZE, - m_axi_mat_C_ch_2_AWVALID, - m_axi_mat_C_ch_2_BID, - m_axi_mat_C_ch_2_BREADY, - m_axi_mat_C_ch_2_BRESP, - m_axi_mat_C_ch_2_BVALID, - m_axi_mat_C_ch_2_RDATA, - m_axi_mat_C_ch_2_RID, - m_axi_mat_C_ch_2_RLAST, - m_axi_mat_C_ch_2_RREADY, - m_axi_mat_C_ch_2_RRESP, - m_axi_mat_C_ch_2_RVALID, - m_axi_mat_C_ch_2_WDATA, - m_axi_mat_C_ch_2_WLAST, - m_axi_mat_C_ch_2_WREADY, - m_axi_mat_C_ch_2_WSTRB, - m_axi_mat_C_ch_2_WVALID, - m_axi_mat_C_ch_3_ARADDR, - m_axi_mat_C_ch_3_ARBURST, - m_axi_mat_C_ch_3_ARCACHE, - m_axi_mat_C_ch_3_ARID, - m_axi_mat_C_ch_3_ARLEN, - m_axi_mat_C_ch_3_ARLOCK, - m_axi_mat_C_ch_3_ARPROT, - m_axi_mat_C_ch_3_ARQOS, - m_axi_mat_C_ch_3_ARREADY, - m_axi_mat_C_ch_3_ARSIZE, - m_axi_mat_C_ch_3_ARVALID, - m_axi_mat_C_ch_3_AWADDR, - m_axi_mat_C_ch_3_AWBURST, - m_axi_mat_C_ch_3_AWCACHE, - m_axi_mat_C_ch_3_AWID, - m_axi_mat_C_ch_3_AWLEN, - m_axi_mat_C_ch_3_AWLOCK, - m_axi_mat_C_ch_3_AWPROT, - m_axi_mat_C_ch_3_AWQOS, - m_axi_mat_C_ch_3_AWREADY, - m_axi_mat_C_ch_3_AWSIZE, - m_axi_mat_C_ch_3_AWVALID, - m_axi_mat_C_ch_3_BID, - m_axi_mat_C_ch_3_BREADY, - m_axi_mat_C_ch_3_BRESP, - m_axi_mat_C_ch_3_BVALID, - m_axi_mat_C_ch_3_RDATA, - m_axi_mat_C_ch_3_RID, - m_axi_mat_C_ch_3_RLAST, - m_axi_mat_C_ch_3_RREADY, - m_axi_mat_C_ch_3_RRESP, - m_axi_mat_C_ch_3_RVALID, - m_axi_mat_C_ch_3_WDATA, - m_axi_mat_C_ch_3_WLAST, - m_axi_mat_C_ch_3_WREADY, - m_axi_mat_C_ch_3_WSTRB, - m_axi_mat_C_ch_3_WVALID, - m_axi_mat_C_ch_4_ARADDR, - m_axi_mat_C_ch_4_ARBURST, - m_axi_mat_C_ch_4_ARCACHE, - m_axi_mat_C_ch_4_ARID, - m_axi_mat_C_ch_4_ARLEN, - m_axi_mat_C_ch_4_ARLOCK, - m_axi_mat_C_ch_4_ARPROT, - m_axi_mat_C_ch_4_ARQOS, - m_axi_mat_C_ch_4_ARREADY, - m_axi_mat_C_ch_4_ARSIZE, - m_axi_mat_C_ch_4_ARVALID, - m_axi_mat_C_ch_4_AWADDR, - m_axi_mat_C_ch_4_AWBURST, - m_axi_mat_C_ch_4_AWCACHE, - m_axi_mat_C_ch_4_AWID, - m_axi_mat_C_ch_4_AWLEN, - m_axi_mat_C_ch_4_AWLOCK, - m_axi_mat_C_ch_4_AWPROT, - m_axi_mat_C_ch_4_AWQOS, - m_axi_mat_C_ch_4_AWREADY, - m_axi_mat_C_ch_4_AWSIZE, - m_axi_mat_C_ch_4_AWVALID, - m_axi_mat_C_ch_4_BID, - m_axi_mat_C_ch_4_BREADY, - m_axi_mat_C_ch_4_BRESP, - m_axi_mat_C_ch_4_BVALID, - m_axi_mat_C_ch_4_RDATA, - m_axi_mat_C_ch_4_RID, - m_axi_mat_C_ch_4_RLAST, - m_axi_mat_C_ch_4_RREADY, - m_axi_mat_C_ch_4_RRESP, - m_axi_mat_C_ch_4_RVALID, - m_axi_mat_C_ch_4_WDATA, - m_axi_mat_C_ch_4_WLAST, - m_axi_mat_C_ch_4_WREADY, - m_axi_mat_C_ch_4_WSTRB, - m_axi_mat_C_ch_4_WVALID, - m_axi_mat_C_ch_5_ARADDR, - m_axi_mat_C_ch_5_ARBURST, - m_axi_mat_C_ch_5_ARCACHE, - m_axi_mat_C_ch_5_ARID, - m_axi_mat_C_ch_5_ARLEN, - m_axi_mat_C_ch_5_ARLOCK, - m_axi_mat_C_ch_5_ARPROT, - m_axi_mat_C_ch_5_ARQOS, - m_axi_mat_C_ch_5_ARREADY, - m_axi_mat_C_ch_5_ARSIZE, - m_axi_mat_C_ch_5_ARVALID, - m_axi_mat_C_ch_5_AWADDR, - m_axi_mat_C_ch_5_AWBURST, - m_axi_mat_C_ch_5_AWCACHE, - m_axi_mat_C_ch_5_AWID, - m_axi_mat_C_ch_5_AWLEN, - m_axi_mat_C_ch_5_AWLOCK, - m_axi_mat_C_ch_5_AWPROT, - m_axi_mat_C_ch_5_AWQOS, - m_axi_mat_C_ch_5_AWREADY, - m_axi_mat_C_ch_5_AWSIZE, - m_axi_mat_C_ch_5_AWVALID, - m_axi_mat_C_ch_5_BID, - m_axi_mat_C_ch_5_BREADY, - m_axi_mat_C_ch_5_BRESP, - m_axi_mat_C_ch_5_BVALID, - m_axi_mat_C_ch_5_RDATA, - m_axi_mat_C_ch_5_RID, - m_axi_mat_C_ch_5_RLAST, - m_axi_mat_C_ch_5_RREADY, - m_axi_mat_C_ch_5_RRESP, - m_axi_mat_C_ch_5_RVALID, - m_axi_mat_C_ch_5_WDATA, - m_axi_mat_C_ch_5_WLAST, - m_axi_mat_C_ch_5_WREADY, - m_axi_mat_C_ch_5_WSTRB, - m_axi_mat_C_ch_5_WVALID, - m_axi_mat_C_ch_6_ARADDR, - m_axi_mat_C_ch_6_ARBURST, - m_axi_mat_C_ch_6_ARCACHE, - m_axi_mat_C_ch_6_ARID, - m_axi_mat_C_ch_6_ARLEN, - m_axi_mat_C_ch_6_ARLOCK, - m_axi_mat_C_ch_6_ARPROT, - m_axi_mat_C_ch_6_ARQOS, - m_axi_mat_C_ch_6_ARREADY, - m_axi_mat_C_ch_6_ARSIZE, - m_axi_mat_C_ch_6_ARVALID, - m_axi_mat_C_ch_6_AWADDR, - m_axi_mat_C_ch_6_AWBURST, - m_axi_mat_C_ch_6_AWCACHE, - m_axi_mat_C_ch_6_AWID, - m_axi_mat_C_ch_6_AWLEN, - m_axi_mat_C_ch_6_AWLOCK, - m_axi_mat_C_ch_6_AWPROT, - m_axi_mat_C_ch_6_AWQOS, - m_axi_mat_C_ch_6_AWREADY, - m_axi_mat_C_ch_6_AWSIZE, - m_axi_mat_C_ch_6_AWVALID, - m_axi_mat_C_ch_6_BID, - m_axi_mat_C_ch_6_BREADY, - m_axi_mat_C_ch_6_BRESP, - m_axi_mat_C_ch_6_BVALID, - m_axi_mat_C_ch_6_RDATA, - m_axi_mat_C_ch_6_RID, - m_axi_mat_C_ch_6_RLAST, - m_axi_mat_C_ch_6_RREADY, - m_axi_mat_C_ch_6_RRESP, - m_axi_mat_C_ch_6_RVALID, - m_axi_mat_C_ch_6_WDATA, - m_axi_mat_C_ch_6_WLAST, - m_axi_mat_C_ch_6_WREADY, - m_axi_mat_C_ch_6_WSTRB, - m_axi_mat_C_ch_6_WVALID, - m_axi_mat_C_ch_7_ARADDR, - m_axi_mat_C_ch_7_ARBURST, - m_axi_mat_C_ch_7_ARCACHE, - m_axi_mat_C_ch_7_ARID, - m_axi_mat_C_ch_7_ARLEN, - m_axi_mat_C_ch_7_ARLOCK, - m_axi_mat_C_ch_7_ARPROT, - m_axi_mat_C_ch_7_ARQOS, - m_axi_mat_C_ch_7_ARREADY, - m_axi_mat_C_ch_7_ARSIZE, - m_axi_mat_C_ch_7_ARVALID, - m_axi_mat_C_ch_7_AWADDR, - m_axi_mat_C_ch_7_AWBURST, - m_axi_mat_C_ch_7_AWCACHE, - m_axi_mat_C_ch_7_AWID, - m_axi_mat_C_ch_7_AWLEN, - m_axi_mat_C_ch_7_AWLOCK, - m_axi_mat_C_ch_7_AWPROT, - m_axi_mat_C_ch_7_AWQOS, - m_axi_mat_C_ch_7_AWREADY, - m_axi_mat_C_ch_7_AWSIZE, - m_axi_mat_C_ch_7_AWVALID, - m_axi_mat_C_ch_7_BID, - m_axi_mat_C_ch_7_BREADY, - m_axi_mat_C_ch_7_BRESP, - m_axi_mat_C_ch_7_BVALID, - m_axi_mat_C_ch_7_RDATA, - m_axi_mat_C_ch_7_RID, - m_axi_mat_C_ch_7_RLAST, - m_axi_mat_C_ch_7_RREADY, - m_axi_mat_C_ch_7_RRESP, - m_axi_mat_C_ch_7_RVALID, - m_axi_mat_C_ch_7_WDATA, - m_axi_mat_C_ch_7_WLAST, - m_axi_mat_C_ch_7_WREADY, - m_axi_mat_C_ch_7_WSTRB, - m_axi_mat_C_ch_7_WVALID -); - - parameter C_S_AXI_CONTROL_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_ADDR_WIDTH = 9; - parameter C_S_AXI_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_WSTRB_WIDTH = 32 / 8; - parameter C_S_AXI_WSTRB_WIDTH = 32 / 8; - (* RS_HS = "s_axi_control_AW.valid" *)input s_axi_control_AWVALID; - (* RS_HS = "s_axi_control_AW.ready" *)output s_axi_control_AWREADY; - (* RS_HS = "s_axi_control_AW.data" *)input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR; - (* RS_HS = "s_axi_control_W.valid" *)input s_axi_control_WVALID; - (* RS_HS = "s_axi_control_W.ready" *)output s_axi_control_WREADY; - (* RS_HS = "s_axi_control_W.data" *)input [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA; - (* RS_HS = "s_axi_control_W.data" *)input [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB; - (* RS_HS = "s_axi_control_AR.valid" *)input s_axi_control_ARVALID; - (* RS_HS = "s_axi_control_AR.ready" *)output s_axi_control_ARREADY; - (* RS_HS = "s_axi_control_AR.data" *)input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_ARADDR; - (* RS_HS = "s_axi_control_R.valid" *)output s_axi_control_RVALID; - (* RS_HS = "s_axi_control_R.ready" *)input s_axi_control_RREADY; - (* RS_HS = "s_axi_control_R.data" *)output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_RDATA; - (* RS_HS = "s_axi_control_R.data" *)output [1:0] s_axi_control_RRESP; - (* RS_HS = "s_axi_control_B.valid" *)output s_axi_control_BVALID; - (* RS_HS = "s_axi_control_B.ready" *)input s_axi_control_BREADY; - (* RS_HS = "s_axi_control_B.data" *)output [1:0] s_axi_control_BRESP; - (* RS_CLK *)input ap_clk; - (* RS_RST = "ff" *)input ap_rst_n; - (* RS_FF = "interrupt" *)output interrupt; - (* RS_HS = "m_axi_edge_list_ch_0_AR.data" *)output [63:0] m_axi_edge_list_ch_0_ARADDR; - (* RS_HS = "m_axi_edge_list_ch_0_AR.data" *)output [1:0] m_axi_edge_list_ch_0_ARBURST; - (* RS_HS = "m_axi_edge_list_ch_0_AR.data" *)output [3:0] m_axi_edge_list_ch_0_ARCACHE; - (* RS_HS = "m_axi_edge_list_ch_0_AR.data" *)output [0:0] m_axi_edge_list_ch_0_ARID; - (* RS_HS = "m_axi_edge_list_ch_0_AR.data" *)output [7:0] m_axi_edge_list_ch_0_ARLEN; - (* RS_HS = "m_axi_edge_list_ch_0_AR.data" *)output m_axi_edge_list_ch_0_ARLOCK; - (* RS_HS = "m_axi_edge_list_ch_0_AR.data" *)output [2:0] m_axi_edge_list_ch_0_ARPROT; - (* RS_HS = "m_axi_edge_list_ch_0_AR.data" *)output [3:0] m_axi_edge_list_ch_0_ARQOS; - (* RS_HS = "m_axi_edge_list_ch_0_AR.ready" *)input m_axi_edge_list_ch_0_ARREADY; - (* RS_HS = "m_axi_edge_list_ch_0_AR.data" *)output [2:0] m_axi_edge_list_ch_0_ARSIZE; - (* RS_HS = "m_axi_edge_list_ch_0_AR.valid" *)output m_axi_edge_list_ch_0_ARVALID; - (* RS_HS = "m_axi_edge_list_ch_0_AW.data" *)output [63:0] m_axi_edge_list_ch_0_AWADDR; - (* RS_HS = "m_axi_edge_list_ch_0_AW.data" *)output [1:0] m_axi_edge_list_ch_0_AWBURST; - (* RS_HS = "m_axi_edge_list_ch_0_AW.data" *)output [3:0] m_axi_edge_list_ch_0_AWCACHE; - (* RS_HS = "m_axi_edge_list_ch_0_AW.data" *)output [0:0] m_axi_edge_list_ch_0_AWID; - (* RS_HS = "m_axi_edge_list_ch_0_AW.data" *)output [7:0] m_axi_edge_list_ch_0_AWLEN; - (* RS_HS = "m_axi_edge_list_ch_0_AW.data" *)output m_axi_edge_list_ch_0_AWLOCK; - (* RS_HS = "m_axi_edge_list_ch_0_AW.data" *)output [2:0] m_axi_edge_list_ch_0_AWPROT; - (* RS_HS = "m_axi_edge_list_ch_0_AW.data" *)output [3:0] m_axi_edge_list_ch_0_AWQOS; - (* RS_HS = "m_axi_edge_list_ch_0_AW.ready" *)input m_axi_edge_list_ch_0_AWREADY; - (* RS_HS = "m_axi_edge_list_ch_0_AW.data" *)output [2:0] m_axi_edge_list_ch_0_AWSIZE; - (* RS_HS = "m_axi_edge_list_ch_0_AW.valid" *)output m_axi_edge_list_ch_0_AWVALID; - (* RS_HS = "m_axi_edge_list_ch_0_B.data" *)input [0:0] m_axi_edge_list_ch_0_BID; - (* RS_HS = "m_axi_edge_list_ch_0_B.ready" *)output m_axi_edge_list_ch_0_BREADY; - (* RS_HS = "m_axi_edge_list_ch_0_B.data" *)input [1:0] m_axi_edge_list_ch_0_BRESP; - (* RS_HS = "m_axi_edge_list_ch_0_B.valid" *)input m_axi_edge_list_ch_0_BVALID; - (* RS_HS = "m_axi_edge_list_ch_0_R.data" *)input [511:0] m_axi_edge_list_ch_0_RDATA; - (* RS_HS = "m_axi_edge_list_ch_0_R.data" *)input [0:0] m_axi_edge_list_ch_0_RID; - (* RS_HS = "m_axi_edge_list_ch_0_R.data" *)input m_axi_edge_list_ch_0_RLAST; - (* RS_HS = "m_axi_edge_list_ch_0_R.ready" *)output m_axi_edge_list_ch_0_RREADY; - (* RS_HS = "m_axi_edge_list_ch_0_R.data" *)input [1:0] m_axi_edge_list_ch_0_RRESP; - (* RS_HS = "m_axi_edge_list_ch_0_R.valid" *)input m_axi_edge_list_ch_0_RVALID; - (* RS_HS = "m_axi_edge_list_ch_0_W.data" *)output [511:0] m_axi_edge_list_ch_0_WDATA; - (* RS_HS = "m_axi_edge_list_ch_0_W.data" *)output m_axi_edge_list_ch_0_WLAST; - (* RS_HS = "m_axi_edge_list_ch_0_W.ready" *)input m_axi_edge_list_ch_0_WREADY; - (* RS_HS = "m_axi_edge_list_ch_0_W.data" *)output [63:0] m_axi_edge_list_ch_0_WSTRB; - (* RS_HS = "m_axi_edge_list_ch_0_W.valid" *)output m_axi_edge_list_ch_0_WVALID; - (* RS_HS = "m_axi_edge_list_ch_1_AR.data" *)output [63:0] m_axi_edge_list_ch_1_ARADDR; - (* RS_HS = "m_axi_edge_list_ch_1_AR.data" *)output [1:0] m_axi_edge_list_ch_1_ARBURST; - (* RS_HS = "m_axi_edge_list_ch_1_AR.data" *)output [3:0] m_axi_edge_list_ch_1_ARCACHE; - (* RS_HS = "m_axi_edge_list_ch_1_AR.data" *)output [0:0] m_axi_edge_list_ch_1_ARID; - (* RS_HS = "m_axi_edge_list_ch_1_AR.data" *)output [7:0] m_axi_edge_list_ch_1_ARLEN; - (* RS_HS = "m_axi_edge_list_ch_1_AR.data" *)output m_axi_edge_list_ch_1_ARLOCK; - (* RS_HS = "m_axi_edge_list_ch_1_AR.data" *)output [2:0] m_axi_edge_list_ch_1_ARPROT; - (* RS_HS = "m_axi_edge_list_ch_1_AR.data" *)output [3:0] m_axi_edge_list_ch_1_ARQOS; - (* RS_HS = "m_axi_edge_list_ch_1_AR.ready" *)input m_axi_edge_list_ch_1_ARREADY; - (* RS_HS = "m_axi_edge_list_ch_1_AR.data" *)output [2:0] m_axi_edge_list_ch_1_ARSIZE; - (* RS_HS = "m_axi_edge_list_ch_1_AR.valid" *)output m_axi_edge_list_ch_1_ARVALID; - (* RS_HS = "m_axi_edge_list_ch_1_AW.data" *)output [63:0] m_axi_edge_list_ch_1_AWADDR; - (* RS_HS = "m_axi_edge_list_ch_1_AW.data" *)output [1:0] m_axi_edge_list_ch_1_AWBURST; - (* RS_HS = "m_axi_edge_list_ch_1_AW.data" *)output [3:0] m_axi_edge_list_ch_1_AWCACHE; - (* RS_HS = "m_axi_edge_list_ch_1_AW.data" *)output [0:0] m_axi_edge_list_ch_1_AWID; - (* RS_HS = "m_axi_edge_list_ch_1_AW.data" *)output [7:0] m_axi_edge_list_ch_1_AWLEN; - (* RS_HS = "m_axi_edge_list_ch_1_AW.data" *)output m_axi_edge_list_ch_1_AWLOCK; - (* RS_HS = "m_axi_edge_list_ch_1_AW.data" *)output [2:0] m_axi_edge_list_ch_1_AWPROT; - (* RS_HS = "m_axi_edge_list_ch_1_AW.data" *)output [3:0] m_axi_edge_list_ch_1_AWQOS; - (* RS_HS = "m_axi_edge_list_ch_1_AW.ready" *)input m_axi_edge_list_ch_1_AWREADY; - (* RS_HS = "m_axi_edge_list_ch_1_AW.data" *)output [2:0] m_axi_edge_list_ch_1_AWSIZE; - (* RS_HS = "m_axi_edge_list_ch_1_AW.valid" *)output m_axi_edge_list_ch_1_AWVALID; - (* RS_HS = "m_axi_edge_list_ch_1_B.data" *)input [0:0] m_axi_edge_list_ch_1_BID; - (* RS_HS = "m_axi_edge_list_ch_1_B.ready" *)output m_axi_edge_list_ch_1_BREADY; - (* RS_HS = "m_axi_edge_list_ch_1_B.data" *)input [1:0] m_axi_edge_list_ch_1_BRESP; - (* RS_HS = "m_axi_edge_list_ch_1_B.valid" *)input m_axi_edge_list_ch_1_BVALID; - (* RS_HS = "m_axi_edge_list_ch_1_R.data" *)input [511:0] m_axi_edge_list_ch_1_RDATA; - (* RS_HS = "m_axi_edge_list_ch_1_R.data" *)input [0:0] m_axi_edge_list_ch_1_RID; - (* RS_HS = "m_axi_edge_list_ch_1_R.data" *)input m_axi_edge_list_ch_1_RLAST; - (* RS_HS = "m_axi_edge_list_ch_1_R.ready" *)output m_axi_edge_list_ch_1_RREADY; - (* RS_HS = "m_axi_edge_list_ch_1_R.data" *)input [1:0] m_axi_edge_list_ch_1_RRESP; - (* RS_HS = "m_axi_edge_list_ch_1_R.valid" *)input m_axi_edge_list_ch_1_RVALID; - (* RS_HS = "m_axi_edge_list_ch_1_W.data" *)output [511:0] m_axi_edge_list_ch_1_WDATA; - (* RS_HS = "m_axi_edge_list_ch_1_W.data" *)output m_axi_edge_list_ch_1_WLAST; - (* RS_HS = "m_axi_edge_list_ch_1_W.ready" *)input m_axi_edge_list_ch_1_WREADY; - (* RS_HS = "m_axi_edge_list_ch_1_W.data" *)output [63:0] m_axi_edge_list_ch_1_WSTRB; - (* RS_HS = "m_axi_edge_list_ch_1_W.valid" *)output m_axi_edge_list_ch_1_WVALID; - (* RS_HS = "m_axi_edge_list_ch_2_AR.data" *)output [63:0] m_axi_edge_list_ch_2_ARADDR; - (* RS_HS = "m_axi_edge_list_ch_2_AR.data" *)output [1:0] m_axi_edge_list_ch_2_ARBURST; - (* RS_HS = "m_axi_edge_list_ch_2_AR.data" *)output [3:0] m_axi_edge_list_ch_2_ARCACHE; - (* RS_HS = "m_axi_edge_list_ch_2_AR.data" *)output [0:0] m_axi_edge_list_ch_2_ARID; - (* RS_HS = "m_axi_edge_list_ch_2_AR.data" *)output [7:0] m_axi_edge_list_ch_2_ARLEN; - (* RS_HS = "m_axi_edge_list_ch_2_AR.data" *)output m_axi_edge_list_ch_2_ARLOCK; - (* RS_HS = "m_axi_edge_list_ch_2_AR.data" *)output [2:0] m_axi_edge_list_ch_2_ARPROT; - (* RS_HS = "m_axi_edge_list_ch_2_AR.data" *)output [3:0] m_axi_edge_list_ch_2_ARQOS; - (* RS_HS = "m_axi_edge_list_ch_2_AR.ready" *)input m_axi_edge_list_ch_2_ARREADY; - (* RS_HS = "m_axi_edge_list_ch_2_AR.data" *)output [2:0] m_axi_edge_list_ch_2_ARSIZE; - (* RS_HS = "m_axi_edge_list_ch_2_AR.valid" *)output m_axi_edge_list_ch_2_ARVALID; - (* RS_HS = "m_axi_edge_list_ch_2_AW.data" *)output [63:0] m_axi_edge_list_ch_2_AWADDR; - (* RS_HS = "m_axi_edge_list_ch_2_AW.data" *)output [1:0] m_axi_edge_list_ch_2_AWBURST; - (* RS_HS = "m_axi_edge_list_ch_2_AW.data" *)output [3:0] m_axi_edge_list_ch_2_AWCACHE; - (* RS_HS = "m_axi_edge_list_ch_2_AW.data" *)output [0:0] m_axi_edge_list_ch_2_AWID; - (* RS_HS = "m_axi_edge_list_ch_2_AW.data" *)output [7:0] m_axi_edge_list_ch_2_AWLEN; - (* RS_HS = "m_axi_edge_list_ch_2_AW.data" *)output m_axi_edge_list_ch_2_AWLOCK; - (* RS_HS = "m_axi_edge_list_ch_2_AW.data" *)output [2:0] m_axi_edge_list_ch_2_AWPROT; - (* RS_HS = "m_axi_edge_list_ch_2_AW.data" *)output [3:0] m_axi_edge_list_ch_2_AWQOS; - (* RS_HS = "m_axi_edge_list_ch_2_AW.ready" *)input m_axi_edge_list_ch_2_AWREADY; - (* RS_HS = "m_axi_edge_list_ch_2_AW.data" *)output [2:0] m_axi_edge_list_ch_2_AWSIZE; - (* RS_HS = "m_axi_edge_list_ch_2_AW.valid" *)output m_axi_edge_list_ch_2_AWVALID; - (* RS_HS = "m_axi_edge_list_ch_2_B.data" *)input [0:0] m_axi_edge_list_ch_2_BID; - (* RS_HS = "m_axi_edge_list_ch_2_B.ready" *)output m_axi_edge_list_ch_2_BREADY; - (* RS_HS = "m_axi_edge_list_ch_2_B.data" *)input [1:0] m_axi_edge_list_ch_2_BRESP; - (* RS_HS = "m_axi_edge_list_ch_2_B.valid" *)input m_axi_edge_list_ch_2_BVALID; - (* RS_HS = "m_axi_edge_list_ch_2_R.data" *)input [511:0] m_axi_edge_list_ch_2_RDATA; - (* RS_HS = "m_axi_edge_list_ch_2_R.data" *)input [0:0] m_axi_edge_list_ch_2_RID; - (* RS_HS = "m_axi_edge_list_ch_2_R.data" *)input m_axi_edge_list_ch_2_RLAST; - (* RS_HS = "m_axi_edge_list_ch_2_R.ready" *)output m_axi_edge_list_ch_2_RREADY; - (* RS_HS = "m_axi_edge_list_ch_2_R.data" *)input [1:0] m_axi_edge_list_ch_2_RRESP; - (* RS_HS = "m_axi_edge_list_ch_2_R.valid" *)input m_axi_edge_list_ch_2_RVALID; - (* RS_HS = "m_axi_edge_list_ch_2_W.data" *)output [511:0] m_axi_edge_list_ch_2_WDATA; - (* RS_HS = "m_axi_edge_list_ch_2_W.data" *)output m_axi_edge_list_ch_2_WLAST; - (* RS_HS = "m_axi_edge_list_ch_2_W.ready" *)input m_axi_edge_list_ch_2_WREADY; - (* RS_HS = "m_axi_edge_list_ch_2_W.data" *)output [63:0] m_axi_edge_list_ch_2_WSTRB; - (* RS_HS = "m_axi_edge_list_ch_2_W.valid" *)output m_axi_edge_list_ch_2_WVALID; - (* RS_HS = "m_axi_edge_list_ch_3_AR.data" *)output [63:0] m_axi_edge_list_ch_3_ARADDR; - (* RS_HS = "m_axi_edge_list_ch_3_AR.data" *)output [1:0] m_axi_edge_list_ch_3_ARBURST; - (* RS_HS = "m_axi_edge_list_ch_3_AR.data" *)output [3:0] m_axi_edge_list_ch_3_ARCACHE; - (* RS_HS = "m_axi_edge_list_ch_3_AR.data" *)output [0:0] m_axi_edge_list_ch_3_ARID; - (* RS_HS = "m_axi_edge_list_ch_3_AR.data" *)output [7:0] m_axi_edge_list_ch_3_ARLEN; - (* RS_HS = "m_axi_edge_list_ch_3_AR.data" *)output m_axi_edge_list_ch_3_ARLOCK; - (* RS_HS = "m_axi_edge_list_ch_3_AR.data" *)output [2:0] m_axi_edge_list_ch_3_ARPROT; - (* RS_HS = "m_axi_edge_list_ch_3_AR.data" *)output [3:0] m_axi_edge_list_ch_3_ARQOS; - (* RS_HS = "m_axi_edge_list_ch_3_AR.ready" *)input m_axi_edge_list_ch_3_ARREADY; - (* RS_HS = "m_axi_edge_list_ch_3_AR.data" *)output [2:0] m_axi_edge_list_ch_3_ARSIZE; - (* RS_HS = "m_axi_edge_list_ch_3_AR.valid" *)output m_axi_edge_list_ch_3_ARVALID; - (* RS_HS = "m_axi_edge_list_ch_3_AW.data" *)output [63:0] m_axi_edge_list_ch_3_AWADDR; - (* RS_HS = "m_axi_edge_list_ch_3_AW.data" *)output [1:0] m_axi_edge_list_ch_3_AWBURST; - (* RS_HS = "m_axi_edge_list_ch_3_AW.data" *)output [3:0] m_axi_edge_list_ch_3_AWCACHE; - (* RS_HS = "m_axi_edge_list_ch_3_AW.data" *)output [0:0] m_axi_edge_list_ch_3_AWID; - (* RS_HS = "m_axi_edge_list_ch_3_AW.data" *)output [7:0] m_axi_edge_list_ch_3_AWLEN; - (* RS_HS = "m_axi_edge_list_ch_3_AW.data" *)output m_axi_edge_list_ch_3_AWLOCK; - (* RS_HS = "m_axi_edge_list_ch_3_AW.data" *)output [2:0] m_axi_edge_list_ch_3_AWPROT; - (* RS_HS = "m_axi_edge_list_ch_3_AW.data" *)output [3:0] m_axi_edge_list_ch_3_AWQOS; - (* RS_HS = "m_axi_edge_list_ch_3_AW.ready" *)input m_axi_edge_list_ch_3_AWREADY; - (* RS_HS = "m_axi_edge_list_ch_3_AW.data" *)output [2:0] m_axi_edge_list_ch_3_AWSIZE; - (* RS_HS = "m_axi_edge_list_ch_3_AW.valid" *)output m_axi_edge_list_ch_3_AWVALID; - (* RS_HS = "m_axi_edge_list_ch_3_B.data" *)input [0:0] m_axi_edge_list_ch_3_BID; - (* RS_HS = "m_axi_edge_list_ch_3_B.ready" *)output m_axi_edge_list_ch_3_BREADY; - (* RS_HS = "m_axi_edge_list_ch_3_B.data" *)input [1:0] m_axi_edge_list_ch_3_BRESP; - (* RS_HS = "m_axi_edge_list_ch_3_B.valid" *)input m_axi_edge_list_ch_3_BVALID; - (* RS_HS = "m_axi_edge_list_ch_3_R.data" *)input [511:0] m_axi_edge_list_ch_3_RDATA; - (* RS_HS = "m_axi_edge_list_ch_3_R.data" *)input [0:0] m_axi_edge_list_ch_3_RID; - (* RS_HS = "m_axi_edge_list_ch_3_R.data" *)input m_axi_edge_list_ch_3_RLAST; - (* RS_HS = "m_axi_edge_list_ch_3_R.ready" *)output m_axi_edge_list_ch_3_RREADY; - (* RS_HS = "m_axi_edge_list_ch_3_R.data" *)input [1:0] m_axi_edge_list_ch_3_RRESP; - (* RS_HS = "m_axi_edge_list_ch_3_R.valid" *)input m_axi_edge_list_ch_3_RVALID; - (* RS_HS = "m_axi_edge_list_ch_3_W.data" *)output [511:0] m_axi_edge_list_ch_3_WDATA; - (* RS_HS = "m_axi_edge_list_ch_3_W.data" *)output m_axi_edge_list_ch_3_WLAST; - (* RS_HS = "m_axi_edge_list_ch_3_W.ready" *)input m_axi_edge_list_ch_3_WREADY; - (* RS_HS = "m_axi_edge_list_ch_3_W.data" *)output [63:0] m_axi_edge_list_ch_3_WSTRB; - (* RS_HS = "m_axi_edge_list_ch_3_W.valid" *)output m_axi_edge_list_ch_3_WVALID; - (* RS_HS = "m_axi_edge_list_ch_4_AR.data" *)output [63:0] m_axi_edge_list_ch_4_ARADDR; - (* RS_HS = "m_axi_edge_list_ch_4_AR.data" *)output [1:0] m_axi_edge_list_ch_4_ARBURST; - (* RS_HS = "m_axi_edge_list_ch_4_AR.data" *)output [3:0] m_axi_edge_list_ch_4_ARCACHE; - (* RS_HS = "m_axi_edge_list_ch_4_AR.data" *)output [0:0] m_axi_edge_list_ch_4_ARID; - (* RS_HS = "m_axi_edge_list_ch_4_AR.data" *)output [7:0] m_axi_edge_list_ch_4_ARLEN; - (* RS_HS = "m_axi_edge_list_ch_4_AR.data" *)output m_axi_edge_list_ch_4_ARLOCK; - (* RS_HS = "m_axi_edge_list_ch_4_AR.data" *)output [2:0] m_axi_edge_list_ch_4_ARPROT; - (* RS_HS = "m_axi_edge_list_ch_4_AR.data" *)output [3:0] m_axi_edge_list_ch_4_ARQOS; - (* RS_HS = "m_axi_edge_list_ch_4_AR.ready" *)input m_axi_edge_list_ch_4_ARREADY; - (* RS_HS = "m_axi_edge_list_ch_4_AR.data" *)output [2:0] m_axi_edge_list_ch_4_ARSIZE; - (* RS_HS = "m_axi_edge_list_ch_4_AR.valid" *)output m_axi_edge_list_ch_4_ARVALID; - (* RS_HS = "m_axi_edge_list_ch_4_AW.data" *)output [63:0] m_axi_edge_list_ch_4_AWADDR; - (* RS_HS = "m_axi_edge_list_ch_4_AW.data" *)output [1:0] m_axi_edge_list_ch_4_AWBURST; - (* RS_HS = "m_axi_edge_list_ch_4_AW.data" *)output [3:0] m_axi_edge_list_ch_4_AWCACHE; - (* RS_HS = "m_axi_edge_list_ch_4_AW.data" *)output [0:0] m_axi_edge_list_ch_4_AWID; - (* RS_HS = "m_axi_edge_list_ch_4_AW.data" *)output [7:0] m_axi_edge_list_ch_4_AWLEN; - (* RS_HS = "m_axi_edge_list_ch_4_AW.data" *)output m_axi_edge_list_ch_4_AWLOCK; - (* RS_HS = "m_axi_edge_list_ch_4_AW.data" *)output [2:0] m_axi_edge_list_ch_4_AWPROT; - (* RS_HS = "m_axi_edge_list_ch_4_AW.data" *)output [3:0] m_axi_edge_list_ch_4_AWQOS; - (* RS_HS = "m_axi_edge_list_ch_4_AW.ready" *)input m_axi_edge_list_ch_4_AWREADY; - (* RS_HS = "m_axi_edge_list_ch_4_AW.data" *)output [2:0] m_axi_edge_list_ch_4_AWSIZE; - (* RS_HS = "m_axi_edge_list_ch_4_AW.valid" *)output m_axi_edge_list_ch_4_AWVALID; - (* RS_HS = "m_axi_edge_list_ch_4_B.data" *)input [0:0] m_axi_edge_list_ch_4_BID; - (* RS_HS = "m_axi_edge_list_ch_4_B.ready" *)output m_axi_edge_list_ch_4_BREADY; - (* RS_HS = "m_axi_edge_list_ch_4_B.data" *)input [1:0] m_axi_edge_list_ch_4_BRESP; - (* RS_HS = "m_axi_edge_list_ch_4_B.valid" *)input m_axi_edge_list_ch_4_BVALID; - (* RS_HS = "m_axi_edge_list_ch_4_R.data" *)input [511:0] m_axi_edge_list_ch_4_RDATA; - (* RS_HS = "m_axi_edge_list_ch_4_R.data" *)input [0:0] m_axi_edge_list_ch_4_RID; - (* RS_HS = "m_axi_edge_list_ch_4_R.data" *)input m_axi_edge_list_ch_4_RLAST; - (* RS_HS = "m_axi_edge_list_ch_4_R.ready" *)output m_axi_edge_list_ch_4_RREADY; - (* RS_HS = "m_axi_edge_list_ch_4_R.data" *)input [1:0] m_axi_edge_list_ch_4_RRESP; - (* RS_HS = "m_axi_edge_list_ch_4_R.valid" *)input m_axi_edge_list_ch_4_RVALID; - (* RS_HS = "m_axi_edge_list_ch_4_W.data" *)output [511:0] m_axi_edge_list_ch_4_WDATA; - (* RS_HS = "m_axi_edge_list_ch_4_W.data" *)output m_axi_edge_list_ch_4_WLAST; - (* RS_HS = "m_axi_edge_list_ch_4_W.ready" *)input m_axi_edge_list_ch_4_WREADY; - (* RS_HS = "m_axi_edge_list_ch_4_W.data" *)output [63:0] m_axi_edge_list_ch_4_WSTRB; - (* RS_HS = "m_axi_edge_list_ch_4_W.valid" *)output m_axi_edge_list_ch_4_WVALID; - (* RS_HS = "m_axi_edge_list_ch_5_AR.data" *)output [63:0] m_axi_edge_list_ch_5_ARADDR; - (* RS_HS = "m_axi_edge_list_ch_5_AR.data" *)output [1:0] m_axi_edge_list_ch_5_ARBURST; - (* RS_HS = "m_axi_edge_list_ch_5_AR.data" *)output [3:0] m_axi_edge_list_ch_5_ARCACHE; - (* RS_HS = "m_axi_edge_list_ch_5_AR.data" *)output [0:0] m_axi_edge_list_ch_5_ARID; - (* RS_HS = "m_axi_edge_list_ch_5_AR.data" *)output [7:0] m_axi_edge_list_ch_5_ARLEN; - (* RS_HS = "m_axi_edge_list_ch_5_AR.data" *)output m_axi_edge_list_ch_5_ARLOCK; - (* RS_HS = "m_axi_edge_list_ch_5_AR.data" *)output [2:0] m_axi_edge_list_ch_5_ARPROT; - (* RS_HS = "m_axi_edge_list_ch_5_AR.data" *)output [3:0] m_axi_edge_list_ch_5_ARQOS; - (* RS_HS = "m_axi_edge_list_ch_5_AR.ready" *)input m_axi_edge_list_ch_5_ARREADY; - (* RS_HS = "m_axi_edge_list_ch_5_AR.data" *)output [2:0] m_axi_edge_list_ch_5_ARSIZE; - (* RS_HS = "m_axi_edge_list_ch_5_AR.valid" *)output m_axi_edge_list_ch_5_ARVALID; - (* RS_HS = "m_axi_edge_list_ch_5_AW.data" *)output [63:0] m_axi_edge_list_ch_5_AWADDR; - (* RS_HS = "m_axi_edge_list_ch_5_AW.data" *)output [1:0] m_axi_edge_list_ch_5_AWBURST; - (* RS_HS = "m_axi_edge_list_ch_5_AW.data" *)output [3:0] m_axi_edge_list_ch_5_AWCACHE; - (* RS_HS = "m_axi_edge_list_ch_5_AW.data" *)output [0:0] m_axi_edge_list_ch_5_AWID; - (* RS_HS = "m_axi_edge_list_ch_5_AW.data" *)output [7:0] m_axi_edge_list_ch_5_AWLEN; - (* RS_HS = "m_axi_edge_list_ch_5_AW.data" *)output m_axi_edge_list_ch_5_AWLOCK; - (* RS_HS = "m_axi_edge_list_ch_5_AW.data" *)output [2:0] m_axi_edge_list_ch_5_AWPROT; - (* RS_HS = "m_axi_edge_list_ch_5_AW.data" *)output [3:0] m_axi_edge_list_ch_5_AWQOS; - (* RS_HS = "m_axi_edge_list_ch_5_AW.ready" *)input m_axi_edge_list_ch_5_AWREADY; - (* RS_HS = "m_axi_edge_list_ch_5_AW.data" *)output [2:0] m_axi_edge_list_ch_5_AWSIZE; - (* RS_HS = "m_axi_edge_list_ch_5_AW.valid" *)output m_axi_edge_list_ch_5_AWVALID; - (* RS_HS = "m_axi_edge_list_ch_5_B.data" *)input [0:0] m_axi_edge_list_ch_5_BID; - (* RS_HS = "m_axi_edge_list_ch_5_B.ready" *)output m_axi_edge_list_ch_5_BREADY; - (* RS_HS = "m_axi_edge_list_ch_5_B.data" *)input [1:0] m_axi_edge_list_ch_5_BRESP; - (* RS_HS = "m_axi_edge_list_ch_5_B.valid" *)input m_axi_edge_list_ch_5_BVALID; - (* RS_HS = "m_axi_edge_list_ch_5_R.data" *)input [511:0] m_axi_edge_list_ch_5_RDATA; - (* RS_HS = "m_axi_edge_list_ch_5_R.data" *)input [0:0] m_axi_edge_list_ch_5_RID; - (* RS_HS = "m_axi_edge_list_ch_5_R.data" *)input m_axi_edge_list_ch_5_RLAST; - (* RS_HS = "m_axi_edge_list_ch_5_R.ready" *)output m_axi_edge_list_ch_5_RREADY; - (* RS_HS = "m_axi_edge_list_ch_5_R.data" *)input [1:0] m_axi_edge_list_ch_5_RRESP; - (* RS_HS = "m_axi_edge_list_ch_5_R.valid" *)input m_axi_edge_list_ch_5_RVALID; - (* RS_HS = "m_axi_edge_list_ch_5_W.data" *)output [511:0] m_axi_edge_list_ch_5_WDATA; - (* RS_HS = "m_axi_edge_list_ch_5_W.data" *)output m_axi_edge_list_ch_5_WLAST; - (* RS_HS = "m_axi_edge_list_ch_5_W.ready" *)input m_axi_edge_list_ch_5_WREADY; - (* RS_HS = "m_axi_edge_list_ch_5_W.data" *)output [63:0] m_axi_edge_list_ch_5_WSTRB; - (* RS_HS = "m_axi_edge_list_ch_5_W.valid" *)output m_axi_edge_list_ch_5_WVALID; - (* RS_HS = "m_axi_edge_list_ch_6_AR.data" *)output [63:0] m_axi_edge_list_ch_6_ARADDR; - (* RS_HS = "m_axi_edge_list_ch_6_AR.data" *)output [1:0] m_axi_edge_list_ch_6_ARBURST; - (* RS_HS = "m_axi_edge_list_ch_6_AR.data" *)output [3:0] m_axi_edge_list_ch_6_ARCACHE; - (* RS_HS = "m_axi_edge_list_ch_6_AR.data" *)output [0:0] m_axi_edge_list_ch_6_ARID; - (* RS_HS = "m_axi_edge_list_ch_6_AR.data" *)output [7:0] m_axi_edge_list_ch_6_ARLEN; - (* RS_HS = "m_axi_edge_list_ch_6_AR.data" *)output m_axi_edge_list_ch_6_ARLOCK; - (* RS_HS = "m_axi_edge_list_ch_6_AR.data" *)output [2:0] m_axi_edge_list_ch_6_ARPROT; - (* RS_HS = "m_axi_edge_list_ch_6_AR.data" *)output [3:0] m_axi_edge_list_ch_6_ARQOS; - (* RS_HS = "m_axi_edge_list_ch_6_AR.ready" *)input m_axi_edge_list_ch_6_ARREADY; - (* RS_HS = "m_axi_edge_list_ch_6_AR.data" *)output [2:0] m_axi_edge_list_ch_6_ARSIZE; - (* RS_HS = "m_axi_edge_list_ch_6_AR.valid" *)output m_axi_edge_list_ch_6_ARVALID; - (* RS_HS = "m_axi_edge_list_ch_6_AW.data" *)output [63:0] m_axi_edge_list_ch_6_AWADDR; - (* RS_HS = "m_axi_edge_list_ch_6_AW.data" *)output [1:0] m_axi_edge_list_ch_6_AWBURST; - (* RS_HS = "m_axi_edge_list_ch_6_AW.data" *)output [3:0] m_axi_edge_list_ch_6_AWCACHE; - (* RS_HS = "m_axi_edge_list_ch_6_AW.data" *)output [0:0] m_axi_edge_list_ch_6_AWID; - (* RS_HS = "m_axi_edge_list_ch_6_AW.data" *)output [7:0] m_axi_edge_list_ch_6_AWLEN; - (* RS_HS = "m_axi_edge_list_ch_6_AW.data" *)output m_axi_edge_list_ch_6_AWLOCK; - (* RS_HS = "m_axi_edge_list_ch_6_AW.data" *)output [2:0] m_axi_edge_list_ch_6_AWPROT; - (* RS_HS = "m_axi_edge_list_ch_6_AW.data" *)output [3:0] m_axi_edge_list_ch_6_AWQOS; - (* RS_HS = "m_axi_edge_list_ch_6_AW.ready" *)input m_axi_edge_list_ch_6_AWREADY; - (* RS_HS = "m_axi_edge_list_ch_6_AW.data" *)output [2:0] m_axi_edge_list_ch_6_AWSIZE; - (* RS_HS = "m_axi_edge_list_ch_6_AW.valid" *)output m_axi_edge_list_ch_6_AWVALID; - (* RS_HS = "m_axi_edge_list_ch_6_B.data" *)input [0:0] m_axi_edge_list_ch_6_BID; - (* RS_HS = "m_axi_edge_list_ch_6_B.ready" *)output m_axi_edge_list_ch_6_BREADY; - (* RS_HS = "m_axi_edge_list_ch_6_B.data" *)input [1:0] m_axi_edge_list_ch_6_BRESP; - (* RS_HS = "m_axi_edge_list_ch_6_B.valid" *)input m_axi_edge_list_ch_6_BVALID; - (* RS_HS = "m_axi_edge_list_ch_6_R.data" *)input [511:0] m_axi_edge_list_ch_6_RDATA; - (* RS_HS = "m_axi_edge_list_ch_6_R.data" *)input [0:0] m_axi_edge_list_ch_6_RID; - (* RS_HS = "m_axi_edge_list_ch_6_R.data" *)input m_axi_edge_list_ch_6_RLAST; - (* RS_HS = "m_axi_edge_list_ch_6_R.ready" *)output m_axi_edge_list_ch_6_RREADY; - (* RS_HS = "m_axi_edge_list_ch_6_R.data" *)input [1:0] m_axi_edge_list_ch_6_RRESP; - (* RS_HS = "m_axi_edge_list_ch_6_R.valid" *)input m_axi_edge_list_ch_6_RVALID; - (* RS_HS = "m_axi_edge_list_ch_6_W.data" *)output [511:0] m_axi_edge_list_ch_6_WDATA; - (* RS_HS = "m_axi_edge_list_ch_6_W.data" *)output m_axi_edge_list_ch_6_WLAST; - (* RS_HS = "m_axi_edge_list_ch_6_W.ready" *)input m_axi_edge_list_ch_6_WREADY; - (* RS_HS = "m_axi_edge_list_ch_6_W.data" *)output [63:0] m_axi_edge_list_ch_6_WSTRB; - (* RS_HS = "m_axi_edge_list_ch_6_W.valid" *)output m_axi_edge_list_ch_6_WVALID; - (* RS_HS = "m_axi_edge_list_ch_7_AR.data" *)output [63:0] m_axi_edge_list_ch_7_ARADDR; - (* RS_HS = "m_axi_edge_list_ch_7_AR.data" *)output [1:0] m_axi_edge_list_ch_7_ARBURST; - (* RS_HS = "m_axi_edge_list_ch_7_AR.data" *)output [3:0] m_axi_edge_list_ch_7_ARCACHE; - (* RS_HS = "m_axi_edge_list_ch_7_AR.data" *)output [0:0] m_axi_edge_list_ch_7_ARID; - (* RS_HS = "m_axi_edge_list_ch_7_AR.data" *)output [7:0] m_axi_edge_list_ch_7_ARLEN; - (* RS_HS = "m_axi_edge_list_ch_7_AR.data" *)output m_axi_edge_list_ch_7_ARLOCK; - (* RS_HS = "m_axi_edge_list_ch_7_AR.data" *)output [2:0] m_axi_edge_list_ch_7_ARPROT; - (* RS_HS = "m_axi_edge_list_ch_7_AR.data" *)output [3:0] m_axi_edge_list_ch_7_ARQOS; - (* RS_HS = "m_axi_edge_list_ch_7_AR.ready" *)input m_axi_edge_list_ch_7_ARREADY; - (* RS_HS = "m_axi_edge_list_ch_7_AR.data" *)output [2:0] m_axi_edge_list_ch_7_ARSIZE; - (* RS_HS = "m_axi_edge_list_ch_7_AR.valid" *)output m_axi_edge_list_ch_7_ARVALID; - (* RS_HS = "m_axi_edge_list_ch_7_AW.data" *)output [63:0] m_axi_edge_list_ch_7_AWADDR; - (* RS_HS = "m_axi_edge_list_ch_7_AW.data" *)output [1:0] m_axi_edge_list_ch_7_AWBURST; - (* RS_HS = "m_axi_edge_list_ch_7_AW.data" *)output [3:0] m_axi_edge_list_ch_7_AWCACHE; - (* RS_HS = "m_axi_edge_list_ch_7_AW.data" *)output [0:0] m_axi_edge_list_ch_7_AWID; - (* RS_HS = "m_axi_edge_list_ch_7_AW.data" *)output [7:0] m_axi_edge_list_ch_7_AWLEN; - (* RS_HS = "m_axi_edge_list_ch_7_AW.data" *)output m_axi_edge_list_ch_7_AWLOCK; - (* RS_HS = "m_axi_edge_list_ch_7_AW.data" *)output [2:0] m_axi_edge_list_ch_7_AWPROT; - (* RS_HS = "m_axi_edge_list_ch_7_AW.data" *)output [3:0] m_axi_edge_list_ch_7_AWQOS; - (* RS_HS = "m_axi_edge_list_ch_7_AW.ready" *)input m_axi_edge_list_ch_7_AWREADY; - (* RS_HS = "m_axi_edge_list_ch_7_AW.data" *)output [2:0] m_axi_edge_list_ch_7_AWSIZE; - (* RS_HS = "m_axi_edge_list_ch_7_AW.valid" *)output m_axi_edge_list_ch_7_AWVALID; - (* RS_HS = "m_axi_edge_list_ch_7_B.data" *)input [0:0] m_axi_edge_list_ch_7_BID; - (* RS_HS = "m_axi_edge_list_ch_7_B.ready" *)output m_axi_edge_list_ch_7_BREADY; - (* RS_HS = "m_axi_edge_list_ch_7_B.data" *)input [1:0] m_axi_edge_list_ch_7_BRESP; - (* RS_HS = "m_axi_edge_list_ch_7_B.valid" *)input m_axi_edge_list_ch_7_BVALID; - (* RS_HS = "m_axi_edge_list_ch_7_R.data" *)input [511:0] m_axi_edge_list_ch_7_RDATA; - (* RS_HS = "m_axi_edge_list_ch_7_R.data" *)input [0:0] m_axi_edge_list_ch_7_RID; - (* RS_HS = "m_axi_edge_list_ch_7_R.data" *)input m_axi_edge_list_ch_7_RLAST; - (* RS_HS = "m_axi_edge_list_ch_7_R.ready" *)output m_axi_edge_list_ch_7_RREADY; - (* RS_HS = "m_axi_edge_list_ch_7_R.data" *)input [1:0] m_axi_edge_list_ch_7_RRESP; - (* RS_HS = "m_axi_edge_list_ch_7_R.valid" *)input m_axi_edge_list_ch_7_RVALID; - (* RS_HS = "m_axi_edge_list_ch_7_W.data" *)output [511:0] m_axi_edge_list_ch_7_WDATA; - (* RS_HS = "m_axi_edge_list_ch_7_W.data" *)output m_axi_edge_list_ch_7_WLAST; - (* RS_HS = "m_axi_edge_list_ch_7_W.ready" *)input m_axi_edge_list_ch_7_WREADY; - (* RS_HS = "m_axi_edge_list_ch_7_W.data" *)output [63:0] m_axi_edge_list_ch_7_WSTRB; - (* RS_HS = "m_axi_edge_list_ch_7_W.valid" *)output m_axi_edge_list_ch_7_WVALID; - (* RS_HS = "m_axi_mat_B_ch_0_AR.data" *)output [63:0] m_axi_mat_B_ch_0_ARADDR; - (* RS_HS = "m_axi_mat_B_ch_0_AR.data" *)output [1:0] m_axi_mat_B_ch_0_ARBURST; - (* RS_HS = "m_axi_mat_B_ch_0_AR.data" *)output [3:0] m_axi_mat_B_ch_0_ARCACHE; - (* RS_HS = "m_axi_mat_B_ch_0_AR.data" *)output [0:0] m_axi_mat_B_ch_0_ARID; - (* RS_HS = "m_axi_mat_B_ch_0_AR.data" *)output [7:0] m_axi_mat_B_ch_0_ARLEN; - (* RS_HS = "m_axi_mat_B_ch_0_AR.data" *)output m_axi_mat_B_ch_0_ARLOCK; - (* RS_HS = "m_axi_mat_B_ch_0_AR.data" *)output [2:0] m_axi_mat_B_ch_0_ARPROT; - (* RS_HS = "m_axi_mat_B_ch_0_AR.data" *)output [3:0] m_axi_mat_B_ch_0_ARQOS; - (* RS_HS = "m_axi_mat_B_ch_0_AR.ready" *)input m_axi_mat_B_ch_0_ARREADY; - (* RS_HS = "m_axi_mat_B_ch_0_AR.data" *)output [2:0] m_axi_mat_B_ch_0_ARSIZE; - (* RS_HS = "m_axi_mat_B_ch_0_AR.valid" *)output m_axi_mat_B_ch_0_ARVALID; - (* RS_HS = "m_axi_mat_B_ch_0_AW.data" *)output [63:0] m_axi_mat_B_ch_0_AWADDR; - (* RS_HS = "m_axi_mat_B_ch_0_AW.data" *)output [1:0] m_axi_mat_B_ch_0_AWBURST; - (* RS_HS = "m_axi_mat_B_ch_0_AW.data" *)output [3:0] m_axi_mat_B_ch_0_AWCACHE; - (* RS_HS = "m_axi_mat_B_ch_0_AW.data" *)output [0:0] m_axi_mat_B_ch_0_AWID; - (* RS_HS = "m_axi_mat_B_ch_0_AW.data" *)output [7:0] m_axi_mat_B_ch_0_AWLEN; - (* RS_HS = "m_axi_mat_B_ch_0_AW.data" *)output m_axi_mat_B_ch_0_AWLOCK; - (* RS_HS = "m_axi_mat_B_ch_0_AW.data" *)output [2:0] m_axi_mat_B_ch_0_AWPROT; - (* RS_HS = "m_axi_mat_B_ch_0_AW.data" *)output [3:0] m_axi_mat_B_ch_0_AWQOS; - (* RS_HS = "m_axi_mat_B_ch_0_AW.ready" *)input m_axi_mat_B_ch_0_AWREADY; - (* RS_HS = "m_axi_mat_B_ch_0_AW.data" *)output [2:0] m_axi_mat_B_ch_0_AWSIZE; - (* RS_HS = "m_axi_mat_B_ch_0_AW.valid" *)output m_axi_mat_B_ch_0_AWVALID; - (* RS_HS = "m_axi_mat_B_ch_0_B.data" *)input [0:0] m_axi_mat_B_ch_0_BID; - (* RS_HS = "m_axi_mat_B_ch_0_B.ready" *)output m_axi_mat_B_ch_0_BREADY; - (* RS_HS = "m_axi_mat_B_ch_0_B.data" *)input [1:0] m_axi_mat_B_ch_0_BRESP; - (* RS_HS = "m_axi_mat_B_ch_0_B.valid" *)input m_axi_mat_B_ch_0_BVALID; - (* RS_HS = "m_axi_mat_B_ch_0_R.data" *)input [511:0] m_axi_mat_B_ch_0_RDATA; - (* RS_HS = "m_axi_mat_B_ch_0_R.data" *)input [0:0] m_axi_mat_B_ch_0_RID; - (* RS_HS = "m_axi_mat_B_ch_0_R.data" *)input m_axi_mat_B_ch_0_RLAST; - (* RS_HS = "m_axi_mat_B_ch_0_R.ready" *)output m_axi_mat_B_ch_0_RREADY; - (* RS_HS = "m_axi_mat_B_ch_0_R.data" *)input [1:0] m_axi_mat_B_ch_0_RRESP; - (* RS_HS = "m_axi_mat_B_ch_0_R.valid" *)input m_axi_mat_B_ch_0_RVALID; - (* RS_HS = "m_axi_mat_B_ch_0_W.data" *)output [511:0] m_axi_mat_B_ch_0_WDATA; - (* RS_HS = "m_axi_mat_B_ch_0_W.data" *)output m_axi_mat_B_ch_0_WLAST; - (* RS_HS = "m_axi_mat_B_ch_0_W.ready" *)input m_axi_mat_B_ch_0_WREADY; - (* RS_HS = "m_axi_mat_B_ch_0_W.data" *)output [63:0] m_axi_mat_B_ch_0_WSTRB; - (* RS_HS = "m_axi_mat_B_ch_0_W.valid" *)output m_axi_mat_B_ch_0_WVALID; - (* RS_HS = "m_axi_mat_B_ch_1_AR.data" *)output [63:0] m_axi_mat_B_ch_1_ARADDR; - (* RS_HS = "m_axi_mat_B_ch_1_AR.data" *)output [1:0] m_axi_mat_B_ch_1_ARBURST; - (* RS_HS = "m_axi_mat_B_ch_1_AR.data" *)output [3:0] m_axi_mat_B_ch_1_ARCACHE; - (* RS_HS = "m_axi_mat_B_ch_1_AR.data" *)output [0:0] m_axi_mat_B_ch_1_ARID; - (* RS_HS = "m_axi_mat_B_ch_1_AR.data" *)output [7:0] m_axi_mat_B_ch_1_ARLEN; - (* RS_HS = "m_axi_mat_B_ch_1_AR.data" *)output m_axi_mat_B_ch_1_ARLOCK; - (* RS_HS = "m_axi_mat_B_ch_1_AR.data" *)output [2:0] m_axi_mat_B_ch_1_ARPROT; - (* RS_HS = "m_axi_mat_B_ch_1_AR.data" *)output [3:0] m_axi_mat_B_ch_1_ARQOS; - (* RS_HS = "m_axi_mat_B_ch_1_AR.ready" *)input m_axi_mat_B_ch_1_ARREADY; - (* RS_HS = "m_axi_mat_B_ch_1_AR.data" *)output [2:0] m_axi_mat_B_ch_1_ARSIZE; - (* RS_HS = "m_axi_mat_B_ch_1_AR.valid" *)output m_axi_mat_B_ch_1_ARVALID; - (* RS_HS = "m_axi_mat_B_ch_1_AW.data" *)output [63:0] m_axi_mat_B_ch_1_AWADDR; - (* RS_HS = "m_axi_mat_B_ch_1_AW.data" *)output [1:0] m_axi_mat_B_ch_1_AWBURST; - (* RS_HS = "m_axi_mat_B_ch_1_AW.data" *)output [3:0] m_axi_mat_B_ch_1_AWCACHE; - (* RS_HS = "m_axi_mat_B_ch_1_AW.data" *)output [0:0] m_axi_mat_B_ch_1_AWID; - (* RS_HS = "m_axi_mat_B_ch_1_AW.data" *)output [7:0] m_axi_mat_B_ch_1_AWLEN; - (* RS_HS = "m_axi_mat_B_ch_1_AW.data" *)output m_axi_mat_B_ch_1_AWLOCK; - (* RS_HS = "m_axi_mat_B_ch_1_AW.data" *)output [2:0] m_axi_mat_B_ch_1_AWPROT; - (* RS_HS = "m_axi_mat_B_ch_1_AW.data" *)output [3:0] m_axi_mat_B_ch_1_AWQOS; - (* RS_HS = "m_axi_mat_B_ch_1_AW.ready" *)input m_axi_mat_B_ch_1_AWREADY; - (* RS_HS = "m_axi_mat_B_ch_1_AW.data" *)output [2:0] m_axi_mat_B_ch_1_AWSIZE; - (* RS_HS = "m_axi_mat_B_ch_1_AW.valid" *)output m_axi_mat_B_ch_1_AWVALID; - (* RS_HS = "m_axi_mat_B_ch_1_B.data" *)input [0:0] m_axi_mat_B_ch_1_BID; - (* RS_HS = "m_axi_mat_B_ch_1_B.ready" *)output m_axi_mat_B_ch_1_BREADY; - (* RS_HS = "m_axi_mat_B_ch_1_B.data" *)input [1:0] m_axi_mat_B_ch_1_BRESP; - (* RS_HS = "m_axi_mat_B_ch_1_B.valid" *)input m_axi_mat_B_ch_1_BVALID; - (* RS_HS = "m_axi_mat_B_ch_1_R.data" *)input [511:0] m_axi_mat_B_ch_1_RDATA; - (* RS_HS = "m_axi_mat_B_ch_1_R.data" *)input [0:0] m_axi_mat_B_ch_1_RID; - (* RS_HS = "m_axi_mat_B_ch_1_R.data" *)input m_axi_mat_B_ch_1_RLAST; - (* RS_HS = "m_axi_mat_B_ch_1_R.ready" *)output m_axi_mat_B_ch_1_RREADY; - (* RS_HS = "m_axi_mat_B_ch_1_R.data" *)input [1:0] m_axi_mat_B_ch_1_RRESP; - (* RS_HS = "m_axi_mat_B_ch_1_R.valid" *)input m_axi_mat_B_ch_1_RVALID; - (* RS_HS = "m_axi_mat_B_ch_1_W.data" *)output [511:0] m_axi_mat_B_ch_1_WDATA; - (* RS_HS = "m_axi_mat_B_ch_1_W.data" *)output m_axi_mat_B_ch_1_WLAST; - (* RS_HS = "m_axi_mat_B_ch_1_W.ready" *)input m_axi_mat_B_ch_1_WREADY; - (* RS_HS = "m_axi_mat_B_ch_1_W.data" *)output [63:0] m_axi_mat_B_ch_1_WSTRB; - (* RS_HS = "m_axi_mat_B_ch_1_W.valid" *)output m_axi_mat_B_ch_1_WVALID; - (* RS_HS = "m_axi_mat_B_ch_2_AR.data" *)output [63:0] m_axi_mat_B_ch_2_ARADDR; - (* RS_HS = "m_axi_mat_B_ch_2_AR.data" *)output [1:0] m_axi_mat_B_ch_2_ARBURST; - (* RS_HS = "m_axi_mat_B_ch_2_AR.data" *)output [3:0] m_axi_mat_B_ch_2_ARCACHE; - (* RS_HS = "m_axi_mat_B_ch_2_AR.data" *)output [0:0] m_axi_mat_B_ch_2_ARID; - (* RS_HS = "m_axi_mat_B_ch_2_AR.data" *)output [7:0] m_axi_mat_B_ch_2_ARLEN; - (* RS_HS = "m_axi_mat_B_ch_2_AR.data" *)output m_axi_mat_B_ch_2_ARLOCK; - (* RS_HS = "m_axi_mat_B_ch_2_AR.data" *)output [2:0] m_axi_mat_B_ch_2_ARPROT; - (* RS_HS = "m_axi_mat_B_ch_2_AR.data" *)output [3:0] m_axi_mat_B_ch_2_ARQOS; - (* RS_HS = "m_axi_mat_B_ch_2_AR.ready" *)input m_axi_mat_B_ch_2_ARREADY; - (* RS_HS = "m_axi_mat_B_ch_2_AR.data" *)output [2:0] m_axi_mat_B_ch_2_ARSIZE; - (* RS_HS = "m_axi_mat_B_ch_2_AR.valid" *)output m_axi_mat_B_ch_2_ARVALID; - (* RS_HS = "m_axi_mat_B_ch_2_AW.data" *)output [63:0] m_axi_mat_B_ch_2_AWADDR; - (* RS_HS = "m_axi_mat_B_ch_2_AW.data" *)output [1:0] m_axi_mat_B_ch_2_AWBURST; - (* RS_HS = "m_axi_mat_B_ch_2_AW.data" *)output [3:0] m_axi_mat_B_ch_2_AWCACHE; - (* RS_HS = "m_axi_mat_B_ch_2_AW.data" *)output [0:0] m_axi_mat_B_ch_2_AWID; - (* RS_HS = "m_axi_mat_B_ch_2_AW.data" *)output [7:0] m_axi_mat_B_ch_2_AWLEN; - (* RS_HS = "m_axi_mat_B_ch_2_AW.data" *)output m_axi_mat_B_ch_2_AWLOCK; - (* RS_HS = "m_axi_mat_B_ch_2_AW.data" *)output [2:0] m_axi_mat_B_ch_2_AWPROT; - (* RS_HS = "m_axi_mat_B_ch_2_AW.data" *)output [3:0] m_axi_mat_B_ch_2_AWQOS; - (* RS_HS = "m_axi_mat_B_ch_2_AW.ready" *)input m_axi_mat_B_ch_2_AWREADY; - (* RS_HS = "m_axi_mat_B_ch_2_AW.data" *)output [2:0] m_axi_mat_B_ch_2_AWSIZE; - (* RS_HS = "m_axi_mat_B_ch_2_AW.valid" *)output m_axi_mat_B_ch_2_AWVALID; - (* RS_HS = "m_axi_mat_B_ch_2_B.data" *)input [0:0] m_axi_mat_B_ch_2_BID; - (* RS_HS = "m_axi_mat_B_ch_2_B.ready" *)output m_axi_mat_B_ch_2_BREADY; - (* RS_HS = "m_axi_mat_B_ch_2_B.data" *)input [1:0] m_axi_mat_B_ch_2_BRESP; - (* RS_HS = "m_axi_mat_B_ch_2_B.valid" *)input m_axi_mat_B_ch_2_BVALID; - (* RS_HS = "m_axi_mat_B_ch_2_R.data" *)input [511:0] m_axi_mat_B_ch_2_RDATA; - (* RS_HS = "m_axi_mat_B_ch_2_R.data" *)input [0:0] m_axi_mat_B_ch_2_RID; - (* RS_HS = "m_axi_mat_B_ch_2_R.data" *)input m_axi_mat_B_ch_2_RLAST; - (* RS_HS = "m_axi_mat_B_ch_2_R.ready" *)output m_axi_mat_B_ch_2_RREADY; - (* RS_HS = "m_axi_mat_B_ch_2_R.data" *)input [1:0] m_axi_mat_B_ch_2_RRESP; - (* RS_HS = "m_axi_mat_B_ch_2_R.valid" *)input m_axi_mat_B_ch_2_RVALID; - (* RS_HS = "m_axi_mat_B_ch_2_W.data" *)output [511:0] m_axi_mat_B_ch_2_WDATA; - (* RS_HS = "m_axi_mat_B_ch_2_W.data" *)output m_axi_mat_B_ch_2_WLAST; - (* RS_HS = "m_axi_mat_B_ch_2_W.ready" *)input m_axi_mat_B_ch_2_WREADY; - (* RS_HS = "m_axi_mat_B_ch_2_W.data" *)output [63:0] m_axi_mat_B_ch_2_WSTRB; - (* RS_HS = "m_axi_mat_B_ch_2_W.valid" *)output m_axi_mat_B_ch_2_WVALID; - (* RS_HS = "m_axi_mat_B_ch_3_AR.data" *)output [63:0] m_axi_mat_B_ch_3_ARADDR; - (* RS_HS = "m_axi_mat_B_ch_3_AR.data" *)output [1:0] m_axi_mat_B_ch_3_ARBURST; - (* RS_HS = "m_axi_mat_B_ch_3_AR.data" *)output [3:0] m_axi_mat_B_ch_3_ARCACHE; - (* RS_HS = "m_axi_mat_B_ch_3_AR.data" *)output [0:0] m_axi_mat_B_ch_3_ARID; - (* RS_HS = "m_axi_mat_B_ch_3_AR.data" *)output [7:0] m_axi_mat_B_ch_3_ARLEN; - (* RS_HS = "m_axi_mat_B_ch_3_AR.data" *)output m_axi_mat_B_ch_3_ARLOCK; - (* RS_HS = "m_axi_mat_B_ch_3_AR.data" *)output [2:0] m_axi_mat_B_ch_3_ARPROT; - (* RS_HS = "m_axi_mat_B_ch_3_AR.data" *)output [3:0] m_axi_mat_B_ch_3_ARQOS; - (* RS_HS = "m_axi_mat_B_ch_3_AR.ready" *)input m_axi_mat_B_ch_3_ARREADY; - (* RS_HS = "m_axi_mat_B_ch_3_AR.data" *)output [2:0] m_axi_mat_B_ch_3_ARSIZE; - (* RS_HS = "m_axi_mat_B_ch_3_AR.valid" *)output m_axi_mat_B_ch_3_ARVALID; - (* RS_HS = "m_axi_mat_B_ch_3_AW.data" *)output [63:0] m_axi_mat_B_ch_3_AWADDR; - (* RS_HS = "m_axi_mat_B_ch_3_AW.data" *)output [1:0] m_axi_mat_B_ch_3_AWBURST; - (* RS_HS = "m_axi_mat_B_ch_3_AW.data" *)output [3:0] m_axi_mat_B_ch_3_AWCACHE; - (* RS_HS = "m_axi_mat_B_ch_3_AW.data" *)output [0:0] m_axi_mat_B_ch_3_AWID; - (* RS_HS = "m_axi_mat_B_ch_3_AW.data" *)output [7:0] m_axi_mat_B_ch_3_AWLEN; - (* RS_HS = "m_axi_mat_B_ch_3_AW.data" *)output m_axi_mat_B_ch_3_AWLOCK; - (* RS_HS = "m_axi_mat_B_ch_3_AW.data" *)output [2:0] m_axi_mat_B_ch_3_AWPROT; - (* RS_HS = "m_axi_mat_B_ch_3_AW.data" *)output [3:0] m_axi_mat_B_ch_3_AWQOS; - (* RS_HS = "m_axi_mat_B_ch_3_AW.ready" *)input m_axi_mat_B_ch_3_AWREADY; - (* RS_HS = "m_axi_mat_B_ch_3_AW.data" *)output [2:0] m_axi_mat_B_ch_3_AWSIZE; - (* RS_HS = "m_axi_mat_B_ch_3_AW.valid" *)output m_axi_mat_B_ch_3_AWVALID; - (* RS_HS = "m_axi_mat_B_ch_3_B.data" *)input [0:0] m_axi_mat_B_ch_3_BID; - (* RS_HS = "m_axi_mat_B_ch_3_B.ready" *)output m_axi_mat_B_ch_3_BREADY; - (* RS_HS = "m_axi_mat_B_ch_3_B.data" *)input [1:0] m_axi_mat_B_ch_3_BRESP; - (* RS_HS = "m_axi_mat_B_ch_3_B.valid" *)input m_axi_mat_B_ch_3_BVALID; - (* RS_HS = "m_axi_mat_B_ch_3_R.data" *)input [511:0] m_axi_mat_B_ch_3_RDATA; - (* RS_HS = "m_axi_mat_B_ch_3_R.data" *)input [0:0] m_axi_mat_B_ch_3_RID; - (* RS_HS = "m_axi_mat_B_ch_3_R.data" *)input m_axi_mat_B_ch_3_RLAST; - (* RS_HS = "m_axi_mat_B_ch_3_R.ready" *)output m_axi_mat_B_ch_3_RREADY; - (* RS_HS = "m_axi_mat_B_ch_3_R.data" *)input [1:0] m_axi_mat_B_ch_3_RRESP; - (* RS_HS = "m_axi_mat_B_ch_3_R.valid" *)input m_axi_mat_B_ch_3_RVALID; - (* RS_HS = "m_axi_mat_B_ch_3_W.data" *)output [511:0] m_axi_mat_B_ch_3_WDATA; - (* RS_HS = "m_axi_mat_B_ch_3_W.data" *)output m_axi_mat_B_ch_3_WLAST; - (* RS_HS = "m_axi_mat_B_ch_3_W.ready" *)input m_axi_mat_B_ch_3_WREADY; - (* RS_HS = "m_axi_mat_B_ch_3_W.data" *)output [63:0] m_axi_mat_B_ch_3_WSTRB; - (* RS_HS = "m_axi_mat_B_ch_3_W.valid" *)output m_axi_mat_B_ch_3_WVALID; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.data" *)output [63:0] m_axi_mat_C_ch_in_0_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.data" *)output [1:0] m_axi_mat_C_ch_in_0_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.data" *)output [3:0] m_axi_mat_C_ch_in_0_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.data" *)output [0:0] m_axi_mat_C_ch_in_0_ARID; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.data" *)output [7:0] m_axi_mat_C_ch_in_0_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.data" *)output m_axi_mat_C_ch_in_0_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.data" *)output [2:0] m_axi_mat_C_ch_in_0_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.data" *)output [3:0] m_axi_mat_C_ch_in_0_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.ready" *)input m_axi_mat_C_ch_in_0_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.data" *)output [2:0] m_axi_mat_C_ch_in_0_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_0_AR.valid" *)output m_axi_mat_C_ch_in_0_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.data" *)output [63:0] m_axi_mat_C_ch_in_0_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.data" *)output [1:0] m_axi_mat_C_ch_in_0_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.data" *)output [3:0] m_axi_mat_C_ch_in_0_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.data" *)output [0:0] m_axi_mat_C_ch_in_0_AWID; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.data" *)output [7:0] m_axi_mat_C_ch_in_0_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.data" *)output m_axi_mat_C_ch_in_0_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.data" *)output [2:0] m_axi_mat_C_ch_in_0_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.data" *)output [3:0] m_axi_mat_C_ch_in_0_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.ready" *)input m_axi_mat_C_ch_in_0_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.data" *)output [2:0] m_axi_mat_C_ch_in_0_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_0_AW.valid" *)output m_axi_mat_C_ch_in_0_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_in_0_B.data" *)input [0:0] m_axi_mat_C_ch_in_0_BID; - (* RS_HS = "m_axi_mat_C_ch_in_0_B.ready" *)output m_axi_mat_C_ch_in_0_BREADY; - (* RS_HS = "m_axi_mat_C_ch_in_0_B.data" *)input [1:0] m_axi_mat_C_ch_in_0_BRESP; - (* RS_HS = "m_axi_mat_C_ch_in_0_B.valid" *)input m_axi_mat_C_ch_in_0_BVALID; - (* RS_HS = "m_axi_mat_C_ch_in_0_R.data" *)input [511:0] m_axi_mat_C_ch_in_0_RDATA; - (* RS_HS = "m_axi_mat_C_ch_in_0_R.data" *)input [0:0] m_axi_mat_C_ch_in_0_RID; - (* RS_HS = "m_axi_mat_C_ch_in_0_R.data" *)input m_axi_mat_C_ch_in_0_RLAST; - (* RS_HS = "m_axi_mat_C_ch_in_0_R.ready" *)output m_axi_mat_C_ch_in_0_RREADY; - (* RS_HS = "m_axi_mat_C_ch_in_0_R.data" *)input [1:0] m_axi_mat_C_ch_in_0_RRESP; - (* RS_HS = "m_axi_mat_C_ch_in_0_R.valid" *)input m_axi_mat_C_ch_in_0_RVALID; - (* RS_HS = "m_axi_mat_C_ch_in_0_W.data" *)output [511:0] m_axi_mat_C_ch_in_0_WDATA; - (* RS_HS = "m_axi_mat_C_ch_in_0_W.data" *)output m_axi_mat_C_ch_in_0_WLAST; - (* RS_HS = "m_axi_mat_C_ch_in_0_W.ready" *)input m_axi_mat_C_ch_in_0_WREADY; - (* RS_HS = "m_axi_mat_C_ch_in_0_W.data" *)output [63:0] m_axi_mat_C_ch_in_0_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_in_0_W.valid" *)output m_axi_mat_C_ch_in_0_WVALID; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.data" *)output [63:0] m_axi_mat_C_ch_in_1_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.data" *)output [1:0] m_axi_mat_C_ch_in_1_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.data" *)output [3:0] m_axi_mat_C_ch_in_1_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.data" *)output [0:0] m_axi_mat_C_ch_in_1_ARID; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.data" *)output [7:0] m_axi_mat_C_ch_in_1_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.data" *)output m_axi_mat_C_ch_in_1_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.data" *)output [2:0] m_axi_mat_C_ch_in_1_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.data" *)output [3:0] m_axi_mat_C_ch_in_1_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.ready" *)input m_axi_mat_C_ch_in_1_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.data" *)output [2:0] m_axi_mat_C_ch_in_1_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_1_AR.valid" *)output m_axi_mat_C_ch_in_1_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.data" *)output [63:0] m_axi_mat_C_ch_in_1_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.data" *)output [1:0] m_axi_mat_C_ch_in_1_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.data" *)output [3:0] m_axi_mat_C_ch_in_1_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.data" *)output [0:0] m_axi_mat_C_ch_in_1_AWID; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.data" *)output [7:0] m_axi_mat_C_ch_in_1_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.data" *)output m_axi_mat_C_ch_in_1_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.data" *)output [2:0] m_axi_mat_C_ch_in_1_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.data" *)output [3:0] m_axi_mat_C_ch_in_1_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.ready" *)input m_axi_mat_C_ch_in_1_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.data" *)output [2:0] m_axi_mat_C_ch_in_1_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_1_AW.valid" *)output m_axi_mat_C_ch_in_1_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_in_1_B.data" *)input [0:0] m_axi_mat_C_ch_in_1_BID; - (* RS_HS = "m_axi_mat_C_ch_in_1_B.ready" *)output m_axi_mat_C_ch_in_1_BREADY; - (* RS_HS = "m_axi_mat_C_ch_in_1_B.data" *)input [1:0] m_axi_mat_C_ch_in_1_BRESP; - (* RS_HS = "m_axi_mat_C_ch_in_1_B.valid" *)input m_axi_mat_C_ch_in_1_BVALID; - (* RS_HS = "m_axi_mat_C_ch_in_1_R.data" *)input [511:0] m_axi_mat_C_ch_in_1_RDATA; - (* RS_HS = "m_axi_mat_C_ch_in_1_R.data" *)input [0:0] m_axi_mat_C_ch_in_1_RID; - (* RS_HS = "m_axi_mat_C_ch_in_1_R.data" *)input m_axi_mat_C_ch_in_1_RLAST; - (* RS_HS = "m_axi_mat_C_ch_in_1_R.ready" *)output m_axi_mat_C_ch_in_1_RREADY; - (* RS_HS = "m_axi_mat_C_ch_in_1_R.data" *)input [1:0] m_axi_mat_C_ch_in_1_RRESP; - (* RS_HS = "m_axi_mat_C_ch_in_1_R.valid" *)input m_axi_mat_C_ch_in_1_RVALID; - (* RS_HS = "m_axi_mat_C_ch_in_1_W.data" *)output [511:0] m_axi_mat_C_ch_in_1_WDATA; - (* RS_HS = "m_axi_mat_C_ch_in_1_W.data" *)output m_axi_mat_C_ch_in_1_WLAST; - (* RS_HS = "m_axi_mat_C_ch_in_1_W.ready" *)input m_axi_mat_C_ch_in_1_WREADY; - (* RS_HS = "m_axi_mat_C_ch_in_1_W.data" *)output [63:0] m_axi_mat_C_ch_in_1_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_in_1_W.valid" *)output m_axi_mat_C_ch_in_1_WVALID; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.data" *)output [63:0] m_axi_mat_C_ch_in_2_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.data" *)output [1:0] m_axi_mat_C_ch_in_2_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.data" *)output [3:0] m_axi_mat_C_ch_in_2_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.data" *)output [0:0] m_axi_mat_C_ch_in_2_ARID; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.data" *)output [7:0] m_axi_mat_C_ch_in_2_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.data" *)output m_axi_mat_C_ch_in_2_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.data" *)output [2:0] m_axi_mat_C_ch_in_2_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.data" *)output [3:0] m_axi_mat_C_ch_in_2_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.ready" *)input m_axi_mat_C_ch_in_2_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.data" *)output [2:0] m_axi_mat_C_ch_in_2_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_2_AR.valid" *)output m_axi_mat_C_ch_in_2_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.data" *)output [63:0] m_axi_mat_C_ch_in_2_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.data" *)output [1:0] m_axi_mat_C_ch_in_2_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.data" *)output [3:0] m_axi_mat_C_ch_in_2_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.data" *)output [0:0] m_axi_mat_C_ch_in_2_AWID; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.data" *)output [7:0] m_axi_mat_C_ch_in_2_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.data" *)output m_axi_mat_C_ch_in_2_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.data" *)output [2:0] m_axi_mat_C_ch_in_2_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.data" *)output [3:0] m_axi_mat_C_ch_in_2_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.ready" *)input m_axi_mat_C_ch_in_2_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.data" *)output [2:0] m_axi_mat_C_ch_in_2_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_2_AW.valid" *)output m_axi_mat_C_ch_in_2_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_in_2_B.data" *)input [0:0] m_axi_mat_C_ch_in_2_BID; - (* RS_HS = "m_axi_mat_C_ch_in_2_B.ready" *)output m_axi_mat_C_ch_in_2_BREADY; - (* RS_HS = "m_axi_mat_C_ch_in_2_B.data" *)input [1:0] m_axi_mat_C_ch_in_2_BRESP; - (* RS_HS = "m_axi_mat_C_ch_in_2_B.valid" *)input m_axi_mat_C_ch_in_2_BVALID; - (* RS_HS = "m_axi_mat_C_ch_in_2_R.data" *)input [511:0] m_axi_mat_C_ch_in_2_RDATA; - (* RS_HS = "m_axi_mat_C_ch_in_2_R.data" *)input [0:0] m_axi_mat_C_ch_in_2_RID; - (* RS_HS = "m_axi_mat_C_ch_in_2_R.data" *)input m_axi_mat_C_ch_in_2_RLAST; - (* RS_HS = "m_axi_mat_C_ch_in_2_R.ready" *)output m_axi_mat_C_ch_in_2_RREADY; - (* RS_HS = "m_axi_mat_C_ch_in_2_R.data" *)input [1:0] m_axi_mat_C_ch_in_2_RRESP; - (* RS_HS = "m_axi_mat_C_ch_in_2_R.valid" *)input m_axi_mat_C_ch_in_2_RVALID; - (* RS_HS = "m_axi_mat_C_ch_in_2_W.data" *)output [511:0] m_axi_mat_C_ch_in_2_WDATA; - (* RS_HS = "m_axi_mat_C_ch_in_2_W.data" *)output m_axi_mat_C_ch_in_2_WLAST; - (* RS_HS = "m_axi_mat_C_ch_in_2_W.ready" *)input m_axi_mat_C_ch_in_2_WREADY; - (* RS_HS = "m_axi_mat_C_ch_in_2_W.data" *)output [63:0] m_axi_mat_C_ch_in_2_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_in_2_W.valid" *)output m_axi_mat_C_ch_in_2_WVALID; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.data" *)output [63:0] m_axi_mat_C_ch_in_3_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.data" *)output [1:0] m_axi_mat_C_ch_in_3_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.data" *)output [3:0] m_axi_mat_C_ch_in_3_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.data" *)output [0:0] m_axi_mat_C_ch_in_3_ARID; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.data" *)output [7:0] m_axi_mat_C_ch_in_3_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.data" *)output m_axi_mat_C_ch_in_3_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.data" *)output [2:0] m_axi_mat_C_ch_in_3_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.data" *)output [3:0] m_axi_mat_C_ch_in_3_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.ready" *)input m_axi_mat_C_ch_in_3_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.data" *)output [2:0] m_axi_mat_C_ch_in_3_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_3_AR.valid" *)output m_axi_mat_C_ch_in_3_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.data" *)output [63:0] m_axi_mat_C_ch_in_3_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.data" *)output [1:0] m_axi_mat_C_ch_in_3_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.data" *)output [3:0] m_axi_mat_C_ch_in_3_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.data" *)output [0:0] m_axi_mat_C_ch_in_3_AWID; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.data" *)output [7:0] m_axi_mat_C_ch_in_3_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.data" *)output m_axi_mat_C_ch_in_3_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.data" *)output [2:0] m_axi_mat_C_ch_in_3_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.data" *)output [3:0] m_axi_mat_C_ch_in_3_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.ready" *)input m_axi_mat_C_ch_in_3_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.data" *)output [2:0] m_axi_mat_C_ch_in_3_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_3_AW.valid" *)output m_axi_mat_C_ch_in_3_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_in_3_B.data" *)input [0:0] m_axi_mat_C_ch_in_3_BID; - (* RS_HS = "m_axi_mat_C_ch_in_3_B.ready" *)output m_axi_mat_C_ch_in_3_BREADY; - (* RS_HS = "m_axi_mat_C_ch_in_3_B.data" *)input [1:0] m_axi_mat_C_ch_in_3_BRESP; - (* RS_HS = "m_axi_mat_C_ch_in_3_B.valid" *)input m_axi_mat_C_ch_in_3_BVALID; - (* RS_HS = "m_axi_mat_C_ch_in_3_R.data" *)input [511:0] m_axi_mat_C_ch_in_3_RDATA; - (* RS_HS = "m_axi_mat_C_ch_in_3_R.data" *)input [0:0] m_axi_mat_C_ch_in_3_RID; - (* RS_HS = "m_axi_mat_C_ch_in_3_R.data" *)input m_axi_mat_C_ch_in_3_RLAST; - (* RS_HS = "m_axi_mat_C_ch_in_3_R.ready" *)output m_axi_mat_C_ch_in_3_RREADY; - (* RS_HS = "m_axi_mat_C_ch_in_3_R.data" *)input [1:0] m_axi_mat_C_ch_in_3_RRESP; - (* RS_HS = "m_axi_mat_C_ch_in_3_R.valid" *)input m_axi_mat_C_ch_in_3_RVALID; - (* RS_HS = "m_axi_mat_C_ch_in_3_W.data" *)output [511:0] m_axi_mat_C_ch_in_3_WDATA; - (* RS_HS = "m_axi_mat_C_ch_in_3_W.data" *)output m_axi_mat_C_ch_in_3_WLAST; - (* RS_HS = "m_axi_mat_C_ch_in_3_W.ready" *)input m_axi_mat_C_ch_in_3_WREADY; - (* RS_HS = "m_axi_mat_C_ch_in_3_W.data" *)output [63:0] m_axi_mat_C_ch_in_3_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_in_3_W.valid" *)output m_axi_mat_C_ch_in_3_WVALID; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.data" *)output [63:0] m_axi_mat_C_ch_in_4_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.data" *)output [1:0] m_axi_mat_C_ch_in_4_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.data" *)output [3:0] m_axi_mat_C_ch_in_4_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.data" *)output [0:0] m_axi_mat_C_ch_in_4_ARID; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.data" *)output [7:0] m_axi_mat_C_ch_in_4_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.data" *)output m_axi_mat_C_ch_in_4_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.data" *)output [2:0] m_axi_mat_C_ch_in_4_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.data" *)output [3:0] m_axi_mat_C_ch_in_4_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.ready" *)input m_axi_mat_C_ch_in_4_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.data" *)output [2:0] m_axi_mat_C_ch_in_4_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_4_AR.valid" *)output m_axi_mat_C_ch_in_4_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.data" *)output [63:0] m_axi_mat_C_ch_in_4_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.data" *)output [1:0] m_axi_mat_C_ch_in_4_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.data" *)output [3:0] m_axi_mat_C_ch_in_4_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.data" *)output [0:0] m_axi_mat_C_ch_in_4_AWID; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.data" *)output [7:0] m_axi_mat_C_ch_in_4_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.data" *)output m_axi_mat_C_ch_in_4_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.data" *)output [2:0] m_axi_mat_C_ch_in_4_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.data" *)output [3:0] m_axi_mat_C_ch_in_4_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.ready" *)input m_axi_mat_C_ch_in_4_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.data" *)output [2:0] m_axi_mat_C_ch_in_4_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_4_AW.valid" *)output m_axi_mat_C_ch_in_4_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_in_4_B.data" *)input [0:0] m_axi_mat_C_ch_in_4_BID; - (* RS_HS = "m_axi_mat_C_ch_in_4_B.ready" *)output m_axi_mat_C_ch_in_4_BREADY; - (* RS_HS = "m_axi_mat_C_ch_in_4_B.data" *)input [1:0] m_axi_mat_C_ch_in_4_BRESP; - (* RS_HS = "m_axi_mat_C_ch_in_4_B.valid" *)input m_axi_mat_C_ch_in_4_BVALID; - (* RS_HS = "m_axi_mat_C_ch_in_4_R.data" *)input [511:0] m_axi_mat_C_ch_in_4_RDATA; - (* RS_HS = "m_axi_mat_C_ch_in_4_R.data" *)input [0:0] m_axi_mat_C_ch_in_4_RID; - (* RS_HS = "m_axi_mat_C_ch_in_4_R.data" *)input m_axi_mat_C_ch_in_4_RLAST; - (* RS_HS = "m_axi_mat_C_ch_in_4_R.ready" *)output m_axi_mat_C_ch_in_4_RREADY; - (* RS_HS = "m_axi_mat_C_ch_in_4_R.data" *)input [1:0] m_axi_mat_C_ch_in_4_RRESP; - (* RS_HS = "m_axi_mat_C_ch_in_4_R.valid" *)input m_axi_mat_C_ch_in_4_RVALID; - (* RS_HS = "m_axi_mat_C_ch_in_4_W.data" *)output [511:0] m_axi_mat_C_ch_in_4_WDATA; - (* RS_HS = "m_axi_mat_C_ch_in_4_W.data" *)output m_axi_mat_C_ch_in_4_WLAST; - (* RS_HS = "m_axi_mat_C_ch_in_4_W.ready" *)input m_axi_mat_C_ch_in_4_WREADY; - (* RS_HS = "m_axi_mat_C_ch_in_4_W.data" *)output [63:0] m_axi_mat_C_ch_in_4_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_in_4_W.valid" *)output m_axi_mat_C_ch_in_4_WVALID; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.data" *)output [63:0] m_axi_mat_C_ch_in_5_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.data" *)output [1:0] m_axi_mat_C_ch_in_5_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.data" *)output [3:0] m_axi_mat_C_ch_in_5_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.data" *)output [0:0] m_axi_mat_C_ch_in_5_ARID; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.data" *)output [7:0] m_axi_mat_C_ch_in_5_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.data" *)output m_axi_mat_C_ch_in_5_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.data" *)output [2:0] m_axi_mat_C_ch_in_5_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.data" *)output [3:0] m_axi_mat_C_ch_in_5_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.ready" *)input m_axi_mat_C_ch_in_5_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.data" *)output [2:0] m_axi_mat_C_ch_in_5_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_5_AR.valid" *)output m_axi_mat_C_ch_in_5_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.data" *)output [63:0] m_axi_mat_C_ch_in_5_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.data" *)output [1:0] m_axi_mat_C_ch_in_5_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.data" *)output [3:0] m_axi_mat_C_ch_in_5_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.data" *)output [0:0] m_axi_mat_C_ch_in_5_AWID; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.data" *)output [7:0] m_axi_mat_C_ch_in_5_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.data" *)output m_axi_mat_C_ch_in_5_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.data" *)output [2:0] m_axi_mat_C_ch_in_5_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.data" *)output [3:0] m_axi_mat_C_ch_in_5_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.ready" *)input m_axi_mat_C_ch_in_5_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.data" *)output [2:0] m_axi_mat_C_ch_in_5_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_5_AW.valid" *)output m_axi_mat_C_ch_in_5_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_in_5_B.data" *)input [0:0] m_axi_mat_C_ch_in_5_BID; - (* RS_HS = "m_axi_mat_C_ch_in_5_B.ready" *)output m_axi_mat_C_ch_in_5_BREADY; - (* RS_HS = "m_axi_mat_C_ch_in_5_B.data" *)input [1:0] m_axi_mat_C_ch_in_5_BRESP; - (* RS_HS = "m_axi_mat_C_ch_in_5_B.valid" *)input m_axi_mat_C_ch_in_5_BVALID; - (* RS_HS = "m_axi_mat_C_ch_in_5_R.data" *)input [511:0] m_axi_mat_C_ch_in_5_RDATA; - (* RS_HS = "m_axi_mat_C_ch_in_5_R.data" *)input [0:0] m_axi_mat_C_ch_in_5_RID; - (* RS_HS = "m_axi_mat_C_ch_in_5_R.data" *)input m_axi_mat_C_ch_in_5_RLAST; - (* RS_HS = "m_axi_mat_C_ch_in_5_R.ready" *)output m_axi_mat_C_ch_in_5_RREADY; - (* RS_HS = "m_axi_mat_C_ch_in_5_R.data" *)input [1:0] m_axi_mat_C_ch_in_5_RRESP; - (* RS_HS = "m_axi_mat_C_ch_in_5_R.valid" *)input m_axi_mat_C_ch_in_5_RVALID; - (* RS_HS = "m_axi_mat_C_ch_in_5_W.data" *)output [511:0] m_axi_mat_C_ch_in_5_WDATA; - (* RS_HS = "m_axi_mat_C_ch_in_5_W.data" *)output m_axi_mat_C_ch_in_5_WLAST; - (* RS_HS = "m_axi_mat_C_ch_in_5_W.ready" *)input m_axi_mat_C_ch_in_5_WREADY; - (* RS_HS = "m_axi_mat_C_ch_in_5_W.data" *)output [63:0] m_axi_mat_C_ch_in_5_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_in_5_W.valid" *)output m_axi_mat_C_ch_in_5_WVALID; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.data" *)output [63:0] m_axi_mat_C_ch_in_6_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.data" *)output [1:0] m_axi_mat_C_ch_in_6_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.data" *)output [3:0] m_axi_mat_C_ch_in_6_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.data" *)output [0:0] m_axi_mat_C_ch_in_6_ARID; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.data" *)output [7:0] m_axi_mat_C_ch_in_6_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.data" *)output m_axi_mat_C_ch_in_6_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.data" *)output [2:0] m_axi_mat_C_ch_in_6_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.data" *)output [3:0] m_axi_mat_C_ch_in_6_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.ready" *)input m_axi_mat_C_ch_in_6_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.data" *)output [2:0] m_axi_mat_C_ch_in_6_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_6_AR.valid" *)output m_axi_mat_C_ch_in_6_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.data" *)output [63:0] m_axi_mat_C_ch_in_6_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.data" *)output [1:0] m_axi_mat_C_ch_in_6_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.data" *)output [3:0] m_axi_mat_C_ch_in_6_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.data" *)output [0:0] m_axi_mat_C_ch_in_6_AWID; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.data" *)output [7:0] m_axi_mat_C_ch_in_6_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.data" *)output m_axi_mat_C_ch_in_6_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.data" *)output [2:0] m_axi_mat_C_ch_in_6_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.data" *)output [3:0] m_axi_mat_C_ch_in_6_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.ready" *)input m_axi_mat_C_ch_in_6_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.data" *)output [2:0] m_axi_mat_C_ch_in_6_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_6_AW.valid" *)output m_axi_mat_C_ch_in_6_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_in_6_B.data" *)input [0:0] m_axi_mat_C_ch_in_6_BID; - (* RS_HS = "m_axi_mat_C_ch_in_6_B.ready" *)output m_axi_mat_C_ch_in_6_BREADY; - (* RS_HS = "m_axi_mat_C_ch_in_6_B.data" *)input [1:0] m_axi_mat_C_ch_in_6_BRESP; - (* RS_HS = "m_axi_mat_C_ch_in_6_B.valid" *)input m_axi_mat_C_ch_in_6_BVALID; - (* RS_HS = "m_axi_mat_C_ch_in_6_R.data" *)input [511:0] m_axi_mat_C_ch_in_6_RDATA; - (* RS_HS = "m_axi_mat_C_ch_in_6_R.data" *)input [0:0] m_axi_mat_C_ch_in_6_RID; - (* RS_HS = "m_axi_mat_C_ch_in_6_R.data" *)input m_axi_mat_C_ch_in_6_RLAST; - (* RS_HS = "m_axi_mat_C_ch_in_6_R.ready" *)output m_axi_mat_C_ch_in_6_RREADY; - (* RS_HS = "m_axi_mat_C_ch_in_6_R.data" *)input [1:0] m_axi_mat_C_ch_in_6_RRESP; - (* RS_HS = "m_axi_mat_C_ch_in_6_R.valid" *)input m_axi_mat_C_ch_in_6_RVALID; - (* RS_HS = "m_axi_mat_C_ch_in_6_W.data" *)output [511:0] m_axi_mat_C_ch_in_6_WDATA; - (* RS_HS = "m_axi_mat_C_ch_in_6_W.data" *)output m_axi_mat_C_ch_in_6_WLAST; - (* RS_HS = "m_axi_mat_C_ch_in_6_W.ready" *)input m_axi_mat_C_ch_in_6_WREADY; - (* RS_HS = "m_axi_mat_C_ch_in_6_W.data" *)output [63:0] m_axi_mat_C_ch_in_6_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_in_6_W.valid" *)output m_axi_mat_C_ch_in_6_WVALID; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.data" *)output [63:0] m_axi_mat_C_ch_in_7_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.data" *)output [1:0] m_axi_mat_C_ch_in_7_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.data" *)output [3:0] m_axi_mat_C_ch_in_7_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.data" *)output [0:0] m_axi_mat_C_ch_in_7_ARID; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.data" *)output [7:0] m_axi_mat_C_ch_in_7_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.data" *)output m_axi_mat_C_ch_in_7_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.data" *)output [2:0] m_axi_mat_C_ch_in_7_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.data" *)output [3:0] m_axi_mat_C_ch_in_7_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.ready" *)input m_axi_mat_C_ch_in_7_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.data" *)output [2:0] m_axi_mat_C_ch_in_7_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_7_AR.valid" *)output m_axi_mat_C_ch_in_7_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.data" *)output [63:0] m_axi_mat_C_ch_in_7_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.data" *)output [1:0] m_axi_mat_C_ch_in_7_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.data" *)output [3:0] m_axi_mat_C_ch_in_7_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.data" *)output [0:0] m_axi_mat_C_ch_in_7_AWID; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.data" *)output [7:0] m_axi_mat_C_ch_in_7_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.data" *)output m_axi_mat_C_ch_in_7_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.data" *)output [2:0] m_axi_mat_C_ch_in_7_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.data" *)output [3:0] m_axi_mat_C_ch_in_7_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.ready" *)input m_axi_mat_C_ch_in_7_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.data" *)output [2:0] m_axi_mat_C_ch_in_7_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_in_7_AW.valid" *)output m_axi_mat_C_ch_in_7_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_in_7_B.data" *)input [0:0] m_axi_mat_C_ch_in_7_BID; - (* RS_HS = "m_axi_mat_C_ch_in_7_B.ready" *)output m_axi_mat_C_ch_in_7_BREADY; - (* RS_HS = "m_axi_mat_C_ch_in_7_B.data" *)input [1:0] m_axi_mat_C_ch_in_7_BRESP; - (* RS_HS = "m_axi_mat_C_ch_in_7_B.valid" *)input m_axi_mat_C_ch_in_7_BVALID; - (* RS_HS = "m_axi_mat_C_ch_in_7_R.data" *)input [511:0] m_axi_mat_C_ch_in_7_RDATA; - (* RS_HS = "m_axi_mat_C_ch_in_7_R.data" *)input [0:0] m_axi_mat_C_ch_in_7_RID; - (* RS_HS = "m_axi_mat_C_ch_in_7_R.data" *)input m_axi_mat_C_ch_in_7_RLAST; - (* RS_HS = "m_axi_mat_C_ch_in_7_R.ready" *)output m_axi_mat_C_ch_in_7_RREADY; - (* RS_HS = "m_axi_mat_C_ch_in_7_R.data" *)input [1:0] m_axi_mat_C_ch_in_7_RRESP; - (* RS_HS = "m_axi_mat_C_ch_in_7_R.valid" *)input m_axi_mat_C_ch_in_7_RVALID; - (* RS_HS = "m_axi_mat_C_ch_in_7_W.data" *)output [511:0] m_axi_mat_C_ch_in_7_WDATA; - (* RS_HS = "m_axi_mat_C_ch_in_7_W.data" *)output m_axi_mat_C_ch_in_7_WLAST; - (* RS_HS = "m_axi_mat_C_ch_in_7_W.ready" *)input m_axi_mat_C_ch_in_7_WREADY; - (* RS_HS = "m_axi_mat_C_ch_in_7_W.data" *)output [63:0] m_axi_mat_C_ch_in_7_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_in_7_W.valid" *)output m_axi_mat_C_ch_in_7_WVALID; - (* RS_HS = "m_axi_edge_list_ptr_AR.data" *)output [63:0] m_axi_edge_list_ptr_ARADDR; - (* RS_HS = "m_axi_edge_list_ptr_AR.data" *)output [1:0] m_axi_edge_list_ptr_ARBURST; - (* RS_HS = "m_axi_edge_list_ptr_AR.data" *)output [3:0] m_axi_edge_list_ptr_ARCACHE; - (* RS_HS = "m_axi_edge_list_ptr_AR.data" *)output [0:0] m_axi_edge_list_ptr_ARID; - (* RS_HS = "m_axi_edge_list_ptr_AR.data" *)output [7:0] m_axi_edge_list_ptr_ARLEN; - (* RS_HS = "m_axi_edge_list_ptr_AR.data" *)output m_axi_edge_list_ptr_ARLOCK; - (* RS_HS = "m_axi_edge_list_ptr_AR.data" *)output [2:0] m_axi_edge_list_ptr_ARPROT; - (* RS_HS = "m_axi_edge_list_ptr_AR.data" *)output [3:0] m_axi_edge_list_ptr_ARQOS; - (* RS_HS = "m_axi_edge_list_ptr_AR.ready" *)input m_axi_edge_list_ptr_ARREADY; - (* RS_HS = "m_axi_edge_list_ptr_AR.data" *)output [2:0] m_axi_edge_list_ptr_ARSIZE; - (* RS_HS = "m_axi_edge_list_ptr_AR.valid" *)output m_axi_edge_list_ptr_ARVALID; - (* RS_HS = "m_axi_edge_list_ptr_AW.data" *)output [63:0] m_axi_edge_list_ptr_AWADDR; - (* RS_HS = "m_axi_edge_list_ptr_AW.data" *)output [1:0] m_axi_edge_list_ptr_AWBURST; - (* RS_HS = "m_axi_edge_list_ptr_AW.data" *)output [3:0] m_axi_edge_list_ptr_AWCACHE; - (* RS_HS = "m_axi_edge_list_ptr_AW.data" *)output [0:0] m_axi_edge_list_ptr_AWID; - (* RS_HS = "m_axi_edge_list_ptr_AW.data" *)output [7:0] m_axi_edge_list_ptr_AWLEN; - (* RS_HS = "m_axi_edge_list_ptr_AW.data" *)output m_axi_edge_list_ptr_AWLOCK; - (* RS_HS = "m_axi_edge_list_ptr_AW.data" *)output [2:0] m_axi_edge_list_ptr_AWPROT; - (* RS_HS = "m_axi_edge_list_ptr_AW.data" *)output [3:0] m_axi_edge_list_ptr_AWQOS; - (* RS_HS = "m_axi_edge_list_ptr_AW.ready" *)input m_axi_edge_list_ptr_AWREADY; - (* RS_HS = "m_axi_edge_list_ptr_AW.data" *)output [2:0] m_axi_edge_list_ptr_AWSIZE; - (* RS_HS = "m_axi_edge_list_ptr_AW.valid" *)output m_axi_edge_list_ptr_AWVALID; - (* RS_HS = "m_axi_edge_list_ptr_B.data" *)input [0:0] m_axi_edge_list_ptr_BID; - (* RS_HS = "m_axi_edge_list_ptr_B.ready" *)output m_axi_edge_list_ptr_BREADY; - (* RS_HS = "m_axi_edge_list_ptr_B.data" *)input [1:0] m_axi_edge_list_ptr_BRESP; - (* RS_HS = "m_axi_edge_list_ptr_B.valid" *)input m_axi_edge_list_ptr_BVALID; - (* RS_HS = "m_axi_edge_list_ptr_R.data" *)input [31:0] m_axi_edge_list_ptr_RDATA; - (* RS_HS = "m_axi_edge_list_ptr_R.data" *)input [0:0] m_axi_edge_list_ptr_RID; - (* RS_HS = "m_axi_edge_list_ptr_R.data" *)input m_axi_edge_list_ptr_RLAST; - (* RS_HS = "m_axi_edge_list_ptr_R.ready" *)output m_axi_edge_list_ptr_RREADY; - (* RS_HS = "m_axi_edge_list_ptr_R.data" *)input [1:0] m_axi_edge_list_ptr_RRESP; - (* RS_HS = "m_axi_edge_list_ptr_R.valid" *)input m_axi_edge_list_ptr_RVALID; - (* RS_HS = "m_axi_edge_list_ptr_W.data" *)output [31:0] m_axi_edge_list_ptr_WDATA; - (* RS_HS = "m_axi_edge_list_ptr_W.data" *)output m_axi_edge_list_ptr_WLAST; - (* RS_HS = "m_axi_edge_list_ptr_W.ready" *)input m_axi_edge_list_ptr_WREADY; - (* RS_HS = "m_axi_edge_list_ptr_W.data" *)output [3:0] m_axi_edge_list_ptr_WSTRB; - (* RS_HS = "m_axi_edge_list_ptr_W.valid" *)output m_axi_edge_list_ptr_WVALID; - (* RS_HS = "m_axi_mat_C_ch_0_AR.data" *)output [63:0] m_axi_mat_C_ch_0_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_0_AR.data" *)output [1:0] m_axi_mat_C_ch_0_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_0_AR.data" *)output [3:0] m_axi_mat_C_ch_0_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_0_AR.data" *)output [0:0] m_axi_mat_C_ch_0_ARID; - (* RS_HS = "m_axi_mat_C_ch_0_AR.data" *)output [7:0] m_axi_mat_C_ch_0_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_0_AR.data" *)output m_axi_mat_C_ch_0_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_0_AR.data" *)output [2:0] m_axi_mat_C_ch_0_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_0_AR.data" *)output [3:0] m_axi_mat_C_ch_0_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_0_AR.ready" *)input m_axi_mat_C_ch_0_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_0_AR.data" *)output [2:0] m_axi_mat_C_ch_0_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_0_AR.valid" *)output m_axi_mat_C_ch_0_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_0_AW.data" *)output [63:0] m_axi_mat_C_ch_0_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_0_AW.data" *)output [1:0] m_axi_mat_C_ch_0_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_0_AW.data" *)output [3:0] m_axi_mat_C_ch_0_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_0_AW.data" *)output [0:0] m_axi_mat_C_ch_0_AWID; - (* RS_HS = "m_axi_mat_C_ch_0_AW.data" *)output [7:0] m_axi_mat_C_ch_0_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_0_AW.data" *)output m_axi_mat_C_ch_0_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_0_AW.data" *)output [2:0] m_axi_mat_C_ch_0_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_0_AW.data" *)output [3:0] m_axi_mat_C_ch_0_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_0_AW.ready" *)input m_axi_mat_C_ch_0_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_0_AW.data" *)output [2:0] m_axi_mat_C_ch_0_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_0_AW.valid" *)output m_axi_mat_C_ch_0_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_0_B.data" *)input [0:0] m_axi_mat_C_ch_0_BID; - (* RS_HS = "m_axi_mat_C_ch_0_B.ready" *)output m_axi_mat_C_ch_0_BREADY; - (* RS_HS = "m_axi_mat_C_ch_0_B.data" *)input [1:0] m_axi_mat_C_ch_0_BRESP; - (* RS_HS = "m_axi_mat_C_ch_0_B.valid" *)input m_axi_mat_C_ch_0_BVALID; - (* RS_HS = "m_axi_mat_C_ch_0_R.data" *)input [511:0] m_axi_mat_C_ch_0_RDATA; - (* RS_HS = "m_axi_mat_C_ch_0_R.data" *)input [0:0] m_axi_mat_C_ch_0_RID; - (* RS_HS = "m_axi_mat_C_ch_0_R.data" *)input m_axi_mat_C_ch_0_RLAST; - (* RS_HS = "m_axi_mat_C_ch_0_R.ready" *)output m_axi_mat_C_ch_0_RREADY; - (* RS_HS = "m_axi_mat_C_ch_0_R.data" *)input [1:0] m_axi_mat_C_ch_0_RRESP; - (* RS_HS = "m_axi_mat_C_ch_0_R.valid" *)input m_axi_mat_C_ch_0_RVALID; - (* RS_HS = "m_axi_mat_C_ch_0_W.data" *)output [511:0] m_axi_mat_C_ch_0_WDATA; - (* RS_HS = "m_axi_mat_C_ch_0_W.data" *)output m_axi_mat_C_ch_0_WLAST; - (* RS_HS = "m_axi_mat_C_ch_0_W.ready" *)input m_axi_mat_C_ch_0_WREADY; - (* RS_HS = "m_axi_mat_C_ch_0_W.data" *)output [63:0] m_axi_mat_C_ch_0_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_0_W.valid" *)output m_axi_mat_C_ch_0_WVALID; - (* RS_HS = "m_axi_mat_C_ch_1_AR.data" *)output [63:0] m_axi_mat_C_ch_1_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_1_AR.data" *)output [1:0] m_axi_mat_C_ch_1_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_1_AR.data" *)output [3:0] m_axi_mat_C_ch_1_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_1_AR.data" *)output [0:0] m_axi_mat_C_ch_1_ARID; - (* RS_HS = "m_axi_mat_C_ch_1_AR.data" *)output [7:0] m_axi_mat_C_ch_1_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_1_AR.data" *)output m_axi_mat_C_ch_1_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_1_AR.data" *)output [2:0] m_axi_mat_C_ch_1_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_1_AR.data" *)output [3:0] m_axi_mat_C_ch_1_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_1_AR.ready" *)input m_axi_mat_C_ch_1_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_1_AR.data" *)output [2:0] m_axi_mat_C_ch_1_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_1_AR.valid" *)output m_axi_mat_C_ch_1_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_1_AW.data" *)output [63:0] m_axi_mat_C_ch_1_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_1_AW.data" *)output [1:0] m_axi_mat_C_ch_1_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_1_AW.data" *)output [3:0] m_axi_mat_C_ch_1_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_1_AW.data" *)output [0:0] m_axi_mat_C_ch_1_AWID; - (* RS_HS = "m_axi_mat_C_ch_1_AW.data" *)output [7:0] m_axi_mat_C_ch_1_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_1_AW.data" *)output m_axi_mat_C_ch_1_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_1_AW.data" *)output [2:0] m_axi_mat_C_ch_1_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_1_AW.data" *)output [3:0] m_axi_mat_C_ch_1_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_1_AW.ready" *)input m_axi_mat_C_ch_1_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_1_AW.data" *)output [2:0] m_axi_mat_C_ch_1_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_1_AW.valid" *)output m_axi_mat_C_ch_1_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_1_B.data" *)input [0:0] m_axi_mat_C_ch_1_BID; - (* RS_HS = "m_axi_mat_C_ch_1_B.ready" *)output m_axi_mat_C_ch_1_BREADY; - (* RS_HS = "m_axi_mat_C_ch_1_B.data" *)input [1:0] m_axi_mat_C_ch_1_BRESP; - (* RS_HS = "m_axi_mat_C_ch_1_B.valid" *)input m_axi_mat_C_ch_1_BVALID; - (* RS_HS = "m_axi_mat_C_ch_1_R.data" *)input [511:0] m_axi_mat_C_ch_1_RDATA; - (* RS_HS = "m_axi_mat_C_ch_1_R.data" *)input [0:0] m_axi_mat_C_ch_1_RID; - (* RS_HS = "m_axi_mat_C_ch_1_R.data" *)input m_axi_mat_C_ch_1_RLAST; - (* RS_HS = "m_axi_mat_C_ch_1_R.ready" *)output m_axi_mat_C_ch_1_RREADY; - (* RS_HS = "m_axi_mat_C_ch_1_R.data" *)input [1:0] m_axi_mat_C_ch_1_RRESP; - (* RS_HS = "m_axi_mat_C_ch_1_R.valid" *)input m_axi_mat_C_ch_1_RVALID; - (* RS_HS = "m_axi_mat_C_ch_1_W.data" *)output [511:0] m_axi_mat_C_ch_1_WDATA; - (* RS_HS = "m_axi_mat_C_ch_1_W.data" *)output m_axi_mat_C_ch_1_WLAST; - (* RS_HS = "m_axi_mat_C_ch_1_W.ready" *)input m_axi_mat_C_ch_1_WREADY; - (* RS_HS = "m_axi_mat_C_ch_1_W.data" *)output [63:0] m_axi_mat_C_ch_1_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_1_W.valid" *)output m_axi_mat_C_ch_1_WVALID; - (* RS_HS = "m_axi_mat_C_ch_2_AR.data" *)output [63:0] m_axi_mat_C_ch_2_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_2_AR.data" *)output [1:0] m_axi_mat_C_ch_2_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_2_AR.data" *)output [3:0] m_axi_mat_C_ch_2_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_2_AR.data" *)output [0:0] m_axi_mat_C_ch_2_ARID; - (* RS_HS = "m_axi_mat_C_ch_2_AR.data" *)output [7:0] m_axi_mat_C_ch_2_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_2_AR.data" *)output m_axi_mat_C_ch_2_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_2_AR.data" *)output [2:0] m_axi_mat_C_ch_2_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_2_AR.data" *)output [3:0] m_axi_mat_C_ch_2_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_2_AR.ready" *)input m_axi_mat_C_ch_2_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_2_AR.data" *)output [2:0] m_axi_mat_C_ch_2_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_2_AR.valid" *)output m_axi_mat_C_ch_2_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_2_AW.data" *)output [63:0] m_axi_mat_C_ch_2_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_2_AW.data" *)output [1:0] m_axi_mat_C_ch_2_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_2_AW.data" *)output [3:0] m_axi_mat_C_ch_2_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_2_AW.data" *)output [0:0] m_axi_mat_C_ch_2_AWID; - (* RS_HS = "m_axi_mat_C_ch_2_AW.data" *)output [7:0] m_axi_mat_C_ch_2_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_2_AW.data" *)output m_axi_mat_C_ch_2_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_2_AW.data" *)output [2:0] m_axi_mat_C_ch_2_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_2_AW.data" *)output [3:0] m_axi_mat_C_ch_2_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_2_AW.ready" *)input m_axi_mat_C_ch_2_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_2_AW.data" *)output [2:0] m_axi_mat_C_ch_2_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_2_AW.valid" *)output m_axi_mat_C_ch_2_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_2_B.data" *)input [0:0] m_axi_mat_C_ch_2_BID; - (* RS_HS = "m_axi_mat_C_ch_2_B.ready" *)output m_axi_mat_C_ch_2_BREADY; - (* RS_HS = "m_axi_mat_C_ch_2_B.data" *)input [1:0] m_axi_mat_C_ch_2_BRESP; - (* RS_HS = "m_axi_mat_C_ch_2_B.valid" *)input m_axi_mat_C_ch_2_BVALID; - (* RS_HS = "m_axi_mat_C_ch_2_R.data" *)input [511:0] m_axi_mat_C_ch_2_RDATA; - (* RS_HS = "m_axi_mat_C_ch_2_R.data" *)input [0:0] m_axi_mat_C_ch_2_RID; - (* RS_HS = "m_axi_mat_C_ch_2_R.data" *)input m_axi_mat_C_ch_2_RLAST; - (* RS_HS = "m_axi_mat_C_ch_2_R.ready" *)output m_axi_mat_C_ch_2_RREADY; - (* RS_HS = "m_axi_mat_C_ch_2_R.data" *)input [1:0] m_axi_mat_C_ch_2_RRESP; - (* RS_HS = "m_axi_mat_C_ch_2_R.valid" *)input m_axi_mat_C_ch_2_RVALID; - (* RS_HS = "m_axi_mat_C_ch_2_W.data" *)output [511:0] m_axi_mat_C_ch_2_WDATA; - (* RS_HS = "m_axi_mat_C_ch_2_W.data" *)output m_axi_mat_C_ch_2_WLAST; - (* RS_HS = "m_axi_mat_C_ch_2_W.ready" *)input m_axi_mat_C_ch_2_WREADY; - (* RS_HS = "m_axi_mat_C_ch_2_W.data" *)output [63:0] m_axi_mat_C_ch_2_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_2_W.valid" *)output m_axi_mat_C_ch_2_WVALID; - (* RS_HS = "m_axi_mat_C_ch_3_AR.data" *)output [63:0] m_axi_mat_C_ch_3_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_3_AR.data" *)output [1:0] m_axi_mat_C_ch_3_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_3_AR.data" *)output [3:0] m_axi_mat_C_ch_3_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_3_AR.data" *)output [0:0] m_axi_mat_C_ch_3_ARID; - (* RS_HS = "m_axi_mat_C_ch_3_AR.data" *)output [7:0] m_axi_mat_C_ch_3_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_3_AR.data" *)output m_axi_mat_C_ch_3_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_3_AR.data" *)output [2:0] m_axi_mat_C_ch_3_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_3_AR.data" *)output [3:0] m_axi_mat_C_ch_3_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_3_AR.ready" *)input m_axi_mat_C_ch_3_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_3_AR.data" *)output [2:0] m_axi_mat_C_ch_3_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_3_AR.valid" *)output m_axi_mat_C_ch_3_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_3_AW.data" *)output [63:0] m_axi_mat_C_ch_3_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_3_AW.data" *)output [1:0] m_axi_mat_C_ch_3_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_3_AW.data" *)output [3:0] m_axi_mat_C_ch_3_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_3_AW.data" *)output [0:0] m_axi_mat_C_ch_3_AWID; - (* RS_HS = "m_axi_mat_C_ch_3_AW.data" *)output [7:0] m_axi_mat_C_ch_3_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_3_AW.data" *)output m_axi_mat_C_ch_3_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_3_AW.data" *)output [2:0] m_axi_mat_C_ch_3_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_3_AW.data" *)output [3:0] m_axi_mat_C_ch_3_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_3_AW.ready" *)input m_axi_mat_C_ch_3_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_3_AW.data" *)output [2:0] m_axi_mat_C_ch_3_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_3_AW.valid" *)output m_axi_mat_C_ch_3_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_3_B.data" *)input [0:0] m_axi_mat_C_ch_3_BID; - (* RS_HS = "m_axi_mat_C_ch_3_B.ready" *)output m_axi_mat_C_ch_3_BREADY; - (* RS_HS = "m_axi_mat_C_ch_3_B.data" *)input [1:0] m_axi_mat_C_ch_3_BRESP; - (* RS_HS = "m_axi_mat_C_ch_3_B.valid" *)input m_axi_mat_C_ch_3_BVALID; - (* RS_HS = "m_axi_mat_C_ch_3_R.data" *)input [511:0] m_axi_mat_C_ch_3_RDATA; - (* RS_HS = "m_axi_mat_C_ch_3_R.data" *)input [0:0] m_axi_mat_C_ch_3_RID; - (* RS_HS = "m_axi_mat_C_ch_3_R.data" *)input m_axi_mat_C_ch_3_RLAST; - (* RS_HS = "m_axi_mat_C_ch_3_R.ready" *)output m_axi_mat_C_ch_3_RREADY; - (* RS_HS = "m_axi_mat_C_ch_3_R.data" *)input [1:0] m_axi_mat_C_ch_3_RRESP; - (* RS_HS = "m_axi_mat_C_ch_3_R.valid" *)input m_axi_mat_C_ch_3_RVALID; - (* RS_HS = "m_axi_mat_C_ch_3_W.data" *)output [511:0] m_axi_mat_C_ch_3_WDATA; - (* RS_HS = "m_axi_mat_C_ch_3_W.data" *)output m_axi_mat_C_ch_3_WLAST; - (* RS_HS = "m_axi_mat_C_ch_3_W.ready" *)input m_axi_mat_C_ch_3_WREADY; - (* RS_HS = "m_axi_mat_C_ch_3_W.data" *)output [63:0] m_axi_mat_C_ch_3_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_3_W.valid" *)output m_axi_mat_C_ch_3_WVALID; - (* RS_HS = "m_axi_mat_C_ch_4_AR.data" *)output [63:0] m_axi_mat_C_ch_4_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_4_AR.data" *)output [1:0] m_axi_mat_C_ch_4_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_4_AR.data" *)output [3:0] m_axi_mat_C_ch_4_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_4_AR.data" *)output [0:0] m_axi_mat_C_ch_4_ARID; - (* RS_HS = "m_axi_mat_C_ch_4_AR.data" *)output [7:0] m_axi_mat_C_ch_4_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_4_AR.data" *)output m_axi_mat_C_ch_4_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_4_AR.data" *)output [2:0] m_axi_mat_C_ch_4_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_4_AR.data" *)output [3:0] m_axi_mat_C_ch_4_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_4_AR.ready" *)input m_axi_mat_C_ch_4_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_4_AR.data" *)output [2:0] m_axi_mat_C_ch_4_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_4_AR.valid" *)output m_axi_mat_C_ch_4_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_4_AW.data" *)output [63:0] m_axi_mat_C_ch_4_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_4_AW.data" *)output [1:0] m_axi_mat_C_ch_4_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_4_AW.data" *)output [3:0] m_axi_mat_C_ch_4_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_4_AW.data" *)output [0:0] m_axi_mat_C_ch_4_AWID; - (* RS_HS = "m_axi_mat_C_ch_4_AW.data" *)output [7:0] m_axi_mat_C_ch_4_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_4_AW.data" *)output m_axi_mat_C_ch_4_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_4_AW.data" *)output [2:0] m_axi_mat_C_ch_4_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_4_AW.data" *)output [3:0] m_axi_mat_C_ch_4_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_4_AW.ready" *)input m_axi_mat_C_ch_4_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_4_AW.data" *)output [2:0] m_axi_mat_C_ch_4_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_4_AW.valid" *)output m_axi_mat_C_ch_4_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_4_B.data" *)input [0:0] m_axi_mat_C_ch_4_BID; - (* RS_HS = "m_axi_mat_C_ch_4_B.ready" *)output m_axi_mat_C_ch_4_BREADY; - (* RS_HS = "m_axi_mat_C_ch_4_B.data" *)input [1:0] m_axi_mat_C_ch_4_BRESP; - (* RS_HS = "m_axi_mat_C_ch_4_B.valid" *)input m_axi_mat_C_ch_4_BVALID; - (* RS_HS = "m_axi_mat_C_ch_4_R.data" *)input [511:0] m_axi_mat_C_ch_4_RDATA; - (* RS_HS = "m_axi_mat_C_ch_4_R.data" *)input [0:0] m_axi_mat_C_ch_4_RID; - (* RS_HS = "m_axi_mat_C_ch_4_R.data" *)input m_axi_mat_C_ch_4_RLAST; - (* RS_HS = "m_axi_mat_C_ch_4_R.ready" *)output m_axi_mat_C_ch_4_RREADY; - (* RS_HS = "m_axi_mat_C_ch_4_R.data" *)input [1:0] m_axi_mat_C_ch_4_RRESP; - (* RS_HS = "m_axi_mat_C_ch_4_R.valid" *)input m_axi_mat_C_ch_4_RVALID; - (* RS_HS = "m_axi_mat_C_ch_4_W.data" *)output [511:0] m_axi_mat_C_ch_4_WDATA; - (* RS_HS = "m_axi_mat_C_ch_4_W.data" *)output m_axi_mat_C_ch_4_WLAST; - (* RS_HS = "m_axi_mat_C_ch_4_W.ready" *)input m_axi_mat_C_ch_4_WREADY; - (* RS_HS = "m_axi_mat_C_ch_4_W.data" *)output [63:0] m_axi_mat_C_ch_4_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_4_W.valid" *)output m_axi_mat_C_ch_4_WVALID; - (* RS_HS = "m_axi_mat_C_ch_5_AR.data" *)output [63:0] m_axi_mat_C_ch_5_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_5_AR.data" *)output [1:0] m_axi_mat_C_ch_5_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_5_AR.data" *)output [3:0] m_axi_mat_C_ch_5_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_5_AR.data" *)output [0:0] m_axi_mat_C_ch_5_ARID; - (* RS_HS = "m_axi_mat_C_ch_5_AR.data" *)output [7:0] m_axi_mat_C_ch_5_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_5_AR.data" *)output m_axi_mat_C_ch_5_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_5_AR.data" *)output [2:0] m_axi_mat_C_ch_5_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_5_AR.data" *)output [3:0] m_axi_mat_C_ch_5_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_5_AR.ready" *)input m_axi_mat_C_ch_5_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_5_AR.data" *)output [2:0] m_axi_mat_C_ch_5_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_5_AR.valid" *)output m_axi_mat_C_ch_5_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_5_AW.data" *)output [63:0] m_axi_mat_C_ch_5_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_5_AW.data" *)output [1:0] m_axi_mat_C_ch_5_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_5_AW.data" *)output [3:0] m_axi_mat_C_ch_5_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_5_AW.data" *)output [0:0] m_axi_mat_C_ch_5_AWID; - (* RS_HS = "m_axi_mat_C_ch_5_AW.data" *)output [7:0] m_axi_mat_C_ch_5_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_5_AW.data" *)output m_axi_mat_C_ch_5_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_5_AW.data" *)output [2:0] m_axi_mat_C_ch_5_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_5_AW.data" *)output [3:0] m_axi_mat_C_ch_5_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_5_AW.ready" *)input m_axi_mat_C_ch_5_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_5_AW.data" *)output [2:0] m_axi_mat_C_ch_5_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_5_AW.valid" *)output m_axi_mat_C_ch_5_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_5_B.data" *)input [0:0] m_axi_mat_C_ch_5_BID; - (* RS_HS = "m_axi_mat_C_ch_5_B.ready" *)output m_axi_mat_C_ch_5_BREADY; - (* RS_HS = "m_axi_mat_C_ch_5_B.data" *)input [1:0] m_axi_mat_C_ch_5_BRESP; - (* RS_HS = "m_axi_mat_C_ch_5_B.valid" *)input m_axi_mat_C_ch_5_BVALID; - (* RS_HS = "m_axi_mat_C_ch_5_R.data" *)input [511:0] m_axi_mat_C_ch_5_RDATA; - (* RS_HS = "m_axi_mat_C_ch_5_R.data" *)input [0:0] m_axi_mat_C_ch_5_RID; - (* RS_HS = "m_axi_mat_C_ch_5_R.data" *)input m_axi_mat_C_ch_5_RLAST; - (* RS_HS = "m_axi_mat_C_ch_5_R.ready" *)output m_axi_mat_C_ch_5_RREADY; - (* RS_HS = "m_axi_mat_C_ch_5_R.data" *)input [1:0] m_axi_mat_C_ch_5_RRESP; - (* RS_HS = "m_axi_mat_C_ch_5_R.valid" *)input m_axi_mat_C_ch_5_RVALID; - (* RS_HS = "m_axi_mat_C_ch_5_W.data" *)output [511:0] m_axi_mat_C_ch_5_WDATA; - (* RS_HS = "m_axi_mat_C_ch_5_W.data" *)output m_axi_mat_C_ch_5_WLAST; - (* RS_HS = "m_axi_mat_C_ch_5_W.ready" *)input m_axi_mat_C_ch_5_WREADY; - (* RS_HS = "m_axi_mat_C_ch_5_W.data" *)output [63:0] m_axi_mat_C_ch_5_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_5_W.valid" *)output m_axi_mat_C_ch_5_WVALID; - (* RS_HS = "m_axi_mat_C_ch_6_AR.data" *)output [63:0] m_axi_mat_C_ch_6_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_6_AR.data" *)output [1:0] m_axi_mat_C_ch_6_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_6_AR.data" *)output [3:0] m_axi_mat_C_ch_6_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_6_AR.data" *)output [0:0] m_axi_mat_C_ch_6_ARID; - (* RS_HS = "m_axi_mat_C_ch_6_AR.data" *)output [7:0] m_axi_mat_C_ch_6_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_6_AR.data" *)output m_axi_mat_C_ch_6_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_6_AR.data" *)output [2:0] m_axi_mat_C_ch_6_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_6_AR.data" *)output [3:0] m_axi_mat_C_ch_6_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_6_AR.ready" *)input m_axi_mat_C_ch_6_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_6_AR.data" *)output [2:0] m_axi_mat_C_ch_6_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_6_AR.valid" *)output m_axi_mat_C_ch_6_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_6_AW.data" *)output [63:0] m_axi_mat_C_ch_6_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_6_AW.data" *)output [1:0] m_axi_mat_C_ch_6_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_6_AW.data" *)output [3:0] m_axi_mat_C_ch_6_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_6_AW.data" *)output [0:0] m_axi_mat_C_ch_6_AWID; - (* RS_HS = "m_axi_mat_C_ch_6_AW.data" *)output [7:0] m_axi_mat_C_ch_6_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_6_AW.data" *)output m_axi_mat_C_ch_6_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_6_AW.data" *)output [2:0] m_axi_mat_C_ch_6_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_6_AW.data" *)output [3:0] m_axi_mat_C_ch_6_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_6_AW.ready" *)input m_axi_mat_C_ch_6_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_6_AW.data" *)output [2:0] m_axi_mat_C_ch_6_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_6_AW.valid" *)output m_axi_mat_C_ch_6_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_6_B.data" *)input [0:0] m_axi_mat_C_ch_6_BID; - (* RS_HS = "m_axi_mat_C_ch_6_B.ready" *)output m_axi_mat_C_ch_6_BREADY; - (* RS_HS = "m_axi_mat_C_ch_6_B.data" *)input [1:0] m_axi_mat_C_ch_6_BRESP; - (* RS_HS = "m_axi_mat_C_ch_6_B.valid" *)input m_axi_mat_C_ch_6_BVALID; - (* RS_HS = "m_axi_mat_C_ch_6_R.data" *)input [511:0] m_axi_mat_C_ch_6_RDATA; - (* RS_HS = "m_axi_mat_C_ch_6_R.data" *)input [0:0] m_axi_mat_C_ch_6_RID; - (* RS_HS = "m_axi_mat_C_ch_6_R.data" *)input m_axi_mat_C_ch_6_RLAST; - (* RS_HS = "m_axi_mat_C_ch_6_R.ready" *)output m_axi_mat_C_ch_6_RREADY; - (* RS_HS = "m_axi_mat_C_ch_6_R.data" *)input [1:0] m_axi_mat_C_ch_6_RRESP; - (* RS_HS = "m_axi_mat_C_ch_6_R.valid" *)input m_axi_mat_C_ch_6_RVALID; - (* RS_HS = "m_axi_mat_C_ch_6_W.data" *)output [511:0] m_axi_mat_C_ch_6_WDATA; - (* RS_HS = "m_axi_mat_C_ch_6_W.data" *)output m_axi_mat_C_ch_6_WLAST; - (* RS_HS = "m_axi_mat_C_ch_6_W.ready" *)input m_axi_mat_C_ch_6_WREADY; - (* RS_HS = "m_axi_mat_C_ch_6_W.data" *)output [63:0] m_axi_mat_C_ch_6_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_6_W.valid" *)output m_axi_mat_C_ch_6_WVALID; - (* RS_HS = "m_axi_mat_C_ch_7_AR.data" *)output [63:0] m_axi_mat_C_ch_7_ARADDR; - (* RS_HS = "m_axi_mat_C_ch_7_AR.data" *)output [1:0] m_axi_mat_C_ch_7_ARBURST; - (* RS_HS = "m_axi_mat_C_ch_7_AR.data" *)output [3:0] m_axi_mat_C_ch_7_ARCACHE; - (* RS_HS = "m_axi_mat_C_ch_7_AR.data" *)output [0:0] m_axi_mat_C_ch_7_ARID; - (* RS_HS = "m_axi_mat_C_ch_7_AR.data" *)output [7:0] m_axi_mat_C_ch_7_ARLEN; - (* RS_HS = "m_axi_mat_C_ch_7_AR.data" *)output m_axi_mat_C_ch_7_ARLOCK; - (* RS_HS = "m_axi_mat_C_ch_7_AR.data" *)output [2:0] m_axi_mat_C_ch_7_ARPROT; - (* RS_HS = "m_axi_mat_C_ch_7_AR.data" *)output [3:0] m_axi_mat_C_ch_7_ARQOS; - (* RS_HS = "m_axi_mat_C_ch_7_AR.ready" *)input m_axi_mat_C_ch_7_ARREADY; - (* RS_HS = "m_axi_mat_C_ch_7_AR.data" *)output [2:0] m_axi_mat_C_ch_7_ARSIZE; - (* RS_HS = "m_axi_mat_C_ch_7_AR.valid" *)output m_axi_mat_C_ch_7_ARVALID; - (* RS_HS = "m_axi_mat_C_ch_7_AW.data" *)output [63:0] m_axi_mat_C_ch_7_AWADDR; - (* RS_HS = "m_axi_mat_C_ch_7_AW.data" *)output [1:0] m_axi_mat_C_ch_7_AWBURST; - (* RS_HS = "m_axi_mat_C_ch_7_AW.data" *)output [3:0] m_axi_mat_C_ch_7_AWCACHE; - (* RS_HS = "m_axi_mat_C_ch_7_AW.data" *)output [0:0] m_axi_mat_C_ch_7_AWID; - (* RS_HS = "m_axi_mat_C_ch_7_AW.data" *)output [7:0] m_axi_mat_C_ch_7_AWLEN; - (* RS_HS = "m_axi_mat_C_ch_7_AW.data" *)output m_axi_mat_C_ch_7_AWLOCK; - (* RS_HS = "m_axi_mat_C_ch_7_AW.data" *)output [2:0] m_axi_mat_C_ch_7_AWPROT; - (* RS_HS = "m_axi_mat_C_ch_7_AW.data" *)output [3:0] m_axi_mat_C_ch_7_AWQOS; - (* RS_HS = "m_axi_mat_C_ch_7_AW.ready" *)input m_axi_mat_C_ch_7_AWREADY; - (* RS_HS = "m_axi_mat_C_ch_7_AW.data" *)output [2:0] m_axi_mat_C_ch_7_AWSIZE; - (* RS_HS = "m_axi_mat_C_ch_7_AW.valid" *)output m_axi_mat_C_ch_7_AWVALID; - (* RS_HS = "m_axi_mat_C_ch_7_B.data" *)input [0:0] m_axi_mat_C_ch_7_BID; - (* RS_HS = "m_axi_mat_C_ch_7_B.ready" *)output m_axi_mat_C_ch_7_BREADY; - (* RS_HS = "m_axi_mat_C_ch_7_B.data" *)input [1:0] m_axi_mat_C_ch_7_BRESP; - (* RS_HS = "m_axi_mat_C_ch_7_B.valid" *)input m_axi_mat_C_ch_7_BVALID; - (* RS_HS = "m_axi_mat_C_ch_7_R.data" *)input [511:0] m_axi_mat_C_ch_7_RDATA; - (* RS_HS = "m_axi_mat_C_ch_7_R.data" *)input [0:0] m_axi_mat_C_ch_7_RID; - (* RS_HS = "m_axi_mat_C_ch_7_R.data" *)input m_axi_mat_C_ch_7_RLAST; - (* RS_HS = "m_axi_mat_C_ch_7_R.ready" *)output m_axi_mat_C_ch_7_RREADY; - (* RS_HS = "m_axi_mat_C_ch_7_R.data" *)input [1:0] m_axi_mat_C_ch_7_RRESP; - (* RS_HS = "m_axi_mat_C_ch_7_R.valid" *)input m_axi_mat_C_ch_7_RVALID; - (* RS_HS = "m_axi_mat_C_ch_7_W.data" *)output [511:0] m_axi_mat_C_ch_7_WDATA; - (* RS_HS = "m_axi_mat_C_ch_7_W.data" *)output m_axi_mat_C_ch_7_WLAST; - (* RS_HS = "m_axi_mat_C_ch_7_W.ready" *)input m_axi_mat_C_ch_7_WREADY; - (* RS_HS = "m_axi_mat_C_ch_7_W.data" *)output [63:0] m_axi_mat_C_ch_7_WSTRB; - (* RS_HS = "m_axi_mat_C_ch_7_W.valid" *)output m_axi_mat_C_ch_7_WVALID; - wire ap_start; - wire [63:0] edge_list_ptr; - wire [63:0] edge_list_ch_0; - wire [63:0] edge_list_ch_1; - wire [63:0] edge_list_ch_2; - wire [63:0] edge_list_ch_3; - wire [63:0] edge_list_ch_4; - wire [63:0] edge_list_ch_5; - wire [63:0] edge_list_ch_6; - wire [63:0] edge_list_ch_7; - wire [63:0] mat_B_ch_0; - wire [63:0] mat_B_ch_1; - wire [63:0] mat_B_ch_2; - wire [63:0] mat_B_ch_3; - wire [63:0] mat_C_ch_in_0; - wire [63:0] mat_C_ch_in_1; - wire [63:0] mat_C_ch_in_2; - wire [63:0] mat_C_ch_in_3; - wire [63:0] mat_C_ch_in_4; - wire [63:0] mat_C_ch_in_5; - wire [63:0] mat_C_ch_in_6; - wire [63:0] mat_C_ch_in_7; - wire [63:0] mat_C_ch_0; - wire [63:0] mat_C_ch_1; - wire [63:0] mat_C_ch_2; - wire [63:0] mat_C_ch_3; - wire [63:0] mat_C_ch_4; - wire [63:0] mat_C_ch_5; - wire [63:0] mat_C_ch_6; - wire [63:0] mat_C_ch_7; - wire [31:0] NUM_ITE; - wire [31:0] NUM_A_LEN; - wire [31:0] M; - wire [31:0] K; - wire [31:0] P_N; - wire [31:0] alpha_u; - wire [31:0] beta_u; - wire [32:0] PE_inst_Sextans_0__dout; - wire PE_inst_Sextans_0__empty_n; - wire PE_inst_Sextans_0__read; - wire [32:0] PE_inst_Sextans_0__din; - wire PE_inst_Sextans_0__full_n; - wire PE_inst_Sextans_0__write; - wire [32:0] PE_inst_Sextans_10__dout; - wire PE_inst_Sextans_10__empty_n; - wire PE_inst_Sextans_10__read; - wire [32:0] PE_inst_Sextans_10__din; - wire PE_inst_Sextans_10__full_n; - wire PE_inst_Sextans_10__write; - wire [32:0] PE_inst_Sextans_11__dout; - wire PE_inst_Sextans_11__empty_n; - wire PE_inst_Sextans_11__read; - wire [32:0] PE_inst_Sextans_11__din; - wire PE_inst_Sextans_11__full_n; - wire PE_inst_Sextans_11__write; - wire [32:0] PE_inst_Sextans_12__dout; - wire PE_inst_Sextans_12__empty_n; - wire PE_inst_Sextans_12__read; - wire [32:0] PE_inst_Sextans_12__din; - wire PE_inst_Sextans_12__full_n; - wire PE_inst_Sextans_12__write; - wire [32:0] PE_inst_Sextans_13__dout; - wire PE_inst_Sextans_13__empty_n; - wire PE_inst_Sextans_13__read; - wire [32:0] PE_inst_Sextans_13__din; - wire PE_inst_Sextans_13__full_n; - wire PE_inst_Sextans_13__write; - wire [32:0] PE_inst_Sextans_14__dout; - wire PE_inst_Sextans_14__empty_n; - wire PE_inst_Sextans_14__read; - wire [32:0] PE_inst_Sextans_14__din; - wire PE_inst_Sextans_14__full_n; - wire PE_inst_Sextans_14__write; - wire [32:0] PE_inst_Sextans_15__dout; - wire PE_inst_Sextans_15__empty_n; - wire PE_inst_Sextans_15__read; - wire [32:0] PE_inst_Sextans_15__din; - wire PE_inst_Sextans_15__full_n; - wire PE_inst_Sextans_15__write; - wire [32:0] PE_inst_Sextans_16__dout; - wire PE_inst_Sextans_16__empty_n; - wire PE_inst_Sextans_16__read; - wire [32:0] PE_inst_Sextans_16__din; - wire PE_inst_Sextans_16__full_n; - wire PE_inst_Sextans_16__write; - wire [32:0] PE_inst_Sextans_1__dout; - wire PE_inst_Sextans_1__empty_n; - wire PE_inst_Sextans_1__read; - wire [32:0] PE_inst_Sextans_1__din; - wire PE_inst_Sextans_1__full_n; - wire PE_inst_Sextans_1__write; - wire [32:0] PE_inst_Sextans_2__dout; - wire PE_inst_Sextans_2__empty_n; - wire PE_inst_Sextans_2__read; - wire [32:0] PE_inst_Sextans_2__din; - wire PE_inst_Sextans_2__full_n; - wire PE_inst_Sextans_2__write; - wire [32:0] PE_inst_Sextans_3__dout; - wire PE_inst_Sextans_3__empty_n; - wire PE_inst_Sextans_3__read; - wire [32:0] PE_inst_Sextans_3__din; - wire PE_inst_Sextans_3__full_n; - wire PE_inst_Sextans_3__write; - wire [32:0] PE_inst_Sextans_4__dout; - wire PE_inst_Sextans_4__empty_n; - wire PE_inst_Sextans_4__read; - wire [32:0] PE_inst_Sextans_4__din; - wire PE_inst_Sextans_4__full_n; - wire PE_inst_Sextans_4__write; - wire [32:0] PE_inst_Sextans_5__dout; - wire PE_inst_Sextans_5__empty_n; - wire PE_inst_Sextans_5__read; - wire [32:0] PE_inst_Sextans_5__din; - wire PE_inst_Sextans_5__full_n; - wire PE_inst_Sextans_5__write; - wire [32:0] PE_inst_Sextans_6__dout; - wire PE_inst_Sextans_6__empty_n; - wire PE_inst_Sextans_6__read; - wire [32:0] PE_inst_Sextans_6__din; - wire PE_inst_Sextans_6__full_n; - wire PE_inst_Sextans_6__write; - wire [32:0] PE_inst_Sextans_7__dout; - wire PE_inst_Sextans_7__empty_n; - wire PE_inst_Sextans_7__read; - wire [32:0] PE_inst_Sextans_7__din; - wire PE_inst_Sextans_7__full_n; - wire PE_inst_Sextans_7__write; - wire [32:0] PE_inst_Sextans_8__dout; - wire PE_inst_Sextans_8__empty_n; - wire PE_inst_Sextans_8__read; - wire [32:0] PE_inst_Sextans_8__din; - wire PE_inst_Sextans_8__full_n; - wire PE_inst_Sextans_8__write; - wire [32:0] PE_inst_Sextans_9__dout; - wire PE_inst_Sextans_9__empty_n; - wire PE_inst_Sextans_9__read; - wire [32:0] PE_inst_Sextans_9__din; - wire PE_inst_Sextans_9__full_n; - wire PE_inst_Sextans_9__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_0__dout; - wire PE_inst_to_Cmtx_Sextans_0__empty_n; - wire PE_inst_to_Cmtx_Sextans_0__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_0__din; - wire PE_inst_to_Cmtx_Sextans_0__full_n; - wire PE_inst_to_Cmtx_Sextans_0__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_10__dout; - wire PE_inst_to_Cmtx_Sextans_10__empty_n; - wire PE_inst_to_Cmtx_Sextans_10__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_10__din; - wire PE_inst_to_Cmtx_Sextans_10__full_n; - wire PE_inst_to_Cmtx_Sextans_10__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_11__dout; - wire PE_inst_to_Cmtx_Sextans_11__empty_n; - wire PE_inst_to_Cmtx_Sextans_11__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_11__din; - wire PE_inst_to_Cmtx_Sextans_11__full_n; - wire PE_inst_to_Cmtx_Sextans_11__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_12__dout; - wire PE_inst_to_Cmtx_Sextans_12__empty_n; - wire PE_inst_to_Cmtx_Sextans_12__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_12__din; - wire PE_inst_to_Cmtx_Sextans_12__full_n; - wire PE_inst_to_Cmtx_Sextans_12__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_13__dout; - wire PE_inst_to_Cmtx_Sextans_13__empty_n; - wire PE_inst_to_Cmtx_Sextans_13__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_13__din; - wire PE_inst_to_Cmtx_Sextans_13__full_n; - wire PE_inst_to_Cmtx_Sextans_13__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_14__dout; - wire PE_inst_to_Cmtx_Sextans_14__empty_n; - wire PE_inst_to_Cmtx_Sextans_14__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_14__din; - wire PE_inst_to_Cmtx_Sextans_14__full_n; - wire PE_inst_to_Cmtx_Sextans_14__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_15__dout; - wire PE_inst_to_Cmtx_Sextans_15__empty_n; - wire PE_inst_to_Cmtx_Sextans_15__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_15__din; - wire PE_inst_to_Cmtx_Sextans_15__full_n; - wire PE_inst_to_Cmtx_Sextans_15__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_1__dout; - wire PE_inst_to_Cmtx_Sextans_1__empty_n; - wire PE_inst_to_Cmtx_Sextans_1__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_1__din; - wire PE_inst_to_Cmtx_Sextans_1__full_n; - wire PE_inst_to_Cmtx_Sextans_1__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_2__dout; - wire PE_inst_to_Cmtx_Sextans_2__empty_n; - wire PE_inst_to_Cmtx_Sextans_2__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_2__din; - wire PE_inst_to_Cmtx_Sextans_2__full_n; - wire PE_inst_to_Cmtx_Sextans_2__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_3__dout; - wire PE_inst_to_Cmtx_Sextans_3__empty_n; - wire PE_inst_to_Cmtx_Sextans_3__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_3__din; - wire PE_inst_to_Cmtx_Sextans_3__full_n; - wire PE_inst_to_Cmtx_Sextans_3__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_4__dout; - wire PE_inst_to_Cmtx_Sextans_4__empty_n; - wire PE_inst_to_Cmtx_Sextans_4__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_4__din; - wire PE_inst_to_Cmtx_Sextans_4__full_n; - wire PE_inst_to_Cmtx_Sextans_4__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_5__dout; - wire PE_inst_to_Cmtx_Sextans_5__empty_n; - wire PE_inst_to_Cmtx_Sextans_5__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_5__din; - wire PE_inst_to_Cmtx_Sextans_5__full_n; - wire PE_inst_to_Cmtx_Sextans_5__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_6__dout; - wire PE_inst_to_Cmtx_Sextans_6__empty_n; - wire PE_inst_to_Cmtx_Sextans_6__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_6__din; - wire PE_inst_to_Cmtx_Sextans_6__full_n; - wire PE_inst_to_Cmtx_Sextans_6__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_7__dout; - wire PE_inst_to_Cmtx_Sextans_7__empty_n; - wire PE_inst_to_Cmtx_Sextans_7__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_7__din; - wire PE_inst_to_Cmtx_Sextans_7__full_n; - wire PE_inst_to_Cmtx_Sextans_7__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_8__dout; - wire PE_inst_to_Cmtx_Sextans_8__empty_n; - wire PE_inst_to_Cmtx_Sextans_8__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_8__din; - wire PE_inst_to_Cmtx_Sextans_8__full_n; - wire PE_inst_to_Cmtx_Sextans_8__write; - wire [32:0] PE_inst_to_Cmtx_Sextans_9__dout; - wire PE_inst_to_Cmtx_Sextans_9__empty_n; - wire PE_inst_to_Cmtx_Sextans_9__read; - wire [32:0] PE_inst_to_Cmtx_Sextans_9__din; - wire PE_inst_to_Cmtx_Sextans_9__full_n; - wire PE_inst_to_Cmtx_Sextans_9__write; - wire [512:0] fifo_A_Sextans_0__dout; - wire fifo_A_Sextans_0__empty_n; - wire fifo_A_Sextans_0__read; - wire [512:0] fifo_A_Sextans_0__din; - wire fifo_A_Sextans_0__full_n; - wire fifo_A_Sextans_0__write; - wire [512:0] fifo_A_Sextans_1__dout; - wire fifo_A_Sextans_1__empty_n; - wire fifo_A_Sextans_1__read; - wire [512:0] fifo_A_Sextans_1__din; - wire fifo_A_Sextans_1__full_n; - wire fifo_A_Sextans_1__write; - wire [512:0] fifo_A_Sextans_2__dout; - wire fifo_A_Sextans_2__empty_n; - wire fifo_A_Sextans_2__read; - wire [512:0] fifo_A_Sextans_2__din; - wire fifo_A_Sextans_2__full_n; - wire fifo_A_Sextans_2__write; - wire [512:0] fifo_A_Sextans_3__dout; - wire fifo_A_Sextans_3__empty_n; - wire fifo_A_Sextans_3__read; - wire [512:0] fifo_A_Sextans_3__din; - wire fifo_A_Sextans_3__full_n; - wire fifo_A_Sextans_3__write; - wire [512:0] fifo_A_Sextans_4__dout; - wire fifo_A_Sextans_4__empty_n; - wire fifo_A_Sextans_4__read; - wire [512:0] fifo_A_Sextans_4__din; - wire fifo_A_Sextans_4__full_n; - wire fifo_A_Sextans_4__write; - wire [512:0] fifo_A_Sextans_5__dout; - wire fifo_A_Sextans_5__empty_n; - wire fifo_A_Sextans_5__read; - wire [512:0] fifo_A_Sextans_5__din; - wire fifo_A_Sextans_5__full_n; - wire fifo_A_Sextans_5__write; - wire [512:0] fifo_A_Sextans_6__dout; - wire fifo_A_Sextans_6__empty_n; - wire fifo_A_Sextans_6__read; - wire [512:0] fifo_A_Sextans_6__din; - wire fifo_A_Sextans_6__full_n; - wire fifo_A_Sextans_6__write; - wire [512:0] fifo_A_Sextans_7__dout; - wire fifo_A_Sextans_7__empty_n; - wire fifo_A_Sextans_7__read; - wire [512:0] fifo_A_Sextans_7__din; - wire fifo_A_Sextans_7__full_n; - wire fifo_A_Sextans_7__write; - wire [256:0] fifo_A_pe_Sextans_0__dout; - wire fifo_A_pe_Sextans_0__empty_n; - wire fifo_A_pe_Sextans_0__read; - wire [256:0] fifo_A_pe_Sextans_0__din; - wire fifo_A_pe_Sextans_0__full_n; - wire fifo_A_pe_Sextans_0__write; - wire [256:0] fifo_A_pe_Sextans_10__dout; - wire fifo_A_pe_Sextans_10__empty_n; - wire fifo_A_pe_Sextans_10__read; - wire [256:0] fifo_A_pe_Sextans_10__din; - wire fifo_A_pe_Sextans_10__full_n; - wire fifo_A_pe_Sextans_10__write; - wire [256:0] fifo_A_pe_Sextans_11__dout; - wire fifo_A_pe_Sextans_11__empty_n; - wire fifo_A_pe_Sextans_11__read; - wire [256:0] fifo_A_pe_Sextans_11__din; - wire fifo_A_pe_Sextans_11__full_n; - wire fifo_A_pe_Sextans_11__write; - wire [256:0] fifo_A_pe_Sextans_12__dout; - wire fifo_A_pe_Sextans_12__empty_n; - wire fifo_A_pe_Sextans_12__read; - wire [256:0] fifo_A_pe_Sextans_12__din; - wire fifo_A_pe_Sextans_12__full_n; - wire fifo_A_pe_Sextans_12__write; - wire [256:0] fifo_A_pe_Sextans_13__dout; - wire fifo_A_pe_Sextans_13__empty_n; - wire fifo_A_pe_Sextans_13__read; - wire [256:0] fifo_A_pe_Sextans_13__din; - wire fifo_A_pe_Sextans_13__full_n; - wire fifo_A_pe_Sextans_13__write; - wire [256:0] fifo_A_pe_Sextans_14__dout; - wire fifo_A_pe_Sextans_14__empty_n; - wire fifo_A_pe_Sextans_14__read; - wire [256:0] fifo_A_pe_Sextans_14__din; - wire fifo_A_pe_Sextans_14__full_n; - wire fifo_A_pe_Sextans_14__write; - wire [256:0] fifo_A_pe_Sextans_15__dout; - wire fifo_A_pe_Sextans_15__empty_n; - wire fifo_A_pe_Sextans_15__read; - wire [256:0] fifo_A_pe_Sextans_15__din; - wire fifo_A_pe_Sextans_15__full_n; - wire fifo_A_pe_Sextans_15__write; - wire [256:0] fifo_A_pe_Sextans_1__dout; - wire fifo_A_pe_Sextans_1__empty_n; - wire fifo_A_pe_Sextans_1__read; - wire [256:0] fifo_A_pe_Sextans_1__din; - wire fifo_A_pe_Sextans_1__full_n; - wire fifo_A_pe_Sextans_1__write; - wire [256:0] fifo_A_pe_Sextans_2__dout; - wire fifo_A_pe_Sextans_2__empty_n; - wire fifo_A_pe_Sextans_2__read; - wire [256:0] fifo_A_pe_Sextans_2__din; - wire fifo_A_pe_Sextans_2__full_n; - wire fifo_A_pe_Sextans_2__write; - wire [256:0] fifo_A_pe_Sextans_3__dout; - wire fifo_A_pe_Sextans_3__empty_n; - wire fifo_A_pe_Sextans_3__read; - wire [256:0] fifo_A_pe_Sextans_3__din; - wire fifo_A_pe_Sextans_3__full_n; - wire fifo_A_pe_Sextans_3__write; - wire [256:0] fifo_A_pe_Sextans_4__dout; - wire fifo_A_pe_Sextans_4__empty_n; - wire fifo_A_pe_Sextans_4__read; - wire [256:0] fifo_A_pe_Sextans_4__din; - wire fifo_A_pe_Sextans_4__full_n; - wire fifo_A_pe_Sextans_4__write; - wire [256:0] fifo_A_pe_Sextans_5__dout; - wire fifo_A_pe_Sextans_5__empty_n; - wire fifo_A_pe_Sextans_5__read; - wire [256:0] fifo_A_pe_Sextans_5__din; - wire fifo_A_pe_Sextans_5__full_n; - wire fifo_A_pe_Sextans_5__write; - wire [256:0] fifo_A_pe_Sextans_6__dout; - wire fifo_A_pe_Sextans_6__empty_n; - wire fifo_A_pe_Sextans_6__read; - wire [256:0] fifo_A_pe_Sextans_6__din; - wire fifo_A_pe_Sextans_6__full_n; - wire fifo_A_pe_Sextans_6__write; - wire [256:0] fifo_A_pe_Sextans_7__dout; - wire fifo_A_pe_Sextans_7__empty_n; - wire fifo_A_pe_Sextans_7__read; - wire [256:0] fifo_A_pe_Sextans_7__din; - wire fifo_A_pe_Sextans_7__full_n; - wire fifo_A_pe_Sextans_7__write; - wire [256:0] fifo_A_pe_Sextans_8__dout; - wire fifo_A_pe_Sextans_8__empty_n; - wire fifo_A_pe_Sextans_8__read; - wire [256:0] fifo_A_pe_Sextans_8__din; - wire fifo_A_pe_Sextans_8__full_n; - wire fifo_A_pe_Sextans_8__write; - wire [256:0] fifo_A_pe_Sextans_9__dout; - wire fifo_A_pe_Sextans_9__empty_n; - wire fifo_A_pe_Sextans_9__read; - wire [256:0] fifo_A_pe_Sextans_9__din; - wire fifo_A_pe_Sextans_9__full_n; - wire fifo_A_pe_Sextans_9__write; - wire [512:0] fifo_B_pe_Sextans_0__dout; - wire fifo_B_pe_Sextans_0__empty_n; - wire fifo_B_pe_Sextans_0__read; - wire [512:0] fifo_B_pe_Sextans_0__din; - wire fifo_B_pe_Sextans_0__full_n; - wire fifo_B_pe_Sextans_0__write; - wire [512:0] fifo_B_pe_Sextans_10__dout; - wire fifo_B_pe_Sextans_10__empty_n; - wire fifo_B_pe_Sextans_10__read; - wire [512:0] fifo_B_pe_Sextans_10__din; - wire fifo_B_pe_Sextans_10__full_n; - wire fifo_B_pe_Sextans_10__write; - wire [512:0] fifo_B_pe_Sextans_11__dout; - wire fifo_B_pe_Sextans_11__empty_n; - wire fifo_B_pe_Sextans_11__read; - wire [512:0] fifo_B_pe_Sextans_11__din; - wire fifo_B_pe_Sextans_11__full_n; - wire fifo_B_pe_Sextans_11__write; - wire [512:0] fifo_B_pe_Sextans_12__dout; - wire fifo_B_pe_Sextans_12__empty_n; - wire fifo_B_pe_Sextans_12__read; - wire [512:0] fifo_B_pe_Sextans_12__din; - wire fifo_B_pe_Sextans_12__full_n; - wire fifo_B_pe_Sextans_12__write; - wire [512:0] fifo_B_pe_Sextans_13__dout; - wire fifo_B_pe_Sextans_13__empty_n; - wire fifo_B_pe_Sextans_13__read; - wire [512:0] fifo_B_pe_Sextans_13__din; - wire fifo_B_pe_Sextans_13__full_n; - wire fifo_B_pe_Sextans_13__write; - wire [512:0] fifo_B_pe_Sextans_14__dout; - wire fifo_B_pe_Sextans_14__empty_n; - wire fifo_B_pe_Sextans_14__read; - wire [512:0] fifo_B_pe_Sextans_14__din; - wire fifo_B_pe_Sextans_14__full_n; - wire fifo_B_pe_Sextans_14__write; - wire [512:0] fifo_B_pe_Sextans_15__dout; - wire fifo_B_pe_Sextans_15__empty_n; - wire fifo_B_pe_Sextans_15__read; - wire [512:0] fifo_B_pe_Sextans_15__din; - wire fifo_B_pe_Sextans_15__full_n; - wire fifo_B_pe_Sextans_15__write; - wire [512:0] fifo_B_pe_Sextans_16__dout; - wire fifo_B_pe_Sextans_16__empty_n; - wire fifo_B_pe_Sextans_16__read; - wire [512:0] fifo_B_pe_Sextans_16__din; - wire fifo_B_pe_Sextans_16__full_n; - wire fifo_B_pe_Sextans_16__write; - wire [512:0] fifo_B_pe_Sextans_17__dout; - wire fifo_B_pe_Sextans_17__empty_n; - wire fifo_B_pe_Sextans_17__read; - wire [512:0] fifo_B_pe_Sextans_17__din; - wire fifo_B_pe_Sextans_17__full_n; - wire fifo_B_pe_Sextans_17__write; - wire [512:0] fifo_B_pe_Sextans_18__dout; - wire fifo_B_pe_Sextans_18__empty_n; - wire fifo_B_pe_Sextans_18__read; - wire [512:0] fifo_B_pe_Sextans_18__din; - wire fifo_B_pe_Sextans_18__full_n; - wire fifo_B_pe_Sextans_18__write; - wire [512:0] fifo_B_pe_Sextans_19__dout; - wire fifo_B_pe_Sextans_19__empty_n; - wire fifo_B_pe_Sextans_19__read; - wire [512:0] fifo_B_pe_Sextans_19__din; - wire fifo_B_pe_Sextans_19__full_n; - wire fifo_B_pe_Sextans_19__write; - wire [512:0] fifo_B_pe_Sextans_1__dout; - wire fifo_B_pe_Sextans_1__empty_n; - wire fifo_B_pe_Sextans_1__read; - wire [512:0] fifo_B_pe_Sextans_1__din; - wire fifo_B_pe_Sextans_1__full_n; - wire fifo_B_pe_Sextans_1__write; - wire [512:0] fifo_B_pe_Sextans_20__dout; - wire fifo_B_pe_Sextans_20__empty_n; - wire fifo_B_pe_Sextans_20__read; - wire [512:0] fifo_B_pe_Sextans_20__din; - wire fifo_B_pe_Sextans_20__full_n; - wire fifo_B_pe_Sextans_20__write; - wire [512:0] fifo_B_pe_Sextans_21__dout; - wire fifo_B_pe_Sextans_21__empty_n; - wire fifo_B_pe_Sextans_21__read; - wire [512:0] fifo_B_pe_Sextans_21__din; - wire fifo_B_pe_Sextans_21__full_n; - wire fifo_B_pe_Sextans_21__write; - wire [512:0] fifo_B_pe_Sextans_22__dout; - wire fifo_B_pe_Sextans_22__empty_n; - wire fifo_B_pe_Sextans_22__read; - wire [512:0] fifo_B_pe_Sextans_22__din; - wire fifo_B_pe_Sextans_22__full_n; - wire fifo_B_pe_Sextans_22__write; - wire [512:0] fifo_B_pe_Sextans_23__dout; - wire fifo_B_pe_Sextans_23__empty_n; - wire fifo_B_pe_Sextans_23__read; - wire [512:0] fifo_B_pe_Sextans_23__din; - wire fifo_B_pe_Sextans_23__full_n; - wire fifo_B_pe_Sextans_23__write; - wire [512:0] fifo_B_pe_Sextans_24__dout; - wire fifo_B_pe_Sextans_24__empty_n; - wire fifo_B_pe_Sextans_24__read; - wire [512:0] fifo_B_pe_Sextans_24__din; - wire fifo_B_pe_Sextans_24__full_n; - wire fifo_B_pe_Sextans_24__write; - wire [512:0] fifo_B_pe_Sextans_25__dout; - wire fifo_B_pe_Sextans_25__empty_n; - wire fifo_B_pe_Sextans_25__read; - wire [512:0] fifo_B_pe_Sextans_25__din; - wire fifo_B_pe_Sextans_25__full_n; - wire fifo_B_pe_Sextans_25__write; - wire [512:0] fifo_B_pe_Sextans_26__dout; - wire fifo_B_pe_Sextans_26__empty_n; - wire fifo_B_pe_Sextans_26__read; - wire [512:0] fifo_B_pe_Sextans_26__din; - wire fifo_B_pe_Sextans_26__full_n; - wire fifo_B_pe_Sextans_26__write; - wire [512:0] fifo_B_pe_Sextans_27__dout; - wire fifo_B_pe_Sextans_27__empty_n; - wire fifo_B_pe_Sextans_27__read; - wire [512:0] fifo_B_pe_Sextans_27__din; - wire fifo_B_pe_Sextans_27__full_n; - wire fifo_B_pe_Sextans_27__write; - wire [512:0] fifo_B_pe_Sextans_28__dout; - wire fifo_B_pe_Sextans_28__empty_n; - wire fifo_B_pe_Sextans_28__read; - wire [512:0] fifo_B_pe_Sextans_28__din; - wire fifo_B_pe_Sextans_28__full_n; - wire fifo_B_pe_Sextans_28__write; - wire [512:0] fifo_B_pe_Sextans_29__dout; - wire fifo_B_pe_Sextans_29__empty_n; - wire fifo_B_pe_Sextans_29__read; - wire [512:0] fifo_B_pe_Sextans_29__din; - wire fifo_B_pe_Sextans_29__full_n; - wire fifo_B_pe_Sextans_29__write; - wire [512:0] fifo_B_pe_Sextans_2__dout; - wire fifo_B_pe_Sextans_2__empty_n; - wire fifo_B_pe_Sextans_2__read; - wire [512:0] fifo_B_pe_Sextans_2__din; - wire fifo_B_pe_Sextans_2__full_n; - wire fifo_B_pe_Sextans_2__write; - wire [512:0] fifo_B_pe_Sextans_30__dout; - wire fifo_B_pe_Sextans_30__empty_n; - wire fifo_B_pe_Sextans_30__read; - wire [512:0] fifo_B_pe_Sextans_30__din; - wire fifo_B_pe_Sextans_30__full_n; - wire fifo_B_pe_Sextans_30__write; - wire [512:0] fifo_B_pe_Sextans_31__dout; - wire fifo_B_pe_Sextans_31__empty_n; - wire fifo_B_pe_Sextans_31__read; - wire [512:0] fifo_B_pe_Sextans_31__din; - wire fifo_B_pe_Sextans_31__full_n; - wire fifo_B_pe_Sextans_31__write; - wire [512:0] fifo_B_pe_Sextans_32__dout; - wire fifo_B_pe_Sextans_32__empty_n; - wire fifo_B_pe_Sextans_32__read; - wire [512:0] fifo_B_pe_Sextans_32__din; - wire fifo_B_pe_Sextans_32__full_n; - wire fifo_B_pe_Sextans_32__write; - wire [512:0] fifo_B_pe_Sextans_33__dout; - wire fifo_B_pe_Sextans_33__empty_n; - wire fifo_B_pe_Sextans_33__read; - wire [512:0] fifo_B_pe_Sextans_33__din; - wire fifo_B_pe_Sextans_33__full_n; - wire fifo_B_pe_Sextans_33__write; - wire [512:0] fifo_B_pe_Sextans_34__dout; - wire fifo_B_pe_Sextans_34__empty_n; - wire fifo_B_pe_Sextans_34__read; - wire [512:0] fifo_B_pe_Sextans_34__din; - wire fifo_B_pe_Sextans_34__full_n; - wire fifo_B_pe_Sextans_34__write; - wire [512:0] fifo_B_pe_Sextans_35__dout; - wire fifo_B_pe_Sextans_35__empty_n; - wire fifo_B_pe_Sextans_35__read; - wire [512:0] fifo_B_pe_Sextans_35__din; - wire fifo_B_pe_Sextans_35__full_n; - wire fifo_B_pe_Sextans_35__write; - wire [512:0] fifo_B_pe_Sextans_36__dout; - wire fifo_B_pe_Sextans_36__empty_n; - wire fifo_B_pe_Sextans_36__read; - wire [512:0] fifo_B_pe_Sextans_36__din; - wire fifo_B_pe_Sextans_36__full_n; - wire fifo_B_pe_Sextans_36__write; - wire [512:0] fifo_B_pe_Sextans_37__dout; - wire fifo_B_pe_Sextans_37__empty_n; - wire fifo_B_pe_Sextans_37__read; - wire [512:0] fifo_B_pe_Sextans_37__din; - wire fifo_B_pe_Sextans_37__full_n; - wire fifo_B_pe_Sextans_37__write; - wire [512:0] fifo_B_pe_Sextans_38__dout; - wire fifo_B_pe_Sextans_38__empty_n; - wire fifo_B_pe_Sextans_38__read; - wire [512:0] fifo_B_pe_Sextans_38__din; - wire fifo_B_pe_Sextans_38__full_n; - wire fifo_B_pe_Sextans_38__write; - wire [512:0] fifo_B_pe_Sextans_39__dout; - wire fifo_B_pe_Sextans_39__empty_n; - wire fifo_B_pe_Sextans_39__read; - wire [512:0] fifo_B_pe_Sextans_39__din; - wire fifo_B_pe_Sextans_39__full_n; - wire fifo_B_pe_Sextans_39__write; - wire [512:0] fifo_B_pe_Sextans_3__dout; - wire fifo_B_pe_Sextans_3__empty_n; - wire fifo_B_pe_Sextans_3__read; - wire [512:0] fifo_B_pe_Sextans_3__din; - wire fifo_B_pe_Sextans_3__full_n; - wire fifo_B_pe_Sextans_3__write; - wire [512:0] fifo_B_pe_Sextans_40__dout; - wire fifo_B_pe_Sextans_40__empty_n; - wire fifo_B_pe_Sextans_40__read; - wire [512:0] fifo_B_pe_Sextans_40__din; - wire fifo_B_pe_Sextans_40__full_n; - wire fifo_B_pe_Sextans_40__write; - wire [512:0] fifo_B_pe_Sextans_41__dout; - wire fifo_B_pe_Sextans_41__empty_n; - wire fifo_B_pe_Sextans_41__read; - wire [512:0] fifo_B_pe_Sextans_41__din; - wire fifo_B_pe_Sextans_41__full_n; - wire fifo_B_pe_Sextans_41__write; - wire [512:0] fifo_B_pe_Sextans_42__dout; - wire fifo_B_pe_Sextans_42__empty_n; - wire fifo_B_pe_Sextans_42__read; - wire [512:0] fifo_B_pe_Sextans_42__din; - wire fifo_B_pe_Sextans_42__full_n; - wire fifo_B_pe_Sextans_42__write; - wire [512:0] fifo_B_pe_Sextans_43__dout; - wire fifo_B_pe_Sextans_43__empty_n; - wire fifo_B_pe_Sextans_43__read; - wire [512:0] fifo_B_pe_Sextans_43__din; - wire fifo_B_pe_Sextans_43__full_n; - wire fifo_B_pe_Sextans_43__write; - wire [512:0] fifo_B_pe_Sextans_44__dout; - wire fifo_B_pe_Sextans_44__empty_n; - wire fifo_B_pe_Sextans_44__read; - wire [512:0] fifo_B_pe_Sextans_44__din; - wire fifo_B_pe_Sextans_44__full_n; - wire fifo_B_pe_Sextans_44__write; - wire [512:0] fifo_B_pe_Sextans_45__dout; - wire fifo_B_pe_Sextans_45__empty_n; - wire fifo_B_pe_Sextans_45__read; - wire [512:0] fifo_B_pe_Sextans_45__din; - wire fifo_B_pe_Sextans_45__full_n; - wire fifo_B_pe_Sextans_45__write; - wire [512:0] fifo_B_pe_Sextans_46__dout; - wire fifo_B_pe_Sextans_46__empty_n; - wire fifo_B_pe_Sextans_46__read; - wire [512:0] fifo_B_pe_Sextans_46__din; - wire fifo_B_pe_Sextans_46__full_n; - wire fifo_B_pe_Sextans_46__write; - wire [512:0] fifo_B_pe_Sextans_47__dout; - wire fifo_B_pe_Sextans_47__empty_n; - wire fifo_B_pe_Sextans_47__read; - wire [512:0] fifo_B_pe_Sextans_47__din; - wire fifo_B_pe_Sextans_47__full_n; - wire fifo_B_pe_Sextans_47__write; - wire [512:0] fifo_B_pe_Sextans_48__dout; - wire fifo_B_pe_Sextans_48__empty_n; - wire fifo_B_pe_Sextans_48__read; - wire [512:0] fifo_B_pe_Sextans_48__din; - wire fifo_B_pe_Sextans_48__full_n; - wire fifo_B_pe_Sextans_48__write; - wire [512:0] fifo_B_pe_Sextans_49__dout; - wire fifo_B_pe_Sextans_49__empty_n; - wire fifo_B_pe_Sextans_49__read; - wire [512:0] fifo_B_pe_Sextans_49__din; - wire fifo_B_pe_Sextans_49__full_n; - wire fifo_B_pe_Sextans_49__write; - wire [512:0] fifo_B_pe_Sextans_4__dout; - wire fifo_B_pe_Sextans_4__empty_n; - wire fifo_B_pe_Sextans_4__read; - wire [512:0] fifo_B_pe_Sextans_4__din; - wire fifo_B_pe_Sextans_4__full_n; - wire fifo_B_pe_Sextans_4__write; - wire [512:0] fifo_B_pe_Sextans_50__dout; - wire fifo_B_pe_Sextans_50__empty_n; - wire fifo_B_pe_Sextans_50__read; - wire [512:0] fifo_B_pe_Sextans_50__din; - wire fifo_B_pe_Sextans_50__full_n; - wire fifo_B_pe_Sextans_50__write; - wire [512:0] fifo_B_pe_Sextans_51__dout; - wire fifo_B_pe_Sextans_51__empty_n; - wire fifo_B_pe_Sextans_51__read; - wire [512:0] fifo_B_pe_Sextans_51__din; - wire fifo_B_pe_Sextans_51__full_n; - wire fifo_B_pe_Sextans_51__write; - wire [512:0] fifo_B_pe_Sextans_52__dout; - wire fifo_B_pe_Sextans_52__empty_n; - wire fifo_B_pe_Sextans_52__read; - wire [512:0] fifo_B_pe_Sextans_52__din; - wire fifo_B_pe_Sextans_52__full_n; - wire fifo_B_pe_Sextans_52__write; - wire [512:0] fifo_B_pe_Sextans_53__dout; - wire fifo_B_pe_Sextans_53__empty_n; - wire fifo_B_pe_Sextans_53__read; - wire [512:0] fifo_B_pe_Sextans_53__din; - wire fifo_B_pe_Sextans_53__full_n; - wire fifo_B_pe_Sextans_53__write; - wire [512:0] fifo_B_pe_Sextans_54__dout; - wire fifo_B_pe_Sextans_54__empty_n; - wire fifo_B_pe_Sextans_54__read; - wire [512:0] fifo_B_pe_Sextans_54__din; - wire fifo_B_pe_Sextans_54__full_n; - wire fifo_B_pe_Sextans_54__write; - wire [512:0] fifo_B_pe_Sextans_55__dout; - wire fifo_B_pe_Sextans_55__empty_n; - wire fifo_B_pe_Sextans_55__read; - wire [512:0] fifo_B_pe_Sextans_55__din; - wire fifo_B_pe_Sextans_55__full_n; - wire fifo_B_pe_Sextans_55__write; - wire [512:0] fifo_B_pe_Sextans_56__dout; - wire fifo_B_pe_Sextans_56__empty_n; - wire fifo_B_pe_Sextans_56__read; - wire [512:0] fifo_B_pe_Sextans_56__din; - wire fifo_B_pe_Sextans_56__full_n; - wire fifo_B_pe_Sextans_56__write; - wire [512:0] fifo_B_pe_Sextans_57__dout; - wire fifo_B_pe_Sextans_57__empty_n; - wire fifo_B_pe_Sextans_57__read; - wire [512:0] fifo_B_pe_Sextans_57__din; - wire fifo_B_pe_Sextans_57__full_n; - wire fifo_B_pe_Sextans_57__write; - wire [512:0] fifo_B_pe_Sextans_58__dout; - wire fifo_B_pe_Sextans_58__empty_n; - wire fifo_B_pe_Sextans_58__read; - wire [512:0] fifo_B_pe_Sextans_58__din; - wire fifo_B_pe_Sextans_58__full_n; - wire fifo_B_pe_Sextans_58__write; - wire [512:0] fifo_B_pe_Sextans_59__dout; - wire fifo_B_pe_Sextans_59__empty_n; - wire fifo_B_pe_Sextans_59__read; - wire [512:0] fifo_B_pe_Sextans_59__din; - wire fifo_B_pe_Sextans_59__full_n; - wire fifo_B_pe_Sextans_59__write; - wire [512:0] fifo_B_pe_Sextans_5__dout; - wire fifo_B_pe_Sextans_5__empty_n; - wire fifo_B_pe_Sextans_5__read; - wire [512:0] fifo_B_pe_Sextans_5__din; - wire fifo_B_pe_Sextans_5__full_n; - wire fifo_B_pe_Sextans_5__write; - wire [512:0] fifo_B_pe_Sextans_60__dout; - wire fifo_B_pe_Sextans_60__empty_n; - wire fifo_B_pe_Sextans_60__read; - wire [512:0] fifo_B_pe_Sextans_60__din; - wire fifo_B_pe_Sextans_60__full_n; - wire fifo_B_pe_Sextans_60__write; - wire [512:0] fifo_B_pe_Sextans_61__dout; - wire fifo_B_pe_Sextans_61__empty_n; - wire fifo_B_pe_Sextans_61__read; - wire [512:0] fifo_B_pe_Sextans_61__din; - wire fifo_B_pe_Sextans_61__full_n; - wire fifo_B_pe_Sextans_61__write; - wire [512:0] fifo_B_pe_Sextans_62__dout; - wire fifo_B_pe_Sextans_62__empty_n; - wire fifo_B_pe_Sextans_62__read; - wire [512:0] fifo_B_pe_Sextans_62__din; - wire fifo_B_pe_Sextans_62__full_n; - wire fifo_B_pe_Sextans_62__write; - wire [512:0] fifo_B_pe_Sextans_63__dout; - wire fifo_B_pe_Sextans_63__empty_n; - wire fifo_B_pe_Sextans_63__read; - wire [512:0] fifo_B_pe_Sextans_63__din; - wire fifo_B_pe_Sextans_63__full_n; - wire fifo_B_pe_Sextans_63__write; - wire [512:0] fifo_B_pe_Sextans_64__dout; - wire fifo_B_pe_Sextans_64__empty_n; - wire fifo_B_pe_Sextans_64__read; - wire [512:0] fifo_B_pe_Sextans_64__din; - wire fifo_B_pe_Sextans_64__full_n; - wire fifo_B_pe_Sextans_64__write; - wire [512:0] fifo_B_pe_Sextans_65__dout; - wire fifo_B_pe_Sextans_65__empty_n; - wire fifo_B_pe_Sextans_65__read; - wire [512:0] fifo_B_pe_Sextans_65__din; - wire fifo_B_pe_Sextans_65__full_n; - wire fifo_B_pe_Sextans_65__write; - wire [512:0] fifo_B_pe_Sextans_66__dout; - wire fifo_B_pe_Sextans_66__empty_n; - wire fifo_B_pe_Sextans_66__read; - wire [512:0] fifo_B_pe_Sextans_66__din; - wire fifo_B_pe_Sextans_66__full_n; - wire fifo_B_pe_Sextans_66__write; - wire [512:0] fifo_B_pe_Sextans_67__dout; - wire fifo_B_pe_Sextans_67__empty_n; - wire fifo_B_pe_Sextans_67__read; - wire [512:0] fifo_B_pe_Sextans_67__din; - wire fifo_B_pe_Sextans_67__full_n; - wire fifo_B_pe_Sextans_67__write; - wire [512:0] fifo_B_pe_Sextans_6__dout; - wire fifo_B_pe_Sextans_6__empty_n; - wire fifo_B_pe_Sextans_6__read; - wire [512:0] fifo_B_pe_Sextans_6__din; - wire fifo_B_pe_Sextans_6__full_n; - wire fifo_B_pe_Sextans_6__write; - wire [512:0] fifo_B_pe_Sextans_7__dout; - wire fifo_B_pe_Sextans_7__empty_n; - wire fifo_B_pe_Sextans_7__read; - wire [512:0] fifo_B_pe_Sextans_7__din; - wire fifo_B_pe_Sextans_7__full_n; - wire fifo_B_pe_Sextans_7__write; - wire [512:0] fifo_B_pe_Sextans_8__dout; - wire fifo_B_pe_Sextans_8__empty_n; - wire fifo_B_pe_Sextans_8__read; - wire [512:0] fifo_B_pe_Sextans_8__din; - wire fifo_B_pe_Sextans_8__full_n; - wire fifo_B_pe_Sextans_8__write; - wire [512:0] fifo_B_pe_Sextans_9__dout; - wire fifo_B_pe_Sextans_9__empty_n; - wire fifo_B_pe_Sextans_9__read; - wire [512:0] fifo_B_pe_Sextans_9__din; - wire fifo_B_pe_Sextans_9__full_n; - wire fifo_B_pe_Sextans_9__write; - wire [512:0] fifo_C_ch_Sextans_0__dout; - wire fifo_C_ch_Sextans_0__empty_n; - wire fifo_C_ch_Sextans_0__read; - wire [512:0] fifo_C_ch_Sextans_0__din; - wire fifo_C_ch_Sextans_0__full_n; - wire fifo_C_ch_Sextans_0__write; - wire [512:0] fifo_C_ch_Sextans_1__dout; - wire fifo_C_ch_Sextans_1__empty_n; - wire fifo_C_ch_Sextans_1__read; - wire [512:0] fifo_C_ch_Sextans_1__din; - wire fifo_C_ch_Sextans_1__full_n; - wire fifo_C_ch_Sextans_1__write; - wire [512:0] fifo_C_ch_Sextans_2__dout; - wire fifo_C_ch_Sextans_2__empty_n; - wire fifo_C_ch_Sextans_2__read; - wire [512:0] fifo_C_ch_Sextans_2__din; - wire fifo_C_ch_Sextans_2__full_n; - wire fifo_C_ch_Sextans_2__write; - wire [512:0] fifo_C_ch_Sextans_3__dout; - wire fifo_C_ch_Sextans_3__empty_n; - wire fifo_C_ch_Sextans_3__read; - wire [512:0] fifo_C_ch_Sextans_3__din; - wire fifo_C_ch_Sextans_3__full_n; - wire fifo_C_ch_Sextans_3__write; - wire [512:0] fifo_C_ch_Sextans_4__dout; - wire fifo_C_ch_Sextans_4__empty_n; - wire fifo_C_ch_Sextans_4__read; - wire [512:0] fifo_C_ch_Sextans_4__din; - wire fifo_C_ch_Sextans_4__full_n; - wire fifo_C_ch_Sextans_4__write; - wire [512:0] fifo_C_ch_Sextans_5__dout; - wire fifo_C_ch_Sextans_5__empty_n; - wire fifo_C_ch_Sextans_5__read; - wire [512:0] fifo_C_ch_Sextans_5__din; - wire fifo_C_ch_Sextans_5__full_n; - wire fifo_C_ch_Sextans_5__write; - wire [512:0] fifo_C_ch_Sextans_6__dout; - wire fifo_C_ch_Sextans_6__empty_n; - wire fifo_C_ch_Sextans_6__read; - wire [512:0] fifo_C_ch_Sextans_6__din; - wire fifo_C_ch_Sextans_6__full_n; - wire fifo_C_ch_Sextans_6__write; - wire [512:0] fifo_C_ch_Sextans_7__dout; - wire fifo_C_ch_Sextans_7__empty_n; - wire fifo_C_ch_Sextans_7__read; - wire [512:0] fifo_C_ch_Sextans_7__din; - wire fifo_C_ch_Sextans_7__full_n; - wire fifo_C_ch_Sextans_7__write; - wire [512:0] fifo_C_ch_result_Sextans_0__dout; - wire fifo_C_ch_result_Sextans_0__empty_n; - wire fifo_C_ch_result_Sextans_0__read; - wire [512:0] fifo_C_ch_result_Sextans_0__din; - wire fifo_C_ch_result_Sextans_0__full_n; - wire fifo_C_ch_result_Sextans_0__write; - wire [512:0] fifo_C_ch_result_Sextans_1__dout; - wire fifo_C_ch_result_Sextans_1__empty_n; - wire fifo_C_ch_result_Sextans_1__read; - wire [512:0] fifo_C_ch_result_Sextans_1__din; - wire fifo_C_ch_result_Sextans_1__full_n; - wire fifo_C_ch_result_Sextans_1__write; - wire [512:0] fifo_C_ch_result_Sextans_2__dout; - wire fifo_C_ch_result_Sextans_2__empty_n; - wire fifo_C_ch_result_Sextans_2__read; - wire [512:0] fifo_C_ch_result_Sextans_2__din; - wire fifo_C_ch_result_Sextans_2__full_n; - wire fifo_C_ch_result_Sextans_2__write; - wire [512:0] fifo_C_ch_result_Sextans_3__dout; - wire fifo_C_ch_result_Sextans_3__empty_n; - wire fifo_C_ch_result_Sextans_3__read; - wire [512:0] fifo_C_ch_result_Sextans_3__din; - wire fifo_C_ch_result_Sextans_3__full_n; - wire fifo_C_ch_result_Sextans_3__write; - wire [512:0] fifo_C_ch_result_Sextans_4__dout; - wire fifo_C_ch_result_Sextans_4__empty_n; - wire fifo_C_ch_result_Sextans_4__read; - wire [512:0] fifo_C_ch_result_Sextans_4__din; - wire fifo_C_ch_result_Sextans_4__full_n; - wire fifo_C_ch_result_Sextans_4__write; - wire [512:0] fifo_C_ch_result_Sextans_5__dout; - wire fifo_C_ch_result_Sextans_5__empty_n; - wire fifo_C_ch_result_Sextans_5__read; - wire [512:0] fifo_C_ch_result_Sextans_5__din; - wire fifo_C_ch_result_Sextans_5__full_n; - wire fifo_C_ch_result_Sextans_5__write; - wire [512:0] fifo_C_ch_result_Sextans_6__dout; - wire fifo_C_ch_result_Sextans_6__empty_n; - wire fifo_C_ch_result_Sextans_6__read; - wire [512:0] fifo_C_ch_result_Sextans_6__din; - wire fifo_C_ch_result_Sextans_6__full_n; - wire fifo_C_ch_result_Sextans_6__write; - wire [512:0] fifo_C_ch_result_Sextans_7__dout; - wire fifo_C_ch_result_Sextans_7__empty_n; - wire fifo_C_ch_result_Sextans_7__read; - wire [512:0] fifo_C_ch_result_Sextans_7__din; - wire fifo_C_ch_result_Sextans_7__full_n; - wire fifo_C_ch_result_Sextans_7__write; - wire [512:0] fifo_C_ch_result_alpha_Sextans_0__dout; - wire fifo_C_ch_result_alpha_Sextans_0__empty_n; - wire fifo_C_ch_result_alpha_Sextans_0__read; - wire [512:0] fifo_C_ch_result_alpha_Sextans_0__din; - wire fifo_C_ch_result_alpha_Sextans_0__full_n; - wire fifo_C_ch_result_alpha_Sextans_0__write; - wire [512:0] fifo_C_ch_result_alpha_Sextans_1__dout; - wire fifo_C_ch_result_alpha_Sextans_1__empty_n; - wire fifo_C_ch_result_alpha_Sextans_1__read; - wire [512:0] fifo_C_ch_result_alpha_Sextans_1__din; - wire fifo_C_ch_result_alpha_Sextans_1__full_n; - wire fifo_C_ch_result_alpha_Sextans_1__write; - wire [512:0] fifo_C_ch_result_alpha_Sextans_2__dout; - wire fifo_C_ch_result_alpha_Sextans_2__empty_n; - wire fifo_C_ch_result_alpha_Sextans_2__read; - wire [512:0] fifo_C_ch_result_alpha_Sextans_2__din; - wire fifo_C_ch_result_alpha_Sextans_2__full_n; - wire fifo_C_ch_result_alpha_Sextans_2__write; - wire [512:0] fifo_C_ch_result_alpha_Sextans_3__dout; - wire fifo_C_ch_result_alpha_Sextans_3__empty_n; - wire fifo_C_ch_result_alpha_Sextans_3__read; - wire [512:0] fifo_C_ch_result_alpha_Sextans_3__din; - wire fifo_C_ch_result_alpha_Sextans_3__full_n; - wire fifo_C_ch_result_alpha_Sextans_3__write; - wire [512:0] fifo_C_ch_result_alpha_Sextans_4__dout; - wire fifo_C_ch_result_alpha_Sextans_4__empty_n; - wire fifo_C_ch_result_alpha_Sextans_4__read; - wire [512:0] fifo_C_ch_result_alpha_Sextans_4__din; - wire fifo_C_ch_result_alpha_Sextans_4__full_n; - wire fifo_C_ch_result_alpha_Sextans_4__write; - wire [512:0] fifo_C_ch_result_alpha_Sextans_5__dout; - wire fifo_C_ch_result_alpha_Sextans_5__empty_n; - wire fifo_C_ch_result_alpha_Sextans_5__read; - wire [512:0] fifo_C_ch_result_alpha_Sextans_5__din; - wire fifo_C_ch_result_alpha_Sextans_5__full_n; - wire fifo_C_ch_result_alpha_Sextans_5__write; - wire [512:0] fifo_C_ch_result_alpha_Sextans_6__dout; - wire fifo_C_ch_result_alpha_Sextans_6__empty_n; - wire fifo_C_ch_result_alpha_Sextans_6__read; - wire [512:0] fifo_C_ch_result_alpha_Sextans_6__din; - wire fifo_C_ch_result_alpha_Sextans_6__full_n; - wire fifo_C_ch_result_alpha_Sextans_6__write; - wire [512:0] fifo_C_ch_result_alpha_Sextans_7__dout; - wire fifo_C_ch_result_alpha_Sextans_7__empty_n; - wire fifo_C_ch_result_alpha_Sextans_7__read; - wire [512:0] fifo_C_ch_result_alpha_Sextans_7__din; - wire fifo_C_ch_result_alpha_Sextans_7__full_n; - wire fifo_C_ch_result_alpha_Sextans_7__write; - wire [256:0] fifo_C_pe_Sextans_0__dout; - wire fifo_C_pe_Sextans_0__empty_n; - wire fifo_C_pe_Sextans_0__read; - wire [256:0] fifo_C_pe_Sextans_0__din; - wire fifo_C_pe_Sextans_0__full_n; - wire fifo_C_pe_Sextans_0__write; - wire [256:0] fifo_C_pe_Sextans_10__dout; - wire fifo_C_pe_Sextans_10__empty_n; - wire fifo_C_pe_Sextans_10__read; - wire [256:0] fifo_C_pe_Sextans_10__din; - wire fifo_C_pe_Sextans_10__full_n; - wire fifo_C_pe_Sextans_10__write; - wire [256:0] fifo_C_pe_Sextans_11__dout; - wire fifo_C_pe_Sextans_11__empty_n; - wire fifo_C_pe_Sextans_11__read; - wire [256:0] fifo_C_pe_Sextans_11__din; - wire fifo_C_pe_Sextans_11__full_n; - wire fifo_C_pe_Sextans_11__write; - wire [256:0] fifo_C_pe_Sextans_12__dout; - wire fifo_C_pe_Sextans_12__empty_n; - wire fifo_C_pe_Sextans_12__read; - wire [256:0] fifo_C_pe_Sextans_12__din; - wire fifo_C_pe_Sextans_12__full_n; - wire fifo_C_pe_Sextans_12__write; - wire [256:0] fifo_C_pe_Sextans_13__dout; - wire fifo_C_pe_Sextans_13__empty_n; - wire fifo_C_pe_Sextans_13__read; - wire [256:0] fifo_C_pe_Sextans_13__din; - wire fifo_C_pe_Sextans_13__full_n; - wire fifo_C_pe_Sextans_13__write; - wire [256:0] fifo_C_pe_Sextans_14__dout; - wire fifo_C_pe_Sextans_14__empty_n; - wire fifo_C_pe_Sextans_14__read; - wire [256:0] fifo_C_pe_Sextans_14__din; - wire fifo_C_pe_Sextans_14__full_n; - wire fifo_C_pe_Sextans_14__write; - wire [256:0] fifo_C_pe_Sextans_15__dout; - wire fifo_C_pe_Sextans_15__empty_n; - wire fifo_C_pe_Sextans_15__read; - wire [256:0] fifo_C_pe_Sextans_15__din; - wire fifo_C_pe_Sextans_15__full_n; - wire fifo_C_pe_Sextans_15__write; - wire [256:0] fifo_C_pe_Sextans_1__dout; - wire fifo_C_pe_Sextans_1__empty_n; - wire fifo_C_pe_Sextans_1__read; - wire [256:0] fifo_C_pe_Sextans_1__din; - wire fifo_C_pe_Sextans_1__full_n; - wire fifo_C_pe_Sextans_1__write; - wire [256:0] fifo_C_pe_Sextans_2__dout; - wire fifo_C_pe_Sextans_2__empty_n; - wire fifo_C_pe_Sextans_2__read; - wire [256:0] fifo_C_pe_Sextans_2__din; - wire fifo_C_pe_Sextans_2__full_n; - wire fifo_C_pe_Sextans_2__write; - wire [256:0] fifo_C_pe_Sextans_3__dout; - wire fifo_C_pe_Sextans_3__empty_n; - wire fifo_C_pe_Sextans_3__read; - wire [256:0] fifo_C_pe_Sextans_3__din; - wire fifo_C_pe_Sextans_3__full_n; - wire fifo_C_pe_Sextans_3__write; - wire [256:0] fifo_C_pe_Sextans_4__dout; - wire fifo_C_pe_Sextans_4__empty_n; - wire fifo_C_pe_Sextans_4__read; - wire [256:0] fifo_C_pe_Sextans_4__din; - wire fifo_C_pe_Sextans_4__full_n; - wire fifo_C_pe_Sextans_4__write; - wire [256:0] fifo_C_pe_Sextans_5__dout; - wire fifo_C_pe_Sextans_5__empty_n; - wire fifo_C_pe_Sextans_5__read; - wire [256:0] fifo_C_pe_Sextans_5__din; - wire fifo_C_pe_Sextans_5__full_n; - wire fifo_C_pe_Sextans_5__write; - wire [256:0] fifo_C_pe_Sextans_6__dout; - wire fifo_C_pe_Sextans_6__empty_n; - wire fifo_C_pe_Sextans_6__read; - wire [256:0] fifo_C_pe_Sextans_6__din; - wire fifo_C_pe_Sextans_6__full_n; - wire fifo_C_pe_Sextans_6__write; - wire [256:0] fifo_C_pe_Sextans_7__dout; - wire fifo_C_pe_Sextans_7__empty_n; - wire fifo_C_pe_Sextans_7__read; - wire [256:0] fifo_C_pe_Sextans_7__din; - wire fifo_C_pe_Sextans_7__full_n; - wire fifo_C_pe_Sextans_7__write; - wire [256:0] fifo_C_pe_Sextans_8__dout; - wire fifo_C_pe_Sextans_8__empty_n; - wire fifo_C_pe_Sextans_8__read; - wire [256:0] fifo_C_pe_Sextans_8__din; - wire fifo_C_pe_Sextans_8__full_n; - wire fifo_C_pe_Sextans_8__write; - wire [256:0] fifo_C_pe_Sextans_9__dout; - wire fifo_C_pe_Sextans_9__empty_n; - wire fifo_C_pe_Sextans_9__read; - wire [256:0] fifo_C_pe_Sextans_9__din; - wire fifo_C_pe_Sextans_9__full_n; - wire fifo_C_pe_Sextans_9__write; - wire [512:0] fifo_C_read_in_Sextans_0__dout; - wire fifo_C_read_in_Sextans_0__empty_n; - wire fifo_C_read_in_Sextans_0__read; - wire [512:0] fifo_C_read_in_Sextans_0__din; - wire fifo_C_read_in_Sextans_0__full_n; - wire fifo_C_read_in_Sextans_0__write; - wire [512:0] fifo_C_read_in_Sextans_1__dout; - wire fifo_C_read_in_Sextans_1__empty_n; - wire fifo_C_read_in_Sextans_1__read; - wire [512:0] fifo_C_read_in_Sextans_1__din; - wire fifo_C_read_in_Sextans_1__full_n; - wire fifo_C_read_in_Sextans_1__write; - wire [512:0] fifo_C_read_in_Sextans_2__dout; - wire fifo_C_read_in_Sextans_2__empty_n; - wire fifo_C_read_in_Sextans_2__read; - wire [512:0] fifo_C_read_in_Sextans_2__din; - wire fifo_C_read_in_Sextans_2__full_n; - wire fifo_C_read_in_Sextans_2__write; - wire [512:0] fifo_C_read_in_Sextans_3__dout; - wire fifo_C_read_in_Sextans_3__empty_n; - wire fifo_C_read_in_Sextans_3__read; - wire [512:0] fifo_C_read_in_Sextans_3__din; - wire fifo_C_read_in_Sextans_3__full_n; - wire fifo_C_read_in_Sextans_3__write; - wire [512:0] fifo_C_read_in_Sextans_4__dout; - wire fifo_C_read_in_Sextans_4__empty_n; - wire fifo_C_read_in_Sextans_4__read; - wire [512:0] fifo_C_read_in_Sextans_4__din; - wire fifo_C_read_in_Sextans_4__full_n; - wire fifo_C_read_in_Sextans_4__write; - wire [512:0] fifo_C_read_in_Sextans_5__dout; - wire fifo_C_read_in_Sextans_5__empty_n; - wire fifo_C_read_in_Sextans_5__read; - wire [512:0] fifo_C_read_in_Sextans_5__din; - wire fifo_C_read_in_Sextans_5__full_n; - wire fifo_C_read_in_Sextans_5__write; - wire [512:0] fifo_C_read_in_Sextans_6__dout; - wire fifo_C_read_in_Sextans_6__empty_n; - wire fifo_C_read_in_Sextans_6__read; - wire [512:0] fifo_C_read_in_Sextans_6__din; - wire fifo_C_read_in_Sextans_6__full_n; - wire fifo_C_read_in_Sextans_6__write; - wire [512:0] fifo_C_read_in_Sextans_7__dout; - wire fifo_C_read_in_Sextans_7__empty_n; - wire fifo_C_read_in_Sextans_7__read; - wire [512:0] fifo_C_read_in_Sextans_7__din; - wire fifo_C_read_in_Sextans_7__full_n; - wire fifo_C_read_in_Sextans_7__write; - wire [512:0] fifo_C_read_in_beta_Sextans_0__dout; - wire fifo_C_read_in_beta_Sextans_0__empty_n; - wire fifo_C_read_in_beta_Sextans_0__read; - wire [512:0] fifo_C_read_in_beta_Sextans_0__din; - wire fifo_C_read_in_beta_Sextans_0__full_n; - wire fifo_C_read_in_beta_Sextans_0__write; - wire [512:0] fifo_C_read_in_beta_Sextans_1__dout; - wire fifo_C_read_in_beta_Sextans_1__empty_n; - wire fifo_C_read_in_beta_Sextans_1__read; - wire [512:0] fifo_C_read_in_beta_Sextans_1__din; - wire fifo_C_read_in_beta_Sextans_1__full_n; - wire fifo_C_read_in_beta_Sextans_1__write; - wire [512:0] fifo_C_read_in_beta_Sextans_2__dout; - wire fifo_C_read_in_beta_Sextans_2__empty_n; - wire fifo_C_read_in_beta_Sextans_2__read; - wire [512:0] fifo_C_read_in_beta_Sextans_2__din; - wire fifo_C_read_in_beta_Sextans_2__full_n; - wire fifo_C_read_in_beta_Sextans_2__write; - wire [512:0] fifo_C_read_in_beta_Sextans_3__dout; - wire fifo_C_read_in_beta_Sextans_3__empty_n; - wire fifo_C_read_in_beta_Sextans_3__read; - wire [512:0] fifo_C_read_in_beta_Sextans_3__din; - wire fifo_C_read_in_beta_Sextans_3__full_n; - wire fifo_C_read_in_beta_Sextans_3__write; - wire [512:0] fifo_C_read_in_beta_Sextans_4__dout; - wire fifo_C_read_in_beta_Sextans_4__empty_n; - wire fifo_C_read_in_beta_Sextans_4__read; - wire [512:0] fifo_C_read_in_beta_Sextans_4__din; - wire fifo_C_read_in_beta_Sextans_4__full_n; - wire fifo_C_read_in_beta_Sextans_4__write; - wire [512:0] fifo_C_read_in_beta_Sextans_5__dout; - wire fifo_C_read_in_beta_Sextans_5__empty_n; - wire fifo_C_read_in_beta_Sextans_5__read; - wire [512:0] fifo_C_read_in_beta_Sextans_5__din; - wire fifo_C_read_in_beta_Sextans_5__full_n; - wire fifo_C_read_in_beta_Sextans_5__write; - wire [512:0] fifo_C_read_in_beta_Sextans_6__dout; - wire fifo_C_read_in_beta_Sextans_6__empty_n; - wire fifo_C_read_in_beta_Sextans_6__read; - wire [512:0] fifo_C_read_in_beta_Sextans_6__din; - wire fifo_C_read_in_beta_Sextans_6__full_n; - wire fifo_C_read_in_beta_Sextans_6__write; - wire [512:0] fifo_C_read_in_beta_Sextans_7__dout; - wire fifo_C_read_in_beta_Sextans_7__empty_n; - wire fifo_C_read_in_beta_Sextans_7__read; - wire [512:0] fifo_C_read_in_beta_Sextans_7__din; - wire fifo_C_read_in_beta_Sextans_7__full_n; - wire fifo_C_read_in_beta_Sextans_7__write; - wire [274:0] fifo_aBvec_Sextans_0__dout; - wire fifo_aBvec_Sextans_0__empty_n; - wire fifo_aBvec_Sextans_0__read; - wire [274:0] fifo_aBvec_Sextans_0__din; - wire fifo_aBvec_Sextans_0__full_n; - wire fifo_aBvec_Sextans_0__write; - wire [274:0] fifo_aBvec_Sextans_10__dout; - wire fifo_aBvec_Sextans_10__empty_n; - wire fifo_aBvec_Sextans_10__read; - wire [274:0] fifo_aBvec_Sextans_10__din; - wire fifo_aBvec_Sextans_10__full_n; - wire fifo_aBvec_Sextans_10__write; - wire [274:0] fifo_aBvec_Sextans_11__dout; - wire fifo_aBvec_Sextans_11__empty_n; - wire fifo_aBvec_Sextans_11__read; - wire [274:0] fifo_aBvec_Sextans_11__din; - wire fifo_aBvec_Sextans_11__full_n; - wire fifo_aBvec_Sextans_11__write; - wire [274:0] fifo_aBvec_Sextans_12__dout; - wire fifo_aBvec_Sextans_12__empty_n; - wire fifo_aBvec_Sextans_12__read; - wire [274:0] fifo_aBvec_Sextans_12__din; - wire fifo_aBvec_Sextans_12__full_n; - wire fifo_aBvec_Sextans_12__write; - wire [274:0] fifo_aBvec_Sextans_13__dout; - wire fifo_aBvec_Sextans_13__empty_n; - wire fifo_aBvec_Sextans_13__read; - wire [274:0] fifo_aBvec_Sextans_13__din; - wire fifo_aBvec_Sextans_13__full_n; - wire fifo_aBvec_Sextans_13__write; - wire [274:0] fifo_aBvec_Sextans_14__dout; - wire fifo_aBvec_Sextans_14__empty_n; - wire fifo_aBvec_Sextans_14__read; - wire [274:0] fifo_aBvec_Sextans_14__din; - wire fifo_aBvec_Sextans_14__full_n; - wire fifo_aBvec_Sextans_14__write; - wire [274:0] fifo_aBvec_Sextans_15__dout; - wire fifo_aBvec_Sextans_15__empty_n; - wire fifo_aBvec_Sextans_15__read; - wire [274:0] fifo_aBvec_Sextans_15__din; - wire fifo_aBvec_Sextans_15__full_n; - wire fifo_aBvec_Sextans_15__write; - wire [274:0] fifo_aBvec_Sextans_16__dout; - wire fifo_aBvec_Sextans_16__empty_n; - wire fifo_aBvec_Sextans_16__read; - wire [274:0] fifo_aBvec_Sextans_16__din; - wire fifo_aBvec_Sextans_16__full_n; - wire fifo_aBvec_Sextans_16__write; - wire [274:0] fifo_aBvec_Sextans_17__dout; - wire fifo_aBvec_Sextans_17__empty_n; - wire fifo_aBvec_Sextans_17__read; - wire [274:0] fifo_aBvec_Sextans_17__din; - wire fifo_aBvec_Sextans_17__full_n; - wire fifo_aBvec_Sextans_17__write; - wire [274:0] fifo_aBvec_Sextans_18__dout; - wire fifo_aBvec_Sextans_18__empty_n; - wire fifo_aBvec_Sextans_18__read; - wire [274:0] fifo_aBvec_Sextans_18__din; - wire fifo_aBvec_Sextans_18__full_n; - wire fifo_aBvec_Sextans_18__write; - wire [274:0] fifo_aBvec_Sextans_19__dout; - wire fifo_aBvec_Sextans_19__empty_n; - wire fifo_aBvec_Sextans_19__read; - wire [274:0] fifo_aBvec_Sextans_19__din; - wire fifo_aBvec_Sextans_19__full_n; - wire fifo_aBvec_Sextans_19__write; - wire [274:0] fifo_aBvec_Sextans_1__dout; - wire fifo_aBvec_Sextans_1__empty_n; - wire fifo_aBvec_Sextans_1__read; - wire [274:0] fifo_aBvec_Sextans_1__din; - wire fifo_aBvec_Sextans_1__full_n; - wire fifo_aBvec_Sextans_1__write; - wire [274:0] fifo_aBvec_Sextans_20__dout; - wire fifo_aBvec_Sextans_20__empty_n; - wire fifo_aBvec_Sextans_20__read; - wire [274:0] fifo_aBvec_Sextans_20__din; - wire fifo_aBvec_Sextans_20__full_n; - wire fifo_aBvec_Sextans_20__write; - wire [274:0] fifo_aBvec_Sextans_21__dout; - wire fifo_aBvec_Sextans_21__empty_n; - wire fifo_aBvec_Sextans_21__read; - wire [274:0] fifo_aBvec_Sextans_21__din; - wire fifo_aBvec_Sextans_21__full_n; - wire fifo_aBvec_Sextans_21__write; - wire [274:0] fifo_aBvec_Sextans_22__dout; - wire fifo_aBvec_Sextans_22__empty_n; - wire fifo_aBvec_Sextans_22__read; - wire [274:0] fifo_aBvec_Sextans_22__din; - wire fifo_aBvec_Sextans_22__full_n; - wire fifo_aBvec_Sextans_22__write; - wire [274:0] fifo_aBvec_Sextans_23__dout; - wire fifo_aBvec_Sextans_23__empty_n; - wire fifo_aBvec_Sextans_23__read; - wire [274:0] fifo_aBvec_Sextans_23__din; - wire fifo_aBvec_Sextans_23__full_n; - wire fifo_aBvec_Sextans_23__write; - wire [274:0] fifo_aBvec_Sextans_24__dout; - wire fifo_aBvec_Sextans_24__empty_n; - wire fifo_aBvec_Sextans_24__read; - wire [274:0] fifo_aBvec_Sextans_24__din; - wire fifo_aBvec_Sextans_24__full_n; - wire fifo_aBvec_Sextans_24__write; - wire [274:0] fifo_aBvec_Sextans_25__dout; - wire fifo_aBvec_Sextans_25__empty_n; - wire fifo_aBvec_Sextans_25__read; - wire [274:0] fifo_aBvec_Sextans_25__din; - wire fifo_aBvec_Sextans_25__full_n; - wire fifo_aBvec_Sextans_25__write; - wire [274:0] fifo_aBvec_Sextans_26__dout; - wire fifo_aBvec_Sextans_26__empty_n; - wire fifo_aBvec_Sextans_26__read; - wire [274:0] fifo_aBvec_Sextans_26__din; - wire fifo_aBvec_Sextans_26__full_n; - wire fifo_aBvec_Sextans_26__write; - wire [274:0] fifo_aBvec_Sextans_27__dout; - wire fifo_aBvec_Sextans_27__empty_n; - wire fifo_aBvec_Sextans_27__read; - wire [274:0] fifo_aBvec_Sextans_27__din; - wire fifo_aBvec_Sextans_27__full_n; - wire fifo_aBvec_Sextans_27__write; - wire [274:0] fifo_aBvec_Sextans_28__dout; - wire fifo_aBvec_Sextans_28__empty_n; - wire fifo_aBvec_Sextans_28__read; - wire [274:0] fifo_aBvec_Sextans_28__din; - wire fifo_aBvec_Sextans_28__full_n; - wire fifo_aBvec_Sextans_28__write; - wire [274:0] fifo_aBvec_Sextans_29__dout; - wire fifo_aBvec_Sextans_29__empty_n; - wire fifo_aBvec_Sextans_29__read; - wire [274:0] fifo_aBvec_Sextans_29__din; - wire fifo_aBvec_Sextans_29__full_n; - wire fifo_aBvec_Sextans_29__write; - wire [274:0] fifo_aBvec_Sextans_2__dout; - wire fifo_aBvec_Sextans_2__empty_n; - wire fifo_aBvec_Sextans_2__read; - wire [274:0] fifo_aBvec_Sextans_2__din; - wire fifo_aBvec_Sextans_2__full_n; - wire fifo_aBvec_Sextans_2__write; - wire [274:0] fifo_aBvec_Sextans_30__dout; - wire fifo_aBvec_Sextans_30__empty_n; - wire fifo_aBvec_Sextans_30__read; - wire [274:0] fifo_aBvec_Sextans_30__din; - wire fifo_aBvec_Sextans_30__full_n; - wire fifo_aBvec_Sextans_30__write; - wire [274:0] fifo_aBvec_Sextans_31__dout; - wire fifo_aBvec_Sextans_31__empty_n; - wire fifo_aBvec_Sextans_31__read; - wire [274:0] fifo_aBvec_Sextans_31__din; - wire fifo_aBvec_Sextans_31__full_n; - wire fifo_aBvec_Sextans_31__write; - wire [274:0] fifo_aBvec_Sextans_32__dout; - wire fifo_aBvec_Sextans_32__empty_n; - wire fifo_aBvec_Sextans_32__read; - wire [274:0] fifo_aBvec_Sextans_32__din; - wire fifo_aBvec_Sextans_32__full_n; - wire fifo_aBvec_Sextans_32__write; - wire [274:0] fifo_aBvec_Sextans_33__dout; - wire fifo_aBvec_Sextans_33__empty_n; - wire fifo_aBvec_Sextans_33__read; - wire [274:0] fifo_aBvec_Sextans_33__din; - wire fifo_aBvec_Sextans_33__full_n; - wire fifo_aBvec_Sextans_33__write; - wire [274:0] fifo_aBvec_Sextans_34__dout; - wire fifo_aBvec_Sextans_34__empty_n; - wire fifo_aBvec_Sextans_34__read; - wire [274:0] fifo_aBvec_Sextans_34__din; - wire fifo_aBvec_Sextans_34__full_n; - wire fifo_aBvec_Sextans_34__write; - wire [274:0] fifo_aBvec_Sextans_35__dout; - wire fifo_aBvec_Sextans_35__empty_n; - wire fifo_aBvec_Sextans_35__read; - wire [274:0] fifo_aBvec_Sextans_35__din; - wire fifo_aBvec_Sextans_35__full_n; - wire fifo_aBvec_Sextans_35__write; - wire [274:0] fifo_aBvec_Sextans_36__dout; - wire fifo_aBvec_Sextans_36__empty_n; - wire fifo_aBvec_Sextans_36__read; - wire [274:0] fifo_aBvec_Sextans_36__din; - wire fifo_aBvec_Sextans_36__full_n; - wire fifo_aBvec_Sextans_36__write; - wire [274:0] fifo_aBvec_Sextans_37__dout; - wire fifo_aBvec_Sextans_37__empty_n; - wire fifo_aBvec_Sextans_37__read; - wire [274:0] fifo_aBvec_Sextans_37__din; - wire fifo_aBvec_Sextans_37__full_n; - wire fifo_aBvec_Sextans_37__write; - wire [274:0] fifo_aBvec_Sextans_38__dout; - wire fifo_aBvec_Sextans_38__empty_n; - wire fifo_aBvec_Sextans_38__read; - wire [274:0] fifo_aBvec_Sextans_38__din; - wire fifo_aBvec_Sextans_38__full_n; - wire fifo_aBvec_Sextans_38__write; - wire [274:0] fifo_aBvec_Sextans_39__dout; - wire fifo_aBvec_Sextans_39__empty_n; - wire fifo_aBvec_Sextans_39__read; - wire [274:0] fifo_aBvec_Sextans_39__din; - wire fifo_aBvec_Sextans_39__full_n; - wire fifo_aBvec_Sextans_39__write; - wire [274:0] fifo_aBvec_Sextans_3__dout; - wire fifo_aBvec_Sextans_3__empty_n; - wire fifo_aBvec_Sextans_3__read; - wire [274:0] fifo_aBvec_Sextans_3__din; - wire fifo_aBvec_Sextans_3__full_n; - wire fifo_aBvec_Sextans_3__write; - wire [274:0] fifo_aBvec_Sextans_40__dout; - wire fifo_aBvec_Sextans_40__empty_n; - wire fifo_aBvec_Sextans_40__read; - wire [274:0] fifo_aBvec_Sextans_40__din; - wire fifo_aBvec_Sextans_40__full_n; - wire fifo_aBvec_Sextans_40__write; - wire [274:0] fifo_aBvec_Sextans_41__dout; - wire fifo_aBvec_Sextans_41__empty_n; - wire fifo_aBvec_Sextans_41__read; - wire [274:0] fifo_aBvec_Sextans_41__din; - wire fifo_aBvec_Sextans_41__full_n; - wire fifo_aBvec_Sextans_41__write; - wire [274:0] fifo_aBvec_Sextans_42__dout; - wire fifo_aBvec_Sextans_42__empty_n; - wire fifo_aBvec_Sextans_42__read; - wire [274:0] fifo_aBvec_Sextans_42__din; - wire fifo_aBvec_Sextans_42__full_n; - wire fifo_aBvec_Sextans_42__write; - wire [274:0] fifo_aBvec_Sextans_43__dout; - wire fifo_aBvec_Sextans_43__empty_n; - wire fifo_aBvec_Sextans_43__read; - wire [274:0] fifo_aBvec_Sextans_43__din; - wire fifo_aBvec_Sextans_43__full_n; - wire fifo_aBvec_Sextans_43__write; - wire [274:0] fifo_aBvec_Sextans_44__dout; - wire fifo_aBvec_Sextans_44__empty_n; - wire fifo_aBvec_Sextans_44__read; - wire [274:0] fifo_aBvec_Sextans_44__din; - wire fifo_aBvec_Sextans_44__full_n; - wire fifo_aBvec_Sextans_44__write; - wire [274:0] fifo_aBvec_Sextans_45__dout; - wire fifo_aBvec_Sextans_45__empty_n; - wire fifo_aBvec_Sextans_45__read; - wire [274:0] fifo_aBvec_Sextans_45__din; - wire fifo_aBvec_Sextans_45__full_n; - wire fifo_aBvec_Sextans_45__write; - wire [274:0] fifo_aBvec_Sextans_46__dout; - wire fifo_aBvec_Sextans_46__empty_n; - wire fifo_aBvec_Sextans_46__read; - wire [274:0] fifo_aBvec_Sextans_46__din; - wire fifo_aBvec_Sextans_46__full_n; - wire fifo_aBvec_Sextans_46__write; - wire [274:0] fifo_aBvec_Sextans_47__dout; - wire fifo_aBvec_Sextans_47__empty_n; - wire fifo_aBvec_Sextans_47__read; - wire [274:0] fifo_aBvec_Sextans_47__din; - wire fifo_aBvec_Sextans_47__full_n; - wire fifo_aBvec_Sextans_47__write; - wire [274:0] fifo_aBvec_Sextans_48__dout; - wire fifo_aBvec_Sextans_48__empty_n; - wire fifo_aBvec_Sextans_48__read; - wire [274:0] fifo_aBvec_Sextans_48__din; - wire fifo_aBvec_Sextans_48__full_n; - wire fifo_aBvec_Sextans_48__write; - wire [274:0] fifo_aBvec_Sextans_49__dout; - wire fifo_aBvec_Sextans_49__empty_n; - wire fifo_aBvec_Sextans_49__read; - wire [274:0] fifo_aBvec_Sextans_49__din; - wire fifo_aBvec_Sextans_49__full_n; - wire fifo_aBvec_Sextans_49__write; - wire [274:0] fifo_aBvec_Sextans_4__dout; - wire fifo_aBvec_Sextans_4__empty_n; - wire fifo_aBvec_Sextans_4__read; - wire [274:0] fifo_aBvec_Sextans_4__din; - wire fifo_aBvec_Sextans_4__full_n; - wire fifo_aBvec_Sextans_4__write; - wire [274:0] fifo_aBvec_Sextans_50__dout; - wire fifo_aBvec_Sextans_50__empty_n; - wire fifo_aBvec_Sextans_50__read; - wire [274:0] fifo_aBvec_Sextans_50__din; - wire fifo_aBvec_Sextans_50__full_n; - wire fifo_aBvec_Sextans_50__write; - wire [274:0] fifo_aBvec_Sextans_51__dout; - wire fifo_aBvec_Sextans_51__empty_n; - wire fifo_aBvec_Sextans_51__read; - wire [274:0] fifo_aBvec_Sextans_51__din; - wire fifo_aBvec_Sextans_51__full_n; - wire fifo_aBvec_Sextans_51__write; - wire [274:0] fifo_aBvec_Sextans_52__dout; - wire fifo_aBvec_Sextans_52__empty_n; - wire fifo_aBvec_Sextans_52__read; - wire [274:0] fifo_aBvec_Sextans_52__din; - wire fifo_aBvec_Sextans_52__full_n; - wire fifo_aBvec_Sextans_52__write; - wire [274:0] fifo_aBvec_Sextans_53__dout; - wire fifo_aBvec_Sextans_53__empty_n; - wire fifo_aBvec_Sextans_53__read; - wire [274:0] fifo_aBvec_Sextans_53__din; - wire fifo_aBvec_Sextans_53__full_n; - wire fifo_aBvec_Sextans_53__write; - wire [274:0] fifo_aBvec_Sextans_54__dout; - wire fifo_aBvec_Sextans_54__empty_n; - wire fifo_aBvec_Sextans_54__read; - wire [274:0] fifo_aBvec_Sextans_54__din; - wire fifo_aBvec_Sextans_54__full_n; - wire fifo_aBvec_Sextans_54__write; - wire [274:0] fifo_aBvec_Sextans_55__dout; - wire fifo_aBvec_Sextans_55__empty_n; - wire fifo_aBvec_Sextans_55__read; - wire [274:0] fifo_aBvec_Sextans_55__din; - wire fifo_aBvec_Sextans_55__full_n; - wire fifo_aBvec_Sextans_55__write; - wire [274:0] fifo_aBvec_Sextans_56__dout; - wire fifo_aBvec_Sextans_56__empty_n; - wire fifo_aBvec_Sextans_56__read; - wire [274:0] fifo_aBvec_Sextans_56__din; - wire fifo_aBvec_Sextans_56__full_n; - wire fifo_aBvec_Sextans_56__write; - wire [274:0] fifo_aBvec_Sextans_57__dout; - wire fifo_aBvec_Sextans_57__empty_n; - wire fifo_aBvec_Sextans_57__read; - wire [274:0] fifo_aBvec_Sextans_57__din; - wire fifo_aBvec_Sextans_57__full_n; - wire fifo_aBvec_Sextans_57__write; - wire [274:0] fifo_aBvec_Sextans_58__dout; - wire fifo_aBvec_Sextans_58__empty_n; - wire fifo_aBvec_Sextans_58__read; - wire [274:0] fifo_aBvec_Sextans_58__din; - wire fifo_aBvec_Sextans_58__full_n; - wire fifo_aBvec_Sextans_58__write; - wire [274:0] fifo_aBvec_Sextans_59__dout; - wire fifo_aBvec_Sextans_59__empty_n; - wire fifo_aBvec_Sextans_59__read; - wire [274:0] fifo_aBvec_Sextans_59__din; - wire fifo_aBvec_Sextans_59__full_n; - wire fifo_aBvec_Sextans_59__write; - wire [274:0] fifo_aBvec_Sextans_5__dout; - wire fifo_aBvec_Sextans_5__empty_n; - wire fifo_aBvec_Sextans_5__read; - wire [274:0] fifo_aBvec_Sextans_5__din; - wire fifo_aBvec_Sextans_5__full_n; - wire fifo_aBvec_Sextans_5__write; - wire [274:0] fifo_aBvec_Sextans_60__dout; - wire fifo_aBvec_Sextans_60__empty_n; - wire fifo_aBvec_Sextans_60__read; - wire [274:0] fifo_aBvec_Sextans_60__din; - wire fifo_aBvec_Sextans_60__full_n; - wire fifo_aBvec_Sextans_60__write; - wire [274:0] fifo_aBvec_Sextans_61__dout; - wire fifo_aBvec_Sextans_61__empty_n; - wire fifo_aBvec_Sextans_61__read; - wire [274:0] fifo_aBvec_Sextans_61__din; - wire fifo_aBvec_Sextans_61__full_n; - wire fifo_aBvec_Sextans_61__write; - wire [274:0] fifo_aBvec_Sextans_62__dout; - wire fifo_aBvec_Sextans_62__empty_n; - wire fifo_aBvec_Sextans_62__read; - wire [274:0] fifo_aBvec_Sextans_62__din; - wire fifo_aBvec_Sextans_62__full_n; - wire fifo_aBvec_Sextans_62__write; - wire [274:0] fifo_aBvec_Sextans_63__dout; - wire fifo_aBvec_Sextans_63__empty_n; - wire fifo_aBvec_Sextans_63__read; - wire [274:0] fifo_aBvec_Sextans_63__din; - wire fifo_aBvec_Sextans_63__full_n; - wire fifo_aBvec_Sextans_63__write; - wire [274:0] fifo_aBvec_Sextans_6__dout; - wire fifo_aBvec_Sextans_6__empty_n; - wire fifo_aBvec_Sextans_6__read; - wire [274:0] fifo_aBvec_Sextans_6__din; - wire fifo_aBvec_Sextans_6__full_n; - wire fifo_aBvec_Sextans_6__write; - wire [274:0] fifo_aBvec_Sextans_7__dout; - wire fifo_aBvec_Sextans_7__empty_n; - wire fifo_aBvec_Sextans_7__read; - wire [274:0] fifo_aBvec_Sextans_7__din; - wire fifo_aBvec_Sextans_7__full_n; - wire fifo_aBvec_Sextans_7__write; - wire [274:0] fifo_aBvec_Sextans_8__dout; - wire fifo_aBvec_Sextans_8__empty_n; - wire fifo_aBvec_Sextans_8__read; - wire [274:0] fifo_aBvec_Sextans_8__din; - wire fifo_aBvec_Sextans_8__full_n; - wire fifo_aBvec_Sextans_8__write; - wire [274:0] fifo_aBvec_Sextans_9__dout; - wire fifo_aBvec_Sextans_9__empty_n; - wire fifo_aBvec_Sextans_9__read; - wire [274:0] fifo_aBvec_Sextans_9__din; - wire fifo_aBvec_Sextans_9__full_n; - wire fifo_aBvec_Sextans_9__write; - wire [32:0] fifo_edge_list_ptr_Sextans_0__dout; - wire fifo_edge_list_ptr_Sextans_0__empty_n; - wire fifo_edge_list_ptr_Sextans_0__read; - wire [32:0] fifo_edge_list_ptr_Sextans_0__din; - wire fifo_edge_list_ptr_Sextans_0__full_n; - wire fifo_edge_list_ptr_Sextans_0__write; - wire [32:0] fifo_edge_list_ptr_Sextans_10__dout; - wire fifo_edge_list_ptr_Sextans_10__empty_n; - wire fifo_edge_list_ptr_Sextans_10__read; - wire [32:0] fifo_edge_list_ptr_Sextans_10__din; - wire fifo_edge_list_ptr_Sextans_10__full_n; - wire fifo_edge_list_ptr_Sextans_10__write; - wire [32:0] fifo_edge_list_ptr_Sextans_11__dout; - wire fifo_edge_list_ptr_Sextans_11__empty_n; - wire fifo_edge_list_ptr_Sextans_11__read; - wire [32:0] fifo_edge_list_ptr_Sextans_11__din; - wire fifo_edge_list_ptr_Sextans_11__full_n; - wire fifo_edge_list_ptr_Sextans_11__write; - wire [32:0] fifo_edge_list_ptr_Sextans_12__dout; - wire fifo_edge_list_ptr_Sextans_12__empty_n; - wire fifo_edge_list_ptr_Sextans_12__read; - wire [32:0] fifo_edge_list_ptr_Sextans_12__din; - wire fifo_edge_list_ptr_Sextans_12__full_n; - wire fifo_edge_list_ptr_Sextans_12__write; - wire [32:0] fifo_edge_list_ptr_Sextans_13__dout; - wire fifo_edge_list_ptr_Sextans_13__empty_n; - wire fifo_edge_list_ptr_Sextans_13__read; - wire [32:0] fifo_edge_list_ptr_Sextans_13__din; - wire fifo_edge_list_ptr_Sextans_13__full_n; - wire fifo_edge_list_ptr_Sextans_13__write; - wire [32:0] fifo_edge_list_ptr_Sextans_14__dout; - wire fifo_edge_list_ptr_Sextans_14__empty_n; - wire fifo_edge_list_ptr_Sextans_14__read; - wire [32:0] fifo_edge_list_ptr_Sextans_14__din; - wire fifo_edge_list_ptr_Sextans_14__full_n; - wire fifo_edge_list_ptr_Sextans_14__write; - wire [32:0] fifo_edge_list_ptr_Sextans_15__dout; - wire fifo_edge_list_ptr_Sextans_15__empty_n; - wire fifo_edge_list_ptr_Sextans_15__read; - wire [32:0] fifo_edge_list_ptr_Sextans_15__din; - wire fifo_edge_list_ptr_Sextans_15__full_n; - wire fifo_edge_list_ptr_Sextans_15__write; - wire [32:0] fifo_edge_list_ptr_Sextans_16__dout; - wire fifo_edge_list_ptr_Sextans_16__empty_n; - wire fifo_edge_list_ptr_Sextans_16__read; - wire [32:0] fifo_edge_list_ptr_Sextans_16__din; - wire fifo_edge_list_ptr_Sextans_16__full_n; - wire fifo_edge_list_ptr_Sextans_16__write; - wire [32:0] fifo_edge_list_ptr_Sextans_1__dout; - wire fifo_edge_list_ptr_Sextans_1__empty_n; - wire fifo_edge_list_ptr_Sextans_1__read; - wire [32:0] fifo_edge_list_ptr_Sextans_1__din; - wire fifo_edge_list_ptr_Sextans_1__full_n; - wire fifo_edge_list_ptr_Sextans_1__write; - wire [32:0] fifo_edge_list_ptr_Sextans_2__dout; - wire fifo_edge_list_ptr_Sextans_2__empty_n; - wire fifo_edge_list_ptr_Sextans_2__read; - wire [32:0] fifo_edge_list_ptr_Sextans_2__din; - wire fifo_edge_list_ptr_Sextans_2__full_n; - wire fifo_edge_list_ptr_Sextans_2__write; - wire [32:0] fifo_edge_list_ptr_Sextans_3__dout; - wire fifo_edge_list_ptr_Sextans_3__empty_n; - wire fifo_edge_list_ptr_Sextans_3__read; - wire [32:0] fifo_edge_list_ptr_Sextans_3__din; - wire fifo_edge_list_ptr_Sextans_3__full_n; - wire fifo_edge_list_ptr_Sextans_3__write; - wire [32:0] fifo_edge_list_ptr_Sextans_4__dout; - wire fifo_edge_list_ptr_Sextans_4__empty_n; - wire fifo_edge_list_ptr_Sextans_4__read; - wire [32:0] fifo_edge_list_ptr_Sextans_4__din; - wire fifo_edge_list_ptr_Sextans_4__full_n; - wire fifo_edge_list_ptr_Sextans_4__write; - wire [32:0] fifo_edge_list_ptr_Sextans_5__dout; - wire fifo_edge_list_ptr_Sextans_5__empty_n; - wire fifo_edge_list_ptr_Sextans_5__read; - wire [32:0] fifo_edge_list_ptr_Sextans_5__din; - wire fifo_edge_list_ptr_Sextans_5__full_n; - wire fifo_edge_list_ptr_Sextans_5__write; - wire [32:0] fifo_edge_list_ptr_Sextans_6__dout; - wire fifo_edge_list_ptr_Sextans_6__empty_n; - wire fifo_edge_list_ptr_Sextans_6__read; - wire [32:0] fifo_edge_list_ptr_Sextans_6__din; - wire fifo_edge_list_ptr_Sextans_6__full_n; - wire fifo_edge_list_ptr_Sextans_6__write; - wire [32:0] fifo_edge_list_ptr_Sextans_7__dout; - wire fifo_edge_list_ptr_Sextans_7__empty_n; - wire fifo_edge_list_ptr_Sextans_7__read; - wire [32:0] fifo_edge_list_ptr_Sextans_7__din; - wire fifo_edge_list_ptr_Sextans_7__full_n; - wire fifo_edge_list_ptr_Sextans_7__write; - wire [32:0] fifo_edge_list_ptr_Sextans_8__dout; - wire fifo_edge_list_ptr_Sextans_8__empty_n; - wire fifo_edge_list_ptr_Sextans_8__read; - wire [32:0] fifo_edge_list_ptr_Sextans_8__din; - wire fifo_edge_list_ptr_Sextans_8__full_n; - wire fifo_edge_list_ptr_Sextans_8__write; - wire [32:0] fifo_edge_list_ptr_Sextans_9__dout; - wire fifo_edge_list_ptr_Sextans_9__empty_n; - wire fifo_edge_list_ptr_Sextans_9__read; - wire [32:0] fifo_edge_list_ptr_Sextans_9__din; - wire fifo_edge_list_ptr_Sextans_9__full_n; - wire fifo_edge_list_ptr_Sextans_9__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_0__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_0__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_0__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_0__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_0__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_0__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_10__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_10__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_10__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_10__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_10__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_10__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_11__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_11__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_11__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_11__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_11__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_11__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_12__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_12__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_12__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_12__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_12__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_12__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_13__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_13__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_13__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_13__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_13__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_13__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_14__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_14__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_14__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_14__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_14__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_14__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_15__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_15__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_15__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_15__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_15__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_15__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_1__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_1__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_1__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_1__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_1__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_1__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_2__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_2__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_2__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_2__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_2__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_2__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_3__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_3__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_3__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_3__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_3__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_3__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_4__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_4__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_4__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_4__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_4__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_4__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_5__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_5__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_5__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_5__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_5__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_5__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_6__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_6__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_6__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_6__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_6__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_6__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_7__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_7__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_7__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_7__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_7__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_7__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_8__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_8__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_8__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_8__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_8__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_8__write; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_9__dout; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_9__empty_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_9__read; - wire [32:0] fifo_edge_list_ptr_to_Cmtx_Sextans_9__din; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_9__full_n; - wire fifo_edge_list_ptr_to_Cmtx_Sextans_9__write; - wire [32:0] wrC_inst_Sextans_0__dout; - wire wrC_inst_Sextans_0__empty_n; - wire wrC_inst_Sextans_0__read; - wire [32:0] wrC_inst_Sextans_0__din; - wire wrC_inst_Sextans_0__full_n; - wire wrC_inst_Sextans_0__write; - wire [32:0] wrC_inst_Sextans_1__dout; - wire wrC_inst_Sextans_1__empty_n; - wire wrC_inst_Sextans_1__read; - wire [32:0] wrC_inst_Sextans_1__din; - wire wrC_inst_Sextans_1__full_n; - wire wrC_inst_Sextans_1__write; - wire [32:0] wrC_inst_Sextans_2__dout; - wire wrC_inst_Sextans_2__empty_n; - wire wrC_inst_Sextans_2__read; - wire [32:0] wrC_inst_Sextans_2__din; - wire wrC_inst_Sextans_2__full_n; - wire wrC_inst_Sextans_2__write; - wire [32:0] wrC_inst_Sextans_3__dout; - wire wrC_inst_Sextans_3__empty_n; - wire wrC_inst_Sextans_3__read; - wire [32:0] wrC_inst_Sextans_3__din; - wire wrC_inst_Sextans_3__full_n; - wire wrC_inst_Sextans_3__write; - wire [32:0] wrC_inst_Sextans_4__dout; - wire wrC_inst_Sextans_4__empty_n; - wire wrC_inst_Sextans_4__read; - wire [32:0] wrC_inst_Sextans_4__din; - wire wrC_inst_Sextans_4__full_n; - wire wrC_inst_Sextans_4__write; - wire [32:0] wrC_inst_Sextans_5__dout; - wire wrC_inst_Sextans_5__empty_n; - wire wrC_inst_Sextans_5__read; - wire [32:0] wrC_inst_Sextans_5__din; - wire wrC_inst_Sextans_5__full_n; - wire wrC_inst_Sextans_5__write; - wire [32:0] wrC_inst_Sextans_6__dout; - wire wrC_inst_Sextans_6__empty_n; - wire wrC_inst_Sextans_6__read; - wire [32:0] wrC_inst_Sextans_6__din; - wire wrC_inst_Sextans_6__full_n; - wire wrC_inst_Sextans_6__write; - wire [32:0] wrC_inst_Sextans_7__dout; - wire wrC_inst_Sextans_7__empty_n; - wire wrC_inst_Sextans_7__read; - wire [32:0] wrC_inst_Sextans_7__din; - wire wrC_inst_Sextans_7__full_n; - wire wrC_inst_Sextans_7__write; - wire FloatvAddFloatv_0__ap_start; - wire FloatvAddFloatv_1__ap_start; - wire FloatvAddFloatv_2__ap_start; - wire FloatvAddFloatv_3__ap_start; - wire FloatvAddFloatv_4__ap_start; - wire FloatvAddFloatv_5__ap_start; - wire FloatvAddFloatv_6__ap_start; - wire FloatvAddFloatv_7__ap_start; - wire [31:0] FloatvMultConst_0___M__q0; - wire [31:0] FloatvMultConst_0___P_N__q0; - wire [31:0] FloatvMultConst_0___beta_u__q0; - wire FloatvMultConst_0__ap_start; - wire FloatvMultConst_0__ap_ready; - wire FloatvMultConst_0__ap_done; - wire FloatvMultConst_0__ap_idle; - wire [31:0] FloatvMultConst_1___M__q0; - wire [31:0] FloatvMultConst_1___P_N__q0; - wire [31:0] FloatvMultConst_1___beta_u__q0; - wire FloatvMultConst_1__ap_start; - wire FloatvMultConst_1__ap_ready; - wire FloatvMultConst_1__ap_done; - wire FloatvMultConst_1__ap_idle; - wire [31:0] FloatvMultConst_2___M__q0; - wire [31:0] FloatvMultConst_2___P_N__q0; - wire [31:0] FloatvMultConst_2___beta_u__q0; - wire FloatvMultConst_2__ap_start; - wire FloatvMultConst_2__ap_ready; - wire FloatvMultConst_2__ap_done; - wire FloatvMultConst_2__ap_idle; - wire [31:0] FloatvMultConst_3___M__q0; - wire [31:0] FloatvMultConst_3___P_N__q0; - wire [31:0] FloatvMultConst_3___beta_u__q0; - wire FloatvMultConst_3__ap_start; - wire FloatvMultConst_3__ap_ready; - wire FloatvMultConst_3__ap_done; - wire FloatvMultConst_3__ap_idle; - wire [31:0] FloatvMultConst_4___M__q0; - wire [31:0] FloatvMultConst_4___P_N__q0; - wire [31:0] FloatvMultConst_4___beta_u__q0; - wire FloatvMultConst_4__ap_start; - wire FloatvMultConst_4__ap_ready; - wire FloatvMultConst_4__ap_done; - wire FloatvMultConst_4__ap_idle; - wire [31:0] FloatvMultConst_5___M__q0; - wire [31:0] FloatvMultConst_5___P_N__q0; - wire [31:0] FloatvMultConst_5___beta_u__q0; - wire FloatvMultConst_5__ap_start; - wire FloatvMultConst_5__ap_ready; - wire FloatvMultConst_5__ap_done; - wire FloatvMultConst_5__ap_idle; - wire [31:0] FloatvMultConst_6___M__q0; - wire [31:0] FloatvMultConst_6___P_N__q0; - wire [31:0] FloatvMultConst_6___beta_u__q0; - wire FloatvMultConst_6__ap_start; - wire FloatvMultConst_6__ap_ready; - wire FloatvMultConst_6__ap_done; - wire FloatvMultConst_6__ap_idle; - wire [31:0] FloatvMultConst_7___M__q0; - wire [31:0] FloatvMultConst_7___P_N__q0; - wire [31:0] FloatvMultConst_7___beta_u__q0; - wire FloatvMultConst_7__ap_start; - wire FloatvMultConst_7__ap_ready; - wire FloatvMultConst_7__ap_done; - wire FloatvMultConst_7__ap_idle; - wire [31:0] FloatvMultConst_8___M__q0; - wire [31:0] FloatvMultConst_8___P_N__q0; - wire [31:0] FloatvMultConst_8___alpha_u__q0; - wire FloatvMultConst_8__ap_start; - wire FloatvMultConst_8__ap_ready; - wire FloatvMultConst_8__ap_done; - wire FloatvMultConst_8__ap_idle; - wire [31:0] FloatvMultConst_9___M__q0; - wire [31:0] FloatvMultConst_9___P_N__q0; - wire [31:0] FloatvMultConst_9___alpha_u__q0; - wire FloatvMultConst_9__ap_start; - wire FloatvMultConst_9__ap_ready; - wire FloatvMultConst_9__ap_done; - wire FloatvMultConst_9__ap_idle; - wire [31:0] FloatvMultConst_10___M__q0; - wire [31:0] FloatvMultConst_10___P_N__q0; - wire [31:0] FloatvMultConst_10___alpha_u__q0; - wire FloatvMultConst_10__ap_start; - wire FloatvMultConst_10__ap_ready; - wire FloatvMultConst_10__ap_done; - wire FloatvMultConst_10__ap_idle; - wire [31:0] FloatvMultConst_11___M__q0; - wire [31:0] FloatvMultConst_11___P_N__q0; - wire [31:0] FloatvMultConst_11___alpha_u__q0; - wire FloatvMultConst_11__ap_start; - wire FloatvMultConst_11__ap_ready; - wire FloatvMultConst_11__ap_done; - wire FloatvMultConst_11__ap_idle; - wire [31:0] FloatvMultConst_12___M__q0; - wire [31:0] FloatvMultConst_12___P_N__q0; - wire [31:0] FloatvMultConst_12___alpha_u__q0; - wire FloatvMultConst_12__ap_start; - wire FloatvMultConst_12__ap_ready; - wire FloatvMultConst_12__ap_done; - wire FloatvMultConst_12__ap_idle; - wire [31:0] FloatvMultConst_13___M__q0; - wire [31:0] FloatvMultConst_13___P_N__q0; - wire [31:0] FloatvMultConst_13___alpha_u__q0; - wire FloatvMultConst_13__ap_start; - wire FloatvMultConst_13__ap_ready; - wire FloatvMultConst_13__ap_done; - wire FloatvMultConst_13__ap_idle; - wire [31:0] FloatvMultConst_14___M__q0; - wire [31:0] FloatvMultConst_14___P_N__q0; - wire [31:0] FloatvMultConst_14___alpha_u__q0; - wire FloatvMultConst_14__ap_start; - wire FloatvMultConst_14__ap_ready; - wire FloatvMultConst_14__ap_done; - wire FloatvMultConst_14__ap_idle; - wire [31:0] FloatvMultConst_15___M__q0; - wire [31:0] FloatvMultConst_15___P_N__q0; - wire [31:0] FloatvMultConst_15___alpha_u__q0; - wire FloatvMultConst_15__ap_start; - wire FloatvMultConst_15__ap_ready; - wire FloatvMultConst_15__ap_done; - wire FloatvMultConst_15__ap_idle; - wire Merger_0__ap_start; - wire Merger_1__ap_start; - wire Merger_2__ap_start; - wire Merger_3__ap_start; - wire Merger_4__ap_start; - wire Merger_5__ap_start; - wire Merger_6__ap_start; - wire Merger_7__ap_start; - wire PEG_Bmtx_0__ap_start; - wire PEG_Bmtx_0__ap_ready; - wire PEG_Bmtx_0__ap_done; - wire PEG_Bmtx_0__ap_idle; - wire PEG_Bmtx_1__ap_start; - wire PEG_Bmtx_1__ap_ready; - wire PEG_Bmtx_1__ap_done; - wire PEG_Bmtx_1__ap_idle; - wire PEG_Bmtx_2__ap_start; - wire PEG_Bmtx_2__ap_ready; - wire PEG_Bmtx_2__ap_done; - wire PEG_Bmtx_2__ap_idle; - wire PEG_Bmtx_3__ap_start; - wire PEG_Bmtx_3__ap_ready; - wire PEG_Bmtx_3__ap_done; - wire PEG_Bmtx_3__ap_idle; - wire PEG_Bmtx_4__ap_start; - wire PEG_Bmtx_4__ap_ready; - wire PEG_Bmtx_4__ap_done; - wire PEG_Bmtx_4__ap_idle; - wire PEG_Bmtx_5__ap_start; - wire PEG_Bmtx_5__ap_ready; - wire PEG_Bmtx_5__ap_done; - wire PEG_Bmtx_5__ap_idle; - wire PEG_Bmtx_6__ap_start; - wire PEG_Bmtx_6__ap_ready; - wire PEG_Bmtx_6__ap_done; - wire PEG_Bmtx_6__ap_idle; - wire PEG_Bmtx_7__ap_start; - wire PEG_Bmtx_7__ap_ready; - wire PEG_Bmtx_7__ap_done; - wire PEG_Bmtx_7__ap_idle; - wire PEG_Bmtx_8__ap_start; - wire PEG_Bmtx_8__ap_ready; - wire PEG_Bmtx_8__ap_done; - wire PEG_Bmtx_8__ap_idle; - wire PEG_Bmtx_9__ap_start; - wire PEG_Bmtx_9__ap_ready; - wire PEG_Bmtx_9__ap_done; - wire PEG_Bmtx_9__ap_idle; - wire PEG_Bmtx_10__ap_start; - wire PEG_Bmtx_10__ap_ready; - wire PEG_Bmtx_10__ap_done; - wire PEG_Bmtx_10__ap_idle; - wire PEG_Bmtx_11__ap_start; - wire PEG_Bmtx_11__ap_ready; - wire PEG_Bmtx_11__ap_done; - wire PEG_Bmtx_11__ap_idle; - wire PEG_Bmtx_12__ap_start; - wire PEG_Bmtx_12__ap_ready; - wire PEG_Bmtx_12__ap_done; - wire PEG_Bmtx_12__ap_idle; - wire PEG_Bmtx_13__ap_start; - wire PEG_Bmtx_13__ap_ready; - wire PEG_Bmtx_13__ap_done; - wire PEG_Bmtx_13__ap_idle; - wire PEG_Bmtx_14__ap_start; - wire PEG_Bmtx_14__ap_ready; - wire PEG_Bmtx_14__ap_done; - wire PEG_Bmtx_14__ap_idle; - wire PEG_Bmtx_15__ap_start; - wire PEG_Bmtx_15__ap_ready; - wire PEG_Bmtx_15__ap_done; - wire PEG_Bmtx_15__ap_idle; - wire PEG_Cmtx_0__ap_start; - wire PEG_Cmtx_0__ap_ready; - wire PEG_Cmtx_0__ap_done; - wire PEG_Cmtx_0__ap_idle; - wire PEG_Cmtx_1__ap_start; - wire PEG_Cmtx_1__ap_ready; - wire PEG_Cmtx_1__ap_done; - wire PEG_Cmtx_1__ap_idle; - wire PEG_Cmtx_2__ap_start; - wire PEG_Cmtx_2__ap_ready; - wire PEG_Cmtx_2__ap_done; - wire PEG_Cmtx_2__ap_idle; - wire PEG_Cmtx_3__ap_start; - wire PEG_Cmtx_3__ap_ready; - wire PEG_Cmtx_3__ap_done; - wire PEG_Cmtx_3__ap_idle; - wire PEG_Cmtx_4__ap_start; - wire PEG_Cmtx_4__ap_ready; - wire PEG_Cmtx_4__ap_done; - wire PEG_Cmtx_4__ap_idle; - wire PEG_Cmtx_5__ap_start; - wire PEG_Cmtx_5__ap_ready; - wire PEG_Cmtx_5__ap_done; - wire PEG_Cmtx_5__ap_idle; - wire PEG_Cmtx_6__ap_start; - wire PEG_Cmtx_6__ap_ready; - wire PEG_Cmtx_6__ap_done; - wire PEG_Cmtx_6__ap_idle; - wire PEG_Cmtx_7__ap_start; - wire PEG_Cmtx_7__ap_ready; - wire PEG_Cmtx_7__ap_done; - wire PEG_Cmtx_7__ap_idle; - wire PEG_Cmtx_8__ap_start; - wire PEG_Cmtx_8__ap_ready; - wire PEG_Cmtx_8__ap_done; - wire PEG_Cmtx_8__ap_idle; - wire PEG_Cmtx_9__ap_start; - wire PEG_Cmtx_9__ap_ready; - wire PEG_Cmtx_9__ap_done; - wire PEG_Cmtx_9__ap_idle; - wire PEG_Cmtx_10__ap_start; - wire PEG_Cmtx_10__ap_ready; - wire PEG_Cmtx_10__ap_done; - wire PEG_Cmtx_10__ap_idle; - wire PEG_Cmtx_11__ap_start; - wire PEG_Cmtx_11__ap_ready; - wire PEG_Cmtx_11__ap_done; - wire PEG_Cmtx_11__ap_idle; - wire PEG_Cmtx_12__ap_start; - wire PEG_Cmtx_12__ap_ready; - wire PEG_Cmtx_12__ap_done; - wire PEG_Cmtx_12__ap_idle; - wire PEG_Cmtx_13__ap_start; - wire PEG_Cmtx_13__ap_ready; - wire PEG_Cmtx_13__ap_done; - wire PEG_Cmtx_13__ap_idle; - wire PEG_Cmtx_14__ap_start; - wire PEG_Cmtx_14__ap_ready; - wire PEG_Cmtx_14__ap_done; - wire PEG_Cmtx_14__ap_idle; - wire PEG_Cmtx_15__ap_start; - wire PEG_Cmtx_15__ap_ready; - wire PEG_Cmtx_15__ap_done; - wire PEG_Cmtx_15__ap_idle; - wire Scatter_1_2_0__ap_start; - wire Scatter_1_2_1__ap_start; - wire Scatter_1_2_2__ap_start; - wire Scatter_1_2_3__ap_start; - wire Scatter_1_2_4__ap_start; - wire Scatter_1_2_5__ap_start; - wire Scatter_1_2_6__ap_start; - wire Scatter_1_2_7__ap_start; - wire black_hole_float_v16_0__ap_start; - wire black_hole_float_v16_1__ap_start; - wire black_hole_float_v16_2__ap_start; - wire black_hole_float_v16_3__ap_start; - wire black_hole_int_0__ap_start; - wire black_hole_int_1__ap_start; - wire [31:0] read_A_0___NUM_A_LEN__q0; - wire [31:0] read_A_0___P_N__q0; - wire [63:0] read_A_0___edge_list_ch_0__q0; - wire [63:0] edge_list_ch_0_read_addr__din; - wire edge_list_ch_0_read_addr__full_n; - wire edge_list_ch_0_read_addr__write; - wire [511:0] edge_list_ch_0_read_data__dout; - wire edge_list_ch_0_read_data__empty_n; - wire edge_list_ch_0_read_data__read; - wire [63:0] edge_list_ch_0_write_addr__din; - wire edge_list_ch_0_write_addr__full_n; - wire edge_list_ch_0_write_addr__write; - wire [511:0] edge_list_ch_0_write_data__din; - wire edge_list_ch_0_write_data__full_n; - wire edge_list_ch_0_write_data__write; - wire [7:0] edge_list_ch_0_write_resp__dout; - wire edge_list_ch_0_write_resp__empty_n; - wire edge_list_ch_0_write_resp__read; - wire read_A_0__ap_start; - wire read_A_0__ap_ready; - wire read_A_0__ap_done; - wire read_A_0__ap_idle; - wire [31:0] read_A_1___NUM_A_LEN__q0; - wire [31:0] read_A_1___P_N__q0; - wire [63:0] read_A_1___edge_list_ch_1__q0; - wire [63:0] edge_list_ch_1_read_addr__din; - wire edge_list_ch_1_read_addr__full_n; - wire edge_list_ch_1_read_addr__write; - wire [511:0] edge_list_ch_1_read_data__dout; - wire edge_list_ch_1_read_data__empty_n; - wire edge_list_ch_1_read_data__read; - wire [63:0] edge_list_ch_1_write_addr__din; - wire edge_list_ch_1_write_addr__full_n; - wire edge_list_ch_1_write_addr__write; - wire [511:0] edge_list_ch_1_write_data__din; - wire edge_list_ch_1_write_data__full_n; - wire edge_list_ch_1_write_data__write; - wire [7:0] edge_list_ch_1_write_resp__dout; - wire edge_list_ch_1_write_resp__empty_n; - wire edge_list_ch_1_write_resp__read; - wire read_A_1__ap_start; - wire read_A_1__ap_ready; - wire read_A_1__ap_done; - wire read_A_1__ap_idle; - wire [31:0] read_A_2___NUM_A_LEN__q0; - wire [31:0] read_A_2___P_N__q0; - wire [63:0] read_A_2___edge_list_ch_2__q0; - wire [63:0] edge_list_ch_2_read_addr__din; - wire edge_list_ch_2_read_addr__full_n; - wire edge_list_ch_2_read_addr__write; - wire [511:0] edge_list_ch_2_read_data__dout; - wire edge_list_ch_2_read_data__empty_n; - wire edge_list_ch_2_read_data__read; - wire [63:0] edge_list_ch_2_write_addr__din; - wire edge_list_ch_2_write_addr__full_n; - wire edge_list_ch_2_write_addr__write; - wire [511:0] edge_list_ch_2_write_data__din; - wire edge_list_ch_2_write_data__full_n; - wire edge_list_ch_2_write_data__write; - wire [7:0] edge_list_ch_2_write_resp__dout; - wire edge_list_ch_2_write_resp__empty_n; - wire edge_list_ch_2_write_resp__read; - wire read_A_2__ap_start; - wire read_A_2__ap_ready; - wire read_A_2__ap_done; - wire read_A_2__ap_idle; - wire [31:0] read_A_3___NUM_A_LEN__q0; - wire [31:0] read_A_3___P_N__q0; - wire [63:0] read_A_3___edge_list_ch_3__q0; - wire [63:0] edge_list_ch_3_read_addr__din; - wire edge_list_ch_3_read_addr__full_n; - wire edge_list_ch_3_read_addr__write; - wire [511:0] edge_list_ch_3_read_data__dout; - wire edge_list_ch_3_read_data__empty_n; - wire edge_list_ch_3_read_data__read; - wire [63:0] edge_list_ch_3_write_addr__din; - wire edge_list_ch_3_write_addr__full_n; - wire edge_list_ch_3_write_addr__write; - wire [511:0] edge_list_ch_3_write_data__din; - wire edge_list_ch_3_write_data__full_n; - wire edge_list_ch_3_write_data__write; - wire [7:0] edge_list_ch_3_write_resp__dout; - wire edge_list_ch_3_write_resp__empty_n; - wire edge_list_ch_3_write_resp__read; - wire read_A_3__ap_start; - wire read_A_3__ap_ready; - wire read_A_3__ap_done; - wire read_A_3__ap_idle; - wire [31:0] read_A_4___NUM_A_LEN__q0; - wire [31:0] read_A_4___P_N__q0; - wire [63:0] read_A_4___edge_list_ch_4__q0; - wire [63:0] edge_list_ch_4_read_addr__din; - wire edge_list_ch_4_read_addr__full_n; - wire edge_list_ch_4_read_addr__write; - wire [511:0] edge_list_ch_4_read_data__dout; - wire edge_list_ch_4_read_data__empty_n; - wire edge_list_ch_4_read_data__read; - wire [63:0] edge_list_ch_4_write_addr__din; - wire edge_list_ch_4_write_addr__full_n; - wire edge_list_ch_4_write_addr__write; - wire [511:0] edge_list_ch_4_write_data__din; - wire edge_list_ch_4_write_data__full_n; - wire edge_list_ch_4_write_data__write; - wire [7:0] edge_list_ch_4_write_resp__dout; - wire edge_list_ch_4_write_resp__empty_n; - wire edge_list_ch_4_write_resp__read; - wire read_A_4__ap_start; - wire read_A_4__ap_ready; - wire read_A_4__ap_done; - wire read_A_4__ap_idle; - wire [31:0] read_A_5___NUM_A_LEN__q0; - wire [31:0] read_A_5___P_N__q0; - wire [63:0] read_A_5___edge_list_ch_5__q0; - wire [63:0] edge_list_ch_5_read_addr__din; - wire edge_list_ch_5_read_addr__full_n; - wire edge_list_ch_5_read_addr__write; - wire [511:0] edge_list_ch_5_read_data__dout; - wire edge_list_ch_5_read_data__empty_n; - wire edge_list_ch_5_read_data__read; - wire [63:0] edge_list_ch_5_write_addr__din; - wire edge_list_ch_5_write_addr__full_n; - wire edge_list_ch_5_write_addr__write; - wire [511:0] edge_list_ch_5_write_data__din; - wire edge_list_ch_5_write_data__full_n; - wire edge_list_ch_5_write_data__write; - wire [7:0] edge_list_ch_5_write_resp__dout; - wire edge_list_ch_5_write_resp__empty_n; - wire edge_list_ch_5_write_resp__read; - wire read_A_5__ap_start; - wire read_A_5__ap_ready; - wire read_A_5__ap_done; - wire read_A_5__ap_idle; - wire [31:0] read_A_6___NUM_A_LEN__q0; - wire [31:0] read_A_6___P_N__q0; - wire [63:0] read_A_6___edge_list_ch_6__q0; - wire [63:0] edge_list_ch_6_read_addr__din; - wire edge_list_ch_6_read_addr__full_n; - wire edge_list_ch_6_read_addr__write; - wire [511:0] edge_list_ch_6_read_data__dout; - wire edge_list_ch_6_read_data__empty_n; - wire edge_list_ch_6_read_data__read; - wire [63:0] edge_list_ch_6_write_addr__din; - wire edge_list_ch_6_write_addr__full_n; - wire edge_list_ch_6_write_addr__write; - wire [511:0] edge_list_ch_6_write_data__din; - wire edge_list_ch_6_write_data__full_n; - wire edge_list_ch_6_write_data__write; - wire [7:0] edge_list_ch_6_write_resp__dout; - wire edge_list_ch_6_write_resp__empty_n; - wire edge_list_ch_6_write_resp__read; - wire read_A_6__ap_start; - wire read_A_6__ap_ready; - wire read_A_6__ap_done; - wire read_A_6__ap_idle; - wire [31:0] read_A_7___NUM_A_LEN__q0; - wire [31:0] read_A_7___P_N__q0; - wire [63:0] read_A_7___edge_list_ch_7__q0; - wire [63:0] edge_list_ch_7_read_addr__din; - wire edge_list_ch_7_read_addr__full_n; - wire edge_list_ch_7_read_addr__write; - wire [511:0] edge_list_ch_7_read_data__dout; - wire edge_list_ch_7_read_data__empty_n; - wire edge_list_ch_7_read_data__read; - wire [63:0] edge_list_ch_7_write_addr__din; - wire edge_list_ch_7_write_addr__full_n; - wire edge_list_ch_7_write_addr__write; - wire [511:0] edge_list_ch_7_write_data__din; - wire edge_list_ch_7_write_data__full_n; - wire edge_list_ch_7_write_data__write; - wire [7:0] edge_list_ch_7_write_resp__dout; - wire edge_list_ch_7_write_resp__empty_n; - wire edge_list_ch_7_write_resp__read; - wire read_A_7__ap_start; - wire read_A_7__ap_ready; - wire read_A_7__ap_done; - wire read_A_7__ap_idle; - wire [31:0] read_B_0___K__q0; - wire [31:0] read_B_0___P_N__q0; - wire [63:0] read_B_0___mat_B_ch_0__q0; - wire [63:0] mat_B_ch_0_read_addr__din; - wire mat_B_ch_0_read_addr__full_n; - wire mat_B_ch_0_read_addr__write; - wire [511:0] mat_B_ch_0_read_data__dout; - wire mat_B_ch_0_read_data__empty_n; - wire mat_B_ch_0_read_data__read; - wire [63:0] mat_B_ch_0_write_addr__din; - wire mat_B_ch_0_write_addr__full_n; - wire mat_B_ch_0_write_addr__write; - wire [511:0] mat_B_ch_0_write_data__din; - wire mat_B_ch_0_write_data__full_n; - wire mat_B_ch_0_write_data__write; - wire [7:0] mat_B_ch_0_write_resp__dout; - wire mat_B_ch_0_write_resp__empty_n; - wire mat_B_ch_0_write_resp__read; - wire read_B_0__ap_start; - wire read_B_0__ap_ready; - wire read_B_0__ap_done; - wire read_B_0__ap_idle; - wire [31:0] read_B_1___K__q0; - wire [31:0] read_B_1___P_N__q0; - wire [63:0] read_B_1___mat_B_ch_1__q0; - wire [63:0] mat_B_ch_1_read_addr__din; - wire mat_B_ch_1_read_addr__full_n; - wire mat_B_ch_1_read_addr__write; - wire [511:0] mat_B_ch_1_read_data__dout; - wire mat_B_ch_1_read_data__empty_n; - wire mat_B_ch_1_read_data__read; - wire [63:0] mat_B_ch_1_write_addr__din; - wire mat_B_ch_1_write_addr__full_n; - wire mat_B_ch_1_write_addr__write; - wire [511:0] mat_B_ch_1_write_data__din; - wire mat_B_ch_1_write_data__full_n; - wire mat_B_ch_1_write_data__write; - wire [7:0] mat_B_ch_1_write_resp__dout; - wire mat_B_ch_1_write_resp__empty_n; - wire mat_B_ch_1_write_resp__read; - wire read_B_1__ap_start; - wire read_B_1__ap_ready; - wire read_B_1__ap_done; - wire read_B_1__ap_idle; - wire [31:0] read_B_2___K__q0; - wire [31:0] read_B_2___P_N__q0; - wire [63:0] read_B_2___mat_B_ch_2__q0; - wire [63:0] mat_B_ch_2_read_addr__din; - wire mat_B_ch_2_read_addr__full_n; - wire mat_B_ch_2_read_addr__write; - wire [511:0] mat_B_ch_2_read_data__dout; - wire mat_B_ch_2_read_data__empty_n; - wire mat_B_ch_2_read_data__read; - wire [63:0] mat_B_ch_2_write_addr__din; - wire mat_B_ch_2_write_addr__full_n; - wire mat_B_ch_2_write_addr__write; - wire [511:0] mat_B_ch_2_write_data__din; - wire mat_B_ch_2_write_data__full_n; - wire mat_B_ch_2_write_data__write; - wire [7:0] mat_B_ch_2_write_resp__dout; - wire mat_B_ch_2_write_resp__empty_n; - wire mat_B_ch_2_write_resp__read; - wire read_B_2__ap_start; - wire read_B_2__ap_ready; - wire read_B_2__ap_done; - wire read_B_2__ap_idle; - wire [31:0] read_B_3___K__q0; - wire [31:0] read_B_3___P_N__q0; - wire [63:0] read_B_3___mat_B_ch_3__q0; - wire [63:0] mat_B_ch_3_read_addr__din; - wire mat_B_ch_3_read_addr__full_n; - wire mat_B_ch_3_read_addr__write; - wire [511:0] mat_B_ch_3_read_data__dout; - wire mat_B_ch_3_read_data__empty_n; - wire mat_B_ch_3_read_data__read; - wire [63:0] mat_B_ch_3_write_addr__din; - wire mat_B_ch_3_write_addr__full_n; - wire mat_B_ch_3_write_addr__write; - wire [511:0] mat_B_ch_3_write_data__din; - wire mat_B_ch_3_write_data__full_n; - wire mat_B_ch_3_write_data__write; - wire [7:0] mat_B_ch_3_write_resp__dout; - wire mat_B_ch_3_write_resp__empty_n; - wire mat_B_ch_3_write_resp__read; - wire read_B_3__ap_start; - wire read_B_3__ap_ready; - wire read_B_3__ap_done; - wire read_B_3__ap_idle; - wire [31:0] read_C_0___M__q0; - wire [31:0] read_C_0___P_N__q0; - wire [63:0] read_C_0___mat_C_ch_in_0__q0; - wire [63:0] mat_C_ch_in_0_read_addr__din; - wire mat_C_ch_in_0_read_addr__full_n; - wire mat_C_ch_in_0_read_addr__write; - wire [511:0] mat_C_ch_in_0_read_data__dout; - wire mat_C_ch_in_0_read_data__empty_n; - wire mat_C_ch_in_0_read_data__read; - wire [63:0] mat_C_ch_in_0_write_addr__din; - wire mat_C_ch_in_0_write_addr__full_n; - wire mat_C_ch_in_0_write_addr__write; - wire [511:0] mat_C_ch_in_0_write_data__din; - wire mat_C_ch_in_0_write_data__full_n; - wire mat_C_ch_in_0_write_data__write; - wire [7:0] mat_C_ch_in_0_write_resp__dout; - wire mat_C_ch_in_0_write_resp__empty_n; - wire mat_C_ch_in_0_write_resp__read; - wire read_C_0__ap_start; - wire read_C_0__ap_ready; - wire read_C_0__ap_done; - wire read_C_0__ap_idle; - wire [31:0] read_C_1___M__q0; - wire [31:0] read_C_1___P_N__q0; - wire [63:0] read_C_1___mat_C_ch_in_1__q0; - wire [63:0] mat_C_ch_in_1_read_addr__din; - wire mat_C_ch_in_1_read_addr__full_n; - wire mat_C_ch_in_1_read_addr__write; - wire [511:0] mat_C_ch_in_1_read_data__dout; - wire mat_C_ch_in_1_read_data__empty_n; - wire mat_C_ch_in_1_read_data__read; - wire [63:0] mat_C_ch_in_1_write_addr__din; - wire mat_C_ch_in_1_write_addr__full_n; - wire mat_C_ch_in_1_write_addr__write; - wire [511:0] mat_C_ch_in_1_write_data__din; - wire mat_C_ch_in_1_write_data__full_n; - wire mat_C_ch_in_1_write_data__write; - wire [7:0] mat_C_ch_in_1_write_resp__dout; - wire mat_C_ch_in_1_write_resp__empty_n; - wire mat_C_ch_in_1_write_resp__read; - wire read_C_1__ap_start; - wire read_C_1__ap_ready; - wire read_C_1__ap_done; - wire read_C_1__ap_idle; - wire [31:0] read_C_2___M__q0; - wire [31:0] read_C_2___P_N__q0; - wire [63:0] read_C_2___mat_C_ch_in_2__q0; - wire [63:0] mat_C_ch_in_2_read_addr__din; - wire mat_C_ch_in_2_read_addr__full_n; - wire mat_C_ch_in_2_read_addr__write; - wire [511:0] mat_C_ch_in_2_read_data__dout; - wire mat_C_ch_in_2_read_data__empty_n; - wire mat_C_ch_in_2_read_data__read; - wire [63:0] mat_C_ch_in_2_write_addr__din; - wire mat_C_ch_in_2_write_addr__full_n; - wire mat_C_ch_in_2_write_addr__write; - wire [511:0] mat_C_ch_in_2_write_data__din; - wire mat_C_ch_in_2_write_data__full_n; - wire mat_C_ch_in_2_write_data__write; - wire [7:0] mat_C_ch_in_2_write_resp__dout; - wire mat_C_ch_in_2_write_resp__empty_n; - wire mat_C_ch_in_2_write_resp__read; - wire read_C_2__ap_start; - wire read_C_2__ap_ready; - wire read_C_2__ap_done; - wire read_C_2__ap_idle; - wire [31:0] read_C_3___M__q0; - wire [31:0] read_C_3___P_N__q0; - wire [63:0] read_C_3___mat_C_ch_in_3__q0; - wire [63:0] mat_C_ch_in_3_read_addr__din; - wire mat_C_ch_in_3_read_addr__full_n; - wire mat_C_ch_in_3_read_addr__write; - wire [511:0] mat_C_ch_in_3_read_data__dout; - wire mat_C_ch_in_3_read_data__empty_n; - wire mat_C_ch_in_3_read_data__read; - wire [63:0] mat_C_ch_in_3_write_addr__din; - wire mat_C_ch_in_3_write_addr__full_n; - wire mat_C_ch_in_3_write_addr__write; - wire [511:0] mat_C_ch_in_3_write_data__din; - wire mat_C_ch_in_3_write_data__full_n; - wire mat_C_ch_in_3_write_data__write; - wire [7:0] mat_C_ch_in_3_write_resp__dout; - wire mat_C_ch_in_3_write_resp__empty_n; - wire mat_C_ch_in_3_write_resp__read; - wire read_C_3__ap_start; - wire read_C_3__ap_ready; - wire read_C_3__ap_done; - wire read_C_3__ap_idle; - wire [31:0] read_C_4___M__q0; - wire [31:0] read_C_4___P_N__q0; - wire [63:0] read_C_4___mat_C_ch_in_4__q0; - wire [63:0] mat_C_ch_in_4_read_addr__din; - wire mat_C_ch_in_4_read_addr__full_n; - wire mat_C_ch_in_4_read_addr__write; - wire [511:0] mat_C_ch_in_4_read_data__dout; - wire mat_C_ch_in_4_read_data__empty_n; - wire mat_C_ch_in_4_read_data__read; - wire [63:0] mat_C_ch_in_4_write_addr__din; - wire mat_C_ch_in_4_write_addr__full_n; - wire mat_C_ch_in_4_write_addr__write; - wire [511:0] mat_C_ch_in_4_write_data__din; - wire mat_C_ch_in_4_write_data__full_n; - wire mat_C_ch_in_4_write_data__write; - wire [7:0] mat_C_ch_in_4_write_resp__dout; - wire mat_C_ch_in_4_write_resp__empty_n; - wire mat_C_ch_in_4_write_resp__read; - wire read_C_4__ap_start; - wire read_C_4__ap_ready; - wire read_C_4__ap_done; - wire read_C_4__ap_idle; - wire [31:0] read_C_5___M__q0; - wire [31:0] read_C_5___P_N__q0; - wire [63:0] read_C_5___mat_C_ch_in_5__q0; - wire [63:0] mat_C_ch_in_5_read_addr__din; - wire mat_C_ch_in_5_read_addr__full_n; - wire mat_C_ch_in_5_read_addr__write; - wire [511:0] mat_C_ch_in_5_read_data__dout; - wire mat_C_ch_in_5_read_data__empty_n; - wire mat_C_ch_in_5_read_data__read; - wire [63:0] mat_C_ch_in_5_write_addr__din; - wire mat_C_ch_in_5_write_addr__full_n; - wire mat_C_ch_in_5_write_addr__write; - wire [511:0] mat_C_ch_in_5_write_data__din; - wire mat_C_ch_in_5_write_data__full_n; - wire mat_C_ch_in_5_write_data__write; - wire [7:0] mat_C_ch_in_5_write_resp__dout; - wire mat_C_ch_in_5_write_resp__empty_n; - wire mat_C_ch_in_5_write_resp__read; - wire read_C_5__ap_start; - wire read_C_5__ap_ready; - wire read_C_5__ap_done; - wire read_C_5__ap_idle; - wire [31:0] read_C_6___M__q0; - wire [31:0] read_C_6___P_N__q0; - wire [63:0] read_C_6___mat_C_ch_in_6__q0; - wire [63:0] mat_C_ch_in_6_read_addr__din; - wire mat_C_ch_in_6_read_addr__full_n; - wire mat_C_ch_in_6_read_addr__write; - wire [511:0] mat_C_ch_in_6_read_data__dout; - wire mat_C_ch_in_6_read_data__empty_n; - wire mat_C_ch_in_6_read_data__read; - wire [63:0] mat_C_ch_in_6_write_addr__din; - wire mat_C_ch_in_6_write_addr__full_n; - wire mat_C_ch_in_6_write_addr__write; - wire [511:0] mat_C_ch_in_6_write_data__din; - wire mat_C_ch_in_6_write_data__full_n; - wire mat_C_ch_in_6_write_data__write; - wire [7:0] mat_C_ch_in_6_write_resp__dout; - wire mat_C_ch_in_6_write_resp__empty_n; - wire mat_C_ch_in_6_write_resp__read; - wire read_C_6__ap_start; - wire read_C_6__ap_ready; - wire read_C_6__ap_done; - wire read_C_6__ap_idle; - wire [31:0] read_C_7___M__q0; - wire [31:0] read_C_7___P_N__q0; - wire [63:0] read_C_7___mat_C_ch_in_7__q0; - wire [63:0] mat_C_ch_in_7_read_addr__din; - wire mat_C_ch_in_7_read_addr__full_n; - wire mat_C_ch_in_7_read_addr__write; - wire [511:0] mat_C_ch_in_7_read_data__dout; - wire mat_C_ch_in_7_read_data__empty_n; - wire mat_C_ch_in_7_read_data__read; - wire [63:0] mat_C_ch_in_7_write_addr__din; - wire mat_C_ch_in_7_write_addr__full_n; - wire mat_C_ch_in_7_write_addr__write; - wire [511:0] mat_C_ch_in_7_write_data__din; - wire mat_C_ch_in_7_write_data__full_n; - wire mat_C_ch_in_7_write_data__write; - wire [7:0] mat_C_ch_in_7_write_resp__dout; - wire mat_C_ch_in_7_write_resp__empty_n; - wire mat_C_ch_in_7_write_resp__read; - wire read_C_7__ap_start; - wire read_C_7__ap_ready; - wire read_C_7__ap_done; - wire read_C_7__ap_idle; - wire [31:0] read_edge_list_ptr_0___K__q0; - wire [31:0] read_edge_list_ptr_0___M__q0; - wire [31:0] read_edge_list_ptr_0___NUM_ITE__q0; - wire [31:0] read_edge_list_ptr_0___P_N__q0; - wire [63:0] read_edge_list_ptr_0___edge_list_ptr__q0; - wire [63:0] edge_list_ptr_read_addr__din; - wire edge_list_ptr_read_addr__full_n; - wire edge_list_ptr_read_addr__write; - wire [31:0] edge_list_ptr_read_data__dout; - wire edge_list_ptr_read_data__empty_n; - wire edge_list_ptr_read_data__read; - wire [63:0] edge_list_ptr_write_addr__din; - wire edge_list_ptr_write_addr__full_n; - wire edge_list_ptr_write_addr__write; - wire [31:0] edge_list_ptr_write_data__din; - wire edge_list_ptr_write_data__full_n; - wire edge_list_ptr_write_data__write; - wire [7:0] edge_list_ptr_write_resp__dout; - wire edge_list_ptr_write_resp__empty_n; - wire edge_list_ptr_write_resp__read; - wire read_edge_list_ptr_0__ap_start; - wire read_edge_list_ptr_0__ap_ready; - wire read_edge_list_ptr_0__ap_done; - wire read_edge_list_ptr_0__ap_idle; - wire [63:0] write_C_0___mat_C_ch_0__q0; - wire [63:0] mat_C_ch_0_read_addr__din; - wire mat_C_ch_0_read_addr__full_n; - wire mat_C_ch_0_read_addr__write; - wire [511:0] mat_C_ch_0_read_data__dout; - wire mat_C_ch_0_read_data__empty_n; - wire mat_C_ch_0_read_data__read; - wire [63:0] mat_C_ch_0_write_addr__din; - wire mat_C_ch_0_write_addr__full_n; - wire mat_C_ch_0_write_addr__write; - wire [511:0] mat_C_ch_0_write_data__din; - wire mat_C_ch_0_write_data__full_n; - wire mat_C_ch_0_write_data__write; - wire [7:0] mat_C_ch_0_write_resp__dout; - wire mat_C_ch_0_write_resp__empty_n; - wire mat_C_ch_0_write_resp__read; - wire write_C_0__ap_start; - wire write_C_0__ap_ready; - wire write_C_0__ap_done; - wire write_C_0__ap_idle; - wire [63:0] write_C_1___mat_C_ch_1__q0; - wire [63:0] mat_C_ch_1_read_addr__din; - wire mat_C_ch_1_read_addr__full_n; - wire mat_C_ch_1_read_addr__write; - wire [511:0] mat_C_ch_1_read_data__dout; - wire mat_C_ch_1_read_data__empty_n; - wire mat_C_ch_1_read_data__read; - wire [63:0] mat_C_ch_1_write_addr__din; - wire mat_C_ch_1_write_addr__full_n; - wire mat_C_ch_1_write_addr__write; - wire [511:0] mat_C_ch_1_write_data__din; - wire mat_C_ch_1_write_data__full_n; - wire mat_C_ch_1_write_data__write; - wire [7:0] mat_C_ch_1_write_resp__dout; - wire mat_C_ch_1_write_resp__empty_n; - wire mat_C_ch_1_write_resp__read; - wire write_C_1__ap_start; - wire write_C_1__ap_ready; - wire write_C_1__ap_done; - wire write_C_1__ap_idle; - wire [63:0] write_C_2___mat_C_ch_2__q0; - wire [63:0] mat_C_ch_2_read_addr__din; - wire mat_C_ch_2_read_addr__full_n; - wire mat_C_ch_2_read_addr__write; - wire [511:0] mat_C_ch_2_read_data__dout; - wire mat_C_ch_2_read_data__empty_n; - wire mat_C_ch_2_read_data__read; - wire [63:0] mat_C_ch_2_write_addr__din; - wire mat_C_ch_2_write_addr__full_n; - wire mat_C_ch_2_write_addr__write; - wire [511:0] mat_C_ch_2_write_data__din; - wire mat_C_ch_2_write_data__full_n; - wire mat_C_ch_2_write_data__write; - wire [7:0] mat_C_ch_2_write_resp__dout; - wire mat_C_ch_2_write_resp__empty_n; - wire mat_C_ch_2_write_resp__read; - wire write_C_2__ap_start; - wire write_C_2__ap_ready; - wire write_C_2__ap_done; - wire write_C_2__ap_idle; - wire [63:0] write_C_3___mat_C_ch_3__q0; - wire [63:0] mat_C_ch_3_read_addr__din; - wire mat_C_ch_3_read_addr__full_n; - wire mat_C_ch_3_read_addr__write; - wire [511:0] mat_C_ch_3_read_data__dout; - wire mat_C_ch_3_read_data__empty_n; - wire mat_C_ch_3_read_data__read; - wire [63:0] mat_C_ch_3_write_addr__din; - wire mat_C_ch_3_write_addr__full_n; - wire mat_C_ch_3_write_addr__write; - wire [511:0] mat_C_ch_3_write_data__din; - wire mat_C_ch_3_write_data__full_n; - wire mat_C_ch_3_write_data__write; - wire [7:0] mat_C_ch_3_write_resp__dout; - wire mat_C_ch_3_write_resp__empty_n; - wire mat_C_ch_3_write_resp__read; - wire write_C_3__ap_start; - wire write_C_3__ap_ready; - wire write_C_3__ap_done; - wire write_C_3__ap_idle; - wire [63:0] write_C_4___mat_C_ch_4__q0; - wire [63:0] mat_C_ch_4_read_addr__din; - wire mat_C_ch_4_read_addr__full_n; - wire mat_C_ch_4_read_addr__write; - wire [511:0] mat_C_ch_4_read_data__dout; - wire mat_C_ch_4_read_data__empty_n; - wire mat_C_ch_4_read_data__read; - wire [63:0] mat_C_ch_4_write_addr__din; - wire mat_C_ch_4_write_addr__full_n; - wire mat_C_ch_4_write_addr__write; - wire [511:0] mat_C_ch_4_write_data__din; - wire mat_C_ch_4_write_data__full_n; - wire mat_C_ch_4_write_data__write; - wire [7:0] mat_C_ch_4_write_resp__dout; - wire mat_C_ch_4_write_resp__empty_n; - wire mat_C_ch_4_write_resp__read; - wire write_C_4__ap_start; - wire write_C_4__ap_ready; - wire write_C_4__ap_done; - wire write_C_4__ap_idle; - wire [63:0] write_C_5___mat_C_ch_5__q0; - wire [63:0] mat_C_ch_5_read_addr__din; - wire mat_C_ch_5_read_addr__full_n; - wire mat_C_ch_5_read_addr__write; - wire [511:0] mat_C_ch_5_read_data__dout; - wire mat_C_ch_5_read_data__empty_n; - wire mat_C_ch_5_read_data__read; - wire [63:0] mat_C_ch_5_write_addr__din; - wire mat_C_ch_5_write_addr__full_n; - wire mat_C_ch_5_write_addr__write; - wire [511:0] mat_C_ch_5_write_data__din; - wire mat_C_ch_5_write_data__full_n; - wire mat_C_ch_5_write_data__write; - wire [7:0] mat_C_ch_5_write_resp__dout; - wire mat_C_ch_5_write_resp__empty_n; - wire mat_C_ch_5_write_resp__read; - wire write_C_5__ap_start; - wire write_C_5__ap_ready; - wire write_C_5__ap_done; - wire write_C_5__ap_idle; - wire [63:0] write_C_6___mat_C_ch_6__q0; - wire [63:0] mat_C_ch_6_read_addr__din; - wire mat_C_ch_6_read_addr__full_n; - wire mat_C_ch_6_read_addr__write; - wire [511:0] mat_C_ch_6_read_data__dout; - wire mat_C_ch_6_read_data__empty_n; - wire mat_C_ch_6_read_data__read; - wire [63:0] mat_C_ch_6_write_addr__din; - wire mat_C_ch_6_write_addr__full_n; - wire mat_C_ch_6_write_addr__write; - wire [511:0] mat_C_ch_6_write_data__din; - wire mat_C_ch_6_write_data__full_n; - wire mat_C_ch_6_write_data__write; - wire [7:0] mat_C_ch_6_write_resp__dout; - wire mat_C_ch_6_write_resp__empty_n; - wire mat_C_ch_6_write_resp__read; - wire write_C_6__ap_start; - wire write_C_6__ap_ready; - wire write_C_6__ap_done; - wire write_C_6__ap_idle; - wire [63:0] write_C_7___mat_C_ch_7__q0; - wire [63:0] mat_C_ch_7_read_addr__din; - wire mat_C_ch_7_read_addr__full_n; - wire mat_C_ch_7_read_addr__write; - wire [511:0] mat_C_ch_7_read_data__dout; - wire mat_C_ch_7_read_data__empty_n; - wire mat_C_ch_7_read_data__read; - wire [63:0] mat_C_ch_7_write_addr__din; - wire mat_C_ch_7_write_addr__full_n; - wire mat_C_ch_7_write_addr__write; - wire [511:0] mat_C_ch_7_write_data__din; - wire mat_C_ch_7_write_data__full_n; - wire mat_C_ch_7_write_data__write; - wire [7:0] mat_C_ch_7_write_resp__dout; - wire mat_C_ch_7_write_resp__empty_n; - wire mat_C_ch_7_write_resp__read; - wire write_C_7__ap_start; - wire write_C_7__ap_ready; - wire write_C_7__ap_done; - wire write_C_7__ap_idle; - wire ap_rst_n_inv; - wire ap_done; - wire ap_idle; - wire ap_ready; - - Sextans_control_s_axi - #( - .C_S_AXI_ADDR_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .C_S_AXI_DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH) - ) - control_s_axi_U - ( - .AWVALID(s_axi_control_AWVALID), - .AWREADY(s_axi_control_AWREADY), - .AWADDR(s_axi_control_AWADDR), - .WVALID(s_axi_control_WVALID), - .WREADY(s_axi_control_WREADY), - .WDATA(s_axi_control_WDATA), - .WSTRB(s_axi_control_WSTRB), - .ARVALID(s_axi_control_ARVALID), - .ARREADY(s_axi_control_ARREADY), - .ARADDR(s_axi_control_ARADDR), - .RVALID(s_axi_control_RVALID), - .RREADY(s_axi_control_RREADY), - .RDATA(s_axi_control_RDATA), - .RRESP(s_axi_control_RRESP), - .BVALID(s_axi_control_BVALID), - .BREADY(s_axi_control_BREADY), - .BRESP(s_axi_control_BRESP), - .ACLK(ap_clk), - .ARESET(ap_rst_n_inv), - .ACLK_EN(1'b1), - .edge_list_ptr(edge_list_ptr), - .edge_list_ch_0(edge_list_ch_0), - .edge_list_ch_1(edge_list_ch_1), - .edge_list_ch_2(edge_list_ch_2), - .edge_list_ch_3(edge_list_ch_3), - .edge_list_ch_4(edge_list_ch_4), - .edge_list_ch_5(edge_list_ch_5), - .edge_list_ch_6(edge_list_ch_6), - .edge_list_ch_7(edge_list_ch_7), - .mat_B_ch_0(mat_B_ch_0), - .mat_B_ch_1(mat_B_ch_1), - .mat_B_ch_2(mat_B_ch_2), - .mat_B_ch_3(mat_B_ch_3), - .mat_C_ch_in_0(mat_C_ch_in_0), - .mat_C_ch_in_1(mat_C_ch_in_1), - .mat_C_ch_in_2(mat_C_ch_in_2), - .mat_C_ch_in_3(mat_C_ch_in_3), - .mat_C_ch_in_4(mat_C_ch_in_4), - .mat_C_ch_in_5(mat_C_ch_in_5), - .mat_C_ch_in_6(mat_C_ch_in_6), - .mat_C_ch_in_7(mat_C_ch_in_7), - .mat_C_ch_0(mat_C_ch_0), - .mat_C_ch_1(mat_C_ch_1), - .mat_C_ch_2(mat_C_ch_2), - .mat_C_ch_3(mat_C_ch_3), - .mat_C_ch_4(mat_C_ch_4), - .mat_C_ch_5(mat_C_ch_5), - .mat_C_ch_6(mat_C_ch_6), - .mat_C_ch_7(mat_C_ch_7), - .NUM_ITE(NUM_ITE), - .NUM_A_LEN(NUM_A_LEN), - .M(M), - .K(K), - .P_N(P_N), - .alpha_u(alpha_u), - .beta_u(beta_u), - .ap_start(ap_start), - .interrupt(interrupt), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_idle(ap_idle) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_0__dout), - .if_empty_n(PE_inst_Sextans_0__empty_n), - .if_read(PE_inst_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_0__din), - .if_full_n(PE_inst_Sextans_0__full_n), - .if_write(PE_inst_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_10 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_10__dout), - .if_empty_n(PE_inst_Sextans_10__empty_n), - .if_read(PE_inst_Sextans_10__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_10__din), - .if_full_n(PE_inst_Sextans_10__full_n), - .if_write(PE_inst_Sextans_10__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_11 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_11__dout), - .if_empty_n(PE_inst_Sextans_11__empty_n), - .if_read(PE_inst_Sextans_11__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_11__din), - .if_full_n(PE_inst_Sextans_11__full_n), - .if_write(PE_inst_Sextans_11__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_12 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_12__dout), - .if_empty_n(PE_inst_Sextans_12__empty_n), - .if_read(PE_inst_Sextans_12__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_12__din), - .if_full_n(PE_inst_Sextans_12__full_n), - .if_write(PE_inst_Sextans_12__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_13 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_13__dout), - .if_empty_n(PE_inst_Sextans_13__empty_n), - .if_read(PE_inst_Sextans_13__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_13__din), - .if_full_n(PE_inst_Sextans_13__full_n), - .if_write(PE_inst_Sextans_13__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_14 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_14__dout), - .if_empty_n(PE_inst_Sextans_14__empty_n), - .if_read(PE_inst_Sextans_14__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_14__din), - .if_full_n(PE_inst_Sextans_14__full_n), - .if_write(PE_inst_Sextans_14__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_15 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_15__dout), - .if_empty_n(PE_inst_Sextans_15__empty_n), - .if_read(PE_inst_Sextans_15__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_15__din), - .if_full_n(PE_inst_Sextans_15__full_n), - .if_write(PE_inst_Sextans_15__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_16 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_16__dout), - .if_empty_n(PE_inst_Sextans_16__empty_n), - .if_read(PE_inst_Sextans_16__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_16__din), - .if_full_n(PE_inst_Sextans_16__full_n), - .if_write(PE_inst_Sextans_16__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_1__dout), - .if_empty_n(PE_inst_Sextans_1__empty_n), - .if_read(PE_inst_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_1__din), - .if_full_n(PE_inst_Sextans_1__full_n), - .if_write(PE_inst_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_2__dout), - .if_empty_n(PE_inst_Sextans_2__empty_n), - .if_read(PE_inst_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_2__din), - .if_full_n(PE_inst_Sextans_2__full_n), - .if_write(PE_inst_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_3__dout), - .if_empty_n(PE_inst_Sextans_3__empty_n), - .if_read(PE_inst_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_3__din), - .if_full_n(PE_inst_Sextans_3__full_n), - .if_write(PE_inst_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_4__dout), - .if_empty_n(PE_inst_Sextans_4__empty_n), - .if_read(PE_inst_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_4__din), - .if_full_n(PE_inst_Sextans_4__full_n), - .if_write(PE_inst_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_5__dout), - .if_empty_n(PE_inst_Sextans_5__empty_n), - .if_read(PE_inst_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_5__din), - .if_full_n(PE_inst_Sextans_5__full_n), - .if_write(PE_inst_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_6__dout), - .if_empty_n(PE_inst_Sextans_6__empty_n), - .if_read(PE_inst_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_6__din), - .if_full_n(PE_inst_Sextans_6__full_n), - .if_write(PE_inst_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_7__dout), - .if_empty_n(PE_inst_Sextans_7__empty_n), - .if_read(PE_inst_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_7__din), - .if_full_n(PE_inst_Sextans_7__full_n), - .if_write(PE_inst_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_8 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_8__dout), - .if_empty_n(PE_inst_Sextans_8__empty_n), - .if_read(PE_inst_Sextans_8__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_8__din), - .if_full_n(PE_inst_Sextans_8__full_n), - .if_write(PE_inst_Sextans_8__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_Sextans_9 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_Sextans_9__dout), - .if_empty_n(PE_inst_Sextans_9__empty_n), - .if_read(PE_inst_Sextans_9__read), - .if_read_ce(1'b1), - .if_din(PE_inst_Sextans_9__din), - .if_full_n(PE_inst_Sextans_9__full_n), - .if_write(PE_inst_Sextans_9__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_0__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_0__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_0__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_0__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_10 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_10__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_10__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_10__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_10__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_10__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_10__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_11 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_11__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_11__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_11__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_11__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_11__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_11__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_12 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_12__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_12__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_12__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_12__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_12__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_12__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_13 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_13__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_13__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_13__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_13__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_13__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_13__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_14 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_14__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_14__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_14__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_14__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_14__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_14__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_15 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_15__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_15__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_15__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_15__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_15__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_15__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_1__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_1__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_1__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_1__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_2__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_2__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_2__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_2__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_3__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_3__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_3__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_3__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_4__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_4__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_4__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_4__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_5__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_5__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_5__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_5__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_6__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_6__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_6__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_6__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_7__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_7__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_7__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_7__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_8 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_8__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_8__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_8__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_8__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_8__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_8__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - PE_inst_to_Cmtx_Sextans_9 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(PE_inst_to_Cmtx_Sextans_9__dout), - .if_empty_n(PE_inst_to_Cmtx_Sextans_9__empty_n), - .if_read(PE_inst_to_Cmtx_Sextans_9__read), - .if_read_ce(1'b1), - .if_din(PE_inst_to_Cmtx_Sextans_9__din), - .if_full_n(PE_inst_to_Cmtx_Sextans_9__full_n), - .if_write(PE_inst_to_Cmtx_Sextans_9__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_Sextans_0__dout), - .if_empty_n(fifo_A_Sextans_0__empty_n), - .if_read(fifo_A_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_A_Sextans_0__din), - .if_full_n(fifo_A_Sextans_0__full_n), - .if_write(fifo_A_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_Sextans_1__dout), - .if_empty_n(fifo_A_Sextans_1__empty_n), - .if_read(fifo_A_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_A_Sextans_1__din), - .if_full_n(fifo_A_Sextans_1__full_n), - .if_write(fifo_A_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_Sextans_2__dout), - .if_empty_n(fifo_A_Sextans_2__empty_n), - .if_read(fifo_A_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_A_Sextans_2__din), - .if_full_n(fifo_A_Sextans_2__full_n), - .if_write(fifo_A_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_Sextans_3__dout), - .if_empty_n(fifo_A_Sextans_3__empty_n), - .if_read(fifo_A_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_A_Sextans_3__din), - .if_full_n(fifo_A_Sextans_3__full_n), - .if_write(fifo_A_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_Sextans_4__dout), - .if_empty_n(fifo_A_Sextans_4__empty_n), - .if_read(fifo_A_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_A_Sextans_4__din), - .if_full_n(fifo_A_Sextans_4__full_n), - .if_write(fifo_A_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_Sextans_5__dout), - .if_empty_n(fifo_A_Sextans_5__empty_n), - .if_read(fifo_A_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_A_Sextans_5__din), - .if_full_n(fifo_A_Sextans_5__full_n), - .if_write(fifo_A_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_Sextans_6__dout), - .if_empty_n(fifo_A_Sextans_6__empty_n), - .if_read(fifo_A_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_A_Sextans_6__din), - .if_full_n(fifo_A_Sextans_6__full_n), - .if_write(fifo_A_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_Sextans_7__dout), - .if_empty_n(fifo_A_Sextans_7__empty_n), - .if_read(fifo_A_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_A_Sextans_7__din), - .if_full_n(fifo_A_Sextans_7__full_n), - .if_write(fifo_A_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_0__dout), - .if_empty_n(fifo_A_pe_Sextans_0__empty_n), - .if_read(fifo_A_pe_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_0__din), - .if_full_n(fifo_A_pe_Sextans_0__full_n), - .if_write(fifo_A_pe_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_10 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_10__dout), - .if_empty_n(fifo_A_pe_Sextans_10__empty_n), - .if_read(fifo_A_pe_Sextans_10__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_10__din), - .if_full_n(fifo_A_pe_Sextans_10__full_n), - .if_write(fifo_A_pe_Sextans_10__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_11 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_11__dout), - .if_empty_n(fifo_A_pe_Sextans_11__empty_n), - .if_read(fifo_A_pe_Sextans_11__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_11__din), - .if_full_n(fifo_A_pe_Sextans_11__full_n), - .if_write(fifo_A_pe_Sextans_11__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_12 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_12__dout), - .if_empty_n(fifo_A_pe_Sextans_12__empty_n), - .if_read(fifo_A_pe_Sextans_12__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_12__din), - .if_full_n(fifo_A_pe_Sextans_12__full_n), - .if_write(fifo_A_pe_Sextans_12__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_13 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_13__dout), - .if_empty_n(fifo_A_pe_Sextans_13__empty_n), - .if_read(fifo_A_pe_Sextans_13__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_13__din), - .if_full_n(fifo_A_pe_Sextans_13__full_n), - .if_write(fifo_A_pe_Sextans_13__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_14 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_14__dout), - .if_empty_n(fifo_A_pe_Sextans_14__empty_n), - .if_read(fifo_A_pe_Sextans_14__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_14__din), - .if_full_n(fifo_A_pe_Sextans_14__full_n), - .if_write(fifo_A_pe_Sextans_14__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_15 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_15__dout), - .if_empty_n(fifo_A_pe_Sextans_15__empty_n), - .if_read(fifo_A_pe_Sextans_15__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_15__din), - .if_full_n(fifo_A_pe_Sextans_15__full_n), - .if_write(fifo_A_pe_Sextans_15__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_1__dout), - .if_empty_n(fifo_A_pe_Sextans_1__empty_n), - .if_read(fifo_A_pe_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_1__din), - .if_full_n(fifo_A_pe_Sextans_1__full_n), - .if_write(fifo_A_pe_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_2__dout), - .if_empty_n(fifo_A_pe_Sextans_2__empty_n), - .if_read(fifo_A_pe_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_2__din), - .if_full_n(fifo_A_pe_Sextans_2__full_n), - .if_write(fifo_A_pe_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_3__dout), - .if_empty_n(fifo_A_pe_Sextans_3__empty_n), - .if_read(fifo_A_pe_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_3__din), - .if_full_n(fifo_A_pe_Sextans_3__full_n), - .if_write(fifo_A_pe_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_4__dout), - .if_empty_n(fifo_A_pe_Sextans_4__empty_n), - .if_read(fifo_A_pe_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_4__din), - .if_full_n(fifo_A_pe_Sextans_4__full_n), - .if_write(fifo_A_pe_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_5__dout), - .if_empty_n(fifo_A_pe_Sextans_5__empty_n), - .if_read(fifo_A_pe_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_5__din), - .if_full_n(fifo_A_pe_Sextans_5__full_n), - .if_write(fifo_A_pe_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_6__dout), - .if_empty_n(fifo_A_pe_Sextans_6__empty_n), - .if_read(fifo_A_pe_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_6__din), - .if_full_n(fifo_A_pe_Sextans_6__full_n), - .if_write(fifo_A_pe_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_7__dout), - .if_empty_n(fifo_A_pe_Sextans_7__empty_n), - .if_read(fifo_A_pe_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_7__din), - .if_full_n(fifo_A_pe_Sextans_7__full_n), - .if_write(fifo_A_pe_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_8 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_8__dout), - .if_empty_n(fifo_A_pe_Sextans_8__empty_n), - .if_read(fifo_A_pe_Sextans_8__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_8__din), - .if_full_n(fifo_A_pe_Sextans_8__full_n), - .if_write(fifo_A_pe_Sextans_8__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_A_pe_Sextans_9 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_A_pe_Sextans_9__dout), - .if_empty_n(fifo_A_pe_Sextans_9__empty_n), - .if_read(fifo_A_pe_Sextans_9__read), - .if_read_ce(1'b1), - .if_din(fifo_A_pe_Sextans_9__din), - .if_full_n(fifo_A_pe_Sextans_9__full_n), - .if_write(fifo_A_pe_Sextans_9__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_0__dout), - .if_empty_n(fifo_B_pe_Sextans_0__empty_n), - .if_read(fifo_B_pe_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_0__din), - .if_full_n(fifo_B_pe_Sextans_0__full_n), - .if_write(fifo_B_pe_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_10 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_10__dout), - .if_empty_n(fifo_B_pe_Sextans_10__empty_n), - .if_read(fifo_B_pe_Sextans_10__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_10__din), - .if_full_n(fifo_B_pe_Sextans_10__full_n), - .if_write(fifo_B_pe_Sextans_10__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_11 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_11__dout), - .if_empty_n(fifo_B_pe_Sextans_11__empty_n), - .if_read(fifo_B_pe_Sextans_11__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_11__din), - .if_full_n(fifo_B_pe_Sextans_11__full_n), - .if_write(fifo_B_pe_Sextans_11__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_12 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_12__dout), - .if_empty_n(fifo_B_pe_Sextans_12__empty_n), - .if_read(fifo_B_pe_Sextans_12__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_12__din), - .if_full_n(fifo_B_pe_Sextans_12__full_n), - .if_write(fifo_B_pe_Sextans_12__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_13 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_13__dout), - .if_empty_n(fifo_B_pe_Sextans_13__empty_n), - .if_read(fifo_B_pe_Sextans_13__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_13__din), - .if_full_n(fifo_B_pe_Sextans_13__full_n), - .if_write(fifo_B_pe_Sextans_13__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_14 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_14__dout), - .if_empty_n(fifo_B_pe_Sextans_14__empty_n), - .if_read(fifo_B_pe_Sextans_14__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_14__din), - .if_full_n(fifo_B_pe_Sextans_14__full_n), - .if_write(fifo_B_pe_Sextans_14__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_15 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_15__dout), - .if_empty_n(fifo_B_pe_Sextans_15__empty_n), - .if_read(fifo_B_pe_Sextans_15__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_15__din), - .if_full_n(fifo_B_pe_Sextans_15__full_n), - .if_write(fifo_B_pe_Sextans_15__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_16 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_16__dout), - .if_empty_n(fifo_B_pe_Sextans_16__empty_n), - .if_read(fifo_B_pe_Sextans_16__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_16__din), - .if_full_n(fifo_B_pe_Sextans_16__full_n), - .if_write(fifo_B_pe_Sextans_16__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_17 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_17__dout), - .if_empty_n(fifo_B_pe_Sextans_17__empty_n), - .if_read(fifo_B_pe_Sextans_17__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_17__din), - .if_full_n(fifo_B_pe_Sextans_17__full_n), - .if_write(fifo_B_pe_Sextans_17__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_18 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_18__dout), - .if_empty_n(fifo_B_pe_Sextans_18__empty_n), - .if_read(fifo_B_pe_Sextans_18__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_18__din), - .if_full_n(fifo_B_pe_Sextans_18__full_n), - .if_write(fifo_B_pe_Sextans_18__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_19 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_19__dout), - .if_empty_n(fifo_B_pe_Sextans_19__empty_n), - .if_read(fifo_B_pe_Sextans_19__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_19__din), - .if_full_n(fifo_B_pe_Sextans_19__full_n), - .if_write(fifo_B_pe_Sextans_19__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_1__dout), - .if_empty_n(fifo_B_pe_Sextans_1__empty_n), - .if_read(fifo_B_pe_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_1__din), - .if_full_n(fifo_B_pe_Sextans_1__full_n), - .if_write(fifo_B_pe_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_20 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_20__dout), - .if_empty_n(fifo_B_pe_Sextans_20__empty_n), - .if_read(fifo_B_pe_Sextans_20__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_20__din), - .if_full_n(fifo_B_pe_Sextans_20__full_n), - .if_write(fifo_B_pe_Sextans_20__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_21 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_21__dout), - .if_empty_n(fifo_B_pe_Sextans_21__empty_n), - .if_read(fifo_B_pe_Sextans_21__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_21__din), - .if_full_n(fifo_B_pe_Sextans_21__full_n), - .if_write(fifo_B_pe_Sextans_21__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_22 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_22__dout), - .if_empty_n(fifo_B_pe_Sextans_22__empty_n), - .if_read(fifo_B_pe_Sextans_22__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_22__din), - .if_full_n(fifo_B_pe_Sextans_22__full_n), - .if_write(fifo_B_pe_Sextans_22__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_23 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_23__dout), - .if_empty_n(fifo_B_pe_Sextans_23__empty_n), - .if_read(fifo_B_pe_Sextans_23__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_23__din), - .if_full_n(fifo_B_pe_Sextans_23__full_n), - .if_write(fifo_B_pe_Sextans_23__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_24 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_24__dout), - .if_empty_n(fifo_B_pe_Sextans_24__empty_n), - .if_read(fifo_B_pe_Sextans_24__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_24__din), - .if_full_n(fifo_B_pe_Sextans_24__full_n), - .if_write(fifo_B_pe_Sextans_24__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_25 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_25__dout), - .if_empty_n(fifo_B_pe_Sextans_25__empty_n), - .if_read(fifo_B_pe_Sextans_25__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_25__din), - .if_full_n(fifo_B_pe_Sextans_25__full_n), - .if_write(fifo_B_pe_Sextans_25__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_26 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_26__dout), - .if_empty_n(fifo_B_pe_Sextans_26__empty_n), - .if_read(fifo_B_pe_Sextans_26__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_26__din), - .if_full_n(fifo_B_pe_Sextans_26__full_n), - .if_write(fifo_B_pe_Sextans_26__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_27 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_27__dout), - .if_empty_n(fifo_B_pe_Sextans_27__empty_n), - .if_read(fifo_B_pe_Sextans_27__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_27__din), - .if_full_n(fifo_B_pe_Sextans_27__full_n), - .if_write(fifo_B_pe_Sextans_27__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_28 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_28__dout), - .if_empty_n(fifo_B_pe_Sextans_28__empty_n), - .if_read(fifo_B_pe_Sextans_28__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_28__din), - .if_full_n(fifo_B_pe_Sextans_28__full_n), - .if_write(fifo_B_pe_Sextans_28__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_29 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_29__dout), - .if_empty_n(fifo_B_pe_Sextans_29__empty_n), - .if_read(fifo_B_pe_Sextans_29__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_29__din), - .if_full_n(fifo_B_pe_Sextans_29__full_n), - .if_write(fifo_B_pe_Sextans_29__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_2__dout), - .if_empty_n(fifo_B_pe_Sextans_2__empty_n), - .if_read(fifo_B_pe_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_2__din), - .if_full_n(fifo_B_pe_Sextans_2__full_n), - .if_write(fifo_B_pe_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_30 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_30__dout), - .if_empty_n(fifo_B_pe_Sextans_30__empty_n), - .if_read(fifo_B_pe_Sextans_30__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_30__din), - .if_full_n(fifo_B_pe_Sextans_30__full_n), - .if_write(fifo_B_pe_Sextans_30__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_31 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_31__dout), - .if_empty_n(fifo_B_pe_Sextans_31__empty_n), - .if_read(fifo_B_pe_Sextans_31__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_31__din), - .if_full_n(fifo_B_pe_Sextans_31__full_n), - .if_write(fifo_B_pe_Sextans_31__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_32 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_32__dout), - .if_empty_n(fifo_B_pe_Sextans_32__empty_n), - .if_read(fifo_B_pe_Sextans_32__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_32__din), - .if_full_n(fifo_B_pe_Sextans_32__full_n), - .if_write(fifo_B_pe_Sextans_32__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_33 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_33__dout), - .if_empty_n(fifo_B_pe_Sextans_33__empty_n), - .if_read(fifo_B_pe_Sextans_33__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_33__din), - .if_full_n(fifo_B_pe_Sextans_33__full_n), - .if_write(fifo_B_pe_Sextans_33__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_34 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_34__dout), - .if_empty_n(fifo_B_pe_Sextans_34__empty_n), - .if_read(fifo_B_pe_Sextans_34__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_34__din), - .if_full_n(fifo_B_pe_Sextans_34__full_n), - .if_write(fifo_B_pe_Sextans_34__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_35 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_35__dout), - .if_empty_n(fifo_B_pe_Sextans_35__empty_n), - .if_read(fifo_B_pe_Sextans_35__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_35__din), - .if_full_n(fifo_B_pe_Sextans_35__full_n), - .if_write(fifo_B_pe_Sextans_35__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_36 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_36__dout), - .if_empty_n(fifo_B_pe_Sextans_36__empty_n), - .if_read(fifo_B_pe_Sextans_36__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_36__din), - .if_full_n(fifo_B_pe_Sextans_36__full_n), - .if_write(fifo_B_pe_Sextans_36__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_37 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_37__dout), - .if_empty_n(fifo_B_pe_Sextans_37__empty_n), - .if_read(fifo_B_pe_Sextans_37__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_37__din), - .if_full_n(fifo_B_pe_Sextans_37__full_n), - .if_write(fifo_B_pe_Sextans_37__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_38 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_38__dout), - .if_empty_n(fifo_B_pe_Sextans_38__empty_n), - .if_read(fifo_B_pe_Sextans_38__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_38__din), - .if_full_n(fifo_B_pe_Sextans_38__full_n), - .if_write(fifo_B_pe_Sextans_38__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_39 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_39__dout), - .if_empty_n(fifo_B_pe_Sextans_39__empty_n), - .if_read(fifo_B_pe_Sextans_39__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_39__din), - .if_full_n(fifo_B_pe_Sextans_39__full_n), - .if_write(fifo_B_pe_Sextans_39__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_3__dout), - .if_empty_n(fifo_B_pe_Sextans_3__empty_n), - .if_read(fifo_B_pe_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_3__din), - .if_full_n(fifo_B_pe_Sextans_3__full_n), - .if_write(fifo_B_pe_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_40 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_40__dout), - .if_empty_n(fifo_B_pe_Sextans_40__empty_n), - .if_read(fifo_B_pe_Sextans_40__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_40__din), - .if_full_n(fifo_B_pe_Sextans_40__full_n), - .if_write(fifo_B_pe_Sextans_40__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_41 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_41__dout), - .if_empty_n(fifo_B_pe_Sextans_41__empty_n), - .if_read(fifo_B_pe_Sextans_41__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_41__din), - .if_full_n(fifo_B_pe_Sextans_41__full_n), - .if_write(fifo_B_pe_Sextans_41__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_42 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_42__dout), - .if_empty_n(fifo_B_pe_Sextans_42__empty_n), - .if_read(fifo_B_pe_Sextans_42__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_42__din), - .if_full_n(fifo_B_pe_Sextans_42__full_n), - .if_write(fifo_B_pe_Sextans_42__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_43 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_43__dout), - .if_empty_n(fifo_B_pe_Sextans_43__empty_n), - .if_read(fifo_B_pe_Sextans_43__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_43__din), - .if_full_n(fifo_B_pe_Sextans_43__full_n), - .if_write(fifo_B_pe_Sextans_43__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_44 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_44__dout), - .if_empty_n(fifo_B_pe_Sextans_44__empty_n), - .if_read(fifo_B_pe_Sextans_44__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_44__din), - .if_full_n(fifo_B_pe_Sextans_44__full_n), - .if_write(fifo_B_pe_Sextans_44__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_45 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_45__dout), - .if_empty_n(fifo_B_pe_Sextans_45__empty_n), - .if_read(fifo_B_pe_Sextans_45__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_45__din), - .if_full_n(fifo_B_pe_Sextans_45__full_n), - .if_write(fifo_B_pe_Sextans_45__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_46 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_46__dout), - .if_empty_n(fifo_B_pe_Sextans_46__empty_n), - .if_read(fifo_B_pe_Sextans_46__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_46__din), - .if_full_n(fifo_B_pe_Sextans_46__full_n), - .if_write(fifo_B_pe_Sextans_46__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_47 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_47__dout), - .if_empty_n(fifo_B_pe_Sextans_47__empty_n), - .if_read(fifo_B_pe_Sextans_47__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_47__din), - .if_full_n(fifo_B_pe_Sextans_47__full_n), - .if_write(fifo_B_pe_Sextans_47__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_48 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_48__dout), - .if_empty_n(fifo_B_pe_Sextans_48__empty_n), - .if_read(fifo_B_pe_Sextans_48__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_48__din), - .if_full_n(fifo_B_pe_Sextans_48__full_n), - .if_write(fifo_B_pe_Sextans_48__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_49 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_49__dout), - .if_empty_n(fifo_B_pe_Sextans_49__empty_n), - .if_read(fifo_B_pe_Sextans_49__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_49__din), - .if_full_n(fifo_B_pe_Sextans_49__full_n), - .if_write(fifo_B_pe_Sextans_49__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_4__dout), - .if_empty_n(fifo_B_pe_Sextans_4__empty_n), - .if_read(fifo_B_pe_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_4__din), - .if_full_n(fifo_B_pe_Sextans_4__full_n), - .if_write(fifo_B_pe_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_50 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_50__dout), - .if_empty_n(fifo_B_pe_Sextans_50__empty_n), - .if_read(fifo_B_pe_Sextans_50__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_50__din), - .if_full_n(fifo_B_pe_Sextans_50__full_n), - .if_write(fifo_B_pe_Sextans_50__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_51 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_51__dout), - .if_empty_n(fifo_B_pe_Sextans_51__empty_n), - .if_read(fifo_B_pe_Sextans_51__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_51__din), - .if_full_n(fifo_B_pe_Sextans_51__full_n), - .if_write(fifo_B_pe_Sextans_51__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_52 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_52__dout), - .if_empty_n(fifo_B_pe_Sextans_52__empty_n), - .if_read(fifo_B_pe_Sextans_52__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_52__din), - .if_full_n(fifo_B_pe_Sextans_52__full_n), - .if_write(fifo_B_pe_Sextans_52__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_53 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_53__dout), - .if_empty_n(fifo_B_pe_Sextans_53__empty_n), - .if_read(fifo_B_pe_Sextans_53__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_53__din), - .if_full_n(fifo_B_pe_Sextans_53__full_n), - .if_write(fifo_B_pe_Sextans_53__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_54 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_54__dout), - .if_empty_n(fifo_B_pe_Sextans_54__empty_n), - .if_read(fifo_B_pe_Sextans_54__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_54__din), - .if_full_n(fifo_B_pe_Sextans_54__full_n), - .if_write(fifo_B_pe_Sextans_54__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_55 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_55__dout), - .if_empty_n(fifo_B_pe_Sextans_55__empty_n), - .if_read(fifo_B_pe_Sextans_55__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_55__din), - .if_full_n(fifo_B_pe_Sextans_55__full_n), - .if_write(fifo_B_pe_Sextans_55__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_56 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_56__dout), - .if_empty_n(fifo_B_pe_Sextans_56__empty_n), - .if_read(fifo_B_pe_Sextans_56__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_56__din), - .if_full_n(fifo_B_pe_Sextans_56__full_n), - .if_write(fifo_B_pe_Sextans_56__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_57 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_57__dout), - .if_empty_n(fifo_B_pe_Sextans_57__empty_n), - .if_read(fifo_B_pe_Sextans_57__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_57__din), - .if_full_n(fifo_B_pe_Sextans_57__full_n), - .if_write(fifo_B_pe_Sextans_57__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_58 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_58__dout), - .if_empty_n(fifo_B_pe_Sextans_58__empty_n), - .if_read(fifo_B_pe_Sextans_58__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_58__din), - .if_full_n(fifo_B_pe_Sextans_58__full_n), - .if_write(fifo_B_pe_Sextans_58__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_59 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_59__dout), - .if_empty_n(fifo_B_pe_Sextans_59__empty_n), - .if_read(fifo_B_pe_Sextans_59__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_59__din), - .if_full_n(fifo_B_pe_Sextans_59__full_n), - .if_write(fifo_B_pe_Sextans_59__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_5__dout), - .if_empty_n(fifo_B_pe_Sextans_5__empty_n), - .if_read(fifo_B_pe_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_5__din), - .if_full_n(fifo_B_pe_Sextans_5__full_n), - .if_write(fifo_B_pe_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_60 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_60__dout), - .if_empty_n(fifo_B_pe_Sextans_60__empty_n), - .if_read(fifo_B_pe_Sextans_60__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_60__din), - .if_full_n(fifo_B_pe_Sextans_60__full_n), - .if_write(fifo_B_pe_Sextans_60__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_61 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_61__dout), - .if_empty_n(fifo_B_pe_Sextans_61__empty_n), - .if_read(fifo_B_pe_Sextans_61__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_61__din), - .if_full_n(fifo_B_pe_Sextans_61__full_n), - .if_write(fifo_B_pe_Sextans_61__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_62 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_62__dout), - .if_empty_n(fifo_B_pe_Sextans_62__empty_n), - .if_read(fifo_B_pe_Sextans_62__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_62__din), - .if_full_n(fifo_B_pe_Sextans_62__full_n), - .if_write(fifo_B_pe_Sextans_62__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_63 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_63__dout), - .if_empty_n(fifo_B_pe_Sextans_63__empty_n), - .if_read(fifo_B_pe_Sextans_63__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_63__din), - .if_full_n(fifo_B_pe_Sextans_63__full_n), - .if_write(fifo_B_pe_Sextans_63__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_64 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_64__dout), - .if_empty_n(fifo_B_pe_Sextans_64__empty_n), - .if_read(fifo_B_pe_Sextans_64__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_64__din), - .if_full_n(fifo_B_pe_Sextans_64__full_n), - .if_write(fifo_B_pe_Sextans_64__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_65 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_65__dout), - .if_empty_n(fifo_B_pe_Sextans_65__empty_n), - .if_read(fifo_B_pe_Sextans_65__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_65__din), - .if_full_n(fifo_B_pe_Sextans_65__full_n), - .if_write(fifo_B_pe_Sextans_65__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_66 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_66__dout), - .if_empty_n(fifo_B_pe_Sextans_66__empty_n), - .if_read(fifo_B_pe_Sextans_66__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_66__din), - .if_full_n(fifo_B_pe_Sextans_66__full_n), - .if_write(fifo_B_pe_Sextans_66__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_67 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_67__dout), - .if_empty_n(fifo_B_pe_Sextans_67__empty_n), - .if_read(fifo_B_pe_Sextans_67__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_67__din), - .if_full_n(fifo_B_pe_Sextans_67__full_n), - .if_write(fifo_B_pe_Sextans_67__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_6__dout), - .if_empty_n(fifo_B_pe_Sextans_6__empty_n), - .if_read(fifo_B_pe_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_6__din), - .if_full_n(fifo_B_pe_Sextans_6__full_n), - .if_write(fifo_B_pe_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_7__dout), - .if_empty_n(fifo_B_pe_Sextans_7__empty_n), - .if_read(fifo_B_pe_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_7__din), - .if_full_n(fifo_B_pe_Sextans_7__full_n), - .if_write(fifo_B_pe_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_8 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_8__dout), - .if_empty_n(fifo_B_pe_Sextans_8__empty_n), - .if_read(fifo_B_pe_Sextans_8__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_8__din), - .if_full_n(fifo_B_pe_Sextans_8__full_n), - .if_write(fifo_B_pe_Sextans_8__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_B_pe_Sextans_9 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_B_pe_Sextans_9__dout), - .if_empty_n(fifo_B_pe_Sextans_9__empty_n), - .if_read(fifo_B_pe_Sextans_9__read), - .if_read_ce(1'b1), - .if_din(fifo_B_pe_Sextans_9__din), - .if_full_n(fifo_B_pe_Sextans_9__full_n), - .if_write(fifo_B_pe_Sextans_9__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_Sextans_0__dout), - .if_empty_n(fifo_C_ch_Sextans_0__empty_n), - .if_read(fifo_C_ch_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_Sextans_0__din), - .if_full_n(fifo_C_ch_Sextans_0__full_n), - .if_write(fifo_C_ch_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_Sextans_1__dout), - .if_empty_n(fifo_C_ch_Sextans_1__empty_n), - .if_read(fifo_C_ch_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_Sextans_1__din), - .if_full_n(fifo_C_ch_Sextans_1__full_n), - .if_write(fifo_C_ch_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_Sextans_2__dout), - .if_empty_n(fifo_C_ch_Sextans_2__empty_n), - .if_read(fifo_C_ch_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_Sextans_2__din), - .if_full_n(fifo_C_ch_Sextans_2__full_n), - .if_write(fifo_C_ch_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_Sextans_3__dout), - .if_empty_n(fifo_C_ch_Sextans_3__empty_n), - .if_read(fifo_C_ch_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_Sextans_3__din), - .if_full_n(fifo_C_ch_Sextans_3__full_n), - .if_write(fifo_C_ch_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_Sextans_4__dout), - .if_empty_n(fifo_C_ch_Sextans_4__empty_n), - .if_read(fifo_C_ch_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_Sextans_4__din), - .if_full_n(fifo_C_ch_Sextans_4__full_n), - .if_write(fifo_C_ch_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_Sextans_5__dout), - .if_empty_n(fifo_C_ch_Sextans_5__empty_n), - .if_read(fifo_C_ch_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_Sextans_5__din), - .if_full_n(fifo_C_ch_Sextans_5__full_n), - .if_write(fifo_C_ch_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_Sextans_6__dout), - .if_empty_n(fifo_C_ch_Sextans_6__empty_n), - .if_read(fifo_C_ch_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_Sextans_6__din), - .if_full_n(fifo_C_ch_Sextans_6__full_n), - .if_write(fifo_C_ch_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_Sextans_7__dout), - .if_empty_n(fifo_C_ch_Sextans_7__empty_n), - .if_read(fifo_C_ch_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_Sextans_7__din), - .if_full_n(fifo_C_ch_Sextans_7__full_n), - .if_write(fifo_C_ch_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_Sextans_0__dout), - .if_empty_n(fifo_C_ch_result_Sextans_0__empty_n), - .if_read(fifo_C_ch_result_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_Sextans_0__din), - .if_full_n(fifo_C_ch_result_Sextans_0__full_n), - .if_write(fifo_C_ch_result_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_Sextans_1__dout), - .if_empty_n(fifo_C_ch_result_Sextans_1__empty_n), - .if_read(fifo_C_ch_result_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_Sextans_1__din), - .if_full_n(fifo_C_ch_result_Sextans_1__full_n), - .if_write(fifo_C_ch_result_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_Sextans_2__dout), - .if_empty_n(fifo_C_ch_result_Sextans_2__empty_n), - .if_read(fifo_C_ch_result_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_Sextans_2__din), - .if_full_n(fifo_C_ch_result_Sextans_2__full_n), - .if_write(fifo_C_ch_result_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_Sextans_3__dout), - .if_empty_n(fifo_C_ch_result_Sextans_3__empty_n), - .if_read(fifo_C_ch_result_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_Sextans_3__din), - .if_full_n(fifo_C_ch_result_Sextans_3__full_n), - .if_write(fifo_C_ch_result_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_Sextans_4__dout), - .if_empty_n(fifo_C_ch_result_Sextans_4__empty_n), - .if_read(fifo_C_ch_result_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_Sextans_4__din), - .if_full_n(fifo_C_ch_result_Sextans_4__full_n), - .if_write(fifo_C_ch_result_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_Sextans_5__dout), - .if_empty_n(fifo_C_ch_result_Sextans_5__empty_n), - .if_read(fifo_C_ch_result_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_Sextans_5__din), - .if_full_n(fifo_C_ch_result_Sextans_5__full_n), - .if_write(fifo_C_ch_result_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_Sextans_6__dout), - .if_empty_n(fifo_C_ch_result_Sextans_6__empty_n), - .if_read(fifo_C_ch_result_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_Sextans_6__din), - .if_full_n(fifo_C_ch_result_Sextans_6__full_n), - .if_write(fifo_C_ch_result_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_Sextans_7__dout), - .if_empty_n(fifo_C_ch_result_Sextans_7__empty_n), - .if_read(fifo_C_ch_result_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_Sextans_7__din), - .if_full_n(fifo_C_ch_result_Sextans_7__full_n), - .if_write(fifo_C_ch_result_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_alpha_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_alpha_Sextans_0__dout), - .if_empty_n(fifo_C_ch_result_alpha_Sextans_0__empty_n), - .if_read(fifo_C_ch_result_alpha_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_alpha_Sextans_0__din), - .if_full_n(fifo_C_ch_result_alpha_Sextans_0__full_n), - .if_write(fifo_C_ch_result_alpha_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_alpha_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_alpha_Sextans_1__dout), - .if_empty_n(fifo_C_ch_result_alpha_Sextans_1__empty_n), - .if_read(fifo_C_ch_result_alpha_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_alpha_Sextans_1__din), - .if_full_n(fifo_C_ch_result_alpha_Sextans_1__full_n), - .if_write(fifo_C_ch_result_alpha_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_alpha_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_alpha_Sextans_2__dout), - .if_empty_n(fifo_C_ch_result_alpha_Sextans_2__empty_n), - .if_read(fifo_C_ch_result_alpha_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_alpha_Sextans_2__din), - .if_full_n(fifo_C_ch_result_alpha_Sextans_2__full_n), - .if_write(fifo_C_ch_result_alpha_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_alpha_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_alpha_Sextans_3__dout), - .if_empty_n(fifo_C_ch_result_alpha_Sextans_3__empty_n), - .if_read(fifo_C_ch_result_alpha_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_alpha_Sextans_3__din), - .if_full_n(fifo_C_ch_result_alpha_Sextans_3__full_n), - .if_write(fifo_C_ch_result_alpha_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_alpha_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_alpha_Sextans_4__dout), - .if_empty_n(fifo_C_ch_result_alpha_Sextans_4__empty_n), - .if_read(fifo_C_ch_result_alpha_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_alpha_Sextans_4__din), - .if_full_n(fifo_C_ch_result_alpha_Sextans_4__full_n), - .if_write(fifo_C_ch_result_alpha_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_alpha_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_alpha_Sextans_5__dout), - .if_empty_n(fifo_C_ch_result_alpha_Sextans_5__empty_n), - .if_read(fifo_C_ch_result_alpha_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_alpha_Sextans_5__din), - .if_full_n(fifo_C_ch_result_alpha_Sextans_5__full_n), - .if_write(fifo_C_ch_result_alpha_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_alpha_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_alpha_Sextans_6__dout), - .if_empty_n(fifo_C_ch_result_alpha_Sextans_6__empty_n), - .if_read(fifo_C_ch_result_alpha_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_alpha_Sextans_6__din), - .if_full_n(fifo_C_ch_result_alpha_Sextans_6__full_n), - .if_write(fifo_C_ch_result_alpha_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_ch_result_alpha_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_ch_result_alpha_Sextans_7__dout), - .if_empty_n(fifo_C_ch_result_alpha_Sextans_7__empty_n), - .if_read(fifo_C_ch_result_alpha_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_C_ch_result_alpha_Sextans_7__din), - .if_full_n(fifo_C_ch_result_alpha_Sextans_7__full_n), - .if_write(fifo_C_ch_result_alpha_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_0__dout), - .if_empty_n(fifo_C_pe_Sextans_0__empty_n), - .if_read(fifo_C_pe_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_0__din), - .if_full_n(fifo_C_pe_Sextans_0__full_n), - .if_write(fifo_C_pe_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_10 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_10__dout), - .if_empty_n(fifo_C_pe_Sextans_10__empty_n), - .if_read(fifo_C_pe_Sextans_10__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_10__din), - .if_full_n(fifo_C_pe_Sextans_10__full_n), - .if_write(fifo_C_pe_Sextans_10__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_11 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_11__dout), - .if_empty_n(fifo_C_pe_Sextans_11__empty_n), - .if_read(fifo_C_pe_Sextans_11__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_11__din), - .if_full_n(fifo_C_pe_Sextans_11__full_n), - .if_write(fifo_C_pe_Sextans_11__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_12 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_12__dout), - .if_empty_n(fifo_C_pe_Sextans_12__empty_n), - .if_read(fifo_C_pe_Sextans_12__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_12__din), - .if_full_n(fifo_C_pe_Sextans_12__full_n), - .if_write(fifo_C_pe_Sextans_12__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_13 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_13__dout), - .if_empty_n(fifo_C_pe_Sextans_13__empty_n), - .if_read(fifo_C_pe_Sextans_13__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_13__din), - .if_full_n(fifo_C_pe_Sextans_13__full_n), - .if_write(fifo_C_pe_Sextans_13__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_14 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_14__dout), - .if_empty_n(fifo_C_pe_Sextans_14__empty_n), - .if_read(fifo_C_pe_Sextans_14__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_14__din), - .if_full_n(fifo_C_pe_Sextans_14__full_n), - .if_write(fifo_C_pe_Sextans_14__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_15 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_15__dout), - .if_empty_n(fifo_C_pe_Sextans_15__empty_n), - .if_read(fifo_C_pe_Sextans_15__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_15__din), - .if_full_n(fifo_C_pe_Sextans_15__full_n), - .if_write(fifo_C_pe_Sextans_15__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_1__dout), - .if_empty_n(fifo_C_pe_Sextans_1__empty_n), - .if_read(fifo_C_pe_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_1__din), - .if_full_n(fifo_C_pe_Sextans_1__full_n), - .if_write(fifo_C_pe_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_2__dout), - .if_empty_n(fifo_C_pe_Sextans_2__empty_n), - .if_read(fifo_C_pe_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_2__din), - .if_full_n(fifo_C_pe_Sextans_2__full_n), - .if_write(fifo_C_pe_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_3__dout), - .if_empty_n(fifo_C_pe_Sextans_3__empty_n), - .if_read(fifo_C_pe_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_3__din), - .if_full_n(fifo_C_pe_Sextans_3__full_n), - .if_write(fifo_C_pe_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_4__dout), - .if_empty_n(fifo_C_pe_Sextans_4__empty_n), - .if_read(fifo_C_pe_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_4__din), - .if_full_n(fifo_C_pe_Sextans_4__full_n), - .if_write(fifo_C_pe_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_5__dout), - .if_empty_n(fifo_C_pe_Sextans_5__empty_n), - .if_read(fifo_C_pe_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_5__din), - .if_full_n(fifo_C_pe_Sextans_5__full_n), - .if_write(fifo_C_pe_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_6__dout), - .if_empty_n(fifo_C_pe_Sextans_6__empty_n), - .if_read(fifo_C_pe_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_6__din), - .if_full_n(fifo_C_pe_Sextans_6__full_n), - .if_write(fifo_C_pe_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_7__dout), - .if_empty_n(fifo_C_pe_Sextans_7__empty_n), - .if_read(fifo_C_pe_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_7__din), - .if_full_n(fifo_C_pe_Sextans_7__full_n), - .if_write(fifo_C_pe_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_8 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_8__dout), - .if_empty_n(fifo_C_pe_Sextans_8__empty_n), - .if_read(fifo_C_pe_Sextans_8__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_8__din), - .if_full_n(fifo_C_pe_Sextans_8__full_n), - .if_write(fifo_C_pe_Sextans_8__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(257), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_pe_Sextans_9 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_pe_Sextans_9__dout), - .if_empty_n(fifo_C_pe_Sextans_9__empty_n), - .if_read(fifo_C_pe_Sextans_9__read), - .if_read_ce(1'b1), - .if_din(fifo_C_pe_Sextans_9__din), - .if_full_n(fifo_C_pe_Sextans_9__full_n), - .if_write(fifo_C_pe_Sextans_9__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_Sextans_0__dout), - .if_empty_n(fifo_C_read_in_Sextans_0__empty_n), - .if_read(fifo_C_read_in_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_Sextans_0__din), - .if_full_n(fifo_C_read_in_Sextans_0__full_n), - .if_write(fifo_C_read_in_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_Sextans_1__dout), - .if_empty_n(fifo_C_read_in_Sextans_1__empty_n), - .if_read(fifo_C_read_in_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_Sextans_1__din), - .if_full_n(fifo_C_read_in_Sextans_1__full_n), - .if_write(fifo_C_read_in_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_Sextans_2__dout), - .if_empty_n(fifo_C_read_in_Sextans_2__empty_n), - .if_read(fifo_C_read_in_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_Sextans_2__din), - .if_full_n(fifo_C_read_in_Sextans_2__full_n), - .if_write(fifo_C_read_in_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_Sextans_3__dout), - .if_empty_n(fifo_C_read_in_Sextans_3__empty_n), - .if_read(fifo_C_read_in_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_Sextans_3__din), - .if_full_n(fifo_C_read_in_Sextans_3__full_n), - .if_write(fifo_C_read_in_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_Sextans_4__dout), - .if_empty_n(fifo_C_read_in_Sextans_4__empty_n), - .if_read(fifo_C_read_in_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_Sextans_4__din), - .if_full_n(fifo_C_read_in_Sextans_4__full_n), - .if_write(fifo_C_read_in_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_Sextans_5__dout), - .if_empty_n(fifo_C_read_in_Sextans_5__empty_n), - .if_read(fifo_C_read_in_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_Sextans_5__din), - .if_full_n(fifo_C_read_in_Sextans_5__full_n), - .if_write(fifo_C_read_in_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_Sextans_6__dout), - .if_empty_n(fifo_C_read_in_Sextans_6__empty_n), - .if_read(fifo_C_read_in_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_Sextans_6__din), - .if_full_n(fifo_C_read_in_Sextans_6__full_n), - .if_write(fifo_C_read_in_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_Sextans_7__dout), - .if_empty_n(fifo_C_read_in_Sextans_7__empty_n), - .if_read(fifo_C_read_in_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_Sextans_7__din), - .if_full_n(fifo_C_read_in_Sextans_7__full_n), - .if_write(fifo_C_read_in_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_beta_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_beta_Sextans_0__dout), - .if_empty_n(fifo_C_read_in_beta_Sextans_0__empty_n), - .if_read(fifo_C_read_in_beta_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_beta_Sextans_0__din), - .if_full_n(fifo_C_read_in_beta_Sextans_0__full_n), - .if_write(fifo_C_read_in_beta_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_beta_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_beta_Sextans_1__dout), - .if_empty_n(fifo_C_read_in_beta_Sextans_1__empty_n), - .if_read(fifo_C_read_in_beta_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_beta_Sextans_1__din), - .if_full_n(fifo_C_read_in_beta_Sextans_1__full_n), - .if_write(fifo_C_read_in_beta_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_beta_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_beta_Sextans_2__dout), - .if_empty_n(fifo_C_read_in_beta_Sextans_2__empty_n), - .if_read(fifo_C_read_in_beta_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_beta_Sextans_2__din), - .if_full_n(fifo_C_read_in_beta_Sextans_2__full_n), - .if_write(fifo_C_read_in_beta_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_beta_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_beta_Sextans_3__dout), - .if_empty_n(fifo_C_read_in_beta_Sextans_3__empty_n), - .if_read(fifo_C_read_in_beta_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_beta_Sextans_3__din), - .if_full_n(fifo_C_read_in_beta_Sextans_3__full_n), - .if_write(fifo_C_read_in_beta_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_beta_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_beta_Sextans_4__dout), - .if_empty_n(fifo_C_read_in_beta_Sextans_4__empty_n), - .if_read(fifo_C_read_in_beta_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_beta_Sextans_4__din), - .if_full_n(fifo_C_read_in_beta_Sextans_4__full_n), - .if_write(fifo_C_read_in_beta_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_beta_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_beta_Sextans_5__dout), - .if_empty_n(fifo_C_read_in_beta_Sextans_5__empty_n), - .if_read(fifo_C_read_in_beta_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_beta_Sextans_5__din), - .if_full_n(fifo_C_read_in_beta_Sextans_5__full_n), - .if_write(fifo_C_read_in_beta_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_beta_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_beta_Sextans_6__dout), - .if_empty_n(fifo_C_read_in_beta_Sextans_6__empty_n), - .if_read(fifo_C_read_in_beta_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_beta_Sextans_6__din), - .if_full_n(fifo_C_read_in_beta_Sextans_6__full_n), - .if_write(fifo_C_read_in_beta_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_C_read_in_beta_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_C_read_in_beta_Sextans_7__dout), - .if_empty_n(fifo_C_read_in_beta_Sextans_7__empty_n), - .if_read(fifo_C_read_in_beta_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_C_read_in_beta_Sextans_7__din), - .if_full_n(fifo_C_read_in_beta_Sextans_7__full_n), - .if_write(fifo_C_read_in_beta_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_0__dout), - .if_empty_n(fifo_aBvec_Sextans_0__empty_n), - .if_read(fifo_aBvec_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_0__din), - .if_full_n(fifo_aBvec_Sextans_0__full_n), - .if_write(fifo_aBvec_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_10 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_10__dout), - .if_empty_n(fifo_aBvec_Sextans_10__empty_n), - .if_read(fifo_aBvec_Sextans_10__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_10__din), - .if_full_n(fifo_aBvec_Sextans_10__full_n), - .if_write(fifo_aBvec_Sextans_10__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_11 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_11__dout), - .if_empty_n(fifo_aBvec_Sextans_11__empty_n), - .if_read(fifo_aBvec_Sextans_11__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_11__din), - .if_full_n(fifo_aBvec_Sextans_11__full_n), - .if_write(fifo_aBvec_Sextans_11__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_12 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_12__dout), - .if_empty_n(fifo_aBvec_Sextans_12__empty_n), - .if_read(fifo_aBvec_Sextans_12__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_12__din), - .if_full_n(fifo_aBvec_Sextans_12__full_n), - .if_write(fifo_aBvec_Sextans_12__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_13 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_13__dout), - .if_empty_n(fifo_aBvec_Sextans_13__empty_n), - .if_read(fifo_aBvec_Sextans_13__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_13__din), - .if_full_n(fifo_aBvec_Sextans_13__full_n), - .if_write(fifo_aBvec_Sextans_13__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_14 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_14__dout), - .if_empty_n(fifo_aBvec_Sextans_14__empty_n), - .if_read(fifo_aBvec_Sextans_14__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_14__din), - .if_full_n(fifo_aBvec_Sextans_14__full_n), - .if_write(fifo_aBvec_Sextans_14__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_15 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_15__dout), - .if_empty_n(fifo_aBvec_Sextans_15__empty_n), - .if_read(fifo_aBvec_Sextans_15__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_15__din), - .if_full_n(fifo_aBvec_Sextans_15__full_n), - .if_write(fifo_aBvec_Sextans_15__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_16 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_16__dout), - .if_empty_n(fifo_aBvec_Sextans_16__empty_n), - .if_read(fifo_aBvec_Sextans_16__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_16__din), - .if_full_n(fifo_aBvec_Sextans_16__full_n), - .if_write(fifo_aBvec_Sextans_16__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_17 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_17__dout), - .if_empty_n(fifo_aBvec_Sextans_17__empty_n), - .if_read(fifo_aBvec_Sextans_17__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_17__din), - .if_full_n(fifo_aBvec_Sextans_17__full_n), - .if_write(fifo_aBvec_Sextans_17__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_18 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_18__dout), - .if_empty_n(fifo_aBvec_Sextans_18__empty_n), - .if_read(fifo_aBvec_Sextans_18__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_18__din), - .if_full_n(fifo_aBvec_Sextans_18__full_n), - .if_write(fifo_aBvec_Sextans_18__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_19 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_19__dout), - .if_empty_n(fifo_aBvec_Sextans_19__empty_n), - .if_read(fifo_aBvec_Sextans_19__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_19__din), - .if_full_n(fifo_aBvec_Sextans_19__full_n), - .if_write(fifo_aBvec_Sextans_19__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_1__dout), - .if_empty_n(fifo_aBvec_Sextans_1__empty_n), - .if_read(fifo_aBvec_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_1__din), - .if_full_n(fifo_aBvec_Sextans_1__full_n), - .if_write(fifo_aBvec_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_20 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_20__dout), - .if_empty_n(fifo_aBvec_Sextans_20__empty_n), - .if_read(fifo_aBvec_Sextans_20__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_20__din), - .if_full_n(fifo_aBvec_Sextans_20__full_n), - .if_write(fifo_aBvec_Sextans_20__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_21 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_21__dout), - .if_empty_n(fifo_aBvec_Sextans_21__empty_n), - .if_read(fifo_aBvec_Sextans_21__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_21__din), - .if_full_n(fifo_aBvec_Sextans_21__full_n), - .if_write(fifo_aBvec_Sextans_21__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_22 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_22__dout), - .if_empty_n(fifo_aBvec_Sextans_22__empty_n), - .if_read(fifo_aBvec_Sextans_22__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_22__din), - .if_full_n(fifo_aBvec_Sextans_22__full_n), - .if_write(fifo_aBvec_Sextans_22__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_23 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_23__dout), - .if_empty_n(fifo_aBvec_Sextans_23__empty_n), - .if_read(fifo_aBvec_Sextans_23__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_23__din), - .if_full_n(fifo_aBvec_Sextans_23__full_n), - .if_write(fifo_aBvec_Sextans_23__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_24 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_24__dout), - .if_empty_n(fifo_aBvec_Sextans_24__empty_n), - .if_read(fifo_aBvec_Sextans_24__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_24__din), - .if_full_n(fifo_aBvec_Sextans_24__full_n), - .if_write(fifo_aBvec_Sextans_24__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_25 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_25__dout), - .if_empty_n(fifo_aBvec_Sextans_25__empty_n), - .if_read(fifo_aBvec_Sextans_25__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_25__din), - .if_full_n(fifo_aBvec_Sextans_25__full_n), - .if_write(fifo_aBvec_Sextans_25__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_26 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_26__dout), - .if_empty_n(fifo_aBvec_Sextans_26__empty_n), - .if_read(fifo_aBvec_Sextans_26__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_26__din), - .if_full_n(fifo_aBvec_Sextans_26__full_n), - .if_write(fifo_aBvec_Sextans_26__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_27 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_27__dout), - .if_empty_n(fifo_aBvec_Sextans_27__empty_n), - .if_read(fifo_aBvec_Sextans_27__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_27__din), - .if_full_n(fifo_aBvec_Sextans_27__full_n), - .if_write(fifo_aBvec_Sextans_27__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_28 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_28__dout), - .if_empty_n(fifo_aBvec_Sextans_28__empty_n), - .if_read(fifo_aBvec_Sextans_28__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_28__din), - .if_full_n(fifo_aBvec_Sextans_28__full_n), - .if_write(fifo_aBvec_Sextans_28__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_29 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_29__dout), - .if_empty_n(fifo_aBvec_Sextans_29__empty_n), - .if_read(fifo_aBvec_Sextans_29__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_29__din), - .if_full_n(fifo_aBvec_Sextans_29__full_n), - .if_write(fifo_aBvec_Sextans_29__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_2__dout), - .if_empty_n(fifo_aBvec_Sextans_2__empty_n), - .if_read(fifo_aBvec_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_2__din), - .if_full_n(fifo_aBvec_Sextans_2__full_n), - .if_write(fifo_aBvec_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_30 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_30__dout), - .if_empty_n(fifo_aBvec_Sextans_30__empty_n), - .if_read(fifo_aBvec_Sextans_30__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_30__din), - .if_full_n(fifo_aBvec_Sextans_30__full_n), - .if_write(fifo_aBvec_Sextans_30__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_31 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_31__dout), - .if_empty_n(fifo_aBvec_Sextans_31__empty_n), - .if_read(fifo_aBvec_Sextans_31__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_31__din), - .if_full_n(fifo_aBvec_Sextans_31__full_n), - .if_write(fifo_aBvec_Sextans_31__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_32 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_32__dout), - .if_empty_n(fifo_aBvec_Sextans_32__empty_n), - .if_read(fifo_aBvec_Sextans_32__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_32__din), - .if_full_n(fifo_aBvec_Sextans_32__full_n), - .if_write(fifo_aBvec_Sextans_32__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_33 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_33__dout), - .if_empty_n(fifo_aBvec_Sextans_33__empty_n), - .if_read(fifo_aBvec_Sextans_33__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_33__din), - .if_full_n(fifo_aBvec_Sextans_33__full_n), - .if_write(fifo_aBvec_Sextans_33__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_34 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_34__dout), - .if_empty_n(fifo_aBvec_Sextans_34__empty_n), - .if_read(fifo_aBvec_Sextans_34__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_34__din), - .if_full_n(fifo_aBvec_Sextans_34__full_n), - .if_write(fifo_aBvec_Sextans_34__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_35 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_35__dout), - .if_empty_n(fifo_aBvec_Sextans_35__empty_n), - .if_read(fifo_aBvec_Sextans_35__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_35__din), - .if_full_n(fifo_aBvec_Sextans_35__full_n), - .if_write(fifo_aBvec_Sextans_35__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_36 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_36__dout), - .if_empty_n(fifo_aBvec_Sextans_36__empty_n), - .if_read(fifo_aBvec_Sextans_36__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_36__din), - .if_full_n(fifo_aBvec_Sextans_36__full_n), - .if_write(fifo_aBvec_Sextans_36__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_37 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_37__dout), - .if_empty_n(fifo_aBvec_Sextans_37__empty_n), - .if_read(fifo_aBvec_Sextans_37__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_37__din), - .if_full_n(fifo_aBvec_Sextans_37__full_n), - .if_write(fifo_aBvec_Sextans_37__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_38 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_38__dout), - .if_empty_n(fifo_aBvec_Sextans_38__empty_n), - .if_read(fifo_aBvec_Sextans_38__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_38__din), - .if_full_n(fifo_aBvec_Sextans_38__full_n), - .if_write(fifo_aBvec_Sextans_38__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_39 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_39__dout), - .if_empty_n(fifo_aBvec_Sextans_39__empty_n), - .if_read(fifo_aBvec_Sextans_39__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_39__din), - .if_full_n(fifo_aBvec_Sextans_39__full_n), - .if_write(fifo_aBvec_Sextans_39__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_3__dout), - .if_empty_n(fifo_aBvec_Sextans_3__empty_n), - .if_read(fifo_aBvec_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_3__din), - .if_full_n(fifo_aBvec_Sextans_3__full_n), - .if_write(fifo_aBvec_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_40 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_40__dout), - .if_empty_n(fifo_aBvec_Sextans_40__empty_n), - .if_read(fifo_aBvec_Sextans_40__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_40__din), - .if_full_n(fifo_aBvec_Sextans_40__full_n), - .if_write(fifo_aBvec_Sextans_40__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_41 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_41__dout), - .if_empty_n(fifo_aBvec_Sextans_41__empty_n), - .if_read(fifo_aBvec_Sextans_41__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_41__din), - .if_full_n(fifo_aBvec_Sextans_41__full_n), - .if_write(fifo_aBvec_Sextans_41__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_42 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_42__dout), - .if_empty_n(fifo_aBvec_Sextans_42__empty_n), - .if_read(fifo_aBvec_Sextans_42__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_42__din), - .if_full_n(fifo_aBvec_Sextans_42__full_n), - .if_write(fifo_aBvec_Sextans_42__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_43 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_43__dout), - .if_empty_n(fifo_aBvec_Sextans_43__empty_n), - .if_read(fifo_aBvec_Sextans_43__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_43__din), - .if_full_n(fifo_aBvec_Sextans_43__full_n), - .if_write(fifo_aBvec_Sextans_43__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_44 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_44__dout), - .if_empty_n(fifo_aBvec_Sextans_44__empty_n), - .if_read(fifo_aBvec_Sextans_44__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_44__din), - .if_full_n(fifo_aBvec_Sextans_44__full_n), - .if_write(fifo_aBvec_Sextans_44__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_45 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_45__dout), - .if_empty_n(fifo_aBvec_Sextans_45__empty_n), - .if_read(fifo_aBvec_Sextans_45__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_45__din), - .if_full_n(fifo_aBvec_Sextans_45__full_n), - .if_write(fifo_aBvec_Sextans_45__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_46 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_46__dout), - .if_empty_n(fifo_aBvec_Sextans_46__empty_n), - .if_read(fifo_aBvec_Sextans_46__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_46__din), - .if_full_n(fifo_aBvec_Sextans_46__full_n), - .if_write(fifo_aBvec_Sextans_46__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_47 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_47__dout), - .if_empty_n(fifo_aBvec_Sextans_47__empty_n), - .if_read(fifo_aBvec_Sextans_47__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_47__din), - .if_full_n(fifo_aBvec_Sextans_47__full_n), - .if_write(fifo_aBvec_Sextans_47__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_48 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_48__dout), - .if_empty_n(fifo_aBvec_Sextans_48__empty_n), - .if_read(fifo_aBvec_Sextans_48__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_48__din), - .if_full_n(fifo_aBvec_Sextans_48__full_n), - .if_write(fifo_aBvec_Sextans_48__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_49 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_49__dout), - .if_empty_n(fifo_aBvec_Sextans_49__empty_n), - .if_read(fifo_aBvec_Sextans_49__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_49__din), - .if_full_n(fifo_aBvec_Sextans_49__full_n), - .if_write(fifo_aBvec_Sextans_49__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_4__dout), - .if_empty_n(fifo_aBvec_Sextans_4__empty_n), - .if_read(fifo_aBvec_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_4__din), - .if_full_n(fifo_aBvec_Sextans_4__full_n), - .if_write(fifo_aBvec_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_50 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_50__dout), - .if_empty_n(fifo_aBvec_Sextans_50__empty_n), - .if_read(fifo_aBvec_Sextans_50__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_50__din), - .if_full_n(fifo_aBvec_Sextans_50__full_n), - .if_write(fifo_aBvec_Sextans_50__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_51 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_51__dout), - .if_empty_n(fifo_aBvec_Sextans_51__empty_n), - .if_read(fifo_aBvec_Sextans_51__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_51__din), - .if_full_n(fifo_aBvec_Sextans_51__full_n), - .if_write(fifo_aBvec_Sextans_51__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_52 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_52__dout), - .if_empty_n(fifo_aBvec_Sextans_52__empty_n), - .if_read(fifo_aBvec_Sextans_52__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_52__din), - .if_full_n(fifo_aBvec_Sextans_52__full_n), - .if_write(fifo_aBvec_Sextans_52__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_53 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_53__dout), - .if_empty_n(fifo_aBvec_Sextans_53__empty_n), - .if_read(fifo_aBvec_Sextans_53__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_53__din), - .if_full_n(fifo_aBvec_Sextans_53__full_n), - .if_write(fifo_aBvec_Sextans_53__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_54 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_54__dout), - .if_empty_n(fifo_aBvec_Sextans_54__empty_n), - .if_read(fifo_aBvec_Sextans_54__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_54__din), - .if_full_n(fifo_aBvec_Sextans_54__full_n), - .if_write(fifo_aBvec_Sextans_54__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_55 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_55__dout), - .if_empty_n(fifo_aBvec_Sextans_55__empty_n), - .if_read(fifo_aBvec_Sextans_55__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_55__din), - .if_full_n(fifo_aBvec_Sextans_55__full_n), - .if_write(fifo_aBvec_Sextans_55__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_56 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_56__dout), - .if_empty_n(fifo_aBvec_Sextans_56__empty_n), - .if_read(fifo_aBvec_Sextans_56__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_56__din), - .if_full_n(fifo_aBvec_Sextans_56__full_n), - .if_write(fifo_aBvec_Sextans_56__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_57 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_57__dout), - .if_empty_n(fifo_aBvec_Sextans_57__empty_n), - .if_read(fifo_aBvec_Sextans_57__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_57__din), - .if_full_n(fifo_aBvec_Sextans_57__full_n), - .if_write(fifo_aBvec_Sextans_57__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_58 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_58__dout), - .if_empty_n(fifo_aBvec_Sextans_58__empty_n), - .if_read(fifo_aBvec_Sextans_58__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_58__din), - .if_full_n(fifo_aBvec_Sextans_58__full_n), - .if_write(fifo_aBvec_Sextans_58__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_59 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_59__dout), - .if_empty_n(fifo_aBvec_Sextans_59__empty_n), - .if_read(fifo_aBvec_Sextans_59__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_59__din), - .if_full_n(fifo_aBvec_Sextans_59__full_n), - .if_write(fifo_aBvec_Sextans_59__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_5__dout), - .if_empty_n(fifo_aBvec_Sextans_5__empty_n), - .if_read(fifo_aBvec_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_5__din), - .if_full_n(fifo_aBvec_Sextans_5__full_n), - .if_write(fifo_aBvec_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_60 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_60__dout), - .if_empty_n(fifo_aBvec_Sextans_60__empty_n), - .if_read(fifo_aBvec_Sextans_60__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_60__din), - .if_full_n(fifo_aBvec_Sextans_60__full_n), - .if_write(fifo_aBvec_Sextans_60__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_61 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_61__dout), - .if_empty_n(fifo_aBvec_Sextans_61__empty_n), - .if_read(fifo_aBvec_Sextans_61__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_61__din), - .if_full_n(fifo_aBvec_Sextans_61__full_n), - .if_write(fifo_aBvec_Sextans_61__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_62 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_62__dout), - .if_empty_n(fifo_aBvec_Sextans_62__empty_n), - .if_read(fifo_aBvec_Sextans_62__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_62__din), - .if_full_n(fifo_aBvec_Sextans_62__full_n), - .if_write(fifo_aBvec_Sextans_62__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_63 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_63__dout), - .if_empty_n(fifo_aBvec_Sextans_63__empty_n), - .if_read(fifo_aBvec_Sextans_63__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_63__din), - .if_full_n(fifo_aBvec_Sextans_63__full_n), - .if_write(fifo_aBvec_Sextans_63__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_6__dout), - .if_empty_n(fifo_aBvec_Sextans_6__empty_n), - .if_read(fifo_aBvec_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_6__din), - .if_full_n(fifo_aBvec_Sextans_6__full_n), - .if_write(fifo_aBvec_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_7__dout), - .if_empty_n(fifo_aBvec_Sextans_7__empty_n), - .if_read(fifo_aBvec_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_7__din), - .if_full_n(fifo_aBvec_Sextans_7__full_n), - .if_write(fifo_aBvec_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_8 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_8__dout), - .if_empty_n(fifo_aBvec_Sextans_8__empty_n), - .if_read(fifo_aBvec_Sextans_8__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_8__din), - .if_full_n(fifo_aBvec_Sextans_8__full_n), - .if_write(fifo_aBvec_Sextans_8__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(275), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_aBvec_Sextans_9 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_aBvec_Sextans_9__dout), - .if_empty_n(fifo_aBvec_Sextans_9__empty_n), - .if_read(fifo_aBvec_Sextans_9__read), - .if_read_ce(1'b1), - .if_din(fifo_aBvec_Sextans_9__din), - .if_full_n(fifo_aBvec_Sextans_9__full_n), - .if_write(fifo_aBvec_Sextans_9__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_0__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_0__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_0__din), - .if_full_n(fifo_edge_list_ptr_Sextans_0__full_n), - .if_write(fifo_edge_list_ptr_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_10 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_10__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_10__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_10__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_10__din), - .if_full_n(fifo_edge_list_ptr_Sextans_10__full_n), - .if_write(fifo_edge_list_ptr_Sextans_10__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_11 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_11__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_11__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_11__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_11__din), - .if_full_n(fifo_edge_list_ptr_Sextans_11__full_n), - .if_write(fifo_edge_list_ptr_Sextans_11__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_12 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_12__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_12__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_12__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_12__din), - .if_full_n(fifo_edge_list_ptr_Sextans_12__full_n), - .if_write(fifo_edge_list_ptr_Sextans_12__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_13 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_13__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_13__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_13__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_13__din), - .if_full_n(fifo_edge_list_ptr_Sextans_13__full_n), - .if_write(fifo_edge_list_ptr_Sextans_13__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_14 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_14__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_14__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_14__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_14__din), - .if_full_n(fifo_edge_list_ptr_Sextans_14__full_n), - .if_write(fifo_edge_list_ptr_Sextans_14__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_15 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_15__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_15__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_15__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_15__din), - .if_full_n(fifo_edge_list_ptr_Sextans_15__full_n), - .if_write(fifo_edge_list_ptr_Sextans_15__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_16 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_16__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_16__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_16__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_16__din), - .if_full_n(fifo_edge_list_ptr_Sextans_16__full_n), - .if_write(fifo_edge_list_ptr_Sextans_16__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_1__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_1__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_1__din), - .if_full_n(fifo_edge_list_ptr_Sextans_1__full_n), - .if_write(fifo_edge_list_ptr_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_2__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_2__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_2__din), - .if_full_n(fifo_edge_list_ptr_Sextans_2__full_n), - .if_write(fifo_edge_list_ptr_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_3__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_3__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_3__din), - .if_full_n(fifo_edge_list_ptr_Sextans_3__full_n), - .if_write(fifo_edge_list_ptr_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_4__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_4__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_4__din), - .if_full_n(fifo_edge_list_ptr_Sextans_4__full_n), - .if_write(fifo_edge_list_ptr_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_5__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_5__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_5__din), - .if_full_n(fifo_edge_list_ptr_Sextans_5__full_n), - .if_write(fifo_edge_list_ptr_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_6__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_6__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_6__din), - .if_full_n(fifo_edge_list_ptr_Sextans_6__full_n), - .if_write(fifo_edge_list_ptr_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_7__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_7__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_7__din), - .if_full_n(fifo_edge_list_ptr_Sextans_7__full_n), - .if_write(fifo_edge_list_ptr_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_8 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_8__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_8__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_8__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_8__din), - .if_full_n(fifo_edge_list_ptr_Sextans_8__full_n), - .if_write(fifo_edge_list_ptr_Sextans_8__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_Sextans_9 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_Sextans_9__dout), - .if_empty_n(fifo_edge_list_ptr_Sextans_9__empty_n), - .if_read(fifo_edge_list_ptr_Sextans_9__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_Sextans_9__din), - .if_full_n(fifo_edge_list_ptr_Sextans_9__full_n), - .if_write(fifo_edge_list_ptr_Sextans_9__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_0__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_0__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_0__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_0__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_10 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_10__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_10__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_10__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_10__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_10__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_10__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_11 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_11__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_11__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_11__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_11__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_11__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_11__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_12 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_12__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_12__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_12__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_12__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_12__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_12__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_13 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_13__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_13__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_13__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_13__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_13__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_13__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_14 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_14__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_14__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_14__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_14__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_14__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_14__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_15 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_15__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_15__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_15__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_15__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_15__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_15__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_1__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_1__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_1__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_1__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_2__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_2__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_2__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_2__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_3__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_3__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_3__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_3__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_4__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_4__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_4__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_4__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_5__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_5__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_5__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_5__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_6__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_6__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_6__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_6__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_7__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_7__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_7__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_7__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_8 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_8__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_8__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_8__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_8__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_8__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_8__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - fifo_edge_list_ptr_to_Cmtx_Sextans_9 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_9__dout), - .if_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_9__empty_n), - .if_read(fifo_edge_list_ptr_to_Cmtx_Sextans_9__read), - .if_read_ce(1'b1), - .if_din(fifo_edge_list_ptr_to_Cmtx_Sextans_9__din), - .if_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_9__full_n), - .if_write(fifo_edge_list_ptr_to_Cmtx_Sextans_9__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - wrC_inst_Sextans_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(wrC_inst_Sextans_0__dout), - .if_empty_n(wrC_inst_Sextans_0__empty_n), - .if_read(wrC_inst_Sextans_0__read), - .if_read_ce(1'b1), - .if_din(wrC_inst_Sextans_0__din), - .if_full_n(wrC_inst_Sextans_0__full_n), - .if_write(wrC_inst_Sextans_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - wrC_inst_Sextans_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(wrC_inst_Sextans_1__dout), - .if_empty_n(wrC_inst_Sextans_1__empty_n), - .if_read(wrC_inst_Sextans_1__read), - .if_read_ce(1'b1), - .if_din(wrC_inst_Sextans_1__din), - .if_full_n(wrC_inst_Sextans_1__full_n), - .if_write(wrC_inst_Sextans_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - wrC_inst_Sextans_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(wrC_inst_Sextans_2__dout), - .if_empty_n(wrC_inst_Sextans_2__empty_n), - .if_read(wrC_inst_Sextans_2__read), - .if_read_ce(1'b1), - .if_din(wrC_inst_Sextans_2__din), - .if_full_n(wrC_inst_Sextans_2__full_n), - .if_write(wrC_inst_Sextans_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - wrC_inst_Sextans_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(wrC_inst_Sextans_3__dout), - .if_empty_n(wrC_inst_Sextans_3__empty_n), - .if_read(wrC_inst_Sextans_3__read), - .if_read_ce(1'b1), - .if_din(wrC_inst_Sextans_3__din), - .if_full_n(wrC_inst_Sextans_3__full_n), - .if_write(wrC_inst_Sextans_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - wrC_inst_Sextans_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(wrC_inst_Sextans_4__dout), - .if_empty_n(wrC_inst_Sextans_4__empty_n), - .if_read(wrC_inst_Sextans_4__read), - .if_read_ce(1'b1), - .if_din(wrC_inst_Sextans_4__din), - .if_full_n(wrC_inst_Sextans_4__full_n), - .if_write(wrC_inst_Sextans_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - wrC_inst_Sextans_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(wrC_inst_Sextans_5__dout), - .if_empty_n(wrC_inst_Sextans_5__empty_n), - .if_read(wrC_inst_Sextans_5__read), - .if_read_ce(1'b1), - .if_din(wrC_inst_Sextans_5__din), - .if_full_n(wrC_inst_Sextans_5__full_n), - .if_write(wrC_inst_Sextans_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - wrC_inst_Sextans_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(wrC_inst_Sextans_6__dout), - .if_empty_n(wrC_inst_Sextans_6__empty_n), - .if_read(wrC_inst_Sextans_6__read), - .if_read_ce(1'b1), - .if_din(wrC_inst_Sextans_6__din), - .if_full_n(wrC_inst_Sextans_6__full_n), - .if_write(wrC_inst_Sextans_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(33), - .ADDR_WIDTH(1), - .DEPTH(2) - ) - wrC_inst_Sextans_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(wrC_inst_Sextans_7__dout), - .if_empty_n(wrC_inst_Sextans_7__empty_n), - .if_read(wrC_inst_Sextans_7__read), - .if_read_ce(1'b1), - .if_din(wrC_inst_Sextans_7__din), - .if_full_n(wrC_inst_Sextans_7__full_n), - .if_write(wrC_inst_Sextans_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) FloatvAddFloatv - FloatvAddFloatv_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvAddFloatv_0__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_Sextans_0__din), - .fifo_out_full_n(fifo_C_ch_Sextans_0__full_n), - .fifo_out_write(fifo_C_ch_Sextans_0__write), - .fifo_in0_s_dout(fifo_C_ch_result_alpha_Sextans_0__dout), - .fifo_in0_peek_dout(fifo_C_ch_result_alpha_Sextans_0__dout), - .fifo_in0_s_empty_n(fifo_C_ch_result_alpha_Sextans_0__empty_n), - .fifo_in0_peek_empty_n(fifo_C_ch_result_alpha_Sextans_0__empty_n), - .fifo_in0_s_read(fifo_C_ch_result_alpha_Sextans_0__read), - .fifo_in0_peek_read(), - .fifo_in1_s_dout(fifo_C_read_in_beta_Sextans_0__dout), - .fifo_in1_peek_dout(fifo_C_read_in_beta_Sextans_0__dout), - .fifo_in1_s_empty_n(fifo_C_read_in_beta_Sextans_0__empty_n), - .fifo_in1_peek_empty_n(fifo_C_read_in_beta_Sextans_0__empty_n), - .fifo_in1_s_read(fifo_C_read_in_beta_Sextans_0__read), - .fifo_in1_peek_read() - ); - - - (* keep_hierarchy = "yes" *) FloatvAddFloatv - FloatvAddFloatv_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvAddFloatv_1__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_Sextans_1__din), - .fifo_out_full_n(fifo_C_ch_Sextans_1__full_n), - .fifo_out_write(fifo_C_ch_Sextans_1__write), - .fifo_in0_s_dout(fifo_C_ch_result_alpha_Sextans_1__dout), - .fifo_in0_peek_dout(fifo_C_ch_result_alpha_Sextans_1__dout), - .fifo_in0_s_empty_n(fifo_C_ch_result_alpha_Sextans_1__empty_n), - .fifo_in0_peek_empty_n(fifo_C_ch_result_alpha_Sextans_1__empty_n), - .fifo_in0_s_read(fifo_C_ch_result_alpha_Sextans_1__read), - .fifo_in0_peek_read(), - .fifo_in1_s_dout(fifo_C_read_in_beta_Sextans_1__dout), - .fifo_in1_peek_dout(fifo_C_read_in_beta_Sextans_1__dout), - .fifo_in1_s_empty_n(fifo_C_read_in_beta_Sextans_1__empty_n), - .fifo_in1_peek_empty_n(fifo_C_read_in_beta_Sextans_1__empty_n), - .fifo_in1_s_read(fifo_C_read_in_beta_Sextans_1__read), - .fifo_in1_peek_read() - ); - - - (* keep_hierarchy = "yes" *) FloatvAddFloatv - FloatvAddFloatv_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvAddFloatv_2__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_Sextans_2__din), - .fifo_out_full_n(fifo_C_ch_Sextans_2__full_n), - .fifo_out_write(fifo_C_ch_Sextans_2__write), - .fifo_in0_s_dout(fifo_C_ch_result_alpha_Sextans_2__dout), - .fifo_in0_peek_dout(fifo_C_ch_result_alpha_Sextans_2__dout), - .fifo_in0_s_empty_n(fifo_C_ch_result_alpha_Sextans_2__empty_n), - .fifo_in0_peek_empty_n(fifo_C_ch_result_alpha_Sextans_2__empty_n), - .fifo_in0_s_read(fifo_C_ch_result_alpha_Sextans_2__read), - .fifo_in0_peek_read(), - .fifo_in1_s_dout(fifo_C_read_in_beta_Sextans_2__dout), - .fifo_in1_peek_dout(fifo_C_read_in_beta_Sextans_2__dout), - .fifo_in1_s_empty_n(fifo_C_read_in_beta_Sextans_2__empty_n), - .fifo_in1_peek_empty_n(fifo_C_read_in_beta_Sextans_2__empty_n), - .fifo_in1_s_read(fifo_C_read_in_beta_Sextans_2__read), - .fifo_in1_peek_read() - ); - - - (* keep_hierarchy = "yes" *) FloatvAddFloatv - FloatvAddFloatv_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvAddFloatv_3__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_Sextans_3__din), - .fifo_out_full_n(fifo_C_ch_Sextans_3__full_n), - .fifo_out_write(fifo_C_ch_Sextans_3__write), - .fifo_in0_s_dout(fifo_C_ch_result_alpha_Sextans_3__dout), - .fifo_in0_peek_dout(fifo_C_ch_result_alpha_Sextans_3__dout), - .fifo_in0_s_empty_n(fifo_C_ch_result_alpha_Sextans_3__empty_n), - .fifo_in0_peek_empty_n(fifo_C_ch_result_alpha_Sextans_3__empty_n), - .fifo_in0_s_read(fifo_C_ch_result_alpha_Sextans_3__read), - .fifo_in0_peek_read(), - .fifo_in1_s_dout(fifo_C_read_in_beta_Sextans_3__dout), - .fifo_in1_peek_dout(fifo_C_read_in_beta_Sextans_3__dout), - .fifo_in1_s_empty_n(fifo_C_read_in_beta_Sextans_3__empty_n), - .fifo_in1_peek_empty_n(fifo_C_read_in_beta_Sextans_3__empty_n), - .fifo_in1_s_read(fifo_C_read_in_beta_Sextans_3__read), - .fifo_in1_peek_read() - ); - - - (* keep_hierarchy = "yes" *) FloatvAddFloatv - FloatvAddFloatv_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvAddFloatv_4__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_Sextans_4__din), - .fifo_out_full_n(fifo_C_ch_Sextans_4__full_n), - .fifo_out_write(fifo_C_ch_Sextans_4__write), - .fifo_in0_s_dout(fifo_C_ch_result_alpha_Sextans_4__dout), - .fifo_in0_peek_dout(fifo_C_ch_result_alpha_Sextans_4__dout), - .fifo_in0_s_empty_n(fifo_C_ch_result_alpha_Sextans_4__empty_n), - .fifo_in0_peek_empty_n(fifo_C_ch_result_alpha_Sextans_4__empty_n), - .fifo_in0_s_read(fifo_C_ch_result_alpha_Sextans_4__read), - .fifo_in0_peek_read(), - .fifo_in1_s_dout(fifo_C_read_in_beta_Sextans_4__dout), - .fifo_in1_peek_dout(fifo_C_read_in_beta_Sextans_4__dout), - .fifo_in1_s_empty_n(fifo_C_read_in_beta_Sextans_4__empty_n), - .fifo_in1_peek_empty_n(fifo_C_read_in_beta_Sextans_4__empty_n), - .fifo_in1_s_read(fifo_C_read_in_beta_Sextans_4__read), - .fifo_in1_peek_read() - ); - - - (* keep_hierarchy = "yes" *) FloatvAddFloatv - FloatvAddFloatv_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvAddFloatv_5__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_Sextans_5__din), - .fifo_out_full_n(fifo_C_ch_Sextans_5__full_n), - .fifo_out_write(fifo_C_ch_Sextans_5__write), - .fifo_in0_s_dout(fifo_C_ch_result_alpha_Sextans_5__dout), - .fifo_in0_peek_dout(fifo_C_ch_result_alpha_Sextans_5__dout), - .fifo_in0_s_empty_n(fifo_C_ch_result_alpha_Sextans_5__empty_n), - .fifo_in0_peek_empty_n(fifo_C_ch_result_alpha_Sextans_5__empty_n), - .fifo_in0_s_read(fifo_C_ch_result_alpha_Sextans_5__read), - .fifo_in0_peek_read(), - .fifo_in1_s_dout(fifo_C_read_in_beta_Sextans_5__dout), - .fifo_in1_peek_dout(fifo_C_read_in_beta_Sextans_5__dout), - .fifo_in1_s_empty_n(fifo_C_read_in_beta_Sextans_5__empty_n), - .fifo_in1_peek_empty_n(fifo_C_read_in_beta_Sextans_5__empty_n), - .fifo_in1_s_read(fifo_C_read_in_beta_Sextans_5__read), - .fifo_in1_peek_read() - ); - - - (* keep_hierarchy = "yes" *) FloatvAddFloatv - FloatvAddFloatv_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvAddFloatv_6__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_Sextans_6__din), - .fifo_out_full_n(fifo_C_ch_Sextans_6__full_n), - .fifo_out_write(fifo_C_ch_Sextans_6__write), - .fifo_in0_s_dout(fifo_C_ch_result_alpha_Sextans_6__dout), - .fifo_in0_peek_dout(fifo_C_ch_result_alpha_Sextans_6__dout), - .fifo_in0_s_empty_n(fifo_C_ch_result_alpha_Sextans_6__empty_n), - .fifo_in0_peek_empty_n(fifo_C_ch_result_alpha_Sextans_6__empty_n), - .fifo_in0_s_read(fifo_C_ch_result_alpha_Sextans_6__read), - .fifo_in0_peek_read(), - .fifo_in1_s_dout(fifo_C_read_in_beta_Sextans_6__dout), - .fifo_in1_peek_dout(fifo_C_read_in_beta_Sextans_6__dout), - .fifo_in1_s_empty_n(fifo_C_read_in_beta_Sextans_6__empty_n), - .fifo_in1_peek_empty_n(fifo_C_read_in_beta_Sextans_6__empty_n), - .fifo_in1_s_read(fifo_C_read_in_beta_Sextans_6__read), - .fifo_in1_peek_read() - ); - - - (* keep_hierarchy = "yes" *) FloatvAddFloatv - FloatvAddFloatv_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvAddFloatv_7__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_Sextans_7__din), - .fifo_out_full_n(fifo_C_ch_Sextans_7__full_n), - .fifo_out_write(fifo_C_ch_Sextans_7__write), - .fifo_in0_s_dout(fifo_C_ch_result_alpha_Sextans_7__dout), - .fifo_in0_peek_dout(fifo_C_ch_result_alpha_Sextans_7__dout), - .fifo_in0_s_empty_n(fifo_C_ch_result_alpha_Sextans_7__empty_n), - .fifo_in0_peek_empty_n(fifo_C_ch_result_alpha_Sextans_7__empty_n), - .fifo_in0_s_read(fifo_C_ch_result_alpha_Sextans_7__read), - .fifo_in0_peek_read(), - .fifo_in1_s_dout(fifo_C_read_in_beta_Sextans_7__dout), - .fifo_in1_peek_dout(fifo_C_read_in_beta_Sextans_7__dout), - .fifo_in1_s_empty_n(fifo_C_read_in_beta_Sextans_7__empty_n), - .fifo_in1_peek_empty_n(fifo_C_read_in_beta_Sextans_7__empty_n), - .fifo_in1_s_read(fifo_C_read_in_beta_Sextans_7__read), - .fifo_in1_peek_read() - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_0__ap_start), - .ap_done(FloatvMultConst_0__ap_done), - .ap_idle(FloatvMultConst_0__ap_idle), - .ap_ready(FloatvMultConst_0__ap_ready), - .M(FloatvMultConst_0___M__q0), - .P_N(FloatvMultConst_0___P_N__q0), - .alpha_u(FloatvMultConst_0___beta_u__q0), - .fifo_in_s_dout(fifo_C_read_in_Sextans_0__dout), - .fifo_in_peek_dout(fifo_C_read_in_Sextans_0__dout), - .fifo_in_s_empty_n(fifo_C_read_in_Sextans_0__empty_n), - .fifo_in_peek_empty_n(fifo_C_read_in_Sextans_0__empty_n), - .fifo_in_s_read(fifo_C_read_in_Sextans_0__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_read_in_beta_Sextans_0__din), - .fifo_out_full_n(fifo_C_read_in_beta_Sextans_0__full_n), - .fifo_out_write(fifo_C_read_in_beta_Sextans_0__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_1__ap_start), - .ap_done(FloatvMultConst_1__ap_done), - .ap_idle(FloatvMultConst_1__ap_idle), - .ap_ready(FloatvMultConst_1__ap_ready), - .M(FloatvMultConst_1___M__q0), - .P_N(FloatvMultConst_1___P_N__q0), - .alpha_u(FloatvMultConst_1___beta_u__q0), - .fifo_in_s_dout(fifo_C_read_in_Sextans_1__dout), - .fifo_in_peek_dout(fifo_C_read_in_Sextans_1__dout), - .fifo_in_s_empty_n(fifo_C_read_in_Sextans_1__empty_n), - .fifo_in_peek_empty_n(fifo_C_read_in_Sextans_1__empty_n), - .fifo_in_s_read(fifo_C_read_in_Sextans_1__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_read_in_beta_Sextans_1__din), - .fifo_out_full_n(fifo_C_read_in_beta_Sextans_1__full_n), - .fifo_out_write(fifo_C_read_in_beta_Sextans_1__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_2__ap_start), - .ap_done(FloatvMultConst_2__ap_done), - .ap_idle(FloatvMultConst_2__ap_idle), - .ap_ready(FloatvMultConst_2__ap_ready), - .M(FloatvMultConst_2___M__q0), - .P_N(FloatvMultConst_2___P_N__q0), - .alpha_u(FloatvMultConst_2___beta_u__q0), - .fifo_in_s_dout(fifo_C_read_in_Sextans_2__dout), - .fifo_in_peek_dout(fifo_C_read_in_Sextans_2__dout), - .fifo_in_s_empty_n(fifo_C_read_in_Sextans_2__empty_n), - .fifo_in_peek_empty_n(fifo_C_read_in_Sextans_2__empty_n), - .fifo_in_s_read(fifo_C_read_in_Sextans_2__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_read_in_beta_Sextans_2__din), - .fifo_out_full_n(fifo_C_read_in_beta_Sextans_2__full_n), - .fifo_out_write(fifo_C_read_in_beta_Sextans_2__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_3__ap_start), - .ap_done(FloatvMultConst_3__ap_done), - .ap_idle(FloatvMultConst_3__ap_idle), - .ap_ready(FloatvMultConst_3__ap_ready), - .M(FloatvMultConst_3___M__q0), - .P_N(FloatvMultConst_3___P_N__q0), - .alpha_u(FloatvMultConst_3___beta_u__q0), - .fifo_in_s_dout(fifo_C_read_in_Sextans_3__dout), - .fifo_in_peek_dout(fifo_C_read_in_Sextans_3__dout), - .fifo_in_s_empty_n(fifo_C_read_in_Sextans_3__empty_n), - .fifo_in_peek_empty_n(fifo_C_read_in_Sextans_3__empty_n), - .fifo_in_s_read(fifo_C_read_in_Sextans_3__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_read_in_beta_Sextans_3__din), - .fifo_out_full_n(fifo_C_read_in_beta_Sextans_3__full_n), - .fifo_out_write(fifo_C_read_in_beta_Sextans_3__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_4__ap_start), - .ap_done(FloatvMultConst_4__ap_done), - .ap_idle(FloatvMultConst_4__ap_idle), - .ap_ready(FloatvMultConst_4__ap_ready), - .M(FloatvMultConst_4___M__q0), - .P_N(FloatvMultConst_4___P_N__q0), - .alpha_u(FloatvMultConst_4___beta_u__q0), - .fifo_in_s_dout(fifo_C_read_in_Sextans_4__dout), - .fifo_in_peek_dout(fifo_C_read_in_Sextans_4__dout), - .fifo_in_s_empty_n(fifo_C_read_in_Sextans_4__empty_n), - .fifo_in_peek_empty_n(fifo_C_read_in_Sextans_4__empty_n), - .fifo_in_s_read(fifo_C_read_in_Sextans_4__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_read_in_beta_Sextans_4__din), - .fifo_out_full_n(fifo_C_read_in_beta_Sextans_4__full_n), - .fifo_out_write(fifo_C_read_in_beta_Sextans_4__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_5__ap_start), - .ap_done(FloatvMultConst_5__ap_done), - .ap_idle(FloatvMultConst_5__ap_idle), - .ap_ready(FloatvMultConst_5__ap_ready), - .M(FloatvMultConst_5___M__q0), - .P_N(FloatvMultConst_5___P_N__q0), - .alpha_u(FloatvMultConst_5___beta_u__q0), - .fifo_in_s_dout(fifo_C_read_in_Sextans_5__dout), - .fifo_in_peek_dout(fifo_C_read_in_Sextans_5__dout), - .fifo_in_s_empty_n(fifo_C_read_in_Sextans_5__empty_n), - .fifo_in_peek_empty_n(fifo_C_read_in_Sextans_5__empty_n), - .fifo_in_s_read(fifo_C_read_in_Sextans_5__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_read_in_beta_Sextans_5__din), - .fifo_out_full_n(fifo_C_read_in_beta_Sextans_5__full_n), - .fifo_out_write(fifo_C_read_in_beta_Sextans_5__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_6__ap_start), - .ap_done(FloatvMultConst_6__ap_done), - .ap_idle(FloatvMultConst_6__ap_idle), - .ap_ready(FloatvMultConst_6__ap_ready), - .M(FloatvMultConst_6___M__q0), - .P_N(FloatvMultConst_6___P_N__q0), - .alpha_u(FloatvMultConst_6___beta_u__q0), - .fifo_in_s_dout(fifo_C_read_in_Sextans_6__dout), - .fifo_in_peek_dout(fifo_C_read_in_Sextans_6__dout), - .fifo_in_s_empty_n(fifo_C_read_in_Sextans_6__empty_n), - .fifo_in_peek_empty_n(fifo_C_read_in_Sextans_6__empty_n), - .fifo_in_s_read(fifo_C_read_in_Sextans_6__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_read_in_beta_Sextans_6__din), - .fifo_out_full_n(fifo_C_read_in_beta_Sextans_6__full_n), - .fifo_out_write(fifo_C_read_in_beta_Sextans_6__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_7__ap_start), - .ap_done(FloatvMultConst_7__ap_done), - .ap_idle(FloatvMultConst_7__ap_idle), - .ap_ready(FloatvMultConst_7__ap_ready), - .M(FloatvMultConst_7___M__q0), - .P_N(FloatvMultConst_7___P_N__q0), - .alpha_u(FloatvMultConst_7___beta_u__q0), - .fifo_in_s_dout(fifo_C_read_in_Sextans_7__dout), - .fifo_in_peek_dout(fifo_C_read_in_Sextans_7__dout), - .fifo_in_s_empty_n(fifo_C_read_in_Sextans_7__empty_n), - .fifo_in_peek_empty_n(fifo_C_read_in_Sextans_7__empty_n), - .fifo_in_s_read(fifo_C_read_in_Sextans_7__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_read_in_beta_Sextans_7__din), - .fifo_out_full_n(fifo_C_read_in_beta_Sextans_7__full_n), - .fifo_out_write(fifo_C_read_in_beta_Sextans_7__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_8 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_8__ap_start), - .ap_done(FloatvMultConst_8__ap_done), - .ap_idle(FloatvMultConst_8__ap_idle), - .ap_ready(FloatvMultConst_8__ap_ready), - .M(FloatvMultConst_8___M__q0), - .P_N(FloatvMultConst_8___P_N__q0), - .alpha_u(FloatvMultConst_8___alpha_u__q0), - .fifo_in_s_dout(fifo_C_ch_result_Sextans_0__dout), - .fifo_in_peek_dout(fifo_C_ch_result_Sextans_0__dout), - .fifo_in_s_empty_n(fifo_C_ch_result_Sextans_0__empty_n), - .fifo_in_peek_empty_n(fifo_C_ch_result_Sextans_0__empty_n), - .fifo_in_s_read(fifo_C_ch_result_Sextans_0__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_ch_result_alpha_Sextans_0__din), - .fifo_out_full_n(fifo_C_ch_result_alpha_Sextans_0__full_n), - .fifo_out_write(fifo_C_ch_result_alpha_Sextans_0__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_9 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_9__ap_start), - .ap_done(FloatvMultConst_9__ap_done), - .ap_idle(FloatvMultConst_9__ap_idle), - .ap_ready(FloatvMultConst_9__ap_ready), - .M(FloatvMultConst_9___M__q0), - .P_N(FloatvMultConst_9___P_N__q0), - .alpha_u(FloatvMultConst_9___alpha_u__q0), - .fifo_in_s_dout(fifo_C_ch_result_Sextans_1__dout), - .fifo_in_peek_dout(fifo_C_ch_result_Sextans_1__dout), - .fifo_in_s_empty_n(fifo_C_ch_result_Sextans_1__empty_n), - .fifo_in_peek_empty_n(fifo_C_ch_result_Sextans_1__empty_n), - .fifo_in_s_read(fifo_C_ch_result_Sextans_1__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_ch_result_alpha_Sextans_1__din), - .fifo_out_full_n(fifo_C_ch_result_alpha_Sextans_1__full_n), - .fifo_out_write(fifo_C_ch_result_alpha_Sextans_1__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_10 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_10__ap_start), - .ap_done(FloatvMultConst_10__ap_done), - .ap_idle(FloatvMultConst_10__ap_idle), - .ap_ready(FloatvMultConst_10__ap_ready), - .M(FloatvMultConst_10___M__q0), - .P_N(FloatvMultConst_10___P_N__q0), - .alpha_u(FloatvMultConst_10___alpha_u__q0), - .fifo_in_s_dout(fifo_C_ch_result_Sextans_2__dout), - .fifo_in_peek_dout(fifo_C_ch_result_Sextans_2__dout), - .fifo_in_s_empty_n(fifo_C_ch_result_Sextans_2__empty_n), - .fifo_in_peek_empty_n(fifo_C_ch_result_Sextans_2__empty_n), - .fifo_in_s_read(fifo_C_ch_result_Sextans_2__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_ch_result_alpha_Sextans_2__din), - .fifo_out_full_n(fifo_C_ch_result_alpha_Sextans_2__full_n), - .fifo_out_write(fifo_C_ch_result_alpha_Sextans_2__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_11 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_11__ap_start), - .ap_done(FloatvMultConst_11__ap_done), - .ap_idle(FloatvMultConst_11__ap_idle), - .ap_ready(FloatvMultConst_11__ap_ready), - .M(FloatvMultConst_11___M__q0), - .P_N(FloatvMultConst_11___P_N__q0), - .alpha_u(FloatvMultConst_11___alpha_u__q0), - .fifo_in_s_dout(fifo_C_ch_result_Sextans_3__dout), - .fifo_in_peek_dout(fifo_C_ch_result_Sextans_3__dout), - .fifo_in_s_empty_n(fifo_C_ch_result_Sextans_3__empty_n), - .fifo_in_peek_empty_n(fifo_C_ch_result_Sextans_3__empty_n), - .fifo_in_s_read(fifo_C_ch_result_Sextans_3__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_ch_result_alpha_Sextans_3__din), - .fifo_out_full_n(fifo_C_ch_result_alpha_Sextans_3__full_n), - .fifo_out_write(fifo_C_ch_result_alpha_Sextans_3__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_12 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_12__ap_start), - .ap_done(FloatvMultConst_12__ap_done), - .ap_idle(FloatvMultConst_12__ap_idle), - .ap_ready(FloatvMultConst_12__ap_ready), - .M(FloatvMultConst_12___M__q0), - .P_N(FloatvMultConst_12___P_N__q0), - .alpha_u(FloatvMultConst_12___alpha_u__q0), - .fifo_in_s_dout(fifo_C_ch_result_Sextans_4__dout), - .fifo_in_peek_dout(fifo_C_ch_result_Sextans_4__dout), - .fifo_in_s_empty_n(fifo_C_ch_result_Sextans_4__empty_n), - .fifo_in_peek_empty_n(fifo_C_ch_result_Sextans_4__empty_n), - .fifo_in_s_read(fifo_C_ch_result_Sextans_4__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_ch_result_alpha_Sextans_4__din), - .fifo_out_full_n(fifo_C_ch_result_alpha_Sextans_4__full_n), - .fifo_out_write(fifo_C_ch_result_alpha_Sextans_4__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_13 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_13__ap_start), - .ap_done(FloatvMultConst_13__ap_done), - .ap_idle(FloatvMultConst_13__ap_idle), - .ap_ready(FloatvMultConst_13__ap_ready), - .M(FloatvMultConst_13___M__q0), - .P_N(FloatvMultConst_13___P_N__q0), - .alpha_u(FloatvMultConst_13___alpha_u__q0), - .fifo_in_s_dout(fifo_C_ch_result_Sextans_5__dout), - .fifo_in_peek_dout(fifo_C_ch_result_Sextans_5__dout), - .fifo_in_s_empty_n(fifo_C_ch_result_Sextans_5__empty_n), - .fifo_in_peek_empty_n(fifo_C_ch_result_Sextans_5__empty_n), - .fifo_in_s_read(fifo_C_ch_result_Sextans_5__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_ch_result_alpha_Sextans_5__din), - .fifo_out_full_n(fifo_C_ch_result_alpha_Sextans_5__full_n), - .fifo_out_write(fifo_C_ch_result_alpha_Sextans_5__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_14 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_14__ap_start), - .ap_done(FloatvMultConst_14__ap_done), - .ap_idle(FloatvMultConst_14__ap_idle), - .ap_ready(FloatvMultConst_14__ap_ready), - .M(FloatvMultConst_14___M__q0), - .P_N(FloatvMultConst_14___P_N__q0), - .alpha_u(FloatvMultConst_14___alpha_u__q0), - .fifo_in_s_dout(fifo_C_ch_result_Sextans_6__dout), - .fifo_in_peek_dout(fifo_C_ch_result_Sextans_6__dout), - .fifo_in_s_empty_n(fifo_C_ch_result_Sextans_6__empty_n), - .fifo_in_peek_empty_n(fifo_C_ch_result_Sextans_6__empty_n), - .fifo_in_s_read(fifo_C_ch_result_Sextans_6__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_ch_result_alpha_Sextans_6__din), - .fifo_out_full_n(fifo_C_ch_result_alpha_Sextans_6__full_n), - .fifo_out_write(fifo_C_ch_result_alpha_Sextans_6__write) - ); - - - (* keep_hierarchy = "yes" *) FloatvMultConst - FloatvMultConst_15 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(FloatvMultConst_15__ap_start), - .ap_done(FloatvMultConst_15__ap_done), - .ap_idle(FloatvMultConst_15__ap_idle), - .ap_ready(FloatvMultConst_15__ap_ready), - .M(FloatvMultConst_15___M__q0), - .P_N(FloatvMultConst_15___P_N__q0), - .alpha_u(FloatvMultConst_15___alpha_u__q0), - .fifo_in_s_dout(fifo_C_ch_result_Sextans_7__dout), - .fifo_in_peek_dout(fifo_C_ch_result_Sextans_7__dout), - .fifo_in_s_empty_n(fifo_C_ch_result_Sextans_7__empty_n), - .fifo_in_peek_empty_n(fifo_C_ch_result_Sextans_7__empty_n), - .fifo_in_s_read(fifo_C_ch_result_Sextans_7__read), - .fifo_in_peek_read(), - .fifo_out_din(fifo_C_ch_result_alpha_Sextans_7__din), - .fifo_out_full_n(fifo_C_ch_result_alpha_Sextans_7__full_n), - .fifo_out_write(fifo_C_ch_result_alpha_Sextans_7__write) - ); - - - (* keep_hierarchy = "yes" *) Merger - Merger_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Merger_0__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_result_Sextans_0__din), - .fifo_out_full_n(fifo_C_ch_result_Sextans_0__full_n), - .fifo_out_write(fifo_C_ch_result_Sextans_0__write), - .fifo_in_0_dout(fifo_C_pe_Sextans_0__dout), - .fifo_in_peek_0_dout(fifo_C_pe_Sextans_0__dout), - .fifo_in_0_empty_n(fifo_C_pe_Sextans_0__empty_n), - .fifo_in_peek_0_empty_n(fifo_C_pe_Sextans_0__empty_n), - .fifo_in_0_read(fifo_C_pe_Sextans_0__read), - .fifo_in_peek_0_read(), - .fifo_in_1_dout(fifo_C_pe_Sextans_1__dout), - .fifo_in_peek_1_dout(fifo_C_pe_Sextans_1__dout), - .fifo_in_1_empty_n(fifo_C_pe_Sextans_1__empty_n), - .fifo_in_peek_1_empty_n(fifo_C_pe_Sextans_1__empty_n), - .fifo_in_1_read(fifo_C_pe_Sextans_1__read), - .fifo_in_peek_1_read() - ); - - - (* keep_hierarchy = "yes" *) Merger - Merger_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Merger_1__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_result_Sextans_1__din), - .fifo_out_full_n(fifo_C_ch_result_Sextans_1__full_n), - .fifo_out_write(fifo_C_ch_result_Sextans_1__write), - .fifo_in_0_dout(fifo_C_pe_Sextans_2__dout), - .fifo_in_peek_0_dout(fifo_C_pe_Sextans_2__dout), - .fifo_in_0_empty_n(fifo_C_pe_Sextans_2__empty_n), - .fifo_in_peek_0_empty_n(fifo_C_pe_Sextans_2__empty_n), - .fifo_in_0_read(fifo_C_pe_Sextans_2__read), - .fifo_in_peek_0_read(), - .fifo_in_1_dout(fifo_C_pe_Sextans_3__dout), - .fifo_in_peek_1_dout(fifo_C_pe_Sextans_3__dout), - .fifo_in_1_empty_n(fifo_C_pe_Sextans_3__empty_n), - .fifo_in_peek_1_empty_n(fifo_C_pe_Sextans_3__empty_n), - .fifo_in_1_read(fifo_C_pe_Sextans_3__read), - .fifo_in_peek_1_read() - ); - - - (* keep_hierarchy = "yes" *) Merger - Merger_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Merger_2__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_result_Sextans_2__din), - .fifo_out_full_n(fifo_C_ch_result_Sextans_2__full_n), - .fifo_out_write(fifo_C_ch_result_Sextans_2__write), - .fifo_in_0_dout(fifo_C_pe_Sextans_4__dout), - .fifo_in_peek_0_dout(fifo_C_pe_Sextans_4__dout), - .fifo_in_0_empty_n(fifo_C_pe_Sextans_4__empty_n), - .fifo_in_peek_0_empty_n(fifo_C_pe_Sextans_4__empty_n), - .fifo_in_0_read(fifo_C_pe_Sextans_4__read), - .fifo_in_peek_0_read(), - .fifo_in_1_dout(fifo_C_pe_Sextans_5__dout), - .fifo_in_peek_1_dout(fifo_C_pe_Sextans_5__dout), - .fifo_in_1_empty_n(fifo_C_pe_Sextans_5__empty_n), - .fifo_in_peek_1_empty_n(fifo_C_pe_Sextans_5__empty_n), - .fifo_in_1_read(fifo_C_pe_Sextans_5__read), - .fifo_in_peek_1_read() - ); - - - (* keep_hierarchy = "yes" *) Merger - Merger_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Merger_3__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_result_Sextans_3__din), - .fifo_out_full_n(fifo_C_ch_result_Sextans_3__full_n), - .fifo_out_write(fifo_C_ch_result_Sextans_3__write), - .fifo_in_0_dout(fifo_C_pe_Sextans_6__dout), - .fifo_in_peek_0_dout(fifo_C_pe_Sextans_6__dout), - .fifo_in_0_empty_n(fifo_C_pe_Sextans_6__empty_n), - .fifo_in_peek_0_empty_n(fifo_C_pe_Sextans_6__empty_n), - .fifo_in_0_read(fifo_C_pe_Sextans_6__read), - .fifo_in_peek_0_read(), - .fifo_in_1_dout(fifo_C_pe_Sextans_7__dout), - .fifo_in_peek_1_dout(fifo_C_pe_Sextans_7__dout), - .fifo_in_1_empty_n(fifo_C_pe_Sextans_7__empty_n), - .fifo_in_peek_1_empty_n(fifo_C_pe_Sextans_7__empty_n), - .fifo_in_1_read(fifo_C_pe_Sextans_7__read), - .fifo_in_peek_1_read() - ); - - - (* keep_hierarchy = "yes" *) Merger - Merger_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Merger_4__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_result_Sextans_4__din), - .fifo_out_full_n(fifo_C_ch_result_Sextans_4__full_n), - .fifo_out_write(fifo_C_ch_result_Sextans_4__write), - .fifo_in_0_dout(fifo_C_pe_Sextans_8__dout), - .fifo_in_peek_0_dout(fifo_C_pe_Sextans_8__dout), - .fifo_in_0_empty_n(fifo_C_pe_Sextans_8__empty_n), - .fifo_in_peek_0_empty_n(fifo_C_pe_Sextans_8__empty_n), - .fifo_in_0_read(fifo_C_pe_Sextans_8__read), - .fifo_in_peek_0_read(), - .fifo_in_1_dout(fifo_C_pe_Sextans_9__dout), - .fifo_in_peek_1_dout(fifo_C_pe_Sextans_9__dout), - .fifo_in_1_empty_n(fifo_C_pe_Sextans_9__empty_n), - .fifo_in_peek_1_empty_n(fifo_C_pe_Sextans_9__empty_n), - .fifo_in_1_read(fifo_C_pe_Sextans_9__read), - .fifo_in_peek_1_read() - ); - - - (* keep_hierarchy = "yes" *) Merger - Merger_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Merger_5__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_result_Sextans_5__din), - .fifo_out_full_n(fifo_C_ch_result_Sextans_5__full_n), - .fifo_out_write(fifo_C_ch_result_Sextans_5__write), - .fifo_in_0_dout(fifo_C_pe_Sextans_10__dout), - .fifo_in_peek_0_dout(fifo_C_pe_Sextans_10__dout), - .fifo_in_0_empty_n(fifo_C_pe_Sextans_10__empty_n), - .fifo_in_peek_0_empty_n(fifo_C_pe_Sextans_10__empty_n), - .fifo_in_0_read(fifo_C_pe_Sextans_10__read), - .fifo_in_peek_0_read(), - .fifo_in_1_dout(fifo_C_pe_Sextans_11__dout), - .fifo_in_peek_1_dout(fifo_C_pe_Sextans_11__dout), - .fifo_in_1_empty_n(fifo_C_pe_Sextans_11__empty_n), - .fifo_in_peek_1_empty_n(fifo_C_pe_Sextans_11__empty_n), - .fifo_in_1_read(fifo_C_pe_Sextans_11__read), - .fifo_in_peek_1_read() - ); - - - (* keep_hierarchy = "yes" *) Merger - Merger_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Merger_6__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_result_Sextans_6__din), - .fifo_out_full_n(fifo_C_ch_result_Sextans_6__full_n), - .fifo_out_write(fifo_C_ch_result_Sextans_6__write), - .fifo_in_0_dout(fifo_C_pe_Sextans_12__dout), - .fifo_in_peek_0_dout(fifo_C_pe_Sextans_12__dout), - .fifo_in_0_empty_n(fifo_C_pe_Sextans_12__empty_n), - .fifo_in_peek_0_empty_n(fifo_C_pe_Sextans_12__empty_n), - .fifo_in_0_read(fifo_C_pe_Sextans_12__read), - .fifo_in_peek_0_read(), - .fifo_in_1_dout(fifo_C_pe_Sextans_13__dout), - .fifo_in_peek_1_dout(fifo_C_pe_Sextans_13__dout), - .fifo_in_1_empty_n(fifo_C_pe_Sextans_13__empty_n), - .fifo_in_peek_1_empty_n(fifo_C_pe_Sextans_13__empty_n), - .fifo_in_1_read(fifo_C_pe_Sextans_13__read), - .fifo_in_peek_1_read() - ); - - - (* keep_hierarchy = "yes" *) Merger - Merger_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Merger_7__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_out_din(fifo_C_ch_result_Sextans_7__din), - .fifo_out_full_n(fifo_C_ch_result_Sextans_7__full_n), - .fifo_out_write(fifo_C_ch_result_Sextans_7__write), - .fifo_in_0_dout(fifo_C_pe_Sextans_14__dout), - .fifo_in_peek_0_dout(fifo_C_pe_Sextans_14__dout), - .fifo_in_0_empty_n(fifo_C_pe_Sextans_14__empty_n), - .fifo_in_peek_0_empty_n(fifo_C_pe_Sextans_14__empty_n), - .fifo_in_0_read(fifo_C_pe_Sextans_14__read), - .fifo_in_peek_0_read(), - .fifo_in_1_dout(fifo_C_pe_Sextans_15__dout), - .fifo_in_peek_1_dout(fifo_C_pe_Sextans_15__dout), - .fifo_in_1_empty_n(fifo_C_pe_Sextans_15__empty_n), - .fifo_in_peek_1_empty_n(fifo_C_pe_Sextans_15__empty_n), - .fifo_in_1_read(fifo_C_pe_Sextans_15__read), - .fifo_in_peek_1_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_0__ap_start), - .ap_done(PEG_Bmtx_0__ap_done), - .ap_idle(PEG_Bmtx_0__ap_idle), - .ap_ready(PEG_Bmtx_0__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_0__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_0__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_0__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_0__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_0__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_1__din), - .PE_inst_out_full_n(PE_inst_Sextans_1__full_n), - .PE_inst_out_write(PE_inst_Sextans_1__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_0__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_0__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_0__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_0__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_0__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_0__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_0__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_0__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_0__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_0__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_0__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_0__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_0__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_1__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_1__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_1__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_1__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_1__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_2__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_2__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_2__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_2__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_2__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_3__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_3__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_3__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_3__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_3__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_4__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_4__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_4__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_5__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_5__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_5__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_6__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_6__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_6__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_7__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_7__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_7__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_0__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_0__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_0__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_1__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_1__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_1__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_2__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_2__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_2__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_3__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_3__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_3__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_0__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_0__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_0__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_0__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_0__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_1__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_1__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_1__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_0__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_0__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_0__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_1__ap_start), - .ap_done(PEG_Bmtx_1__ap_done), - .ap_idle(PEG_Bmtx_1__ap_idle), - .ap_ready(PEG_Bmtx_1__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_1__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_1__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_1__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_1__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_1__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_2__din), - .PE_inst_out_full_n(PE_inst_Sextans_2__full_n), - .PE_inst_out_write(PE_inst_Sextans_2__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_1__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_1__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_1__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_1__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_1__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_1__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_1__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_1__read), - .fifo_A_peek_read(), - .fifo_B_out_2_din(fifo_B_pe_Sextans_10__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_10__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_10__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_11__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_11__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_11__write), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_4__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_4__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_4__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_4__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_4__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_5__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_5__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_5__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_5__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_5__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_6__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_6__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_6__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_6__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_6__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_7__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_7__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_7__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_7__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_7__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_8__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_8__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_8__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_9__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_9__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_9__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_4__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_4__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_4__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_5__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_5__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_5__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_6__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_6__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_6__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_7__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_7__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_7__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_1__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_1__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_1__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_1__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_1__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_2__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_2__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_2__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_1__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_1__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_1__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_2__ap_start), - .ap_done(PEG_Bmtx_2__ap_done), - .ap_idle(PEG_Bmtx_2__ap_idle), - .ap_ready(PEG_Bmtx_2__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_2__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_2__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_2__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_2__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_2__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_3__din), - .PE_inst_out_full_n(PE_inst_Sextans_3__full_n), - .PE_inst_out_write(PE_inst_Sextans_3__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_2__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_2__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_2__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_2__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_2__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_2__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_2__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_2__read), - .fifo_A_peek_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_10__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_10__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_10__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_10__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_10__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_11__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_11__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_11__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_11__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_11__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_12__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_12__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_12__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_13__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_13__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_13__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_14__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_14__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_14__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_15__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_15__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_15__write), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_8__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_8__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_8__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_8__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_8__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_9__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_9__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_9__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_9__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_9__read), - .fifo_B_in_peek_1_read(), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_10__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_10__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_10__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_11__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_11__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_11__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_8__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_8__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_8__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_9__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_9__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_9__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_2__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_2__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_2__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_2__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_2__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_3__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_3__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_3__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_2__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_2__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_2__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_3__ap_start), - .ap_done(PEG_Bmtx_3__ap_done), - .ap_idle(PEG_Bmtx_3__ap_idle), - .ap_ready(PEG_Bmtx_3__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_3__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_3__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_3__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_3__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_3__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_4__din), - .PE_inst_out_full_n(PE_inst_Sextans_4__full_n), - .PE_inst_out_write(PE_inst_Sextans_4__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_3__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_3__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_3__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_3__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_3__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_3__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_3__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_3__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_12__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_12__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_12__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_12__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_12__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_13__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_13__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_13__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_13__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_13__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_14__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_14__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_14__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_14__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_14__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_15__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_15__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_15__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_15__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_15__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_16__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_16__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_16__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_17__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_17__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_17__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_18__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_18__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_18__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_19__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_19__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_19__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_12__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_12__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_12__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_13__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_13__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_13__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_14__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_14__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_14__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_15__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_15__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_15__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_3__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_3__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_3__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_3__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_3__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_4__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_4__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_4__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_3__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_3__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_3__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_4__ap_start), - .ap_done(PEG_Bmtx_4__ap_done), - .ap_idle(PEG_Bmtx_4__ap_idle), - .ap_ready(PEG_Bmtx_4__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_4__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_4__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_4__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_4__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_4__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_5__din), - .PE_inst_out_full_n(PE_inst_Sextans_5__full_n), - .PE_inst_out_write(PE_inst_Sextans_5__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_4__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_4__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_4__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_4__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_4__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_4__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_4__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_4__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_16__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_16__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_16__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_16__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_16__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_17__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_17__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_17__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_17__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_17__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_18__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_18__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_18__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_18__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_18__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_19__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_19__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_19__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_19__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_19__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_20__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_20__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_20__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_21__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_21__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_21__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_22__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_22__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_22__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_23__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_23__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_23__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_16__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_16__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_16__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_17__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_17__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_17__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_18__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_18__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_18__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_19__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_19__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_19__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_4__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_4__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_4__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_4__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_4__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_5__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_5__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_5__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_4__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_4__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_4__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_5__ap_start), - .ap_done(PEG_Bmtx_5__ap_done), - .ap_idle(PEG_Bmtx_5__ap_idle), - .ap_ready(PEG_Bmtx_5__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_5__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_5__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_5__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_5__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_5__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_6__din), - .PE_inst_out_full_n(PE_inst_Sextans_6__full_n), - .PE_inst_out_write(PE_inst_Sextans_6__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_5__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_5__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_5__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_5__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_5__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_5__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_5__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_5__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_20__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_20__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_20__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_20__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_20__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_21__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_21__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_21__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_21__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_21__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_22__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_22__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_22__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_22__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_22__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_23__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_23__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_23__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_23__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_23__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_24__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_24__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_24__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_25__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_25__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_25__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_26__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_26__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_26__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_27__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_27__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_27__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_20__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_20__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_20__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_21__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_21__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_21__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_22__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_22__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_22__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_23__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_23__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_23__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_5__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_5__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_5__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_5__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_5__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_6__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_6__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_6__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_5__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_5__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_5__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_6__ap_start), - .ap_done(PEG_Bmtx_6__ap_done), - .ap_idle(PEG_Bmtx_6__ap_idle), - .ap_ready(PEG_Bmtx_6__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_6__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_6__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_6__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_6__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_6__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_7__din), - .PE_inst_out_full_n(PE_inst_Sextans_7__full_n), - .PE_inst_out_write(PE_inst_Sextans_7__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_6__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_6__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_6__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_6__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_6__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_6__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_6__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_6__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_24__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_24__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_24__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_24__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_24__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_25__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_25__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_25__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_25__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_25__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_26__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_26__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_26__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_26__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_26__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_27__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_27__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_27__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_27__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_27__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_28__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_28__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_28__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_29__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_29__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_29__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_30__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_30__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_30__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_31__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_31__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_31__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_24__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_24__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_24__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_25__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_25__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_25__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_26__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_26__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_26__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_27__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_27__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_27__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_6__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_6__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_6__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_6__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_6__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_7__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_7__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_7__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_6__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_6__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_6__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_7__ap_start), - .ap_done(PEG_Bmtx_7__ap_done), - .ap_idle(PEG_Bmtx_7__ap_idle), - .ap_ready(PEG_Bmtx_7__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_7__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_7__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_7__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_7__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_7__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_8__din), - .PE_inst_out_full_n(PE_inst_Sextans_8__full_n), - .PE_inst_out_write(PE_inst_Sextans_8__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_7__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_7__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_7__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_7__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_7__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_7__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_7__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_7__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_28__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_28__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_28__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_28__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_28__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_29__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_29__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_29__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_29__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_29__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_30__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_30__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_30__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_30__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_30__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_31__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_31__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_31__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_31__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_31__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_32__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_32__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_32__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_33__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_33__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_33__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_34__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_34__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_34__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_35__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_35__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_35__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_28__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_28__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_28__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_29__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_29__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_29__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_30__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_30__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_30__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_31__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_31__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_31__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_7__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_7__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_7__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_7__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_7__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_8__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_8__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_8__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_7__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_7__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_7__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_8 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_8__ap_start), - .ap_done(PEG_Bmtx_8__ap_done), - .ap_idle(PEG_Bmtx_8__ap_idle), - .ap_ready(PEG_Bmtx_8__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_8__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_8__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_8__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_8__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_8__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_9__din), - .PE_inst_out_full_n(PE_inst_Sextans_9__full_n), - .PE_inst_out_write(PE_inst_Sextans_9__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_8__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_8__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_8__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_8__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_8__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_8__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_8__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_8__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_32__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_32__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_32__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_32__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_32__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_33__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_33__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_33__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_33__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_33__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_34__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_34__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_34__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_34__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_34__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_35__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_35__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_35__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_35__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_35__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_36__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_36__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_36__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_37__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_37__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_37__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_38__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_38__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_38__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_39__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_39__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_39__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_32__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_32__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_32__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_33__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_33__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_33__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_34__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_34__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_34__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_35__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_35__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_35__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_8__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_8__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_8__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_8__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_8__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_9__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_9__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_9__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_8__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_8__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_8__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_9 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_9__ap_start), - .ap_done(PEG_Bmtx_9__ap_done), - .ap_idle(PEG_Bmtx_9__ap_idle), - .ap_ready(PEG_Bmtx_9__ap_ready), - .PE_inst_out_din(PE_inst_Sextans_10__din), - .PE_inst_out_full_n(PE_inst_Sextans_10__full_n), - .PE_inst_out_write(PE_inst_Sextans_10__write), - .PE_inst_in_s_dout(PE_inst_Sextans_9__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_9__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_9__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_9__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_9__read), - .PE_inst_in_peek_read(), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_9__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_9__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_9__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_9__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_9__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_9__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_9__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_9__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_36__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_36__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_36__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_36__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_36__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_37__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_37__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_37__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_37__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_37__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_38__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_38__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_38__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_38__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_38__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_39__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_39__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_39__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_39__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_39__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_40__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_40__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_40__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_41__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_41__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_41__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_42__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_42__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_42__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_43__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_43__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_43__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_36__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_36__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_36__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_37__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_37__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_37__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_38__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_38__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_38__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_39__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_39__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_39__write), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_10__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_10__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_10__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_9__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_9__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_9__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_9__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_9__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_9__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_9__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_9__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_10 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_10__ap_start), - .ap_done(PEG_Bmtx_10__ap_done), - .ap_idle(PEG_Bmtx_10__ap_idle), - .ap_ready(PEG_Bmtx_10__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_10__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_10__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_10__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_10__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_10__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_11__din), - .PE_inst_out_full_n(PE_inst_Sextans_11__full_n), - .PE_inst_out_write(PE_inst_Sextans_11__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_10__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_10__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_10__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_10__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_10__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_10__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_10__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_10__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_40__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_40__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_40__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_40__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_40__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_41__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_41__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_41__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_41__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_41__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_42__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_42__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_42__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_42__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_42__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_43__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_43__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_43__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_43__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_43__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_44__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_44__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_44__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_45__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_45__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_45__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_46__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_46__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_46__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_47__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_47__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_47__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_40__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_40__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_40__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_41__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_41__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_41__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_42__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_42__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_42__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_43__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_43__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_43__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_10__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_10__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_10__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_10__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_10__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_11__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_11__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_11__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_10__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_10__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_10__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_11 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_11__ap_start), - .ap_done(PEG_Bmtx_11__ap_done), - .ap_idle(PEG_Bmtx_11__ap_idle), - .ap_ready(PEG_Bmtx_11__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_11__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_11__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_11__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_11__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_11__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_12__din), - .PE_inst_out_full_n(PE_inst_Sextans_12__full_n), - .PE_inst_out_write(PE_inst_Sextans_12__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_11__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_11__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_11__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_11__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_11__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_11__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_11__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_11__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_44__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_44__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_44__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_44__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_44__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_45__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_45__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_45__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_45__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_45__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_46__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_46__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_46__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_46__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_46__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_47__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_47__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_47__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_47__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_47__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_48__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_48__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_48__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_49__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_49__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_49__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_50__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_50__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_50__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_51__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_51__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_51__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_44__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_44__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_44__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_45__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_45__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_45__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_46__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_46__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_46__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_47__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_47__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_47__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_11__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_11__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_11__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_11__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_11__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_12__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_12__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_12__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_11__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_11__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_11__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_12 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_12__ap_start), - .ap_done(PEG_Bmtx_12__ap_done), - .ap_idle(PEG_Bmtx_12__ap_idle), - .ap_ready(PEG_Bmtx_12__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_12__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_12__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_12__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_12__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_12__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_13__din), - .PE_inst_out_full_n(PE_inst_Sextans_13__full_n), - .PE_inst_out_write(PE_inst_Sextans_13__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_12__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_12__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_12__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_12__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_12__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_12__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_12__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_12__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_48__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_48__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_48__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_48__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_48__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_49__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_49__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_49__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_49__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_49__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_50__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_50__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_50__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_50__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_50__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_51__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_51__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_51__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_51__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_51__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_52__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_52__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_52__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_53__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_53__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_53__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_54__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_54__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_54__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_55__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_55__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_55__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_48__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_48__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_48__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_49__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_49__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_49__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_50__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_50__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_50__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_51__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_51__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_51__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_12__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_12__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_12__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_12__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_12__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_13__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_13__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_13__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_12__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_12__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_12__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_13 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_13__ap_start), - .ap_done(PEG_Bmtx_13__ap_done), - .ap_idle(PEG_Bmtx_13__ap_idle), - .ap_ready(PEG_Bmtx_13__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_13__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_13__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_13__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_13__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_13__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_14__din), - .PE_inst_out_full_n(PE_inst_Sextans_14__full_n), - .PE_inst_out_write(PE_inst_Sextans_14__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_13__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_13__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_13__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_13__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_13__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_13__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_13__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_13__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_52__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_52__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_52__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_52__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_52__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_53__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_53__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_53__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_53__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_53__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_54__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_54__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_54__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_54__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_54__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_55__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_55__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_55__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_55__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_55__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_56__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_56__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_56__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_57__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_57__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_57__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_58__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_58__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_58__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_59__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_59__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_59__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_52__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_52__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_52__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_53__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_53__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_53__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_54__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_54__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_54__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_55__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_55__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_55__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_13__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_13__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_13__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_13__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_13__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_14__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_14__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_14__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_13__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_13__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_13__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_14 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_14__ap_start), - .ap_done(PEG_Bmtx_14__ap_done), - .ap_idle(PEG_Bmtx_14__ap_idle), - .ap_ready(PEG_Bmtx_14__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_14__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_14__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_14__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_14__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_14__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_15__din), - .PE_inst_out_full_n(PE_inst_Sextans_15__full_n), - .PE_inst_out_write(PE_inst_Sextans_15__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_14__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_14__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_14__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_14__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_14__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_14__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_14__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_14__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_56__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_56__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_56__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_56__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_56__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_57__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_57__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_57__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_57__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_57__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_58__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_58__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_58__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_58__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_58__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_59__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_59__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_59__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_59__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_59__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_60__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_60__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_60__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_61__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_61__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_61__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_62__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_62__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_62__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_63__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_63__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_63__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_56__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_56__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_56__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_57__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_57__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_57__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_58__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_58__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_58__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_59__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_59__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_59__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_14__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_14__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_14__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_14__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_14__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_15__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_15__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_15__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_14__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_14__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_14__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Bmtx - PEG_Bmtx_15 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Bmtx_15__ap_start), - .ap_done(PEG_Bmtx_15__ap_done), - .ap_idle(PEG_Bmtx_15__ap_idle), - .ap_ready(PEG_Bmtx_15__ap_ready), - .PE_inst_in_s_dout(PE_inst_Sextans_15__dout), - .PE_inst_in_peek_dout(PE_inst_Sextans_15__dout), - .PE_inst_in_s_empty_n(PE_inst_Sextans_15__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_Sextans_15__empty_n), - .PE_inst_in_s_read(PE_inst_Sextans_15__read), - .PE_inst_in_peek_read(), - .PE_inst_out_din(PE_inst_Sextans_16__din), - .PE_inst_out_full_n(PE_inst_Sextans_16__full_n), - .PE_inst_out_write(PE_inst_Sextans_16__write), - .PE_inst_to_Cmtx_din(PE_inst_to_Cmtx_Sextans_15__din), - .PE_inst_to_Cmtx_full_n(PE_inst_to_Cmtx_Sextans_15__full_n), - .PE_inst_to_Cmtx_write(PE_inst_to_Cmtx_Sextans_15__write), - .fifo_A_s_dout(fifo_A_pe_Sextans_15__dout), - .fifo_A_peek_dout(fifo_A_pe_Sextans_15__dout), - .fifo_A_s_empty_n(fifo_A_pe_Sextans_15__empty_n), - .fifo_A_peek_empty_n(fifo_A_pe_Sextans_15__empty_n), - .fifo_A_s_read(fifo_A_pe_Sextans_15__read), - .fifo_A_peek_read(), - .fifo_B_in_0_dout(fifo_B_pe_Sextans_60__dout), - .fifo_B_in_peek_0_dout(fifo_B_pe_Sextans_60__dout), - .fifo_B_in_0_empty_n(fifo_B_pe_Sextans_60__empty_n), - .fifo_B_in_peek_0_empty_n(fifo_B_pe_Sextans_60__empty_n), - .fifo_B_in_0_read(fifo_B_pe_Sextans_60__read), - .fifo_B_in_peek_0_read(), - .fifo_B_in_1_dout(fifo_B_pe_Sextans_61__dout), - .fifo_B_in_peek_1_dout(fifo_B_pe_Sextans_61__dout), - .fifo_B_in_1_empty_n(fifo_B_pe_Sextans_61__empty_n), - .fifo_B_in_peek_1_empty_n(fifo_B_pe_Sextans_61__empty_n), - .fifo_B_in_1_read(fifo_B_pe_Sextans_61__read), - .fifo_B_in_peek_1_read(), - .fifo_B_in_2_dout(fifo_B_pe_Sextans_62__dout), - .fifo_B_in_peek_2_dout(fifo_B_pe_Sextans_62__dout), - .fifo_B_in_2_empty_n(fifo_B_pe_Sextans_62__empty_n), - .fifo_B_in_peek_2_empty_n(fifo_B_pe_Sextans_62__empty_n), - .fifo_B_in_2_read(fifo_B_pe_Sextans_62__read), - .fifo_B_in_peek_2_read(), - .fifo_B_in_3_dout(fifo_B_pe_Sextans_63__dout), - .fifo_B_in_peek_3_dout(fifo_B_pe_Sextans_63__dout), - .fifo_B_in_3_empty_n(fifo_B_pe_Sextans_63__empty_n), - .fifo_B_in_peek_3_empty_n(fifo_B_pe_Sextans_63__empty_n), - .fifo_B_in_3_read(fifo_B_pe_Sextans_63__read), - .fifo_B_in_peek_3_read(), - .fifo_B_out_0_din(fifo_B_pe_Sextans_64__din), - .fifo_B_out_0_full_n(fifo_B_pe_Sextans_64__full_n), - .fifo_B_out_0_write(fifo_B_pe_Sextans_64__write), - .fifo_B_out_1_din(fifo_B_pe_Sextans_65__din), - .fifo_B_out_1_full_n(fifo_B_pe_Sextans_65__full_n), - .fifo_B_out_1_write(fifo_B_pe_Sextans_65__write), - .fifo_B_out_2_din(fifo_B_pe_Sextans_66__din), - .fifo_B_out_2_full_n(fifo_B_pe_Sextans_66__full_n), - .fifo_B_out_2_write(fifo_B_pe_Sextans_66__write), - .fifo_B_out_3_din(fifo_B_pe_Sextans_67__din), - .fifo_B_out_3_full_n(fifo_B_pe_Sextans_67__full_n), - .fifo_B_out_3_write(fifo_B_pe_Sextans_67__write), - .fifo_aBvec_0_din(fifo_aBvec_Sextans_60__din), - .fifo_aBvec_0_full_n(fifo_aBvec_Sextans_60__full_n), - .fifo_aBvec_0_write(fifo_aBvec_Sextans_60__write), - .fifo_aBvec_1_din(fifo_aBvec_Sextans_61__din), - .fifo_aBvec_1_full_n(fifo_aBvec_Sextans_61__full_n), - .fifo_aBvec_1_write(fifo_aBvec_Sextans_61__write), - .fifo_aBvec_2_din(fifo_aBvec_Sextans_62__din), - .fifo_aBvec_2_full_n(fifo_aBvec_Sextans_62__full_n), - .fifo_aBvec_2_write(fifo_aBvec_Sextans_62__write), - .fifo_aBvec_3_din(fifo_aBvec_Sextans_63__din), - .fifo_aBvec_3_full_n(fifo_aBvec_Sextans_63__full_n), - .fifo_aBvec_3_write(fifo_aBvec_Sextans_63__write), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_Sextans_15__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_Sextans_15__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_Sextans_15__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_Sextans_15__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_Sextans_15__read), - .fifo_inst_in_peek_read(), - .fifo_inst_out_din(fifo_edge_list_ptr_Sextans_16__din), - .fifo_inst_out_full_n(fifo_edge_list_ptr_Sextans_16__full_n), - .fifo_inst_out_write(fifo_edge_list_ptr_Sextans_16__write), - .fifo_inst_out_to_Cmtx_din(fifo_edge_list_ptr_to_Cmtx_Sextans_15__din), - .fifo_inst_out_to_Cmtx_full_n(fifo_edge_list_ptr_to_Cmtx_Sextans_15__full_n), - .fifo_inst_out_to_Cmtx_write(fifo_edge_list_ptr_to_Cmtx_Sextans_15__write) - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_0__ap_start), - .ap_done(PEG_Cmtx_0__ap_done), - .ap_idle(PEG_Cmtx_0__ap_idle), - .ap_ready(PEG_Cmtx_0__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_0__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_0__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_0__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_0__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_0__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_0__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_0__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_0__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_0__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_0__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_0__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_0__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_0__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_1__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_1__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_1__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_1__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_1__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_2__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_2__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_2__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_2__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_2__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_3__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_3__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_3__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_3__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_3__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_0__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_0__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_0__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_0__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_0__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_1__ap_start), - .ap_done(PEG_Cmtx_1__ap_done), - .ap_idle(PEG_Cmtx_1__ap_idle), - .ap_ready(PEG_Cmtx_1__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_1__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_1__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_1__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_1__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_1__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_1__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_1__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_1__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_4__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_4__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_4__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_4__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_4__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_5__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_5__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_5__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_5__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_5__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_6__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_6__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_6__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_6__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_6__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_7__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_7__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_7__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_7__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_7__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_1__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_1__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_1__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_1__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_1__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_2__ap_start), - .ap_done(PEG_Cmtx_2__ap_done), - .ap_idle(PEG_Cmtx_2__ap_idle), - .ap_ready(PEG_Cmtx_2__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_2__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_2__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_2__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_2__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_2__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_2__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_2__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_2__write), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_10__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_10__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_10__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_10__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_10__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_11__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_11__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_11__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_11__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_11__read), - .fifo_aBvec_peek_3_read(), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_8__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_8__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_8__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_8__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_8__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_9__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_9__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_9__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_9__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_9__read), - .fifo_aBvec_peek_1_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_2__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_2__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_2__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_2__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_2__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_3__ap_start), - .ap_done(PEG_Cmtx_3__ap_done), - .ap_idle(PEG_Cmtx_3__ap_idle), - .ap_ready(PEG_Cmtx_3__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_3__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_3__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_3__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_3__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_3__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_3__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_3__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_3__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_12__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_12__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_12__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_12__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_12__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_13__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_13__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_13__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_13__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_13__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_14__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_14__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_14__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_14__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_14__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_15__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_15__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_15__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_15__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_15__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_3__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_3__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_3__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_3__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_3__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_4__ap_start), - .ap_done(PEG_Cmtx_4__ap_done), - .ap_idle(PEG_Cmtx_4__ap_idle), - .ap_ready(PEG_Cmtx_4__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_4__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_4__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_4__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_4__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_4__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_4__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_4__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_4__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_16__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_16__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_16__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_16__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_16__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_17__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_17__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_17__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_17__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_17__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_18__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_18__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_18__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_18__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_18__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_19__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_19__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_19__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_19__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_19__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_4__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_4__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_4__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_4__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_4__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_5__ap_start), - .ap_done(PEG_Cmtx_5__ap_done), - .ap_idle(PEG_Cmtx_5__ap_idle), - .ap_ready(PEG_Cmtx_5__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_5__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_5__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_5__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_5__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_5__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_5__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_5__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_5__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_20__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_20__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_20__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_20__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_20__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_21__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_21__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_21__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_21__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_21__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_22__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_22__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_22__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_22__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_22__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_23__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_23__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_23__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_23__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_23__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_5__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_5__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_5__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_5__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_5__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_6__ap_start), - .ap_done(PEG_Cmtx_6__ap_done), - .ap_idle(PEG_Cmtx_6__ap_idle), - .ap_ready(PEG_Cmtx_6__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_6__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_6__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_6__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_6__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_6__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_6__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_6__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_6__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_24__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_24__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_24__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_24__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_24__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_25__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_25__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_25__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_25__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_25__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_26__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_26__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_26__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_26__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_26__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_27__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_27__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_27__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_27__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_27__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_6__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_6__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_6__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_6__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_6__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_7__ap_start), - .ap_done(PEG_Cmtx_7__ap_done), - .ap_idle(PEG_Cmtx_7__ap_idle), - .ap_ready(PEG_Cmtx_7__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_7__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_7__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_7__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_7__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_7__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_7__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_7__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_7__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_28__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_28__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_28__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_28__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_28__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_29__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_29__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_29__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_29__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_29__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_30__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_30__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_30__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_30__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_30__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_31__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_31__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_31__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_31__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_31__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_7__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_7__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_7__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_7__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_7__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_8 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_8__ap_start), - .ap_done(PEG_Cmtx_8__ap_done), - .ap_idle(PEG_Cmtx_8__ap_idle), - .ap_ready(PEG_Cmtx_8__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_8__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_8__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_8__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_8__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_8__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_8__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_8__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_8__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_32__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_32__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_32__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_32__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_32__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_33__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_33__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_33__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_33__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_33__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_34__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_34__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_34__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_34__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_34__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_35__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_35__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_35__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_35__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_35__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_8__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_8__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_8__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_8__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_8__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_9 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_9__ap_start), - .ap_done(PEG_Cmtx_9__ap_done), - .ap_idle(PEG_Cmtx_9__ap_idle), - .ap_ready(PEG_Cmtx_9__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_9__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_9__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_9__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_9__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_9__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_9__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_9__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_9__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_36__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_36__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_36__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_36__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_36__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_37__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_37__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_37__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_37__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_37__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_38__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_38__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_38__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_38__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_38__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_39__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_39__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_39__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_39__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_39__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_9__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_9__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_9__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_9__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_9__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_10 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_10__ap_start), - .ap_done(PEG_Cmtx_10__ap_done), - .ap_idle(PEG_Cmtx_10__ap_idle), - .ap_ready(PEG_Cmtx_10__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_10__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_10__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_10__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_10__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_10__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_10__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_10__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_10__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_40__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_40__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_40__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_40__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_40__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_41__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_41__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_41__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_41__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_41__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_42__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_42__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_42__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_42__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_42__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_43__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_43__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_43__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_43__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_43__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_10__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_10__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_10__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_10__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_10__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_11 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_11__ap_start), - .ap_done(PEG_Cmtx_11__ap_done), - .ap_idle(PEG_Cmtx_11__ap_idle), - .ap_ready(PEG_Cmtx_11__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_11__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_11__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_11__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_11__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_11__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_11__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_11__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_11__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_44__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_44__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_44__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_44__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_44__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_45__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_45__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_45__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_45__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_45__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_46__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_46__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_46__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_46__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_46__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_47__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_47__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_47__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_47__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_47__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_11__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_11__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_11__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_11__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_11__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_12 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_12__ap_start), - .ap_done(PEG_Cmtx_12__ap_done), - .ap_idle(PEG_Cmtx_12__ap_idle), - .ap_ready(PEG_Cmtx_12__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_12__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_12__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_12__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_12__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_12__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_12__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_12__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_12__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_48__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_48__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_48__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_48__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_48__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_49__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_49__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_49__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_49__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_49__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_50__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_50__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_50__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_50__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_50__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_51__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_51__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_51__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_51__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_51__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_12__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_12__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_12__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_12__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_12__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_13 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_13__ap_start), - .ap_done(PEG_Cmtx_13__ap_done), - .ap_idle(PEG_Cmtx_13__ap_idle), - .ap_ready(PEG_Cmtx_13__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_13__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_13__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_13__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_13__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_13__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_13__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_13__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_13__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_52__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_52__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_52__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_52__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_52__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_53__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_53__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_53__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_53__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_53__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_54__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_54__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_54__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_54__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_54__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_55__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_55__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_55__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_55__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_55__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_13__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_13__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_13__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_13__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_13__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_14 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_14__ap_start), - .ap_done(PEG_Cmtx_14__ap_done), - .ap_idle(PEG_Cmtx_14__ap_idle), - .ap_ready(PEG_Cmtx_14__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_14__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_14__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_14__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_14__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_14__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_14__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_14__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_14__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_56__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_56__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_56__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_56__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_56__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_57__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_57__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_57__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_57__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_57__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_58__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_58__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_58__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_58__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_58__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_59__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_59__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_59__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_59__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_59__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_14__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_14__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_14__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_14__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_14__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) PEG_Cmtx - PEG_Cmtx_15 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(PEG_Cmtx_15__ap_start), - .ap_done(PEG_Cmtx_15__ap_done), - .ap_idle(PEG_Cmtx_15__ap_idle), - .ap_ready(PEG_Cmtx_15__ap_ready), - .PE_inst_in_s_dout(PE_inst_to_Cmtx_Sextans_15__dout), - .PE_inst_in_peek_dout(PE_inst_to_Cmtx_Sextans_15__dout), - .PE_inst_in_s_empty_n(PE_inst_to_Cmtx_Sextans_15__empty_n), - .PE_inst_in_peek_empty_n(PE_inst_to_Cmtx_Sextans_15__empty_n), - .PE_inst_in_s_read(PE_inst_to_Cmtx_Sextans_15__read), - .PE_inst_in_peek_read(), - .fifo_C_out_din(fifo_C_pe_Sextans_15__din), - .fifo_C_out_full_n(fifo_C_pe_Sextans_15__full_n), - .fifo_C_out_write(fifo_C_pe_Sextans_15__write), - .fifo_aBvec_0_dout(fifo_aBvec_Sextans_60__dout), - .fifo_aBvec_peek_0_dout(fifo_aBvec_Sextans_60__dout), - .fifo_aBvec_0_empty_n(fifo_aBvec_Sextans_60__empty_n), - .fifo_aBvec_peek_0_empty_n(fifo_aBvec_Sextans_60__empty_n), - .fifo_aBvec_0_read(fifo_aBvec_Sextans_60__read), - .fifo_aBvec_peek_0_read(), - .fifo_aBvec_1_dout(fifo_aBvec_Sextans_61__dout), - .fifo_aBvec_peek_1_dout(fifo_aBvec_Sextans_61__dout), - .fifo_aBvec_1_empty_n(fifo_aBvec_Sextans_61__empty_n), - .fifo_aBvec_peek_1_empty_n(fifo_aBvec_Sextans_61__empty_n), - .fifo_aBvec_1_read(fifo_aBvec_Sextans_61__read), - .fifo_aBvec_peek_1_read(), - .fifo_aBvec_2_dout(fifo_aBvec_Sextans_62__dout), - .fifo_aBvec_peek_2_dout(fifo_aBvec_Sextans_62__dout), - .fifo_aBvec_2_empty_n(fifo_aBvec_Sextans_62__empty_n), - .fifo_aBvec_peek_2_empty_n(fifo_aBvec_Sextans_62__empty_n), - .fifo_aBvec_2_read(fifo_aBvec_Sextans_62__read), - .fifo_aBvec_peek_2_read(), - .fifo_aBvec_3_dout(fifo_aBvec_Sextans_63__dout), - .fifo_aBvec_peek_3_dout(fifo_aBvec_Sextans_63__dout), - .fifo_aBvec_3_empty_n(fifo_aBvec_Sextans_63__empty_n), - .fifo_aBvec_peek_3_empty_n(fifo_aBvec_Sextans_63__empty_n), - .fifo_aBvec_3_read(fifo_aBvec_Sextans_63__read), - .fifo_aBvec_peek_3_read(), - .fifo_inst_in_s_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_15__dout), - .fifo_inst_in_peek_dout(fifo_edge_list_ptr_to_Cmtx_Sextans_15__dout), - .fifo_inst_in_s_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_15__empty_n), - .fifo_inst_in_peek_empty_n(fifo_edge_list_ptr_to_Cmtx_Sextans_15__empty_n), - .fifo_inst_in_s_read(fifo_edge_list_ptr_to_Cmtx_Sextans_15__read), - .fifo_inst_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) Scatter_1_2 - Scatter_1_2_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Scatter_1_2_0__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_A_Sextans_0__dout), - .fifo_in_peek_dout(fifo_A_Sextans_0__dout), - .fifo_in_s_empty_n(fifo_A_Sextans_0__empty_n), - .fifo_in_peek_empty_n(fifo_A_Sextans_0__empty_n), - .fifo_in_s_read(fifo_A_Sextans_0__read), - .fifo_in_peek_read(), - .fifo_out_0_din(fifo_A_pe_Sextans_0__din), - .fifo_out_0_full_n(fifo_A_pe_Sextans_0__full_n), - .fifo_out_0_write(fifo_A_pe_Sextans_0__write), - .fifo_out_1_din(fifo_A_pe_Sextans_1__din), - .fifo_out_1_full_n(fifo_A_pe_Sextans_1__full_n), - .fifo_out_1_write(fifo_A_pe_Sextans_1__write) - ); - - - (* keep_hierarchy = "yes" *) Scatter_1_2 - Scatter_1_2_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Scatter_1_2_1__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_A_Sextans_1__dout), - .fifo_in_peek_dout(fifo_A_Sextans_1__dout), - .fifo_in_s_empty_n(fifo_A_Sextans_1__empty_n), - .fifo_in_peek_empty_n(fifo_A_Sextans_1__empty_n), - .fifo_in_s_read(fifo_A_Sextans_1__read), - .fifo_in_peek_read(), - .fifo_out_0_din(fifo_A_pe_Sextans_2__din), - .fifo_out_0_full_n(fifo_A_pe_Sextans_2__full_n), - .fifo_out_0_write(fifo_A_pe_Sextans_2__write), - .fifo_out_1_din(fifo_A_pe_Sextans_3__din), - .fifo_out_1_full_n(fifo_A_pe_Sextans_3__full_n), - .fifo_out_1_write(fifo_A_pe_Sextans_3__write) - ); - - - (* keep_hierarchy = "yes" *) Scatter_1_2 - Scatter_1_2_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Scatter_1_2_2__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_A_Sextans_2__dout), - .fifo_in_peek_dout(fifo_A_Sextans_2__dout), - .fifo_in_s_empty_n(fifo_A_Sextans_2__empty_n), - .fifo_in_peek_empty_n(fifo_A_Sextans_2__empty_n), - .fifo_in_s_read(fifo_A_Sextans_2__read), - .fifo_in_peek_read(), - .fifo_out_0_din(fifo_A_pe_Sextans_4__din), - .fifo_out_0_full_n(fifo_A_pe_Sextans_4__full_n), - .fifo_out_0_write(fifo_A_pe_Sextans_4__write), - .fifo_out_1_din(fifo_A_pe_Sextans_5__din), - .fifo_out_1_full_n(fifo_A_pe_Sextans_5__full_n), - .fifo_out_1_write(fifo_A_pe_Sextans_5__write) - ); - - - (* keep_hierarchy = "yes" *) Scatter_1_2 - Scatter_1_2_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Scatter_1_2_3__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_A_Sextans_3__dout), - .fifo_in_peek_dout(fifo_A_Sextans_3__dout), - .fifo_in_s_empty_n(fifo_A_Sextans_3__empty_n), - .fifo_in_peek_empty_n(fifo_A_Sextans_3__empty_n), - .fifo_in_s_read(fifo_A_Sextans_3__read), - .fifo_in_peek_read(), - .fifo_out_0_din(fifo_A_pe_Sextans_6__din), - .fifo_out_0_full_n(fifo_A_pe_Sextans_6__full_n), - .fifo_out_0_write(fifo_A_pe_Sextans_6__write), - .fifo_out_1_din(fifo_A_pe_Sextans_7__din), - .fifo_out_1_full_n(fifo_A_pe_Sextans_7__full_n), - .fifo_out_1_write(fifo_A_pe_Sextans_7__write) - ); - - - (* keep_hierarchy = "yes" *) Scatter_1_2 - Scatter_1_2_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Scatter_1_2_4__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_A_Sextans_4__dout), - .fifo_in_peek_dout(fifo_A_Sextans_4__dout), - .fifo_in_s_empty_n(fifo_A_Sextans_4__empty_n), - .fifo_in_peek_empty_n(fifo_A_Sextans_4__empty_n), - .fifo_in_s_read(fifo_A_Sextans_4__read), - .fifo_in_peek_read(), - .fifo_out_0_din(fifo_A_pe_Sextans_8__din), - .fifo_out_0_full_n(fifo_A_pe_Sextans_8__full_n), - .fifo_out_0_write(fifo_A_pe_Sextans_8__write), - .fifo_out_1_din(fifo_A_pe_Sextans_9__din), - .fifo_out_1_full_n(fifo_A_pe_Sextans_9__full_n), - .fifo_out_1_write(fifo_A_pe_Sextans_9__write) - ); - - - (* keep_hierarchy = "yes" *) Scatter_1_2 - Scatter_1_2_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Scatter_1_2_5__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_A_Sextans_5__dout), - .fifo_in_peek_dout(fifo_A_Sextans_5__dout), - .fifo_in_s_empty_n(fifo_A_Sextans_5__empty_n), - .fifo_in_peek_empty_n(fifo_A_Sextans_5__empty_n), - .fifo_in_s_read(fifo_A_Sextans_5__read), - .fifo_in_peek_read(), - .fifo_out_0_din(fifo_A_pe_Sextans_10__din), - .fifo_out_0_full_n(fifo_A_pe_Sextans_10__full_n), - .fifo_out_0_write(fifo_A_pe_Sextans_10__write), - .fifo_out_1_din(fifo_A_pe_Sextans_11__din), - .fifo_out_1_full_n(fifo_A_pe_Sextans_11__full_n), - .fifo_out_1_write(fifo_A_pe_Sextans_11__write) - ); - - - (* keep_hierarchy = "yes" *) Scatter_1_2 - Scatter_1_2_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Scatter_1_2_6__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_A_Sextans_6__dout), - .fifo_in_peek_dout(fifo_A_Sextans_6__dout), - .fifo_in_s_empty_n(fifo_A_Sextans_6__empty_n), - .fifo_in_peek_empty_n(fifo_A_Sextans_6__empty_n), - .fifo_in_s_read(fifo_A_Sextans_6__read), - .fifo_in_peek_read(), - .fifo_out_0_din(fifo_A_pe_Sextans_12__din), - .fifo_out_0_full_n(fifo_A_pe_Sextans_12__full_n), - .fifo_out_0_write(fifo_A_pe_Sextans_12__write), - .fifo_out_1_din(fifo_A_pe_Sextans_13__din), - .fifo_out_1_full_n(fifo_A_pe_Sextans_13__full_n), - .fifo_out_1_write(fifo_A_pe_Sextans_13__write) - ); - - - (* keep_hierarchy = "yes" *) Scatter_1_2 - Scatter_1_2_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(Scatter_1_2_7__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_A_Sextans_7__dout), - .fifo_in_peek_dout(fifo_A_Sextans_7__dout), - .fifo_in_s_empty_n(fifo_A_Sextans_7__empty_n), - .fifo_in_peek_empty_n(fifo_A_Sextans_7__empty_n), - .fifo_in_s_read(fifo_A_Sextans_7__read), - .fifo_in_peek_read(), - .fifo_out_0_din(fifo_A_pe_Sextans_14__din), - .fifo_out_0_full_n(fifo_A_pe_Sextans_14__full_n), - .fifo_out_0_write(fifo_A_pe_Sextans_14__write), - .fifo_out_1_din(fifo_A_pe_Sextans_15__din), - .fifo_out_1_full_n(fifo_A_pe_Sextans_15__full_n), - .fifo_out_1_write(fifo_A_pe_Sextans_15__write) - ); - - - (* keep_hierarchy = "yes" *) black_hole_float_v16 - black_hole_float_v16_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(black_hole_float_v16_0__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_B_pe_Sextans_64__dout), - .fifo_in_peek_dout(fifo_B_pe_Sextans_64__dout), - .fifo_in_s_empty_n(fifo_B_pe_Sextans_64__empty_n), - .fifo_in_peek_empty_n(fifo_B_pe_Sextans_64__empty_n), - .fifo_in_s_read(fifo_B_pe_Sextans_64__read), - .fifo_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) black_hole_float_v16 - black_hole_float_v16_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(black_hole_float_v16_1__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_B_pe_Sextans_65__dout), - .fifo_in_peek_dout(fifo_B_pe_Sextans_65__dout), - .fifo_in_s_empty_n(fifo_B_pe_Sextans_65__empty_n), - .fifo_in_peek_empty_n(fifo_B_pe_Sextans_65__empty_n), - .fifo_in_s_read(fifo_B_pe_Sextans_65__read), - .fifo_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) black_hole_float_v16 - black_hole_float_v16_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(black_hole_float_v16_2__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_B_pe_Sextans_66__dout), - .fifo_in_peek_dout(fifo_B_pe_Sextans_66__dout), - .fifo_in_s_empty_n(fifo_B_pe_Sextans_66__empty_n), - .fifo_in_peek_empty_n(fifo_B_pe_Sextans_66__empty_n), - .fifo_in_s_read(fifo_B_pe_Sextans_66__read), - .fifo_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) black_hole_float_v16 - black_hole_float_v16_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(black_hole_float_v16_3__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_B_pe_Sextans_67__dout), - .fifo_in_peek_dout(fifo_B_pe_Sextans_67__dout), - .fifo_in_s_empty_n(fifo_B_pe_Sextans_67__empty_n), - .fifo_in_peek_empty_n(fifo_B_pe_Sextans_67__empty_n), - .fifo_in_s_read(fifo_B_pe_Sextans_67__read), - .fifo_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) black_hole_int - black_hole_int_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(black_hole_int_0__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(PE_inst_Sextans_16__dout), - .fifo_in_peek_dout(PE_inst_Sextans_16__dout), - .fifo_in_s_empty_n(PE_inst_Sextans_16__empty_n), - .fifo_in_peek_empty_n(PE_inst_Sextans_16__empty_n), - .fifo_in_s_read(PE_inst_Sextans_16__read), - .fifo_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) black_hole_int - black_hole_int_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(black_hole_int_1__ap_start), - .ap_done(), - .ap_idle(), - .ap_ready(), - .fifo_in_s_dout(fifo_edge_list_ptr_Sextans_16__dout), - .fifo_in_peek_dout(fifo_edge_list_ptr_Sextans_16__dout), - .fifo_in_s_empty_n(fifo_edge_list_ptr_Sextans_16__empty_n), - .fifo_in_peek_empty_n(fifo_edge_list_ptr_Sextans_16__empty_n), - .fifo_in_s_read(fifo_edge_list_ptr_Sextans_16__read), - .fifo_in_peek_read() - ); - - - (* keep_hierarchy = "yes" *) read_A - read_A_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_A_0__ap_start), - .ap_done(read_A_0__ap_done), - .ap_idle(read_A_0__ap_idle), - .ap_ready(read_A_0__ap_ready), - .A_len(read_A_0___NUM_A_LEN__q0), - .P_N(read_A_0___P_N__q0), - .A_read_addr_din(edge_list_ch_0_read_addr__din), - .A_read_addr_full_n(edge_list_ch_0_read_addr__full_n), - .A_read_addr_write(edge_list_ch_0_read_addr__write), - .A_read_data_s_dout({1'b0, edge_list_ch_0_read_data__dout}), - .A_read_data_peek_dout({1'b0, edge_list_ch_0_read_data__dout}), - .A_read_data_s_empty_n(edge_list_ch_0_read_data__empty_n), - .A_read_data_peek_empty_n(edge_list_ch_0_read_data__empty_n), - .A_read_data_s_read(edge_list_ch_0_read_data__read), - .A_read_data_peek_read(), - .A_write_addr_din(edge_list_ch_0_write_addr__din), - .A_write_addr_full_n(edge_list_ch_0_write_addr__full_n), - .A_write_addr_write(edge_list_ch_0_write_addr__write), - .A_write_data_din(edge_list_ch_0_write_data__din), - .A_write_data_full_n(edge_list_ch_0_write_data__full_n), - .A_write_data_write(edge_list_ch_0_write_data__write), - .A_write_resp_s_dout({1'b0, edge_list_ch_0_write_resp__dout}), - .A_write_resp_peek_dout({1'b0, edge_list_ch_0_write_resp__dout}), - .A_write_resp_s_empty_n(edge_list_ch_0_write_resp__empty_n), - .A_write_resp_peek_empty_n(edge_list_ch_0_write_resp__empty_n), - .A_write_resp_s_read(edge_list_ch_0_write_resp__read), - .A_write_resp_peek_read(), - .fifo_A_din(fifo_A_Sextans_0__din), - .fifo_A_full_n(fifo_A_Sextans_0__full_n), - .fifo_A_write(fifo_A_Sextans_0__write) - ); - - - (* keep_hierarchy = "yes" *) read_A - read_A_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_A_1__ap_start), - .ap_done(read_A_1__ap_done), - .ap_idle(read_A_1__ap_idle), - .ap_ready(read_A_1__ap_ready), - .A_len(read_A_1___NUM_A_LEN__q0), - .P_N(read_A_1___P_N__q0), - .A_read_addr_din(edge_list_ch_1_read_addr__din), - .A_read_addr_full_n(edge_list_ch_1_read_addr__full_n), - .A_read_addr_write(edge_list_ch_1_read_addr__write), - .A_read_data_s_dout({1'b0, edge_list_ch_1_read_data__dout}), - .A_read_data_peek_dout({1'b0, edge_list_ch_1_read_data__dout}), - .A_read_data_s_empty_n(edge_list_ch_1_read_data__empty_n), - .A_read_data_peek_empty_n(edge_list_ch_1_read_data__empty_n), - .A_read_data_s_read(edge_list_ch_1_read_data__read), - .A_read_data_peek_read(), - .A_write_addr_din(edge_list_ch_1_write_addr__din), - .A_write_addr_full_n(edge_list_ch_1_write_addr__full_n), - .A_write_addr_write(edge_list_ch_1_write_addr__write), - .A_write_data_din(edge_list_ch_1_write_data__din), - .A_write_data_full_n(edge_list_ch_1_write_data__full_n), - .A_write_data_write(edge_list_ch_1_write_data__write), - .A_write_resp_s_dout({1'b0, edge_list_ch_1_write_resp__dout}), - .A_write_resp_peek_dout({1'b0, edge_list_ch_1_write_resp__dout}), - .A_write_resp_s_empty_n(edge_list_ch_1_write_resp__empty_n), - .A_write_resp_peek_empty_n(edge_list_ch_1_write_resp__empty_n), - .A_write_resp_s_read(edge_list_ch_1_write_resp__read), - .A_write_resp_peek_read(), - .fifo_A_din(fifo_A_Sextans_1__din), - .fifo_A_full_n(fifo_A_Sextans_1__full_n), - .fifo_A_write(fifo_A_Sextans_1__write) - ); - - - (* keep_hierarchy = "yes" *) read_A - read_A_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_A_2__ap_start), - .ap_done(read_A_2__ap_done), - .ap_idle(read_A_2__ap_idle), - .ap_ready(read_A_2__ap_ready), - .A_len(read_A_2___NUM_A_LEN__q0), - .P_N(read_A_2___P_N__q0), - .A_read_addr_din(edge_list_ch_2_read_addr__din), - .A_read_addr_full_n(edge_list_ch_2_read_addr__full_n), - .A_read_addr_write(edge_list_ch_2_read_addr__write), - .A_read_data_s_dout({1'b0, edge_list_ch_2_read_data__dout}), - .A_read_data_peek_dout({1'b0, edge_list_ch_2_read_data__dout}), - .A_read_data_s_empty_n(edge_list_ch_2_read_data__empty_n), - .A_read_data_peek_empty_n(edge_list_ch_2_read_data__empty_n), - .A_read_data_s_read(edge_list_ch_2_read_data__read), - .A_read_data_peek_read(), - .A_write_addr_din(edge_list_ch_2_write_addr__din), - .A_write_addr_full_n(edge_list_ch_2_write_addr__full_n), - .A_write_addr_write(edge_list_ch_2_write_addr__write), - .A_write_data_din(edge_list_ch_2_write_data__din), - .A_write_data_full_n(edge_list_ch_2_write_data__full_n), - .A_write_data_write(edge_list_ch_2_write_data__write), - .A_write_resp_s_dout({1'b0, edge_list_ch_2_write_resp__dout}), - .A_write_resp_peek_dout({1'b0, edge_list_ch_2_write_resp__dout}), - .A_write_resp_s_empty_n(edge_list_ch_2_write_resp__empty_n), - .A_write_resp_peek_empty_n(edge_list_ch_2_write_resp__empty_n), - .A_write_resp_s_read(edge_list_ch_2_write_resp__read), - .A_write_resp_peek_read(), - .fifo_A_din(fifo_A_Sextans_2__din), - .fifo_A_full_n(fifo_A_Sextans_2__full_n), - .fifo_A_write(fifo_A_Sextans_2__write) - ); - - - (* keep_hierarchy = "yes" *) read_A - read_A_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_A_3__ap_start), - .ap_done(read_A_3__ap_done), - .ap_idle(read_A_3__ap_idle), - .ap_ready(read_A_3__ap_ready), - .A_len(read_A_3___NUM_A_LEN__q0), - .P_N(read_A_3___P_N__q0), - .A_read_addr_din(edge_list_ch_3_read_addr__din), - .A_read_addr_full_n(edge_list_ch_3_read_addr__full_n), - .A_read_addr_write(edge_list_ch_3_read_addr__write), - .A_read_data_s_dout({1'b0, edge_list_ch_3_read_data__dout}), - .A_read_data_peek_dout({1'b0, edge_list_ch_3_read_data__dout}), - .A_read_data_s_empty_n(edge_list_ch_3_read_data__empty_n), - .A_read_data_peek_empty_n(edge_list_ch_3_read_data__empty_n), - .A_read_data_s_read(edge_list_ch_3_read_data__read), - .A_read_data_peek_read(), - .A_write_addr_din(edge_list_ch_3_write_addr__din), - .A_write_addr_full_n(edge_list_ch_3_write_addr__full_n), - .A_write_addr_write(edge_list_ch_3_write_addr__write), - .A_write_data_din(edge_list_ch_3_write_data__din), - .A_write_data_full_n(edge_list_ch_3_write_data__full_n), - .A_write_data_write(edge_list_ch_3_write_data__write), - .A_write_resp_s_dout({1'b0, edge_list_ch_3_write_resp__dout}), - .A_write_resp_peek_dout({1'b0, edge_list_ch_3_write_resp__dout}), - .A_write_resp_s_empty_n(edge_list_ch_3_write_resp__empty_n), - .A_write_resp_peek_empty_n(edge_list_ch_3_write_resp__empty_n), - .A_write_resp_s_read(edge_list_ch_3_write_resp__read), - .A_write_resp_peek_read(), - .fifo_A_din(fifo_A_Sextans_3__din), - .fifo_A_full_n(fifo_A_Sextans_3__full_n), - .fifo_A_write(fifo_A_Sextans_3__write) - ); - - - (* keep_hierarchy = "yes" *) read_A - read_A_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_A_4__ap_start), - .ap_done(read_A_4__ap_done), - .ap_idle(read_A_4__ap_idle), - .ap_ready(read_A_4__ap_ready), - .A_len(read_A_4___NUM_A_LEN__q0), - .P_N(read_A_4___P_N__q0), - .A_read_addr_din(edge_list_ch_4_read_addr__din), - .A_read_addr_full_n(edge_list_ch_4_read_addr__full_n), - .A_read_addr_write(edge_list_ch_4_read_addr__write), - .A_read_data_s_dout({1'b0, edge_list_ch_4_read_data__dout}), - .A_read_data_peek_dout({1'b0, edge_list_ch_4_read_data__dout}), - .A_read_data_s_empty_n(edge_list_ch_4_read_data__empty_n), - .A_read_data_peek_empty_n(edge_list_ch_4_read_data__empty_n), - .A_read_data_s_read(edge_list_ch_4_read_data__read), - .A_read_data_peek_read(), - .A_write_addr_din(edge_list_ch_4_write_addr__din), - .A_write_addr_full_n(edge_list_ch_4_write_addr__full_n), - .A_write_addr_write(edge_list_ch_4_write_addr__write), - .A_write_data_din(edge_list_ch_4_write_data__din), - .A_write_data_full_n(edge_list_ch_4_write_data__full_n), - .A_write_data_write(edge_list_ch_4_write_data__write), - .A_write_resp_s_dout({1'b0, edge_list_ch_4_write_resp__dout}), - .A_write_resp_peek_dout({1'b0, edge_list_ch_4_write_resp__dout}), - .A_write_resp_s_empty_n(edge_list_ch_4_write_resp__empty_n), - .A_write_resp_peek_empty_n(edge_list_ch_4_write_resp__empty_n), - .A_write_resp_s_read(edge_list_ch_4_write_resp__read), - .A_write_resp_peek_read(), - .fifo_A_din(fifo_A_Sextans_4__din), - .fifo_A_full_n(fifo_A_Sextans_4__full_n), - .fifo_A_write(fifo_A_Sextans_4__write) - ); - - - (* keep_hierarchy = "yes" *) read_A - read_A_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_A_5__ap_start), - .ap_done(read_A_5__ap_done), - .ap_idle(read_A_5__ap_idle), - .ap_ready(read_A_5__ap_ready), - .A_len(read_A_5___NUM_A_LEN__q0), - .P_N(read_A_5___P_N__q0), - .A_read_addr_din(edge_list_ch_5_read_addr__din), - .A_read_addr_full_n(edge_list_ch_5_read_addr__full_n), - .A_read_addr_write(edge_list_ch_5_read_addr__write), - .A_read_data_s_dout({1'b0, edge_list_ch_5_read_data__dout}), - .A_read_data_peek_dout({1'b0, edge_list_ch_5_read_data__dout}), - .A_read_data_s_empty_n(edge_list_ch_5_read_data__empty_n), - .A_read_data_peek_empty_n(edge_list_ch_5_read_data__empty_n), - .A_read_data_s_read(edge_list_ch_5_read_data__read), - .A_read_data_peek_read(), - .A_write_addr_din(edge_list_ch_5_write_addr__din), - .A_write_addr_full_n(edge_list_ch_5_write_addr__full_n), - .A_write_addr_write(edge_list_ch_5_write_addr__write), - .A_write_data_din(edge_list_ch_5_write_data__din), - .A_write_data_full_n(edge_list_ch_5_write_data__full_n), - .A_write_data_write(edge_list_ch_5_write_data__write), - .A_write_resp_s_dout({1'b0, edge_list_ch_5_write_resp__dout}), - .A_write_resp_peek_dout({1'b0, edge_list_ch_5_write_resp__dout}), - .A_write_resp_s_empty_n(edge_list_ch_5_write_resp__empty_n), - .A_write_resp_peek_empty_n(edge_list_ch_5_write_resp__empty_n), - .A_write_resp_s_read(edge_list_ch_5_write_resp__read), - .A_write_resp_peek_read(), - .fifo_A_din(fifo_A_Sextans_5__din), - .fifo_A_full_n(fifo_A_Sextans_5__full_n), - .fifo_A_write(fifo_A_Sextans_5__write) - ); - - - (* keep_hierarchy = "yes" *) read_A - read_A_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_A_6__ap_start), - .ap_done(read_A_6__ap_done), - .ap_idle(read_A_6__ap_idle), - .ap_ready(read_A_6__ap_ready), - .A_len(read_A_6___NUM_A_LEN__q0), - .P_N(read_A_6___P_N__q0), - .A_read_addr_din(edge_list_ch_6_read_addr__din), - .A_read_addr_full_n(edge_list_ch_6_read_addr__full_n), - .A_read_addr_write(edge_list_ch_6_read_addr__write), - .A_read_data_s_dout({1'b0, edge_list_ch_6_read_data__dout}), - .A_read_data_peek_dout({1'b0, edge_list_ch_6_read_data__dout}), - .A_read_data_s_empty_n(edge_list_ch_6_read_data__empty_n), - .A_read_data_peek_empty_n(edge_list_ch_6_read_data__empty_n), - .A_read_data_s_read(edge_list_ch_6_read_data__read), - .A_read_data_peek_read(), - .A_write_addr_din(edge_list_ch_6_write_addr__din), - .A_write_addr_full_n(edge_list_ch_6_write_addr__full_n), - .A_write_addr_write(edge_list_ch_6_write_addr__write), - .A_write_data_din(edge_list_ch_6_write_data__din), - .A_write_data_full_n(edge_list_ch_6_write_data__full_n), - .A_write_data_write(edge_list_ch_6_write_data__write), - .A_write_resp_s_dout({1'b0, edge_list_ch_6_write_resp__dout}), - .A_write_resp_peek_dout({1'b0, edge_list_ch_6_write_resp__dout}), - .A_write_resp_s_empty_n(edge_list_ch_6_write_resp__empty_n), - .A_write_resp_peek_empty_n(edge_list_ch_6_write_resp__empty_n), - .A_write_resp_s_read(edge_list_ch_6_write_resp__read), - .A_write_resp_peek_read(), - .fifo_A_din(fifo_A_Sextans_6__din), - .fifo_A_full_n(fifo_A_Sextans_6__full_n), - .fifo_A_write(fifo_A_Sextans_6__write) - ); - - - (* keep_hierarchy = "yes" *) read_A - read_A_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_A_7__ap_start), - .ap_done(read_A_7__ap_done), - .ap_idle(read_A_7__ap_idle), - .ap_ready(read_A_7__ap_ready), - .A_len(read_A_7___NUM_A_LEN__q0), - .P_N(read_A_7___P_N__q0), - .A_read_addr_din(edge_list_ch_7_read_addr__din), - .A_read_addr_full_n(edge_list_ch_7_read_addr__full_n), - .A_read_addr_write(edge_list_ch_7_read_addr__write), - .A_read_data_s_dout({1'b0, edge_list_ch_7_read_data__dout}), - .A_read_data_peek_dout({1'b0, edge_list_ch_7_read_data__dout}), - .A_read_data_s_empty_n(edge_list_ch_7_read_data__empty_n), - .A_read_data_peek_empty_n(edge_list_ch_7_read_data__empty_n), - .A_read_data_s_read(edge_list_ch_7_read_data__read), - .A_read_data_peek_read(), - .A_write_addr_din(edge_list_ch_7_write_addr__din), - .A_write_addr_full_n(edge_list_ch_7_write_addr__full_n), - .A_write_addr_write(edge_list_ch_7_write_addr__write), - .A_write_data_din(edge_list_ch_7_write_data__din), - .A_write_data_full_n(edge_list_ch_7_write_data__full_n), - .A_write_data_write(edge_list_ch_7_write_data__write), - .A_write_resp_s_dout({1'b0, edge_list_ch_7_write_resp__dout}), - .A_write_resp_peek_dout({1'b0, edge_list_ch_7_write_resp__dout}), - .A_write_resp_s_empty_n(edge_list_ch_7_write_resp__empty_n), - .A_write_resp_peek_empty_n(edge_list_ch_7_write_resp__empty_n), - .A_write_resp_s_read(edge_list_ch_7_write_resp__read), - .A_write_resp_peek_read(), - .fifo_A_din(fifo_A_Sextans_7__din), - .fifo_A_full_n(fifo_A_Sextans_7__full_n), - .fifo_A_write(fifo_A_Sextans_7__write) - ); - - - (* keep_hierarchy = "yes" *) read_B - read_B_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_B_0__ap_start), - .ap_done(read_B_0__ap_done), - .ap_idle(read_B_0__ap_idle), - .ap_ready(read_B_0__ap_ready), - .K(read_B_0___K__q0), - .P_N(read_B_0___P_N__q0), - .fifo_B_din(fifo_B_pe_Sextans_0__din), - .fifo_B_full_n(fifo_B_pe_Sextans_0__full_n), - .fifo_B_write(fifo_B_pe_Sextans_0__write), - .B_read_addr_din(mat_B_ch_0_read_addr__din), - .B_read_addr_full_n(mat_B_ch_0_read_addr__full_n), - .B_read_addr_write(mat_B_ch_0_read_addr__write), - .B_read_data_s_dout({1'b0, mat_B_ch_0_read_data__dout}), - .B_read_data_peek_dout({1'b0, mat_B_ch_0_read_data__dout}), - .B_read_data_s_empty_n(mat_B_ch_0_read_data__empty_n), - .B_read_data_peek_empty_n(mat_B_ch_0_read_data__empty_n), - .B_read_data_s_read(mat_B_ch_0_read_data__read), - .B_read_data_peek_read(), - .B_write_addr_din(mat_B_ch_0_write_addr__din), - .B_write_addr_full_n(mat_B_ch_0_write_addr__full_n), - .B_write_addr_write(mat_B_ch_0_write_addr__write), - .B_write_data_din(mat_B_ch_0_write_data__din), - .B_write_data_full_n(mat_B_ch_0_write_data__full_n), - .B_write_data_write(mat_B_ch_0_write_data__write), - .B_write_resp_s_dout({1'b0, mat_B_ch_0_write_resp__dout}), - .B_write_resp_peek_dout({1'b0, mat_B_ch_0_write_resp__dout}), - .B_write_resp_s_empty_n(mat_B_ch_0_write_resp__empty_n), - .B_write_resp_peek_empty_n(mat_B_ch_0_write_resp__empty_n), - .B_write_resp_s_read(mat_B_ch_0_write_resp__read), - .B_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) read_B - read_B_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_B_1__ap_start), - .ap_done(read_B_1__ap_done), - .ap_idle(read_B_1__ap_idle), - .ap_ready(read_B_1__ap_ready), - .K(read_B_1___K__q0), - .P_N(read_B_1___P_N__q0), - .fifo_B_din(fifo_B_pe_Sextans_1__din), - .fifo_B_full_n(fifo_B_pe_Sextans_1__full_n), - .fifo_B_write(fifo_B_pe_Sextans_1__write), - .B_read_addr_din(mat_B_ch_1_read_addr__din), - .B_read_addr_full_n(mat_B_ch_1_read_addr__full_n), - .B_read_addr_write(mat_B_ch_1_read_addr__write), - .B_read_data_s_dout({1'b0, mat_B_ch_1_read_data__dout}), - .B_read_data_peek_dout({1'b0, mat_B_ch_1_read_data__dout}), - .B_read_data_s_empty_n(mat_B_ch_1_read_data__empty_n), - .B_read_data_peek_empty_n(mat_B_ch_1_read_data__empty_n), - .B_read_data_s_read(mat_B_ch_1_read_data__read), - .B_read_data_peek_read(), - .B_write_addr_din(mat_B_ch_1_write_addr__din), - .B_write_addr_full_n(mat_B_ch_1_write_addr__full_n), - .B_write_addr_write(mat_B_ch_1_write_addr__write), - .B_write_data_din(mat_B_ch_1_write_data__din), - .B_write_data_full_n(mat_B_ch_1_write_data__full_n), - .B_write_data_write(mat_B_ch_1_write_data__write), - .B_write_resp_s_dout({1'b0, mat_B_ch_1_write_resp__dout}), - .B_write_resp_peek_dout({1'b0, mat_B_ch_1_write_resp__dout}), - .B_write_resp_s_empty_n(mat_B_ch_1_write_resp__empty_n), - .B_write_resp_peek_empty_n(mat_B_ch_1_write_resp__empty_n), - .B_write_resp_s_read(mat_B_ch_1_write_resp__read), - .B_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) read_B - read_B_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_B_2__ap_start), - .ap_done(read_B_2__ap_done), - .ap_idle(read_B_2__ap_idle), - .ap_ready(read_B_2__ap_ready), - .K(read_B_2___K__q0), - .P_N(read_B_2___P_N__q0), - .fifo_B_din(fifo_B_pe_Sextans_2__din), - .fifo_B_full_n(fifo_B_pe_Sextans_2__full_n), - .fifo_B_write(fifo_B_pe_Sextans_2__write), - .B_read_addr_din(mat_B_ch_2_read_addr__din), - .B_read_addr_full_n(mat_B_ch_2_read_addr__full_n), - .B_read_addr_write(mat_B_ch_2_read_addr__write), - .B_read_data_s_dout({1'b0, mat_B_ch_2_read_data__dout}), - .B_read_data_peek_dout({1'b0, mat_B_ch_2_read_data__dout}), - .B_read_data_s_empty_n(mat_B_ch_2_read_data__empty_n), - .B_read_data_peek_empty_n(mat_B_ch_2_read_data__empty_n), - .B_read_data_s_read(mat_B_ch_2_read_data__read), - .B_read_data_peek_read(), - .B_write_addr_din(mat_B_ch_2_write_addr__din), - .B_write_addr_full_n(mat_B_ch_2_write_addr__full_n), - .B_write_addr_write(mat_B_ch_2_write_addr__write), - .B_write_data_din(mat_B_ch_2_write_data__din), - .B_write_data_full_n(mat_B_ch_2_write_data__full_n), - .B_write_data_write(mat_B_ch_2_write_data__write), - .B_write_resp_s_dout({1'b0, mat_B_ch_2_write_resp__dout}), - .B_write_resp_peek_dout({1'b0, mat_B_ch_2_write_resp__dout}), - .B_write_resp_s_empty_n(mat_B_ch_2_write_resp__empty_n), - .B_write_resp_peek_empty_n(mat_B_ch_2_write_resp__empty_n), - .B_write_resp_s_read(mat_B_ch_2_write_resp__read), - .B_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) read_B - read_B_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_B_3__ap_start), - .ap_done(read_B_3__ap_done), - .ap_idle(read_B_3__ap_idle), - .ap_ready(read_B_3__ap_ready), - .K(read_B_3___K__q0), - .P_N(read_B_3___P_N__q0), - .fifo_B_din(fifo_B_pe_Sextans_3__din), - .fifo_B_full_n(fifo_B_pe_Sextans_3__full_n), - .fifo_B_write(fifo_B_pe_Sextans_3__write), - .B_read_addr_din(mat_B_ch_3_read_addr__din), - .B_read_addr_full_n(mat_B_ch_3_read_addr__full_n), - .B_read_addr_write(mat_B_ch_3_read_addr__write), - .B_read_data_s_dout({1'b0, mat_B_ch_3_read_data__dout}), - .B_read_data_peek_dout({1'b0, mat_B_ch_3_read_data__dout}), - .B_read_data_s_empty_n(mat_B_ch_3_read_data__empty_n), - .B_read_data_peek_empty_n(mat_B_ch_3_read_data__empty_n), - .B_read_data_s_read(mat_B_ch_3_read_data__read), - .B_read_data_peek_read(), - .B_write_addr_din(mat_B_ch_3_write_addr__din), - .B_write_addr_full_n(mat_B_ch_3_write_addr__full_n), - .B_write_addr_write(mat_B_ch_3_write_addr__write), - .B_write_data_din(mat_B_ch_3_write_data__din), - .B_write_data_full_n(mat_B_ch_3_write_data__full_n), - .B_write_data_write(mat_B_ch_3_write_data__write), - .B_write_resp_s_dout({1'b0, mat_B_ch_3_write_resp__dout}), - .B_write_resp_peek_dout({1'b0, mat_B_ch_3_write_resp__dout}), - .B_write_resp_s_empty_n(mat_B_ch_3_write_resp__empty_n), - .B_write_resp_peek_empty_n(mat_B_ch_3_write_resp__empty_n), - .B_write_resp_s_read(mat_B_ch_3_write_resp__read), - .B_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) read_C - read_C_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_C_0__ap_start), - .ap_done(read_C_0__ap_done), - .ap_idle(read_C_0__ap_idle), - .ap_ready(read_C_0__ap_ready), - .M(read_C_0___M__q0), - .P_N(read_C_0___P_N__q0), - .fifo_C_din(fifo_C_read_in_Sextans_0__din), - .fifo_C_full_n(fifo_C_read_in_Sextans_0__full_n), - .fifo_C_write(fifo_C_read_in_Sextans_0__write), - .C_read_addr_din(mat_C_ch_in_0_read_addr__din), - .C_read_addr_full_n(mat_C_ch_in_0_read_addr__full_n), - .C_read_addr_write(mat_C_ch_in_0_read_addr__write), - .C_read_data_s_dout({1'b0, mat_C_ch_in_0_read_data__dout}), - .C_read_data_peek_dout({1'b0, mat_C_ch_in_0_read_data__dout}), - .C_read_data_s_empty_n(mat_C_ch_in_0_read_data__empty_n), - .C_read_data_peek_empty_n(mat_C_ch_in_0_read_data__empty_n), - .C_read_data_s_read(mat_C_ch_in_0_read_data__read), - .C_read_data_peek_read(), - .C_write_addr_din(mat_C_ch_in_0_write_addr__din), - .C_write_addr_full_n(mat_C_ch_in_0_write_addr__full_n), - .C_write_addr_write(mat_C_ch_in_0_write_addr__write), - .C_write_data_din(mat_C_ch_in_0_write_data__din), - .C_write_data_full_n(mat_C_ch_in_0_write_data__full_n), - .C_write_data_write(mat_C_ch_in_0_write_data__write), - .C_write_resp_s_dout({1'b0, mat_C_ch_in_0_write_resp__dout}), - .C_write_resp_peek_dout({1'b0, mat_C_ch_in_0_write_resp__dout}), - .C_write_resp_s_empty_n(mat_C_ch_in_0_write_resp__empty_n), - .C_write_resp_peek_empty_n(mat_C_ch_in_0_write_resp__empty_n), - .C_write_resp_s_read(mat_C_ch_in_0_write_resp__read), - .C_write_resp_peek_read(), - .wrC_inst_din(wrC_inst_Sextans_0__din), - .wrC_inst_full_n(wrC_inst_Sextans_0__full_n), - .wrC_inst_write(wrC_inst_Sextans_0__write) - ); - - - (* keep_hierarchy = "yes" *) read_C - read_C_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_C_1__ap_start), - .ap_done(read_C_1__ap_done), - .ap_idle(read_C_1__ap_idle), - .ap_ready(read_C_1__ap_ready), - .M(read_C_1___M__q0), - .P_N(read_C_1___P_N__q0), - .fifo_C_din(fifo_C_read_in_Sextans_1__din), - .fifo_C_full_n(fifo_C_read_in_Sextans_1__full_n), - .fifo_C_write(fifo_C_read_in_Sextans_1__write), - .C_read_addr_din(mat_C_ch_in_1_read_addr__din), - .C_read_addr_full_n(mat_C_ch_in_1_read_addr__full_n), - .C_read_addr_write(mat_C_ch_in_1_read_addr__write), - .C_read_data_s_dout({1'b0, mat_C_ch_in_1_read_data__dout}), - .C_read_data_peek_dout({1'b0, mat_C_ch_in_1_read_data__dout}), - .C_read_data_s_empty_n(mat_C_ch_in_1_read_data__empty_n), - .C_read_data_peek_empty_n(mat_C_ch_in_1_read_data__empty_n), - .C_read_data_s_read(mat_C_ch_in_1_read_data__read), - .C_read_data_peek_read(), - .C_write_addr_din(mat_C_ch_in_1_write_addr__din), - .C_write_addr_full_n(mat_C_ch_in_1_write_addr__full_n), - .C_write_addr_write(mat_C_ch_in_1_write_addr__write), - .C_write_data_din(mat_C_ch_in_1_write_data__din), - .C_write_data_full_n(mat_C_ch_in_1_write_data__full_n), - .C_write_data_write(mat_C_ch_in_1_write_data__write), - .C_write_resp_s_dout({1'b0, mat_C_ch_in_1_write_resp__dout}), - .C_write_resp_peek_dout({1'b0, mat_C_ch_in_1_write_resp__dout}), - .C_write_resp_s_empty_n(mat_C_ch_in_1_write_resp__empty_n), - .C_write_resp_peek_empty_n(mat_C_ch_in_1_write_resp__empty_n), - .C_write_resp_s_read(mat_C_ch_in_1_write_resp__read), - .C_write_resp_peek_read(), - .wrC_inst_din(wrC_inst_Sextans_1__din), - .wrC_inst_full_n(wrC_inst_Sextans_1__full_n), - .wrC_inst_write(wrC_inst_Sextans_1__write) - ); - - - (* keep_hierarchy = "yes" *) read_C - read_C_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_C_2__ap_start), - .ap_done(read_C_2__ap_done), - .ap_idle(read_C_2__ap_idle), - .ap_ready(read_C_2__ap_ready), - .M(read_C_2___M__q0), - .P_N(read_C_2___P_N__q0), - .fifo_C_din(fifo_C_read_in_Sextans_2__din), - .fifo_C_full_n(fifo_C_read_in_Sextans_2__full_n), - .fifo_C_write(fifo_C_read_in_Sextans_2__write), - .C_read_addr_din(mat_C_ch_in_2_read_addr__din), - .C_read_addr_full_n(mat_C_ch_in_2_read_addr__full_n), - .C_read_addr_write(mat_C_ch_in_2_read_addr__write), - .C_read_data_s_dout({1'b0, mat_C_ch_in_2_read_data__dout}), - .C_read_data_peek_dout({1'b0, mat_C_ch_in_2_read_data__dout}), - .C_read_data_s_empty_n(mat_C_ch_in_2_read_data__empty_n), - .C_read_data_peek_empty_n(mat_C_ch_in_2_read_data__empty_n), - .C_read_data_s_read(mat_C_ch_in_2_read_data__read), - .C_read_data_peek_read(), - .C_write_addr_din(mat_C_ch_in_2_write_addr__din), - .C_write_addr_full_n(mat_C_ch_in_2_write_addr__full_n), - .C_write_addr_write(mat_C_ch_in_2_write_addr__write), - .C_write_data_din(mat_C_ch_in_2_write_data__din), - .C_write_data_full_n(mat_C_ch_in_2_write_data__full_n), - .C_write_data_write(mat_C_ch_in_2_write_data__write), - .C_write_resp_s_dout({1'b0, mat_C_ch_in_2_write_resp__dout}), - .C_write_resp_peek_dout({1'b0, mat_C_ch_in_2_write_resp__dout}), - .C_write_resp_s_empty_n(mat_C_ch_in_2_write_resp__empty_n), - .C_write_resp_peek_empty_n(mat_C_ch_in_2_write_resp__empty_n), - .C_write_resp_s_read(mat_C_ch_in_2_write_resp__read), - .C_write_resp_peek_read(), - .wrC_inst_din(wrC_inst_Sextans_2__din), - .wrC_inst_full_n(wrC_inst_Sextans_2__full_n), - .wrC_inst_write(wrC_inst_Sextans_2__write) - ); - - - (* keep_hierarchy = "yes" *) read_C - read_C_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_C_3__ap_start), - .ap_done(read_C_3__ap_done), - .ap_idle(read_C_3__ap_idle), - .ap_ready(read_C_3__ap_ready), - .M(read_C_3___M__q0), - .P_N(read_C_3___P_N__q0), - .fifo_C_din(fifo_C_read_in_Sextans_3__din), - .fifo_C_full_n(fifo_C_read_in_Sextans_3__full_n), - .fifo_C_write(fifo_C_read_in_Sextans_3__write), - .C_read_addr_din(mat_C_ch_in_3_read_addr__din), - .C_read_addr_full_n(mat_C_ch_in_3_read_addr__full_n), - .C_read_addr_write(mat_C_ch_in_3_read_addr__write), - .C_read_data_s_dout({1'b0, mat_C_ch_in_3_read_data__dout}), - .C_read_data_peek_dout({1'b0, mat_C_ch_in_3_read_data__dout}), - .C_read_data_s_empty_n(mat_C_ch_in_3_read_data__empty_n), - .C_read_data_peek_empty_n(mat_C_ch_in_3_read_data__empty_n), - .C_read_data_s_read(mat_C_ch_in_3_read_data__read), - .C_read_data_peek_read(), - .C_write_addr_din(mat_C_ch_in_3_write_addr__din), - .C_write_addr_full_n(mat_C_ch_in_3_write_addr__full_n), - .C_write_addr_write(mat_C_ch_in_3_write_addr__write), - .C_write_data_din(mat_C_ch_in_3_write_data__din), - .C_write_data_full_n(mat_C_ch_in_3_write_data__full_n), - .C_write_data_write(mat_C_ch_in_3_write_data__write), - .C_write_resp_s_dout({1'b0, mat_C_ch_in_3_write_resp__dout}), - .C_write_resp_peek_dout({1'b0, mat_C_ch_in_3_write_resp__dout}), - .C_write_resp_s_empty_n(mat_C_ch_in_3_write_resp__empty_n), - .C_write_resp_peek_empty_n(mat_C_ch_in_3_write_resp__empty_n), - .C_write_resp_s_read(mat_C_ch_in_3_write_resp__read), - .C_write_resp_peek_read(), - .wrC_inst_din(wrC_inst_Sextans_3__din), - .wrC_inst_full_n(wrC_inst_Sextans_3__full_n), - .wrC_inst_write(wrC_inst_Sextans_3__write) - ); - - - (* keep_hierarchy = "yes" *) read_C - read_C_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_C_4__ap_start), - .ap_done(read_C_4__ap_done), - .ap_idle(read_C_4__ap_idle), - .ap_ready(read_C_4__ap_ready), - .M(read_C_4___M__q0), - .P_N(read_C_4___P_N__q0), - .fifo_C_din(fifo_C_read_in_Sextans_4__din), - .fifo_C_full_n(fifo_C_read_in_Sextans_4__full_n), - .fifo_C_write(fifo_C_read_in_Sextans_4__write), - .C_read_addr_din(mat_C_ch_in_4_read_addr__din), - .C_read_addr_full_n(mat_C_ch_in_4_read_addr__full_n), - .C_read_addr_write(mat_C_ch_in_4_read_addr__write), - .C_read_data_s_dout({1'b0, mat_C_ch_in_4_read_data__dout}), - .C_read_data_peek_dout({1'b0, mat_C_ch_in_4_read_data__dout}), - .C_read_data_s_empty_n(mat_C_ch_in_4_read_data__empty_n), - .C_read_data_peek_empty_n(mat_C_ch_in_4_read_data__empty_n), - .C_read_data_s_read(mat_C_ch_in_4_read_data__read), - .C_read_data_peek_read(), - .C_write_addr_din(mat_C_ch_in_4_write_addr__din), - .C_write_addr_full_n(mat_C_ch_in_4_write_addr__full_n), - .C_write_addr_write(mat_C_ch_in_4_write_addr__write), - .C_write_data_din(mat_C_ch_in_4_write_data__din), - .C_write_data_full_n(mat_C_ch_in_4_write_data__full_n), - .C_write_data_write(mat_C_ch_in_4_write_data__write), - .C_write_resp_s_dout({1'b0, mat_C_ch_in_4_write_resp__dout}), - .C_write_resp_peek_dout({1'b0, mat_C_ch_in_4_write_resp__dout}), - .C_write_resp_s_empty_n(mat_C_ch_in_4_write_resp__empty_n), - .C_write_resp_peek_empty_n(mat_C_ch_in_4_write_resp__empty_n), - .C_write_resp_s_read(mat_C_ch_in_4_write_resp__read), - .C_write_resp_peek_read(), - .wrC_inst_din(wrC_inst_Sextans_4__din), - .wrC_inst_full_n(wrC_inst_Sextans_4__full_n), - .wrC_inst_write(wrC_inst_Sextans_4__write) - ); - - - (* keep_hierarchy = "yes" *) read_C - read_C_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_C_5__ap_start), - .ap_done(read_C_5__ap_done), - .ap_idle(read_C_5__ap_idle), - .ap_ready(read_C_5__ap_ready), - .M(read_C_5___M__q0), - .P_N(read_C_5___P_N__q0), - .fifo_C_din(fifo_C_read_in_Sextans_5__din), - .fifo_C_full_n(fifo_C_read_in_Sextans_5__full_n), - .fifo_C_write(fifo_C_read_in_Sextans_5__write), - .C_read_addr_din(mat_C_ch_in_5_read_addr__din), - .C_read_addr_full_n(mat_C_ch_in_5_read_addr__full_n), - .C_read_addr_write(mat_C_ch_in_5_read_addr__write), - .C_read_data_s_dout({1'b0, mat_C_ch_in_5_read_data__dout}), - .C_read_data_peek_dout({1'b0, mat_C_ch_in_5_read_data__dout}), - .C_read_data_s_empty_n(mat_C_ch_in_5_read_data__empty_n), - .C_read_data_peek_empty_n(mat_C_ch_in_5_read_data__empty_n), - .C_read_data_s_read(mat_C_ch_in_5_read_data__read), - .C_read_data_peek_read(), - .C_write_addr_din(mat_C_ch_in_5_write_addr__din), - .C_write_addr_full_n(mat_C_ch_in_5_write_addr__full_n), - .C_write_addr_write(mat_C_ch_in_5_write_addr__write), - .C_write_data_din(mat_C_ch_in_5_write_data__din), - .C_write_data_full_n(mat_C_ch_in_5_write_data__full_n), - .C_write_data_write(mat_C_ch_in_5_write_data__write), - .C_write_resp_s_dout({1'b0, mat_C_ch_in_5_write_resp__dout}), - .C_write_resp_peek_dout({1'b0, mat_C_ch_in_5_write_resp__dout}), - .C_write_resp_s_empty_n(mat_C_ch_in_5_write_resp__empty_n), - .C_write_resp_peek_empty_n(mat_C_ch_in_5_write_resp__empty_n), - .C_write_resp_s_read(mat_C_ch_in_5_write_resp__read), - .C_write_resp_peek_read(), - .wrC_inst_din(wrC_inst_Sextans_5__din), - .wrC_inst_full_n(wrC_inst_Sextans_5__full_n), - .wrC_inst_write(wrC_inst_Sextans_5__write) - ); - - - (* keep_hierarchy = "yes" *) read_C - read_C_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_C_6__ap_start), - .ap_done(read_C_6__ap_done), - .ap_idle(read_C_6__ap_idle), - .ap_ready(read_C_6__ap_ready), - .M(read_C_6___M__q0), - .P_N(read_C_6___P_N__q0), - .fifo_C_din(fifo_C_read_in_Sextans_6__din), - .fifo_C_full_n(fifo_C_read_in_Sextans_6__full_n), - .fifo_C_write(fifo_C_read_in_Sextans_6__write), - .C_read_addr_din(mat_C_ch_in_6_read_addr__din), - .C_read_addr_full_n(mat_C_ch_in_6_read_addr__full_n), - .C_read_addr_write(mat_C_ch_in_6_read_addr__write), - .C_read_data_s_dout({1'b0, mat_C_ch_in_6_read_data__dout}), - .C_read_data_peek_dout({1'b0, mat_C_ch_in_6_read_data__dout}), - .C_read_data_s_empty_n(mat_C_ch_in_6_read_data__empty_n), - .C_read_data_peek_empty_n(mat_C_ch_in_6_read_data__empty_n), - .C_read_data_s_read(mat_C_ch_in_6_read_data__read), - .C_read_data_peek_read(), - .C_write_addr_din(mat_C_ch_in_6_write_addr__din), - .C_write_addr_full_n(mat_C_ch_in_6_write_addr__full_n), - .C_write_addr_write(mat_C_ch_in_6_write_addr__write), - .C_write_data_din(mat_C_ch_in_6_write_data__din), - .C_write_data_full_n(mat_C_ch_in_6_write_data__full_n), - .C_write_data_write(mat_C_ch_in_6_write_data__write), - .C_write_resp_s_dout({1'b0, mat_C_ch_in_6_write_resp__dout}), - .C_write_resp_peek_dout({1'b0, mat_C_ch_in_6_write_resp__dout}), - .C_write_resp_s_empty_n(mat_C_ch_in_6_write_resp__empty_n), - .C_write_resp_peek_empty_n(mat_C_ch_in_6_write_resp__empty_n), - .C_write_resp_s_read(mat_C_ch_in_6_write_resp__read), - .C_write_resp_peek_read(), - .wrC_inst_din(wrC_inst_Sextans_6__din), - .wrC_inst_full_n(wrC_inst_Sextans_6__full_n), - .wrC_inst_write(wrC_inst_Sextans_6__write) - ); - - - (* keep_hierarchy = "yes" *) read_C - read_C_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_C_7__ap_start), - .ap_done(read_C_7__ap_done), - .ap_idle(read_C_7__ap_idle), - .ap_ready(read_C_7__ap_ready), - .M(read_C_7___M__q0), - .P_N(read_C_7___P_N__q0), - .fifo_C_din(fifo_C_read_in_Sextans_7__din), - .fifo_C_full_n(fifo_C_read_in_Sextans_7__full_n), - .fifo_C_write(fifo_C_read_in_Sextans_7__write), - .C_read_addr_din(mat_C_ch_in_7_read_addr__din), - .C_read_addr_full_n(mat_C_ch_in_7_read_addr__full_n), - .C_read_addr_write(mat_C_ch_in_7_read_addr__write), - .C_read_data_s_dout({1'b0, mat_C_ch_in_7_read_data__dout}), - .C_read_data_peek_dout({1'b0, mat_C_ch_in_7_read_data__dout}), - .C_read_data_s_empty_n(mat_C_ch_in_7_read_data__empty_n), - .C_read_data_peek_empty_n(mat_C_ch_in_7_read_data__empty_n), - .C_read_data_s_read(mat_C_ch_in_7_read_data__read), - .C_read_data_peek_read(), - .C_write_addr_din(mat_C_ch_in_7_write_addr__din), - .C_write_addr_full_n(mat_C_ch_in_7_write_addr__full_n), - .C_write_addr_write(mat_C_ch_in_7_write_addr__write), - .C_write_data_din(mat_C_ch_in_7_write_data__din), - .C_write_data_full_n(mat_C_ch_in_7_write_data__full_n), - .C_write_data_write(mat_C_ch_in_7_write_data__write), - .C_write_resp_s_dout({1'b0, mat_C_ch_in_7_write_resp__dout}), - .C_write_resp_peek_dout({1'b0, mat_C_ch_in_7_write_resp__dout}), - .C_write_resp_s_empty_n(mat_C_ch_in_7_write_resp__empty_n), - .C_write_resp_peek_empty_n(mat_C_ch_in_7_write_resp__empty_n), - .C_write_resp_s_read(mat_C_ch_in_7_write_resp__read), - .C_write_resp_peek_read(), - .wrC_inst_din(wrC_inst_Sextans_7__din), - .wrC_inst_full_n(wrC_inst_Sextans_7__full_n), - .wrC_inst_write(wrC_inst_Sextans_7__write) - ); - - - (* keep_hierarchy = "yes" *) read_edge_list_ptr - read_edge_list_ptr_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(read_edge_list_ptr_0__ap_start), - .ap_done(read_edge_list_ptr_0__ap_done), - .ap_idle(read_edge_list_ptr_0__ap_idle), - .ap_ready(read_edge_list_ptr_0__ap_ready), - .K(read_edge_list_ptr_0___K__q0), - .M(read_edge_list_ptr_0___M__q0), - .num_ite(read_edge_list_ptr_0___NUM_ITE__q0), - .PE_inst_din(PE_inst_Sextans_0__din), - .PE_inst_full_n(PE_inst_Sextans_0__full_n), - .PE_inst_write(PE_inst_Sextans_0__write), - .P_N(read_edge_list_ptr_0___P_N__q0), - .edge_list_ptr_read_addr_din(edge_list_ptr_read_addr__din), - .edge_list_ptr_read_addr_full_n(edge_list_ptr_read_addr__full_n), - .edge_list_ptr_read_addr_write(edge_list_ptr_read_addr__write), - .edge_list_ptr_read_data_s_dout({1'b0, edge_list_ptr_read_data__dout}), - .edge_list_ptr_read_data_peek_dout({1'b0, edge_list_ptr_read_data__dout}), - .edge_list_ptr_read_data_s_empty_n(edge_list_ptr_read_data__empty_n), - .edge_list_ptr_read_data_peek_empty_n(edge_list_ptr_read_data__empty_n), - .edge_list_ptr_read_data_s_read(edge_list_ptr_read_data__read), - .edge_list_ptr_read_data_peek_read(), - .edge_list_ptr_write_addr_din(edge_list_ptr_write_addr__din), - .edge_list_ptr_write_addr_full_n(edge_list_ptr_write_addr__full_n), - .edge_list_ptr_write_addr_write(edge_list_ptr_write_addr__write), - .edge_list_ptr_write_data_din(edge_list_ptr_write_data__din), - .edge_list_ptr_write_data_full_n(edge_list_ptr_write_data__full_n), - .edge_list_ptr_write_data_write(edge_list_ptr_write_data__write), - .edge_list_ptr_write_resp_s_dout({1'b0, edge_list_ptr_write_resp__dout}), - .edge_list_ptr_write_resp_peek_dout({1'b0, edge_list_ptr_write_resp__dout}), - .edge_list_ptr_write_resp_s_empty_n(edge_list_ptr_write_resp__empty_n), - .edge_list_ptr_write_resp_peek_empty_n(edge_list_ptr_write_resp__empty_n), - .edge_list_ptr_write_resp_s_read(edge_list_ptr_write_resp__read), - .edge_list_ptr_write_resp_peek_read(), - .fifo_edge_list_ptr_din(fifo_edge_list_ptr_Sextans_0__din), - .fifo_edge_list_ptr_full_n(fifo_edge_list_ptr_Sextans_0__full_n), - .fifo_edge_list_ptr_write(fifo_edge_list_ptr_Sextans_0__write) - ); - - - (* keep_hierarchy = "yes" *) write_C - write_C_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(write_C_0__ap_start), - .ap_done(write_C_0__ap_done), - .ap_idle(write_C_0__ap_idle), - .ap_ready(write_C_0__ap_ready), - .fifo_C_s_dout(fifo_C_ch_Sextans_0__dout), - .fifo_C_peek_dout(fifo_C_ch_Sextans_0__dout), - .fifo_C_s_empty_n(fifo_C_ch_Sextans_0__empty_n), - .fifo_C_peek_empty_n(fifo_C_ch_Sextans_0__empty_n), - .fifo_C_s_read(fifo_C_ch_Sextans_0__read), - .fifo_C_peek_read(), - .C_out_read_addr_din(mat_C_ch_0_read_addr__din), - .C_out_read_addr_full_n(mat_C_ch_0_read_addr__full_n), - .C_out_read_addr_write(mat_C_ch_0_read_addr__write), - .C_out_read_data_s_dout({1'b0, mat_C_ch_0_read_data__dout}), - .C_out_read_data_peek_dout({1'b0, mat_C_ch_0_read_data__dout}), - .C_out_read_data_s_empty_n(mat_C_ch_0_read_data__empty_n), - .C_out_read_data_peek_empty_n(mat_C_ch_0_read_data__empty_n), - .C_out_read_data_s_read(mat_C_ch_0_read_data__read), - .C_out_read_data_peek_read(), - .C_out_write_addr_din(mat_C_ch_0_write_addr__din), - .C_out_write_addr_full_n(mat_C_ch_0_write_addr__full_n), - .C_out_write_addr_write(mat_C_ch_0_write_addr__write), - .C_out_write_data_din(mat_C_ch_0_write_data__din), - .C_out_write_data_full_n(mat_C_ch_0_write_data__full_n), - .C_out_write_data_write(mat_C_ch_0_write_data__write), - .C_out_write_resp_s_dout({1'b0, mat_C_ch_0_write_resp__dout}), - .C_out_write_resp_peek_dout({1'b0, mat_C_ch_0_write_resp__dout}), - .C_out_write_resp_s_empty_n(mat_C_ch_0_write_resp__empty_n), - .C_out_write_resp_peek_empty_n(mat_C_ch_0_write_resp__empty_n), - .C_out_write_resp_s_read(mat_C_ch_0_write_resp__read), - .C_out_write_resp_peek_read(), - .wrC_inst_s_dout(wrC_inst_Sextans_0__dout), - .wrC_inst_peek_dout(wrC_inst_Sextans_0__dout), - .wrC_inst_s_empty_n(wrC_inst_Sextans_0__empty_n), - .wrC_inst_peek_empty_n(wrC_inst_Sextans_0__empty_n), - .wrC_inst_s_read(wrC_inst_Sextans_0__read), - .wrC_inst_peek_read() - ); - - - (* keep_hierarchy = "yes" *) write_C - write_C_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(write_C_1__ap_start), - .ap_done(write_C_1__ap_done), - .ap_idle(write_C_1__ap_idle), - .ap_ready(write_C_1__ap_ready), - .fifo_C_s_dout(fifo_C_ch_Sextans_1__dout), - .fifo_C_peek_dout(fifo_C_ch_Sextans_1__dout), - .fifo_C_s_empty_n(fifo_C_ch_Sextans_1__empty_n), - .fifo_C_peek_empty_n(fifo_C_ch_Sextans_1__empty_n), - .fifo_C_s_read(fifo_C_ch_Sextans_1__read), - .fifo_C_peek_read(), - .C_out_read_addr_din(mat_C_ch_1_read_addr__din), - .C_out_read_addr_full_n(mat_C_ch_1_read_addr__full_n), - .C_out_read_addr_write(mat_C_ch_1_read_addr__write), - .C_out_read_data_s_dout({1'b0, mat_C_ch_1_read_data__dout}), - .C_out_read_data_peek_dout({1'b0, mat_C_ch_1_read_data__dout}), - .C_out_read_data_s_empty_n(mat_C_ch_1_read_data__empty_n), - .C_out_read_data_peek_empty_n(mat_C_ch_1_read_data__empty_n), - .C_out_read_data_s_read(mat_C_ch_1_read_data__read), - .C_out_read_data_peek_read(), - .C_out_write_addr_din(mat_C_ch_1_write_addr__din), - .C_out_write_addr_full_n(mat_C_ch_1_write_addr__full_n), - .C_out_write_addr_write(mat_C_ch_1_write_addr__write), - .C_out_write_data_din(mat_C_ch_1_write_data__din), - .C_out_write_data_full_n(mat_C_ch_1_write_data__full_n), - .C_out_write_data_write(mat_C_ch_1_write_data__write), - .C_out_write_resp_s_dout({1'b0, mat_C_ch_1_write_resp__dout}), - .C_out_write_resp_peek_dout({1'b0, mat_C_ch_1_write_resp__dout}), - .C_out_write_resp_s_empty_n(mat_C_ch_1_write_resp__empty_n), - .C_out_write_resp_peek_empty_n(mat_C_ch_1_write_resp__empty_n), - .C_out_write_resp_s_read(mat_C_ch_1_write_resp__read), - .C_out_write_resp_peek_read(), - .wrC_inst_s_dout(wrC_inst_Sextans_1__dout), - .wrC_inst_peek_dout(wrC_inst_Sextans_1__dout), - .wrC_inst_s_empty_n(wrC_inst_Sextans_1__empty_n), - .wrC_inst_peek_empty_n(wrC_inst_Sextans_1__empty_n), - .wrC_inst_s_read(wrC_inst_Sextans_1__read), - .wrC_inst_peek_read() - ); - - - (* keep_hierarchy = "yes" *) write_C - write_C_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(write_C_2__ap_start), - .ap_done(write_C_2__ap_done), - .ap_idle(write_C_2__ap_idle), - .ap_ready(write_C_2__ap_ready), - .fifo_C_s_dout(fifo_C_ch_Sextans_2__dout), - .fifo_C_peek_dout(fifo_C_ch_Sextans_2__dout), - .fifo_C_s_empty_n(fifo_C_ch_Sextans_2__empty_n), - .fifo_C_peek_empty_n(fifo_C_ch_Sextans_2__empty_n), - .fifo_C_s_read(fifo_C_ch_Sextans_2__read), - .fifo_C_peek_read(), - .C_out_read_addr_din(mat_C_ch_2_read_addr__din), - .C_out_read_addr_full_n(mat_C_ch_2_read_addr__full_n), - .C_out_read_addr_write(mat_C_ch_2_read_addr__write), - .C_out_read_data_s_dout({1'b0, mat_C_ch_2_read_data__dout}), - .C_out_read_data_peek_dout({1'b0, mat_C_ch_2_read_data__dout}), - .C_out_read_data_s_empty_n(mat_C_ch_2_read_data__empty_n), - .C_out_read_data_peek_empty_n(mat_C_ch_2_read_data__empty_n), - .C_out_read_data_s_read(mat_C_ch_2_read_data__read), - .C_out_read_data_peek_read(), - .C_out_write_addr_din(mat_C_ch_2_write_addr__din), - .C_out_write_addr_full_n(mat_C_ch_2_write_addr__full_n), - .C_out_write_addr_write(mat_C_ch_2_write_addr__write), - .C_out_write_data_din(mat_C_ch_2_write_data__din), - .C_out_write_data_full_n(mat_C_ch_2_write_data__full_n), - .C_out_write_data_write(mat_C_ch_2_write_data__write), - .C_out_write_resp_s_dout({1'b0, mat_C_ch_2_write_resp__dout}), - .C_out_write_resp_peek_dout({1'b0, mat_C_ch_2_write_resp__dout}), - .C_out_write_resp_s_empty_n(mat_C_ch_2_write_resp__empty_n), - .C_out_write_resp_peek_empty_n(mat_C_ch_2_write_resp__empty_n), - .C_out_write_resp_s_read(mat_C_ch_2_write_resp__read), - .C_out_write_resp_peek_read(), - .wrC_inst_s_dout(wrC_inst_Sextans_2__dout), - .wrC_inst_peek_dout(wrC_inst_Sextans_2__dout), - .wrC_inst_s_empty_n(wrC_inst_Sextans_2__empty_n), - .wrC_inst_peek_empty_n(wrC_inst_Sextans_2__empty_n), - .wrC_inst_s_read(wrC_inst_Sextans_2__read), - .wrC_inst_peek_read() - ); - - - (* keep_hierarchy = "yes" *) write_C - write_C_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(write_C_3__ap_start), - .ap_done(write_C_3__ap_done), - .ap_idle(write_C_3__ap_idle), - .ap_ready(write_C_3__ap_ready), - .fifo_C_s_dout(fifo_C_ch_Sextans_3__dout), - .fifo_C_peek_dout(fifo_C_ch_Sextans_3__dout), - .fifo_C_s_empty_n(fifo_C_ch_Sextans_3__empty_n), - .fifo_C_peek_empty_n(fifo_C_ch_Sextans_3__empty_n), - .fifo_C_s_read(fifo_C_ch_Sextans_3__read), - .fifo_C_peek_read(), - .C_out_read_addr_din(mat_C_ch_3_read_addr__din), - .C_out_read_addr_full_n(mat_C_ch_3_read_addr__full_n), - .C_out_read_addr_write(mat_C_ch_3_read_addr__write), - .C_out_read_data_s_dout({1'b0, mat_C_ch_3_read_data__dout}), - .C_out_read_data_peek_dout({1'b0, mat_C_ch_3_read_data__dout}), - .C_out_read_data_s_empty_n(mat_C_ch_3_read_data__empty_n), - .C_out_read_data_peek_empty_n(mat_C_ch_3_read_data__empty_n), - .C_out_read_data_s_read(mat_C_ch_3_read_data__read), - .C_out_read_data_peek_read(), - .C_out_write_addr_din(mat_C_ch_3_write_addr__din), - .C_out_write_addr_full_n(mat_C_ch_3_write_addr__full_n), - .C_out_write_addr_write(mat_C_ch_3_write_addr__write), - .C_out_write_data_din(mat_C_ch_3_write_data__din), - .C_out_write_data_full_n(mat_C_ch_3_write_data__full_n), - .C_out_write_data_write(mat_C_ch_3_write_data__write), - .C_out_write_resp_s_dout({1'b0, mat_C_ch_3_write_resp__dout}), - .C_out_write_resp_peek_dout({1'b0, mat_C_ch_3_write_resp__dout}), - .C_out_write_resp_s_empty_n(mat_C_ch_3_write_resp__empty_n), - .C_out_write_resp_peek_empty_n(mat_C_ch_3_write_resp__empty_n), - .C_out_write_resp_s_read(mat_C_ch_3_write_resp__read), - .C_out_write_resp_peek_read(), - .wrC_inst_s_dout(wrC_inst_Sextans_3__dout), - .wrC_inst_peek_dout(wrC_inst_Sextans_3__dout), - .wrC_inst_s_empty_n(wrC_inst_Sextans_3__empty_n), - .wrC_inst_peek_empty_n(wrC_inst_Sextans_3__empty_n), - .wrC_inst_s_read(wrC_inst_Sextans_3__read), - .wrC_inst_peek_read() - ); - - - (* keep_hierarchy = "yes" *) write_C - write_C_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(write_C_4__ap_start), - .ap_done(write_C_4__ap_done), - .ap_idle(write_C_4__ap_idle), - .ap_ready(write_C_4__ap_ready), - .fifo_C_s_dout(fifo_C_ch_Sextans_4__dout), - .fifo_C_peek_dout(fifo_C_ch_Sextans_4__dout), - .fifo_C_s_empty_n(fifo_C_ch_Sextans_4__empty_n), - .fifo_C_peek_empty_n(fifo_C_ch_Sextans_4__empty_n), - .fifo_C_s_read(fifo_C_ch_Sextans_4__read), - .fifo_C_peek_read(), - .C_out_read_addr_din(mat_C_ch_4_read_addr__din), - .C_out_read_addr_full_n(mat_C_ch_4_read_addr__full_n), - .C_out_read_addr_write(mat_C_ch_4_read_addr__write), - .C_out_read_data_s_dout({1'b0, mat_C_ch_4_read_data__dout}), - .C_out_read_data_peek_dout({1'b0, mat_C_ch_4_read_data__dout}), - .C_out_read_data_s_empty_n(mat_C_ch_4_read_data__empty_n), - .C_out_read_data_peek_empty_n(mat_C_ch_4_read_data__empty_n), - .C_out_read_data_s_read(mat_C_ch_4_read_data__read), - .C_out_read_data_peek_read(), - .C_out_write_addr_din(mat_C_ch_4_write_addr__din), - .C_out_write_addr_full_n(mat_C_ch_4_write_addr__full_n), - .C_out_write_addr_write(mat_C_ch_4_write_addr__write), - .C_out_write_data_din(mat_C_ch_4_write_data__din), - .C_out_write_data_full_n(mat_C_ch_4_write_data__full_n), - .C_out_write_data_write(mat_C_ch_4_write_data__write), - .C_out_write_resp_s_dout({1'b0, mat_C_ch_4_write_resp__dout}), - .C_out_write_resp_peek_dout({1'b0, mat_C_ch_4_write_resp__dout}), - .C_out_write_resp_s_empty_n(mat_C_ch_4_write_resp__empty_n), - .C_out_write_resp_peek_empty_n(mat_C_ch_4_write_resp__empty_n), - .C_out_write_resp_s_read(mat_C_ch_4_write_resp__read), - .C_out_write_resp_peek_read(), - .wrC_inst_s_dout(wrC_inst_Sextans_4__dout), - .wrC_inst_peek_dout(wrC_inst_Sextans_4__dout), - .wrC_inst_s_empty_n(wrC_inst_Sextans_4__empty_n), - .wrC_inst_peek_empty_n(wrC_inst_Sextans_4__empty_n), - .wrC_inst_s_read(wrC_inst_Sextans_4__read), - .wrC_inst_peek_read() - ); - - - (* keep_hierarchy = "yes" *) write_C - write_C_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(write_C_5__ap_start), - .ap_done(write_C_5__ap_done), - .ap_idle(write_C_5__ap_idle), - .ap_ready(write_C_5__ap_ready), - .fifo_C_s_dout(fifo_C_ch_Sextans_5__dout), - .fifo_C_peek_dout(fifo_C_ch_Sextans_5__dout), - .fifo_C_s_empty_n(fifo_C_ch_Sextans_5__empty_n), - .fifo_C_peek_empty_n(fifo_C_ch_Sextans_5__empty_n), - .fifo_C_s_read(fifo_C_ch_Sextans_5__read), - .fifo_C_peek_read(), - .C_out_read_addr_din(mat_C_ch_5_read_addr__din), - .C_out_read_addr_full_n(mat_C_ch_5_read_addr__full_n), - .C_out_read_addr_write(mat_C_ch_5_read_addr__write), - .C_out_read_data_s_dout({1'b0, mat_C_ch_5_read_data__dout}), - .C_out_read_data_peek_dout({1'b0, mat_C_ch_5_read_data__dout}), - .C_out_read_data_s_empty_n(mat_C_ch_5_read_data__empty_n), - .C_out_read_data_peek_empty_n(mat_C_ch_5_read_data__empty_n), - .C_out_read_data_s_read(mat_C_ch_5_read_data__read), - .C_out_read_data_peek_read(), - .C_out_write_addr_din(mat_C_ch_5_write_addr__din), - .C_out_write_addr_full_n(mat_C_ch_5_write_addr__full_n), - .C_out_write_addr_write(mat_C_ch_5_write_addr__write), - .C_out_write_data_din(mat_C_ch_5_write_data__din), - .C_out_write_data_full_n(mat_C_ch_5_write_data__full_n), - .C_out_write_data_write(mat_C_ch_5_write_data__write), - .C_out_write_resp_s_dout({1'b0, mat_C_ch_5_write_resp__dout}), - .C_out_write_resp_peek_dout({1'b0, mat_C_ch_5_write_resp__dout}), - .C_out_write_resp_s_empty_n(mat_C_ch_5_write_resp__empty_n), - .C_out_write_resp_peek_empty_n(mat_C_ch_5_write_resp__empty_n), - .C_out_write_resp_s_read(mat_C_ch_5_write_resp__read), - .C_out_write_resp_peek_read(), - .wrC_inst_s_dout(wrC_inst_Sextans_5__dout), - .wrC_inst_peek_dout(wrC_inst_Sextans_5__dout), - .wrC_inst_s_empty_n(wrC_inst_Sextans_5__empty_n), - .wrC_inst_peek_empty_n(wrC_inst_Sextans_5__empty_n), - .wrC_inst_s_read(wrC_inst_Sextans_5__read), - .wrC_inst_peek_read() - ); - - - (* keep_hierarchy = "yes" *) write_C - write_C_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(write_C_6__ap_start), - .ap_done(write_C_6__ap_done), - .ap_idle(write_C_6__ap_idle), - .ap_ready(write_C_6__ap_ready), - .fifo_C_s_dout(fifo_C_ch_Sextans_6__dout), - .fifo_C_peek_dout(fifo_C_ch_Sextans_6__dout), - .fifo_C_s_empty_n(fifo_C_ch_Sextans_6__empty_n), - .fifo_C_peek_empty_n(fifo_C_ch_Sextans_6__empty_n), - .fifo_C_s_read(fifo_C_ch_Sextans_6__read), - .fifo_C_peek_read(), - .C_out_read_addr_din(mat_C_ch_6_read_addr__din), - .C_out_read_addr_full_n(mat_C_ch_6_read_addr__full_n), - .C_out_read_addr_write(mat_C_ch_6_read_addr__write), - .C_out_read_data_s_dout({1'b0, mat_C_ch_6_read_data__dout}), - .C_out_read_data_peek_dout({1'b0, mat_C_ch_6_read_data__dout}), - .C_out_read_data_s_empty_n(mat_C_ch_6_read_data__empty_n), - .C_out_read_data_peek_empty_n(mat_C_ch_6_read_data__empty_n), - .C_out_read_data_s_read(mat_C_ch_6_read_data__read), - .C_out_read_data_peek_read(), - .C_out_write_addr_din(mat_C_ch_6_write_addr__din), - .C_out_write_addr_full_n(mat_C_ch_6_write_addr__full_n), - .C_out_write_addr_write(mat_C_ch_6_write_addr__write), - .C_out_write_data_din(mat_C_ch_6_write_data__din), - .C_out_write_data_full_n(mat_C_ch_6_write_data__full_n), - .C_out_write_data_write(mat_C_ch_6_write_data__write), - .C_out_write_resp_s_dout({1'b0, mat_C_ch_6_write_resp__dout}), - .C_out_write_resp_peek_dout({1'b0, mat_C_ch_6_write_resp__dout}), - .C_out_write_resp_s_empty_n(mat_C_ch_6_write_resp__empty_n), - .C_out_write_resp_peek_empty_n(mat_C_ch_6_write_resp__empty_n), - .C_out_write_resp_s_read(mat_C_ch_6_write_resp__read), - .C_out_write_resp_peek_read(), - .wrC_inst_s_dout(wrC_inst_Sextans_6__dout), - .wrC_inst_peek_dout(wrC_inst_Sextans_6__dout), - .wrC_inst_s_empty_n(wrC_inst_Sextans_6__empty_n), - .wrC_inst_peek_empty_n(wrC_inst_Sextans_6__empty_n), - .wrC_inst_s_read(wrC_inst_Sextans_6__read), - .wrC_inst_peek_read() - ); - - - (* keep_hierarchy = "yes" *) write_C - write_C_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(write_C_7__ap_start), - .ap_done(write_C_7__ap_done), - .ap_idle(write_C_7__ap_idle), - .ap_ready(write_C_7__ap_ready), - .fifo_C_s_dout(fifo_C_ch_Sextans_7__dout), - .fifo_C_peek_dout(fifo_C_ch_Sextans_7__dout), - .fifo_C_s_empty_n(fifo_C_ch_Sextans_7__empty_n), - .fifo_C_peek_empty_n(fifo_C_ch_Sextans_7__empty_n), - .fifo_C_s_read(fifo_C_ch_Sextans_7__read), - .fifo_C_peek_read(), - .C_out_read_addr_din(mat_C_ch_7_read_addr__din), - .C_out_read_addr_full_n(mat_C_ch_7_read_addr__full_n), - .C_out_read_addr_write(mat_C_ch_7_read_addr__write), - .C_out_read_data_s_dout({1'b0, mat_C_ch_7_read_data__dout}), - .C_out_read_data_peek_dout({1'b0, mat_C_ch_7_read_data__dout}), - .C_out_read_data_s_empty_n(mat_C_ch_7_read_data__empty_n), - .C_out_read_data_peek_empty_n(mat_C_ch_7_read_data__empty_n), - .C_out_read_data_s_read(mat_C_ch_7_read_data__read), - .C_out_read_data_peek_read(), - .C_out_write_addr_din(mat_C_ch_7_write_addr__din), - .C_out_write_addr_full_n(mat_C_ch_7_write_addr__full_n), - .C_out_write_addr_write(mat_C_ch_7_write_addr__write), - .C_out_write_data_din(mat_C_ch_7_write_data__din), - .C_out_write_data_full_n(mat_C_ch_7_write_data__full_n), - .C_out_write_data_write(mat_C_ch_7_write_data__write), - .C_out_write_resp_s_dout({1'b0, mat_C_ch_7_write_resp__dout}), - .C_out_write_resp_peek_dout({1'b0, mat_C_ch_7_write_resp__dout}), - .C_out_write_resp_s_empty_n(mat_C_ch_7_write_resp__empty_n), - .C_out_write_resp_peek_empty_n(mat_C_ch_7_write_resp__empty_n), - .C_out_write_resp_s_read(mat_C_ch_7_write_resp__read), - .C_out_write_resp_peek_read(), - .wrC_inst_s_dout(wrC_inst_Sextans_7__dout), - .wrC_inst_peek_dout(wrC_inst_Sextans_7__dout), - .wrC_inst_s_empty_n(wrC_inst_Sextans_7__empty_n), - .wrC_inst_peek_empty_n(wrC_inst_Sextans_7__empty_n), - .wrC_inst_s_read(wrC_inst_Sextans_7__read), - .wrC_inst_peek_read() - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - edge_list_ch_0__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_A_0___edge_list_ch_0__q0), - .m_axi_ARADDR(m_axi_edge_list_ch_0_ARADDR), - .m_axi_ARBURST(m_axi_edge_list_ch_0_ARBURST), - .m_axi_ARCACHE(m_axi_edge_list_ch_0_ARCACHE), - .m_axi_ARID(m_axi_edge_list_ch_0_ARID), - .m_axi_ARLEN(m_axi_edge_list_ch_0_ARLEN), - .m_axi_ARLOCK(m_axi_edge_list_ch_0_ARLOCK), - .m_axi_ARPROT(m_axi_edge_list_ch_0_ARPROT), - .m_axi_ARQOS(m_axi_edge_list_ch_0_ARQOS), - .m_axi_ARREADY(m_axi_edge_list_ch_0_ARREADY), - .m_axi_ARSIZE(m_axi_edge_list_ch_0_ARSIZE), - .m_axi_ARVALID(m_axi_edge_list_ch_0_ARVALID), - .m_axi_AWADDR(m_axi_edge_list_ch_0_AWADDR), - .m_axi_AWBURST(m_axi_edge_list_ch_0_AWBURST), - .m_axi_AWCACHE(m_axi_edge_list_ch_0_AWCACHE), - .m_axi_AWID(m_axi_edge_list_ch_0_AWID), - .m_axi_AWLEN(m_axi_edge_list_ch_0_AWLEN), - .m_axi_AWLOCK(m_axi_edge_list_ch_0_AWLOCK), - .m_axi_AWPROT(m_axi_edge_list_ch_0_AWPROT), - .m_axi_AWQOS(m_axi_edge_list_ch_0_AWQOS), - .m_axi_AWREADY(m_axi_edge_list_ch_0_AWREADY), - .m_axi_AWSIZE(m_axi_edge_list_ch_0_AWSIZE), - .m_axi_AWVALID(m_axi_edge_list_ch_0_AWVALID), - .m_axi_BID(m_axi_edge_list_ch_0_BID), - .m_axi_BREADY(m_axi_edge_list_ch_0_BREADY), - .m_axi_BRESP(m_axi_edge_list_ch_0_BRESP), - .m_axi_BVALID(m_axi_edge_list_ch_0_BVALID), - .m_axi_RDATA(m_axi_edge_list_ch_0_RDATA), - .m_axi_RID(m_axi_edge_list_ch_0_RID), - .m_axi_RLAST(m_axi_edge_list_ch_0_RLAST), - .m_axi_RREADY(m_axi_edge_list_ch_0_RREADY), - .m_axi_RRESP(m_axi_edge_list_ch_0_RRESP), - .m_axi_RVALID(m_axi_edge_list_ch_0_RVALID), - .m_axi_WDATA(m_axi_edge_list_ch_0_WDATA), - .m_axi_WLAST(m_axi_edge_list_ch_0_WLAST), - .m_axi_WREADY(m_axi_edge_list_ch_0_WREADY), - .m_axi_WSTRB(m_axi_edge_list_ch_0_WSTRB), - .m_axi_WVALID(m_axi_edge_list_ch_0_WVALID), - .read_addr_din(edge_list_ch_0_read_addr__din), - .read_addr_full_n(edge_list_ch_0_read_addr__full_n), - .read_addr_write(edge_list_ch_0_read_addr__write), - .read_data_dout(edge_list_ch_0_read_data__dout), - .read_data_empty_n(edge_list_ch_0_read_data__empty_n), - .read_data_read(edge_list_ch_0_read_data__read), - .write_addr_din(edge_list_ch_0_write_addr__din), - .write_addr_full_n(edge_list_ch_0_write_addr__full_n), - .write_addr_write(edge_list_ch_0_write_addr__write), - .write_data_din(edge_list_ch_0_write_data__din), - .write_data_full_n(edge_list_ch_0_write_data__full_n), - .write_data_write(edge_list_ch_0_write_data__write), - .write_resp_dout(edge_list_ch_0_write_resp__dout), - .write_resp_empty_n(edge_list_ch_0_write_resp__empty_n), - .write_resp_read(edge_list_ch_0_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - edge_list_ch_1__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_A_1___edge_list_ch_1__q0), - .m_axi_ARADDR(m_axi_edge_list_ch_1_ARADDR), - .m_axi_ARBURST(m_axi_edge_list_ch_1_ARBURST), - .m_axi_ARCACHE(m_axi_edge_list_ch_1_ARCACHE), - .m_axi_ARID(m_axi_edge_list_ch_1_ARID), - .m_axi_ARLEN(m_axi_edge_list_ch_1_ARLEN), - .m_axi_ARLOCK(m_axi_edge_list_ch_1_ARLOCK), - .m_axi_ARPROT(m_axi_edge_list_ch_1_ARPROT), - .m_axi_ARQOS(m_axi_edge_list_ch_1_ARQOS), - .m_axi_ARREADY(m_axi_edge_list_ch_1_ARREADY), - .m_axi_ARSIZE(m_axi_edge_list_ch_1_ARSIZE), - .m_axi_ARVALID(m_axi_edge_list_ch_1_ARVALID), - .m_axi_AWADDR(m_axi_edge_list_ch_1_AWADDR), - .m_axi_AWBURST(m_axi_edge_list_ch_1_AWBURST), - .m_axi_AWCACHE(m_axi_edge_list_ch_1_AWCACHE), - .m_axi_AWID(m_axi_edge_list_ch_1_AWID), - .m_axi_AWLEN(m_axi_edge_list_ch_1_AWLEN), - .m_axi_AWLOCK(m_axi_edge_list_ch_1_AWLOCK), - .m_axi_AWPROT(m_axi_edge_list_ch_1_AWPROT), - .m_axi_AWQOS(m_axi_edge_list_ch_1_AWQOS), - .m_axi_AWREADY(m_axi_edge_list_ch_1_AWREADY), - .m_axi_AWSIZE(m_axi_edge_list_ch_1_AWSIZE), - .m_axi_AWVALID(m_axi_edge_list_ch_1_AWVALID), - .m_axi_BID(m_axi_edge_list_ch_1_BID), - .m_axi_BREADY(m_axi_edge_list_ch_1_BREADY), - .m_axi_BRESP(m_axi_edge_list_ch_1_BRESP), - .m_axi_BVALID(m_axi_edge_list_ch_1_BVALID), - .m_axi_RDATA(m_axi_edge_list_ch_1_RDATA), - .m_axi_RID(m_axi_edge_list_ch_1_RID), - .m_axi_RLAST(m_axi_edge_list_ch_1_RLAST), - .m_axi_RREADY(m_axi_edge_list_ch_1_RREADY), - .m_axi_RRESP(m_axi_edge_list_ch_1_RRESP), - .m_axi_RVALID(m_axi_edge_list_ch_1_RVALID), - .m_axi_WDATA(m_axi_edge_list_ch_1_WDATA), - .m_axi_WLAST(m_axi_edge_list_ch_1_WLAST), - .m_axi_WREADY(m_axi_edge_list_ch_1_WREADY), - .m_axi_WSTRB(m_axi_edge_list_ch_1_WSTRB), - .m_axi_WVALID(m_axi_edge_list_ch_1_WVALID), - .read_addr_din(edge_list_ch_1_read_addr__din), - .read_addr_full_n(edge_list_ch_1_read_addr__full_n), - .read_addr_write(edge_list_ch_1_read_addr__write), - .read_data_dout(edge_list_ch_1_read_data__dout), - .read_data_empty_n(edge_list_ch_1_read_data__empty_n), - .read_data_read(edge_list_ch_1_read_data__read), - .write_addr_din(edge_list_ch_1_write_addr__din), - .write_addr_full_n(edge_list_ch_1_write_addr__full_n), - .write_addr_write(edge_list_ch_1_write_addr__write), - .write_data_din(edge_list_ch_1_write_data__din), - .write_data_full_n(edge_list_ch_1_write_data__full_n), - .write_data_write(edge_list_ch_1_write_data__write), - .write_resp_dout(edge_list_ch_1_write_resp__dout), - .write_resp_empty_n(edge_list_ch_1_write_resp__empty_n), - .write_resp_read(edge_list_ch_1_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - edge_list_ch_2__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_A_2___edge_list_ch_2__q0), - .m_axi_ARADDR(m_axi_edge_list_ch_2_ARADDR), - .m_axi_ARBURST(m_axi_edge_list_ch_2_ARBURST), - .m_axi_ARCACHE(m_axi_edge_list_ch_2_ARCACHE), - .m_axi_ARID(m_axi_edge_list_ch_2_ARID), - .m_axi_ARLEN(m_axi_edge_list_ch_2_ARLEN), - .m_axi_ARLOCK(m_axi_edge_list_ch_2_ARLOCK), - .m_axi_ARPROT(m_axi_edge_list_ch_2_ARPROT), - .m_axi_ARQOS(m_axi_edge_list_ch_2_ARQOS), - .m_axi_ARREADY(m_axi_edge_list_ch_2_ARREADY), - .m_axi_ARSIZE(m_axi_edge_list_ch_2_ARSIZE), - .m_axi_ARVALID(m_axi_edge_list_ch_2_ARVALID), - .m_axi_AWADDR(m_axi_edge_list_ch_2_AWADDR), - .m_axi_AWBURST(m_axi_edge_list_ch_2_AWBURST), - .m_axi_AWCACHE(m_axi_edge_list_ch_2_AWCACHE), - .m_axi_AWID(m_axi_edge_list_ch_2_AWID), - .m_axi_AWLEN(m_axi_edge_list_ch_2_AWLEN), - .m_axi_AWLOCK(m_axi_edge_list_ch_2_AWLOCK), - .m_axi_AWPROT(m_axi_edge_list_ch_2_AWPROT), - .m_axi_AWQOS(m_axi_edge_list_ch_2_AWQOS), - .m_axi_AWREADY(m_axi_edge_list_ch_2_AWREADY), - .m_axi_AWSIZE(m_axi_edge_list_ch_2_AWSIZE), - .m_axi_AWVALID(m_axi_edge_list_ch_2_AWVALID), - .m_axi_BID(m_axi_edge_list_ch_2_BID), - .m_axi_BREADY(m_axi_edge_list_ch_2_BREADY), - .m_axi_BRESP(m_axi_edge_list_ch_2_BRESP), - .m_axi_BVALID(m_axi_edge_list_ch_2_BVALID), - .m_axi_RDATA(m_axi_edge_list_ch_2_RDATA), - .m_axi_RID(m_axi_edge_list_ch_2_RID), - .m_axi_RLAST(m_axi_edge_list_ch_2_RLAST), - .m_axi_RREADY(m_axi_edge_list_ch_2_RREADY), - .m_axi_RRESP(m_axi_edge_list_ch_2_RRESP), - .m_axi_RVALID(m_axi_edge_list_ch_2_RVALID), - .m_axi_WDATA(m_axi_edge_list_ch_2_WDATA), - .m_axi_WLAST(m_axi_edge_list_ch_2_WLAST), - .m_axi_WREADY(m_axi_edge_list_ch_2_WREADY), - .m_axi_WSTRB(m_axi_edge_list_ch_2_WSTRB), - .m_axi_WVALID(m_axi_edge_list_ch_2_WVALID), - .read_addr_din(edge_list_ch_2_read_addr__din), - .read_addr_full_n(edge_list_ch_2_read_addr__full_n), - .read_addr_write(edge_list_ch_2_read_addr__write), - .read_data_dout(edge_list_ch_2_read_data__dout), - .read_data_empty_n(edge_list_ch_2_read_data__empty_n), - .read_data_read(edge_list_ch_2_read_data__read), - .write_addr_din(edge_list_ch_2_write_addr__din), - .write_addr_full_n(edge_list_ch_2_write_addr__full_n), - .write_addr_write(edge_list_ch_2_write_addr__write), - .write_data_din(edge_list_ch_2_write_data__din), - .write_data_full_n(edge_list_ch_2_write_data__full_n), - .write_data_write(edge_list_ch_2_write_data__write), - .write_resp_dout(edge_list_ch_2_write_resp__dout), - .write_resp_empty_n(edge_list_ch_2_write_resp__empty_n), - .write_resp_read(edge_list_ch_2_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - edge_list_ch_3__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_A_3___edge_list_ch_3__q0), - .m_axi_ARADDR(m_axi_edge_list_ch_3_ARADDR), - .m_axi_ARBURST(m_axi_edge_list_ch_3_ARBURST), - .m_axi_ARCACHE(m_axi_edge_list_ch_3_ARCACHE), - .m_axi_ARID(m_axi_edge_list_ch_3_ARID), - .m_axi_ARLEN(m_axi_edge_list_ch_3_ARLEN), - .m_axi_ARLOCK(m_axi_edge_list_ch_3_ARLOCK), - .m_axi_ARPROT(m_axi_edge_list_ch_3_ARPROT), - .m_axi_ARQOS(m_axi_edge_list_ch_3_ARQOS), - .m_axi_ARREADY(m_axi_edge_list_ch_3_ARREADY), - .m_axi_ARSIZE(m_axi_edge_list_ch_3_ARSIZE), - .m_axi_ARVALID(m_axi_edge_list_ch_3_ARVALID), - .m_axi_AWADDR(m_axi_edge_list_ch_3_AWADDR), - .m_axi_AWBURST(m_axi_edge_list_ch_3_AWBURST), - .m_axi_AWCACHE(m_axi_edge_list_ch_3_AWCACHE), - .m_axi_AWID(m_axi_edge_list_ch_3_AWID), - .m_axi_AWLEN(m_axi_edge_list_ch_3_AWLEN), - .m_axi_AWLOCK(m_axi_edge_list_ch_3_AWLOCK), - .m_axi_AWPROT(m_axi_edge_list_ch_3_AWPROT), - .m_axi_AWQOS(m_axi_edge_list_ch_3_AWQOS), - .m_axi_AWREADY(m_axi_edge_list_ch_3_AWREADY), - .m_axi_AWSIZE(m_axi_edge_list_ch_3_AWSIZE), - .m_axi_AWVALID(m_axi_edge_list_ch_3_AWVALID), - .m_axi_BID(m_axi_edge_list_ch_3_BID), - .m_axi_BREADY(m_axi_edge_list_ch_3_BREADY), - .m_axi_BRESP(m_axi_edge_list_ch_3_BRESP), - .m_axi_BVALID(m_axi_edge_list_ch_3_BVALID), - .m_axi_RDATA(m_axi_edge_list_ch_3_RDATA), - .m_axi_RID(m_axi_edge_list_ch_3_RID), - .m_axi_RLAST(m_axi_edge_list_ch_3_RLAST), - .m_axi_RREADY(m_axi_edge_list_ch_3_RREADY), - .m_axi_RRESP(m_axi_edge_list_ch_3_RRESP), - .m_axi_RVALID(m_axi_edge_list_ch_3_RVALID), - .m_axi_WDATA(m_axi_edge_list_ch_3_WDATA), - .m_axi_WLAST(m_axi_edge_list_ch_3_WLAST), - .m_axi_WREADY(m_axi_edge_list_ch_3_WREADY), - .m_axi_WSTRB(m_axi_edge_list_ch_3_WSTRB), - .m_axi_WVALID(m_axi_edge_list_ch_3_WVALID), - .read_addr_din(edge_list_ch_3_read_addr__din), - .read_addr_full_n(edge_list_ch_3_read_addr__full_n), - .read_addr_write(edge_list_ch_3_read_addr__write), - .read_data_dout(edge_list_ch_3_read_data__dout), - .read_data_empty_n(edge_list_ch_3_read_data__empty_n), - .read_data_read(edge_list_ch_3_read_data__read), - .write_addr_din(edge_list_ch_3_write_addr__din), - .write_addr_full_n(edge_list_ch_3_write_addr__full_n), - .write_addr_write(edge_list_ch_3_write_addr__write), - .write_data_din(edge_list_ch_3_write_data__din), - .write_data_full_n(edge_list_ch_3_write_data__full_n), - .write_data_write(edge_list_ch_3_write_data__write), - .write_resp_dout(edge_list_ch_3_write_resp__dout), - .write_resp_empty_n(edge_list_ch_3_write_resp__empty_n), - .write_resp_read(edge_list_ch_3_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - edge_list_ch_4__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_A_4___edge_list_ch_4__q0), - .m_axi_ARADDR(m_axi_edge_list_ch_4_ARADDR), - .m_axi_ARBURST(m_axi_edge_list_ch_4_ARBURST), - .m_axi_ARCACHE(m_axi_edge_list_ch_4_ARCACHE), - .m_axi_ARID(m_axi_edge_list_ch_4_ARID), - .m_axi_ARLEN(m_axi_edge_list_ch_4_ARLEN), - .m_axi_ARLOCK(m_axi_edge_list_ch_4_ARLOCK), - .m_axi_ARPROT(m_axi_edge_list_ch_4_ARPROT), - .m_axi_ARQOS(m_axi_edge_list_ch_4_ARQOS), - .m_axi_ARREADY(m_axi_edge_list_ch_4_ARREADY), - .m_axi_ARSIZE(m_axi_edge_list_ch_4_ARSIZE), - .m_axi_ARVALID(m_axi_edge_list_ch_4_ARVALID), - .m_axi_AWADDR(m_axi_edge_list_ch_4_AWADDR), - .m_axi_AWBURST(m_axi_edge_list_ch_4_AWBURST), - .m_axi_AWCACHE(m_axi_edge_list_ch_4_AWCACHE), - .m_axi_AWID(m_axi_edge_list_ch_4_AWID), - .m_axi_AWLEN(m_axi_edge_list_ch_4_AWLEN), - .m_axi_AWLOCK(m_axi_edge_list_ch_4_AWLOCK), - .m_axi_AWPROT(m_axi_edge_list_ch_4_AWPROT), - .m_axi_AWQOS(m_axi_edge_list_ch_4_AWQOS), - .m_axi_AWREADY(m_axi_edge_list_ch_4_AWREADY), - .m_axi_AWSIZE(m_axi_edge_list_ch_4_AWSIZE), - .m_axi_AWVALID(m_axi_edge_list_ch_4_AWVALID), - .m_axi_BID(m_axi_edge_list_ch_4_BID), - .m_axi_BREADY(m_axi_edge_list_ch_4_BREADY), - .m_axi_BRESP(m_axi_edge_list_ch_4_BRESP), - .m_axi_BVALID(m_axi_edge_list_ch_4_BVALID), - .m_axi_RDATA(m_axi_edge_list_ch_4_RDATA), - .m_axi_RID(m_axi_edge_list_ch_4_RID), - .m_axi_RLAST(m_axi_edge_list_ch_4_RLAST), - .m_axi_RREADY(m_axi_edge_list_ch_4_RREADY), - .m_axi_RRESP(m_axi_edge_list_ch_4_RRESP), - .m_axi_RVALID(m_axi_edge_list_ch_4_RVALID), - .m_axi_WDATA(m_axi_edge_list_ch_4_WDATA), - .m_axi_WLAST(m_axi_edge_list_ch_4_WLAST), - .m_axi_WREADY(m_axi_edge_list_ch_4_WREADY), - .m_axi_WSTRB(m_axi_edge_list_ch_4_WSTRB), - .m_axi_WVALID(m_axi_edge_list_ch_4_WVALID), - .read_addr_din(edge_list_ch_4_read_addr__din), - .read_addr_full_n(edge_list_ch_4_read_addr__full_n), - .read_addr_write(edge_list_ch_4_read_addr__write), - .read_data_dout(edge_list_ch_4_read_data__dout), - .read_data_empty_n(edge_list_ch_4_read_data__empty_n), - .read_data_read(edge_list_ch_4_read_data__read), - .write_addr_din(edge_list_ch_4_write_addr__din), - .write_addr_full_n(edge_list_ch_4_write_addr__full_n), - .write_addr_write(edge_list_ch_4_write_addr__write), - .write_data_din(edge_list_ch_4_write_data__din), - .write_data_full_n(edge_list_ch_4_write_data__full_n), - .write_data_write(edge_list_ch_4_write_data__write), - .write_resp_dout(edge_list_ch_4_write_resp__dout), - .write_resp_empty_n(edge_list_ch_4_write_resp__empty_n), - .write_resp_read(edge_list_ch_4_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - edge_list_ch_5__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_A_5___edge_list_ch_5__q0), - .m_axi_ARADDR(m_axi_edge_list_ch_5_ARADDR), - .m_axi_ARBURST(m_axi_edge_list_ch_5_ARBURST), - .m_axi_ARCACHE(m_axi_edge_list_ch_5_ARCACHE), - .m_axi_ARID(m_axi_edge_list_ch_5_ARID), - .m_axi_ARLEN(m_axi_edge_list_ch_5_ARLEN), - .m_axi_ARLOCK(m_axi_edge_list_ch_5_ARLOCK), - .m_axi_ARPROT(m_axi_edge_list_ch_5_ARPROT), - .m_axi_ARQOS(m_axi_edge_list_ch_5_ARQOS), - .m_axi_ARREADY(m_axi_edge_list_ch_5_ARREADY), - .m_axi_ARSIZE(m_axi_edge_list_ch_5_ARSIZE), - .m_axi_ARVALID(m_axi_edge_list_ch_5_ARVALID), - .m_axi_AWADDR(m_axi_edge_list_ch_5_AWADDR), - .m_axi_AWBURST(m_axi_edge_list_ch_5_AWBURST), - .m_axi_AWCACHE(m_axi_edge_list_ch_5_AWCACHE), - .m_axi_AWID(m_axi_edge_list_ch_5_AWID), - .m_axi_AWLEN(m_axi_edge_list_ch_5_AWLEN), - .m_axi_AWLOCK(m_axi_edge_list_ch_5_AWLOCK), - .m_axi_AWPROT(m_axi_edge_list_ch_5_AWPROT), - .m_axi_AWQOS(m_axi_edge_list_ch_5_AWQOS), - .m_axi_AWREADY(m_axi_edge_list_ch_5_AWREADY), - .m_axi_AWSIZE(m_axi_edge_list_ch_5_AWSIZE), - .m_axi_AWVALID(m_axi_edge_list_ch_5_AWVALID), - .m_axi_BID(m_axi_edge_list_ch_5_BID), - .m_axi_BREADY(m_axi_edge_list_ch_5_BREADY), - .m_axi_BRESP(m_axi_edge_list_ch_5_BRESP), - .m_axi_BVALID(m_axi_edge_list_ch_5_BVALID), - .m_axi_RDATA(m_axi_edge_list_ch_5_RDATA), - .m_axi_RID(m_axi_edge_list_ch_5_RID), - .m_axi_RLAST(m_axi_edge_list_ch_5_RLAST), - .m_axi_RREADY(m_axi_edge_list_ch_5_RREADY), - .m_axi_RRESP(m_axi_edge_list_ch_5_RRESP), - .m_axi_RVALID(m_axi_edge_list_ch_5_RVALID), - .m_axi_WDATA(m_axi_edge_list_ch_5_WDATA), - .m_axi_WLAST(m_axi_edge_list_ch_5_WLAST), - .m_axi_WREADY(m_axi_edge_list_ch_5_WREADY), - .m_axi_WSTRB(m_axi_edge_list_ch_5_WSTRB), - .m_axi_WVALID(m_axi_edge_list_ch_5_WVALID), - .read_addr_din(edge_list_ch_5_read_addr__din), - .read_addr_full_n(edge_list_ch_5_read_addr__full_n), - .read_addr_write(edge_list_ch_5_read_addr__write), - .read_data_dout(edge_list_ch_5_read_data__dout), - .read_data_empty_n(edge_list_ch_5_read_data__empty_n), - .read_data_read(edge_list_ch_5_read_data__read), - .write_addr_din(edge_list_ch_5_write_addr__din), - .write_addr_full_n(edge_list_ch_5_write_addr__full_n), - .write_addr_write(edge_list_ch_5_write_addr__write), - .write_data_din(edge_list_ch_5_write_data__din), - .write_data_full_n(edge_list_ch_5_write_data__full_n), - .write_data_write(edge_list_ch_5_write_data__write), - .write_resp_dout(edge_list_ch_5_write_resp__dout), - .write_resp_empty_n(edge_list_ch_5_write_resp__empty_n), - .write_resp_read(edge_list_ch_5_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - edge_list_ch_6__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_A_6___edge_list_ch_6__q0), - .m_axi_ARADDR(m_axi_edge_list_ch_6_ARADDR), - .m_axi_ARBURST(m_axi_edge_list_ch_6_ARBURST), - .m_axi_ARCACHE(m_axi_edge_list_ch_6_ARCACHE), - .m_axi_ARID(m_axi_edge_list_ch_6_ARID), - .m_axi_ARLEN(m_axi_edge_list_ch_6_ARLEN), - .m_axi_ARLOCK(m_axi_edge_list_ch_6_ARLOCK), - .m_axi_ARPROT(m_axi_edge_list_ch_6_ARPROT), - .m_axi_ARQOS(m_axi_edge_list_ch_6_ARQOS), - .m_axi_ARREADY(m_axi_edge_list_ch_6_ARREADY), - .m_axi_ARSIZE(m_axi_edge_list_ch_6_ARSIZE), - .m_axi_ARVALID(m_axi_edge_list_ch_6_ARVALID), - .m_axi_AWADDR(m_axi_edge_list_ch_6_AWADDR), - .m_axi_AWBURST(m_axi_edge_list_ch_6_AWBURST), - .m_axi_AWCACHE(m_axi_edge_list_ch_6_AWCACHE), - .m_axi_AWID(m_axi_edge_list_ch_6_AWID), - .m_axi_AWLEN(m_axi_edge_list_ch_6_AWLEN), - .m_axi_AWLOCK(m_axi_edge_list_ch_6_AWLOCK), - .m_axi_AWPROT(m_axi_edge_list_ch_6_AWPROT), - .m_axi_AWQOS(m_axi_edge_list_ch_6_AWQOS), - .m_axi_AWREADY(m_axi_edge_list_ch_6_AWREADY), - .m_axi_AWSIZE(m_axi_edge_list_ch_6_AWSIZE), - .m_axi_AWVALID(m_axi_edge_list_ch_6_AWVALID), - .m_axi_BID(m_axi_edge_list_ch_6_BID), - .m_axi_BREADY(m_axi_edge_list_ch_6_BREADY), - .m_axi_BRESP(m_axi_edge_list_ch_6_BRESP), - .m_axi_BVALID(m_axi_edge_list_ch_6_BVALID), - .m_axi_RDATA(m_axi_edge_list_ch_6_RDATA), - .m_axi_RID(m_axi_edge_list_ch_6_RID), - .m_axi_RLAST(m_axi_edge_list_ch_6_RLAST), - .m_axi_RREADY(m_axi_edge_list_ch_6_RREADY), - .m_axi_RRESP(m_axi_edge_list_ch_6_RRESP), - .m_axi_RVALID(m_axi_edge_list_ch_6_RVALID), - .m_axi_WDATA(m_axi_edge_list_ch_6_WDATA), - .m_axi_WLAST(m_axi_edge_list_ch_6_WLAST), - .m_axi_WREADY(m_axi_edge_list_ch_6_WREADY), - .m_axi_WSTRB(m_axi_edge_list_ch_6_WSTRB), - .m_axi_WVALID(m_axi_edge_list_ch_6_WVALID), - .read_addr_din(edge_list_ch_6_read_addr__din), - .read_addr_full_n(edge_list_ch_6_read_addr__full_n), - .read_addr_write(edge_list_ch_6_read_addr__write), - .read_data_dout(edge_list_ch_6_read_data__dout), - .read_data_empty_n(edge_list_ch_6_read_data__empty_n), - .read_data_read(edge_list_ch_6_read_data__read), - .write_addr_din(edge_list_ch_6_write_addr__din), - .write_addr_full_n(edge_list_ch_6_write_addr__full_n), - .write_addr_write(edge_list_ch_6_write_addr__write), - .write_data_din(edge_list_ch_6_write_data__din), - .write_data_full_n(edge_list_ch_6_write_data__full_n), - .write_data_write(edge_list_ch_6_write_data__write), - .write_resp_dout(edge_list_ch_6_write_resp__dout), - .write_resp_empty_n(edge_list_ch_6_write_resp__empty_n), - .write_resp_read(edge_list_ch_6_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - edge_list_ch_7__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_A_7___edge_list_ch_7__q0), - .m_axi_ARADDR(m_axi_edge_list_ch_7_ARADDR), - .m_axi_ARBURST(m_axi_edge_list_ch_7_ARBURST), - .m_axi_ARCACHE(m_axi_edge_list_ch_7_ARCACHE), - .m_axi_ARID(m_axi_edge_list_ch_7_ARID), - .m_axi_ARLEN(m_axi_edge_list_ch_7_ARLEN), - .m_axi_ARLOCK(m_axi_edge_list_ch_7_ARLOCK), - .m_axi_ARPROT(m_axi_edge_list_ch_7_ARPROT), - .m_axi_ARQOS(m_axi_edge_list_ch_7_ARQOS), - .m_axi_ARREADY(m_axi_edge_list_ch_7_ARREADY), - .m_axi_ARSIZE(m_axi_edge_list_ch_7_ARSIZE), - .m_axi_ARVALID(m_axi_edge_list_ch_7_ARVALID), - .m_axi_AWADDR(m_axi_edge_list_ch_7_AWADDR), - .m_axi_AWBURST(m_axi_edge_list_ch_7_AWBURST), - .m_axi_AWCACHE(m_axi_edge_list_ch_7_AWCACHE), - .m_axi_AWID(m_axi_edge_list_ch_7_AWID), - .m_axi_AWLEN(m_axi_edge_list_ch_7_AWLEN), - .m_axi_AWLOCK(m_axi_edge_list_ch_7_AWLOCK), - .m_axi_AWPROT(m_axi_edge_list_ch_7_AWPROT), - .m_axi_AWQOS(m_axi_edge_list_ch_7_AWQOS), - .m_axi_AWREADY(m_axi_edge_list_ch_7_AWREADY), - .m_axi_AWSIZE(m_axi_edge_list_ch_7_AWSIZE), - .m_axi_AWVALID(m_axi_edge_list_ch_7_AWVALID), - .m_axi_BID(m_axi_edge_list_ch_7_BID), - .m_axi_BREADY(m_axi_edge_list_ch_7_BREADY), - .m_axi_BRESP(m_axi_edge_list_ch_7_BRESP), - .m_axi_BVALID(m_axi_edge_list_ch_7_BVALID), - .m_axi_RDATA(m_axi_edge_list_ch_7_RDATA), - .m_axi_RID(m_axi_edge_list_ch_7_RID), - .m_axi_RLAST(m_axi_edge_list_ch_7_RLAST), - .m_axi_RREADY(m_axi_edge_list_ch_7_RREADY), - .m_axi_RRESP(m_axi_edge_list_ch_7_RRESP), - .m_axi_RVALID(m_axi_edge_list_ch_7_RVALID), - .m_axi_WDATA(m_axi_edge_list_ch_7_WDATA), - .m_axi_WLAST(m_axi_edge_list_ch_7_WLAST), - .m_axi_WREADY(m_axi_edge_list_ch_7_WREADY), - .m_axi_WSTRB(m_axi_edge_list_ch_7_WSTRB), - .m_axi_WVALID(m_axi_edge_list_ch_7_WVALID), - .read_addr_din(edge_list_ch_7_read_addr__din), - .read_addr_full_n(edge_list_ch_7_read_addr__full_n), - .read_addr_write(edge_list_ch_7_read_addr__write), - .read_data_dout(edge_list_ch_7_read_data__dout), - .read_data_empty_n(edge_list_ch_7_read_data__empty_n), - .read_data_read(edge_list_ch_7_read_data__read), - .write_addr_din(edge_list_ch_7_write_addr__din), - .write_addr_full_n(edge_list_ch_7_write_addr__full_n), - .write_addr_write(edge_list_ch_7_write_addr__write), - .write_data_din(edge_list_ch_7_write_data__din), - .write_data_full_n(edge_list_ch_7_write_data__full_n), - .write_data_write(edge_list_ch_7_write_data__write), - .write_resp_dout(edge_list_ch_7_write_resp__dout), - .write_resp_empty_n(edge_list_ch_7_write_resp__empty_n), - .write_resp_read(edge_list_ch_7_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_B_ch_0__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_B_0___mat_B_ch_0__q0), - .m_axi_ARADDR(m_axi_mat_B_ch_0_ARADDR), - .m_axi_ARBURST(m_axi_mat_B_ch_0_ARBURST), - .m_axi_ARCACHE(m_axi_mat_B_ch_0_ARCACHE), - .m_axi_ARID(m_axi_mat_B_ch_0_ARID), - .m_axi_ARLEN(m_axi_mat_B_ch_0_ARLEN), - .m_axi_ARLOCK(m_axi_mat_B_ch_0_ARLOCK), - .m_axi_ARPROT(m_axi_mat_B_ch_0_ARPROT), - .m_axi_ARQOS(m_axi_mat_B_ch_0_ARQOS), - .m_axi_ARREADY(m_axi_mat_B_ch_0_ARREADY), - .m_axi_ARSIZE(m_axi_mat_B_ch_0_ARSIZE), - .m_axi_ARVALID(m_axi_mat_B_ch_0_ARVALID), - .m_axi_AWADDR(m_axi_mat_B_ch_0_AWADDR), - .m_axi_AWBURST(m_axi_mat_B_ch_0_AWBURST), - .m_axi_AWCACHE(m_axi_mat_B_ch_0_AWCACHE), - .m_axi_AWID(m_axi_mat_B_ch_0_AWID), - .m_axi_AWLEN(m_axi_mat_B_ch_0_AWLEN), - .m_axi_AWLOCK(m_axi_mat_B_ch_0_AWLOCK), - .m_axi_AWPROT(m_axi_mat_B_ch_0_AWPROT), - .m_axi_AWQOS(m_axi_mat_B_ch_0_AWQOS), - .m_axi_AWREADY(m_axi_mat_B_ch_0_AWREADY), - .m_axi_AWSIZE(m_axi_mat_B_ch_0_AWSIZE), - .m_axi_AWVALID(m_axi_mat_B_ch_0_AWVALID), - .m_axi_BID(m_axi_mat_B_ch_0_BID), - .m_axi_BREADY(m_axi_mat_B_ch_0_BREADY), - .m_axi_BRESP(m_axi_mat_B_ch_0_BRESP), - .m_axi_BVALID(m_axi_mat_B_ch_0_BVALID), - .m_axi_RDATA(m_axi_mat_B_ch_0_RDATA), - .m_axi_RID(m_axi_mat_B_ch_0_RID), - .m_axi_RLAST(m_axi_mat_B_ch_0_RLAST), - .m_axi_RREADY(m_axi_mat_B_ch_0_RREADY), - .m_axi_RRESP(m_axi_mat_B_ch_0_RRESP), - .m_axi_RVALID(m_axi_mat_B_ch_0_RVALID), - .m_axi_WDATA(m_axi_mat_B_ch_0_WDATA), - .m_axi_WLAST(m_axi_mat_B_ch_0_WLAST), - .m_axi_WREADY(m_axi_mat_B_ch_0_WREADY), - .m_axi_WSTRB(m_axi_mat_B_ch_0_WSTRB), - .m_axi_WVALID(m_axi_mat_B_ch_0_WVALID), - .read_addr_din(mat_B_ch_0_read_addr__din), - .read_addr_full_n(mat_B_ch_0_read_addr__full_n), - .read_addr_write(mat_B_ch_0_read_addr__write), - .read_data_dout(mat_B_ch_0_read_data__dout), - .read_data_empty_n(mat_B_ch_0_read_data__empty_n), - .read_data_read(mat_B_ch_0_read_data__read), - .write_addr_din(mat_B_ch_0_write_addr__din), - .write_addr_full_n(mat_B_ch_0_write_addr__full_n), - .write_addr_write(mat_B_ch_0_write_addr__write), - .write_data_din(mat_B_ch_0_write_data__din), - .write_data_full_n(mat_B_ch_0_write_data__full_n), - .write_data_write(mat_B_ch_0_write_data__write), - .write_resp_dout(mat_B_ch_0_write_resp__dout), - .write_resp_empty_n(mat_B_ch_0_write_resp__empty_n), - .write_resp_read(mat_B_ch_0_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_B_ch_1__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_B_1___mat_B_ch_1__q0), - .m_axi_ARADDR(m_axi_mat_B_ch_1_ARADDR), - .m_axi_ARBURST(m_axi_mat_B_ch_1_ARBURST), - .m_axi_ARCACHE(m_axi_mat_B_ch_1_ARCACHE), - .m_axi_ARID(m_axi_mat_B_ch_1_ARID), - .m_axi_ARLEN(m_axi_mat_B_ch_1_ARLEN), - .m_axi_ARLOCK(m_axi_mat_B_ch_1_ARLOCK), - .m_axi_ARPROT(m_axi_mat_B_ch_1_ARPROT), - .m_axi_ARQOS(m_axi_mat_B_ch_1_ARQOS), - .m_axi_ARREADY(m_axi_mat_B_ch_1_ARREADY), - .m_axi_ARSIZE(m_axi_mat_B_ch_1_ARSIZE), - .m_axi_ARVALID(m_axi_mat_B_ch_1_ARVALID), - .m_axi_AWADDR(m_axi_mat_B_ch_1_AWADDR), - .m_axi_AWBURST(m_axi_mat_B_ch_1_AWBURST), - .m_axi_AWCACHE(m_axi_mat_B_ch_1_AWCACHE), - .m_axi_AWID(m_axi_mat_B_ch_1_AWID), - .m_axi_AWLEN(m_axi_mat_B_ch_1_AWLEN), - .m_axi_AWLOCK(m_axi_mat_B_ch_1_AWLOCK), - .m_axi_AWPROT(m_axi_mat_B_ch_1_AWPROT), - .m_axi_AWQOS(m_axi_mat_B_ch_1_AWQOS), - .m_axi_AWREADY(m_axi_mat_B_ch_1_AWREADY), - .m_axi_AWSIZE(m_axi_mat_B_ch_1_AWSIZE), - .m_axi_AWVALID(m_axi_mat_B_ch_1_AWVALID), - .m_axi_BID(m_axi_mat_B_ch_1_BID), - .m_axi_BREADY(m_axi_mat_B_ch_1_BREADY), - .m_axi_BRESP(m_axi_mat_B_ch_1_BRESP), - .m_axi_BVALID(m_axi_mat_B_ch_1_BVALID), - .m_axi_RDATA(m_axi_mat_B_ch_1_RDATA), - .m_axi_RID(m_axi_mat_B_ch_1_RID), - .m_axi_RLAST(m_axi_mat_B_ch_1_RLAST), - .m_axi_RREADY(m_axi_mat_B_ch_1_RREADY), - .m_axi_RRESP(m_axi_mat_B_ch_1_RRESP), - .m_axi_RVALID(m_axi_mat_B_ch_1_RVALID), - .m_axi_WDATA(m_axi_mat_B_ch_1_WDATA), - .m_axi_WLAST(m_axi_mat_B_ch_1_WLAST), - .m_axi_WREADY(m_axi_mat_B_ch_1_WREADY), - .m_axi_WSTRB(m_axi_mat_B_ch_1_WSTRB), - .m_axi_WVALID(m_axi_mat_B_ch_1_WVALID), - .read_addr_din(mat_B_ch_1_read_addr__din), - .read_addr_full_n(mat_B_ch_1_read_addr__full_n), - .read_addr_write(mat_B_ch_1_read_addr__write), - .read_data_dout(mat_B_ch_1_read_data__dout), - .read_data_empty_n(mat_B_ch_1_read_data__empty_n), - .read_data_read(mat_B_ch_1_read_data__read), - .write_addr_din(mat_B_ch_1_write_addr__din), - .write_addr_full_n(mat_B_ch_1_write_addr__full_n), - .write_addr_write(mat_B_ch_1_write_addr__write), - .write_data_din(mat_B_ch_1_write_data__din), - .write_data_full_n(mat_B_ch_1_write_data__full_n), - .write_data_write(mat_B_ch_1_write_data__write), - .write_resp_dout(mat_B_ch_1_write_resp__dout), - .write_resp_empty_n(mat_B_ch_1_write_resp__empty_n), - .write_resp_read(mat_B_ch_1_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_B_ch_2__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_B_2___mat_B_ch_2__q0), - .m_axi_ARADDR(m_axi_mat_B_ch_2_ARADDR), - .m_axi_ARBURST(m_axi_mat_B_ch_2_ARBURST), - .m_axi_ARCACHE(m_axi_mat_B_ch_2_ARCACHE), - .m_axi_ARID(m_axi_mat_B_ch_2_ARID), - .m_axi_ARLEN(m_axi_mat_B_ch_2_ARLEN), - .m_axi_ARLOCK(m_axi_mat_B_ch_2_ARLOCK), - .m_axi_ARPROT(m_axi_mat_B_ch_2_ARPROT), - .m_axi_ARQOS(m_axi_mat_B_ch_2_ARQOS), - .m_axi_ARREADY(m_axi_mat_B_ch_2_ARREADY), - .m_axi_ARSIZE(m_axi_mat_B_ch_2_ARSIZE), - .m_axi_ARVALID(m_axi_mat_B_ch_2_ARVALID), - .m_axi_AWADDR(m_axi_mat_B_ch_2_AWADDR), - .m_axi_AWBURST(m_axi_mat_B_ch_2_AWBURST), - .m_axi_AWCACHE(m_axi_mat_B_ch_2_AWCACHE), - .m_axi_AWID(m_axi_mat_B_ch_2_AWID), - .m_axi_AWLEN(m_axi_mat_B_ch_2_AWLEN), - .m_axi_AWLOCK(m_axi_mat_B_ch_2_AWLOCK), - .m_axi_AWPROT(m_axi_mat_B_ch_2_AWPROT), - .m_axi_AWQOS(m_axi_mat_B_ch_2_AWQOS), - .m_axi_AWREADY(m_axi_mat_B_ch_2_AWREADY), - .m_axi_AWSIZE(m_axi_mat_B_ch_2_AWSIZE), - .m_axi_AWVALID(m_axi_mat_B_ch_2_AWVALID), - .m_axi_BID(m_axi_mat_B_ch_2_BID), - .m_axi_BREADY(m_axi_mat_B_ch_2_BREADY), - .m_axi_BRESP(m_axi_mat_B_ch_2_BRESP), - .m_axi_BVALID(m_axi_mat_B_ch_2_BVALID), - .m_axi_RDATA(m_axi_mat_B_ch_2_RDATA), - .m_axi_RID(m_axi_mat_B_ch_2_RID), - .m_axi_RLAST(m_axi_mat_B_ch_2_RLAST), - .m_axi_RREADY(m_axi_mat_B_ch_2_RREADY), - .m_axi_RRESP(m_axi_mat_B_ch_2_RRESP), - .m_axi_RVALID(m_axi_mat_B_ch_2_RVALID), - .m_axi_WDATA(m_axi_mat_B_ch_2_WDATA), - .m_axi_WLAST(m_axi_mat_B_ch_2_WLAST), - .m_axi_WREADY(m_axi_mat_B_ch_2_WREADY), - .m_axi_WSTRB(m_axi_mat_B_ch_2_WSTRB), - .m_axi_WVALID(m_axi_mat_B_ch_2_WVALID), - .read_addr_din(mat_B_ch_2_read_addr__din), - .read_addr_full_n(mat_B_ch_2_read_addr__full_n), - .read_addr_write(mat_B_ch_2_read_addr__write), - .read_data_dout(mat_B_ch_2_read_data__dout), - .read_data_empty_n(mat_B_ch_2_read_data__empty_n), - .read_data_read(mat_B_ch_2_read_data__read), - .write_addr_din(mat_B_ch_2_write_addr__din), - .write_addr_full_n(mat_B_ch_2_write_addr__full_n), - .write_addr_write(mat_B_ch_2_write_addr__write), - .write_data_din(mat_B_ch_2_write_data__din), - .write_data_full_n(mat_B_ch_2_write_data__full_n), - .write_data_write(mat_B_ch_2_write_data__write), - .write_resp_dout(mat_B_ch_2_write_resp__dout), - .write_resp_empty_n(mat_B_ch_2_write_resp__empty_n), - .write_resp_read(mat_B_ch_2_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_B_ch_3__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_B_3___mat_B_ch_3__q0), - .m_axi_ARADDR(m_axi_mat_B_ch_3_ARADDR), - .m_axi_ARBURST(m_axi_mat_B_ch_3_ARBURST), - .m_axi_ARCACHE(m_axi_mat_B_ch_3_ARCACHE), - .m_axi_ARID(m_axi_mat_B_ch_3_ARID), - .m_axi_ARLEN(m_axi_mat_B_ch_3_ARLEN), - .m_axi_ARLOCK(m_axi_mat_B_ch_3_ARLOCK), - .m_axi_ARPROT(m_axi_mat_B_ch_3_ARPROT), - .m_axi_ARQOS(m_axi_mat_B_ch_3_ARQOS), - .m_axi_ARREADY(m_axi_mat_B_ch_3_ARREADY), - .m_axi_ARSIZE(m_axi_mat_B_ch_3_ARSIZE), - .m_axi_ARVALID(m_axi_mat_B_ch_3_ARVALID), - .m_axi_AWADDR(m_axi_mat_B_ch_3_AWADDR), - .m_axi_AWBURST(m_axi_mat_B_ch_3_AWBURST), - .m_axi_AWCACHE(m_axi_mat_B_ch_3_AWCACHE), - .m_axi_AWID(m_axi_mat_B_ch_3_AWID), - .m_axi_AWLEN(m_axi_mat_B_ch_3_AWLEN), - .m_axi_AWLOCK(m_axi_mat_B_ch_3_AWLOCK), - .m_axi_AWPROT(m_axi_mat_B_ch_3_AWPROT), - .m_axi_AWQOS(m_axi_mat_B_ch_3_AWQOS), - .m_axi_AWREADY(m_axi_mat_B_ch_3_AWREADY), - .m_axi_AWSIZE(m_axi_mat_B_ch_3_AWSIZE), - .m_axi_AWVALID(m_axi_mat_B_ch_3_AWVALID), - .m_axi_BID(m_axi_mat_B_ch_3_BID), - .m_axi_BREADY(m_axi_mat_B_ch_3_BREADY), - .m_axi_BRESP(m_axi_mat_B_ch_3_BRESP), - .m_axi_BVALID(m_axi_mat_B_ch_3_BVALID), - .m_axi_RDATA(m_axi_mat_B_ch_3_RDATA), - .m_axi_RID(m_axi_mat_B_ch_3_RID), - .m_axi_RLAST(m_axi_mat_B_ch_3_RLAST), - .m_axi_RREADY(m_axi_mat_B_ch_3_RREADY), - .m_axi_RRESP(m_axi_mat_B_ch_3_RRESP), - .m_axi_RVALID(m_axi_mat_B_ch_3_RVALID), - .m_axi_WDATA(m_axi_mat_B_ch_3_WDATA), - .m_axi_WLAST(m_axi_mat_B_ch_3_WLAST), - .m_axi_WREADY(m_axi_mat_B_ch_3_WREADY), - .m_axi_WSTRB(m_axi_mat_B_ch_3_WSTRB), - .m_axi_WVALID(m_axi_mat_B_ch_3_WVALID), - .read_addr_din(mat_B_ch_3_read_addr__din), - .read_addr_full_n(mat_B_ch_3_read_addr__full_n), - .read_addr_write(mat_B_ch_3_read_addr__write), - .read_data_dout(mat_B_ch_3_read_data__dout), - .read_data_empty_n(mat_B_ch_3_read_data__empty_n), - .read_data_read(mat_B_ch_3_read_data__read), - .write_addr_din(mat_B_ch_3_write_addr__din), - .write_addr_full_n(mat_B_ch_3_write_addr__full_n), - .write_addr_write(mat_B_ch_3_write_addr__write), - .write_data_din(mat_B_ch_3_write_data__din), - .write_data_full_n(mat_B_ch_3_write_data__full_n), - .write_data_write(mat_B_ch_3_write_data__write), - .write_resp_dout(mat_B_ch_3_write_resp__dout), - .write_resp_empty_n(mat_B_ch_3_write_resp__empty_n), - .write_resp_read(mat_B_ch_3_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_in_0__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_C_0___mat_C_ch_in_0__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_in_0_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_in_0_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_in_0_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_in_0_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_in_0_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_in_0_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_in_0_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_in_0_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_in_0_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_in_0_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_in_0_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_in_0_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_in_0_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_in_0_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_in_0_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_in_0_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_in_0_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_in_0_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_in_0_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_in_0_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_in_0_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_in_0_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_in_0_BID), - .m_axi_BREADY(m_axi_mat_C_ch_in_0_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_in_0_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_in_0_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_in_0_RDATA), - .m_axi_RID(m_axi_mat_C_ch_in_0_RID), - .m_axi_RLAST(m_axi_mat_C_ch_in_0_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_in_0_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_in_0_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_in_0_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_in_0_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_in_0_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_in_0_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_in_0_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_in_0_WVALID), - .read_addr_din(mat_C_ch_in_0_read_addr__din), - .read_addr_full_n(mat_C_ch_in_0_read_addr__full_n), - .read_addr_write(mat_C_ch_in_0_read_addr__write), - .read_data_dout(mat_C_ch_in_0_read_data__dout), - .read_data_empty_n(mat_C_ch_in_0_read_data__empty_n), - .read_data_read(mat_C_ch_in_0_read_data__read), - .write_addr_din(mat_C_ch_in_0_write_addr__din), - .write_addr_full_n(mat_C_ch_in_0_write_addr__full_n), - .write_addr_write(mat_C_ch_in_0_write_addr__write), - .write_data_din(mat_C_ch_in_0_write_data__din), - .write_data_full_n(mat_C_ch_in_0_write_data__full_n), - .write_data_write(mat_C_ch_in_0_write_data__write), - .write_resp_dout(mat_C_ch_in_0_write_resp__dout), - .write_resp_empty_n(mat_C_ch_in_0_write_resp__empty_n), - .write_resp_read(mat_C_ch_in_0_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_in_1__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_C_1___mat_C_ch_in_1__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_in_1_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_in_1_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_in_1_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_in_1_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_in_1_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_in_1_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_in_1_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_in_1_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_in_1_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_in_1_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_in_1_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_in_1_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_in_1_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_in_1_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_in_1_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_in_1_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_in_1_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_in_1_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_in_1_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_in_1_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_in_1_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_in_1_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_in_1_BID), - .m_axi_BREADY(m_axi_mat_C_ch_in_1_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_in_1_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_in_1_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_in_1_RDATA), - .m_axi_RID(m_axi_mat_C_ch_in_1_RID), - .m_axi_RLAST(m_axi_mat_C_ch_in_1_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_in_1_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_in_1_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_in_1_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_in_1_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_in_1_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_in_1_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_in_1_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_in_1_WVALID), - .read_addr_din(mat_C_ch_in_1_read_addr__din), - .read_addr_full_n(mat_C_ch_in_1_read_addr__full_n), - .read_addr_write(mat_C_ch_in_1_read_addr__write), - .read_data_dout(mat_C_ch_in_1_read_data__dout), - .read_data_empty_n(mat_C_ch_in_1_read_data__empty_n), - .read_data_read(mat_C_ch_in_1_read_data__read), - .write_addr_din(mat_C_ch_in_1_write_addr__din), - .write_addr_full_n(mat_C_ch_in_1_write_addr__full_n), - .write_addr_write(mat_C_ch_in_1_write_addr__write), - .write_data_din(mat_C_ch_in_1_write_data__din), - .write_data_full_n(mat_C_ch_in_1_write_data__full_n), - .write_data_write(mat_C_ch_in_1_write_data__write), - .write_resp_dout(mat_C_ch_in_1_write_resp__dout), - .write_resp_empty_n(mat_C_ch_in_1_write_resp__empty_n), - .write_resp_read(mat_C_ch_in_1_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_in_2__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_C_2___mat_C_ch_in_2__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_in_2_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_in_2_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_in_2_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_in_2_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_in_2_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_in_2_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_in_2_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_in_2_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_in_2_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_in_2_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_in_2_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_in_2_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_in_2_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_in_2_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_in_2_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_in_2_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_in_2_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_in_2_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_in_2_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_in_2_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_in_2_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_in_2_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_in_2_BID), - .m_axi_BREADY(m_axi_mat_C_ch_in_2_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_in_2_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_in_2_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_in_2_RDATA), - .m_axi_RID(m_axi_mat_C_ch_in_2_RID), - .m_axi_RLAST(m_axi_mat_C_ch_in_2_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_in_2_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_in_2_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_in_2_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_in_2_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_in_2_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_in_2_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_in_2_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_in_2_WVALID), - .read_addr_din(mat_C_ch_in_2_read_addr__din), - .read_addr_full_n(mat_C_ch_in_2_read_addr__full_n), - .read_addr_write(mat_C_ch_in_2_read_addr__write), - .read_data_dout(mat_C_ch_in_2_read_data__dout), - .read_data_empty_n(mat_C_ch_in_2_read_data__empty_n), - .read_data_read(mat_C_ch_in_2_read_data__read), - .write_addr_din(mat_C_ch_in_2_write_addr__din), - .write_addr_full_n(mat_C_ch_in_2_write_addr__full_n), - .write_addr_write(mat_C_ch_in_2_write_addr__write), - .write_data_din(mat_C_ch_in_2_write_data__din), - .write_data_full_n(mat_C_ch_in_2_write_data__full_n), - .write_data_write(mat_C_ch_in_2_write_data__write), - .write_resp_dout(mat_C_ch_in_2_write_resp__dout), - .write_resp_empty_n(mat_C_ch_in_2_write_resp__empty_n), - .write_resp_read(mat_C_ch_in_2_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_in_3__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_C_3___mat_C_ch_in_3__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_in_3_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_in_3_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_in_3_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_in_3_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_in_3_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_in_3_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_in_3_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_in_3_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_in_3_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_in_3_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_in_3_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_in_3_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_in_3_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_in_3_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_in_3_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_in_3_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_in_3_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_in_3_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_in_3_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_in_3_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_in_3_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_in_3_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_in_3_BID), - .m_axi_BREADY(m_axi_mat_C_ch_in_3_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_in_3_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_in_3_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_in_3_RDATA), - .m_axi_RID(m_axi_mat_C_ch_in_3_RID), - .m_axi_RLAST(m_axi_mat_C_ch_in_3_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_in_3_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_in_3_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_in_3_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_in_3_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_in_3_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_in_3_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_in_3_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_in_3_WVALID), - .read_addr_din(mat_C_ch_in_3_read_addr__din), - .read_addr_full_n(mat_C_ch_in_3_read_addr__full_n), - .read_addr_write(mat_C_ch_in_3_read_addr__write), - .read_data_dout(mat_C_ch_in_3_read_data__dout), - .read_data_empty_n(mat_C_ch_in_3_read_data__empty_n), - .read_data_read(mat_C_ch_in_3_read_data__read), - .write_addr_din(mat_C_ch_in_3_write_addr__din), - .write_addr_full_n(mat_C_ch_in_3_write_addr__full_n), - .write_addr_write(mat_C_ch_in_3_write_addr__write), - .write_data_din(mat_C_ch_in_3_write_data__din), - .write_data_full_n(mat_C_ch_in_3_write_data__full_n), - .write_data_write(mat_C_ch_in_3_write_data__write), - .write_resp_dout(mat_C_ch_in_3_write_resp__dout), - .write_resp_empty_n(mat_C_ch_in_3_write_resp__empty_n), - .write_resp_read(mat_C_ch_in_3_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_in_4__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_C_4___mat_C_ch_in_4__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_in_4_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_in_4_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_in_4_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_in_4_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_in_4_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_in_4_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_in_4_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_in_4_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_in_4_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_in_4_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_in_4_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_in_4_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_in_4_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_in_4_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_in_4_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_in_4_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_in_4_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_in_4_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_in_4_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_in_4_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_in_4_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_in_4_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_in_4_BID), - .m_axi_BREADY(m_axi_mat_C_ch_in_4_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_in_4_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_in_4_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_in_4_RDATA), - .m_axi_RID(m_axi_mat_C_ch_in_4_RID), - .m_axi_RLAST(m_axi_mat_C_ch_in_4_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_in_4_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_in_4_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_in_4_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_in_4_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_in_4_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_in_4_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_in_4_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_in_4_WVALID), - .read_addr_din(mat_C_ch_in_4_read_addr__din), - .read_addr_full_n(mat_C_ch_in_4_read_addr__full_n), - .read_addr_write(mat_C_ch_in_4_read_addr__write), - .read_data_dout(mat_C_ch_in_4_read_data__dout), - .read_data_empty_n(mat_C_ch_in_4_read_data__empty_n), - .read_data_read(mat_C_ch_in_4_read_data__read), - .write_addr_din(mat_C_ch_in_4_write_addr__din), - .write_addr_full_n(mat_C_ch_in_4_write_addr__full_n), - .write_addr_write(mat_C_ch_in_4_write_addr__write), - .write_data_din(mat_C_ch_in_4_write_data__din), - .write_data_full_n(mat_C_ch_in_4_write_data__full_n), - .write_data_write(mat_C_ch_in_4_write_data__write), - .write_resp_dout(mat_C_ch_in_4_write_resp__dout), - .write_resp_empty_n(mat_C_ch_in_4_write_resp__empty_n), - .write_resp_read(mat_C_ch_in_4_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_in_5__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_C_5___mat_C_ch_in_5__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_in_5_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_in_5_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_in_5_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_in_5_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_in_5_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_in_5_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_in_5_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_in_5_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_in_5_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_in_5_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_in_5_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_in_5_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_in_5_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_in_5_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_in_5_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_in_5_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_in_5_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_in_5_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_in_5_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_in_5_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_in_5_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_in_5_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_in_5_BID), - .m_axi_BREADY(m_axi_mat_C_ch_in_5_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_in_5_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_in_5_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_in_5_RDATA), - .m_axi_RID(m_axi_mat_C_ch_in_5_RID), - .m_axi_RLAST(m_axi_mat_C_ch_in_5_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_in_5_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_in_5_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_in_5_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_in_5_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_in_5_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_in_5_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_in_5_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_in_5_WVALID), - .read_addr_din(mat_C_ch_in_5_read_addr__din), - .read_addr_full_n(mat_C_ch_in_5_read_addr__full_n), - .read_addr_write(mat_C_ch_in_5_read_addr__write), - .read_data_dout(mat_C_ch_in_5_read_data__dout), - .read_data_empty_n(mat_C_ch_in_5_read_data__empty_n), - .read_data_read(mat_C_ch_in_5_read_data__read), - .write_addr_din(mat_C_ch_in_5_write_addr__din), - .write_addr_full_n(mat_C_ch_in_5_write_addr__full_n), - .write_addr_write(mat_C_ch_in_5_write_addr__write), - .write_data_din(mat_C_ch_in_5_write_data__din), - .write_data_full_n(mat_C_ch_in_5_write_data__full_n), - .write_data_write(mat_C_ch_in_5_write_data__write), - .write_resp_dout(mat_C_ch_in_5_write_resp__dout), - .write_resp_empty_n(mat_C_ch_in_5_write_resp__empty_n), - .write_resp_read(mat_C_ch_in_5_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_in_6__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_C_6___mat_C_ch_in_6__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_in_6_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_in_6_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_in_6_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_in_6_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_in_6_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_in_6_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_in_6_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_in_6_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_in_6_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_in_6_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_in_6_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_in_6_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_in_6_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_in_6_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_in_6_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_in_6_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_in_6_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_in_6_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_in_6_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_in_6_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_in_6_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_in_6_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_in_6_BID), - .m_axi_BREADY(m_axi_mat_C_ch_in_6_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_in_6_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_in_6_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_in_6_RDATA), - .m_axi_RID(m_axi_mat_C_ch_in_6_RID), - .m_axi_RLAST(m_axi_mat_C_ch_in_6_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_in_6_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_in_6_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_in_6_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_in_6_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_in_6_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_in_6_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_in_6_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_in_6_WVALID), - .read_addr_din(mat_C_ch_in_6_read_addr__din), - .read_addr_full_n(mat_C_ch_in_6_read_addr__full_n), - .read_addr_write(mat_C_ch_in_6_read_addr__write), - .read_data_dout(mat_C_ch_in_6_read_data__dout), - .read_data_empty_n(mat_C_ch_in_6_read_data__empty_n), - .read_data_read(mat_C_ch_in_6_read_data__read), - .write_addr_din(mat_C_ch_in_6_write_addr__din), - .write_addr_full_n(mat_C_ch_in_6_write_addr__full_n), - .write_addr_write(mat_C_ch_in_6_write_addr__write), - .write_data_din(mat_C_ch_in_6_write_data__din), - .write_data_full_n(mat_C_ch_in_6_write_data__full_n), - .write_data_write(mat_C_ch_in_6_write_data__write), - .write_resp_dout(mat_C_ch_in_6_write_resp__dout), - .write_resp_empty_n(mat_C_ch_in_6_write_resp__empty_n), - .write_resp_read(mat_C_ch_in_6_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_in_7__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_C_7___mat_C_ch_in_7__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_in_7_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_in_7_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_in_7_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_in_7_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_in_7_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_in_7_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_in_7_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_in_7_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_in_7_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_in_7_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_in_7_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_in_7_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_in_7_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_in_7_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_in_7_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_in_7_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_in_7_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_in_7_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_in_7_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_in_7_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_in_7_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_in_7_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_in_7_BID), - .m_axi_BREADY(m_axi_mat_C_ch_in_7_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_in_7_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_in_7_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_in_7_RDATA), - .m_axi_RID(m_axi_mat_C_ch_in_7_RID), - .m_axi_RLAST(m_axi_mat_C_ch_in_7_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_in_7_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_in_7_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_in_7_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_in_7_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_in_7_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_in_7_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_in_7_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_in_7_WVALID), - .read_addr_din(mat_C_ch_in_7_read_addr__din), - .read_addr_full_n(mat_C_ch_in_7_read_addr__full_n), - .read_addr_write(mat_C_ch_in_7_read_addr__write), - .read_data_dout(mat_C_ch_in_7_read_data__dout), - .read_data_empty_n(mat_C_ch_in_7_read_data__empty_n), - .read_data_read(mat_C_ch_in_7_read_data__read), - .write_addr_din(mat_C_ch_in_7_write_addr__din), - .write_addr_full_n(mat_C_ch_in_7_write_addr__full_n), - .write_addr_write(mat_C_ch_in_7_write_addr__write), - .write_data_din(mat_C_ch_in_7_write_data__din), - .write_data_full_n(mat_C_ch_in_7_write_data__full_n), - .write_data_write(mat_C_ch_in_7_write_data__write), - .write_resp_dout(mat_C_ch_in_7_write_resp__dout), - .write_resp_empty_n(mat_C_ch_in_7_write_resp__empty_n), - .write_resp_read(mat_C_ch_in_7_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(32), - .DataWidthBytesLog(2), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(255) - ) - edge_list_ptr__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(read_edge_list_ptr_0___edge_list_ptr__q0), - .m_axi_ARADDR(m_axi_edge_list_ptr_ARADDR), - .m_axi_ARBURST(m_axi_edge_list_ptr_ARBURST), - .m_axi_ARCACHE(m_axi_edge_list_ptr_ARCACHE), - .m_axi_ARID(m_axi_edge_list_ptr_ARID), - .m_axi_ARLEN(m_axi_edge_list_ptr_ARLEN), - .m_axi_ARLOCK(m_axi_edge_list_ptr_ARLOCK), - .m_axi_ARPROT(m_axi_edge_list_ptr_ARPROT), - .m_axi_ARQOS(m_axi_edge_list_ptr_ARQOS), - .m_axi_ARREADY(m_axi_edge_list_ptr_ARREADY), - .m_axi_ARSIZE(m_axi_edge_list_ptr_ARSIZE), - .m_axi_ARVALID(m_axi_edge_list_ptr_ARVALID), - .m_axi_AWADDR(m_axi_edge_list_ptr_AWADDR), - .m_axi_AWBURST(m_axi_edge_list_ptr_AWBURST), - .m_axi_AWCACHE(m_axi_edge_list_ptr_AWCACHE), - .m_axi_AWID(m_axi_edge_list_ptr_AWID), - .m_axi_AWLEN(m_axi_edge_list_ptr_AWLEN), - .m_axi_AWLOCK(m_axi_edge_list_ptr_AWLOCK), - .m_axi_AWPROT(m_axi_edge_list_ptr_AWPROT), - .m_axi_AWQOS(m_axi_edge_list_ptr_AWQOS), - .m_axi_AWREADY(m_axi_edge_list_ptr_AWREADY), - .m_axi_AWSIZE(m_axi_edge_list_ptr_AWSIZE), - .m_axi_AWVALID(m_axi_edge_list_ptr_AWVALID), - .m_axi_BID(m_axi_edge_list_ptr_BID), - .m_axi_BREADY(m_axi_edge_list_ptr_BREADY), - .m_axi_BRESP(m_axi_edge_list_ptr_BRESP), - .m_axi_BVALID(m_axi_edge_list_ptr_BVALID), - .m_axi_RDATA(m_axi_edge_list_ptr_RDATA), - .m_axi_RID(m_axi_edge_list_ptr_RID), - .m_axi_RLAST(m_axi_edge_list_ptr_RLAST), - .m_axi_RREADY(m_axi_edge_list_ptr_RREADY), - .m_axi_RRESP(m_axi_edge_list_ptr_RRESP), - .m_axi_RVALID(m_axi_edge_list_ptr_RVALID), - .m_axi_WDATA(m_axi_edge_list_ptr_WDATA), - .m_axi_WLAST(m_axi_edge_list_ptr_WLAST), - .m_axi_WREADY(m_axi_edge_list_ptr_WREADY), - .m_axi_WSTRB(m_axi_edge_list_ptr_WSTRB), - .m_axi_WVALID(m_axi_edge_list_ptr_WVALID), - .read_addr_din(edge_list_ptr_read_addr__din), - .read_addr_full_n(edge_list_ptr_read_addr__full_n), - .read_addr_write(edge_list_ptr_read_addr__write), - .read_data_dout(edge_list_ptr_read_data__dout), - .read_data_empty_n(edge_list_ptr_read_data__empty_n), - .read_data_read(edge_list_ptr_read_data__read), - .write_addr_din(edge_list_ptr_write_addr__din), - .write_addr_full_n(edge_list_ptr_write_addr__full_n), - .write_addr_write(edge_list_ptr_write_addr__write), - .write_data_din(edge_list_ptr_write_data__din), - .write_data_full_n(edge_list_ptr_write_data__full_n), - .write_data_write(edge_list_ptr_write_data__write), - .write_resp_dout(edge_list_ptr_write_resp__dout), - .write_resp_empty_n(edge_list_ptr_write_resp__empty_n), - .write_resp_read(edge_list_ptr_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_0__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(write_C_0___mat_C_ch_0__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_0_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_0_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_0_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_0_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_0_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_0_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_0_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_0_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_0_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_0_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_0_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_0_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_0_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_0_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_0_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_0_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_0_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_0_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_0_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_0_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_0_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_0_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_0_BID), - .m_axi_BREADY(m_axi_mat_C_ch_0_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_0_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_0_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_0_RDATA), - .m_axi_RID(m_axi_mat_C_ch_0_RID), - .m_axi_RLAST(m_axi_mat_C_ch_0_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_0_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_0_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_0_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_0_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_0_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_0_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_0_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_0_WVALID), - .read_addr_din(mat_C_ch_0_read_addr__din), - .read_addr_full_n(mat_C_ch_0_read_addr__full_n), - .read_addr_write(mat_C_ch_0_read_addr__write), - .read_data_dout(mat_C_ch_0_read_data__dout), - .read_data_empty_n(mat_C_ch_0_read_data__empty_n), - .read_data_read(mat_C_ch_0_read_data__read), - .write_addr_din(mat_C_ch_0_write_addr__din), - .write_addr_full_n(mat_C_ch_0_write_addr__full_n), - .write_addr_write(mat_C_ch_0_write_addr__write), - .write_data_din(mat_C_ch_0_write_data__din), - .write_data_full_n(mat_C_ch_0_write_data__full_n), - .write_data_write(mat_C_ch_0_write_data__write), - .write_resp_dout(mat_C_ch_0_write_resp__dout), - .write_resp_empty_n(mat_C_ch_0_write_resp__empty_n), - .write_resp_read(mat_C_ch_0_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_1__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(write_C_1___mat_C_ch_1__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_1_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_1_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_1_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_1_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_1_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_1_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_1_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_1_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_1_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_1_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_1_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_1_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_1_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_1_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_1_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_1_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_1_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_1_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_1_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_1_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_1_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_1_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_1_BID), - .m_axi_BREADY(m_axi_mat_C_ch_1_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_1_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_1_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_1_RDATA), - .m_axi_RID(m_axi_mat_C_ch_1_RID), - .m_axi_RLAST(m_axi_mat_C_ch_1_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_1_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_1_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_1_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_1_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_1_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_1_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_1_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_1_WVALID), - .read_addr_din(mat_C_ch_1_read_addr__din), - .read_addr_full_n(mat_C_ch_1_read_addr__full_n), - .read_addr_write(mat_C_ch_1_read_addr__write), - .read_data_dout(mat_C_ch_1_read_data__dout), - .read_data_empty_n(mat_C_ch_1_read_data__empty_n), - .read_data_read(mat_C_ch_1_read_data__read), - .write_addr_din(mat_C_ch_1_write_addr__din), - .write_addr_full_n(mat_C_ch_1_write_addr__full_n), - .write_addr_write(mat_C_ch_1_write_addr__write), - .write_data_din(mat_C_ch_1_write_data__din), - .write_data_full_n(mat_C_ch_1_write_data__full_n), - .write_data_write(mat_C_ch_1_write_data__write), - .write_resp_dout(mat_C_ch_1_write_resp__dout), - .write_resp_empty_n(mat_C_ch_1_write_resp__empty_n), - .write_resp_read(mat_C_ch_1_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_2__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(write_C_2___mat_C_ch_2__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_2_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_2_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_2_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_2_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_2_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_2_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_2_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_2_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_2_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_2_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_2_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_2_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_2_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_2_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_2_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_2_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_2_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_2_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_2_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_2_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_2_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_2_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_2_BID), - .m_axi_BREADY(m_axi_mat_C_ch_2_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_2_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_2_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_2_RDATA), - .m_axi_RID(m_axi_mat_C_ch_2_RID), - .m_axi_RLAST(m_axi_mat_C_ch_2_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_2_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_2_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_2_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_2_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_2_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_2_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_2_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_2_WVALID), - .read_addr_din(mat_C_ch_2_read_addr__din), - .read_addr_full_n(mat_C_ch_2_read_addr__full_n), - .read_addr_write(mat_C_ch_2_read_addr__write), - .read_data_dout(mat_C_ch_2_read_data__dout), - .read_data_empty_n(mat_C_ch_2_read_data__empty_n), - .read_data_read(mat_C_ch_2_read_data__read), - .write_addr_din(mat_C_ch_2_write_addr__din), - .write_addr_full_n(mat_C_ch_2_write_addr__full_n), - .write_addr_write(mat_C_ch_2_write_addr__write), - .write_data_din(mat_C_ch_2_write_data__din), - .write_data_full_n(mat_C_ch_2_write_data__full_n), - .write_data_write(mat_C_ch_2_write_data__write), - .write_resp_dout(mat_C_ch_2_write_resp__dout), - .write_resp_empty_n(mat_C_ch_2_write_resp__empty_n), - .write_resp_read(mat_C_ch_2_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_3__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(write_C_3___mat_C_ch_3__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_3_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_3_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_3_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_3_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_3_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_3_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_3_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_3_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_3_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_3_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_3_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_3_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_3_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_3_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_3_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_3_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_3_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_3_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_3_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_3_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_3_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_3_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_3_BID), - .m_axi_BREADY(m_axi_mat_C_ch_3_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_3_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_3_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_3_RDATA), - .m_axi_RID(m_axi_mat_C_ch_3_RID), - .m_axi_RLAST(m_axi_mat_C_ch_3_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_3_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_3_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_3_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_3_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_3_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_3_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_3_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_3_WVALID), - .read_addr_din(mat_C_ch_3_read_addr__din), - .read_addr_full_n(mat_C_ch_3_read_addr__full_n), - .read_addr_write(mat_C_ch_3_read_addr__write), - .read_data_dout(mat_C_ch_3_read_data__dout), - .read_data_empty_n(mat_C_ch_3_read_data__empty_n), - .read_data_read(mat_C_ch_3_read_data__read), - .write_addr_din(mat_C_ch_3_write_addr__din), - .write_addr_full_n(mat_C_ch_3_write_addr__full_n), - .write_addr_write(mat_C_ch_3_write_addr__write), - .write_data_din(mat_C_ch_3_write_data__din), - .write_data_full_n(mat_C_ch_3_write_data__full_n), - .write_data_write(mat_C_ch_3_write_data__write), - .write_resp_dout(mat_C_ch_3_write_resp__dout), - .write_resp_empty_n(mat_C_ch_3_write_resp__empty_n), - .write_resp_read(mat_C_ch_3_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_4__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(write_C_4___mat_C_ch_4__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_4_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_4_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_4_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_4_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_4_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_4_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_4_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_4_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_4_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_4_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_4_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_4_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_4_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_4_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_4_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_4_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_4_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_4_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_4_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_4_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_4_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_4_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_4_BID), - .m_axi_BREADY(m_axi_mat_C_ch_4_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_4_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_4_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_4_RDATA), - .m_axi_RID(m_axi_mat_C_ch_4_RID), - .m_axi_RLAST(m_axi_mat_C_ch_4_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_4_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_4_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_4_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_4_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_4_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_4_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_4_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_4_WVALID), - .read_addr_din(mat_C_ch_4_read_addr__din), - .read_addr_full_n(mat_C_ch_4_read_addr__full_n), - .read_addr_write(mat_C_ch_4_read_addr__write), - .read_data_dout(mat_C_ch_4_read_data__dout), - .read_data_empty_n(mat_C_ch_4_read_data__empty_n), - .read_data_read(mat_C_ch_4_read_data__read), - .write_addr_din(mat_C_ch_4_write_addr__din), - .write_addr_full_n(mat_C_ch_4_write_addr__full_n), - .write_addr_write(mat_C_ch_4_write_addr__write), - .write_data_din(mat_C_ch_4_write_data__din), - .write_data_full_n(mat_C_ch_4_write_data__full_n), - .write_data_write(mat_C_ch_4_write_data__write), - .write_resp_dout(mat_C_ch_4_write_resp__dout), - .write_resp_empty_n(mat_C_ch_4_write_resp__empty_n), - .write_resp_read(mat_C_ch_4_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_5__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(write_C_5___mat_C_ch_5__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_5_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_5_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_5_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_5_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_5_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_5_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_5_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_5_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_5_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_5_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_5_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_5_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_5_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_5_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_5_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_5_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_5_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_5_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_5_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_5_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_5_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_5_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_5_BID), - .m_axi_BREADY(m_axi_mat_C_ch_5_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_5_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_5_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_5_RDATA), - .m_axi_RID(m_axi_mat_C_ch_5_RID), - .m_axi_RLAST(m_axi_mat_C_ch_5_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_5_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_5_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_5_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_5_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_5_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_5_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_5_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_5_WVALID), - .read_addr_din(mat_C_ch_5_read_addr__din), - .read_addr_full_n(mat_C_ch_5_read_addr__full_n), - .read_addr_write(mat_C_ch_5_read_addr__write), - .read_data_dout(mat_C_ch_5_read_data__dout), - .read_data_empty_n(mat_C_ch_5_read_data__empty_n), - .read_data_read(mat_C_ch_5_read_data__read), - .write_addr_din(mat_C_ch_5_write_addr__din), - .write_addr_full_n(mat_C_ch_5_write_addr__full_n), - .write_addr_write(mat_C_ch_5_write_addr__write), - .write_data_din(mat_C_ch_5_write_data__din), - .write_data_full_n(mat_C_ch_5_write_data__full_n), - .write_data_write(mat_C_ch_5_write_data__write), - .write_resp_dout(mat_C_ch_5_write_resp__dout), - .write_resp_empty_n(mat_C_ch_5_write_resp__empty_n), - .write_resp_read(mat_C_ch_5_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_6__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(write_C_6___mat_C_ch_6__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_6_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_6_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_6_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_6_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_6_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_6_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_6_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_6_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_6_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_6_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_6_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_6_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_6_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_6_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_6_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_6_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_6_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_6_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_6_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_6_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_6_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_6_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_6_BID), - .m_axi_BREADY(m_axi_mat_C_ch_6_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_6_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_6_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_6_RDATA), - .m_axi_RID(m_axi_mat_C_ch_6_RID), - .m_axi_RLAST(m_axi_mat_C_ch_6_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_6_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_6_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_6_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_6_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_6_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_6_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_6_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_6_WVALID), - .read_addr_din(mat_C_ch_6_read_addr__din), - .read_addr_full_n(mat_C_ch_6_read_addr__full_n), - .read_addr_write(mat_C_ch_6_read_addr__write), - .read_data_dout(mat_C_ch_6_read_data__dout), - .read_data_empty_n(mat_C_ch_6_read_data__empty_n), - .read_data_read(mat_C_ch_6_read_data__read), - .write_addr_din(mat_C_ch_6_write_addr__din), - .write_addr_full_n(mat_C_ch_6_write_addr__full_n), - .write_addr_write(mat_C_ch_6_write_addr__write), - .write_data_din(mat_C_ch_6_write_data__din), - .write_data_full_n(mat_C_ch_6_write_data__full_n), - .write_data_write(mat_C_ch_6_write_data__write), - .write_resp_dout(mat_C_ch_6_write_resp__dout), - .write_resp_empty_n(mat_C_ch_6_write_resp__empty_n), - .write_resp_read(mat_C_ch_6_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - mat_C_ch_7__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(write_C_7___mat_C_ch_7__q0), - .m_axi_ARADDR(m_axi_mat_C_ch_7_ARADDR), - .m_axi_ARBURST(m_axi_mat_C_ch_7_ARBURST), - .m_axi_ARCACHE(m_axi_mat_C_ch_7_ARCACHE), - .m_axi_ARID(m_axi_mat_C_ch_7_ARID), - .m_axi_ARLEN(m_axi_mat_C_ch_7_ARLEN), - .m_axi_ARLOCK(m_axi_mat_C_ch_7_ARLOCK), - .m_axi_ARPROT(m_axi_mat_C_ch_7_ARPROT), - .m_axi_ARQOS(m_axi_mat_C_ch_7_ARQOS), - .m_axi_ARREADY(m_axi_mat_C_ch_7_ARREADY), - .m_axi_ARSIZE(m_axi_mat_C_ch_7_ARSIZE), - .m_axi_ARVALID(m_axi_mat_C_ch_7_ARVALID), - .m_axi_AWADDR(m_axi_mat_C_ch_7_AWADDR), - .m_axi_AWBURST(m_axi_mat_C_ch_7_AWBURST), - .m_axi_AWCACHE(m_axi_mat_C_ch_7_AWCACHE), - .m_axi_AWID(m_axi_mat_C_ch_7_AWID), - .m_axi_AWLEN(m_axi_mat_C_ch_7_AWLEN), - .m_axi_AWLOCK(m_axi_mat_C_ch_7_AWLOCK), - .m_axi_AWPROT(m_axi_mat_C_ch_7_AWPROT), - .m_axi_AWQOS(m_axi_mat_C_ch_7_AWQOS), - .m_axi_AWREADY(m_axi_mat_C_ch_7_AWREADY), - .m_axi_AWSIZE(m_axi_mat_C_ch_7_AWSIZE), - .m_axi_AWVALID(m_axi_mat_C_ch_7_AWVALID), - .m_axi_BID(m_axi_mat_C_ch_7_BID), - .m_axi_BREADY(m_axi_mat_C_ch_7_BREADY), - .m_axi_BRESP(m_axi_mat_C_ch_7_BRESP), - .m_axi_BVALID(m_axi_mat_C_ch_7_BVALID), - .m_axi_RDATA(m_axi_mat_C_ch_7_RDATA), - .m_axi_RID(m_axi_mat_C_ch_7_RID), - .m_axi_RLAST(m_axi_mat_C_ch_7_RLAST), - .m_axi_RREADY(m_axi_mat_C_ch_7_RREADY), - .m_axi_RRESP(m_axi_mat_C_ch_7_RRESP), - .m_axi_RVALID(m_axi_mat_C_ch_7_RVALID), - .m_axi_WDATA(m_axi_mat_C_ch_7_WDATA), - .m_axi_WLAST(m_axi_mat_C_ch_7_WLAST), - .m_axi_WREADY(m_axi_mat_C_ch_7_WREADY), - .m_axi_WSTRB(m_axi_mat_C_ch_7_WSTRB), - .m_axi_WVALID(m_axi_mat_C_ch_7_WVALID), - .read_addr_din(mat_C_ch_7_read_addr__din), - .read_addr_full_n(mat_C_ch_7_read_addr__full_n), - .read_addr_write(mat_C_ch_7_read_addr__write), - .read_data_dout(mat_C_ch_7_read_data__dout), - .read_data_empty_n(mat_C_ch_7_read_data__empty_n), - .read_data_read(mat_C_ch_7_read_data__read), - .write_addr_din(mat_C_ch_7_write_addr__din), - .write_addr_full_n(mat_C_ch_7_write_addr__full_n), - .write_addr_write(mat_C_ch_7_write_addr__write), - .write_data_din(mat_C_ch_7_write_data__din), - .write_data_full_n(mat_C_ch_7_write_data__full_n), - .write_data_write(mat_C_ch_7_write_data__write), - .write_resp_dout(mat_C_ch_7_write_resp__dout), - .write_resp_empty_n(mat_C_ch_7_write_resp__empty_n), - .write_resp_read(mat_C_ch_7_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) Sextans_fsm - __tapa_fsm_unit - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(ap_start), - .ap_done(ap_done), - .ap_idle(ap_idle), - .ap_ready(ap_ready), - .FloatvAddFloatv_0__ap_start(FloatvAddFloatv_0__ap_start), - .FloatvAddFloatv_1__ap_start(FloatvAddFloatv_1__ap_start), - .FloatvAddFloatv_2__ap_start(FloatvAddFloatv_2__ap_start), - .FloatvAddFloatv_3__ap_start(FloatvAddFloatv_3__ap_start), - .FloatvAddFloatv_4__ap_start(FloatvAddFloatv_4__ap_start), - .FloatvAddFloatv_5__ap_start(FloatvAddFloatv_5__ap_start), - .FloatvAddFloatv_6__ap_start(FloatvAddFloatv_6__ap_start), - .FloatvAddFloatv_7__ap_start(FloatvAddFloatv_7__ap_start), - .FloatvMultConst_0__ap_start(FloatvMultConst_0__ap_start), - .FloatvMultConst_0__ap_ready(FloatvMultConst_0__ap_ready), - .FloatvMultConst_0__ap_done(FloatvMultConst_0__ap_done), - .FloatvMultConst_0__ap_idle(FloatvMultConst_0__ap_idle), - .FloatvMultConst_1__ap_start(FloatvMultConst_1__ap_start), - .FloatvMultConst_1__ap_ready(FloatvMultConst_1__ap_ready), - .FloatvMultConst_1__ap_done(FloatvMultConst_1__ap_done), - .FloatvMultConst_1__ap_idle(FloatvMultConst_1__ap_idle), - .FloatvMultConst_2__ap_start(FloatvMultConst_2__ap_start), - .FloatvMultConst_2__ap_ready(FloatvMultConst_2__ap_ready), - .FloatvMultConst_2__ap_done(FloatvMultConst_2__ap_done), - .FloatvMultConst_2__ap_idle(FloatvMultConst_2__ap_idle), - .FloatvMultConst_3__ap_start(FloatvMultConst_3__ap_start), - .FloatvMultConst_3__ap_ready(FloatvMultConst_3__ap_ready), - .FloatvMultConst_3__ap_done(FloatvMultConst_3__ap_done), - .FloatvMultConst_3__ap_idle(FloatvMultConst_3__ap_idle), - .FloatvMultConst_4__ap_start(FloatvMultConst_4__ap_start), - .FloatvMultConst_4__ap_ready(FloatvMultConst_4__ap_ready), - .FloatvMultConst_4__ap_done(FloatvMultConst_4__ap_done), - .FloatvMultConst_4__ap_idle(FloatvMultConst_4__ap_idle), - .FloatvMultConst_5__ap_start(FloatvMultConst_5__ap_start), - .FloatvMultConst_5__ap_ready(FloatvMultConst_5__ap_ready), - .FloatvMultConst_5__ap_done(FloatvMultConst_5__ap_done), - .FloatvMultConst_5__ap_idle(FloatvMultConst_5__ap_idle), - .FloatvMultConst_6__ap_start(FloatvMultConst_6__ap_start), - .FloatvMultConst_6__ap_ready(FloatvMultConst_6__ap_ready), - .FloatvMultConst_6__ap_done(FloatvMultConst_6__ap_done), - .FloatvMultConst_6__ap_idle(FloatvMultConst_6__ap_idle), - .FloatvMultConst_7__ap_start(FloatvMultConst_7__ap_start), - .FloatvMultConst_7__ap_ready(FloatvMultConst_7__ap_ready), - .FloatvMultConst_7__ap_done(FloatvMultConst_7__ap_done), - .FloatvMultConst_7__ap_idle(FloatvMultConst_7__ap_idle), - .FloatvMultConst_8__ap_start(FloatvMultConst_8__ap_start), - .FloatvMultConst_8__ap_ready(FloatvMultConst_8__ap_ready), - .FloatvMultConst_8__ap_done(FloatvMultConst_8__ap_done), - .FloatvMultConst_8__ap_idle(FloatvMultConst_8__ap_idle), - .FloatvMultConst_9__ap_start(FloatvMultConst_9__ap_start), - .FloatvMultConst_9__ap_ready(FloatvMultConst_9__ap_ready), - .FloatvMultConst_9__ap_done(FloatvMultConst_9__ap_done), - .FloatvMultConst_9__ap_idle(FloatvMultConst_9__ap_idle), - .FloatvMultConst_10__ap_start(FloatvMultConst_10__ap_start), - .FloatvMultConst_10__ap_ready(FloatvMultConst_10__ap_ready), - .FloatvMultConst_10__ap_done(FloatvMultConst_10__ap_done), - .FloatvMultConst_10__ap_idle(FloatvMultConst_10__ap_idle), - .FloatvMultConst_11__ap_start(FloatvMultConst_11__ap_start), - .FloatvMultConst_11__ap_ready(FloatvMultConst_11__ap_ready), - .FloatvMultConst_11__ap_done(FloatvMultConst_11__ap_done), - .FloatvMultConst_11__ap_idle(FloatvMultConst_11__ap_idle), - .FloatvMultConst_12__ap_start(FloatvMultConst_12__ap_start), - .FloatvMultConst_12__ap_ready(FloatvMultConst_12__ap_ready), - .FloatvMultConst_12__ap_done(FloatvMultConst_12__ap_done), - .FloatvMultConst_12__ap_idle(FloatvMultConst_12__ap_idle), - .FloatvMultConst_13__ap_start(FloatvMultConst_13__ap_start), - .FloatvMultConst_13__ap_ready(FloatvMultConst_13__ap_ready), - .FloatvMultConst_13__ap_done(FloatvMultConst_13__ap_done), - .FloatvMultConst_13__ap_idle(FloatvMultConst_13__ap_idle), - .FloatvMultConst_14__ap_start(FloatvMultConst_14__ap_start), - .FloatvMultConst_14__ap_ready(FloatvMultConst_14__ap_ready), - .FloatvMultConst_14__ap_done(FloatvMultConst_14__ap_done), - .FloatvMultConst_14__ap_idle(FloatvMultConst_14__ap_idle), - .FloatvMultConst_15__ap_start(FloatvMultConst_15__ap_start), - .FloatvMultConst_15__ap_ready(FloatvMultConst_15__ap_ready), - .FloatvMultConst_15__ap_done(FloatvMultConst_15__ap_done), - .FloatvMultConst_15__ap_idle(FloatvMultConst_15__ap_idle), - .Merger_0__ap_start(Merger_0__ap_start), - .Merger_1__ap_start(Merger_1__ap_start), - .Merger_2__ap_start(Merger_2__ap_start), - .Merger_3__ap_start(Merger_3__ap_start), - .Merger_4__ap_start(Merger_4__ap_start), - .Merger_5__ap_start(Merger_5__ap_start), - .Merger_6__ap_start(Merger_6__ap_start), - .Merger_7__ap_start(Merger_7__ap_start), - .PEG_Bmtx_0__ap_start(PEG_Bmtx_0__ap_start), - .PEG_Bmtx_0__ap_ready(PEG_Bmtx_0__ap_ready), - .PEG_Bmtx_0__ap_done(PEG_Bmtx_0__ap_done), - .PEG_Bmtx_0__ap_idle(PEG_Bmtx_0__ap_idle), - .PEG_Bmtx_1__ap_start(PEG_Bmtx_1__ap_start), - .PEG_Bmtx_1__ap_ready(PEG_Bmtx_1__ap_ready), - .PEG_Bmtx_1__ap_done(PEG_Bmtx_1__ap_done), - .PEG_Bmtx_1__ap_idle(PEG_Bmtx_1__ap_idle), - .PEG_Bmtx_2__ap_start(PEG_Bmtx_2__ap_start), - .PEG_Bmtx_2__ap_ready(PEG_Bmtx_2__ap_ready), - .PEG_Bmtx_2__ap_done(PEG_Bmtx_2__ap_done), - .PEG_Bmtx_2__ap_idle(PEG_Bmtx_2__ap_idle), - .PEG_Bmtx_3__ap_start(PEG_Bmtx_3__ap_start), - .PEG_Bmtx_3__ap_ready(PEG_Bmtx_3__ap_ready), - .PEG_Bmtx_3__ap_done(PEG_Bmtx_3__ap_done), - .PEG_Bmtx_3__ap_idle(PEG_Bmtx_3__ap_idle), - .PEG_Bmtx_4__ap_start(PEG_Bmtx_4__ap_start), - .PEG_Bmtx_4__ap_ready(PEG_Bmtx_4__ap_ready), - .PEG_Bmtx_4__ap_done(PEG_Bmtx_4__ap_done), - .PEG_Bmtx_4__ap_idle(PEG_Bmtx_4__ap_idle), - .PEG_Bmtx_5__ap_start(PEG_Bmtx_5__ap_start), - .PEG_Bmtx_5__ap_ready(PEG_Bmtx_5__ap_ready), - .PEG_Bmtx_5__ap_done(PEG_Bmtx_5__ap_done), - .PEG_Bmtx_5__ap_idle(PEG_Bmtx_5__ap_idle), - .PEG_Bmtx_6__ap_start(PEG_Bmtx_6__ap_start), - .PEG_Bmtx_6__ap_ready(PEG_Bmtx_6__ap_ready), - .PEG_Bmtx_6__ap_done(PEG_Bmtx_6__ap_done), - .PEG_Bmtx_6__ap_idle(PEG_Bmtx_6__ap_idle), - .PEG_Bmtx_7__ap_start(PEG_Bmtx_7__ap_start), - .PEG_Bmtx_7__ap_ready(PEG_Bmtx_7__ap_ready), - .PEG_Bmtx_7__ap_done(PEG_Bmtx_7__ap_done), - .PEG_Bmtx_7__ap_idle(PEG_Bmtx_7__ap_idle), - .PEG_Bmtx_8__ap_start(PEG_Bmtx_8__ap_start), - .PEG_Bmtx_8__ap_ready(PEG_Bmtx_8__ap_ready), - .PEG_Bmtx_8__ap_done(PEG_Bmtx_8__ap_done), - .PEG_Bmtx_8__ap_idle(PEG_Bmtx_8__ap_idle), - .PEG_Bmtx_9__ap_start(PEG_Bmtx_9__ap_start), - .PEG_Bmtx_9__ap_ready(PEG_Bmtx_9__ap_ready), - .PEG_Bmtx_9__ap_done(PEG_Bmtx_9__ap_done), - .PEG_Bmtx_9__ap_idle(PEG_Bmtx_9__ap_idle), - .PEG_Bmtx_10__ap_start(PEG_Bmtx_10__ap_start), - .PEG_Bmtx_10__ap_ready(PEG_Bmtx_10__ap_ready), - .PEG_Bmtx_10__ap_done(PEG_Bmtx_10__ap_done), - .PEG_Bmtx_10__ap_idle(PEG_Bmtx_10__ap_idle), - .PEG_Bmtx_11__ap_start(PEG_Bmtx_11__ap_start), - .PEG_Bmtx_11__ap_ready(PEG_Bmtx_11__ap_ready), - .PEG_Bmtx_11__ap_done(PEG_Bmtx_11__ap_done), - .PEG_Bmtx_11__ap_idle(PEG_Bmtx_11__ap_idle), - .PEG_Bmtx_12__ap_start(PEG_Bmtx_12__ap_start), - .PEG_Bmtx_12__ap_ready(PEG_Bmtx_12__ap_ready), - .PEG_Bmtx_12__ap_done(PEG_Bmtx_12__ap_done), - .PEG_Bmtx_12__ap_idle(PEG_Bmtx_12__ap_idle), - .PEG_Bmtx_13__ap_start(PEG_Bmtx_13__ap_start), - .PEG_Bmtx_13__ap_ready(PEG_Bmtx_13__ap_ready), - .PEG_Bmtx_13__ap_done(PEG_Bmtx_13__ap_done), - .PEG_Bmtx_13__ap_idle(PEG_Bmtx_13__ap_idle), - .PEG_Bmtx_14__ap_start(PEG_Bmtx_14__ap_start), - .PEG_Bmtx_14__ap_ready(PEG_Bmtx_14__ap_ready), - .PEG_Bmtx_14__ap_done(PEG_Bmtx_14__ap_done), - .PEG_Bmtx_14__ap_idle(PEG_Bmtx_14__ap_idle), - .PEG_Bmtx_15__ap_start(PEG_Bmtx_15__ap_start), - .PEG_Bmtx_15__ap_ready(PEG_Bmtx_15__ap_ready), - .PEG_Bmtx_15__ap_done(PEG_Bmtx_15__ap_done), - .PEG_Bmtx_15__ap_idle(PEG_Bmtx_15__ap_idle), - .PEG_Cmtx_0__ap_start(PEG_Cmtx_0__ap_start), - .PEG_Cmtx_0__ap_ready(PEG_Cmtx_0__ap_ready), - .PEG_Cmtx_0__ap_done(PEG_Cmtx_0__ap_done), - .PEG_Cmtx_0__ap_idle(PEG_Cmtx_0__ap_idle), - .PEG_Cmtx_1__ap_start(PEG_Cmtx_1__ap_start), - .PEG_Cmtx_1__ap_ready(PEG_Cmtx_1__ap_ready), - .PEG_Cmtx_1__ap_done(PEG_Cmtx_1__ap_done), - .PEG_Cmtx_1__ap_idle(PEG_Cmtx_1__ap_idle), - .PEG_Cmtx_2__ap_start(PEG_Cmtx_2__ap_start), - .PEG_Cmtx_2__ap_ready(PEG_Cmtx_2__ap_ready), - .PEG_Cmtx_2__ap_done(PEG_Cmtx_2__ap_done), - .PEG_Cmtx_2__ap_idle(PEG_Cmtx_2__ap_idle), - .PEG_Cmtx_3__ap_start(PEG_Cmtx_3__ap_start), - .PEG_Cmtx_3__ap_ready(PEG_Cmtx_3__ap_ready), - .PEG_Cmtx_3__ap_done(PEG_Cmtx_3__ap_done), - .PEG_Cmtx_3__ap_idle(PEG_Cmtx_3__ap_idle), - .PEG_Cmtx_4__ap_start(PEG_Cmtx_4__ap_start), - .PEG_Cmtx_4__ap_ready(PEG_Cmtx_4__ap_ready), - .PEG_Cmtx_4__ap_done(PEG_Cmtx_4__ap_done), - .PEG_Cmtx_4__ap_idle(PEG_Cmtx_4__ap_idle), - .PEG_Cmtx_5__ap_start(PEG_Cmtx_5__ap_start), - .PEG_Cmtx_5__ap_ready(PEG_Cmtx_5__ap_ready), - .PEG_Cmtx_5__ap_done(PEG_Cmtx_5__ap_done), - .PEG_Cmtx_5__ap_idle(PEG_Cmtx_5__ap_idle), - .PEG_Cmtx_6__ap_start(PEG_Cmtx_6__ap_start), - .PEG_Cmtx_6__ap_ready(PEG_Cmtx_6__ap_ready), - .PEG_Cmtx_6__ap_done(PEG_Cmtx_6__ap_done), - .PEG_Cmtx_6__ap_idle(PEG_Cmtx_6__ap_idle), - .PEG_Cmtx_7__ap_start(PEG_Cmtx_7__ap_start), - .PEG_Cmtx_7__ap_ready(PEG_Cmtx_7__ap_ready), - .PEG_Cmtx_7__ap_done(PEG_Cmtx_7__ap_done), - .PEG_Cmtx_7__ap_idle(PEG_Cmtx_7__ap_idle), - .PEG_Cmtx_8__ap_start(PEG_Cmtx_8__ap_start), - .PEG_Cmtx_8__ap_ready(PEG_Cmtx_8__ap_ready), - .PEG_Cmtx_8__ap_done(PEG_Cmtx_8__ap_done), - .PEG_Cmtx_8__ap_idle(PEG_Cmtx_8__ap_idle), - .PEG_Cmtx_9__ap_start(PEG_Cmtx_9__ap_start), - .PEG_Cmtx_9__ap_ready(PEG_Cmtx_9__ap_ready), - .PEG_Cmtx_9__ap_done(PEG_Cmtx_9__ap_done), - .PEG_Cmtx_9__ap_idle(PEG_Cmtx_9__ap_idle), - .PEG_Cmtx_10__ap_start(PEG_Cmtx_10__ap_start), - .PEG_Cmtx_10__ap_ready(PEG_Cmtx_10__ap_ready), - .PEG_Cmtx_10__ap_done(PEG_Cmtx_10__ap_done), - .PEG_Cmtx_10__ap_idle(PEG_Cmtx_10__ap_idle), - .PEG_Cmtx_11__ap_start(PEG_Cmtx_11__ap_start), - .PEG_Cmtx_11__ap_ready(PEG_Cmtx_11__ap_ready), - .PEG_Cmtx_11__ap_done(PEG_Cmtx_11__ap_done), - .PEG_Cmtx_11__ap_idle(PEG_Cmtx_11__ap_idle), - .PEG_Cmtx_12__ap_start(PEG_Cmtx_12__ap_start), - .PEG_Cmtx_12__ap_ready(PEG_Cmtx_12__ap_ready), - .PEG_Cmtx_12__ap_done(PEG_Cmtx_12__ap_done), - .PEG_Cmtx_12__ap_idle(PEG_Cmtx_12__ap_idle), - .PEG_Cmtx_13__ap_start(PEG_Cmtx_13__ap_start), - .PEG_Cmtx_13__ap_ready(PEG_Cmtx_13__ap_ready), - .PEG_Cmtx_13__ap_done(PEG_Cmtx_13__ap_done), - .PEG_Cmtx_13__ap_idle(PEG_Cmtx_13__ap_idle), - .PEG_Cmtx_14__ap_start(PEG_Cmtx_14__ap_start), - .PEG_Cmtx_14__ap_ready(PEG_Cmtx_14__ap_ready), - .PEG_Cmtx_14__ap_done(PEG_Cmtx_14__ap_done), - .PEG_Cmtx_14__ap_idle(PEG_Cmtx_14__ap_idle), - .PEG_Cmtx_15__ap_start(PEG_Cmtx_15__ap_start), - .PEG_Cmtx_15__ap_ready(PEG_Cmtx_15__ap_ready), - .PEG_Cmtx_15__ap_done(PEG_Cmtx_15__ap_done), - .PEG_Cmtx_15__ap_idle(PEG_Cmtx_15__ap_idle), - .Scatter_1_2_0__ap_start(Scatter_1_2_0__ap_start), - .Scatter_1_2_1__ap_start(Scatter_1_2_1__ap_start), - .Scatter_1_2_2__ap_start(Scatter_1_2_2__ap_start), - .Scatter_1_2_3__ap_start(Scatter_1_2_3__ap_start), - .Scatter_1_2_4__ap_start(Scatter_1_2_4__ap_start), - .Scatter_1_2_5__ap_start(Scatter_1_2_5__ap_start), - .Scatter_1_2_6__ap_start(Scatter_1_2_6__ap_start), - .Scatter_1_2_7__ap_start(Scatter_1_2_7__ap_start), - .black_hole_float_v16_0__ap_start(black_hole_float_v16_0__ap_start), - .black_hole_float_v16_1__ap_start(black_hole_float_v16_1__ap_start), - .black_hole_float_v16_2__ap_start(black_hole_float_v16_2__ap_start), - .black_hole_float_v16_3__ap_start(black_hole_float_v16_3__ap_start), - .black_hole_int_0__ap_start(black_hole_int_0__ap_start), - .black_hole_int_1__ap_start(black_hole_int_1__ap_start), - .read_A_0__ap_start(read_A_0__ap_start), - .read_A_0__ap_ready(read_A_0__ap_ready), - .read_A_0__ap_done(read_A_0__ap_done), - .read_A_0__ap_idle(read_A_0__ap_idle), - .read_A_1__ap_start(read_A_1__ap_start), - .read_A_1__ap_ready(read_A_1__ap_ready), - .read_A_1__ap_done(read_A_1__ap_done), - .read_A_1__ap_idle(read_A_1__ap_idle), - .read_A_2__ap_start(read_A_2__ap_start), - .read_A_2__ap_ready(read_A_2__ap_ready), - .read_A_2__ap_done(read_A_2__ap_done), - .read_A_2__ap_idle(read_A_2__ap_idle), - .read_A_3__ap_start(read_A_3__ap_start), - .read_A_3__ap_ready(read_A_3__ap_ready), - .read_A_3__ap_done(read_A_3__ap_done), - .read_A_3__ap_idle(read_A_3__ap_idle), - .read_A_4__ap_start(read_A_4__ap_start), - .read_A_4__ap_ready(read_A_4__ap_ready), - .read_A_4__ap_done(read_A_4__ap_done), - .read_A_4__ap_idle(read_A_4__ap_idle), - .read_A_5__ap_start(read_A_5__ap_start), - .read_A_5__ap_ready(read_A_5__ap_ready), - .read_A_5__ap_done(read_A_5__ap_done), - .read_A_5__ap_idle(read_A_5__ap_idle), - .read_A_6__ap_start(read_A_6__ap_start), - .read_A_6__ap_ready(read_A_6__ap_ready), - .read_A_6__ap_done(read_A_6__ap_done), - .read_A_6__ap_idle(read_A_6__ap_idle), - .read_A_7__ap_start(read_A_7__ap_start), - .read_A_7__ap_ready(read_A_7__ap_ready), - .read_A_7__ap_done(read_A_7__ap_done), - .read_A_7__ap_idle(read_A_7__ap_idle), - .read_B_0__ap_start(read_B_0__ap_start), - .read_B_0__ap_ready(read_B_0__ap_ready), - .read_B_0__ap_done(read_B_0__ap_done), - .read_B_0__ap_idle(read_B_0__ap_idle), - .read_B_1__ap_start(read_B_1__ap_start), - .read_B_1__ap_ready(read_B_1__ap_ready), - .read_B_1__ap_done(read_B_1__ap_done), - .read_B_1__ap_idle(read_B_1__ap_idle), - .read_B_2__ap_start(read_B_2__ap_start), - .read_B_2__ap_ready(read_B_2__ap_ready), - .read_B_2__ap_done(read_B_2__ap_done), - .read_B_2__ap_idle(read_B_2__ap_idle), - .read_B_3__ap_start(read_B_3__ap_start), - .read_B_3__ap_ready(read_B_3__ap_ready), - .read_B_3__ap_done(read_B_3__ap_done), - .read_B_3__ap_idle(read_B_3__ap_idle), - .read_C_0__ap_start(read_C_0__ap_start), - .read_C_0__ap_ready(read_C_0__ap_ready), - .read_C_0__ap_done(read_C_0__ap_done), - .read_C_0__ap_idle(read_C_0__ap_idle), - .read_C_1__ap_start(read_C_1__ap_start), - .read_C_1__ap_ready(read_C_1__ap_ready), - .read_C_1__ap_done(read_C_1__ap_done), - .read_C_1__ap_idle(read_C_1__ap_idle), - .read_C_2__ap_start(read_C_2__ap_start), - .read_C_2__ap_ready(read_C_2__ap_ready), - .read_C_2__ap_done(read_C_2__ap_done), - .read_C_2__ap_idle(read_C_2__ap_idle), - .read_C_3__ap_start(read_C_3__ap_start), - .read_C_3__ap_ready(read_C_3__ap_ready), - .read_C_3__ap_done(read_C_3__ap_done), - .read_C_3__ap_idle(read_C_3__ap_idle), - .read_C_4__ap_start(read_C_4__ap_start), - .read_C_4__ap_ready(read_C_4__ap_ready), - .read_C_4__ap_done(read_C_4__ap_done), - .read_C_4__ap_idle(read_C_4__ap_idle), - .read_C_5__ap_start(read_C_5__ap_start), - .read_C_5__ap_ready(read_C_5__ap_ready), - .read_C_5__ap_done(read_C_5__ap_done), - .read_C_5__ap_idle(read_C_5__ap_idle), - .read_C_6__ap_start(read_C_6__ap_start), - .read_C_6__ap_ready(read_C_6__ap_ready), - .read_C_6__ap_done(read_C_6__ap_done), - .read_C_6__ap_idle(read_C_6__ap_idle), - .read_C_7__ap_start(read_C_7__ap_start), - .read_C_7__ap_ready(read_C_7__ap_ready), - .read_C_7__ap_done(read_C_7__ap_done), - .read_C_7__ap_idle(read_C_7__ap_idle), - .read_edge_list_ptr_0__ap_start(read_edge_list_ptr_0__ap_start), - .read_edge_list_ptr_0__ap_ready(read_edge_list_ptr_0__ap_ready), - .read_edge_list_ptr_0__ap_done(read_edge_list_ptr_0__ap_done), - .read_edge_list_ptr_0__ap_idle(read_edge_list_ptr_0__ap_idle), - .write_C_0__ap_start(write_C_0__ap_start), - .write_C_0__ap_ready(write_C_0__ap_ready), - .write_C_0__ap_done(write_C_0__ap_done), - .write_C_0__ap_idle(write_C_0__ap_idle), - .write_C_1__ap_start(write_C_1__ap_start), - .write_C_1__ap_ready(write_C_1__ap_ready), - .write_C_1__ap_done(write_C_1__ap_done), - .write_C_1__ap_idle(write_C_1__ap_idle), - .write_C_2__ap_start(write_C_2__ap_start), - .write_C_2__ap_ready(write_C_2__ap_ready), - .write_C_2__ap_done(write_C_2__ap_done), - .write_C_2__ap_idle(write_C_2__ap_idle), - .write_C_3__ap_start(write_C_3__ap_start), - .write_C_3__ap_ready(write_C_3__ap_ready), - .write_C_3__ap_done(write_C_3__ap_done), - .write_C_3__ap_idle(write_C_3__ap_idle), - .write_C_4__ap_start(write_C_4__ap_start), - .write_C_4__ap_ready(write_C_4__ap_ready), - .write_C_4__ap_done(write_C_4__ap_done), - .write_C_4__ap_idle(write_C_4__ap_idle), - .write_C_5__ap_start(write_C_5__ap_start), - .write_C_5__ap_ready(write_C_5__ap_ready), - .write_C_5__ap_done(write_C_5__ap_done), - .write_C_5__ap_idle(write_C_5__ap_idle), - .write_C_6__ap_start(write_C_6__ap_start), - .write_C_6__ap_ready(write_C_6__ap_ready), - .write_C_6__ap_done(write_C_6__ap_done), - .write_C_6__ap_idle(write_C_6__ap_idle), - .write_C_7__ap_start(write_C_7__ap_start), - .write_C_7__ap_ready(write_C_7__ap_ready), - .write_C_7__ap_done(write_C_7__ap_done), - .write_C_7__ap_idle(write_C_7__ap_idle) - ); - - assign ap_rst_n_inv = (~ap_rst_n); - assign FloatvMultConst_0___M__q0 = M; - assign FloatvMultConst_0___P_N__q0 = P_N; - assign FloatvMultConst_0___beta_u__q0 = beta_u; - assign FloatvMultConst_1___M__q0 = M; - assign FloatvMultConst_1___P_N__q0 = P_N; - assign FloatvMultConst_1___beta_u__q0 = beta_u; - assign FloatvMultConst_2___M__q0 = M; - assign FloatvMultConst_2___P_N__q0 = P_N; - assign FloatvMultConst_2___beta_u__q0 = beta_u; - assign FloatvMultConst_3___M__q0 = M; - assign FloatvMultConst_3___P_N__q0 = P_N; - assign FloatvMultConst_3___beta_u__q0 = beta_u; - assign FloatvMultConst_4___M__q0 = M; - assign FloatvMultConst_4___P_N__q0 = P_N; - assign FloatvMultConst_4___beta_u__q0 = beta_u; - assign FloatvMultConst_5___M__q0 = M; - assign FloatvMultConst_5___P_N__q0 = P_N; - assign FloatvMultConst_5___beta_u__q0 = beta_u; - assign FloatvMultConst_6___M__q0 = M; - assign FloatvMultConst_6___P_N__q0 = P_N; - assign FloatvMultConst_6___beta_u__q0 = beta_u; - assign FloatvMultConst_7___M__q0 = M; - assign FloatvMultConst_7___P_N__q0 = P_N; - assign FloatvMultConst_7___beta_u__q0 = beta_u; - assign FloatvMultConst_8___M__q0 = M; - assign FloatvMultConst_8___P_N__q0 = P_N; - assign FloatvMultConst_8___alpha_u__q0 = alpha_u; - assign FloatvMultConst_9___M__q0 = M; - assign FloatvMultConst_9___P_N__q0 = P_N; - assign FloatvMultConst_9___alpha_u__q0 = alpha_u; - assign FloatvMultConst_10___M__q0 = M; - assign FloatvMultConst_10___P_N__q0 = P_N; - assign FloatvMultConst_10___alpha_u__q0 = alpha_u; - assign FloatvMultConst_11___M__q0 = M; - assign FloatvMultConst_11___P_N__q0 = P_N; - assign FloatvMultConst_11___alpha_u__q0 = alpha_u; - assign FloatvMultConst_12___M__q0 = M; - assign FloatvMultConst_12___P_N__q0 = P_N; - assign FloatvMultConst_12___alpha_u__q0 = alpha_u; - assign FloatvMultConst_13___M__q0 = M; - assign FloatvMultConst_13___P_N__q0 = P_N; - assign FloatvMultConst_13___alpha_u__q0 = alpha_u; - assign FloatvMultConst_14___M__q0 = M; - assign FloatvMultConst_14___P_N__q0 = P_N; - assign FloatvMultConst_14___alpha_u__q0 = alpha_u; - assign FloatvMultConst_15___M__q0 = M; - assign FloatvMultConst_15___P_N__q0 = P_N; - assign FloatvMultConst_15___alpha_u__q0 = alpha_u; - assign read_A_0___NUM_A_LEN__q0 = NUM_A_LEN; - assign read_A_0___P_N__q0 = P_N; - assign read_A_0___edge_list_ch_0__q0 = edge_list_ch_0; - assign read_A_1___NUM_A_LEN__q0 = NUM_A_LEN; - assign read_A_1___P_N__q0 = P_N; - assign read_A_1___edge_list_ch_1__q0 = edge_list_ch_1; - assign read_A_2___NUM_A_LEN__q0 = NUM_A_LEN; - assign read_A_2___P_N__q0 = P_N; - assign read_A_2___edge_list_ch_2__q0 = edge_list_ch_2; - assign read_A_3___NUM_A_LEN__q0 = NUM_A_LEN; - assign read_A_3___P_N__q0 = P_N; - assign read_A_3___edge_list_ch_3__q0 = edge_list_ch_3; - assign read_A_4___NUM_A_LEN__q0 = NUM_A_LEN; - assign read_A_4___P_N__q0 = P_N; - assign read_A_4___edge_list_ch_4__q0 = edge_list_ch_4; - assign read_A_5___NUM_A_LEN__q0 = NUM_A_LEN; - assign read_A_5___P_N__q0 = P_N; - assign read_A_5___edge_list_ch_5__q0 = edge_list_ch_5; - assign read_A_6___NUM_A_LEN__q0 = NUM_A_LEN; - assign read_A_6___P_N__q0 = P_N; - assign read_A_6___edge_list_ch_6__q0 = edge_list_ch_6; - assign read_A_7___NUM_A_LEN__q0 = NUM_A_LEN; - assign read_A_7___P_N__q0 = P_N; - assign read_A_7___edge_list_ch_7__q0 = edge_list_ch_7; - assign read_B_0___K__q0 = K; - assign read_B_0___P_N__q0 = P_N; - assign read_B_0___mat_B_ch_0__q0 = mat_B_ch_0; - assign read_B_1___K__q0 = K; - assign read_B_1___P_N__q0 = P_N; - assign read_B_1___mat_B_ch_1__q0 = mat_B_ch_1; - assign read_B_2___K__q0 = K; - assign read_B_2___P_N__q0 = P_N; - assign read_B_2___mat_B_ch_2__q0 = mat_B_ch_2; - assign read_B_3___K__q0 = K; - assign read_B_3___P_N__q0 = P_N; - assign read_B_3___mat_B_ch_3__q0 = mat_B_ch_3; - assign read_C_0___M__q0 = M; - assign read_C_0___P_N__q0 = P_N; - assign read_C_0___mat_C_ch_in_0__q0 = mat_C_ch_in_0; - assign read_C_1___M__q0 = M; - assign read_C_1___P_N__q0 = P_N; - assign read_C_1___mat_C_ch_in_1__q0 = mat_C_ch_in_1; - assign read_C_2___M__q0 = M; - assign read_C_2___P_N__q0 = P_N; - assign read_C_2___mat_C_ch_in_2__q0 = mat_C_ch_in_2; - assign read_C_3___M__q0 = M; - assign read_C_3___P_N__q0 = P_N; - assign read_C_3___mat_C_ch_in_3__q0 = mat_C_ch_in_3; - assign read_C_4___M__q0 = M; - assign read_C_4___P_N__q0 = P_N; - assign read_C_4___mat_C_ch_in_4__q0 = mat_C_ch_in_4; - assign read_C_5___M__q0 = M; - assign read_C_5___P_N__q0 = P_N; - assign read_C_5___mat_C_ch_in_5__q0 = mat_C_ch_in_5; - assign read_C_6___M__q0 = M; - assign read_C_6___P_N__q0 = P_N; - assign read_C_6___mat_C_ch_in_6__q0 = mat_C_ch_in_6; - assign read_C_7___M__q0 = M; - assign read_C_7___P_N__q0 = P_N; - assign read_C_7___mat_C_ch_in_7__q0 = mat_C_ch_in_7; - assign read_edge_list_ptr_0___K__q0 = K; - assign read_edge_list_ptr_0___M__q0 = M; - assign read_edge_list_ptr_0___NUM_ITE__q0 = NUM_ITE; - assign read_edge_list_ptr_0___P_N__q0 = P_N; - assign read_edge_list_ptr_0___edge_list_ptr__q0 = edge_list_ptr; - assign write_C_0___mat_C_ch_0__q0 = mat_C_ch_0; - assign write_C_1___mat_C_ch_1__q0 = mat_C_ch_1; - assign write_C_2___mat_C_ch_2__q0 = mat_C_ch_2; - assign write_C_3___mat_C_ch_3__q0 = mat_C_ch_3; - assign write_C_4___mat_C_ch_4__q0 = mat_C_ch_4; - assign write_C_5___mat_C_ch_5__q0 = mat_C_ch_5; - assign write_C_6___mat_C_ch_6__q0 = mat_C_ch_6; - assign write_C_7___mat_C_ch_7__q0 = mat_C_ch_7; - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/Sextans_control_s_axi.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/Sextans_control_s_axi.v deleted file mode 100644 index bf9b0fab..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/Sextans_control_s_axi.v +++ /dev/null @@ -1,1574 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== -`timescale 1ns/1ps -module Sextans_control_s_axi -#(parameter - C_S_AXI_ADDR_WIDTH = 9, - C_S_AXI_DATA_WIDTH = 32 -)( - input wire ACLK, - input wire ARESET, - input wire ACLK_EN, - input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR, - input wire AWVALID, - output wire AWREADY, - input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA, - input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB, - input wire WVALID, - output wire WREADY, - output wire [1:0] BRESP, - output wire BVALID, - input wire BREADY, - input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR, - input wire ARVALID, - output wire ARREADY, - output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA, - output wire [1:0] RRESP, - output wire RVALID, - input wire RREADY, - output wire interrupt, - output wire [63:0] edge_list_ptr, - output wire [63:0] edge_list_ch_0, - output wire [63:0] edge_list_ch_1, - output wire [63:0] edge_list_ch_2, - output wire [63:0] edge_list_ch_3, - output wire [63:0] edge_list_ch_4, - output wire [63:0] edge_list_ch_5, - output wire [63:0] edge_list_ch_6, - output wire [63:0] edge_list_ch_7, - output wire [63:0] mat_B_ch_0, - output wire [63:0] mat_B_ch_1, - output wire [63:0] mat_B_ch_2, - output wire [63:0] mat_B_ch_3, - output wire [63:0] mat_C_ch_in_0, - output wire [63:0] mat_C_ch_in_1, - output wire [63:0] mat_C_ch_in_2, - output wire [63:0] mat_C_ch_in_3, - output wire [63:0] mat_C_ch_in_4, - output wire [63:0] mat_C_ch_in_5, - output wire [63:0] mat_C_ch_in_6, - output wire [63:0] mat_C_ch_in_7, - output wire [63:0] mat_C_ch_0, - output wire [63:0] mat_C_ch_1, - output wire [63:0] mat_C_ch_2, - output wire [63:0] mat_C_ch_3, - output wire [63:0] mat_C_ch_4, - output wire [63:0] mat_C_ch_5, - output wire [63:0] mat_C_ch_6, - output wire [63:0] mat_C_ch_7, - output wire [31:0] NUM_ITE, - output wire [31:0] NUM_A_LEN, - output wire [31:0] M, - output wire [31:0] K, - output wire [31:0] P_N, - output wire [31:0] alpha_u, - output wire [31:0] beta_u, - output wire ap_start, - input wire ap_done, - input wire ap_ready, - input wire ap_idle -); -//------------------------Address Info------------------- -// 0x000 : Control signals -// bit 0 - ap_start (Read/Write/SC) -// bit 1 - ap_done (Read/COR) -// bit 2 - ap_idle (Read) -// bit 3 - ap_ready (Read/COR) -// bit 7 - auto_restart (Read/Write) -// bit 9 - interrupt (Read) -// others - reserved -// 0x004 : Global Interrupt Enable Register -// bit 0 - Global Interrupt Enable (Read/Write) -// others - reserved -// 0x008 : IP Interrupt Enable Register (Read/Write) -// bit 0 - enable ap_done interrupt (Read/Write) -// others - reserved -// 0x00c : IP Interrupt Status Register (Read/TOW) -// bit 0 - ap_done (Read/TOW) -// others - reserved -// 0x010 : Data signal of edge_list_ptr -// bit 31~0 - edge_list_ptr[31:0] (Read/Write) -// 0x014 : Data signal of edge_list_ptr -// bit 31~0 - edge_list_ptr[63:32] (Read/Write) -// 0x018 : reserved -// 0x01c : Data signal of edge_list_ch_0 -// bit 31~0 - edge_list_ch_0[31:0] (Read/Write) -// 0x020 : Data signal of edge_list_ch_0 -// bit 31~0 - edge_list_ch_0[63:32] (Read/Write) -// 0x024 : reserved -// 0x028 : Data signal of edge_list_ch_1 -// bit 31~0 - edge_list_ch_1[31:0] (Read/Write) -// 0x02c : Data signal of edge_list_ch_1 -// bit 31~0 - edge_list_ch_1[63:32] (Read/Write) -// 0x030 : reserved -// 0x034 : Data signal of edge_list_ch_2 -// bit 31~0 - edge_list_ch_2[31:0] (Read/Write) -// 0x038 : Data signal of edge_list_ch_2 -// bit 31~0 - edge_list_ch_2[63:32] (Read/Write) -// 0x03c : reserved -// 0x040 : Data signal of edge_list_ch_3 -// bit 31~0 - edge_list_ch_3[31:0] (Read/Write) -// 0x044 : Data signal of edge_list_ch_3 -// bit 31~0 - edge_list_ch_3[63:32] (Read/Write) -// 0x048 : reserved -// 0x04c : Data signal of edge_list_ch_4 -// bit 31~0 - edge_list_ch_4[31:0] (Read/Write) -// 0x050 : Data signal of edge_list_ch_4 -// bit 31~0 - edge_list_ch_4[63:32] (Read/Write) -// 0x054 : reserved -// 0x058 : Data signal of edge_list_ch_5 -// bit 31~0 - edge_list_ch_5[31:0] (Read/Write) -// 0x05c : Data signal of edge_list_ch_5 -// bit 31~0 - edge_list_ch_5[63:32] (Read/Write) -// 0x060 : reserved -// 0x064 : Data signal of edge_list_ch_6 -// bit 31~0 - edge_list_ch_6[31:0] (Read/Write) -// 0x068 : Data signal of edge_list_ch_6 -// bit 31~0 - edge_list_ch_6[63:32] (Read/Write) -// 0x06c : reserved -// 0x070 : Data signal of edge_list_ch_7 -// bit 31~0 - edge_list_ch_7[31:0] (Read/Write) -// 0x074 : Data signal of edge_list_ch_7 -// bit 31~0 - edge_list_ch_7[63:32] (Read/Write) -// 0x078 : reserved -// 0x07c : Data signal of mat_B_ch_0 -// bit 31~0 - mat_B_ch_0[31:0] (Read/Write) -// 0x080 : Data signal of mat_B_ch_0 -// bit 31~0 - mat_B_ch_0[63:32] (Read/Write) -// 0x084 : reserved -// 0x088 : Data signal of mat_B_ch_1 -// bit 31~0 - mat_B_ch_1[31:0] (Read/Write) -// 0x08c : Data signal of mat_B_ch_1 -// bit 31~0 - mat_B_ch_1[63:32] (Read/Write) -// 0x090 : reserved -// 0x094 : Data signal of mat_B_ch_2 -// bit 31~0 - mat_B_ch_2[31:0] (Read/Write) -// 0x098 : Data signal of mat_B_ch_2 -// bit 31~0 - mat_B_ch_2[63:32] (Read/Write) -// 0x09c : reserved -// 0x0a0 : Data signal of mat_B_ch_3 -// bit 31~0 - mat_B_ch_3[31:0] (Read/Write) -// 0x0a4 : Data signal of mat_B_ch_3 -// bit 31~0 - mat_B_ch_3[63:32] (Read/Write) -// 0x0a8 : reserved -// 0x0ac : Data signal of mat_C_ch_in_0 -// bit 31~0 - mat_C_ch_in_0[31:0] (Read/Write) -// 0x0b0 : Data signal of mat_C_ch_in_0 -// bit 31~0 - mat_C_ch_in_0[63:32] (Read/Write) -// 0x0b4 : reserved -// 0x0b8 : Data signal of mat_C_ch_in_1 -// bit 31~0 - mat_C_ch_in_1[31:0] (Read/Write) -// 0x0bc : Data signal of mat_C_ch_in_1 -// bit 31~0 - mat_C_ch_in_1[63:32] (Read/Write) -// 0x0c0 : reserved -// 0x0c4 : Data signal of mat_C_ch_in_2 -// bit 31~0 - mat_C_ch_in_2[31:0] (Read/Write) -// 0x0c8 : Data signal of mat_C_ch_in_2 -// bit 31~0 - mat_C_ch_in_2[63:32] (Read/Write) -// 0x0cc : reserved -// 0x0d0 : Data signal of mat_C_ch_in_3 -// bit 31~0 - mat_C_ch_in_3[31:0] (Read/Write) -// 0x0d4 : Data signal of mat_C_ch_in_3 -// bit 31~0 - mat_C_ch_in_3[63:32] (Read/Write) -// 0x0d8 : reserved -// 0x0dc : Data signal of mat_C_ch_in_4 -// bit 31~0 - mat_C_ch_in_4[31:0] (Read/Write) -// 0x0e0 : Data signal of mat_C_ch_in_4 -// bit 31~0 - mat_C_ch_in_4[63:32] (Read/Write) -// 0x0e4 : reserved -// 0x0e8 : Data signal of mat_C_ch_in_5 -// bit 31~0 - mat_C_ch_in_5[31:0] (Read/Write) -// 0x0ec : Data signal of mat_C_ch_in_5 -// bit 31~0 - mat_C_ch_in_5[63:32] (Read/Write) -// 0x0f0 : reserved -// 0x0f4 : Data signal of mat_C_ch_in_6 -// bit 31~0 - mat_C_ch_in_6[31:0] (Read/Write) -// 0x0f8 : Data signal of mat_C_ch_in_6 -// bit 31~0 - mat_C_ch_in_6[63:32] (Read/Write) -// 0x0fc : reserved -// 0x100 : Data signal of mat_C_ch_in_7 -// bit 31~0 - mat_C_ch_in_7[31:0] (Read/Write) -// 0x104 : Data signal of mat_C_ch_in_7 -// bit 31~0 - mat_C_ch_in_7[63:32] (Read/Write) -// 0x108 : reserved -// 0x10c : Data signal of mat_C_ch_0 -// bit 31~0 - mat_C_ch_0[31:0] (Read/Write) -// 0x110 : Data signal of mat_C_ch_0 -// bit 31~0 - mat_C_ch_0[63:32] (Read/Write) -// 0x114 : reserved -// 0x118 : Data signal of mat_C_ch_1 -// bit 31~0 - mat_C_ch_1[31:0] (Read/Write) -// 0x11c : Data signal of mat_C_ch_1 -// bit 31~0 - mat_C_ch_1[63:32] (Read/Write) -// 0x120 : reserved -// 0x124 : Data signal of mat_C_ch_2 -// bit 31~0 - mat_C_ch_2[31:0] (Read/Write) -// 0x128 : Data signal of mat_C_ch_2 -// bit 31~0 - mat_C_ch_2[63:32] (Read/Write) -// 0x12c : reserved -// 0x130 : Data signal of mat_C_ch_3 -// bit 31~0 - mat_C_ch_3[31:0] (Read/Write) -// 0x134 : Data signal of mat_C_ch_3 -// bit 31~0 - mat_C_ch_3[63:32] (Read/Write) -// 0x138 : reserved -// 0x13c : Data signal of mat_C_ch_4 -// bit 31~0 - mat_C_ch_4[31:0] (Read/Write) -// 0x140 : Data signal of mat_C_ch_4 -// bit 31~0 - mat_C_ch_4[63:32] (Read/Write) -// 0x144 : reserved -// 0x148 : Data signal of mat_C_ch_5 -// bit 31~0 - mat_C_ch_5[31:0] (Read/Write) -// 0x14c : Data signal of mat_C_ch_5 -// bit 31~0 - mat_C_ch_5[63:32] (Read/Write) -// 0x150 : reserved -// 0x154 : Data signal of mat_C_ch_6 -// bit 31~0 - mat_C_ch_6[31:0] (Read/Write) -// 0x158 : Data signal of mat_C_ch_6 -// bit 31~0 - mat_C_ch_6[63:32] (Read/Write) -// 0x15c : reserved -// 0x160 : Data signal of mat_C_ch_7 -// bit 31~0 - mat_C_ch_7[31:0] (Read/Write) -// 0x164 : Data signal of mat_C_ch_7 -// bit 31~0 - mat_C_ch_7[63:32] (Read/Write) -// 0x168 : reserved -// 0x16c : Data signal of NUM_ITE -// bit 31~0 - NUM_ITE[31:0] (Read/Write) -// 0x170 : reserved -// 0x174 : Data signal of NUM_A_LEN -// bit 31~0 - NUM_A_LEN[31:0] (Read/Write) -// 0x178 : reserved -// 0x17c : Data signal of M -// bit 31~0 - M[31:0] (Read/Write) -// 0x180 : reserved -// 0x184 : Data signal of K -// bit 31~0 - K[31:0] (Read/Write) -// 0x188 : reserved -// 0x18c : Data signal of P_N -// bit 31~0 - P_N[31:0] (Read/Write) -// 0x190 : reserved -// 0x194 : Data signal of alpha_u -// bit 31~0 - alpha_u[31:0] (Read/Write) -// 0x198 : reserved -// 0x19c : Data signal of beta_u -// bit 31~0 - beta_u[31:0] (Read/Write) -// 0x1a0 : reserved -// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) - -//------------------------Parameter---------------------- -localparam - ADDR_AP_CTRL = 9'h000, - ADDR_GIE = 9'h004, - ADDR_IER = 9'h008, - ADDR_ISR = 9'h00c, - ADDR_EDGE_LIST_PTR_DATA_0 = 9'h010, - ADDR_EDGE_LIST_PTR_DATA_1 = 9'h014, - ADDR_EDGE_LIST_PTR_CTRL = 9'h018, - ADDR_EDGE_LIST_CH_0_DATA_0 = 9'h01c, - ADDR_EDGE_LIST_CH_0_DATA_1 = 9'h020, - ADDR_EDGE_LIST_CH_0_CTRL = 9'h024, - ADDR_EDGE_LIST_CH_1_DATA_0 = 9'h028, - ADDR_EDGE_LIST_CH_1_DATA_1 = 9'h02c, - ADDR_EDGE_LIST_CH_1_CTRL = 9'h030, - ADDR_EDGE_LIST_CH_2_DATA_0 = 9'h034, - ADDR_EDGE_LIST_CH_2_DATA_1 = 9'h038, - ADDR_EDGE_LIST_CH_2_CTRL = 9'h03c, - ADDR_EDGE_LIST_CH_3_DATA_0 = 9'h040, - ADDR_EDGE_LIST_CH_3_DATA_1 = 9'h044, - ADDR_EDGE_LIST_CH_3_CTRL = 9'h048, - ADDR_EDGE_LIST_CH_4_DATA_0 = 9'h04c, - ADDR_EDGE_LIST_CH_4_DATA_1 = 9'h050, - ADDR_EDGE_LIST_CH_4_CTRL = 9'h054, - ADDR_EDGE_LIST_CH_5_DATA_0 = 9'h058, - ADDR_EDGE_LIST_CH_5_DATA_1 = 9'h05c, - ADDR_EDGE_LIST_CH_5_CTRL = 9'h060, - ADDR_EDGE_LIST_CH_6_DATA_0 = 9'h064, - ADDR_EDGE_LIST_CH_6_DATA_1 = 9'h068, - ADDR_EDGE_LIST_CH_6_CTRL = 9'h06c, - ADDR_EDGE_LIST_CH_7_DATA_0 = 9'h070, - ADDR_EDGE_LIST_CH_7_DATA_1 = 9'h074, - ADDR_EDGE_LIST_CH_7_CTRL = 9'h078, - ADDR_MAT_B_CH_0_DATA_0 = 9'h07c, - ADDR_MAT_B_CH_0_DATA_1 = 9'h080, - ADDR_MAT_B_CH_0_CTRL = 9'h084, - ADDR_MAT_B_CH_1_DATA_0 = 9'h088, - ADDR_MAT_B_CH_1_DATA_1 = 9'h08c, - ADDR_MAT_B_CH_1_CTRL = 9'h090, - ADDR_MAT_B_CH_2_DATA_0 = 9'h094, - ADDR_MAT_B_CH_2_DATA_1 = 9'h098, - ADDR_MAT_B_CH_2_CTRL = 9'h09c, - ADDR_MAT_B_CH_3_DATA_0 = 9'h0a0, - ADDR_MAT_B_CH_3_DATA_1 = 9'h0a4, - ADDR_MAT_B_CH_3_CTRL = 9'h0a8, - ADDR_MAT_C_CH_IN_0_DATA_0 = 9'h0ac, - ADDR_MAT_C_CH_IN_0_DATA_1 = 9'h0b0, - ADDR_MAT_C_CH_IN_0_CTRL = 9'h0b4, - ADDR_MAT_C_CH_IN_1_DATA_0 = 9'h0b8, - ADDR_MAT_C_CH_IN_1_DATA_1 = 9'h0bc, - ADDR_MAT_C_CH_IN_1_CTRL = 9'h0c0, - ADDR_MAT_C_CH_IN_2_DATA_0 = 9'h0c4, - ADDR_MAT_C_CH_IN_2_DATA_1 = 9'h0c8, - ADDR_MAT_C_CH_IN_2_CTRL = 9'h0cc, - ADDR_MAT_C_CH_IN_3_DATA_0 = 9'h0d0, - ADDR_MAT_C_CH_IN_3_DATA_1 = 9'h0d4, - ADDR_MAT_C_CH_IN_3_CTRL = 9'h0d8, - ADDR_MAT_C_CH_IN_4_DATA_0 = 9'h0dc, - ADDR_MAT_C_CH_IN_4_DATA_1 = 9'h0e0, - ADDR_MAT_C_CH_IN_4_CTRL = 9'h0e4, - ADDR_MAT_C_CH_IN_5_DATA_0 = 9'h0e8, - ADDR_MAT_C_CH_IN_5_DATA_1 = 9'h0ec, - ADDR_MAT_C_CH_IN_5_CTRL = 9'h0f0, - ADDR_MAT_C_CH_IN_6_DATA_0 = 9'h0f4, - ADDR_MAT_C_CH_IN_6_DATA_1 = 9'h0f8, - ADDR_MAT_C_CH_IN_6_CTRL = 9'h0fc, - ADDR_MAT_C_CH_IN_7_DATA_0 = 9'h100, - ADDR_MAT_C_CH_IN_7_DATA_1 = 9'h104, - ADDR_MAT_C_CH_IN_7_CTRL = 9'h108, - ADDR_MAT_C_CH_0_DATA_0 = 9'h10c, - ADDR_MAT_C_CH_0_DATA_1 = 9'h110, - ADDR_MAT_C_CH_0_CTRL = 9'h114, - ADDR_MAT_C_CH_1_DATA_0 = 9'h118, - ADDR_MAT_C_CH_1_DATA_1 = 9'h11c, - ADDR_MAT_C_CH_1_CTRL = 9'h120, - ADDR_MAT_C_CH_2_DATA_0 = 9'h124, - ADDR_MAT_C_CH_2_DATA_1 = 9'h128, - ADDR_MAT_C_CH_2_CTRL = 9'h12c, - ADDR_MAT_C_CH_3_DATA_0 = 9'h130, - ADDR_MAT_C_CH_3_DATA_1 = 9'h134, - ADDR_MAT_C_CH_3_CTRL = 9'h138, - ADDR_MAT_C_CH_4_DATA_0 = 9'h13c, - ADDR_MAT_C_CH_4_DATA_1 = 9'h140, - ADDR_MAT_C_CH_4_CTRL = 9'h144, - ADDR_MAT_C_CH_5_DATA_0 = 9'h148, - ADDR_MAT_C_CH_5_DATA_1 = 9'h14c, - ADDR_MAT_C_CH_5_CTRL = 9'h150, - ADDR_MAT_C_CH_6_DATA_0 = 9'h154, - ADDR_MAT_C_CH_6_DATA_1 = 9'h158, - ADDR_MAT_C_CH_6_CTRL = 9'h15c, - ADDR_MAT_C_CH_7_DATA_0 = 9'h160, - ADDR_MAT_C_CH_7_DATA_1 = 9'h164, - ADDR_MAT_C_CH_7_CTRL = 9'h168, - ADDR_NUM_ITE_DATA_0 = 9'h16c, - ADDR_NUM_ITE_CTRL = 9'h170, - ADDR_NUM_A_LEN_DATA_0 = 9'h174, - ADDR_NUM_A_LEN_CTRL = 9'h178, - ADDR_M_DATA_0 = 9'h17c, - ADDR_M_CTRL = 9'h180, - ADDR_K_DATA_0 = 9'h184, - ADDR_K_CTRL = 9'h188, - ADDR_P_N_DATA_0 = 9'h18c, - ADDR_P_N_CTRL = 9'h190, - ADDR_ALPHA_U_DATA_0 = 9'h194, - ADDR_ALPHA_U_CTRL = 9'h198, - ADDR_BETA_U_DATA_0 = 9'h19c, - ADDR_BETA_U_CTRL = 9'h1a0, - WRIDLE = 2'd0, - WRDATA = 2'd1, - WRRESP = 2'd2, - WRRESET = 2'd3, - RDIDLE = 2'd0, - RDDATA = 2'd1, - RDRESET = 2'd2, - ADDR_BITS = 9; - -//------------------------Local signal------------------- - reg [1:0] wstate = WRRESET; - reg [1:0] wnext; - reg [ADDR_BITS-1:0] waddr; - wire [C_S_AXI_DATA_WIDTH-1:0] wmask; - wire aw_hs; - wire w_hs; - reg [1:0] rstate = RDRESET; - reg [1:0] rnext; - reg [C_S_AXI_DATA_WIDTH-1:0] rdata; - wire ar_hs; - wire [ADDR_BITS-1:0] raddr; - // internal registers - reg int_ap_idle; - reg int_ap_ready = 1'b0; - wire task_ap_ready; - reg int_ap_done = 1'b0; - wire task_ap_done; - reg int_task_ap_done = 1'b0; - reg int_ap_start = 1'b0; - reg int_interrupt = 1'b0; - reg int_auto_restart = 1'b0; - reg auto_restart_status = 1'b0; - wire auto_restart_done; - reg int_gie = 1'b0; - reg int_ier = 1'b0; - reg int_isr = 1'b0; - reg [63:0] int_edge_list_ptr = 'b0; - reg [63:0] int_edge_list_ch_0 = 'b0; - reg [63:0] int_edge_list_ch_1 = 'b0; - reg [63:0] int_edge_list_ch_2 = 'b0; - reg [63:0] int_edge_list_ch_3 = 'b0; - reg [63:0] int_edge_list_ch_4 = 'b0; - reg [63:0] int_edge_list_ch_5 = 'b0; - reg [63:0] int_edge_list_ch_6 = 'b0; - reg [63:0] int_edge_list_ch_7 = 'b0; - reg [63:0] int_mat_B_ch_0 = 'b0; - reg [63:0] int_mat_B_ch_1 = 'b0; - reg [63:0] int_mat_B_ch_2 = 'b0; - reg [63:0] int_mat_B_ch_3 = 'b0; - reg [63:0] int_mat_C_ch_in_0 = 'b0; - reg [63:0] int_mat_C_ch_in_1 = 'b0; - reg [63:0] int_mat_C_ch_in_2 = 'b0; - reg [63:0] int_mat_C_ch_in_3 = 'b0; - reg [63:0] int_mat_C_ch_in_4 = 'b0; - reg [63:0] int_mat_C_ch_in_5 = 'b0; - reg [63:0] int_mat_C_ch_in_6 = 'b0; - reg [63:0] int_mat_C_ch_in_7 = 'b0; - reg [63:0] int_mat_C_ch_0 = 'b0; - reg [63:0] int_mat_C_ch_1 = 'b0; - reg [63:0] int_mat_C_ch_2 = 'b0; - reg [63:0] int_mat_C_ch_3 = 'b0; - reg [63:0] int_mat_C_ch_4 = 'b0; - reg [63:0] int_mat_C_ch_5 = 'b0; - reg [63:0] int_mat_C_ch_6 = 'b0; - reg [63:0] int_mat_C_ch_7 = 'b0; - reg [31:0] int_NUM_ITE = 'b0; - reg [31:0] int_NUM_A_LEN = 'b0; - reg [31:0] int_M = 'b0; - reg [31:0] int_K = 'b0; - reg [31:0] int_P_N = 'b0; - reg [31:0] int_alpha_u = 'b0; - reg [31:0] int_beta_u = 'b0; - -//------------------------Instantiation------------------ - - -//------------------------AXI write fsm------------------ -assign AWREADY = (wstate == WRIDLE); -assign WREADY = (wstate == WRDATA); -assign BRESP = 2'b00; // OKAY -assign BVALID = (wstate == WRRESP); -assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} }; -assign aw_hs = AWVALID & AWREADY; -assign w_hs = WVALID & WREADY; - -// wstate -always @(posedge ACLK) begin - if (ARESET) - wstate <= WRRESET; - else if (ACLK_EN) - wstate <= wnext; -end - -// wnext -always @(*) begin - case (wstate) - WRIDLE: - if (AWVALID) - wnext = WRDATA; - else - wnext = WRIDLE; - WRDATA: - if (WVALID) - wnext = WRRESP; - else - wnext = WRDATA; - WRRESP: - if (BREADY) - wnext = WRIDLE; - else - wnext = WRRESP; - default: - wnext = WRIDLE; - endcase -end - -// waddr -always @(posedge ACLK) begin - if (ACLK_EN) begin - if (aw_hs) - waddr <= AWADDR[ADDR_BITS-1:0]; - end -end - -//------------------------AXI read fsm------------------- -assign ARREADY = (rstate == RDIDLE); -assign RDATA = rdata; -assign RRESP = 2'b00; // OKAY -assign RVALID = (rstate == RDDATA); -assign ar_hs = ARVALID & ARREADY; -assign raddr = ARADDR[ADDR_BITS-1:0]; - -// rstate -always @(posedge ACLK) begin - if (ARESET) - rstate <= RDRESET; - else if (ACLK_EN) - rstate <= rnext; -end - -// rnext -always @(*) begin - case (rstate) - RDIDLE: - if (ARVALID) - rnext = RDDATA; - else - rnext = RDIDLE; - RDDATA: - if (RREADY & RVALID) - rnext = RDIDLE; - else - rnext = RDDATA; - default: - rnext = RDIDLE; - endcase -end - -// rdata -always @(posedge ACLK) begin - if (ACLK_EN) begin - if (ar_hs) begin - rdata <= 'b0; - case (raddr) - ADDR_AP_CTRL: begin - rdata[0] <= int_ap_start; - rdata[1] <= int_task_ap_done; - rdata[2] <= int_ap_idle; - rdata[3] <= int_ap_ready; - rdata[7] <= int_auto_restart; - rdata[9] <= int_interrupt; - end - ADDR_GIE: begin - rdata <= int_gie; - end - ADDR_IER: begin - rdata <= int_ier; - end - ADDR_ISR: begin - rdata <= int_isr; - end - ADDR_EDGE_LIST_PTR_DATA_0: begin - rdata <= int_edge_list_ptr[31:0]; - end - ADDR_EDGE_LIST_PTR_DATA_1: begin - rdata <= int_edge_list_ptr[63:32]; - end - ADDR_EDGE_LIST_CH_0_DATA_0: begin - rdata <= int_edge_list_ch_0[31:0]; - end - ADDR_EDGE_LIST_CH_0_DATA_1: begin - rdata <= int_edge_list_ch_0[63:32]; - end - ADDR_EDGE_LIST_CH_1_DATA_0: begin - rdata <= int_edge_list_ch_1[31:0]; - end - ADDR_EDGE_LIST_CH_1_DATA_1: begin - rdata <= int_edge_list_ch_1[63:32]; - end - ADDR_EDGE_LIST_CH_2_DATA_0: begin - rdata <= int_edge_list_ch_2[31:0]; - end - ADDR_EDGE_LIST_CH_2_DATA_1: begin - rdata <= int_edge_list_ch_2[63:32]; - end - ADDR_EDGE_LIST_CH_3_DATA_0: begin - rdata <= int_edge_list_ch_3[31:0]; - end - ADDR_EDGE_LIST_CH_3_DATA_1: begin - rdata <= int_edge_list_ch_3[63:32]; - end - ADDR_EDGE_LIST_CH_4_DATA_0: begin - rdata <= int_edge_list_ch_4[31:0]; - end - ADDR_EDGE_LIST_CH_4_DATA_1: begin - rdata <= int_edge_list_ch_4[63:32]; - end - ADDR_EDGE_LIST_CH_5_DATA_0: begin - rdata <= int_edge_list_ch_5[31:0]; - end - ADDR_EDGE_LIST_CH_5_DATA_1: begin - rdata <= int_edge_list_ch_5[63:32]; - end - ADDR_EDGE_LIST_CH_6_DATA_0: begin - rdata <= int_edge_list_ch_6[31:0]; - end - ADDR_EDGE_LIST_CH_6_DATA_1: begin - rdata <= int_edge_list_ch_6[63:32]; - end - ADDR_EDGE_LIST_CH_7_DATA_0: begin - rdata <= int_edge_list_ch_7[31:0]; - end - ADDR_EDGE_LIST_CH_7_DATA_1: begin - rdata <= int_edge_list_ch_7[63:32]; - end - ADDR_MAT_B_CH_0_DATA_0: begin - rdata <= int_mat_B_ch_0[31:0]; - end - ADDR_MAT_B_CH_0_DATA_1: begin - rdata <= int_mat_B_ch_0[63:32]; - end - ADDR_MAT_B_CH_1_DATA_0: begin - rdata <= int_mat_B_ch_1[31:0]; - end - ADDR_MAT_B_CH_1_DATA_1: begin - rdata <= int_mat_B_ch_1[63:32]; - end - ADDR_MAT_B_CH_2_DATA_0: begin - rdata <= int_mat_B_ch_2[31:0]; - end - ADDR_MAT_B_CH_2_DATA_1: begin - rdata <= int_mat_B_ch_2[63:32]; - end - ADDR_MAT_B_CH_3_DATA_0: begin - rdata <= int_mat_B_ch_3[31:0]; - end - ADDR_MAT_B_CH_3_DATA_1: begin - rdata <= int_mat_B_ch_3[63:32]; - end - ADDR_MAT_C_CH_IN_0_DATA_0: begin - rdata <= int_mat_C_ch_in_0[31:0]; - end - ADDR_MAT_C_CH_IN_0_DATA_1: begin - rdata <= int_mat_C_ch_in_0[63:32]; - end - ADDR_MAT_C_CH_IN_1_DATA_0: begin - rdata <= int_mat_C_ch_in_1[31:0]; - end - ADDR_MAT_C_CH_IN_1_DATA_1: begin - rdata <= int_mat_C_ch_in_1[63:32]; - end - ADDR_MAT_C_CH_IN_2_DATA_0: begin - rdata <= int_mat_C_ch_in_2[31:0]; - end - ADDR_MAT_C_CH_IN_2_DATA_1: begin - rdata <= int_mat_C_ch_in_2[63:32]; - end - ADDR_MAT_C_CH_IN_3_DATA_0: begin - rdata <= int_mat_C_ch_in_3[31:0]; - end - ADDR_MAT_C_CH_IN_3_DATA_1: begin - rdata <= int_mat_C_ch_in_3[63:32]; - end - ADDR_MAT_C_CH_IN_4_DATA_0: begin - rdata <= int_mat_C_ch_in_4[31:0]; - end - ADDR_MAT_C_CH_IN_4_DATA_1: begin - rdata <= int_mat_C_ch_in_4[63:32]; - end - ADDR_MAT_C_CH_IN_5_DATA_0: begin - rdata <= int_mat_C_ch_in_5[31:0]; - end - ADDR_MAT_C_CH_IN_5_DATA_1: begin - rdata <= int_mat_C_ch_in_5[63:32]; - end - ADDR_MAT_C_CH_IN_6_DATA_0: begin - rdata <= int_mat_C_ch_in_6[31:0]; - end - ADDR_MAT_C_CH_IN_6_DATA_1: begin - rdata <= int_mat_C_ch_in_6[63:32]; - end - ADDR_MAT_C_CH_IN_7_DATA_0: begin - rdata <= int_mat_C_ch_in_7[31:0]; - end - ADDR_MAT_C_CH_IN_7_DATA_1: begin - rdata <= int_mat_C_ch_in_7[63:32]; - end - ADDR_MAT_C_CH_0_DATA_0: begin - rdata <= int_mat_C_ch_0[31:0]; - end - ADDR_MAT_C_CH_0_DATA_1: begin - rdata <= int_mat_C_ch_0[63:32]; - end - ADDR_MAT_C_CH_1_DATA_0: begin - rdata <= int_mat_C_ch_1[31:0]; - end - ADDR_MAT_C_CH_1_DATA_1: begin - rdata <= int_mat_C_ch_1[63:32]; - end - ADDR_MAT_C_CH_2_DATA_0: begin - rdata <= int_mat_C_ch_2[31:0]; - end - ADDR_MAT_C_CH_2_DATA_1: begin - rdata <= int_mat_C_ch_2[63:32]; - end - ADDR_MAT_C_CH_3_DATA_0: begin - rdata <= int_mat_C_ch_3[31:0]; - end - ADDR_MAT_C_CH_3_DATA_1: begin - rdata <= int_mat_C_ch_3[63:32]; - end - ADDR_MAT_C_CH_4_DATA_0: begin - rdata <= int_mat_C_ch_4[31:0]; - end - ADDR_MAT_C_CH_4_DATA_1: begin - rdata <= int_mat_C_ch_4[63:32]; - end - ADDR_MAT_C_CH_5_DATA_0: begin - rdata <= int_mat_C_ch_5[31:0]; - end - ADDR_MAT_C_CH_5_DATA_1: begin - rdata <= int_mat_C_ch_5[63:32]; - end - ADDR_MAT_C_CH_6_DATA_0: begin - rdata <= int_mat_C_ch_6[31:0]; - end - ADDR_MAT_C_CH_6_DATA_1: begin - rdata <= int_mat_C_ch_6[63:32]; - end - ADDR_MAT_C_CH_7_DATA_0: begin - rdata <= int_mat_C_ch_7[31:0]; - end - ADDR_MAT_C_CH_7_DATA_1: begin - rdata <= int_mat_C_ch_7[63:32]; - end - ADDR_NUM_ITE_DATA_0: begin - rdata <= int_NUM_ITE[31:0]; - end - ADDR_NUM_A_LEN_DATA_0: begin - rdata <= int_NUM_A_LEN[31:0]; - end - ADDR_M_DATA_0: begin - rdata <= int_M[31:0]; - end - ADDR_K_DATA_0: begin - rdata <= int_K[31:0]; - end - ADDR_P_N_DATA_0: begin - rdata <= int_P_N[31:0]; - end - ADDR_ALPHA_U_DATA_0: begin - rdata <= int_alpha_u[31:0]; - end - ADDR_BETA_U_DATA_0: begin - rdata <= int_beta_u[31:0]; - end - endcase - end - end -end - - -//------------------------Register logic----------------- -assign interrupt = int_interrupt; -assign ap_start = int_ap_start; -assign task_ap_done = (ap_done && !auto_restart_status) || auto_restart_done; -assign task_ap_ready = ap_ready && !int_auto_restart; -assign auto_restart_done = auto_restart_status && (ap_idle && !int_ap_idle); -assign edge_list_ptr = int_edge_list_ptr; -assign edge_list_ch_0 = int_edge_list_ch_0; -assign edge_list_ch_1 = int_edge_list_ch_1; -assign edge_list_ch_2 = int_edge_list_ch_2; -assign edge_list_ch_3 = int_edge_list_ch_3; -assign edge_list_ch_4 = int_edge_list_ch_4; -assign edge_list_ch_5 = int_edge_list_ch_5; -assign edge_list_ch_6 = int_edge_list_ch_6; -assign edge_list_ch_7 = int_edge_list_ch_7; -assign mat_B_ch_0 = int_mat_B_ch_0; -assign mat_B_ch_1 = int_mat_B_ch_1; -assign mat_B_ch_2 = int_mat_B_ch_2; -assign mat_B_ch_3 = int_mat_B_ch_3; -assign mat_C_ch_in_0 = int_mat_C_ch_in_0; -assign mat_C_ch_in_1 = int_mat_C_ch_in_1; -assign mat_C_ch_in_2 = int_mat_C_ch_in_2; -assign mat_C_ch_in_3 = int_mat_C_ch_in_3; -assign mat_C_ch_in_4 = int_mat_C_ch_in_4; -assign mat_C_ch_in_5 = int_mat_C_ch_in_5; -assign mat_C_ch_in_6 = int_mat_C_ch_in_6; -assign mat_C_ch_in_7 = int_mat_C_ch_in_7; -assign mat_C_ch_0 = int_mat_C_ch_0; -assign mat_C_ch_1 = int_mat_C_ch_1; -assign mat_C_ch_2 = int_mat_C_ch_2; -assign mat_C_ch_3 = int_mat_C_ch_3; -assign mat_C_ch_4 = int_mat_C_ch_4; -assign mat_C_ch_5 = int_mat_C_ch_5; -assign mat_C_ch_6 = int_mat_C_ch_6; -assign mat_C_ch_7 = int_mat_C_ch_7; -assign NUM_ITE = int_NUM_ITE; -assign NUM_A_LEN = int_NUM_A_LEN; -assign M = int_M; -assign K = int_K; -assign P_N = int_P_N; -assign alpha_u = int_alpha_u; -assign beta_u = int_beta_u; -// int_interrupt -always @(posedge ACLK) begin - if (ARESET) - int_interrupt <= 1'b0; - else if (ACLK_EN) begin - if (int_gie && (|int_isr)) - int_interrupt <= 1'b1; - else - int_interrupt <= 1'b0; - end -end - -// int_ap_start -always @(posedge ACLK) begin - if (ARESET) - int_ap_start <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0]) - int_ap_start <= 1'b1; - else if (ap_done & int_auto_restart) - int_ap_start <= 1'b1; // auto restart - else - int_ap_start <= 1'b0; // self clear - end -end - -// int_ap_done -always @(posedge ACLK) begin - if (ARESET) - int_ap_done <= 1'b0; - else if (ACLK_EN) begin - int_ap_done <= ap_done; - end -end - -// int_task_ap_done -always @(posedge ACLK) begin - if (ARESET) - int_task_ap_done <= 1'b0; - else if (ACLK_EN) begin - if (task_ap_done) - int_task_ap_done <= 1'b1; - else if (ar_hs && raddr == ADDR_AP_CTRL) - int_task_ap_done <= 1'b0; // clear on read - end -end - -// int_ap_idle -always @(posedge ACLK) begin - if (ARESET) - int_ap_idle <= 1'b0; - else if (ACLK_EN) begin - int_ap_idle <= ap_idle; - end -end - -// int_ap_ready -always @(posedge ACLK) begin - if (ARESET) - int_ap_ready <= 1'b0; - else if (ACLK_EN) begin - if (task_ap_ready) - int_ap_ready <= 1'b1; - else if (ar_hs && raddr == ADDR_AP_CTRL) - int_ap_ready <= 1'b0; - end -end - -// int_auto_restart -always @(posedge ACLK) begin - if (ARESET) - int_auto_restart <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0]) - int_auto_restart <= WDATA[7]; - end -end - -// auto_restart_status -always @(posedge ACLK) begin - if (ARESET) - auto_restart_status <= 1'b0; - else if (ACLK_EN) begin - if (int_auto_restart) - auto_restart_status <= 1'b1; - else if (ap_idle) - auto_restart_status <= 1'b0; - end -end - -// int_gie -always @(posedge ACLK) begin - if (ARESET) - int_gie <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_GIE && WSTRB[0]) - int_gie <= WDATA[0]; - end -end - -// int_ier -always @(posedge ACLK) begin - if (ARESET) - int_ier <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IER && WSTRB[0]) - int_ier <= WDATA[0]; - end -end - -// int_isr -always @(posedge ACLK) begin - if (ARESET) - int_isr <= 1'b0; - else if (ACLK_EN) begin - if (int_ier & ap_done) - int_isr <= 1'b1; - else if (w_hs && waddr == ADDR_ISR && WSTRB[0]) - int_isr <= int_isr ^ WDATA[0]; // toggle on write - end -end - -// int_edge_list_ptr[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ptr[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_PTR_DATA_0) - int_edge_list_ptr[31:0] <= (WDATA[31:0] & wmask) | (int_edge_list_ptr[31:0] & ~wmask); - end -end - -// int_edge_list_ptr[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ptr[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_PTR_DATA_1) - int_edge_list_ptr[63:32] <= (WDATA[31:0] & wmask) | (int_edge_list_ptr[63:32] & ~wmask); - end -end - -// int_edge_list_ch_0[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_0[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_0_DATA_0) - int_edge_list_ch_0[31:0] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_0[31:0] & ~wmask); - end -end - -// int_edge_list_ch_0[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_0[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_0_DATA_1) - int_edge_list_ch_0[63:32] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_0[63:32] & ~wmask); - end -end - -// int_edge_list_ch_1[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_1[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_1_DATA_0) - int_edge_list_ch_1[31:0] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_1[31:0] & ~wmask); - end -end - -// int_edge_list_ch_1[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_1[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_1_DATA_1) - int_edge_list_ch_1[63:32] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_1[63:32] & ~wmask); - end -end - -// int_edge_list_ch_2[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_2[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_2_DATA_0) - int_edge_list_ch_2[31:0] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_2[31:0] & ~wmask); - end -end - -// int_edge_list_ch_2[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_2[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_2_DATA_1) - int_edge_list_ch_2[63:32] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_2[63:32] & ~wmask); - end -end - -// int_edge_list_ch_3[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_3[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_3_DATA_0) - int_edge_list_ch_3[31:0] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_3[31:0] & ~wmask); - end -end - -// int_edge_list_ch_3[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_3[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_3_DATA_1) - int_edge_list_ch_3[63:32] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_3[63:32] & ~wmask); - end -end - -// int_edge_list_ch_4[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_4[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_4_DATA_0) - int_edge_list_ch_4[31:0] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_4[31:0] & ~wmask); - end -end - -// int_edge_list_ch_4[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_4[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_4_DATA_1) - int_edge_list_ch_4[63:32] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_4[63:32] & ~wmask); - end -end - -// int_edge_list_ch_5[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_5[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_5_DATA_0) - int_edge_list_ch_5[31:0] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_5[31:0] & ~wmask); - end -end - -// int_edge_list_ch_5[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_5[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_5_DATA_1) - int_edge_list_ch_5[63:32] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_5[63:32] & ~wmask); - end -end - -// int_edge_list_ch_6[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_6[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_6_DATA_0) - int_edge_list_ch_6[31:0] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_6[31:0] & ~wmask); - end -end - -// int_edge_list_ch_6[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_6[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_6_DATA_1) - int_edge_list_ch_6[63:32] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_6[63:32] & ~wmask); - end -end - -// int_edge_list_ch_7[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_7[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_7_DATA_0) - int_edge_list_ch_7[31:0] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_7[31:0] & ~wmask); - end -end - -// int_edge_list_ch_7[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_edge_list_ch_7[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_EDGE_LIST_CH_7_DATA_1) - int_edge_list_ch_7[63:32] <= (WDATA[31:0] & wmask) | (int_edge_list_ch_7[63:32] & ~wmask); - end -end - -// int_mat_B_ch_0[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_B_ch_0[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_B_CH_0_DATA_0) - int_mat_B_ch_0[31:0] <= (WDATA[31:0] & wmask) | (int_mat_B_ch_0[31:0] & ~wmask); - end -end - -// int_mat_B_ch_0[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_B_ch_0[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_B_CH_0_DATA_1) - int_mat_B_ch_0[63:32] <= (WDATA[31:0] & wmask) | (int_mat_B_ch_0[63:32] & ~wmask); - end -end - -// int_mat_B_ch_1[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_B_ch_1[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_B_CH_1_DATA_0) - int_mat_B_ch_1[31:0] <= (WDATA[31:0] & wmask) | (int_mat_B_ch_1[31:0] & ~wmask); - end -end - -// int_mat_B_ch_1[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_B_ch_1[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_B_CH_1_DATA_1) - int_mat_B_ch_1[63:32] <= (WDATA[31:0] & wmask) | (int_mat_B_ch_1[63:32] & ~wmask); - end -end - -// int_mat_B_ch_2[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_B_ch_2[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_B_CH_2_DATA_0) - int_mat_B_ch_2[31:0] <= (WDATA[31:0] & wmask) | (int_mat_B_ch_2[31:0] & ~wmask); - end -end - -// int_mat_B_ch_2[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_B_ch_2[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_B_CH_2_DATA_1) - int_mat_B_ch_2[63:32] <= (WDATA[31:0] & wmask) | (int_mat_B_ch_2[63:32] & ~wmask); - end -end - -// int_mat_B_ch_3[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_B_ch_3[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_B_CH_3_DATA_0) - int_mat_B_ch_3[31:0] <= (WDATA[31:0] & wmask) | (int_mat_B_ch_3[31:0] & ~wmask); - end -end - -// int_mat_B_ch_3[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_B_ch_3[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_B_CH_3_DATA_1) - int_mat_B_ch_3[63:32] <= (WDATA[31:0] & wmask) | (int_mat_B_ch_3[63:32] & ~wmask); - end -end - -// int_mat_C_ch_in_0[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_0[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_0_DATA_0) - int_mat_C_ch_in_0[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_0[31:0] & ~wmask); - end -end - -// int_mat_C_ch_in_0[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_0[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_0_DATA_1) - int_mat_C_ch_in_0[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_0[63:32] & ~wmask); - end -end - -// int_mat_C_ch_in_1[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_1[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_1_DATA_0) - int_mat_C_ch_in_1[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_1[31:0] & ~wmask); - end -end - -// int_mat_C_ch_in_1[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_1[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_1_DATA_1) - int_mat_C_ch_in_1[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_1[63:32] & ~wmask); - end -end - -// int_mat_C_ch_in_2[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_2[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_2_DATA_0) - int_mat_C_ch_in_2[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_2[31:0] & ~wmask); - end -end - -// int_mat_C_ch_in_2[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_2[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_2_DATA_1) - int_mat_C_ch_in_2[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_2[63:32] & ~wmask); - end -end - -// int_mat_C_ch_in_3[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_3[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_3_DATA_0) - int_mat_C_ch_in_3[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_3[31:0] & ~wmask); - end -end - -// int_mat_C_ch_in_3[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_3[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_3_DATA_1) - int_mat_C_ch_in_3[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_3[63:32] & ~wmask); - end -end - -// int_mat_C_ch_in_4[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_4[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_4_DATA_0) - int_mat_C_ch_in_4[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_4[31:0] & ~wmask); - end -end - -// int_mat_C_ch_in_4[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_4[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_4_DATA_1) - int_mat_C_ch_in_4[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_4[63:32] & ~wmask); - end -end - -// int_mat_C_ch_in_5[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_5[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_5_DATA_0) - int_mat_C_ch_in_5[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_5[31:0] & ~wmask); - end -end - -// int_mat_C_ch_in_5[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_5[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_5_DATA_1) - int_mat_C_ch_in_5[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_5[63:32] & ~wmask); - end -end - -// int_mat_C_ch_in_6[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_6[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_6_DATA_0) - int_mat_C_ch_in_6[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_6[31:0] & ~wmask); - end -end - -// int_mat_C_ch_in_6[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_6[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_6_DATA_1) - int_mat_C_ch_in_6[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_6[63:32] & ~wmask); - end -end - -// int_mat_C_ch_in_7[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_7[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_7_DATA_0) - int_mat_C_ch_in_7[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_7[31:0] & ~wmask); - end -end - -// int_mat_C_ch_in_7[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_in_7[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_IN_7_DATA_1) - int_mat_C_ch_in_7[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_in_7[63:32] & ~wmask); - end -end - -// int_mat_C_ch_0[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_0[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_0_DATA_0) - int_mat_C_ch_0[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_0[31:0] & ~wmask); - end -end - -// int_mat_C_ch_0[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_0[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_0_DATA_1) - int_mat_C_ch_0[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_0[63:32] & ~wmask); - end -end - -// int_mat_C_ch_1[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_1[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_1_DATA_0) - int_mat_C_ch_1[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_1[31:0] & ~wmask); - end -end - -// int_mat_C_ch_1[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_1[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_1_DATA_1) - int_mat_C_ch_1[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_1[63:32] & ~wmask); - end -end - -// int_mat_C_ch_2[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_2[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_2_DATA_0) - int_mat_C_ch_2[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_2[31:0] & ~wmask); - end -end - -// int_mat_C_ch_2[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_2[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_2_DATA_1) - int_mat_C_ch_2[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_2[63:32] & ~wmask); - end -end - -// int_mat_C_ch_3[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_3[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_3_DATA_0) - int_mat_C_ch_3[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_3[31:0] & ~wmask); - end -end - -// int_mat_C_ch_3[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_3[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_3_DATA_1) - int_mat_C_ch_3[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_3[63:32] & ~wmask); - end -end - -// int_mat_C_ch_4[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_4[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_4_DATA_0) - int_mat_C_ch_4[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_4[31:0] & ~wmask); - end -end - -// int_mat_C_ch_4[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_4[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_4_DATA_1) - int_mat_C_ch_4[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_4[63:32] & ~wmask); - end -end - -// int_mat_C_ch_5[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_5[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_5_DATA_0) - int_mat_C_ch_5[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_5[31:0] & ~wmask); - end -end - -// int_mat_C_ch_5[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_5[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_5_DATA_1) - int_mat_C_ch_5[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_5[63:32] & ~wmask); - end -end - -// int_mat_C_ch_6[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_6[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_6_DATA_0) - int_mat_C_ch_6[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_6[31:0] & ~wmask); - end -end - -// int_mat_C_ch_6[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_6[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_6_DATA_1) - int_mat_C_ch_6[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_6[63:32] & ~wmask); - end -end - -// int_mat_C_ch_7[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_7[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_7_DATA_0) - int_mat_C_ch_7[31:0] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_7[31:0] & ~wmask); - end -end - -// int_mat_C_ch_7[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_mat_C_ch_7[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_MAT_C_CH_7_DATA_1) - int_mat_C_ch_7[63:32] <= (WDATA[31:0] & wmask) | (int_mat_C_ch_7[63:32] & ~wmask); - end -end - -// int_NUM_ITE[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_NUM_ITE[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_NUM_ITE_DATA_0) - int_NUM_ITE[31:0] <= (WDATA[31:0] & wmask) | (int_NUM_ITE[31:0] & ~wmask); - end -end - -// int_NUM_A_LEN[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_NUM_A_LEN[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_NUM_A_LEN_DATA_0) - int_NUM_A_LEN[31:0] <= (WDATA[31:0] & wmask) | (int_NUM_A_LEN[31:0] & ~wmask); - end -end - -// int_M[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_M[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_M_DATA_0) - int_M[31:0] <= (WDATA[31:0] & wmask) | (int_M[31:0] & ~wmask); - end -end - -// int_K[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_K[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_K_DATA_0) - int_K[31:0] <= (WDATA[31:0] & wmask) | (int_K[31:0] & ~wmask); - end -end - -// int_P_N[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_P_N[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_P_N_DATA_0) - int_P_N[31:0] <= (WDATA[31:0] & wmask) | (int_P_N[31:0] & ~wmask); - end -end - -// int_alpha_u[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_alpha_u[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_ALPHA_U_DATA_0) - int_alpha_u[31:0] <= (WDATA[31:0] & wmask) | (int_alpha_u[31:0] & ~wmask); - end -end - -// int_beta_u[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_beta_u[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_BETA_U_DATA_0) - int_beta_u[31:0] <= (WDATA[31:0] & wmask) | (int_beta_u[31:0] & ~wmask); - end -end - -//synthesis translate_off -always @(posedge ACLK) begin - if (ACLK_EN) begin - if (int_gie & ~int_isr & int_ier & ap_done) - $display ("// Interrupt Monitor : interrupt for ap_done detected @ \"%0t\"", $time); - end -end -//synthesis translate_on - -//------------------------Memory logic------------------- - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/Sextans_fsm.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/Sextans_fsm.v deleted file mode 100644 index 2c79f074..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/Sextans_fsm.v +++ /dev/null @@ -1,4484 +0,0 @@ - - -module Sextans_fsm -( - ap_clk, - ap_rst_n, - ap_start, - ap_ready, - ap_done, - ap_idle, - FloatvAddFloatv_0__ap_start, - FloatvAddFloatv_1__ap_start, - FloatvAddFloatv_2__ap_start, - FloatvAddFloatv_3__ap_start, - FloatvAddFloatv_4__ap_start, - FloatvAddFloatv_5__ap_start, - FloatvAddFloatv_6__ap_start, - FloatvAddFloatv_7__ap_start, - FloatvMultConst_0__ap_start, - FloatvMultConst_0__ap_ready, - FloatvMultConst_0__ap_done, - FloatvMultConst_0__ap_idle, - FloatvMultConst_1__ap_start, - FloatvMultConst_1__ap_ready, - FloatvMultConst_1__ap_done, - FloatvMultConst_1__ap_idle, - FloatvMultConst_2__ap_start, - FloatvMultConst_2__ap_ready, - FloatvMultConst_2__ap_done, - FloatvMultConst_2__ap_idle, - FloatvMultConst_3__ap_start, - FloatvMultConst_3__ap_ready, - FloatvMultConst_3__ap_done, - FloatvMultConst_3__ap_idle, - FloatvMultConst_4__ap_start, - FloatvMultConst_4__ap_ready, - FloatvMultConst_4__ap_done, - FloatvMultConst_4__ap_idle, - FloatvMultConst_5__ap_start, - FloatvMultConst_5__ap_ready, - FloatvMultConst_5__ap_done, - FloatvMultConst_5__ap_idle, - FloatvMultConst_6__ap_start, - FloatvMultConst_6__ap_ready, - FloatvMultConst_6__ap_done, - FloatvMultConst_6__ap_idle, - FloatvMultConst_7__ap_start, - FloatvMultConst_7__ap_ready, - FloatvMultConst_7__ap_done, - FloatvMultConst_7__ap_idle, - FloatvMultConst_8__ap_start, - FloatvMultConst_8__ap_ready, - FloatvMultConst_8__ap_done, - FloatvMultConst_8__ap_idle, - FloatvMultConst_9__ap_start, - FloatvMultConst_9__ap_ready, - FloatvMultConst_9__ap_done, - FloatvMultConst_9__ap_idle, - FloatvMultConst_10__ap_start, - FloatvMultConst_10__ap_ready, - FloatvMultConst_10__ap_done, - FloatvMultConst_10__ap_idle, - FloatvMultConst_11__ap_start, - FloatvMultConst_11__ap_ready, - FloatvMultConst_11__ap_done, - FloatvMultConst_11__ap_idle, - FloatvMultConst_12__ap_start, - FloatvMultConst_12__ap_ready, - FloatvMultConst_12__ap_done, - FloatvMultConst_12__ap_idle, - FloatvMultConst_13__ap_start, - FloatvMultConst_13__ap_ready, - FloatvMultConst_13__ap_done, - FloatvMultConst_13__ap_idle, - FloatvMultConst_14__ap_start, - FloatvMultConst_14__ap_ready, - FloatvMultConst_14__ap_done, - FloatvMultConst_14__ap_idle, - FloatvMultConst_15__ap_start, - FloatvMultConst_15__ap_ready, - FloatvMultConst_15__ap_done, - FloatvMultConst_15__ap_idle, - Merger_0__ap_start, - Merger_1__ap_start, - Merger_2__ap_start, - Merger_3__ap_start, - Merger_4__ap_start, - Merger_5__ap_start, - Merger_6__ap_start, - Merger_7__ap_start, - PEG_Bmtx_0__ap_start, - PEG_Bmtx_0__ap_ready, - PEG_Bmtx_0__ap_done, - PEG_Bmtx_0__ap_idle, - PEG_Bmtx_1__ap_start, - PEG_Bmtx_1__ap_ready, - PEG_Bmtx_1__ap_done, - PEG_Bmtx_1__ap_idle, - PEG_Bmtx_2__ap_start, - PEG_Bmtx_2__ap_ready, - PEG_Bmtx_2__ap_done, - PEG_Bmtx_2__ap_idle, - PEG_Bmtx_3__ap_start, - PEG_Bmtx_3__ap_ready, - PEG_Bmtx_3__ap_done, - PEG_Bmtx_3__ap_idle, - PEG_Bmtx_4__ap_start, - PEG_Bmtx_4__ap_ready, - PEG_Bmtx_4__ap_done, - PEG_Bmtx_4__ap_idle, - PEG_Bmtx_5__ap_start, - PEG_Bmtx_5__ap_ready, - PEG_Bmtx_5__ap_done, - PEG_Bmtx_5__ap_idle, - PEG_Bmtx_6__ap_start, - PEG_Bmtx_6__ap_ready, - PEG_Bmtx_6__ap_done, - PEG_Bmtx_6__ap_idle, - PEG_Bmtx_7__ap_start, - PEG_Bmtx_7__ap_ready, - PEG_Bmtx_7__ap_done, - PEG_Bmtx_7__ap_idle, - PEG_Bmtx_8__ap_start, - PEG_Bmtx_8__ap_ready, - PEG_Bmtx_8__ap_done, - PEG_Bmtx_8__ap_idle, - PEG_Bmtx_9__ap_start, - PEG_Bmtx_9__ap_ready, - PEG_Bmtx_9__ap_done, - PEG_Bmtx_9__ap_idle, - PEG_Bmtx_10__ap_start, - PEG_Bmtx_10__ap_ready, - PEG_Bmtx_10__ap_done, - PEG_Bmtx_10__ap_idle, - PEG_Bmtx_11__ap_start, - PEG_Bmtx_11__ap_ready, - PEG_Bmtx_11__ap_done, - PEG_Bmtx_11__ap_idle, - PEG_Bmtx_12__ap_start, - PEG_Bmtx_12__ap_ready, - PEG_Bmtx_12__ap_done, - PEG_Bmtx_12__ap_idle, - PEG_Bmtx_13__ap_start, - PEG_Bmtx_13__ap_ready, - PEG_Bmtx_13__ap_done, - PEG_Bmtx_13__ap_idle, - PEG_Bmtx_14__ap_start, - PEG_Bmtx_14__ap_ready, - PEG_Bmtx_14__ap_done, - PEG_Bmtx_14__ap_idle, - PEG_Bmtx_15__ap_start, - PEG_Bmtx_15__ap_ready, - PEG_Bmtx_15__ap_done, - PEG_Bmtx_15__ap_idle, - PEG_Cmtx_0__ap_start, - PEG_Cmtx_0__ap_ready, - PEG_Cmtx_0__ap_done, - PEG_Cmtx_0__ap_idle, - PEG_Cmtx_1__ap_start, - PEG_Cmtx_1__ap_ready, - PEG_Cmtx_1__ap_done, - PEG_Cmtx_1__ap_idle, - PEG_Cmtx_2__ap_start, - PEG_Cmtx_2__ap_ready, - PEG_Cmtx_2__ap_done, - PEG_Cmtx_2__ap_idle, - PEG_Cmtx_3__ap_start, - PEG_Cmtx_3__ap_ready, - PEG_Cmtx_3__ap_done, - PEG_Cmtx_3__ap_idle, - PEG_Cmtx_4__ap_start, - PEG_Cmtx_4__ap_ready, - PEG_Cmtx_4__ap_done, - PEG_Cmtx_4__ap_idle, - PEG_Cmtx_5__ap_start, - PEG_Cmtx_5__ap_ready, - PEG_Cmtx_5__ap_done, - PEG_Cmtx_5__ap_idle, - PEG_Cmtx_6__ap_start, - PEG_Cmtx_6__ap_ready, - PEG_Cmtx_6__ap_done, - PEG_Cmtx_6__ap_idle, - PEG_Cmtx_7__ap_start, - PEG_Cmtx_7__ap_ready, - PEG_Cmtx_7__ap_done, - PEG_Cmtx_7__ap_idle, - PEG_Cmtx_8__ap_start, - PEG_Cmtx_8__ap_ready, - PEG_Cmtx_8__ap_done, - PEG_Cmtx_8__ap_idle, - PEG_Cmtx_9__ap_start, - PEG_Cmtx_9__ap_ready, - PEG_Cmtx_9__ap_done, - PEG_Cmtx_9__ap_idle, - PEG_Cmtx_10__ap_start, - PEG_Cmtx_10__ap_ready, - PEG_Cmtx_10__ap_done, - PEG_Cmtx_10__ap_idle, - PEG_Cmtx_11__ap_start, - PEG_Cmtx_11__ap_ready, - PEG_Cmtx_11__ap_done, - PEG_Cmtx_11__ap_idle, - PEG_Cmtx_12__ap_start, - PEG_Cmtx_12__ap_ready, - PEG_Cmtx_12__ap_done, - PEG_Cmtx_12__ap_idle, - PEG_Cmtx_13__ap_start, - PEG_Cmtx_13__ap_ready, - PEG_Cmtx_13__ap_done, - PEG_Cmtx_13__ap_idle, - PEG_Cmtx_14__ap_start, - PEG_Cmtx_14__ap_ready, - PEG_Cmtx_14__ap_done, - PEG_Cmtx_14__ap_idle, - PEG_Cmtx_15__ap_start, - PEG_Cmtx_15__ap_ready, - PEG_Cmtx_15__ap_done, - PEG_Cmtx_15__ap_idle, - Scatter_1_2_0__ap_start, - Scatter_1_2_1__ap_start, - Scatter_1_2_2__ap_start, - Scatter_1_2_3__ap_start, - Scatter_1_2_4__ap_start, - Scatter_1_2_5__ap_start, - Scatter_1_2_6__ap_start, - Scatter_1_2_7__ap_start, - black_hole_float_v16_0__ap_start, - black_hole_float_v16_1__ap_start, - black_hole_float_v16_2__ap_start, - black_hole_float_v16_3__ap_start, - black_hole_int_0__ap_start, - black_hole_int_1__ap_start, - read_A_0__ap_start, - read_A_0__ap_ready, - read_A_0__ap_done, - read_A_0__ap_idle, - read_A_1__ap_start, - read_A_1__ap_ready, - read_A_1__ap_done, - read_A_1__ap_idle, - read_A_2__ap_start, - read_A_2__ap_ready, - read_A_2__ap_done, - read_A_2__ap_idle, - read_A_3__ap_start, - read_A_3__ap_ready, - read_A_3__ap_done, - read_A_3__ap_idle, - read_A_4__ap_start, - read_A_4__ap_ready, - read_A_4__ap_done, - read_A_4__ap_idle, - read_A_5__ap_start, - read_A_5__ap_ready, - read_A_5__ap_done, - read_A_5__ap_idle, - read_A_6__ap_start, - read_A_6__ap_ready, - read_A_6__ap_done, - read_A_6__ap_idle, - read_A_7__ap_start, - read_A_7__ap_ready, - read_A_7__ap_done, - read_A_7__ap_idle, - read_B_0__ap_start, - read_B_0__ap_ready, - read_B_0__ap_done, - read_B_0__ap_idle, - read_B_1__ap_start, - read_B_1__ap_ready, - read_B_1__ap_done, - read_B_1__ap_idle, - read_B_2__ap_start, - read_B_2__ap_ready, - read_B_2__ap_done, - read_B_2__ap_idle, - read_B_3__ap_start, - read_B_3__ap_ready, - read_B_3__ap_done, - read_B_3__ap_idle, - read_C_0__ap_start, - read_C_0__ap_ready, - read_C_0__ap_done, - read_C_0__ap_idle, - read_C_1__ap_start, - read_C_1__ap_ready, - read_C_1__ap_done, - read_C_1__ap_idle, - read_C_2__ap_start, - read_C_2__ap_ready, - read_C_2__ap_done, - read_C_2__ap_idle, - read_C_3__ap_start, - read_C_3__ap_ready, - read_C_3__ap_done, - read_C_3__ap_idle, - read_C_4__ap_start, - read_C_4__ap_ready, - read_C_4__ap_done, - read_C_4__ap_idle, - read_C_5__ap_start, - read_C_5__ap_ready, - read_C_5__ap_done, - read_C_5__ap_idle, - read_C_6__ap_start, - read_C_6__ap_ready, - read_C_6__ap_done, - read_C_6__ap_idle, - read_C_7__ap_start, - read_C_7__ap_ready, - read_C_7__ap_done, - read_C_7__ap_idle, - read_edge_list_ptr_0__ap_start, - read_edge_list_ptr_0__ap_ready, - read_edge_list_ptr_0__ap_done, - read_edge_list_ptr_0__ap_idle, - write_C_0__ap_start, - write_C_0__ap_ready, - write_C_0__ap_done, - write_C_0__ap_idle, - write_C_1__ap_start, - write_C_1__ap_ready, - write_C_1__ap_done, - write_C_1__ap_idle, - write_C_2__ap_start, - write_C_2__ap_ready, - write_C_2__ap_done, - write_C_2__ap_idle, - write_C_3__ap_start, - write_C_3__ap_ready, - write_C_3__ap_done, - write_C_3__ap_idle, - write_C_4__ap_start, - write_C_4__ap_ready, - write_C_4__ap_done, - write_C_4__ap_idle, - write_C_5__ap_start, - write_C_5__ap_ready, - write_C_5__ap_done, - write_C_5__ap_idle, - write_C_6__ap_start, - write_C_6__ap_ready, - write_C_6__ap_done, - write_C_6__ap_idle, - write_C_7__ap_start, - write_C_7__ap_ready, - write_C_7__ap_done, - write_C_7__ap_idle -); - - (* RS_CLK *)input ap_clk; - (* RS_RST = "ff" *)input ap_rst_n; - (* RS_AP_CTRL = "Sextans.ap_start" *)input ap_start; - (* RS_AP_CTRL = "Sextans.ap_ready" *)output ap_ready; - (* RS_FF = "Sextans__ap_done" *)output ap_done; - (* RS_FF = "Sextans__ap_idle" *)output ap_idle; - (* RS_FF = "FloatvAddFloatv_0__ap_start" *)output FloatvAddFloatv_0__ap_start; - (* RS_FF = "FloatvAddFloatv_1__ap_start" *)output FloatvAddFloatv_1__ap_start; - (* RS_FF = "FloatvAddFloatv_2__ap_start" *)output FloatvAddFloatv_2__ap_start; - (* RS_FF = "FloatvAddFloatv_3__ap_start" *)output FloatvAddFloatv_3__ap_start; - (* RS_FF = "FloatvAddFloatv_4__ap_start" *)output FloatvAddFloatv_4__ap_start; - (* RS_FF = "FloatvAddFloatv_5__ap_start" *)output FloatvAddFloatv_5__ap_start; - (* RS_FF = "FloatvAddFloatv_6__ap_start" *)output FloatvAddFloatv_6__ap_start; - (* RS_FF = "FloatvAddFloatv_7__ap_start" *)output FloatvAddFloatv_7__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_0.ap_start" *)output FloatvMultConst_0__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_0.ap_ready" *)input FloatvMultConst_0__ap_ready; - (* RS_FF = "FloatvMultConst_0__ap_done" *)input FloatvMultConst_0__ap_done; - (* RS_FF = "FloatvMultConst_0__ap_idle" *)input FloatvMultConst_0__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_1.ap_start" *)output FloatvMultConst_1__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_1.ap_ready" *)input FloatvMultConst_1__ap_ready; - (* RS_FF = "FloatvMultConst_1__ap_done" *)input FloatvMultConst_1__ap_done; - (* RS_FF = "FloatvMultConst_1__ap_idle" *)input FloatvMultConst_1__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_2.ap_start" *)output FloatvMultConst_2__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_2.ap_ready" *)input FloatvMultConst_2__ap_ready; - (* RS_FF = "FloatvMultConst_2__ap_done" *)input FloatvMultConst_2__ap_done; - (* RS_FF = "FloatvMultConst_2__ap_idle" *)input FloatvMultConst_2__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_3.ap_start" *)output FloatvMultConst_3__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_3.ap_ready" *)input FloatvMultConst_3__ap_ready; - (* RS_FF = "FloatvMultConst_3__ap_done" *)input FloatvMultConst_3__ap_done; - (* RS_FF = "FloatvMultConst_3__ap_idle" *)input FloatvMultConst_3__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_4.ap_start" *)output FloatvMultConst_4__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_4.ap_ready" *)input FloatvMultConst_4__ap_ready; - (* RS_FF = "FloatvMultConst_4__ap_done" *)input FloatvMultConst_4__ap_done; - (* RS_FF = "FloatvMultConst_4__ap_idle" *)input FloatvMultConst_4__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_5.ap_start" *)output FloatvMultConst_5__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_5.ap_ready" *)input FloatvMultConst_5__ap_ready; - (* RS_FF = "FloatvMultConst_5__ap_done" *)input FloatvMultConst_5__ap_done; - (* RS_FF = "FloatvMultConst_5__ap_idle" *)input FloatvMultConst_5__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_6.ap_start" *)output FloatvMultConst_6__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_6.ap_ready" *)input FloatvMultConst_6__ap_ready; - (* RS_FF = "FloatvMultConst_6__ap_done" *)input FloatvMultConst_6__ap_done; - (* RS_FF = "FloatvMultConst_6__ap_idle" *)input FloatvMultConst_6__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_7.ap_start" *)output FloatvMultConst_7__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_7.ap_ready" *)input FloatvMultConst_7__ap_ready; - (* RS_FF = "FloatvMultConst_7__ap_done" *)input FloatvMultConst_7__ap_done; - (* RS_FF = "FloatvMultConst_7__ap_idle" *)input FloatvMultConst_7__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_8.ap_start" *)output FloatvMultConst_8__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_8.ap_ready" *)input FloatvMultConst_8__ap_ready; - (* RS_FF = "FloatvMultConst_8__ap_done" *)input FloatvMultConst_8__ap_done; - (* RS_FF = "FloatvMultConst_8__ap_idle" *)input FloatvMultConst_8__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_9.ap_start" *)output FloatvMultConst_9__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_9.ap_ready" *)input FloatvMultConst_9__ap_ready; - (* RS_FF = "FloatvMultConst_9__ap_done" *)input FloatvMultConst_9__ap_done; - (* RS_FF = "FloatvMultConst_9__ap_idle" *)input FloatvMultConst_9__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_10.ap_start" *)output FloatvMultConst_10__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_10.ap_ready" *)input FloatvMultConst_10__ap_ready; - (* RS_FF = "FloatvMultConst_10__ap_done" *)input FloatvMultConst_10__ap_done; - (* RS_FF = "FloatvMultConst_10__ap_idle" *)input FloatvMultConst_10__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_11.ap_start" *)output FloatvMultConst_11__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_11.ap_ready" *)input FloatvMultConst_11__ap_ready; - (* RS_FF = "FloatvMultConst_11__ap_done" *)input FloatvMultConst_11__ap_done; - (* RS_FF = "FloatvMultConst_11__ap_idle" *)input FloatvMultConst_11__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_12.ap_start" *)output FloatvMultConst_12__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_12.ap_ready" *)input FloatvMultConst_12__ap_ready; - (* RS_FF = "FloatvMultConst_12__ap_done" *)input FloatvMultConst_12__ap_done; - (* RS_FF = "FloatvMultConst_12__ap_idle" *)input FloatvMultConst_12__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_13.ap_start" *)output FloatvMultConst_13__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_13.ap_ready" *)input FloatvMultConst_13__ap_ready; - (* RS_FF = "FloatvMultConst_13__ap_done" *)input FloatvMultConst_13__ap_done; - (* RS_FF = "FloatvMultConst_13__ap_idle" *)input FloatvMultConst_13__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_14.ap_start" *)output FloatvMultConst_14__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_14.ap_ready" *)input FloatvMultConst_14__ap_ready; - (* RS_FF = "FloatvMultConst_14__ap_done" *)input FloatvMultConst_14__ap_done; - (* RS_FF = "FloatvMultConst_14__ap_idle" *)input FloatvMultConst_14__ap_idle; - (* RS_AP_CTRL = "FloatvMultConst_15.ap_start" *)output FloatvMultConst_15__ap_start; - (* RS_AP_CTRL = "FloatvMultConst_15.ap_ready" *)input FloatvMultConst_15__ap_ready; - (* RS_FF = "FloatvMultConst_15__ap_done" *)input FloatvMultConst_15__ap_done; - (* RS_FF = "FloatvMultConst_15__ap_idle" *)input FloatvMultConst_15__ap_idle; - (* RS_FF = "Merger_0__ap_start" *)output Merger_0__ap_start; - (* RS_FF = "Merger_1__ap_start" *)output Merger_1__ap_start; - (* RS_FF = "Merger_2__ap_start" *)output Merger_2__ap_start; - (* RS_FF = "Merger_3__ap_start" *)output Merger_3__ap_start; - (* RS_FF = "Merger_4__ap_start" *)output Merger_4__ap_start; - (* RS_FF = "Merger_5__ap_start" *)output Merger_5__ap_start; - (* RS_FF = "Merger_6__ap_start" *)output Merger_6__ap_start; - (* RS_FF = "Merger_7__ap_start" *)output Merger_7__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_0.ap_start" *)output PEG_Bmtx_0__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_0.ap_ready" *)input PEG_Bmtx_0__ap_ready; - (* RS_FF = "PEG_Bmtx_0__ap_done" *)input PEG_Bmtx_0__ap_done; - (* RS_FF = "PEG_Bmtx_0__ap_idle" *)input PEG_Bmtx_0__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_1.ap_start" *)output PEG_Bmtx_1__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_1.ap_ready" *)input PEG_Bmtx_1__ap_ready; - (* RS_FF = "PEG_Bmtx_1__ap_done" *)input PEG_Bmtx_1__ap_done; - (* RS_FF = "PEG_Bmtx_1__ap_idle" *)input PEG_Bmtx_1__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_2.ap_start" *)output PEG_Bmtx_2__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_2.ap_ready" *)input PEG_Bmtx_2__ap_ready; - (* RS_FF = "PEG_Bmtx_2__ap_done" *)input PEG_Bmtx_2__ap_done; - (* RS_FF = "PEG_Bmtx_2__ap_idle" *)input PEG_Bmtx_2__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_3.ap_start" *)output PEG_Bmtx_3__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_3.ap_ready" *)input PEG_Bmtx_3__ap_ready; - (* RS_FF = "PEG_Bmtx_3__ap_done" *)input PEG_Bmtx_3__ap_done; - (* RS_FF = "PEG_Bmtx_3__ap_idle" *)input PEG_Bmtx_3__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_4.ap_start" *)output PEG_Bmtx_4__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_4.ap_ready" *)input PEG_Bmtx_4__ap_ready; - (* RS_FF = "PEG_Bmtx_4__ap_done" *)input PEG_Bmtx_4__ap_done; - (* RS_FF = "PEG_Bmtx_4__ap_idle" *)input PEG_Bmtx_4__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_5.ap_start" *)output PEG_Bmtx_5__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_5.ap_ready" *)input PEG_Bmtx_5__ap_ready; - (* RS_FF = "PEG_Bmtx_5__ap_done" *)input PEG_Bmtx_5__ap_done; - (* RS_FF = "PEG_Bmtx_5__ap_idle" *)input PEG_Bmtx_5__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_6.ap_start" *)output PEG_Bmtx_6__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_6.ap_ready" *)input PEG_Bmtx_6__ap_ready; - (* RS_FF = "PEG_Bmtx_6__ap_done" *)input PEG_Bmtx_6__ap_done; - (* RS_FF = "PEG_Bmtx_6__ap_idle" *)input PEG_Bmtx_6__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_7.ap_start" *)output PEG_Bmtx_7__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_7.ap_ready" *)input PEG_Bmtx_7__ap_ready; - (* RS_FF = "PEG_Bmtx_7__ap_done" *)input PEG_Bmtx_7__ap_done; - (* RS_FF = "PEG_Bmtx_7__ap_idle" *)input PEG_Bmtx_7__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_8.ap_start" *)output PEG_Bmtx_8__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_8.ap_ready" *)input PEG_Bmtx_8__ap_ready; - (* RS_FF = "PEG_Bmtx_8__ap_done" *)input PEG_Bmtx_8__ap_done; - (* RS_FF = "PEG_Bmtx_8__ap_idle" *)input PEG_Bmtx_8__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_9.ap_start" *)output PEG_Bmtx_9__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_9.ap_ready" *)input PEG_Bmtx_9__ap_ready; - (* RS_FF = "PEG_Bmtx_9__ap_done" *)input PEG_Bmtx_9__ap_done; - (* RS_FF = "PEG_Bmtx_9__ap_idle" *)input PEG_Bmtx_9__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_10.ap_start" *)output PEG_Bmtx_10__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_10.ap_ready" *)input PEG_Bmtx_10__ap_ready; - (* RS_FF = "PEG_Bmtx_10__ap_done" *)input PEG_Bmtx_10__ap_done; - (* RS_FF = "PEG_Bmtx_10__ap_idle" *)input PEG_Bmtx_10__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_11.ap_start" *)output PEG_Bmtx_11__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_11.ap_ready" *)input PEG_Bmtx_11__ap_ready; - (* RS_FF = "PEG_Bmtx_11__ap_done" *)input PEG_Bmtx_11__ap_done; - (* RS_FF = "PEG_Bmtx_11__ap_idle" *)input PEG_Bmtx_11__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_12.ap_start" *)output PEG_Bmtx_12__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_12.ap_ready" *)input PEG_Bmtx_12__ap_ready; - (* RS_FF = "PEG_Bmtx_12__ap_done" *)input PEG_Bmtx_12__ap_done; - (* RS_FF = "PEG_Bmtx_12__ap_idle" *)input PEG_Bmtx_12__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_13.ap_start" *)output PEG_Bmtx_13__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_13.ap_ready" *)input PEG_Bmtx_13__ap_ready; - (* RS_FF = "PEG_Bmtx_13__ap_done" *)input PEG_Bmtx_13__ap_done; - (* RS_FF = "PEG_Bmtx_13__ap_idle" *)input PEG_Bmtx_13__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_14.ap_start" *)output PEG_Bmtx_14__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_14.ap_ready" *)input PEG_Bmtx_14__ap_ready; - (* RS_FF = "PEG_Bmtx_14__ap_done" *)input PEG_Bmtx_14__ap_done; - (* RS_FF = "PEG_Bmtx_14__ap_idle" *)input PEG_Bmtx_14__ap_idle; - (* RS_AP_CTRL = "PEG_Bmtx_15.ap_start" *)output PEG_Bmtx_15__ap_start; - (* RS_AP_CTRL = "PEG_Bmtx_15.ap_ready" *)input PEG_Bmtx_15__ap_ready; - (* RS_FF = "PEG_Bmtx_15__ap_done" *)input PEG_Bmtx_15__ap_done; - (* RS_FF = "PEG_Bmtx_15__ap_idle" *)input PEG_Bmtx_15__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_0.ap_start" *)output PEG_Cmtx_0__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_0.ap_ready" *)input PEG_Cmtx_0__ap_ready; - (* RS_FF = "PEG_Cmtx_0__ap_done" *)input PEG_Cmtx_0__ap_done; - (* RS_FF = "PEG_Cmtx_0__ap_idle" *)input PEG_Cmtx_0__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_1.ap_start" *)output PEG_Cmtx_1__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_1.ap_ready" *)input PEG_Cmtx_1__ap_ready; - (* RS_FF = "PEG_Cmtx_1__ap_done" *)input PEG_Cmtx_1__ap_done; - (* RS_FF = "PEG_Cmtx_1__ap_idle" *)input PEG_Cmtx_1__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_2.ap_start" *)output PEG_Cmtx_2__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_2.ap_ready" *)input PEG_Cmtx_2__ap_ready; - (* RS_FF = "PEG_Cmtx_2__ap_done" *)input PEG_Cmtx_2__ap_done; - (* RS_FF = "PEG_Cmtx_2__ap_idle" *)input PEG_Cmtx_2__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_3.ap_start" *)output PEG_Cmtx_3__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_3.ap_ready" *)input PEG_Cmtx_3__ap_ready; - (* RS_FF = "PEG_Cmtx_3__ap_done" *)input PEG_Cmtx_3__ap_done; - (* RS_FF = "PEG_Cmtx_3__ap_idle" *)input PEG_Cmtx_3__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_4.ap_start" *)output PEG_Cmtx_4__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_4.ap_ready" *)input PEG_Cmtx_4__ap_ready; - (* RS_FF = "PEG_Cmtx_4__ap_done" *)input PEG_Cmtx_4__ap_done; - (* RS_FF = "PEG_Cmtx_4__ap_idle" *)input PEG_Cmtx_4__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_5.ap_start" *)output PEG_Cmtx_5__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_5.ap_ready" *)input PEG_Cmtx_5__ap_ready; - (* RS_FF = "PEG_Cmtx_5__ap_done" *)input PEG_Cmtx_5__ap_done; - (* RS_FF = "PEG_Cmtx_5__ap_idle" *)input PEG_Cmtx_5__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_6.ap_start" *)output PEG_Cmtx_6__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_6.ap_ready" *)input PEG_Cmtx_6__ap_ready; - (* RS_FF = "PEG_Cmtx_6__ap_done" *)input PEG_Cmtx_6__ap_done; - (* RS_FF = "PEG_Cmtx_6__ap_idle" *)input PEG_Cmtx_6__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_7.ap_start" *)output PEG_Cmtx_7__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_7.ap_ready" *)input PEG_Cmtx_7__ap_ready; - (* RS_FF = "PEG_Cmtx_7__ap_done" *)input PEG_Cmtx_7__ap_done; - (* RS_FF = "PEG_Cmtx_7__ap_idle" *)input PEG_Cmtx_7__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_8.ap_start" *)output PEG_Cmtx_8__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_8.ap_ready" *)input PEG_Cmtx_8__ap_ready; - (* RS_FF = "PEG_Cmtx_8__ap_done" *)input PEG_Cmtx_8__ap_done; - (* RS_FF = "PEG_Cmtx_8__ap_idle" *)input PEG_Cmtx_8__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_9.ap_start" *)output PEG_Cmtx_9__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_9.ap_ready" *)input PEG_Cmtx_9__ap_ready; - (* RS_FF = "PEG_Cmtx_9__ap_done" *)input PEG_Cmtx_9__ap_done; - (* RS_FF = "PEG_Cmtx_9__ap_idle" *)input PEG_Cmtx_9__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_10.ap_start" *)output PEG_Cmtx_10__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_10.ap_ready" *)input PEG_Cmtx_10__ap_ready; - (* RS_FF = "PEG_Cmtx_10__ap_done" *)input PEG_Cmtx_10__ap_done; - (* RS_FF = "PEG_Cmtx_10__ap_idle" *)input PEG_Cmtx_10__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_11.ap_start" *)output PEG_Cmtx_11__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_11.ap_ready" *)input PEG_Cmtx_11__ap_ready; - (* RS_FF = "PEG_Cmtx_11__ap_done" *)input PEG_Cmtx_11__ap_done; - (* RS_FF = "PEG_Cmtx_11__ap_idle" *)input PEG_Cmtx_11__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_12.ap_start" *)output PEG_Cmtx_12__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_12.ap_ready" *)input PEG_Cmtx_12__ap_ready; - (* RS_FF = "PEG_Cmtx_12__ap_done" *)input PEG_Cmtx_12__ap_done; - (* RS_FF = "PEG_Cmtx_12__ap_idle" *)input PEG_Cmtx_12__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_13.ap_start" *)output PEG_Cmtx_13__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_13.ap_ready" *)input PEG_Cmtx_13__ap_ready; - (* RS_FF = "PEG_Cmtx_13__ap_done" *)input PEG_Cmtx_13__ap_done; - (* RS_FF = "PEG_Cmtx_13__ap_idle" *)input PEG_Cmtx_13__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_14.ap_start" *)output PEG_Cmtx_14__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_14.ap_ready" *)input PEG_Cmtx_14__ap_ready; - (* RS_FF = "PEG_Cmtx_14__ap_done" *)input PEG_Cmtx_14__ap_done; - (* RS_FF = "PEG_Cmtx_14__ap_idle" *)input PEG_Cmtx_14__ap_idle; - (* RS_AP_CTRL = "PEG_Cmtx_15.ap_start" *)output PEG_Cmtx_15__ap_start; - (* RS_AP_CTRL = "PEG_Cmtx_15.ap_ready" *)input PEG_Cmtx_15__ap_ready; - (* RS_FF = "PEG_Cmtx_15__ap_done" *)input PEG_Cmtx_15__ap_done; - (* RS_FF = "PEG_Cmtx_15__ap_idle" *)input PEG_Cmtx_15__ap_idle; - (* RS_FF = "Scatter_1_2_0__ap_start" *)output Scatter_1_2_0__ap_start; - (* RS_FF = "Scatter_1_2_1__ap_start" *)output Scatter_1_2_1__ap_start; - (* RS_FF = "Scatter_1_2_2__ap_start" *)output Scatter_1_2_2__ap_start; - (* RS_FF = "Scatter_1_2_3__ap_start" *)output Scatter_1_2_3__ap_start; - (* RS_FF = "Scatter_1_2_4__ap_start" *)output Scatter_1_2_4__ap_start; - (* RS_FF = "Scatter_1_2_5__ap_start" *)output Scatter_1_2_5__ap_start; - (* RS_FF = "Scatter_1_2_6__ap_start" *)output Scatter_1_2_6__ap_start; - (* RS_FF = "Scatter_1_2_7__ap_start" *)output Scatter_1_2_7__ap_start; - (* RS_FF = "black_hole_float_v16_0__ap_start" *)output black_hole_float_v16_0__ap_start; - (* RS_FF = "black_hole_float_v16_1__ap_start" *)output black_hole_float_v16_1__ap_start; - (* RS_FF = "black_hole_float_v16_2__ap_start" *)output black_hole_float_v16_2__ap_start; - (* RS_FF = "black_hole_float_v16_3__ap_start" *)output black_hole_float_v16_3__ap_start; - (* RS_FF = "black_hole_int_0__ap_start" *)output black_hole_int_0__ap_start; - (* RS_FF = "black_hole_int_1__ap_start" *)output black_hole_int_1__ap_start; - (* RS_AP_CTRL = "read_A_0.ap_start" *)output read_A_0__ap_start; - (* RS_AP_CTRL = "read_A_0.ap_ready" *)input read_A_0__ap_ready; - (* RS_FF = "read_A_0__ap_done" *)input read_A_0__ap_done; - (* RS_FF = "read_A_0__ap_idle" *)input read_A_0__ap_idle; - (* RS_AP_CTRL = "read_A_1.ap_start" *)output read_A_1__ap_start; - (* RS_AP_CTRL = "read_A_1.ap_ready" *)input read_A_1__ap_ready; - (* RS_FF = "read_A_1__ap_done" *)input read_A_1__ap_done; - (* RS_FF = "read_A_1__ap_idle" *)input read_A_1__ap_idle; - (* RS_AP_CTRL = "read_A_2.ap_start" *)output read_A_2__ap_start; - (* RS_AP_CTRL = "read_A_2.ap_ready" *)input read_A_2__ap_ready; - (* RS_FF = "read_A_2__ap_done" *)input read_A_2__ap_done; - (* RS_FF = "read_A_2__ap_idle" *)input read_A_2__ap_idle; - (* RS_AP_CTRL = "read_A_3.ap_start" *)output read_A_3__ap_start; - (* RS_AP_CTRL = "read_A_3.ap_ready" *)input read_A_3__ap_ready; - (* RS_FF = "read_A_3__ap_done" *)input read_A_3__ap_done; - (* RS_FF = "read_A_3__ap_idle" *)input read_A_3__ap_idle; - (* RS_AP_CTRL = "read_A_4.ap_start" *)output read_A_4__ap_start; - (* RS_AP_CTRL = "read_A_4.ap_ready" *)input read_A_4__ap_ready; - (* RS_FF = "read_A_4__ap_done" *)input read_A_4__ap_done; - (* RS_FF = "read_A_4__ap_idle" *)input read_A_4__ap_idle; - (* RS_AP_CTRL = "read_A_5.ap_start" *)output read_A_5__ap_start; - (* RS_AP_CTRL = "read_A_5.ap_ready" *)input read_A_5__ap_ready; - (* RS_FF = "read_A_5__ap_done" *)input read_A_5__ap_done; - (* RS_FF = "read_A_5__ap_idle" *)input read_A_5__ap_idle; - (* RS_AP_CTRL = "read_A_6.ap_start" *)output read_A_6__ap_start; - (* RS_AP_CTRL = "read_A_6.ap_ready" *)input read_A_6__ap_ready; - (* RS_FF = "read_A_6__ap_done" *)input read_A_6__ap_done; - (* RS_FF = "read_A_6__ap_idle" *)input read_A_6__ap_idle; - (* RS_AP_CTRL = "read_A_7.ap_start" *)output read_A_7__ap_start; - (* RS_AP_CTRL = "read_A_7.ap_ready" *)input read_A_7__ap_ready; - (* RS_FF = "read_A_7__ap_done" *)input read_A_7__ap_done; - (* RS_FF = "read_A_7__ap_idle" *)input read_A_7__ap_idle; - (* RS_AP_CTRL = "read_B_0.ap_start" *)output read_B_0__ap_start; - (* RS_AP_CTRL = "read_B_0.ap_ready" *)input read_B_0__ap_ready; - (* RS_FF = "read_B_0__ap_done" *)input read_B_0__ap_done; - (* RS_FF = "read_B_0__ap_idle" *)input read_B_0__ap_idle; - (* RS_AP_CTRL = "read_B_1.ap_start" *)output read_B_1__ap_start; - (* RS_AP_CTRL = "read_B_1.ap_ready" *)input read_B_1__ap_ready; - (* RS_FF = "read_B_1__ap_done" *)input read_B_1__ap_done; - (* RS_FF = "read_B_1__ap_idle" *)input read_B_1__ap_idle; - (* RS_AP_CTRL = "read_B_2.ap_start" *)output read_B_2__ap_start; - (* RS_AP_CTRL = "read_B_2.ap_ready" *)input read_B_2__ap_ready; - (* RS_FF = "read_B_2__ap_done" *)input read_B_2__ap_done; - (* RS_FF = "read_B_2__ap_idle" *)input read_B_2__ap_idle; - (* RS_AP_CTRL = "read_B_3.ap_start" *)output read_B_3__ap_start; - (* RS_AP_CTRL = "read_B_3.ap_ready" *)input read_B_3__ap_ready; - (* RS_FF = "read_B_3__ap_done" *)input read_B_3__ap_done; - (* RS_FF = "read_B_3__ap_idle" *)input read_B_3__ap_idle; - (* RS_AP_CTRL = "read_C_0.ap_start" *)output read_C_0__ap_start; - (* RS_AP_CTRL = "read_C_0.ap_ready" *)input read_C_0__ap_ready; - (* RS_FF = "read_C_0__ap_done" *)input read_C_0__ap_done; - (* RS_FF = "read_C_0__ap_idle" *)input read_C_0__ap_idle; - (* RS_AP_CTRL = "read_C_1.ap_start" *)output read_C_1__ap_start; - (* RS_AP_CTRL = "read_C_1.ap_ready" *)input read_C_1__ap_ready; - (* RS_FF = "read_C_1__ap_done" *)input read_C_1__ap_done; - (* RS_FF = "read_C_1__ap_idle" *)input read_C_1__ap_idle; - (* RS_AP_CTRL = "read_C_2.ap_start" *)output read_C_2__ap_start; - (* RS_AP_CTRL = "read_C_2.ap_ready" *)input read_C_2__ap_ready; - (* RS_FF = "read_C_2__ap_done" *)input read_C_2__ap_done; - (* RS_FF = "read_C_2__ap_idle" *)input read_C_2__ap_idle; - (* RS_AP_CTRL = "read_C_3.ap_start" *)output read_C_3__ap_start; - (* RS_AP_CTRL = "read_C_3.ap_ready" *)input read_C_3__ap_ready; - (* RS_FF = "read_C_3__ap_done" *)input read_C_3__ap_done; - (* RS_FF = "read_C_3__ap_idle" *)input read_C_3__ap_idle; - (* RS_AP_CTRL = "read_C_4.ap_start" *)output read_C_4__ap_start; - (* RS_AP_CTRL = "read_C_4.ap_ready" *)input read_C_4__ap_ready; - (* RS_FF = "read_C_4__ap_done" *)input read_C_4__ap_done; - (* RS_FF = "read_C_4__ap_idle" *)input read_C_4__ap_idle; - (* RS_AP_CTRL = "read_C_5.ap_start" *)output read_C_5__ap_start; - (* RS_AP_CTRL = "read_C_5.ap_ready" *)input read_C_5__ap_ready; - (* RS_FF = "read_C_5__ap_done" *)input read_C_5__ap_done; - (* RS_FF = "read_C_5__ap_idle" *)input read_C_5__ap_idle; - (* RS_AP_CTRL = "read_C_6.ap_start" *)output read_C_6__ap_start; - (* RS_AP_CTRL = "read_C_6.ap_ready" *)input read_C_6__ap_ready; - (* RS_FF = "read_C_6__ap_done" *)input read_C_6__ap_done; - (* RS_FF = "read_C_6__ap_idle" *)input read_C_6__ap_idle; - (* RS_AP_CTRL = "read_C_7.ap_start" *)output read_C_7__ap_start; - (* RS_AP_CTRL = "read_C_7.ap_ready" *)input read_C_7__ap_ready; - (* RS_FF = "read_C_7__ap_done" *)input read_C_7__ap_done; - (* RS_FF = "read_C_7__ap_idle" *)input read_C_7__ap_idle; - (* RS_AP_CTRL = "read_edge_list_ptr_0.ap_start" *)output read_edge_list_ptr_0__ap_start; - (* RS_AP_CTRL = "read_edge_list_ptr_0.ap_ready" *)input read_edge_list_ptr_0__ap_ready; - (* RS_FF = "read_edge_list_ptr_0__ap_done" *)input read_edge_list_ptr_0__ap_done; - (* RS_FF = "read_edge_list_ptr_0__ap_idle" *)input read_edge_list_ptr_0__ap_idle; - (* RS_AP_CTRL = "write_C_0.ap_start" *)output write_C_0__ap_start; - (* RS_AP_CTRL = "write_C_0.ap_ready" *)input write_C_0__ap_ready; - (* RS_FF = "write_C_0__ap_done" *)input write_C_0__ap_done; - (* RS_FF = "write_C_0__ap_idle" *)input write_C_0__ap_idle; - (* RS_AP_CTRL = "write_C_1.ap_start" *)output write_C_1__ap_start; - (* RS_AP_CTRL = "write_C_1.ap_ready" *)input write_C_1__ap_ready; - (* RS_FF = "write_C_1__ap_done" *)input write_C_1__ap_done; - (* RS_FF = "write_C_1__ap_idle" *)input write_C_1__ap_idle; - (* RS_AP_CTRL = "write_C_2.ap_start" *)output write_C_2__ap_start; - (* RS_AP_CTRL = "write_C_2.ap_ready" *)input write_C_2__ap_ready; - (* RS_FF = "write_C_2__ap_done" *)input write_C_2__ap_done; - (* RS_FF = "write_C_2__ap_idle" *)input write_C_2__ap_idle; - (* RS_AP_CTRL = "write_C_3.ap_start" *)output write_C_3__ap_start; - (* RS_AP_CTRL = "write_C_3.ap_ready" *)input write_C_3__ap_ready; - (* RS_FF = "write_C_3__ap_done" *)input write_C_3__ap_done; - (* RS_FF = "write_C_3__ap_idle" *)input write_C_3__ap_idle; - (* RS_AP_CTRL = "write_C_4.ap_start" *)output write_C_4__ap_start; - (* RS_AP_CTRL = "write_C_4.ap_ready" *)input write_C_4__ap_ready; - (* RS_FF = "write_C_4__ap_done" *)input write_C_4__ap_done; - (* RS_FF = "write_C_4__ap_idle" *)input write_C_4__ap_idle; - (* RS_AP_CTRL = "write_C_5.ap_start" *)output write_C_5__ap_start; - (* RS_AP_CTRL = "write_C_5.ap_ready" *)input write_C_5__ap_ready; - (* RS_FF = "write_C_5__ap_done" *)input write_C_5__ap_done; - (* RS_FF = "write_C_5__ap_idle" *)input write_C_5__ap_idle; - (* RS_AP_CTRL = "write_C_6.ap_start" *)output write_C_6__ap_start; - (* RS_AP_CTRL = "write_C_6.ap_ready" *)input write_C_6__ap_ready; - (* RS_FF = "write_C_6__ap_done" *)input write_C_6__ap_done; - (* RS_FF = "write_C_6__ap_idle" *)input write_C_6__ap_idle; - (* RS_AP_CTRL = "write_C_7.ap_start" *)output write_C_7__ap_start; - (* RS_AP_CTRL = "write_C_7.ap_ready" *)input write_C_7__ap_ready; - (* RS_FF = "write_C_7__ap_done" *)input write_C_7__ap_done; - (* RS_FF = "write_C_7__ap_idle" *)input write_C_7__ap_idle; - wire FloatvAddFloatv_0__ap_start_global__q0; - reg FloatvAddFloatv_0__ap_start; - wire FloatvAddFloatv_1__ap_start_global__q0; - reg FloatvAddFloatv_1__ap_start; - wire FloatvAddFloatv_2__ap_start_global__q0; - reg FloatvAddFloatv_2__ap_start; - wire FloatvAddFloatv_3__ap_start_global__q0; - reg FloatvAddFloatv_3__ap_start; - wire FloatvAddFloatv_4__ap_start_global__q0; - reg FloatvAddFloatv_4__ap_start; - wire FloatvAddFloatv_5__ap_start_global__q0; - reg FloatvAddFloatv_5__ap_start; - wire FloatvAddFloatv_6__ap_start_global__q0; - reg FloatvAddFloatv_6__ap_start; - wire FloatvAddFloatv_7__ap_start_global__q0; - reg FloatvAddFloatv_7__ap_start; - wire FloatvMultConst_0__ap_start_global__q0; - wire FloatvMultConst_0__is_done__q0; - wire FloatvMultConst_0__ap_done_global__q0; - wire FloatvMultConst_0__ap_start; - wire FloatvMultConst_0__ap_ready; - wire FloatvMultConst_0__ap_done; - wire FloatvMultConst_0__ap_idle; - reg [1:0] FloatvMultConst_0__state; - wire FloatvMultConst_1__ap_start_global__q0; - wire FloatvMultConst_1__is_done__q0; - wire FloatvMultConst_1__ap_done_global__q0; - wire FloatvMultConst_1__ap_start; - wire FloatvMultConst_1__ap_ready; - wire FloatvMultConst_1__ap_done; - wire FloatvMultConst_1__ap_idle; - reg [1:0] FloatvMultConst_1__state; - wire FloatvMultConst_2__ap_start_global__q0; - wire FloatvMultConst_2__is_done__q0; - wire FloatvMultConst_2__ap_done_global__q0; - wire FloatvMultConst_2__ap_start; - wire FloatvMultConst_2__ap_ready; - wire FloatvMultConst_2__ap_done; - wire FloatvMultConst_2__ap_idle; - reg [1:0] FloatvMultConst_2__state; - wire FloatvMultConst_3__ap_start_global__q0; - wire FloatvMultConst_3__is_done__q0; - wire FloatvMultConst_3__ap_done_global__q0; - wire FloatvMultConst_3__ap_start; - wire FloatvMultConst_3__ap_ready; - wire FloatvMultConst_3__ap_done; - wire FloatvMultConst_3__ap_idle; - reg [1:0] FloatvMultConst_3__state; - wire FloatvMultConst_4__ap_start_global__q0; - wire FloatvMultConst_4__is_done__q0; - wire FloatvMultConst_4__ap_done_global__q0; - wire FloatvMultConst_4__ap_start; - wire FloatvMultConst_4__ap_ready; - wire FloatvMultConst_4__ap_done; - wire FloatvMultConst_4__ap_idle; - reg [1:0] FloatvMultConst_4__state; - wire FloatvMultConst_5__ap_start_global__q0; - wire FloatvMultConst_5__is_done__q0; - wire FloatvMultConst_5__ap_done_global__q0; - wire FloatvMultConst_5__ap_start; - wire FloatvMultConst_5__ap_ready; - wire FloatvMultConst_5__ap_done; - wire FloatvMultConst_5__ap_idle; - reg [1:0] FloatvMultConst_5__state; - wire FloatvMultConst_6__ap_start_global__q0; - wire FloatvMultConst_6__is_done__q0; - wire FloatvMultConst_6__ap_done_global__q0; - wire FloatvMultConst_6__ap_start; - wire FloatvMultConst_6__ap_ready; - wire FloatvMultConst_6__ap_done; - wire FloatvMultConst_6__ap_idle; - reg [1:0] FloatvMultConst_6__state; - wire FloatvMultConst_7__ap_start_global__q0; - wire FloatvMultConst_7__is_done__q0; - wire FloatvMultConst_7__ap_done_global__q0; - wire FloatvMultConst_7__ap_start; - wire FloatvMultConst_7__ap_ready; - wire FloatvMultConst_7__ap_done; - wire FloatvMultConst_7__ap_idle; - reg [1:0] FloatvMultConst_7__state; - wire FloatvMultConst_8__ap_start_global__q0; - wire FloatvMultConst_8__is_done__q0; - wire FloatvMultConst_8__ap_done_global__q0; - wire FloatvMultConst_8__ap_start; - wire FloatvMultConst_8__ap_ready; - wire FloatvMultConst_8__ap_done; - wire FloatvMultConst_8__ap_idle; - reg [1:0] FloatvMultConst_8__state; - wire FloatvMultConst_9__ap_start_global__q0; - wire FloatvMultConst_9__is_done__q0; - wire FloatvMultConst_9__ap_done_global__q0; - wire FloatvMultConst_9__ap_start; - wire FloatvMultConst_9__ap_ready; - wire FloatvMultConst_9__ap_done; - wire FloatvMultConst_9__ap_idle; - reg [1:0] FloatvMultConst_9__state; - wire FloatvMultConst_10__ap_start_global__q0; - wire FloatvMultConst_10__is_done__q0; - wire FloatvMultConst_10__ap_done_global__q0; - wire FloatvMultConst_10__ap_start; - wire FloatvMultConst_10__ap_ready; - wire FloatvMultConst_10__ap_done; - wire FloatvMultConst_10__ap_idle; - reg [1:0] FloatvMultConst_10__state; - wire FloatvMultConst_11__ap_start_global__q0; - wire FloatvMultConst_11__is_done__q0; - wire FloatvMultConst_11__ap_done_global__q0; - wire FloatvMultConst_11__ap_start; - wire FloatvMultConst_11__ap_ready; - wire FloatvMultConst_11__ap_done; - wire FloatvMultConst_11__ap_idle; - reg [1:0] FloatvMultConst_11__state; - wire FloatvMultConst_12__ap_start_global__q0; - wire FloatvMultConst_12__is_done__q0; - wire FloatvMultConst_12__ap_done_global__q0; - wire FloatvMultConst_12__ap_start; - wire FloatvMultConst_12__ap_ready; - wire FloatvMultConst_12__ap_done; - wire FloatvMultConst_12__ap_idle; - reg [1:0] FloatvMultConst_12__state; - wire FloatvMultConst_13__ap_start_global__q0; - wire FloatvMultConst_13__is_done__q0; - wire FloatvMultConst_13__ap_done_global__q0; - wire FloatvMultConst_13__ap_start; - wire FloatvMultConst_13__ap_ready; - wire FloatvMultConst_13__ap_done; - wire FloatvMultConst_13__ap_idle; - reg [1:0] FloatvMultConst_13__state; - wire FloatvMultConst_14__ap_start_global__q0; - wire FloatvMultConst_14__is_done__q0; - wire FloatvMultConst_14__ap_done_global__q0; - wire FloatvMultConst_14__ap_start; - wire FloatvMultConst_14__ap_ready; - wire FloatvMultConst_14__ap_done; - wire FloatvMultConst_14__ap_idle; - reg [1:0] FloatvMultConst_14__state; - wire FloatvMultConst_15__ap_start_global__q0; - wire FloatvMultConst_15__is_done__q0; - wire FloatvMultConst_15__ap_done_global__q0; - wire FloatvMultConst_15__ap_start; - wire FloatvMultConst_15__ap_ready; - wire FloatvMultConst_15__ap_done; - wire FloatvMultConst_15__ap_idle; - reg [1:0] FloatvMultConst_15__state; - wire Merger_0__ap_start_global__q0; - reg Merger_0__ap_start; - wire Merger_1__ap_start_global__q0; - reg Merger_1__ap_start; - wire Merger_2__ap_start_global__q0; - reg Merger_2__ap_start; - wire Merger_3__ap_start_global__q0; - reg Merger_3__ap_start; - wire Merger_4__ap_start_global__q0; - reg Merger_4__ap_start; - wire Merger_5__ap_start_global__q0; - reg Merger_5__ap_start; - wire Merger_6__ap_start_global__q0; - reg Merger_6__ap_start; - wire Merger_7__ap_start_global__q0; - reg Merger_7__ap_start; - wire PEG_Bmtx_0__ap_start_global__q0; - wire PEG_Bmtx_0__is_done__q0; - wire PEG_Bmtx_0__ap_done_global__q0; - wire PEG_Bmtx_0__ap_start; - wire PEG_Bmtx_0__ap_ready; - wire PEG_Bmtx_0__ap_done; - wire PEG_Bmtx_0__ap_idle; - reg [1:0] PEG_Bmtx_0__state; - wire PEG_Bmtx_1__ap_start_global__q0; - wire PEG_Bmtx_1__is_done__q0; - wire PEG_Bmtx_1__ap_done_global__q0; - wire PEG_Bmtx_1__ap_start; - wire PEG_Bmtx_1__ap_ready; - wire PEG_Bmtx_1__ap_done; - wire PEG_Bmtx_1__ap_idle; - reg [1:0] PEG_Bmtx_1__state; - wire PEG_Bmtx_2__ap_start_global__q0; - wire PEG_Bmtx_2__is_done__q0; - wire PEG_Bmtx_2__ap_done_global__q0; - wire PEG_Bmtx_2__ap_start; - wire PEG_Bmtx_2__ap_ready; - wire PEG_Bmtx_2__ap_done; - wire PEG_Bmtx_2__ap_idle; - reg [1:0] PEG_Bmtx_2__state; - wire PEG_Bmtx_3__ap_start_global__q0; - wire PEG_Bmtx_3__is_done__q0; - wire PEG_Bmtx_3__ap_done_global__q0; - wire PEG_Bmtx_3__ap_start; - wire PEG_Bmtx_3__ap_ready; - wire PEG_Bmtx_3__ap_done; - wire PEG_Bmtx_3__ap_idle; - reg [1:0] PEG_Bmtx_3__state; - wire PEG_Bmtx_4__ap_start_global__q0; - wire PEG_Bmtx_4__is_done__q0; - wire PEG_Bmtx_4__ap_done_global__q0; - wire PEG_Bmtx_4__ap_start; - wire PEG_Bmtx_4__ap_ready; - wire PEG_Bmtx_4__ap_done; - wire PEG_Bmtx_4__ap_idle; - reg [1:0] PEG_Bmtx_4__state; - wire PEG_Bmtx_5__ap_start_global__q0; - wire PEG_Bmtx_5__is_done__q0; - wire PEG_Bmtx_5__ap_done_global__q0; - wire PEG_Bmtx_5__ap_start; - wire PEG_Bmtx_5__ap_ready; - wire PEG_Bmtx_5__ap_done; - wire PEG_Bmtx_5__ap_idle; - reg [1:0] PEG_Bmtx_5__state; - wire PEG_Bmtx_6__ap_start_global__q0; - wire PEG_Bmtx_6__is_done__q0; - wire PEG_Bmtx_6__ap_done_global__q0; - wire PEG_Bmtx_6__ap_start; - wire PEG_Bmtx_6__ap_ready; - wire PEG_Bmtx_6__ap_done; - wire PEG_Bmtx_6__ap_idle; - reg [1:0] PEG_Bmtx_6__state; - wire PEG_Bmtx_7__ap_start_global__q0; - wire PEG_Bmtx_7__is_done__q0; - wire PEG_Bmtx_7__ap_done_global__q0; - wire PEG_Bmtx_7__ap_start; - wire PEG_Bmtx_7__ap_ready; - wire PEG_Bmtx_7__ap_done; - wire PEG_Bmtx_7__ap_idle; - reg [1:0] PEG_Bmtx_7__state; - wire PEG_Bmtx_8__ap_start_global__q0; - wire PEG_Bmtx_8__is_done__q0; - wire PEG_Bmtx_8__ap_done_global__q0; - wire PEG_Bmtx_8__ap_start; - wire PEG_Bmtx_8__ap_ready; - wire PEG_Bmtx_8__ap_done; - wire PEG_Bmtx_8__ap_idle; - reg [1:0] PEG_Bmtx_8__state; - wire PEG_Bmtx_9__ap_start_global__q0; - wire PEG_Bmtx_9__is_done__q0; - wire PEG_Bmtx_9__ap_done_global__q0; - wire PEG_Bmtx_9__ap_start; - wire PEG_Bmtx_9__ap_ready; - wire PEG_Bmtx_9__ap_done; - wire PEG_Bmtx_9__ap_idle; - reg [1:0] PEG_Bmtx_9__state; - wire PEG_Bmtx_10__ap_start_global__q0; - wire PEG_Bmtx_10__is_done__q0; - wire PEG_Bmtx_10__ap_done_global__q0; - wire PEG_Bmtx_10__ap_start; - wire PEG_Bmtx_10__ap_ready; - wire PEG_Bmtx_10__ap_done; - wire PEG_Bmtx_10__ap_idle; - reg [1:0] PEG_Bmtx_10__state; - wire PEG_Bmtx_11__ap_start_global__q0; - wire PEG_Bmtx_11__is_done__q0; - wire PEG_Bmtx_11__ap_done_global__q0; - wire PEG_Bmtx_11__ap_start; - wire PEG_Bmtx_11__ap_ready; - wire PEG_Bmtx_11__ap_done; - wire PEG_Bmtx_11__ap_idle; - reg [1:0] PEG_Bmtx_11__state; - wire PEG_Bmtx_12__ap_start_global__q0; - wire PEG_Bmtx_12__is_done__q0; - wire PEG_Bmtx_12__ap_done_global__q0; - wire PEG_Bmtx_12__ap_start; - wire PEG_Bmtx_12__ap_ready; - wire PEG_Bmtx_12__ap_done; - wire PEG_Bmtx_12__ap_idle; - reg [1:0] PEG_Bmtx_12__state; - wire PEG_Bmtx_13__ap_start_global__q0; - wire PEG_Bmtx_13__is_done__q0; - wire PEG_Bmtx_13__ap_done_global__q0; - wire PEG_Bmtx_13__ap_start; - wire PEG_Bmtx_13__ap_ready; - wire PEG_Bmtx_13__ap_done; - wire PEG_Bmtx_13__ap_idle; - reg [1:0] PEG_Bmtx_13__state; - wire PEG_Bmtx_14__ap_start_global__q0; - wire PEG_Bmtx_14__is_done__q0; - wire PEG_Bmtx_14__ap_done_global__q0; - wire PEG_Bmtx_14__ap_start; - wire PEG_Bmtx_14__ap_ready; - wire PEG_Bmtx_14__ap_done; - wire PEG_Bmtx_14__ap_idle; - reg [1:0] PEG_Bmtx_14__state; - wire PEG_Bmtx_15__ap_start_global__q0; - wire PEG_Bmtx_15__is_done__q0; - wire PEG_Bmtx_15__ap_done_global__q0; - wire PEG_Bmtx_15__ap_start; - wire PEG_Bmtx_15__ap_ready; - wire PEG_Bmtx_15__ap_done; - wire PEG_Bmtx_15__ap_idle; - reg [1:0] PEG_Bmtx_15__state; - wire PEG_Cmtx_0__ap_start_global__q0; - wire PEG_Cmtx_0__is_done__q0; - wire PEG_Cmtx_0__ap_done_global__q0; - wire PEG_Cmtx_0__ap_start; - wire PEG_Cmtx_0__ap_ready; - wire PEG_Cmtx_0__ap_done; - wire PEG_Cmtx_0__ap_idle; - reg [1:0] PEG_Cmtx_0__state; - wire PEG_Cmtx_1__ap_start_global__q0; - wire PEG_Cmtx_1__is_done__q0; - wire PEG_Cmtx_1__ap_done_global__q0; - wire PEG_Cmtx_1__ap_start; - wire PEG_Cmtx_1__ap_ready; - wire PEG_Cmtx_1__ap_done; - wire PEG_Cmtx_1__ap_idle; - reg [1:0] PEG_Cmtx_1__state; - wire PEG_Cmtx_2__ap_start_global__q0; - wire PEG_Cmtx_2__is_done__q0; - wire PEG_Cmtx_2__ap_done_global__q0; - wire PEG_Cmtx_2__ap_start; - wire PEG_Cmtx_2__ap_ready; - wire PEG_Cmtx_2__ap_done; - wire PEG_Cmtx_2__ap_idle; - reg [1:0] PEG_Cmtx_2__state; - wire PEG_Cmtx_3__ap_start_global__q0; - wire PEG_Cmtx_3__is_done__q0; - wire PEG_Cmtx_3__ap_done_global__q0; - wire PEG_Cmtx_3__ap_start; - wire PEG_Cmtx_3__ap_ready; - wire PEG_Cmtx_3__ap_done; - wire PEG_Cmtx_3__ap_idle; - reg [1:0] PEG_Cmtx_3__state; - wire PEG_Cmtx_4__ap_start_global__q0; - wire PEG_Cmtx_4__is_done__q0; - wire PEG_Cmtx_4__ap_done_global__q0; - wire PEG_Cmtx_4__ap_start; - wire PEG_Cmtx_4__ap_ready; - wire PEG_Cmtx_4__ap_done; - wire PEG_Cmtx_4__ap_idle; - reg [1:0] PEG_Cmtx_4__state; - wire PEG_Cmtx_5__ap_start_global__q0; - wire PEG_Cmtx_5__is_done__q0; - wire PEG_Cmtx_5__ap_done_global__q0; - wire PEG_Cmtx_5__ap_start; - wire PEG_Cmtx_5__ap_ready; - wire PEG_Cmtx_5__ap_done; - wire PEG_Cmtx_5__ap_idle; - reg [1:0] PEG_Cmtx_5__state; - wire PEG_Cmtx_6__ap_start_global__q0; - wire PEG_Cmtx_6__is_done__q0; - wire PEG_Cmtx_6__ap_done_global__q0; - wire PEG_Cmtx_6__ap_start; - wire PEG_Cmtx_6__ap_ready; - wire PEG_Cmtx_6__ap_done; - wire PEG_Cmtx_6__ap_idle; - reg [1:0] PEG_Cmtx_6__state; - wire PEG_Cmtx_7__ap_start_global__q0; - wire PEG_Cmtx_7__is_done__q0; - wire PEG_Cmtx_7__ap_done_global__q0; - wire PEG_Cmtx_7__ap_start; - wire PEG_Cmtx_7__ap_ready; - wire PEG_Cmtx_7__ap_done; - wire PEG_Cmtx_7__ap_idle; - reg [1:0] PEG_Cmtx_7__state; - wire PEG_Cmtx_8__ap_start_global__q0; - wire PEG_Cmtx_8__is_done__q0; - wire PEG_Cmtx_8__ap_done_global__q0; - wire PEG_Cmtx_8__ap_start; - wire PEG_Cmtx_8__ap_ready; - wire PEG_Cmtx_8__ap_done; - wire PEG_Cmtx_8__ap_idle; - reg [1:0] PEG_Cmtx_8__state; - wire PEG_Cmtx_9__ap_start_global__q0; - wire PEG_Cmtx_9__is_done__q0; - wire PEG_Cmtx_9__ap_done_global__q0; - wire PEG_Cmtx_9__ap_start; - wire PEG_Cmtx_9__ap_ready; - wire PEG_Cmtx_9__ap_done; - wire PEG_Cmtx_9__ap_idle; - reg [1:0] PEG_Cmtx_9__state; - wire PEG_Cmtx_10__ap_start_global__q0; - wire PEG_Cmtx_10__is_done__q0; - wire PEG_Cmtx_10__ap_done_global__q0; - wire PEG_Cmtx_10__ap_start; - wire PEG_Cmtx_10__ap_ready; - wire PEG_Cmtx_10__ap_done; - wire PEG_Cmtx_10__ap_idle; - reg [1:0] PEG_Cmtx_10__state; - wire PEG_Cmtx_11__ap_start_global__q0; - wire PEG_Cmtx_11__is_done__q0; - wire PEG_Cmtx_11__ap_done_global__q0; - wire PEG_Cmtx_11__ap_start; - wire PEG_Cmtx_11__ap_ready; - wire PEG_Cmtx_11__ap_done; - wire PEG_Cmtx_11__ap_idle; - reg [1:0] PEG_Cmtx_11__state; - wire PEG_Cmtx_12__ap_start_global__q0; - wire PEG_Cmtx_12__is_done__q0; - wire PEG_Cmtx_12__ap_done_global__q0; - wire PEG_Cmtx_12__ap_start; - wire PEG_Cmtx_12__ap_ready; - wire PEG_Cmtx_12__ap_done; - wire PEG_Cmtx_12__ap_idle; - reg [1:0] PEG_Cmtx_12__state; - wire PEG_Cmtx_13__ap_start_global__q0; - wire PEG_Cmtx_13__is_done__q0; - wire PEG_Cmtx_13__ap_done_global__q0; - wire PEG_Cmtx_13__ap_start; - wire PEG_Cmtx_13__ap_ready; - wire PEG_Cmtx_13__ap_done; - wire PEG_Cmtx_13__ap_idle; - reg [1:0] PEG_Cmtx_13__state; - wire PEG_Cmtx_14__ap_start_global__q0; - wire PEG_Cmtx_14__is_done__q0; - wire PEG_Cmtx_14__ap_done_global__q0; - wire PEG_Cmtx_14__ap_start; - wire PEG_Cmtx_14__ap_ready; - wire PEG_Cmtx_14__ap_done; - wire PEG_Cmtx_14__ap_idle; - reg [1:0] PEG_Cmtx_14__state; - wire PEG_Cmtx_15__ap_start_global__q0; - wire PEG_Cmtx_15__is_done__q0; - wire PEG_Cmtx_15__ap_done_global__q0; - wire PEG_Cmtx_15__ap_start; - wire PEG_Cmtx_15__ap_ready; - wire PEG_Cmtx_15__ap_done; - wire PEG_Cmtx_15__ap_idle; - reg [1:0] PEG_Cmtx_15__state; - wire Scatter_1_2_0__ap_start_global__q0; - reg Scatter_1_2_0__ap_start; - wire Scatter_1_2_1__ap_start_global__q0; - reg Scatter_1_2_1__ap_start; - wire Scatter_1_2_2__ap_start_global__q0; - reg Scatter_1_2_2__ap_start; - wire Scatter_1_2_3__ap_start_global__q0; - reg Scatter_1_2_3__ap_start; - wire Scatter_1_2_4__ap_start_global__q0; - reg Scatter_1_2_4__ap_start; - wire Scatter_1_2_5__ap_start_global__q0; - reg Scatter_1_2_5__ap_start; - wire Scatter_1_2_6__ap_start_global__q0; - reg Scatter_1_2_6__ap_start; - wire Scatter_1_2_7__ap_start_global__q0; - reg Scatter_1_2_7__ap_start; - wire black_hole_float_v16_0__ap_start_global__q0; - reg black_hole_float_v16_0__ap_start; - wire black_hole_float_v16_1__ap_start_global__q0; - reg black_hole_float_v16_1__ap_start; - wire black_hole_float_v16_2__ap_start_global__q0; - reg black_hole_float_v16_2__ap_start; - wire black_hole_float_v16_3__ap_start_global__q0; - reg black_hole_float_v16_3__ap_start; - wire black_hole_int_0__ap_start_global__q0; - reg black_hole_int_0__ap_start; - wire black_hole_int_1__ap_start_global__q0; - reg black_hole_int_1__ap_start; - wire read_A_0__ap_start_global__q0; - wire read_A_0__is_done__q0; - wire read_A_0__ap_done_global__q0; - wire read_A_0__ap_start; - wire read_A_0__ap_ready; - wire read_A_0__ap_done; - wire read_A_0__ap_idle; - reg [1:0] read_A_0__state; - wire read_A_1__ap_start_global__q0; - wire read_A_1__is_done__q0; - wire read_A_1__ap_done_global__q0; - wire read_A_1__ap_start; - wire read_A_1__ap_ready; - wire read_A_1__ap_done; - wire read_A_1__ap_idle; - reg [1:0] read_A_1__state; - wire read_A_2__ap_start_global__q0; - wire read_A_2__is_done__q0; - wire read_A_2__ap_done_global__q0; - wire read_A_2__ap_start; - wire read_A_2__ap_ready; - wire read_A_2__ap_done; - wire read_A_2__ap_idle; - reg [1:0] read_A_2__state; - wire read_A_3__ap_start_global__q0; - wire read_A_3__is_done__q0; - wire read_A_3__ap_done_global__q0; - wire read_A_3__ap_start; - wire read_A_3__ap_ready; - wire read_A_3__ap_done; - wire read_A_3__ap_idle; - reg [1:0] read_A_3__state; - wire read_A_4__ap_start_global__q0; - wire read_A_4__is_done__q0; - wire read_A_4__ap_done_global__q0; - wire read_A_4__ap_start; - wire read_A_4__ap_ready; - wire read_A_4__ap_done; - wire read_A_4__ap_idle; - reg [1:0] read_A_4__state; - wire read_A_5__ap_start_global__q0; - wire read_A_5__is_done__q0; - wire read_A_5__ap_done_global__q0; - wire read_A_5__ap_start; - wire read_A_5__ap_ready; - wire read_A_5__ap_done; - wire read_A_5__ap_idle; - reg [1:0] read_A_5__state; - wire read_A_6__ap_start_global__q0; - wire read_A_6__is_done__q0; - wire read_A_6__ap_done_global__q0; - wire read_A_6__ap_start; - wire read_A_6__ap_ready; - wire read_A_6__ap_done; - wire read_A_6__ap_idle; - reg [1:0] read_A_6__state; - wire read_A_7__ap_start_global__q0; - wire read_A_7__is_done__q0; - wire read_A_7__ap_done_global__q0; - wire read_A_7__ap_start; - wire read_A_7__ap_ready; - wire read_A_7__ap_done; - wire read_A_7__ap_idle; - reg [1:0] read_A_7__state; - wire read_B_0__ap_start_global__q0; - wire read_B_0__is_done__q0; - wire read_B_0__ap_done_global__q0; - wire read_B_0__ap_start; - wire read_B_0__ap_ready; - wire read_B_0__ap_done; - wire read_B_0__ap_idle; - reg [1:0] read_B_0__state; - wire read_B_1__ap_start_global__q0; - wire read_B_1__is_done__q0; - wire read_B_1__ap_done_global__q0; - wire read_B_1__ap_start; - wire read_B_1__ap_ready; - wire read_B_1__ap_done; - wire read_B_1__ap_idle; - reg [1:0] read_B_1__state; - wire read_B_2__ap_start_global__q0; - wire read_B_2__is_done__q0; - wire read_B_2__ap_done_global__q0; - wire read_B_2__ap_start; - wire read_B_2__ap_ready; - wire read_B_2__ap_done; - wire read_B_2__ap_idle; - reg [1:0] read_B_2__state; - wire read_B_3__ap_start_global__q0; - wire read_B_3__is_done__q0; - wire read_B_3__ap_done_global__q0; - wire read_B_3__ap_start; - wire read_B_3__ap_ready; - wire read_B_3__ap_done; - wire read_B_3__ap_idle; - reg [1:0] read_B_3__state; - wire read_C_0__ap_start_global__q0; - wire read_C_0__is_done__q0; - wire read_C_0__ap_done_global__q0; - wire read_C_0__ap_start; - wire read_C_0__ap_ready; - wire read_C_0__ap_done; - wire read_C_0__ap_idle; - reg [1:0] read_C_0__state; - wire read_C_1__ap_start_global__q0; - wire read_C_1__is_done__q0; - wire read_C_1__ap_done_global__q0; - wire read_C_1__ap_start; - wire read_C_1__ap_ready; - wire read_C_1__ap_done; - wire read_C_1__ap_idle; - reg [1:0] read_C_1__state; - wire read_C_2__ap_start_global__q0; - wire read_C_2__is_done__q0; - wire read_C_2__ap_done_global__q0; - wire read_C_2__ap_start; - wire read_C_2__ap_ready; - wire read_C_2__ap_done; - wire read_C_2__ap_idle; - reg [1:0] read_C_2__state; - wire read_C_3__ap_start_global__q0; - wire read_C_3__is_done__q0; - wire read_C_3__ap_done_global__q0; - wire read_C_3__ap_start; - wire read_C_3__ap_ready; - wire read_C_3__ap_done; - wire read_C_3__ap_idle; - reg [1:0] read_C_3__state; - wire read_C_4__ap_start_global__q0; - wire read_C_4__is_done__q0; - wire read_C_4__ap_done_global__q0; - wire read_C_4__ap_start; - wire read_C_4__ap_ready; - wire read_C_4__ap_done; - wire read_C_4__ap_idle; - reg [1:0] read_C_4__state; - wire read_C_5__ap_start_global__q0; - wire read_C_5__is_done__q0; - wire read_C_5__ap_done_global__q0; - wire read_C_5__ap_start; - wire read_C_5__ap_ready; - wire read_C_5__ap_done; - wire read_C_5__ap_idle; - reg [1:0] read_C_5__state; - wire read_C_6__ap_start_global__q0; - wire read_C_6__is_done__q0; - wire read_C_6__ap_done_global__q0; - wire read_C_6__ap_start; - wire read_C_6__ap_ready; - wire read_C_6__ap_done; - wire read_C_6__ap_idle; - reg [1:0] read_C_6__state; - wire read_C_7__ap_start_global__q0; - wire read_C_7__is_done__q0; - wire read_C_7__ap_done_global__q0; - wire read_C_7__ap_start; - wire read_C_7__ap_ready; - wire read_C_7__ap_done; - wire read_C_7__ap_idle; - reg [1:0] read_C_7__state; - wire read_edge_list_ptr_0__ap_start_global__q0; - wire read_edge_list_ptr_0__is_done__q0; - wire read_edge_list_ptr_0__ap_done_global__q0; - wire read_edge_list_ptr_0__ap_start; - wire read_edge_list_ptr_0__ap_ready; - wire read_edge_list_ptr_0__ap_done; - wire read_edge_list_ptr_0__ap_idle; - reg [1:0] read_edge_list_ptr_0__state; - wire write_C_0__ap_start_global__q0; - wire write_C_0__is_done__q0; - wire write_C_0__ap_done_global__q0; - wire write_C_0__ap_start; - wire write_C_0__ap_ready; - wire write_C_0__ap_done; - wire write_C_0__ap_idle; - reg [1:0] write_C_0__state; - wire write_C_1__ap_start_global__q0; - wire write_C_1__is_done__q0; - wire write_C_1__ap_done_global__q0; - wire write_C_1__ap_start; - wire write_C_1__ap_ready; - wire write_C_1__ap_done; - wire write_C_1__ap_idle; - reg [1:0] write_C_1__state; - wire write_C_2__ap_start_global__q0; - wire write_C_2__is_done__q0; - wire write_C_2__ap_done_global__q0; - wire write_C_2__ap_start; - wire write_C_2__ap_ready; - wire write_C_2__ap_done; - wire write_C_2__ap_idle; - reg [1:0] write_C_2__state; - wire write_C_3__ap_start_global__q0; - wire write_C_3__is_done__q0; - wire write_C_3__ap_done_global__q0; - wire write_C_3__ap_start; - wire write_C_3__ap_ready; - wire write_C_3__ap_done; - wire write_C_3__ap_idle; - reg [1:0] write_C_3__state; - wire write_C_4__ap_start_global__q0; - wire write_C_4__is_done__q0; - wire write_C_4__ap_done_global__q0; - wire write_C_4__ap_start; - wire write_C_4__ap_ready; - wire write_C_4__ap_done; - wire write_C_4__ap_idle; - reg [1:0] write_C_4__state; - wire write_C_5__ap_start_global__q0; - wire write_C_5__is_done__q0; - wire write_C_5__ap_done_global__q0; - wire write_C_5__ap_start; - wire write_C_5__ap_ready; - wire write_C_5__ap_done; - wire write_C_5__ap_idle; - reg [1:0] write_C_5__state; - wire write_C_6__ap_start_global__q0; - wire write_C_6__is_done__q0; - wire write_C_6__ap_done_global__q0; - wire write_C_6__ap_start; - wire write_C_6__ap_ready; - wire write_C_6__ap_done; - wire write_C_6__ap_idle; - reg [1:0] write_C_6__state; - wire write_C_7__ap_start_global__q0; - wire write_C_7__is_done__q0; - wire write_C_7__ap_done_global__q0; - wire write_C_7__ap_start; - wire write_C_7__ap_ready; - wire write_C_7__ap_done; - wire write_C_7__ap_idle; - reg [1:0] write_C_7__state; - reg [1:0] tapa_state; - reg [0:0] countdown; - wire ap_start__q0; - wire ap_done__q0; - assign FloatvAddFloatv_0__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvAddFloatv_0__ap_start <= 1'b0; - end else if(FloatvAddFloatv_0__ap_start_global__q0) begin - FloatvAddFloatv_0__ap_start <= 1'b1; - end - end - - assign FloatvAddFloatv_1__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvAddFloatv_1__ap_start <= 1'b0; - end else if(FloatvAddFloatv_1__ap_start_global__q0) begin - FloatvAddFloatv_1__ap_start <= 1'b1; - end - end - - assign FloatvAddFloatv_2__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvAddFloatv_2__ap_start <= 1'b0; - end else if(FloatvAddFloatv_2__ap_start_global__q0) begin - FloatvAddFloatv_2__ap_start <= 1'b1; - end - end - - assign FloatvAddFloatv_3__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvAddFloatv_3__ap_start <= 1'b0; - end else if(FloatvAddFloatv_3__ap_start_global__q0) begin - FloatvAddFloatv_3__ap_start <= 1'b1; - end - end - - assign FloatvAddFloatv_4__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvAddFloatv_4__ap_start <= 1'b0; - end else if(FloatvAddFloatv_4__ap_start_global__q0) begin - FloatvAddFloatv_4__ap_start <= 1'b1; - end - end - - assign FloatvAddFloatv_5__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvAddFloatv_5__ap_start <= 1'b0; - end else if(FloatvAddFloatv_5__ap_start_global__q0) begin - FloatvAddFloatv_5__ap_start <= 1'b1; - end - end - - assign FloatvAddFloatv_6__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvAddFloatv_6__ap_start <= 1'b0; - end else if(FloatvAddFloatv_6__ap_start_global__q0) begin - FloatvAddFloatv_6__ap_start <= 1'b1; - end - end - - assign FloatvAddFloatv_7__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvAddFloatv_7__ap_start <= 1'b0; - end else if(FloatvAddFloatv_7__ap_start_global__q0) begin - FloatvAddFloatv_7__ap_start <= 1'b1; - end - end - - assign FloatvMultConst_0__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_0__is_done__q0 = (FloatvMultConst_0__state == 2'b10); - assign FloatvMultConst_0__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_0__state <= 2'b00; - end else begin - if(FloatvMultConst_0__state == 2'b00) begin - if(FloatvMultConst_0__ap_start_global__q0) begin - FloatvMultConst_0__state <= 2'b01; - end - end - if(FloatvMultConst_0__state == 2'b01) begin - if(FloatvMultConst_0__ap_ready) begin - if(FloatvMultConst_0__ap_done) begin - FloatvMultConst_0__state <= 2'b10; - end else begin - FloatvMultConst_0__state <= 2'b11; - end - end - end - if(FloatvMultConst_0__state == 2'b11) begin - if(FloatvMultConst_0__ap_done) begin - FloatvMultConst_0__state <= 2'b10; - end - end - if(FloatvMultConst_0__state == 2'b10) begin - if(FloatvMultConst_0__ap_done_global__q0) begin - FloatvMultConst_0__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_0__ap_start = (FloatvMultConst_0__state == 2'b01); - assign FloatvMultConst_1__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_1__is_done__q0 = (FloatvMultConst_1__state == 2'b10); - assign FloatvMultConst_1__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_1__state <= 2'b00; - end else begin - if(FloatvMultConst_1__state == 2'b00) begin - if(FloatvMultConst_1__ap_start_global__q0) begin - FloatvMultConst_1__state <= 2'b01; - end - end - if(FloatvMultConst_1__state == 2'b01) begin - if(FloatvMultConst_1__ap_ready) begin - if(FloatvMultConst_1__ap_done) begin - FloatvMultConst_1__state <= 2'b10; - end else begin - FloatvMultConst_1__state <= 2'b11; - end - end - end - if(FloatvMultConst_1__state == 2'b11) begin - if(FloatvMultConst_1__ap_done) begin - FloatvMultConst_1__state <= 2'b10; - end - end - if(FloatvMultConst_1__state == 2'b10) begin - if(FloatvMultConst_1__ap_done_global__q0) begin - FloatvMultConst_1__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_1__ap_start = (FloatvMultConst_1__state == 2'b01); - assign FloatvMultConst_2__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_2__is_done__q0 = (FloatvMultConst_2__state == 2'b10); - assign FloatvMultConst_2__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_2__state <= 2'b00; - end else begin - if(FloatvMultConst_2__state == 2'b00) begin - if(FloatvMultConst_2__ap_start_global__q0) begin - FloatvMultConst_2__state <= 2'b01; - end - end - if(FloatvMultConst_2__state == 2'b01) begin - if(FloatvMultConst_2__ap_ready) begin - if(FloatvMultConst_2__ap_done) begin - FloatvMultConst_2__state <= 2'b10; - end else begin - FloatvMultConst_2__state <= 2'b11; - end - end - end - if(FloatvMultConst_2__state == 2'b11) begin - if(FloatvMultConst_2__ap_done) begin - FloatvMultConst_2__state <= 2'b10; - end - end - if(FloatvMultConst_2__state == 2'b10) begin - if(FloatvMultConst_2__ap_done_global__q0) begin - FloatvMultConst_2__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_2__ap_start = (FloatvMultConst_2__state == 2'b01); - assign FloatvMultConst_3__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_3__is_done__q0 = (FloatvMultConst_3__state == 2'b10); - assign FloatvMultConst_3__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_3__state <= 2'b00; - end else begin - if(FloatvMultConst_3__state == 2'b00) begin - if(FloatvMultConst_3__ap_start_global__q0) begin - FloatvMultConst_3__state <= 2'b01; - end - end - if(FloatvMultConst_3__state == 2'b01) begin - if(FloatvMultConst_3__ap_ready) begin - if(FloatvMultConst_3__ap_done) begin - FloatvMultConst_3__state <= 2'b10; - end else begin - FloatvMultConst_3__state <= 2'b11; - end - end - end - if(FloatvMultConst_3__state == 2'b11) begin - if(FloatvMultConst_3__ap_done) begin - FloatvMultConst_3__state <= 2'b10; - end - end - if(FloatvMultConst_3__state == 2'b10) begin - if(FloatvMultConst_3__ap_done_global__q0) begin - FloatvMultConst_3__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_3__ap_start = (FloatvMultConst_3__state == 2'b01); - assign FloatvMultConst_4__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_4__is_done__q0 = (FloatvMultConst_4__state == 2'b10); - assign FloatvMultConst_4__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_4__state <= 2'b00; - end else begin - if(FloatvMultConst_4__state == 2'b00) begin - if(FloatvMultConst_4__ap_start_global__q0) begin - FloatvMultConst_4__state <= 2'b01; - end - end - if(FloatvMultConst_4__state == 2'b01) begin - if(FloatvMultConst_4__ap_ready) begin - if(FloatvMultConst_4__ap_done) begin - FloatvMultConst_4__state <= 2'b10; - end else begin - FloatvMultConst_4__state <= 2'b11; - end - end - end - if(FloatvMultConst_4__state == 2'b11) begin - if(FloatvMultConst_4__ap_done) begin - FloatvMultConst_4__state <= 2'b10; - end - end - if(FloatvMultConst_4__state == 2'b10) begin - if(FloatvMultConst_4__ap_done_global__q0) begin - FloatvMultConst_4__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_4__ap_start = (FloatvMultConst_4__state == 2'b01); - assign FloatvMultConst_5__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_5__is_done__q0 = (FloatvMultConst_5__state == 2'b10); - assign FloatvMultConst_5__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_5__state <= 2'b00; - end else begin - if(FloatvMultConst_5__state == 2'b00) begin - if(FloatvMultConst_5__ap_start_global__q0) begin - FloatvMultConst_5__state <= 2'b01; - end - end - if(FloatvMultConst_5__state == 2'b01) begin - if(FloatvMultConst_5__ap_ready) begin - if(FloatvMultConst_5__ap_done) begin - FloatvMultConst_5__state <= 2'b10; - end else begin - FloatvMultConst_5__state <= 2'b11; - end - end - end - if(FloatvMultConst_5__state == 2'b11) begin - if(FloatvMultConst_5__ap_done) begin - FloatvMultConst_5__state <= 2'b10; - end - end - if(FloatvMultConst_5__state == 2'b10) begin - if(FloatvMultConst_5__ap_done_global__q0) begin - FloatvMultConst_5__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_5__ap_start = (FloatvMultConst_5__state == 2'b01); - assign FloatvMultConst_6__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_6__is_done__q0 = (FloatvMultConst_6__state == 2'b10); - assign FloatvMultConst_6__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_6__state <= 2'b00; - end else begin - if(FloatvMultConst_6__state == 2'b00) begin - if(FloatvMultConst_6__ap_start_global__q0) begin - FloatvMultConst_6__state <= 2'b01; - end - end - if(FloatvMultConst_6__state == 2'b01) begin - if(FloatvMultConst_6__ap_ready) begin - if(FloatvMultConst_6__ap_done) begin - FloatvMultConst_6__state <= 2'b10; - end else begin - FloatvMultConst_6__state <= 2'b11; - end - end - end - if(FloatvMultConst_6__state == 2'b11) begin - if(FloatvMultConst_6__ap_done) begin - FloatvMultConst_6__state <= 2'b10; - end - end - if(FloatvMultConst_6__state == 2'b10) begin - if(FloatvMultConst_6__ap_done_global__q0) begin - FloatvMultConst_6__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_6__ap_start = (FloatvMultConst_6__state == 2'b01); - assign FloatvMultConst_7__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_7__is_done__q0 = (FloatvMultConst_7__state == 2'b10); - assign FloatvMultConst_7__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_7__state <= 2'b00; - end else begin - if(FloatvMultConst_7__state == 2'b00) begin - if(FloatvMultConst_7__ap_start_global__q0) begin - FloatvMultConst_7__state <= 2'b01; - end - end - if(FloatvMultConst_7__state == 2'b01) begin - if(FloatvMultConst_7__ap_ready) begin - if(FloatvMultConst_7__ap_done) begin - FloatvMultConst_7__state <= 2'b10; - end else begin - FloatvMultConst_7__state <= 2'b11; - end - end - end - if(FloatvMultConst_7__state == 2'b11) begin - if(FloatvMultConst_7__ap_done) begin - FloatvMultConst_7__state <= 2'b10; - end - end - if(FloatvMultConst_7__state == 2'b10) begin - if(FloatvMultConst_7__ap_done_global__q0) begin - FloatvMultConst_7__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_7__ap_start = (FloatvMultConst_7__state == 2'b01); - assign FloatvMultConst_8__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_8__is_done__q0 = (FloatvMultConst_8__state == 2'b10); - assign FloatvMultConst_8__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_8__state <= 2'b00; - end else begin - if(FloatvMultConst_8__state == 2'b00) begin - if(FloatvMultConst_8__ap_start_global__q0) begin - FloatvMultConst_8__state <= 2'b01; - end - end - if(FloatvMultConst_8__state == 2'b01) begin - if(FloatvMultConst_8__ap_ready) begin - if(FloatvMultConst_8__ap_done) begin - FloatvMultConst_8__state <= 2'b10; - end else begin - FloatvMultConst_8__state <= 2'b11; - end - end - end - if(FloatvMultConst_8__state == 2'b11) begin - if(FloatvMultConst_8__ap_done) begin - FloatvMultConst_8__state <= 2'b10; - end - end - if(FloatvMultConst_8__state == 2'b10) begin - if(FloatvMultConst_8__ap_done_global__q0) begin - FloatvMultConst_8__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_8__ap_start = (FloatvMultConst_8__state == 2'b01); - assign FloatvMultConst_9__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_9__is_done__q0 = (FloatvMultConst_9__state == 2'b10); - assign FloatvMultConst_9__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_9__state <= 2'b00; - end else begin - if(FloatvMultConst_9__state == 2'b00) begin - if(FloatvMultConst_9__ap_start_global__q0) begin - FloatvMultConst_9__state <= 2'b01; - end - end - if(FloatvMultConst_9__state == 2'b01) begin - if(FloatvMultConst_9__ap_ready) begin - if(FloatvMultConst_9__ap_done) begin - FloatvMultConst_9__state <= 2'b10; - end else begin - FloatvMultConst_9__state <= 2'b11; - end - end - end - if(FloatvMultConst_9__state == 2'b11) begin - if(FloatvMultConst_9__ap_done) begin - FloatvMultConst_9__state <= 2'b10; - end - end - if(FloatvMultConst_9__state == 2'b10) begin - if(FloatvMultConst_9__ap_done_global__q0) begin - FloatvMultConst_9__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_9__ap_start = (FloatvMultConst_9__state == 2'b01); - assign FloatvMultConst_10__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_10__is_done__q0 = (FloatvMultConst_10__state == 2'b10); - assign FloatvMultConst_10__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_10__state <= 2'b00; - end else begin - if(FloatvMultConst_10__state == 2'b00) begin - if(FloatvMultConst_10__ap_start_global__q0) begin - FloatvMultConst_10__state <= 2'b01; - end - end - if(FloatvMultConst_10__state == 2'b01) begin - if(FloatvMultConst_10__ap_ready) begin - if(FloatvMultConst_10__ap_done) begin - FloatvMultConst_10__state <= 2'b10; - end else begin - FloatvMultConst_10__state <= 2'b11; - end - end - end - if(FloatvMultConst_10__state == 2'b11) begin - if(FloatvMultConst_10__ap_done) begin - FloatvMultConst_10__state <= 2'b10; - end - end - if(FloatvMultConst_10__state == 2'b10) begin - if(FloatvMultConst_10__ap_done_global__q0) begin - FloatvMultConst_10__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_10__ap_start = (FloatvMultConst_10__state == 2'b01); - assign FloatvMultConst_11__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_11__is_done__q0 = (FloatvMultConst_11__state == 2'b10); - assign FloatvMultConst_11__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_11__state <= 2'b00; - end else begin - if(FloatvMultConst_11__state == 2'b00) begin - if(FloatvMultConst_11__ap_start_global__q0) begin - FloatvMultConst_11__state <= 2'b01; - end - end - if(FloatvMultConst_11__state == 2'b01) begin - if(FloatvMultConst_11__ap_ready) begin - if(FloatvMultConst_11__ap_done) begin - FloatvMultConst_11__state <= 2'b10; - end else begin - FloatvMultConst_11__state <= 2'b11; - end - end - end - if(FloatvMultConst_11__state == 2'b11) begin - if(FloatvMultConst_11__ap_done) begin - FloatvMultConst_11__state <= 2'b10; - end - end - if(FloatvMultConst_11__state == 2'b10) begin - if(FloatvMultConst_11__ap_done_global__q0) begin - FloatvMultConst_11__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_11__ap_start = (FloatvMultConst_11__state == 2'b01); - assign FloatvMultConst_12__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_12__is_done__q0 = (FloatvMultConst_12__state == 2'b10); - assign FloatvMultConst_12__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_12__state <= 2'b00; - end else begin - if(FloatvMultConst_12__state == 2'b00) begin - if(FloatvMultConst_12__ap_start_global__q0) begin - FloatvMultConst_12__state <= 2'b01; - end - end - if(FloatvMultConst_12__state == 2'b01) begin - if(FloatvMultConst_12__ap_ready) begin - if(FloatvMultConst_12__ap_done) begin - FloatvMultConst_12__state <= 2'b10; - end else begin - FloatvMultConst_12__state <= 2'b11; - end - end - end - if(FloatvMultConst_12__state == 2'b11) begin - if(FloatvMultConst_12__ap_done) begin - FloatvMultConst_12__state <= 2'b10; - end - end - if(FloatvMultConst_12__state == 2'b10) begin - if(FloatvMultConst_12__ap_done_global__q0) begin - FloatvMultConst_12__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_12__ap_start = (FloatvMultConst_12__state == 2'b01); - assign FloatvMultConst_13__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_13__is_done__q0 = (FloatvMultConst_13__state == 2'b10); - assign FloatvMultConst_13__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_13__state <= 2'b00; - end else begin - if(FloatvMultConst_13__state == 2'b00) begin - if(FloatvMultConst_13__ap_start_global__q0) begin - FloatvMultConst_13__state <= 2'b01; - end - end - if(FloatvMultConst_13__state == 2'b01) begin - if(FloatvMultConst_13__ap_ready) begin - if(FloatvMultConst_13__ap_done) begin - FloatvMultConst_13__state <= 2'b10; - end else begin - FloatvMultConst_13__state <= 2'b11; - end - end - end - if(FloatvMultConst_13__state == 2'b11) begin - if(FloatvMultConst_13__ap_done) begin - FloatvMultConst_13__state <= 2'b10; - end - end - if(FloatvMultConst_13__state == 2'b10) begin - if(FloatvMultConst_13__ap_done_global__q0) begin - FloatvMultConst_13__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_13__ap_start = (FloatvMultConst_13__state == 2'b01); - assign FloatvMultConst_14__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_14__is_done__q0 = (FloatvMultConst_14__state == 2'b10); - assign FloatvMultConst_14__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_14__state <= 2'b00; - end else begin - if(FloatvMultConst_14__state == 2'b00) begin - if(FloatvMultConst_14__ap_start_global__q0) begin - FloatvMultConst_14__state <= 2'b01; - end - end - if(FloatvMultConst_14__state == 2'b01) begin - if(FloatvMultConst_14__ap_ready) begin - if(FloatvMultConst_14__ap_done) begin - FloatvMultConst_14__state <= 2'b10; - end else begin - FloatvMultConst_14__state <= 2'b11; - end - end - end - if(FloatvMultConst_14__state == 2'b11) begin - if(FloatvMultConst_14__ap_done) begin - FloatvMultConst_14__state <= 2'b10; - end - end - if(FloatvMultConst_14__state == 2'b10) begin - if(FloatvMultConst_14__ap_done_global__q0) begin - FloatvMultConst_14__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_14__ap_start = (FloatvMultConst_14__state == 2'b01); - assign FloatvMultConst_15__ap_start_global__q0 = ap_start__q0; - assign FloatvMultConst_15__is_done__q0 = (FloatvMultConst_15__state == 2'b10); - assign FloatvMultConst_15__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - FloatvMultConst_15__state <= 2'b00; - end else begin - if(FloatvMultConst_15__state == 2'b00) begin - if(FloatvMultConst_15__ap_start_global__q0) begin - FloatvMultConst_15__state <= 2'b01; - end - end - if(FloatvMultConst_15__state == 2'b01) begin - if(FloatvMultConst_15__ap_ready) begin - if(FloatvMultConst_15__ap_done) begin - FloatvMultConst_15__state <= 2'b10; - end else begin - FloatvMultConst_15__state <= 2'b11; - end - end - end - if(FloatvMultConst_15__state == 2'b11) begin - if(FloatvMultConst_15__ap_done) begin - FloatvMultConst_15__state <= 2'b10; - end - end - if(FloatvMultConst_15__state == 2'b10) begin - if(FloatvMultConst_15__ap_done_global__q0) begin - FloatvMultConst_15__state <= 2'b00; - end - end - end - end - - assign FloatvMultConst_15__ap_start = (FloatvMultConst_15__state == 2'b01); - assign Merger_0__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Merger_0__ap_start <= 1'b0; - end else if(Merger_0__ap_start_global__q0) begin - Merger_0__ap_start <= 1'b1; - end - end - - assign Merger_1__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Merger_1__ap_start <= 1'b0; - end else if(Merger_1__ap_start_global__q0) begin - Merger_1__ap_start <= 1'b1; - end - end - - assign Merger_2__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Merger_2__ap_start <= 1'b0; - end else if(Merger_2__ap_start_global__q0) begin - Merger_2__ap_start <= 1'b1; - end - end - - assign Merger_3__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Merger_3__ap_start <= 1'b0; - end else if(Merger_3__ap_start_global__q0) begin - Merger_3__ap_start <= 1'b1; - end - end - - assign Merger_4__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Merger_4__ap_start <= 1'b0; - end else if(Merger_4__ap_start_global__q0) begin - Merger_4__ap_start <= 1'b1; - end - end - - assign Merger_5__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Merger_5__ap_start <= 1'b0; - end else if(Merger_5__ap_start_global__q0) begin - Merger_5__ap_start <= 1'b1; - end - end - - assign Merger_6__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Merger_6__ap_start <= 1'b0; - end else if(Merger_6__ap_start_global__q0) begin - Merger_6__ap_start <= 1'b1; - end - end - - assign Merger_7__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Merger_7__ap_start <= 1'b0; - end else if(Merger_7__ap_start_global__q0) begin - Merger_7__ap_start <= 1'b1; - end - end - - assign PEG_Bmtx_0__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_0__is_done__q0 = (PEG_Bmtx_0__state == 2'b10); - assign PEG_Bmtx_0__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_0__state <= 2'b00; - end else begin - if(PEG_Bmtx_0__state == 2'b00) begin - if(PEG_Bmtx_0__ap_start_global__q0) begin - PEG_Bmtx_0__state <= 2'b01; - end - end - if(PEG_Bmtx_0__state == 2'b01) begin - if(PEG_Bmtx_0__ap_ready) begin - if(PEG_Bmtx_0__ap_done) begin - PEG_Bmtx_0__state <= 2'b10; - end else begin - PEG_Bmtx_0__state <= 2'b11; - end - end - end - if(PEG_Bmtx_0__state == 2'b11) begin - if(PEG_Bmtx_0__ap_done) begin - PEG_Bmtx_0__state <= 2'b10; - end - end - if(PEG_Bmtx_0__state == 2'b10) begin - if(PEG_Bmtx_0__ap_done_global__q0) begin - PEG_Bmtx_0__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_0__ap_start = (PEG_Bmtx_0__state == 2'b01); - assign PEG_Bmtx_1__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_1__is_done__q0 = (PEG_Bmtx_1__state == 2'b10); - assign PEG_Bmtx_1__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_1__state <= 2'b00; - end else begin - if(PEG_Bmtx_1__state == 2'b00) begin - if(PEG_Bmtx_1__ap_start_global__q0) begin - PEG_Bmtx_1__state <= 2'b01; - end - end - if(PEG_Bmtx_1__state == 2'b01) begin - if(PEG_Bmtx_1__ap_ready) begin - if(PEG_Bmtx_1__ap_done) begin - PEG_Bmtx_1__state <= 2'b10; - end else begin - PEG_Bmtx_1__state <= 2'b11; - end - end - end - if(PEG_Bmtx_1__state == 2'b11) begin - if(PEG_Bmtx_1__ap_done) begin - PEG_Bmtx_1__state <= 2'b10; - end - end - if(PEG_Bmtx_1__state == 2'b10) begin - if(PEG_Bmtx_1__ap_done_global__q0) begin - PEG_Bmtx_1__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_1__ap_start = (PEG_Bmtx_1__state == 2'b01); - assign PEG_Bmtx_2__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_2__is_done__q0 = (PEG_Bmtx_2__state == 2'b10); - assign PEG_Bmtx_2__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_2__state <= 2'b00; - end else begin - if(PEG_Bmtx_2__state == 2'b00) begin - if(PEG_Bmtx_2__ap_start_global__q0) begin - PEG_Bmtx_2__state <= 2'b01; - end - end - if(PEG_Bmtx_2__state == 2'b01) begin - if(PEG_Bmtx_2__ap_ready) begin - if(PEG_Bmtx_2__ap_done) begin - PEG_Bmtx_2__state <= 2'b10; - end else begin - PEG_Bmtx_2__state <= 2'b11; - end - end - end - if(PEG_Bmtx_2__state == 2'b11) begin - if(PEG_Bmtx_2__ap_done) begin - PEG_Bmtx_2__state <= 2'b10; - end - end - if(PEG_Bmtx_2__state == 2'b10) begin - if(PEG_Bmtx_2__ap_done_global__q0) begin - PEG_Bmtx_2__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_2__ap_start = (PEG_Bmtx_2__state == 2'b01); - assign PEG_Bmtx_3__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_3__is_done__q0 = (PEG_Bmtx_3__state == 2'b10); - assign PEG_Bmtx_3__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_3__state <= 2'b00; - end else begin - if(PEG_Bmtx_3__state == 2'b00) begin - if(PEG_Bmtx_3__ap_start_global__q0) begin - PEG_Bmtx_3__state <= 2'b01; - end - end - if(PEG_Bmtx_3__state == 2'b01) begin - if(PEG_Bmtx_3__ap_ready) begin - if(PEG_Bmtx_3__ap_done) begin - PEG_Bmtx_3__state <= 2'b10; - end else begin - PEG_Bmtx_3__state <= 2'b11; - end - end - end - if(PEG_Bmtx_3__state == 2'b11) begin - if(PEG_Bmtx_3__ap_done) begin - PEG_Bmtx_3__state <= 2'b10; - end - end - if(PEG_Bmtx_3__state == 2'b10) begin - if(PEG_Bmtx_3__ap_done_global__q0) begin - PEG_Bmtx_3__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_3__ap_start = (PEG_Bmtx_3__state == 2'b01); - assign PEG_Bmtx_4__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_4__is_done__q0 = (PEG_Bmtx_4__state == 2'b10); - assign PEG_Bmtx_4__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_4__state <= 2'b00; - end else begin - if(PEG_Bmtx_4__state == 2'b00) begin - if(PEG_Bmtx_4__ap_start_global__q0) begin - PEG_Bmtx_4__state <= 2'b01; - end - end - if(PEG_Bmtx_4__state == 2'b01) begin - if(PEG_Bmtx_4__ap_ready) begin - if(PEG_Bmtx_4__ap_done) begin - PEG_Bmtx_4__state <= 2'b10; - end else begin - PEG_Bmtx_4__state <= 2'b11; - end - end - end - if(PEG_Bmtx_4__state == 2'b11) begin - if(PEG_Bmtx_4__ap_done) begin - PEG_Bmtx_4__state <= 2'b10; - end - end - if(PEG_Bmtx_4__state == 2'b10) begin - if(PEG_Bmtx_4__ap_done_global__q0) begin - PEG_Bmtx_4__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_4__ap_start = (PEG_Bmtx_4__state == 2'b01); - assign PEG_Bmtx_5__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_5__is_done__q0 = (PEG_Bmtx_5__state == 2'b10); - assign PEG_Bmtx_5__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_5__state <= 2'b00; - end else begin - if(PEG_Bmtx_5__state == 2'b00) begin - if(PEG_Bmtx_5__ap_start_global__q0) begin - PEG_Bmtx_5__state <= 2'b01; - end - end - if(PEG_Bmtx_5__state == 2'b01) begin - if(PEG_Bmtx_5__ap_ready) begin - if(PEG_Bmtx_5__ap_done) begin - PEG_Bmtx_5__state <= 2'b10; - end else begin - PEG_Bmtx_5__state <= 2'b11; - end - end - end - if(PEG_Bmtx_5__state == 2'b11) begin - if(PEG_Bmtx_5__ap_done) begin - PEG_Bmtx_5__state <= 2'b10; - end - end - if(PEG_Bmtx_5__state == 2'b10) begin - if(PEG_Bmtx_5__ap_done_global__q0) begin - PEG_Bmtx_5__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_5__ap_start = (PEG_Bmtx_5__state == 2'b01); - assign PEG_Bmtx_6__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_6__is_done__q0 = (PEG_Bmtx_6__state == 2'b10); - assign PEG_Bmtx_6__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_6__state <= 2'b00; - end else begin - if(PEG_Bmtx_6__state == 2'b00) begin - if(PEG_Bmtx_6__ap_start_global__q0) begin - PEG_Bmtx_6__state <= 2'b01; - end - end - if(PEG_Bmtx_6__state == 2'b01) begin - if(PEG_Bmtx_6__ap_ready) begin - if(PEG_Bmtx_6__ap_done) begin - PEG_Bmtx_6__state <= 2'b10; - end else begin - PEG_Bmtx_6__state <= 2'b11; - end - end - end - if(PEG_Bmtx_6__state == 2'b11) begin - if(PEG_Bmtx_6__ap_done) begin - PEG_Bmtx_6__state <= 2'b10; - end - end - if(PEG_Bmtx_6__state == 2'b10) begin - if(PEG_Bmtx_6__ap_done_global__q0) begin - PEG_Bmtx_6__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_6__ap_start = (PEG_Bmtx_6__state == 2'b01); - assign PEG_Bmtx_7__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_7__is_done__q0 = (PEG_Bmtx_7__state == 2'b10); - assign PEG_Bmtx_7__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_7__state <= 2'b00; - end else begin - if(PEG_Bmtx_7__state == 2'b00) begin - if(PEG_Bmtx_7__ap_start_global__q0) begin - PEG_Bmtx_7__state <= 2'b01; - end - end - if(PEG_Bmtx_7__state == 2'b01) begin - if(PEG_Bmtx_7__ap_ready) begin - if(PEG_Bmtx_7__ap_done) begin - PEG_Bmtx_7__state <= 2'b10; - end else begin - PEG_Bmtx_7__state <= 2'b11; - end - end - end - if(PEG_Bmtx_7__state == 2'b11) begin - if(PEG_Bmtx_7__ap_done) begin - PEG_Bmtx_7__state <= 2'b10; - end - end - if(PEG_Bmtx_7__state == 2'b10) begin - if(PEG_Bmtx_7__ap_done_global__q0) begin - PEG_Bmtx_7__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_7__ap_start = (PEG_Bmtx_7__state == 2'b01); - assign PEG_Bmtx_8__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_8__is_done__q0 = (PEG_Bmtx_8__state == 2'b10); - assign PEG_Bmtx_8__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_8__state <= 2'b00; - end else begin - if(PEG_Bmtx_8__state == 2'b00) begin - if(PEG_Bmtx_8__ap_start_global__q0) begin - PEG_Bmtx_8__state <= 2'b01; - end - end - if(PEG_Bmtx_8__state == 2'b01) begin - if(PEG_Bmtx_8__ap_ready) begin - if(PEG_Bmtx_8__ap_done) begin - PEG_Bmtx_8__state <= 2'b10; - end else begin - PEG_Bmtx_8__state <= 2'b11; - end - end - end - if(PEG_Bmtx_8__state == 2'b11) begin - if(PEG_Bmtx_8__ap_done) begin - PEG_Bmtx_8__state <= 2'b10; - end - end - if(PEG_Bmtx_8__state == 2'b10) begin - if(PEG_Bmtx_8__ap_done_global__q0) begin - PEG_Bmtx_8__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_8__ap_start = (PEG_Bmtx_8__state == 2'b01); - assign PEG_Bmtx_9__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_9__is_done__q0 = (PEG_Bmtx_9__state == 2'b10); - assign PEG_Bmtx_9__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_9__state <= 2'b00; - end else begin - if(PEG_Bmtx_9__state == 2'b00) begin - if(PEG_Bmtx_9__ap_start_global__q0) begin - PEG_Bmtx_9__state <= 2'b01; - end - end - if(PEG_Bmtx_9__state == 2'b01) begin - if(PEG_Bmtx_9__ap_ready) begin - if(PEG_Bmtx_9__ap_done) begin - PEG_Bmtx_9__state <= 2'b10; - end else begin - PEG_Bmtx_9__state <= 2'b11; - end - end - end - if(PEG_Bmtx_9__state == 2'b11) begin - if(PEG_Bmtx_9__ap_done) begin - PEG_Bmtx_9__state <= 2'b10; - end - end - if(PEG_Bmtx_9__state == 2'b10) begin - if(PEG_Bmtx_9__ap_done_global__q0) begin - PEG_Bmtx_9__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_9__ap_start = (PEG_Bmtx_9__state == 2'b01); - assign PEG_Bmtx_10__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_10__is_done__q0 = (PEG_Bmtx_10__state == 2'b10); - assign PEG_Bmtx_10__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_10__state <= 2'b00; - end else begin - if(PEG_Bmtx_10__state == 2'b00) begin - if(PEG_Bmtx_10__ap_start_global__q0) begin - PEG_Bmtx_10__state <= 2'b01; - end - end - if(PEG_Bmtx_10__state == 2'b01) begin - if(PEG_Bmtx_10__ap_ready) begin - if(PEG_Bmtx_10__ap_done) begin - PEG_Bmtx_10__state <= 2'b10; - end else begin - PEG_Bmtx_10__state <= 2'b11; - end - end - end - if(PEG_Bmtx_10__state == 2'b11) begin - if(PEG_Bmtx_10__ap_done) begin - PEG_Bmtx_10__state <= 2'b10; - end - end - if(PEG_Bmtx_10__state == 2'b10) begin - if(PEG_Bmtx_10__ap_done_global__q0) begin - PEG_Bmtx_10__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_10__ap_start = (PEG_Bmtx_10__state == 2'b01); - assign PEG_Bmtx_11__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_11__is_done__q0 = (PEG_Bmtx_11__state == 2'b10); - assign PEG_Bmtx_11__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_11__state <= 2'b00; - end else begin - if(PEG_Bmtx_11__state == 2'b00) begin - if(PEG_Bmtx_11__ap_start_global__q0) begin - PEG_Bmtx_11__state <= 2'b01; - end - end - if(PEG_Bmtx_11__state == 2'b01) begin - if(PEG_Bmtx_11__ap_ready) begin - if(PEG_Bmtx_11__ap_done) begin - PEG_Bmtx_11__state <= 2'b10; - end else begin - PEG_Bmtx_11__state <= 2'b11; - end - end - end - if(PEG_Bmtx_11__state == 2'b11) begin - if(PEG_Bmtx_11__ap_done) begin - PEG_Bmtx_11__state <= 2'b10; - end - end - if(PEG_Bmtx_11__state == 2'b10) begin - if(PEG_Bmtx_11__ap_done_global__q0) begin - PEG_Bmtx_11__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_11__ap_start = (PEG_Bmtx_11__state == 2'b01); - assign PEG_Bmtx_12__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_12__is_done__q0 = (PEG_Bmtx_12__state == 2'b10); - assign PEG_Bmtx_12__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_12__state <= 2'b00; - end else begin - if(PEG_Bmtx_12__state == 2'b00) begin - if(PEG_Bmtx_12__ap_start_global__q0) begin - PEG_Bmtx_12__state <= 2'b01; - end - end - if(PEG_Bmtx_12__state == 2'b01) begin - if(PEG_Bmtx_12__ap_ready) begin - if(PEG_Bmtx_12__ap_done) begin - PEG_Bmtx_12__state <= 2'b10; - end else begin - PEG_Bmtx_12__state <= 2'b11; - end - end - end - if(PEG_Bmtx_12__state == 2'b11) begin - if(PEG_Bmtx_12__ap_done) begin - PEG_Bmtx_12__state <= 2'b10; - end - end - if(PEG_Bmtx_12__state == 2'b10) begin - if(PEG_Bmtx_12__ap_done_global__q0) begin - PEG_Bmtx_12__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_12__ap_start = (PEG_Bmtx_12__state == 2'b01); - assign PEG_Bmtx_13__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_13__is_done__q0 = (PEG_Bmtx_13__state == 2'b10); - assign PEG_Bmtx_13__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_13__state <= 2'b00; - end else begin - if(PEG_Bmtx_13__state == 2'b00) begin - if(PEG_Bmtx_13__ap_start_global__q0) begin - PEG_Bmtx_13__state <= 2'b01; - end - end - if(PEG_Bmtx_13__state == 2'b01) begin - if(PEG_Bmtx_13__ap_ready) begin - if(PEG_Bmtx_13__ap_done) begin - PEG_Bmtx_13__state <= 2'b10; - end else begin - PEG_Bmtx_13__state <= 2'b11; - end - end - end - if(PEG_Bmtx_13__state == 2'b11) begin - if(PEG_Bmtx_13__ap_done) begin - PEG_Bmtx_13__state <= 2'b10; - end - end - if(PEG_Bmtx_13__state == 2'b10) begin - if(PEG_Bmtx_13__ap_done_global__q0) begin - PEG_Bmtx_13__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_13__ap_start = (PEG_Bmtx_13__state == 2'b01); - assign PEG_Bmtx_14__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_14__is_done__q0 = (PEG_Bmtx_14__state == 2'b10); - assign PEG_Bmtx_14__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_14__state <= 2'b00; - end else begin - if(PEG_Bmtx_14__state == 2'b00) begin - if(PEG_Bmtx_14__ap_start_global__q0) begin - PEG_Bmtx_14__state <= 2'b01; - end - end - if(PEG_Bmtx_14__state == 2'b01) begin - if(PEG_Bmtx_14__ap_ready) begin - if(PEG_Bmtx_14__ap_done) begin - PEG_Bmtx_14__state <= 2'b10; - end else begin - PEG_Bmtx_14__state <= 2'b11; - end - end - end - if(PEG_Bmtx_14__state == 2'b11) begin - if(PEG_Bmtx_14__ap_done) begin - PEG_Bmtx_14__state <= 2'b10; - end - end - if(PEG_Bmtx_14__state == 2'b10) begin - if(PEG_Bmtx_14__ap_done_global__q0) begin - PEG_Bmtx_14__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_14__ap_start = (PEG_Bmtx_14__state == 2'b01); - assign PEG_Bmtx_15__ap_start_global__q0 = ap_start__q0; - assign PEG_Bmtx_15__is_done__q0 = (PEG_Bmtx_15__state == 2'b10); - assign PEG_Bmtx_15__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Bmtx_15__state <= 2'b00; - end else begin - if(PEG_Bmtx_15__state == 2'b00) begin - if(PEG_Bmtx_15__ap_start_global__q0) begin - PEG_Bmtx_15__state <= 2'b01; - end - end - if(PEG_Bmtx_15__state == 2'b01) begin - if(PEG_Bmtx_15__ap_ready) begin - if(PEG_Bmtx_15__ap_done) begin - PEG_Bmtx_15__state <= 2'b10; - end else begin - PEG_Bmtx_15__state <= 2'b11; - end - end - end - if(PEG_Bmtx_15__state == 2'b11) begin - if(PEG_Bmtx_15__ap_done) begin - PEG_Bmtx_15__state <= 2'b10; - end - end - if(PEG_Bmtx_15__state == 2'b10) begin - if(PEG_Bmtx_15__ap_done_global__q0) begin - PEG_Bmtx_15__state <= 2'b00; - end - end - end - end - - assign PEG_Bmtx_15__ap_start = (PEG_Bmtx_15__state == 2'b01); - assign PEG_Cmtx_0__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_0__is_done__q0 = (PEG_Cmtx_0__state == 2'b10); - assign PEG_Cmtx_0__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_0__state <= 2'b00; - end else begin - if(PEG_Cmtx_0__state == 2'b00) begin - if(PEG_Cmtx_0__ap_start_global__q0) begin - PEG_Cmtx_0__state <= 2'b01; - end - end - if(PEG_Cmtx_0__state == 2'b01) begin - if(PEG_Cmtx_0__ap_ready) begin - if(PEG_Cmtx_0__ap_done) begin - PEG_Cmtx_0__state <= 2'b10; - end else begin - PEG_Cmtx_0__state <= 2'b11; - end - end - end - if(PEG_Cmtx_0__state == 2'b11) begin - if(PEG_Cmtx_0__ap_done) begin - PEG_Cmtx_0__state <= 2'b10; - end - end - if(PEG_Cmtx_0__state == 2'b10) begin - if(PEG_Cmtx_0__ap_done_global__q0) begin - PEG_Cmtx_0__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_0__ap_start = (PEG_Cmtx_0__state == 2'b01); - assign PEG_Cmtx_1__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_1__is_done__q0 = (PEG_Cmtx_1__state == 2'b10); - assign PEG_Cmtx_1__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_1__state <= 2'b00; - end else begin - if(PEG_Cmtx_1__state == 2'b00) begin - if(PEG_Cmtx_1__ap_start_global__q0) begin - PEG_Cmtx_1__state <= 2'b01; - end - end - if(PEG_Cmtx_1__state == 2'b01) begin - if(PEG_Cmtx_1__ap_ready) begin - if(PEG_Cmtx_1__ap_done) begin - PEG_Cmtx_1__state <= 2'b10; - end else begin - PEG_Cmtx_1__state <= 2'b11; - end - end - end - if(PEG_Cmtx_1__state == 2'b11) begin - if(PEG_Cmtx_1__ap_done) begin - PEG_Cmtx_1__state <= 2'b10; - end - end - if(PEG_Cmtx_1__state == 2'b10) begin - if(PEG_Cmtx_1__ap_done_global__q0) begin - PEG_Cmtx_1__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_1__ap_start = (PEG_Cmtx_1__state == 2'b01); - assign PEG_Cmtx_2__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_2__is_done__q0 = (PEG_Cmtx_2__state == 2'b10); - assign PEG_Cmtx_2__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_2__state <= 2'b00; - end else begin - if(PEG_Cmtx_2__state == 2'b00) begin - if(PEG_Cmtx_2__ap_start_global__q0) begin - PEG_Cmtx_2__state <= 2'b01; - end - end - if(PEG_Cmtx_2__state == 2'b01) begin - if(PEG_Cmtx_2__ap_ready) begin - if(PEG_Cmtx_2__ap_done) begin - PEG_Cmtx_2__state <= 2'b10; - end else begin - PEG_Cmtx_2__state <= 2'b11; - end - end - end - if(PEG_Cmtx_2__state == 2'b11) begin - if(PEG_Cmtx_2__ap_done) begin - PEG_Cmtx_2__state <= 2'b10; - end - end - if(PEG_Cmtx_2__state == 2'b10) begin - if(PEG_Cmtx_2__ap_done_global__q0) begin - PEG_Cmtx_2__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_2__ap_start = (PEG_Cmtx_2__state == 2'b01); - assign PEG_Cmtx_3__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_3__is_done__q0 = (PEG_Cmtx_3__state == 2'b10); - assign PEG_Cmtx_3__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_3__state <= 2'b00; - end else begin - if(PEG_Cmtx_3__state == 2'b00) begin - if(PEG_Cmtx_3__ap_start_global__q0) begin - PEG_Cmtx_3__state <= 2'b01; - end - end - if(PEG_Cmtx_3__state == 2'b01) begin - if(PEG_Cmtx_3__ap_ready) begin - if(PEG_Cmtx_3__ap_done) begin - PEG_Cmtx_3__state <= 2'b10; - end else begin - PEG_Cmtx_3__state <= 2'b11; - end - end - end - if(PEG_Cmtx_3__state == 2'b11) begin - if(PEG_Cmtx_3__ap_done) begin - PEG_Cmtx_3__state <= 2'b10; - end - end - if(PEG_Cmtx_3__state == 2'b10) begin - if(PEG_Cmtx_3__ap_done_global__q0) begin - PEG_Cmtx_3__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_3__ap_start = (PEG_Cmtx_3__state == 2'b01); - assign PEG_Cmtx_4__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_4__is_done__q0 = (PEG_Cmtx_4__state == 2'b10); - assign PEG_Cmtx_4__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_4__state <= 2'b00; - end else begin - if(PEG_Cmtx_4__state == 2'b00) begin - if(PEG_Cmtx_4__ap_start_global__q0) begin - PEG_Cmtx_4__state <= 2'b01; - end - end - if(PEG_Cmtx_4__state == 2'b01) begin - if(PEG_Cmtx_4__ap_ready) begin - if(PEG_Cmtx_4__ap_done) begin - PEG_Cmtx_4__state <= 2'b10; - end else begin - PEG_Cmtx_4__state <= 2'b11; - end - end - end - if(PEG_Cmtx_4__state == 2'b11) begin - if(PEG_Cmtx_4__ap_done) begin - PEG_Cmtx_4__state <= 2'b10; - end - end - if(PEG_Cmtx_4__state == 2'b10) begin - if(PEG_Cmtx_4__ap_done_global__q0) begin - PEG_Cmtx_4__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_4__ap_start = (PEG_Cmtx_4__state == 2'b01); - assign PEG_Cmtx_5__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_5__is_done__q0 = (PEG_Cmtx_5__state == 2'b10); - assign PEG_Cmtx_5__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_5__state <= 2'b00; - end else begin - if(PEG_Cmtx_5__state == 2'b00) begin - if(PEG_Cmtx_5__ap_start_global__q0) begin - PEG_Cmtx_5__state <= 2'b01; - end - end - if(PEG_Cmtx_5__state == 2'b01) begin - if(PEG_Cmtx_5__ap_ready) begin - if(PEG_Cmtx_5__ap_done) begin - PEG_Cmtx_5__state <= 2'b10; - end else begin - PEG_Cmtx_5__state <= 2'b11; - end - end - end - if(PEG_Cmtx_5__state == 2'b11) begin - if(PEG_Cmtx_5__ap_done) begin - PEG_Cmtx_5__state <= 2'b10; - end - end - if(PEG_Cmtx_5__state == 2'b10) begin - if(PEG_Cmtx_5__ap_done_global__q0) begin - PEG_Cmtx_5__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_5__ap_start = (PEG_Cmtx_5__state == 2'b01); - assign PEG_Cmtx_6__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_6__is_done__q0 = (PEG_Cmtx_6__state == 2'b10); - assign PEG_Cmtx_6__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_6__state <= 2'b00; - end else begin - if(PEG_Cmtx_6__state == 2'b00) begin - if(PEG_Cmtx_6__ap_start_global__q0) begin - PEG_Cmtx_6__state <= 2'b01; - end - end - if(PEG_Cmtx_6__state == 2'b01) begin - if(PEG_Cmtx_6__ap_ready) begin - if(PEG_Cmtx_6__ap_done) begin - PEG_Cmtx_6__state <= 2'b10; - end else begin - PEG_Cmtx_6__state <= 2'b11; - end - end - end - if(PEG_Cmtx_6__state == 2'b11) begin - if(PEG_Cmtx_6__ap_done) begin - PEG_Cmtx_6__state <= 2'b10; - end - end - if(PEG_Cmtx_6__state == 2'b10) begin - if(PEG_Cmtx_6__ap_done_global__q0) begin - PEG_Cmtx_6__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_6__ap_start = (PEG_Cmtx_6__state == 2'b01); - assign PEG_Cmtx_7__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_7__is_done__q0 = (PEG_Cmtx_7__state == 2'b10); - assign PEG_Cmtx_7__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_7__state <= 2'b00; - end else begin - if(PEG_Cmtx_7__state == 2'b00) begin - if(PEG_Cmtx_7__ap_start_global__q0) begin - PEG_Cmtx_7__state <= 2'b01; - end - end - if(PEG_Cmtx_7__state == 2'b01) begin - if(PEG_Cmtx_7__ap_ready) begin - if(PEG_Cmtx_7__ap_done) begin - PEG_Cmtx_7__state <= 2'b10; - end else begin - PEG_Cmtx_7__state <= 2'b11; - end - end - end - if(PEG_Cmtx_7__state == 2'b11) begin - if(PEG_Cmtx_7__ap_done) begin - PEG_Cmtx_7__state <= 2'b10; - end - end - if(PEG_Cmtx_7__state == 2'b10) begin - if(PEG_Cmtx_7__ap_done_global__q0) begin - PEG_Cmtx_7__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_7__ap_start = (PEG_Cmtx_7__state == 2'b01); - assign PEG_Cmtx_8__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_8__is_done__q0 = (PEG_Cmtx_8__state == 2'b10); - assign PEG_Cmtx_8__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_8__state <= 2'b00; - end else begin - if(PEG_Cmtx_8__state == 2'b00) begin - if(PEG_Cmtx_8__ap_start_global__q0) begin - PEG_Cmtx_8__state <= 2'b01; - end - end - if(PEG_Cmtx_8__state == 2'b01) begin - if(PEG_Cmtx_8__ap_ready) begin - if(PEG_Cmtx_8__ap_done) begin - PEG_Cmtx_8__state <= 2'b10; - end else begin - PEG_Cmtx_8__state <= 2'b11; - end - end - end - if(PEG_Cmtx_8__state == 2'b11) begin - if(PEG_Cmtx_8__ap_done) begin - PEG_Cmtx_8__state <= 2'b10; - end - end - if(PEG_Cmtx_8__state == 2'b10) begin - if(PEG_Cmtx_8__ap_done_global__q0) begin - PEG_Cmtx_8__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_8__ap_start = (PEG_Cmtx_8__state == 2'b01); - assign PEG_Cmtx_9__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_9__is_done__q0 = (PEG_Cmtx_9__state == 2'b10); - assign PEG_Cmtx_9__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_9__state <= 2'b00; - end else begin - if(PEG_Cmtx_9__state == 2'b00) begin - if(PEG_Cmtx_9__ap_start_global__q0) begin - PEG_Cmtx_9__state <= 2'b01; - end - end - if(PEG_Cmtx_9__state == 2'b01) begin - if(PEG_Cmtx_9__ap_ready) begin - if(PEG_Cmtx_9__ap_done) begin - PEG_Cmtx_9__state <= 2'b10; - end else begin - PEG_Cmtx_9__state <= 2'b11; - end - end - end - if(PEG_Cmtx_9__state == 2'b11) begin - if(PEG_Cmtx_9__ap_done) begin - PEG_Cmtx_9__state <= 2'b10; - end - end - if(PEG_Cmtx_9__state == 2'b10) begin - if(PEG_Cmtx_9__ap_done_global__q0) begin - PEG_Cmtx_9__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_9__ap_start = (PEG_Cmtx_9__state == 2'b01); - assign PEG_Cmtx_10__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_10__is_done__q0 = (PEG_Cmtx_10__state == 2'b10); - assign PEG_Cmtx_10__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_10__state <= 2'b00; - end else begin - if(PEG_Cmtx_10__state == 2'b00) begin - if(PEG_Cmtx_10__ap_start_global__q0) begin - PEG_Cmtx_10__state <= 2'b01; - end - end - if(PEG_Cmtx_10__state == 2'b01) begin - if(PEG_Cmtx_10__ap_ready) begin - if(PEG_Cmtx_10__ap_done) begin - PEG_Cmtx_10__state <= 2'b10; - end else begin - PEG_Cmtx_10__state <= 2'b11; - end - end - end - if(PEG_Cmtx_10__state == 2'b11) begin - if(PEG_Cmtx_10__ap_done) begin - PEG_Cmtx_10__state <= 2'b10; - end - end - if(PEG_Cmtx_10__state == 2'b10) begin - if(PEG_Cmtx_10__ap_done_global__q0) begin - PEG_Cmtx_10__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_10__ap_start = (PEG_Cmtx_10__state == 2'b01); - assign PEG_Cmtx_11__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_11__is_done__q0 = (PEG_Cmtx_11__state == 2'b10); - assign PEG_Cmtx_11__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_11__state <= 2'b00; - end else begin - if(PEG_Cmtx_11__state == 2'b00) begin - if(PEG_Cmtx_11__ap_start_global__q0) begin - PEG_Cmtx_11__state <= 2'b01; - end - end - if(PEG_Cmtx_11__state == 2'b01) begin - if(PEG_Cmtx_11__ap_ready) begin - if(PEG_Cmtx_11__ap_done) begin - PEG_Cmtx_11__state <= 2'b10; - end else begin - PEG_Cmtx_11__state <= 2'b11; - end - end - end - if(PEG_Cmtx_11__state == 2'b11) begin - if(PEG_Cmtx_11__ap_done) begin - PEG_Cmtx_11__state <= 2'b10; - end - end - if(PEG_Cmtx_11__state == 2'b10) begin - if(PEG_Cmtx_11__ap_done_global__q0) begin - PEG_Cmtx_11__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_11__ap_start = (PEG_Cmtx_11__state == 2'b01); - assign PEG_Cmtx_12__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_12__is_done__q0 = (PEG_Cmtx_12__state == 2'b10); - assign PEG_Cmtx_12__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_12__state <= 2'b00; - end else begin - if(PEG_Cmtx_12__state == 2'b00) begin - if(PEG_Cmtx_12__ap_start_global__q0) begin - PEG_Cmtx_12__state <= 2'b01; - end - end - if(PEG_Cmtx_12__state == 2'b01) begin - if(PEG_Cmtx_12__ap_ready) begin - if(PEG_Cmtx_12__ap_done) begin - PEG_Cmtx_12__state <= 2'b10; - end else begin - PEG_Cmtx_12__state <= 2'b11; - end - end - end - if(PEG_Cmtx_12__state == 2'b11) begin - if(PEG_Cmtx_12__ap_done) begin - PEG_Cmtx_12__state <= 2'b10; - end - end - if(PEG_Cmtx_12__state == 2'b10) begin - if(PEG_Cmtx_12__ap_done_global__q0) begin - PEG_Cmtx_12__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_12__ap_start = (PEG_Cmtx_12__state == 2'b01); - assign PEG_Cmtx_13__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_13__is_done__q0 = (PEG_Cmtx_13__state == 2'b10); - assign PEG_Cmtx_13__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_13__state <= 2'b00; - end else begin - if(PEG_Cmtx_13__state == 2'b00) begin - if(PEG_Cmtx_13__ap_start_global__q0) begin - PEG_Cmtx_13__state <= 2'b01; - end - end - if(PEG_Cmtx_13__state == 2'b01) begin - if(PEG_Cmtx_13__ap_ready) begin - if(PEG_Cmtx_13__ap_done) begin - PEG_Cmtx_13__state <= 2'b10; - end else begin - PEG_Cmtx_13__state <= 2'b11; - end - end - end - if(PEG_Cmtx_13__state == 2'b11) begin - if(PEG_Cmtx_13__ap_done) begin - PEG_Cmtx_13__state <= 2'b10; - end - end - if(PEG_Cmtx_13__state == 2'b10) begin - if(PEG_Cmtx_13__ap_done_global__q0) begin - PEG_Cmtx_13__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_13__ap_start = (PEG_Cmtx_13__state == 2'b01); - assign PEG_Cmtx_14__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_14__is_done__q0 = (PEG_Cmtx_14__state == 2'b10); - assign PEG_Cmtx_14__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_14__state <= 2'b00; - end else begin - if(PEG_Cmtx_14__state == 2'b00) begin - if(PEG_Cmtx_14__ap_start_global__q0) begin - PEG_Cmtx_14__state <= 2'b01; - end - end - if(PEG_Cmtx_14__state == 2'b01) begin - if(PEG_Cmtx_14__ap_ready) begin - if(PEG_Cmtx_14__ap_done) begin - PEG_Cmtx_14__state <= 2'b10; - end else begin - PEG_Cmtx_14__state <= 2'b11; - end - end - end - if(PEG_Cmtx_14__state == 2'b11) begin - if(PEG_Cmtx_14__ap_done) begin - PEG_Cmtx_14__state <= 2'b10; - end - end - if(PEG_Cmtx_14__state == 2'b10) begin - if(PEG_Cmtx_14__ap_done_global__q0) begin - PEG_Cmtx_14__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_14__ap_start = (PEG_Cmtx_14__state == 2'b01); - assign PEG_Cmtx_15__ap_start_global__q0 = ap_start__q0; - assign PEG_Cmtx_15__is_done__q0 = (PEG_Cmtx_15__state == 2'b10); - assign PEG_Cmtx_15__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - PEG_Cmtx_15__state <= 2'b00; - end else begin - if(PEG_Cmtx_15__state == 2'b00) begin - if(PEG_Cmtx_15__ap_start_global__q0) begin - PEG_Cmtx_15__state <= 2'b01; - end - end - if(PEG_Cmtx_15__state == 2'b01) begin - if(PEG_Cmtx_15__ap_ready) begin - if(PEG_Cmtx_15__ap_done) begin - PEG_Cmtx_15__state <= 2'b10; - end else begin - PEG_Cmtx_15__state <= 2'b11; - end - end - end - if(PEG_Cmtx_15__state == 2'b11) begin - if(PEG_Cmtx_15__ap_done) begin - PEG_Cmtx_15__state <= 2'b10; - end - end - if(PEG_Cmtx_15__state == 2'b10) begin - if(PEG_Cmtx_15__ap_done_global__q0) begin - PEG_Cmtx_15__state <= 2'b00; - end - end - end - end - - assign PEG_Cmtx_15__ap_start = (PEG_Cmtx_15__state == 2'b01); - assign Scatter_1_2_0__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Scatter_1_2_0__ap_start <= 1'b0; - end else if(Scatter_1_2_0__ap_start_global__q0) begin - Scatter_1_2_0__ap_start <= 1'b1; - end - end - - assign Scatter_1_2_1__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Scatter_1_2_1__ap_start <= 1'b0; - end else if(Scatter_1_2_1__ap_start_global__q0) begin - Scatter_1_2_1__ap_start <= 1'b1; - end - end - - assign Scatter_1_2_2__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Scatter_1_2_2__ap_start <= 1'b0; - end else if(Scatter_1_2_2__ap_start_global__q0) begin - Scatter_1_2_2__ap_start <= 1'b1; - end - end - - assign Scatter_1_2_3__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Scatter_1_2_3__ap_start <= 1'b0; - end else if(Scatter_1_2_3__ap_start_global__q0) begin - Scatter_1_2_3__ap_start <= 1'b1; - end - end - - assign Scatter_1_2_4__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Scatter_1_2_4__ap_start <= 1'b0; - end else if(Scatter_1_2_4__ap_start_global__q0) begin - Scatter_1_2_4__ap_start <= 1'b1; - end - end - - assign Scatter_1_2_5__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Scatter_1_2_5__ap_start <= 1'b0; - end else if(Scatter_1_2_5__ap_start_global__q0) begin - Scatter_1_2_5__ap_start <= 1'b1; - end - end - - assign Scatter_1_2_6__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Scatter_1_2_6__ap_start <= 1'b0; - end else if(Scatter_1_2_6__ap_start_global__q0) begin - Scatter_1_2_6__ap_start <= 1'b1; - end - end - - assign Scatter_1_2_7__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - Scatter_1_2_7__ap_start <= 1'b0; - end else if(Scatter_1_2_7__ap_start_global__q0) begin - Scatter_1_2_7__ap_start <= 1'b1; - end - end - - assign black_hole_float_v16_0__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - black_hole_float_v16_0__ap_start <= 1'b0; - end else if(black_hole_float_v16_0__ap_start_global__q0) begin - black_hole_float_v16_0__ap_start <= 1'b1; - end - end - - assign black_hole_float_v16_1__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - black_hole_float_v16_1__ap_start <= 1'b0; - end else if(black_hole_float_v16_1__ap_start_global__q0) begin - black_hole_float_v16_1__ap_start <= 1'b1; - end - end - - assign black_hole_float_v16_2__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - black_hole_float_v16_2__ap_start <= 1'b0; - end else if(black_hole_float_v16_2__ap_start_global__q0) begin - black_hole_float_v16_2__ap_start <= 1'b1; - end - end - - assign black_hole_float_v16_3__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - black_hole_float_v16_3__ap_start <= 1'b0; - end else if(black_hole_float_v16_3__ap_start_global__q0) begin - black_hole_float_v16_3__ap_start <= 1'b1; - end - end - - assign black_hole_int_0__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - black_hole_int_0__ap_start <= 1'b0; - end else if(black_hole_int_0__ap_start_global__q0) begin - black_hole_int_0__ap_start <= 1'b1; - end - end - - assign black_hole_int_1__ap_start_global__q0 = ap_start__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - black_hole_int_1__ap_start <= 1'b0; - end else if(black_hole_int_1__ap_start_global__q0) begin - black_hole_int_1__ap_start <= 1'b1; - end - end - - assign read_A_0__ap_start_global__q0 = ap_start__q0; - assign read_A_0__is_done__q0 = (read_A_0__state == 2'b10); - assign read_A_0__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_A_0__state <= 2'b00; - end else begin - if(read_A_0__state == 2'b00) begin - if(read_A_0__ap_start_global__q0) begin - read_A_0__state <= 2'b01; - end - end - if(read_A_0__state == 2'b01) begin - if(read_A_0__ap_ready) begin - if(read_A_0__ap_done) begin - read_A_0__state <= 2'b10; - end else begin - read_A_0__state <= 2'b11; - end - end - end - if(read_A_0__state == 2'b11) begin - if(read_A_0__ap_done) begin - read_A_0__state <= 2'b10; - end - end - if(read_A_0__state == 2'b10) begin - if(read_A_0__ap_done_global__q0) begin - read_A_0__state <= 2'b00; - end - end - end - end - - assign read_A_0__ap_start = (read_A_0__state == 2'b01); - assign read_A_1__ap_start_global__q0 = ap_start__q0; - assign read_A_1__is_done__q0 = (read_A_1__state == 2'b10); - assign read_A_1__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_A_1__state <= 2'b00; - end else begin - if(read_A_1__state == 2'b00) begin - if(read_A_1__ap_start_global__q0) begin - read_A_1__state <= 2'b01; - end - end - if(read_A_1__state == 2'b01) begin - if(read_A_1__ap_ready) begin - if(read_A_1__ap_done) begin - read_A_1__state <= 2'b10; - end else begin - read_A_1__state <= 2'b11; - end - end - end - if(read_A_1__state == 2'b11) begin - if(read_A_1__ap_done) begin - read_A_1__state <= 2'b10; - end - end - if(read_A_1__state == 2'b10) begin - if(read_A_1__ap_done_global__q0) begin - read_A_1__state <= 2'b00; - end - end - end - end - - assign read_A_1__ap_start = (read_A_1__state == 2'b01); - assign read_A_2__ap_start_global__q0 = ap_start__q0; - assign read_A_2__is_done__q0 = (read_A_2__state == 2'b10); - assign read_A_2__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_A_2__state <= 2'b00; - end else begin - if(read_A_2__state == 2'b00) begin - if(read_A_2__ap_start_global__q0) begin - read_A_2__state <= 2'b01; - end - end - if(read_A_2__state == 2'b01) begin - if(read_A_2__ap_ready) begin - if(read_A_2__ap_done) begin - read_A_2__state <= 2'b10; - end else begin - read_A_2__state <= 2'b11; - end - end - end - if(read_A_2__state == 2'b11) begin - if(read_A_2__ap_done) begin - read_A_2__state <= 2'b10; - end - end - if(read_A_2__state == 2'b10) begin - if(read_A_2__ap_done_global__q0) begin - read_A_2__state <= 2'b00; - end - end - end - end - - assign read_A_2__ap_start = (read_A_2__state == 2'b01); - assign read_A_3__ap_start_global__q0 = ap_start__q0; - assign read_A_3__is_done__q0 = (read_A_3__state == 2'b10); - assign read_A_3__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_A_3__state <= 2'b00; - end else begin - if(read_A_3__state == 2'b00) begin - if(read_A_3__ap_start_global__q0) begin - read_A_3__state <= 2'b01; - end - end - if(read_A_3__state == 2'b01) begin - if(read_A_3__ap_ready) begin - if(read_A_3__ap_done) begin - read_A_3__state <= 2'b10; - end else begin - read_A_3__state <= 2'b11; - end - end - end - if(read_A_3__state == 2'b11) begin - if(read_A_3__ap_done) begin - read_A_3__state <= 2'b10; - end - end - if(read_A_3__state == 2'b10) begin - if(read_A_3__ap_done_global__q0) begin - read_A_3__state <= 2'b00; - end - end - end - end - - assign read_A_3__ap_start = (read_A_3__state == 2'b01); - assign read_A_4__ap_start_global__q0 = ap_start__q0; - assign read_A_4__is_done__q0 = (read_A_4__state == 2'b10); - assign read_A_4__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_A_4__state <= 2'b00; - end else begin - if(read_A_4__state == 2'b00) begin - if(read_A_4__ap_start_global__q0) begin - read_A_4__state <= 2'b01; - end - end - if(read_A_4__state == 2'b01) begin - if(read_A_4__ap_ready) begin - if(read_A_4__ap_done) begin - read_A_4__state <= 2'b10; - end else begin - read_A_4__state <= 2'b11; - end - end - end - if(read_A_4__state == 2'b11) begin - if(read_A_4__ap_done) begin - read_A_4__state <= 2'b10; - end - end - if(read_A_4__state == 2'b10) begin - if(read_A_4__ap_done_global__q0) begin - read_A_4__state <= 2'b00; - end - end - end - end - - assign read_A_4__ap_start = (read_A_4__state == 2'b01); - assign read_A_5__ap_start_global__q0 = ap_start__q0; - assign read_A_5__is_done__q0 = (read_A_5__state == 2'b10); - assign read_A_5__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_A_5__state <= 2'b00; - end else begin - if(read_A_5__state == 2'b00) begin - if(read_A_5__ap_start_global__q0) begin - read_A_5__state <= 2'b01; - end - end - if(read_A_5__state == 2'b01) begin - if(read_A_5__ap_ready) begin - if(read_A_5__ap_done) begin - read_A_5__state <= 2'b10; - end else begin - read_A_5__state <= 2'b11; - end - end - end - if(read_A_5__state == 2'b11) begin - if(read_A_5__ap_done) begin - read_A_5__state <= 2'b10; - end - end - if(read_A_5__state == 2'b10) begin - if(read_A_5__ap_done_global__q0) begin - read_A_5__state <= 2'b00; - end - end - end - end - - assign read_A_5__ap_start = (read_A_5__state == 2'b01); - assign read_A_6__ap_start_global__q0 = ap_start__q0; - assign read_A_6__is_done__q0 = (read_A_6__state == 2'b10); - assign read_A_6__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_A_6__state <= 2'b00; - end else begin - if(read_A_6__state == 2'b00) begin - if(read_A_6__ap_start_global__q0) begin - read_A_6__state <= 2'b01; - end - end - if(read_A_6__state == 2'b01) begin - if(read_A_6__ap_ready) begin - if(read_A_6__ap_done) begin - read_A_6__state <= 2'b10; - end else begin - read_A_6__state <= 2'b11; - end - end - end - if(read_A_6__state == 2'b11) begin - if(read_A_6__ap_done) begin - read_A_6__state <= 2'b10; - end - end - if(read_A_6__state == 2'b10) begin - if(read_A_6__ap_done_global__q0) begin - read_A_6__state <= 2'b00; - end - end - end - end - - assign read_A_6__ap_start = (read_A_6__state == 2'b01); - assign read_A_7__ap_start_global__q0 = ap_start__q0; - assign read_A_7__is_done__q0 = (read_A_7__state == 2'b10); - assign read_A_7__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_A_7__state <= 2'b00; - end else begin - if(read_A_7__state == 2'b00) begin - if(read_A_7__ap_start_global__q0) begin - read_A_7__state <= 2'b01; - end - end - if(read_A_7__state == 2'b01) begin - if(read_A_7__ap_ready) begin - if(read_A_7__ap_done) begin - read_A_7__state <= 2'b10; - end else begin - read_A_7__state <= 2'b11; - end - end - end - if(read_A_7__state == 2'b11) begin - if(read_A_7__ap_done) begin - read_A_7__state <= 2'b10; - end - end - if(read_A_7__state == 2'b10) begin - if(read_A_7__ap_done_global__q0) begin - read_A_7__state <= 2'b00; - end - end - end - end - - assign read_A_7__ap_start = (read_A_7__state == 2'b01); - assign read_B_0__ap_start_global__q0 = ap_start__q0; - assign read_B_0__is_done__q0 = (read_B_0__state == 2'b10); - assign read_B_0__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_B_0__state <= 2'b00; - end else begin - if(read_B_0__state == 2'b00) begin - if(read_B_0__ap_start_global__q0) begin - read_B_0__state <= 2'b01; - end - end - if(read_B_0__state == 2'b01) begin - if(read_B_0__ap_ready) begin - if(read_B_0__ap_done) begin - read_B_0__state <= 2'b10; - end else begin - read_B_0__state <= 2'b11; - end - end - end - if(read_B_0__state == 2'b11) begin - if(read_B_0__ap_done) begin - read_B_0__state <= 2'b10; - end - end - if(read_B_0__state == 2'b10) begin - if(read_B_0__ap_done_global__q0) begin - read_B_0__state <= 2'b00; - end - end - end - end - - assign read_B_0__ap_start = (read_B_0__state == 2'b01); - assign read_B_1__ap_start_global__q0 = ap_start__q0; - assign read_B_1__is_done__q0 = (read_B_1__state == 2'b10); - assign read_B_1__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_B_1__state <= 2'b00; - end else begin - if(read_B_1__state == 2'b00) begin - if(read_B_1__ap_start_global__q0) begin - read_B_1__state <= 2'b01; - end - end - if(read_B_1__state == 2'b01) begin - if(read_B_1__ap_ready) begin - if(read_B_1__ap_done) begin - read_B_1__state <= 2'b10; - end else begin - read_B_1__state <= 2'b11; - end - end - end - if(read_B_1__state == 2'b11) begin - if(read_B_1__ap_done) begin - read_B_1__state <= 2'b10; - end - end - if(read_B_1__state == 2'b10) begin - if(read_B_1__ap_done_global__q0) begin - read_B_1__state <= 2'b00; - end - end - end - end - - assign read_B_1__ap_start = (read_B_1__state == 2'b01); - assign read_B_2__ap_start_global__q0 = ap_start__q0; - assign read_B_2__is_done__q0 = (read_B_2__state == 2'b10); - assign read_B_2__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_B_2__state <= 2'b00; - end else begin - if(read_B_2__state == 2'b00) begin - if(read_B_2__ap_start_global__q0) begin - read_B_2__state <= 2'b01; - end - end - if(read_B_2__state == 2'b01) begin - if(read_B_2__ap_ready) begin - if(read_B_2__ap_done) begin - read_B_2__state <= 2'b10; - end else begin - read_B_2__state <= 2'b11; - end - end - end - if(read_B_2__state == 2'b11) begin - if(read_B_2__ap_done) begin - read_B_2__state <= 2'b10; - end - end - if(read_B_2__state == 2'b10) begin - if(read_B_2__ap_done_global__q0) begin - read_B_2__state <= 2'b00; - end - end - end - end - - assign read_B_2__ap_start = (read_B_2__state == 2'b01); - assign read_B_3__ap_start_global__q0 = ap_start__q0; - assign read_B_3__is_done__q0 = (read_B_3__state == 2'b10); - assign read_B_3__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_B_3__state <= 2'b00; - end else begin - if(read_B_3__state == 2'b00) begin - if(read_B_3__ap_start_global__q0) begin - read_B_3__state <= 2'b01; - end - end - if(read_B_3__state == 2'b01) begin - if(read_B_3__ap_ready) begin - if(read_B_3__ap_done) begin - read_B_3__state <= 2'b10; - end else begin - read_B_3__state <= 2'b11; - end - end - end - if(read_B_3__state == 2'b11) begin - if(read_B_3__ap_done) begin - read_B_3__state <= 2'b10; - end - end - if(read_B_3__state == 2'b10) begin - if(read_B_3__ap_done_global__q0) begin - read_B_3__state <= 2'b00; - end - end - end - end - - assign read_B_3__ap_start = (read_B_3__state == 2'b01); - assign read_C_0__ap_start_global__q0 = ap_start__q0; - assign read_C_0__is_done__q0 = (read_C_0__state == 2'b10); - assign read_C_0__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_C_0__state <= 2'b00; - end else begin - if(read_C_0__state == 2'b00) begin - if(read_C_0__ap_start_global__q0) begin - read_C_0__state <= 2'b01; - end - end - if(read_C_0__state == 2'b01) begin - if(read_C_0__ap_ready) begin - if(read_C_0__ap_done) begin - read_C_0__state <= 2'b10; - end else begin - read_C_0__state <= 2'b11; - end - end - end - if(read_C_0__state == 2'b11) begin - if(read_C_0__ap_done) begin - read_C_0__state <= 2'b10; - end - end - if(read_C_0__state == 2'b10) begin - if(read_C_0__ap_done_global__q0) begin - read_C_0__state <= 2'b00; - end - end - end - end - - assign read_C_0__ap_start = (read_C_0__state == 2'b01); - assign read_C_1__ap_start_global__q0 = ap_start__q0; - assign read_C_1__is_done__q0 = (read_C_1__state == 2'b10); - assign read_C_1__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_C_1__state <= 2'b00; - end else begin - if(read_C_1__state == 2'b00) begin - if(read_C_1__ap_start_global__q0) begin - read_C_1__state <= 2'b01; - end - end - if(read_C_1__state == 2'b01) begin - if(read_C_1__ap_ready) begin - if(read_C_1__ap_done) begin - read_C_1__state <= 2'b10; - end else begin - read_C_1__state <= 2'b11; - end - end - end - if(read_C_1__state == 2'b11) begin - if(read_C_1__ap_done) begin - read_C_1__state <= 2'b10; - end - end - if(read_C_1__state == 2'b10) begin - if(read_C_1__ap_done_global__q0) begin - read_C_1__state <= 2'b00; - end - end - end - end - - assign read_C_1__ap_start = (read_C_1__state == 2'b01); - assign read_C_2__ap_start_global__q0 = ap_start__q0; - assign read_C_2__is_done__q0 = (read_C_2__state == 2'b10); - assign read_C_2__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_C_2__state <= 2'b00; - end else begin - if(read_C_2__state == 2'b00) begin - if(read_C_2__ap_start_global__q0) begin - read_C_2__state <= 2'b01; - end - end - if(read_C_2__state == 2'b01) begin - if(read_C_2__ap_ready) begin - if(read_C_2__ap_done) begin - read_C_2__state <= 2'b10; - end else begin - read_C_2__state <= 2'b11; - end - end - end - if(read_C_2__state == 2'b11) begin - if(read_C_2__ap_done) begin - read_C_2__state <= 2'b10; - end - end - if(read_C_2__state == 2'b10) begin - if(read_C_2__ap_done_global__q0) begin - read_C_2__state <= 2'b00; - end - end - end - end - - assign read_C_2__ap_start = (read_C_2__state == 2'b01); - assign read_C_3__ap_start_global__q0 = ap_start__q0; - assign read_C_3__is_done__q0 = (read_C_3__state == 2'b10); - assign read_C_3__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_C_3__state <= 2'b00; - end else begin - if(read_C_3__state == 2'b00) begin - if(read_C_3__ap_start_global__q0) begin - read_C_3__state <= 2'b01; - end - end - if(read_C_3__state == 2'b01) begin - if(read_C_3__ap_ready) begin - if(read_C_3__ap_done) begin - read_C_3__state <= 2'b10; - end else begin - read_C_3__state <= 2'b11; - end - end - end - if(read_C_3__state == 2'b11) begin - if(read_C_3__ap_done) begin - read_C_3__state <= 2'b10; - end - end - if(read_C_3__state == 2'b10) begin - if(read_C_3__ap_done_global__q0) begin - read_C_3__state <= 2'b00; - end - end - end - end - - assign read_C_3__ap_start = (read_C_3__state == 2'b01); - assign read_C_4__ap_start_global__q0 = ap_start__q0; - assign read_C_4__is_done__q0 = (read_C_4__state == 2'b10); - assign read_C_4__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_C_4__state <= 2'b00; - end else begin - if(read_C_4__state == 2'b00) begin - if(read_C_4__ap_start_global__q0) begin - read_C_4__state <= 2'b01; - end - end - if(read_C_4__state == 2'b01) begin - if(read_C_4__ap_ready) begin - if(read_C_4__ap_done) begin - read_C_4__state <= 2'b10; - end else begin - read_C_4__state <= 2'b11; - end - end - end - if(read_C_4__state == 2'b11) begin - if(read_C_4__ap_done) begin - read_C_4__state <= 2'b10; - end - end - if(read_C_4__state == 2'b10) begin - if(read_C_4__ap_done_global__q0) begin - read_C_4__state <= 2'b00; - end - end - end - end - - assign read_C_4__ap_start = (read_C_4__state == 2'b01); - assign read_C_5__ap_start_global__q0 = ap_start__q0; - assign read_C_5__is_done__q0 = (read_C_5__state == 2'b10); - assign read_C_5__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_C_5__state <= 2'b00; - end else begin - if(read_C_5__state == 2'b00) begin - if(read_C_5__ap_start_global__q0) begin - read_C_5__state <= 2'b01; - end - end - if(read_C_5__state == 2'b01) begin - if(read_C_5__ap_ready) begin - if(read_C_5__ap_done) begin - read_C_5__state <= 2'b10; - end else begin - read_C_5__state <= 2'b11; - end - end - end - if(read_C_5__state == 2'b11) begin - if(read_C_5__ap_done) begin - read_C_5__state <= 2'b10; - end - end - if(read_C_5__state == 2'b10) begin - if(read_C_5__ap_done_global__q0) begin - read_C_5__state <= 2'b00; - end - end - end - end - - assign read_C_5__ap_start = (read_C_5__state == 2'b01); - assign read_C_6__ap_start_global__q0 = ap_start__q0; - assign read_C_6__is_done__q0 = (read_C_6__state == 2'b10); - assign read_C_6__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_C_6__state <= 2'b00; - end else begin - if(read_C_6__state == 2'b00) begin - if(read_C_6__ap_start_global__q0) begin - read_C_6__state <= 2'b01; - end - end - if(read_C_6__state == 2'b01) begin - if(read_C_6__ap_ready) begin - if(read_C_6__ap_done) begin - read_C_6__state <= 2'b10; - end else begin - read_C_6__state <= 2'b11; - end - end - end - if(read_C_6__state == 2'b11) begin - if(read_C_6__ap_done) begin - read_C_6__state <= 2'b10; - end - end - if(read_C_6__state == 2'b10) begin - if(read_C_6__ap_done_global__q0) begin - read_C_6__state <= 2'b00; - end - end - end - end - - assign read_C_6__ap_start = (read_C_6__state == 2'b01); - assign read_C_7__ap_start_global__q0 = ap_start__q0; - assign read_C_7__is_done__q0 = (read_C_7__state == 2'b10); - assign read_C_7__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_C_7__state <= 2'b00; - end else begin - if(read_C_7__state == 2'b00) begin - if(read_C_7__ap_start_global__q0) begin - read_C_7__state <= 2'b01; - end - end - if(read_C_7__state == 2'b01) begin - if(read_C_7__ap_ready) begin - if(read_C_7__ap_done) begin - read_C_7__state <= 2'b10; - end else begin - read_C_7__state <= 2'b11; - end - end - end - if(read_C_7__state == 2'b11) begin - if(read_C_7__ap_done) begin - read_C_7__state <= 2'b10; - end - end - if(read_C_7__state == 2'b10) begin - if(read_C_7__ap_done_global__q0) begin - read_C_7__state <= 2'b00; - end - end - end - end - - assign read_C_7__ap_start = (read_C_7__state == 2'b01); - assign read_edge_list_ptr_0__ap_start_global__q0 = ap_start__q0; - assign read_edge_list_ptr_0__is_done__q0 = (read_edge_list_ptr_0__state == 2'b10); - assign read_edge_list_ptr_0__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - read_edge_list_ptr_0__state <= 2'b00; - end else begin - if(read_edge_list_ptr_0__state == 2'b00) begin - if(read_edge_list_ptr_0__ap_start_global__q0) begin - read_edge_list_ptr_0__state <= 2'b01; - end - end - if(read_edge_list_ptr_0__state == 2'b01) begin - if(read_edge_list_ptr_0__ap_ready) begin - if(read_edge_list_ptr_0__ap_done) begin - read_edge_list_ptr_0__state <= 2'b10; - end else begin - read_edge_list_ptr_0__state <= 2'b11; - end - end - end - if(read_edge_list_ptr_0__state == 2'b11) begin - if(read_edge_list_ptr_0__ap_done) begin - read_edge_list_ptr_0__state <= 2'b10; - end - end - if(read_edge_list_ptr_0__state == 2'b10) begin - if(read_edge_list_ptr_0__ap_done_global__q0) begin - read_edge_list_ptr_0__state <= 2'b00; - end - end - end - end - - assign read_edge_list_ptr_0__ap_start = (read_edge_list_ptr_0__state == 2'b01); - assign write_C_0__ap_start_global__q0 = ap_start__q0; - assign write_C_0__is_done__q0 = (write_C_0__state == 2'b10); - assign write_C_0__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - write_C_0__state <= 2'b00; - end else begin - if(write_C_0__state == 2'b00) begin - if(write_C_0__ap_start_global__q0) begin - write_C_0__state <= 2'b01; - end - end - if(write_C_0__state == 2'b01) begin - if(write_C_0__ap_ready) begin - if(write_C_0__ap_done) begin - write_C_0__state <= 2'b10; - end else begin - write_C_0__state <= 2'b11; - end - end - end - if(write_C_0__state == 2'b11) begin - if(write_C_0__ap_done) begin - write_C_0__state <= 2'b10; - end - end - if(write_C_0__state == 2'b10) begin - if(write_C_0__ap_done_global__q0) begin - write_C_0__state <= 2'b00; - end - end - end - end - - assign write_C_0__ap_start = (write_C_0__state == 2'b01); - assign write_C_1__ap_start_global__q0 = ap_start__q0; - assign write_C_1__is_done__q0 = (write_C_1__state == 2'b10); - assign write_C_1__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - write_C_1__state <= 2'b00; - end else begin - if(write_C_1__state == 2'b00) begin - if(write_C_1__ap_start_global__q0) begin - write_C_1__state <= 2'b01; - end - end - if(write_C_1__state == 2'b01) begin - if(write_C_1__ap_ready) begin - if(write_C_1__ap_done) begin - write_C_1__state <= 2'b10; - end else begin - write_C_1__state <= 2'b11; - end - end - end - if(write_C_1__state == 2'b11) begin - if(write_C_1__ap_done) begin - write_C_1__state <= 2'b10; - end - end - if(write_C_1__state == 2'b10) begin - if(write_C_1__ap_done_global__q0) begin - write_C_1__state <= 2'b00; - end - end - end - end - - assign write_C_1__ap_start = (write_C_1__state == 2'b01); - assign write_C_2__ap_start_global__q0 = ap_start__q0; - assign write_C_2__is_done__q0 = (write_C_2__state == 2'b10); - assign write_C_2__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - write_C_2__state <= 2'b00; - end else begin - if(write_C_2__state == 2'b00) begin - if(write_C_2__ap_start_global__q0) begin - write_C_2__state <= 2'b01; - end - end - if(write_C_2__state == 2'b01) begin - if(write_C_2__ap_ready) begin - if(write_C_2__ap_done) begin - write_C_2__state <= 2'b10; - end else begin - write_C_2__state <= 2'b11; - end - end - end - if(write_C_2__state == 2'b11) begin - if(write_C_2__ap_done) begin - write_C_2__state <= 2'b10; - end - end - if(write_C_2__state == 2'b10) begin - if(write_C_2__ap_done_global__q0) begin - write_C_2__state <= 2'b00; - end - end - end - end - - assign write_C_2__ap_start = (write_C_2__state == 2'b01); - assign write_C_3__ap_start_global__q0 = ap_start__q0; - assign write_C_3__is_done__q0 = (write_C_3__state == 2'b10); - assign write_C_3__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - write_C_3__state <= 2'b00; - end else begin - if(write_C_3__state == 2'b00) begin - if(write_C_3__ap_start_global__q0) begin - write_C_3__state <= 2'b01; - end - end - if(write_C_3__state == 2'b01) begin - if(write_C_3__ap_ready) begin - if(write_C_3__ap_done) begin - write_C_3__state <= 2'b10; - end else begin - write_C_3__state <= 2'b11; - end - end - end - if(write_C_3__state == 2'b11) begin - if(write_C_3__ap_done) begin - write_C_3__state <= 2'b10; - end - end - if(write_C_3__state == 2'b10) begin - if(write_C_3__ap_done_global__q0) begin - write_C_3__state <= 2'b00; - end - end - end - end - - assign write_C_3__ap_start = (write_C_3__state == 2'b01); - assign write_C_4__ap_start_global__q0 = ap_start__q0; - assign write_C_4__is_done__q0 = (write_C_4__state == 2'b10); - assign write_C_4__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - write_C_4__state <= 2'b00; - end else begin - if(write_C_4__state == 2'b00) begin - if(write_C_4__ap_start_global__q0) begin - write_C_4__state <= 2'b01; - end - end - if(write_C_4__state == 2'b01) begin - if(write_C_4__ap_ready) begin - if(write_C_4__ap_done) begin - write_C_4__state <= 2'b10; - end else begin - write_C_4__state <= 2'b11; - end - end - end - if(write_C_4__state == 2'b11) begin - if(write_C_4__ap_done) begin - write_C_4__state <= 2'b10; - end - end - if(write_C_4__state == 2'b10) begin - if(write_C_4__ap_done_global__q0) begin - write_C_4__state <= 2'b00; - end - end - end - end - - assign write_C_4__ap_start = (write_C_4__state == 2'b01); - assign write_C_5__ap_start_global__q0 = ap_start__q0; - assign write_C_5__is_done__q0 = (write_C_5__state == 2'b10); - assign write_C_5__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - write_C_5__state <= 2'b00; - end else begin - if(write_C_5__state == 2'b00) begin - if(write_C_5__ap_start_global__q0) begin - write_C_5__state <= 2'b01; - end - end - if(write_C_5__state == 2'b01) begin - if(write_C_5__ap_ready) begin - if(write_C_5__ap_done) begin - write_C_5__state <= 2'b10; - end else begin - write_C_5__state <= 2'b11; - end - end - end - if(write_C_5__state == 2'b11) begin - if(write_C_5__ap_done) begin - write_C_5__state <= 2'b10; - end - end - if(write_C_5__state == 2'b10) begin - if(write_C_5__ap_done_global__q0) begin - write_C_5__state <= 2'b00; - end - end - end - end - - assign write_C_5__ap_start = (write_C_5__state == 2'b01); - assign write_C_6__ap_start_global__q0 = ap_start__q0; - assign write_C_6__is_done__q0 = (write_C_6__state == 2'b10); - assign write_C_6__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - write_C_6__state <= 2'b00; - end else begin - if(write_C_6__state == 2'b00) begin - if(write_C_6__ap_start_global__q0) begin - write_C_6__state <= 2'b01; - end - end - if(write_C_6__state == 2'b01) begin - if(write_C_6__ap_ready) begin - if(write_C_6__ap_done) begin - write_C_6__state <= 2'b10; - end else begin - write_C_6__state <= 2'b11; - end - end - end - if(write_C_6__state == 2'b11) begin - if(write_C_6__ap_done) begin - write_C_6__state <= 2'b10; - end - end - if(write_C_6__state == 2'b10) begin - if(write_C_6__ap_done_global__q0) begin - write_C_6__state <= 2'b00; - end - end - end - end - - assign write_C_6__ap_start = (write_C_6__state == 2'b01); - assign write_C_7__ap_start_global__q0 = ap_start__q0; - assign write_C_7__is_done__q0 = (write_C_7__state == 2'b10); - assign write_C_7__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - write_C_7__state <= 2'b00; - end else begin - if(write_C_7__state == 2'b00) begin - if(write_C_7__ap_start_global__q0) begin - write_C_7__state <= 2'b01; - end - end - if(write_C_7__state == 2'b01) begin - if(write_C_7__ap_ready) begin - if(write_C_7__ap_done) begin - write_C_7__state <= 2'b10; - end else begin - write_C_7__state <= 2'b11; - end - end - end - if(write_C_7__state == 2'b11) begin - if(write_C_7__ap_done) begin - write_C_7__state <= 2'b10; - end - end - if(write_C_7__state == 2'b10) begin - if(write_C_7__ap_done_global__q0) begin - write_C_7__state <= 2'b00; - end - end - end - end - - assign write_C_7__ap_start = (write_C_7__state == 2'b01); - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - tapa_state <= 2'b00; - end else begin - case(tapa_state) - 2'b00: begin - if(ap_start__q0) begin - tapa_state <= 2'b01; - end - end - 2'b01: begin - if(FloatvMultConst_0__is_done__q0 && FloatvMultConst_1__is_done__q0 && FloatvMultConst_2__is_done__q0 && FloatvMultConst_3__is_done__q0 && FloatvMultConst_4__is_done__q0 && FloatvMultConst_5__is_done__q0 && FloatvMultConst_6__is_done__q0 && FloatvMultConst_7__is_done__q0 && FloatvMultConst_8__is_done__q0 && FloatvMultConst_9__is_done__q0 && FloatvMultConst_10__is_done__q0 && FloatvMultConst_11__is_done__q0 && FloatvMultConst_12__is_done__q0 && FloatvMultConst_13__is_done__q0 && FloatvMultConst_14__is_done__q0 && FloatvMultConst_15__is_done__q0 && PEG_Bmtx_0__is_done__q0 && PEG_Bmtx_1__is_done__q0 && PEG_Bmtx_2__is_done__q0 && PEG_Bmtx_3__is_done__q0 && PEG_Bmtx_4__is_done__q0 && PEG_Bmtx_5__is_done__q0 && PEG_Bmtx_6__is_done__q0 && PEG_Bmtx_7__is_done__q0 && PEG_Bmtx_8__is_done__q0 && PEG_Bmtx_9__is_done__q0 && PEG_Bmtx_10__is_done__q0 && PEG_Bmtx_11__is_done__q0 && PEG_Bmtx_12__is_done__q0 && PEG_Bmtx_13__is_done__q0 && PEG_Bmtx_14__is_done__q0 && PEG_Bmtx_15__is_done__q0 && PEG_Cmtx_0__is_done__q0 && PEG_Cmtx_1__is_done__q0 && PEG_Cmtx_2__is_done__q0 && PEG_Cmtx_3__is_done__q0 && PEG_Cmtx_4__is_done__q0 && PEG_Cmtx_5__is_done__q0 && PEG_Cmtx_6__is_done__q0 && PEG_Cmtx_7__is_done__q0 && PEG_Cmtx_8__is_done__q0 && PEG_Cmtx_9__is_done__q0 && PEG_Cmtx_10__is_done__q0 && PEG_Cmtx_11__is_done__q0 && PEG_Cmtx_12__is_done__q0 && PEG_Cmtx_13__is_done__q0 && PEG_Cmtx_14__is_done__q0 && PEG_Cmtx_15__is_done__q0 && read_A_0__is_done__q0 && read_A_1__is_done__q0 && read_A_2__is_done__q0 && read_A_3__is_done__q0 && read_A_4__is_done__q0 && read_A_5__is_done__q0 && read_A_6__is_done__q0 && read_A_7__is_done__q0 && read_B_0__is_done__q0 && read_B_1__is_done__q0 && read_B_2__is_done__q0 && read_B_3__is_done__q0 && read_C_0__is_done__q0 && read_C_1__is_done__q0 && read_C_2__is_done__q0 && read_C_3__is_done__q0 && read_C_4__is_done__q0 && read_C_5__is_done__q0 && read_C_6__is_done__q0 && read_C_7__is_done__q0 && read_edge_list_ptr_0__is_done__q0 && write_C_0__is_done__q0 && write_C_1__is_done__q0 && write_C_2__is_done__q0 && write_C_3__is_done__q0 && write_C_4__is_done__q0 && write_C_5__is_done__q0 && write_C_6__is_done__q0 && write_C_7__is_done__q0) begin - tapa_state <= 2'b10; - end - end - 2'b10: begin - tapa_state <= 2'b00; - countdown <= 1'd0; - end - 2'b11: begin - if(countdown == 1'd0) begin - tapa_state <= 2'b00; - end else begin - countdown <= (countdown - 1'd1); - end - end - endcase - end - end - - assign ap_idle = (tapa_state == 2'b00); - assign ap_done = ap_done__q0; - assign ap_ready = ap_done__q0; - assign ap_start__q0 = ap_start; - assign ap_done__q0 = (tapa_state == 2'b10); - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/a_axi_write_broadcastor_1_to_3.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/a_axi_write_broadcastor_1_to_3.v deleted file mode 100644 index d84fe57e..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/a_axi_write_broadcastor_1_to_3.v +++ /dev/null @@ -1,269 +0,0 @@ - -module a_axi_write_broadcastor_1_to_3 ( - ap_clk, - - s_axi_control_AWVALID_slr_0, - s_axi_control_AWREADY_slr_0, - s_axi_control_AWADDR_slr_0, - s_axi_control_WVALID_slr_0, - s_axi_control_WREADY_slr_0, - s_axi_control_WDATA_slr_0, - s_axi_control_WSTRB_slr_0, - s_axi_control_AWVALID_slr_1, - s_axi_control_AWREADY_slr_1, - s_axi_control_AWADDR_slr_1, - s_axi_control_WVALID_slr_1, - s_axi_control_WREADY_slr_1, - s_axi_control_WDATA_slr_1, - s_axi_control_WSTRB_slr_1, - s_axi_control_AWVALID_slr_2, - s_axi_control_AWREADY_slr_2, - s_axi_control_AWADDR_slr_2, - s_axi_control_WVALID_slr_2, - s_axi_control_WREADY_slr_2, - s_axi_control_WDATA_slr_2, - s_axi_control_WSTRB_slr_2, - s_axi_control_AWVALID, - s_axi_control_AWREADY, - s_axi_control_AWADDR, - s_axi_control_WVALID, - s_axi_control_WREADY, - s_axi_control_WDATA, - s_axi_control_WSTRB -); - parameter C_S_AXI_CONTROL_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_ADDR_WIDTH = 9; - parameter C_S_AXI_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_WSTRB_WIDTH = 32 / 8; - parameter C_S_AXI_WSTRB_WIDTH = 32 / 8; - - input ap_clk; - - input s_axi_control_AWVALID; - output s_axi_control_AWREADY; - input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR; - input s_axi_control_WVALID; - output s_axi_control_WREADY; - input [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA; - input [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB; - - output s_axi_control_AWVALID_slr_0; - input s_axi_control_AWREADY_slr_0; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0; - output s_axi_control_WVALID_slr_0; - input s_axi_control_WREADY_slr_0; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0; - - output s_axi_control_AWVALID_slr_1; - input s_axi_control_AWREADY_slr_1; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1; - output s_axi_control_WVALID_slr_1; - input s_axi_control_WREADY_slr_1; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1; - - output s_axi_control_AWVALID_slr_2; - input s_axi_control_AWREADY_slr_2; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2; - output s_axi_control_WVALID_slr_2; - input s_axi_control_WREADY_slr_2; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2; - - wire s_axi_control_AWVALID_slr_0_inner; - wire s_axi_control_AWREADY_slr_0_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0_inner; - wire s_axi_control_WVALID_slr_0_inner; - wire s_axi_control_WREADY_slr_0_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0_inner; - - wire s_axi_control_AWVALID_slr_1_inner; - wire s_axi_control_AWREADY_slr_1_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1_inner; - wire s_axi_control_WVALID_slr_1_inner; - wire s_axi_control_WREADY_slr_1_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1_inner; - - wire s_axi_control_AWVALID_slr_2_inner; - wire s_axi_control_AWREADY_slr_2_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2_inner; - wire s_axi_control_WVALID_slr_2_inner; - wire s_axi_control_WREADY_slr_2_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2_inner; - - // broadcast the AW channel - assign s_axi_control_AWADDR_slr_0_inner = s_axi_control_AWADDR; - assign s_axi_control_AWADDR_slr_1_inner = s_axi_control_AWADDR; - assign s_axi_control_AWADDR_slr_2_inner = s_axi_control_AWADDR; - - assign s_axi_control_AWVALID_slr_0_inner = s_axi_control_AWVALID; - assign s_axi_control_AWVALID_slr_1_inner = s_axi_control_AWVALID; - assign s_axi_control_AWVALID_slr_2_inner = s_axi_control_AWVALID; - - assign s_axi_control_AWREADY = s_axi_control_AWREADY_slr_0_inner & - s_axi_control_AWREADY_slr_1_inner & - s_axi_control_AWREADY_slr_2_inner; - - // broadcast the W channel - assign s_axi_control_WDATA_slr_0_inner = s_axi_control_WDATA; - assign s_axi_control_WDATA_slr_1_inner = s_axi_control_WDATA; - assign s_axi_control_WDATA_slr_2_inner = s_axi_control_WDATA; - - assign s_axi_control_WSTRB_slr_0_inner = s_axi_control_WSTRB; - assign s_axi_control_WSTRB_slr_1_inner = s_axi_control_WSTRB; - assign s_axi_control_WSTRB_slr_2_inner = s_axi_control_WSTRB; - - assign s_axi_control_WVALID_slr_0_inner = s_axi_control_WVALID; - assign s_axi_control_WVALID_slr_1_inner = s_axi_control_WVALID; - assign s_axi_control_WVALID_slr_2_inner = s_axi_control_WVALID; - - assign s_axi_control_WREADY = s_axi_control_WREADY_slr_0_inner & - s_axi_control_WREADY_slr_1_inner & - s_axi_control_WREADY_slr_2_inner; - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_0 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_0_inner), - .if_full_n (s_axi_control_AWREADY_slr_0_inner), - .if_write (s_axi_control_AWVALID_slr_0_inner), - - .if_dout (s_axi_control_AWADDR_slr_0), - .if_empty_n (s_axi_control_AWVALID_slr_0), - .if_read (s_axi_control_AWREADY_slr_0) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_0 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_0_inner, s_axi_control_WSTRB_slr_0_inner}), - .if_full_n (s_axi_control_WREADY_slr_0_inner), - .if_write (s_axi_control_WVALID_slr_0_inner), - - .if_dout ({s_axi_control_WDATA_slr_0, s_axi_control_WSTRB_slr_0}), - .if_empty_n (s_axi_control_WVALID_slr_0), - .if_read (s_axi_control_WREADY_slr_0) - ); - - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_1 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_1_inner), - .if_full_n (s_axi_control_AWREADY_slr_1_inner), - .if_write (s_axi_control_AWVALID_slr_1_inner), - - .if_dout (s_axi_control_AWADDR_slr_1), - .if_empty_n (s_axi_control_AWVALID_slr_1), - .if_read (s_axi_control_AWREADY_slr_1) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_1 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_1_inner, s_axi_control_WSTRB_slr_1_inner}), - .if_full_n (s_axi_control_WREADY_slr_1_inner), - .if_write (s_axi_control_WVALID_slr_1_inner), - - .if_dout ({s_axi_control_WDATA_slr_1, s_axi_control_WSTRB_slr_1}), - .if_empty_n (s_axi_control_WVALID_slr_1), - .if_read (s_axi_control_WREADY_slr_1) - ); - - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_2 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_2_inner), - .if_full_n (s_axi_control_AWREADY_slr_2_inner), - .if_write (s_axi_control_AWVALID_slr_2_inner), - - .if_dout (s_axi_control_AWADDR_slr_2), - .if_empty_n (s_axi_control_AWVALID_slr_2), - .if_read (s_axi_control_AWREADY_slr_2) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_2 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_2_inner, s_axi_control_WSTRB_slr_2_inner}), - .if_full_n (s_axi_control_WREADY_slr_2_inner), - .if_write (s_axi_control_WVALID_slr_2_inner), - - .if_dout ({s_axi_control_WDATA_slr_2, s_axi_control_WSTRB_slr_2}), - .if_empty_n (s_axi_control_WVALID_slr_2), - .if_read (s_axi_control_WREADY_slr_2) - ); - - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/a_axi_write_broadcastor_1_to_4.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/a_axi_write_broadcastor_1_to_4.v deleted file mode 100644 index 055ed0bd..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/a_axi_write_broadcastor_1_to_4.v +++ /dev/null @@ -1,346 +0,0 @@ - -module a_axi_write_broadcastor_1_to_4 ( - ap_clk, - - s_axi_control_AWVALID_slr_0, - s_axi_control_AWREADY_slr_0, - s_axi_control_AWADDR_slr_0, - s_axi_control_WVALID_slr_0, - s_axi_control_WREADY_slr_0, - s_axi_control_WDATA_slr_0, - s_axi_control_WSTRB_slr_0, - s_axi_control_AWVALID_slr_1, - s_axi_control_AWREADY_slr_1, - s_axi_control_AWADDR_slr_1, - s_axi_control_WVALID_slr_1, - s_axi_control_WREADY_slr_1, - s_axi_control_WDATA_slr_1, - s_axi_control_WSTRB_slr_1, - s_axi_control_AWVALID_slr_2, - s_axi_control_AWREADY_slr_2, - s_axi_control_AWADDR_slr_2, - s_axi_control_WVALID_slr_2, - s_axi_control_WREADY_slr_2, - s_axi_control_WDATA_slr_2, - s_axi_control_WSTRB_slr_2, - s_axi_control_AWVALID_slr_3, - s_axi_control_AWREADY_slr_3, - s_axi_control_AWADDR_slr_3, - s_axi_control_WVALID_slr_3, - s_axi_control_WREADY_slr_3, - s_axi_control_WDATA_slr_3, - s_axi_control_WSTRB_slr_3, - s_axi_control_AWVALID, - s_axi_control_AWREADY, - s_axi_control_AWADDR, - s_axi_control_WVALID, - s_axi_control_WREADY, - s_axi_control_WDATA, - s_axi_control_WSTRB -); - parameter C_S_AXI_CONTROL_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_ADDR_WIDTH = 9; - parameter C_S_AXI_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_WSTRB_WIDTH = 32 / 8; - parameter C_S_AXI_WSTRB_WIDTH = 32 / 8; - - input ap_clk; - input s_axi_control_AWVALID; - output s_axi_control_AWREADY; - input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR; - input s_axi_control_WVALID; - output s_axi_control_WREADY; - input [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA; - input [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB; - - output s_axi_control_AWVALID_slr_0; - input s_axi_control_AWREADY_slr_0; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0; - output s_axi_control_WVALID_slr_0; - input s_axi_control_WREADY_slr_0; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0; - - output s_axi_control_AWVALID_slr_1; - input s_axi_control_AWREADY_slr_1; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1; - output s_axi_control_WVALID_slr_1; - input s_axi_control_WREADY_slr_1; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1; - - output s_axi_control_AWVALID_slr_2; - input s_axi_control_AWREADY_slr_2; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2; - output s_axi_control_WVALID_slr_2; - input s_axi_control_WREADY_slr_2; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2; - - output s_axi_control_AWVALID_slr_3; - input s_axi_control_AWREADY_slr_3; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_3; - output s_axi_control_WVALID_slr_3; - input s_axi_control_WREADY_slr_3; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_3; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_3; - - wire s_axi_control_AWVALID_slr_0_inner; - wire s_axi_control_AWREADY_slr_0_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0_inner; - wire s_axi_control_WVALID_slr_0_inner; - wire s_axi_control_WREADY_slr_0_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0_inner; - - wire s_axi_control_AWVALID_slr_1_inner; - wire s_axi_control_AWREADY_slr_1_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1_inner; - wire s_axi_control_WVALID_slr_1_inner; - wire s_axi_control_WREADY_slr_1_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1_inner; - - wire s_axi_control_AWVALID_slr_2_inner; - wire s_axi_control_AWREADY_slr_2_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2_inner; - wire s_axi_control_WVALID_slr_2_inner; - wire s_axi_control_WREADY_slr_2_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2_inner; - - wire s_axi_control_AWVALID_slr_3_inner; - wire s_axi_control_AWREADY_slr_3_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_3_inner; - wire s_axi_control_WVALID_slr_3_inner; - wire s_axi_control_WREADY_slr_3_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_3_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_3_inner; - - // broadcast the AW channel - assign s_axi_control_AWADDR_slr_0_inner = s_axi_control_AWADDR; - assign s_axi_control_AWADDR_slr_1_inner = s_axi_control_AWADDR; - assign s_axi_control_AWADDR_slr_2_inner = s_axi_control_AWADDR; - assign s_axi_control_AWADDR_slr_3_inner = s_axi_control_AWADDR; - - assign s_axi_control_AWVALID_slr_0_inner = s_axi_control_AWVALID; - assign s_axi_control_AWVALID_slr_1_inner = s_axi_control_AWVALID; - assign s_axi_control_AWVALID_slr_2_inner = s_axi_control_AWVALID; - assign s_axi_control_AWVALID_slr_3_inner = s_axi_control_AWVALID; - - assign s_axi_control_AWREADY = s_axi_control_AWREADY_slr_0_inner & - s_axi_control_AWREADY_slr_1_inner & - s_axi_control_AWREADY_slr_2_inner & - s_axi_control_AWREADY_slr_3_inner; - - // broadcast the W channel - assign s_axi_control_WDATA_slr_0_inner = s_axi_control_WDATA; - assign s_axi_control_WDATA_slr_1_inner = s_axi_control_WDATA; - assign s_axi_control_WDATA_slr_2_inner = s_axi_control_WDATA; - assign s_axi_control_WDATA_slr_3_inner = s_axi_control_WDATA; - - assign s_axi_control_WSTRB_slr_0_inner = s_axi_control_WSTRB; - assign s_axi_control_WSTRB_slr_1_inner = s_axi_control_WSTRB; - assign s_axi_control_WSTRB_slr_2_inner = s_axi_control_WSTRB; - assign s_axi_control_WSTRB_slr_3_inner = s_axi_control_WSTRB; - - assign s_axi_control_WVALID_slr_0_inner = s_axi_control_WVALID; - assign s_axi_control_WVALID_slr_1_inner = s_axi_control_WVALID; - assign s_axi_control_WVALID_slr_2_inner = s_axi_control_WVALID; - assign s_axi_control_WVALID_slr_3_inner = s_axi_control_WVALID; - - assign s_axi_control_WREADY = s_axi_control_WREADY_slr_0_inner & - s_axi_control_WREADY_slr_1_inner & - s_axi_control_WREADY_slr_2_inner & - s_axi_control_WREADY_slr_3_inner; - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_0 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_0_inner), - .if_full_n (s_axi_control_AWREADY_slr_0_inner), - .if_write (s_axi_control_AWVALID_slr_0_inner), - - .if_dout (s_axi_control_AWADDR_slr_0), - .if_empty_n (s_axi_control_AWVALID_slr_0), - .if_read (s_axi_control_AWREADY_slr_0) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_0 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_0_inner, s_axi_control_WSTRB_slr_0_inner}), - .if_full_n (s_axi_control_WREADY_slr_0_inner), - .if_write (s_axi_control_WVALID_slr_0_inner), - - .if_dout ({s_axi_control_WDATA_slr_0, s_axi_control_WSTRB_slr_0}), - .if_empty_n (s_axi_control_WVALID_slr_0), - .if_read (s_axi_control_WREADY_slr_0) - ); - - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_1 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_1_inner), - .if_full_n (s_axi_control_AWREADY_slr_1_inner), - .if_write (s_axi_control_AWVALID_slr_1_inner), - - .if_dout (s_axi_control_AWADDR_slr_1), - .if_empty_n (s_axi_control_AWVALID_slr_1), - .if_read (s_axi_control_AWREADY_slr_1) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_1 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_1_inner, s_axi_control_WSTRB_slr_1_inner}), - .if_full_n (s_axi_control_WREADY_slr_1_inner), - .if_write (s_axi_control_WVALID_slr_1_inner), - - .if_dout ({s_axi_control_WDATA_slr_1, s_axi_control_WSTRB_slr_1}), - .if_empty_n (s_axi_control_WVALID_slr_1), - .if_read (s_axi_control_WREADY_slr_1) - ); - - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_2 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_2_inner), - .if_full_n (s_axi_control_AWREADY_slr_2_inner), - .if_write (s_axi_control_AWVALID_slr_2_inner), - - .if_dout (s_axi_control_AWADDR_slr_2), - .if_empty_n (s_axi_control_AWVALID_slr_2), - .if_read (s_axi_control_AWREADY_slr_2) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_2 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_2_inner, s_axi_control_WSTRB_slr_2_inner}), - .if_full_n (s_axi_control_WREADY_slr_2_inner), - .if_write (s_axi_control_WVALID_slr_2_inner), - - .if_dout ({s_axi_control_WDATA_slr_2, s_axi_control_WSTRB_slr_2}), - .if_empty_n (s_axi_control_WVALID_slr_2), - .if_read (s_axi_control_WREADY_slr_2) - ); - - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_3 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_3_inner), - .if_full_n (s_axi_control_AWREADY_slr_3_inner), - .if_write (s_axi_control_AWVALID_slr_3_inner), - - .if_dout (s_axi_control_AWADDR_slr_3), - .if_empty_n (s_axi_control_AWVALID_slr_3), - .if_read (s_axi_control_AWREADY_slr_3) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_3 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_3_inner, s_axi_control_WSTRB_slr_3_inner}), - .if_full_n (s_axi_control_WREADY_slr_3_inner), - .if_write (s_axi_control_WVALID_slr_3_inner), - - .if_dout ({s_axi_control_WDATA_slr_3, s_axi_control_WSTRB_slr_3}), - .if_empty_n (s_axi_control_WVALID_slr_3), - .if_read (s_axi_control_WREADY_slr_3) - ); - - - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/arbiter.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/arbiter.v deleted file mode 100644 index cfac70d1..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/arbiter.v +++ /dev/null @@ -1,159 +0,0 @@ -/* - -Copyright (c) 2014-2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Arbiter module - */ -module arbiter # -( - parameter PORTS = 4, - // select round robin arbitration - parameter ARB_TYPE_ROUND_ROBIN = 0, - // blocking arbiter enable - parameter ARB_BLOCK = 0, - // block on acknowledge assert when nonzero, request deassert when 0 - parameter ARB_BLOCK_ACK = 1, - // LSB priority selection - parameter ARB_LSB_HIGH_PRIORITY = 0 -) -( - input wire clk, - input wire rst, - - input wire [PORTS-1:0] request, - input wire [PORTS-1:0] acknowledge, - - output wire [PORTS-1:0] grant, - output wire grant_valid, - output wire [$clog2(PORTS)-1:0] grant_encoded -); - -reg [PORTS-1:0] grant_reg = 0, grant_next; -reg grant_valid_reg = 0, grant_valid_next; -reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next; - -assign grant_valid = grant_valid_reg; -assign grant = grant_reg; -assign grant_encoded = grant_encoded_reg; - -wire request_valid; -wire [$clog2(PORTS)-1:0] request_index; -wire [PORTS-1:0] request_mask; - -priority_encoder #( - .WIDTH(PORTS), - .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY) -) -priority_encoder_inst ( - .input_unencoded(request), - .output_valid(request_valid), - .output_encoded(request_index), - .output_unencoded(request_mask) -); - -reg [PORTS-1:0] mask_reg = 0, mask_next; - -wire masked_request_valid; -wire [$clog2(PORTS)-1:0] masked_request_index; -wire [PORTS-1:0] masked_request_mask; - -priority_encoder #( - .WIDTH(PORTS), - .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY) -) -priority_encoder_masked ( - .input_unencoded(request & mask_reg), - .output_valid(masked_request_valid), - .output_encoded(masked_request_index), - .output_unencoded(masked_request_mask) -); - -always @* begin - grant_next = 0; - grant_valid_next = 0; - grant_encoded_next = 0; - mask_next = mask_reg; - - if (ARB_BLOCK && !ARB_BLOCK_ACK && grant_reg & request) begin - // granted request still asserted; hold it - grant_valid_next = grant_valid_reg; - grant_next = grant_reg; - grant_encoded_next = grant_encoded_reg; - end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && !(grant_reg & acknowledge)) begin - // granted request not yet acknowledged; hold it - grant_valid_next = grant_valid_reg; - grant_next = grant_reg; - grant_encoded_next = grant_encoded_reg; - end else if (request_valid) begin - if (ARB_TYPE_ROUND_ROBIN) begin - if (masked_request_valid) begin - grant_valid_next = 1; - grant_next = masked_request_mask; - grant_encoded_next = masked_request_index; - if (ARB_LSB_HIGH_PRIORITY) begin - mask_next = {PORTS{1'b1}} << (masked_request_index + 1); - end else begin - mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index); - end - end else begin - grant_valid_next = 1; - grant_next = request_mask; - grant_encoded_next = request_index; - if (ARB_LSB_HIGH_PRIORITY) begin - mask_next = {PORTS{1'b1}} << (request_index + 1); - end else begin - mask_next = {PORTS{1'b1}} >> (PORTS - request_index); - end - end - end else begin - grant_valid_next = 1; - grant_next = request_mask; - grant_encoded_next = request_index; - end - end -end - -always @(posedge clk) begin - if (rst) begin - grant_reg <= 0; - grant_valid_reg <= 0; - grant_encoded_reg <= 0; - mask_reg <= 0; - end else begin - grant_reg <= grant_next; - grant_valid_reg <= grant_valid_next; - grant_encoded_reg <= grant_encoded_next; - mask_reg <= mask_next; - end -end - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/async_mmap.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/async_mmap.v deleted file mode 100644 index af1c6118..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/async_mmap.v +++ /dev/null @@ -1,524 +0,0 @@ -`default_nettype none - -module async_mmap #( - parameter BufferSize = 32, - parameter BufferSizeLog = 5, - parameter AddrWidth = 64, - parameter AxiSideAddrWidth = 64, - parameter DataWidth = 512, - parameter DataWidthBytesLog = 6, // must equal log2(DataWidth/8) - parameter WaitTimeWidth = 4, - parameter BurstLenWidth = 8, - // implement the FIFOs for the read channel - // if set to 0: disconnect the data link - parameter EnableReadChannel = 1, - parameter EnableWriteChannel= 1, - // for burst inference - parameter MaxWaitTime = 3, - parameter MaxBurstLen = 15 -) ( - (* RS_CLK *) input wire clk, - (* RS_RST *) input wire rst, // active high - - // base address for the memory region - (* RS_FF = "offset" *) input wire [63:0] offset, - - // axi write addr channel - (* RS_HS = "aw.valid" *) output wire m_axi_AWVALID, - (* RS_HS = "aw.ready" *) input wire m_axi_AWREADY, - (* RS_HS = "aw.data" *) output wire [AxiSideAddrWidth-1:0] m_axi_AWADDR, - (* RS_HS = "aw.data" *) output wire [0:0] m_axi_AWID, - (* RS_HS = "aw.data" *) output wire [7:0] m_axi_AWLEN, - (* RS_HS = "aw.data" *) output wire [2:0] m_axi_AWSIZE, - (* RS_HS = "aw.data" *) output wire [1:0] m_axi_AWBURST, - (* RS_HS = "aw.data" *) output wire [0:0] m_axi_AWLOCK, - (* RS_HS = "aw.data" *) output wire [3:0] m_axi_AWCACHE, - (* RS_HS = "aw.data" *) output wire [2:0] m_axi_AWPROT, - (* RS_HS = "aw.data" *) output wire [3:0] m_axi_AWQOS, - - // axi write data channel - (* RS_HS = "w.valid" *) output wire m_axi_WVALID, - (* RS_HS = "w.ready" *) input wire m_axi_WREADY, - (* RS_HS = "w.data" *) output wire [DataWidth-1:0] m_axi_WDATA, - (* RS_HS = "w.data" *) output wire [DataWidth/8-1:0] m_axi_WSTRB, - (* RS_HS = "w.data" *) output wire m_axi_WLAST, - - // axi write acknowledge channel - (* RS_HS = "b.valid" *) input wire m_axi_BVALID, - (* RS_HS = "b.ready" *) output wire m_axi_BREADY, - (* RS_HS = "b.data" *) input wire [1:0] m_axi_BRESP, - (* RS_HS = "b.data" *) input wire [0:0] m_axi_BID, - - // axi read addr channel - (* RS_HS = "ar.valid" *) output wire m_axi_ARVALID, - (* RS_HS = "ar.ready" *) input wire m_axi_ARREADY, - (* RS_HS = "ar.data" *) output wire [AxiSideAddrWidth-1:0] m_axi_ARADDR, - (* RS_HS = "ar.data" *) output wire [0:0] m_axi_ARID, - (* RS_HS = "ar.data" *) output wire [7:0] m_axi_ARLEN, - (* RS_HS = "ar.data" *) output wire [2:0] m_axi_ARSIZE, - (* RS_HS = "ar.data" *) output wire [1:0] m_axi_ARBURST, - (* RS_HS = "ar.data" *) output wire [0:0] m_axi_ARLOCK, - (* RS_HS = "ar.data" *) output wire [3:0] m_axi_ARCACHE, - (* RS_HS = "ar.data" *) output wire [2:0] m_axi_ARPROT, - (* RS_HS = "ar.data" *) output wire [3:0] m_axi_ARQOS, - - // axi read response channel - (* RS_HS = "r.valid" *) input wire m_axi_RVALID, - (* RS_HS = "r.ready" *) output wire m_axi_RREADY, - (* RS_HS = "r.data" *) input wire [DataWidth-1:0] m_axi_RDATA, - (* RS_HS = "r.data" *) input wire m_axi_RLAST, - (* RS_HS = "r.data" *) input wire [0:0] m_axi_RID, - (* RS_HS = "r.data" *) input wire [1:0] m_axi_RRESP, - - - // push read addr here - (* RS_HS = "read_addr.data" *) input wire [AddrWidth-1:0] read_addr_din, - (* RS_HS = "read_addr.valid" *) input wire read_addr_write, - (* RS_HS = "read_addr.ready" *) output wire read_addr_full_n, - - // pop read resp here - (* RS_HS = "read_data.data" *) output wire [DataWidth-1:0] read_data_dout, - (* RS_HS = "read_data.ready" *) input wire read_data_read, - (* RS_HS = "read_data.valid" *) output wire read_data_empty_n, - - // push write addr and data here - (* RS_HS = "write_addr.data" *) input wire [AddrWidth-1:0] write_addr_din, - (* RS_HS = "write_addr.valid" *) input wire write_addr_write, - (* RS_HS = "write_addr.ready" *) output wire write_addr_full_n, - (* RS_HS = "write_data.data" *) input wire [DataWidth-1:0] write_data_din, - (* RS_HS = "write_data.valid" *) input wire write_data_write, - (* RS_HS = "write_data.ready" *) output wire write_data_full_n, - - // pop write resp here - (* RS_HS = "write_resp.data" *) output wire [7:0] write_resp_dout, - (* RS_HS = "write_resp.ready" *) input wire write_resp_read, - (* RS_HS = "write_resp.valid" *) output wire write_resp_empty_n -); - - // write addr buffer, from user to burst detector - wire [AddrWidth-1:0] write_addr_dout; - wire write_addr_empty_n; - wire write_addr_read; - - relay_station #( - .DATA_WIDTH(AddrWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) write_addr ( - .clk (clk), - .reset(rst), - - // from user - .if_full_n (write_addr_full_n), - .if_write_ce(1'b1), - .if_write (write_addr_write), - .if_din (offset + (write_addr_din << $clog2(DataWidth/8))), - - // to burst detector - .if_empty_n(write_addr_empty_n), - .if_read_ce(1'b1), - .if_read (write_addr_read), - .if_dout (write_addr_dout) - ); - - // burst write addr buffer, from burst detector to axi - wire [BurstLenWidth+AddrWidth-1:0] burst_write_addr_din; - wire burst_write_addr_full_n; - wire burst_write_addr_write; - wire [AddrWidth-1:0] burst_write_addr_dout_addr; - wire [BurstLenWidth-1:0] burst_write_addr_dout_burst_len; - wire burst_write_addr_empty_n; - wire burst_write_addr_read; - - wire [BurstLenWidth-1:0] burst_write_len_din; - wire burst_write_len_full_n; - wire burst_write_len_write; - wire [BurstLenWidth-1:0] burst_write_len_dout; - wire burst_write_len_empty_n; - wire burst_write_len_read; - - wire [BurstLenWidth-1:0] write_req_din; - wire write_req_write; - wire write_req_full_n; - wire [BurstLenWidth-1:0] write_req_dout; - wire write_req_read; - wire write_req_empty_n; - - wire burst_write_last_din; - wire burst_write_last_full_n; - wire burst_write_last_write; - wire burst_write_last_dout; - wire burst_write_last_empty_n; - - detect_burst #( - .AddrWidth (AddrWidth), - .DataWidthBytesLog(DataWidthBytesLog), - .WaitTimeWidth (WaitTimeWidth), - .BurstLenWidth (BurstLenWidth) - ) detect_burst_write ( - .clk(clk), - .rst(rst), - - .max_wait_time(MaxWaitTime[WaitTimeWidth-1:0]), - .max_burst_len(MaxBurstLen[BurstLenWidth-1:0]), - - // input: individual addresses - .addr_dout (write_addr_dout), - .addr_empty_n(write_addr_empty_n), - .addr_read (write_addr_read), - - // output: inferred burst addresses - .addr_din (burst_write_addr_din), - .addr_full_n(burst_write_addr_full_n), - .addr_write (burst_write_addr_write), - - // output: used to generate the "last" signals - .burst_len_0_din (burst_write_len_din), - .burst_len_0_full_n(burst_write_len_full_n), - .burst_len_0_write (burst_write_len_write), - - // output: used to generate write responses - .burst_len_1_din (write_req_din), - .burst_len_1_full_n(write_req_full_n), - .burst_len_1_write (write_req_write) - ); - - relay_station #( - .DATA_WIDTH(BurstLenWidth + AddrWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) burst_write_addr ( - .clk (clk), - .reset(rst), - - // from burst detector - .if_full_n (burst_write_addr_full_n), - .if_write_ce(1'b1), - .if_write (burst_write_addr_write), - .if_din (burst_write_addr_din), - - // to axi - .if_empty_n(burst_write_addr_empty_n), - .if_read_ce(1'b1), - .if_read (burst_write_addr_read), - .if_dout ({burst_write_addr_dout_burst_len, burst_write_addr_dout_addr}) - ); - - relay_station #( - .DATA_WIDTH(BurstLenWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) burst_write_len ( - .clk (clk), - .reset(rst), - - // from burst detector - .if_full_n (burst_write_len_full_n), - .if_write_ce(1'b1), - .if_write (burst_write_len_write), - .if_din (burst_write_len_din), - - // to last generator - .if_empty_n(burst_write_len_empty_n), - .if_read_ce(1'b1), - .if_read (burst_write_len_read), - .if_dout (burst_write_len_dout) - ); - - // generate last signal for W channel - generate_last #( - .BurstLenWidth(BurstLenWidth) - ) generate_last_unit( - .clk(clk), - .rst(rst), - - .burst_len_dout (burst_write_len_dout), - .burst_len_empty_n(burst_write_len_empty_n), - .burst_len_read (burst_write_len_read), - - .last_din (burst_write_last_din), - .last_full_n(burst_write_last_full_n), - .last_write (burst_write_last_write) - ); - - // write req buffer that remembers the burst length of each write transaction - relay_station #( - .DATA_WIDTH(BurstLenWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) write_req ( - .clk (clk), - .reset(rst), - - // from burst detector - .if_full_n (write_req_full_n), - .if_write_ce(1'b1), - .if_write (write_req_write), - .if_din (write_req_din), - - // to write resp buffer - .if_empty_n(write_req_empty_n), - .if_read_ce(1'b1), - .if_read (write_req_read), - .if_dout (write_req_dout) - ); - - // this relay_station should be synchronized with the wr_data relay_station - relay_station #( - .DATA_WIDTH(1), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) burst_write_last ( - .clk (clk), - .reset(rst), - - // from burst detector - .if_full_n (burst_write_last_full_n), - .if_write_ce(1'b1), - .if_write (burst_write_last_write), - .if_din (burst_write_last_din), - - // to axi - .if_empty_n(burst_write_last_empty_n), - .if_read_ce(1'b1), - // deal with when last-relay_station is non-empty while data-relay_station is empty - .if_read (m_axi_WREADY && write_data_empty_n), - .if_dout (burst_write_last_dout) - ); - - // write data buffer - wire [DataWidth-1:0] write_data_dout; - wire write_data_empty_n; - relay_station #( - .DATA_WIDTH(DataWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) write_data ( - .clk (clk), - .reset(rst), - - // from user - .if_full_n (write_data_full_n), - .if_write_ce(1'b1), - .if_write (write_data_write), - .if_din (write_data_din), - - // to axi - .if_empty_n(write_data_empty_n), - .if_read_ce(1'b1), - // deal with when data-relay_station is non empty but last-relay_station is empty - .if_read (m_axi_WREADY && burst_write_last_empty_n), - .if_dout (write_data_dout) - ); - - // write resp buffer - wire [BurstLenWidth-1:0] write_resp_din = write_req_dout; - wire write_resp_write = m_axi_BVALID && write_req_empty_n; - wire write_resp_full_n; - relay_station #( - .DATA_WIDTH(BurstLenWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) write_resp ( - .clk (clk), - .reset(rst), - - // from write req buffer and axi - .if_full_n (write_resp_full_n), - .if_write_ce(1'b1), - .if_write (write_resp_write), - .if_din (write_resp_din), - - // to user - .if_empty_n(write_resp_empty_n), - .if_read_ce(1'b1), - .if_read (write_resp_read), - .if_dout (write_resp_dout) - ); - - // AW channel - assign burst_write_addr_read = m_axi_AWREADY; - assign m_axi_AWVALID = burst_write_addr_empty_n; - assign m_axi_AWADDR = {{(AxiSideAddrWidth - AddrWidth){1'b0}}, burst_write_addr_dout_addr}; - assign m_axi_AWID = 0; - assign m_axi_AWLEN = burst_write_addr_dout_burst_len; - assign m_axi_AWSIZE = DataWidthBytesLog; - assign m_axi_AWBURST = 1; // INCR mode - assign m_axi_AWLOCK = 0; // Xilinx only supports 0 - assign m_axi_AWCACHE = 4'b0011; // Xilinx only supports 4'b0011 - assign m_axi_AWPROT = 0; - assign m_axi_AWQOS = 0; - - // W channel - assign m_axi_WVALID = write_data_empty_n && burst_write_last_empty_n; - assign m_axi_WDATA = write_data_dout; - assign m_axi_WSTRB = {(DataWidth/8){1'b1}}; // assume every bit is valid - assign m_axi_WLAST = burst_write_last_dout; - - // B channel - assign m_axi_BREADY = write_resp_full_n && write_req_empty_n; - assign write_req_read = write_resp_full_n && m_axi_BVALID; - - // read addr buffer, from user to burst detector - wire [AddrWidth-1:0] read_addr_dout; - wire read_addr_empty_n; - wire read_addr_read; - - relay_station #( - .DATA_WIDTH(AddrWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableReadChannel) - ) read_addr ( - .clk (clk), - .reset(rst), - - // from user - .if_full_n (read_addr_full_n), - .if_write_ce(1'b1), - .if_write (read_addr_write), - .if_din (offset + (read_addr_din << $clog2(DataWidth/8))), - - // to axi - .if_empty_n(read_addr_empty_n), - .if_read_ce(1'b1), - .if_read (read_addr_read), - .if_dout (read_addr_dout) - ); - - wire [BurstLenWidth+AddrWidth-1:0] burst_read_addr_din; - wire burst_read_addr_full_n; - wire burst_read_addr_write; - wire [AddrWidth-1:0] burst_read_addr_dout_addr; - wire [BurstLenWidth-1:0] burst_read_addr_dout_burst_len; - wire burst_read_addr_empty_n; - wire burst_read_addr_read; - - relay_station #( - .DATA_WIDTH(BurstLenWidth + AddrWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableReadChannel) - ) burst_read_addr ( - .clk (clk), - .reset(rst), - - // from burst detector - .if_full_n (burst_read_addr_full_n), - .if_write_ce(1'b1), - .if_write (burst_read_addr_write), - .if_din (burst_read_addr_din), - - // to axi - .if_empty_n(burst_read_addr_empty_n), - .if_read_ce(1'b1), - .if_read (burst_read_addr_read), - .if_dout ({burst_read_addr_dout_burst_len, burst_read_addr_dout_addr}) - ); - - detect_burst #( - .AddrWidth (AddrWidth), - .DataWidthBytesLog(DataWidthBytesLog), - .WaitTimeWidth (WaitTimeWidth), - .BurstLenWidth (BurstLenWidth) - ) detect_burst_read ( - .clk(clk), - .rst(rst), - - .max_wait_time(MaxWaitTime[WaitTimeWidth-1:0]), - .max_burst_len(MaxBurstLen[BurstLenWidth-1:0]), - - // input: individual addresses - .addr_dout (read_addr_dout), - .addr_empty_n(read_addr_empty_n), - .addr_read (read_addr_read), - - // output: inferred burst addresses - .addr_din (burst_read_addr_din), - .addr_full_n(burst_read_addr_full_n), - .addr_write (burst_read_addr_write), - - // output: used to generate the "last" signals, unused - .burst_len_0_din (), - .burst_len_0_full_n(1'b1), - .burst_len_0_write (), - - // output: used to generate write responses, unused - .burst_len_1_din (), - .burst_len_1_full_n(1'b1), - .burst_len_1_write () - ); - - // read resp buffer - wire [DataWidth-1:0] read_data_din; - wire read_data_write; - wire read_data_full_n; - relay_station #( - .DATA_WIDTH(DataWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableReadChannel) - ) read_data ( - .clk (clk), - .reset(rst), - - // from axi - .if_full_n (read_data_full_n), - .if_write_ce(1'b1), - .if_write (read_data_write), - .if_din (read_data_din), - - // to user - .if_empty_n(read_data_empty_n), - .if_read_ce(1'b1), - .if_read (read_data_read), - .if_dout (read_data_dout) - ); - - // AR channel - assign burst_read_addr_read = m_axi_ARREADY; - assign m_axi_ARVALID = burst_read_addr_empty_n; - assign m_axi_ARADDR = {{(AxiSideAddrWidth - AddrWidth){1'b0}}, burst_read_addr_dout_addr}; - assign m_axi_ARID = 0; - assign m_axi_ARLEN = burst_read_addr_dout_burst_len; - assign m_axi_ARSIZE = DataWidthBytesLog; - assign m_axi_ARBURST = 1; // INCR mode - assign m_axi_ARLOCK = 0; // Xilinx only supports 0 - assign m_axi_ARCACHE = 4'b0011; // Xilinx only supports 4'b0011 - assign m_axi_ARPROT = 0; - assign m_axi_ARQOS = 0; - - // R channel - assign m_axi_RREADY = read_data_full_n; - assign read_data_write = m_axi_RVALID; - assign read_data_din = m_axi_RDATA; - - // unused input signals - wire _unused = &{1'b0, - m_axi_BRESP, - m_axi_BID, - m_axi_RLAST, - m_axi_RID, - m_axi_RRESP, - 1'b0}; - -endmodule // async_mmap - -`default_nettype wire diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar.v deleted file mode 100644 index 991d4540..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar.v +++ /dev/null @@ -1,391 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 crossbar - */ -module axi_crossbar # -( - // Number of AXI inputs (slave interfaces) - parameter S_COUNT = 4, - // Number of AXI outputs (master interfaces) - parameter M_COUNT = 4, - // Width of data bus in bits - parameter DATA_WIDTH = 32, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // Width of wstrb (width of data bus in words) - parameter STRB_WIDTH = (DATA_WIDTH/8), - // Input ID field width (from AXI masters) - parameter S_ID_WIDTH = 8, - // Output ID field width (towards AXI slaves) - // Additional bits required for response routing - parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), - // Propagate awuser signal - parameter AWUSER_ENABLE = 0, - // Width of awuser signal - parameter AWUSER_WIDTH = 1, - // Propagate wuser signal - parameter WUSER_ENABLE = 0, - // Width of wuser signal - parameter WUSER_WIDTH = 1, - // Propagate buser signal - parameter BUSER_ENABLE = 0, - // Width of buser signal - parameter BUSER_WIDTH = 1, - // Propagate aruser signal - parameter ARUSER_ENABLE = 0, - // Width of aruser signal - parameter ARUSER_WIDTH = 1, - // Propagate ruser signal - parameter RUSER_ENABLE = 0, - // Width of ruser signal - parameter RUSER_WIDTH = 1, - // Number of concurrent unique IDs for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_THREADS = {S_COUNT{32'd2}}, - // Number of concurrent operations for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_ACCEPT = {S_COUNT{32'd16}}, - // Number of regions per master interface - parameter M_REGIONS = 1, - // Master interface base addresses - // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits - // set to zero for default addressing based on M_ADDR_WIDTH - parameter M_BASE_ADDR = 0, - // Master interface address widths - // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits - parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}}, - // Read connections between interfaces - // M_COUNT concatenated fields of S_COUNT bits - parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}}, - // Write connections between interfaces - // M_COUNT concatenated fields of S_COUNT bits - parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}}, - // Number of concurrent operations for each master interface - // M_COUNT concatenated fields of 32 bits - parameter M_ISSUE = {M_COUNT{32'd4}}, - // Secure master (fail operations based on awprot/arprot) - // M_COUNT bits - parameter M_SECURE = {M_COUNT{1'b0}}, - // Slave interface AW channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_AW_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface W channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_W_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface B channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_B_REG_TYPE = {S_COUNT{2'd1}}, - // Slave interface AR channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_AR_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface R channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_R_REG_TYPE = {S_COUNT{2'd2}}, - // Master interface AW channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, - // Master interface W channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, - // Master interface B channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_B_REG_TYPE = {M_COUNT{2'd0}}, - // Master interface AR channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, - // Master interface R channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_R_REG_TYPE = {M_COUNT{2'd0}} -) -( - input wire clk, - input wire rst, - - /* - * AXI slave interfaces - */ - input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_awid, - input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr, - input wire [S_COUNT*8-1:0] s_axi_awlen, - input wire [S_COUNT*3-1:0] s_axi_awsize, - input wire [S_COUNT*2-1:0] s_axi_awburst, - input wire [S_COUNT-1:0] s_axi_awlock, - input wire [S_COUNT*4-1:0] s_axi_awcache, - input wire [S_COUNT*3-1:0] s_axi_awprot, - input wire [S_COUNT*4-1:0] s_axi_awqos, - input wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser, - input wire [S_COUNT-1:0] s_axi_awvalid, - output wire [S_COUNT-1:0] s_axi_awready, - input wire [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata, - input wire [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb, - input wire [S_COUNT-1:0] s_axi_wlast, - input wire [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser, - input wire [S_COUNT-1:0] s_axi_wvalid, - output wire [S_COUNT-1:0] s_axi_wready, - output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_bid, - output wire [S_COUNT*2-1:0] s_axi_bresp, - output wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser, - output wire [S_COUNT-1:0] s_axi_bvalid, - input wire [S_COUNT-1:0] s_axi_bready, - input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_arid, - input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr, - input wire [S_COUNT*8-1:0] s_axi_arlen, - input wire [S_COUNT*3-1:0] s_axi_arsize, - input wire [S_COUNT*2-1:0] s_axi_arburst, - input wire [S_COUNT-1:0] s_axi_arlock, - input wire [S_COUNT*4-1:0] s_axi_arcache, - input wire [S_COUNT*3-1:0] s_axi_arprot, - input wire [S_COUNT*4-1:0] s_axi_arqos, - input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser, - input wire [S_COUNT-1:0] s_axi_arvalid, - output wire [S_COUNT-1:0] s_axi_arready, - output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_rid, - output wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata, - output wire [S_COUNT*2-1:0] s_axi_rresp, - output wire [S_COUNT-1:0] s_axi_rlast, - output wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser, - output wire [S_COUNT-1:0] s_axi_rvalid, - input wire [S_COUNT-1:0] s_axi_rready, - - /* - * AXI master interfaces - */ - output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_awid, - output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [M_COUNT*8-1:0] m_axi_awlen, - output wire [M_COUNT*3-1:0] m_axi_awsize, - output wire [M_COUNT*2-1:0] m_axi_awburst, - output wire [M_COUNT-1:0] m_axi_awlock, - output wire [M_COUNT*4-1:0] m_axi_awcache, - output wire [M_COUNT*3-1:0] m_axi_awprot, - output wire [M_COUNT*4-1:0] m_axi_awqos, - output wire [M_COUNT*4-1:0] m_axi_awregion, - output wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser, - output wire [M_COUNT-1:0] m_axi_awvalid, - input wire [M_COUNT-1:0] m_axi_awready, - output wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata, - output wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb, - output wire [M_COUNT-1:0] m_axi_wlast, - output wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser, - output wire [M_COUNT-1:0] m_axi_wvalid, - input wire [M_COUNT-1:0] m_axi_wready, - input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_bid, - input wire [M_COUNT*2-1:0] m_axi_bresp, - input wire [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser, - input wire [M_COUNT-1:0] m_axi_bvalid, - output wire [M_COUNT-1:0] m_axi_bready, - output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_arid, - output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr, - output wire [M_COUNT*8-1:0] m_axi_arlen, - output wire [M_COUNT*3-1:0] m_axi_arsize, - output wire [M_COUNT*2-1:0] m_axi_arburst, - output wire [M_COUNT-1:0] m_axi_arlock, - output wire [M_COUNT*4-1:0] m_axi_arcache, - output wire [M_COUNT*3-1:0] m_axi_arprot, - output wire [M_COUNT*4-1:0] m_axi_arqos, - output wire [M_COUNT*4-1:0] m_axi_arregion, - output wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser, - output wire [M_COUNT-1:0] m_axi_arvalid, - input wire [M_COUNT-1:0] m_axi_arready, - input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_rid, - input wire [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata, - input wire [M_COUNT*2-1:0] m_axi_rresp, - input wire [M_COUNT-1:0] m_axi_rlast, - input wire [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser, - input wire [M_COUNT-1:0] m_axi_rvalid, - output wire [M_COUNT-1:0] m_axi_rready -); - -axi_crossbar_wr #( - .S_COUNT(S_COUNT), - .M_COUNT(M_COUNT), - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .S_ID_WIDTH(S_ID_WIDTH), - .M_ID_WIDTH(M_ID_WIDTH), - .AWUSER_ENABLE(AWUSER_ENABLE), - .AWUSER_WIDTH(AWUSER_WIDTH), - .WUSER_ENABLE(WUSER_ENABLE), - .WUSER_WIDTH(WUSER_WIDTH), - .BUSER_ENABLE(BUSER_ENABLE), - .BUSER_WIDTH(BUSER_WIDTH), - .S_THREADS(S_THREADS), - .S_ACCEPT(S_ACCEPT), - .M_REGIONS(M_REGIONS), - .M_BASE_ADDR(M_BASE_ADDR), - .M_ADDR_WIDTH(M_ADDR_WIDTH), - .M_CONNECT(M_CONNECT_WRITE), - .M_ISSUE(M_ISSUE), - .M_SECURE(M_SECURE), - .S_AW_REG_TYPE(S_AW_REG_TYPE), - .S_W_REG_TYPE (S_W_REG_TYPE), - .S_B_REG_TYPE (S_B_REG_TYPE) -) -axi_crossbar_wr_inst ( - .clk(clk), - .rst(rst), - - /* - * AXI slave interfaces - */ - .s_axi_awid(s_axi_awid), - .s_axi_awaddr(s_axi_awaddr), - .s_axi_awlen(s_axi_awlen), - .s_axi_awsize(s_axi_awsize), - .s_axi_awburst(s_axi_awburst), - .s_axi_awlock(s_axi_awlock), - .s_axi_awcache(s_axi_awcache), - .s_axi_awprot(s_axi_awprot), - .s_axi_awqos(s_axi_awqos), - .s_axi_awuser(s_axi_awuser), - .s_axi_awvalid(s_axi_awvalid), - .s_axi_awready(s_axi_awready), - .s_axi_wdata(s_axi_wdata), - .s_axi_wstrb(s_axi_wstrb), - .s_axi_wlast(s_axi_wlast), - .s_axi_wuser(s_axi_wuser), - .s_axi_wvalid(s_axi_wvalid), - .s_axi_wready(s_axi_wready), - .s_axi_bid(s_axi_bid), - .s_axi_bresp(s_axi_bresp), - .s_axi_buser(s_axi_buser), - .s_axi_bvalid(s_axi_bvalid), - .s_axi_bready(s_axi_bready), - - /* - * AXI master interfaces - */ - .m_axi_awid(m_axi_awid), - .m_axi_awaddr(m_axi_awaddr), - .m_axi_awlen(m_axi_awlen), - .m_axi_awsize(m_axi_awsize), - .m_axi_awburst(m_axi_awburst), - .m_axi_awlock(m_axi_awlock), - .m_axi_awcache(m_axi_awcache), - .m_axi_awprot(m_axi_awprot), - .m_axi_awqos(m_axi_awqos), - .m_axi_awregion(m_axi_awregion), - .m_axi_awuser(m_axi_awuser), - .m_axi_awvalid(m_axi_awvalid), - .m_axi_awready(m_axi_awready), - .m_axi_wdata(m_axi_wdata), - .m_axi_wstrb(m_axi_wstrb), - .m_axi_wlast(m_axi_wlast), - .m_axi_wuser(m_axi_wuser), - .m_axi_wvalid(m_axi_wvalid), - .m_axi_wready(m_axi_wready), - .m_axi_bid(m_axi_bid), - .m_axi_bresp(m_axi_bresp), - .m_axi_buser(m_axi_buser), - .m_axi_bvalid(m_axi_bvalid), - .m_axi_bready(m_axi_bready) -); - -axi_crossbar_rd #( - .S_COUNT(S_COUNT), - .M_COUNT(M_COUNT), - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .S_ID_WIDTH(S_ID_WIDTH), - .M_ID_WIDTH(M_ID_WIDTH), - .ARUSER_ENABLE(ARUSER_ENABLE), - .ARUSER_WIDTH(ARUSER_WIDTH), - .RUSER_ENABLE(RUSER_ENABLE), - .RUSER_WIDTH(RUSER_WIDTH), - .S_THREADS(S_THREADS), - .S_ACCEPT(S_ACCEPT), - .M_REGIONS(M_REGIONS), - .M_BASE_ADDR(M_BASE_ADDR), - .M_ADDR_WIDTH(M_ADDR_WIDTH), - .M_CONNECT(M_CONNECT_READ), - .M_ISSUE(M_ISSUE), - .M_SECURE(M_SECURE), - .S_AR_REG_TYPE(S_AR_REG_TYPE), - .S_R_REG_TYPE (S_R_REG_TYPE) -) -axi_crossbar_rd_inst ( - .clk(clk), - .rst(rst), - - /* - * AXI slave interfaces - */ - .s_axi_arid(s_axi_arid), - .s_axi_araddr(s_axi_araddr), - .s_axi_arlen(s_axi_arlen), - .s_axi_arsize(s_axi_arsize), - .s_axi_arburst(s_axi_arburst), - .s_axi_arlock(s_axi_arlock), - .s_axi_arcache(s_axi_arcache), - .s_axi_arprot(s_axi_arprot), - .s_axi_arqos(s_axi_arqos), - .s_axi_aruser(s_axi_aruser), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_arready(s_axi_arready), - .s_axi_rid(s_axi_rid), - .s_axi_rdata(s_axi_rdata), - .s_axi_rresp(s_axi_rresp), - .s_axi_rlast(s_axi_rlast), - .s_axi_ruser(s_axi_ruser), - .s_axi_rvalid(s_axi_rvalid), - .s_axi_rready(s_axi_rready), - - /* - * AXI master interfaces - */ - .m_axi_arid(m_axi_arid), - .m_axi_araddr(m_axi_araddr), - .m_axi_arlen(m_axi_arlen), - .m_axi_arsize(m_axi_arsize), - .m_axi_arburst(m_axi_arburst), - .m_axi_arlock(m_axi_arlock), - .m_axi_arcache(m_axi_arcache), - .m_axi_arprot(m_axi_arprot), - .m_axi_arqos(m_axi_arqos), - .m_axi_arregion(m_axi_arregion), - .m_axi_aruser(m_axi_aruser), - .m_axi_arvalid(m_axi_arvalid), - .m_axi_arready(m_axi_arready), - .m_axi_rid(m_axi_rid), - .m_axi_rdata(m_axi_rdata), - .m_axi_rresp(m_axi_rresp), - .m_axi_rlast(m_axi_rlast), - .m_axi_ruser(m_axi_ruser), - .m_axi_rvalid(m_axi_rvalid), - .m_axi_rready(m_axi_rready) -); - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar_addr.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar_addr.v deleted file mode 100644 index 7b784652..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar_addr.v +++ /dev/null @@ -1,418 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 crossbar address decode and admission control - */ -module axi_crossbar_addr # -( - // Slave interface index - parameter S = 0, - // Number of AXI inputs (slave interfaces) - parameter S_COUNT = 4, - // Number of AXI outputs (master interfaces) - parameter M_COUNT = 4, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // ID field width - parameter ID_WIDTH = 8, - // Number of concurrent unique IDs - parameter S_THREADS = 32'd2, - // Number of concurrent operations - parameter S_ACCEPT = 32'd16, - // Number of regions per master interface - parameter M_REGIONS = 1, - // Master interface base addresses - // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits - // set to zero for default addressing based on M_ADDR_WIDTH - parameter M_BASE_ADDR = 0, - // Master interface address widths - // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits - parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}}, - // Connections between interfaces - // M_COUNT concatenated fields of S_COUNT bits - parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, - // Secure master (fail operations based on awprot/arprot) - // M_COUNT bits - parameter M_SECURE = {M_COUNT{1'b0}}, - // Enable write command output - parameter WC_OUTPUT = 0 -) -( - input wire clk, - input wire rst, - - /* - * Address input - */ - input wire [ID_WIDTH-1:0] s_axi_aid, - input wire [ADDR_WIDTH-1:0] s_axi_aaddr, - input wire [2:0] s_axi_aprot, - input wire [3:0] s_axi_aqos, - input wire s_axi_avalid, - output wire s_axi_aready, - - /* - * Address output - */ - output wire [3:0] m_axi_aregion, - output wire [$clog2(M_COUNT)-1:0] m_select, - output wire m_axi_avalid, - input wire m_axi_aready, - - /* - * Write command output - */ - output wire [$clog2(M_COUNT)-1:0] m_wc_select, - output wire m_wc_decerr, - output wire m_wc_valid, - input wire m_wc_ready, - - /* - * Reply command output - */ - output wire m_rc_decerr, - output wire m_rc_valid, - input wire m_rc_ready, - - /* - * Completion input - */ - input wire [ID_WIDTH-1:0] s_cpl_id, - input wire s_cpl_valid -); - -parameter CL_S_COUNT = $clog2(S_COUNT); -parameter CL_M_COUNT = $clog2(M_COUNT); - -parameter S_INT_THREADS = S_THREADS > S_ACCEPT ? S_ACCEPT : S_THREADS; -parameter CL_S_INT_THREADS = $clog2(S_INT_THREADS); -parameter CL_S_ACCEPT = $clog2(S_ACCEPT); - -// default address computation -function [M_COUNT*M_REGIONS*ADDR_WIDTH-1:0] calcBaseAddrs(input [31:0] dummy); - integer i; - reg [ADDR_WIDTH-1:0] base; - reg [ADDR_WIDTH-1:0] width; - reg [ADDR_WIDTH-1:0] size; - reg [ADDR_WIDTH-1:0] mask; - begin - calcBaseAddrs = {M_COUNT*M_REGIONS*ADDR_WIDTH{1'b0}}; - base = 0; - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - width = M_ADDR_WIDTH[i*32 +: 32]; - mask = {ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - width); - size = mask + 1; - if (width > 0) begin - if ((base & mask) != 0) begin - base = base + size - (base & mask); // align - end - calcBaseAddrs[i * ADDR_WIDTH +: ADDR_WIDTH] = base; - base = base + size; // increment - end - end - end -endfunction - -parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); - -integer i, j; - -// check configuration -initial begin - if (S_ACCEPT < 1) begin - $error("Error: need at least 1 accept (instance %m)"); - $finish; - end - - if (S_THREADS < 1) begin - $error("Error: need at least 1 thread (instance %m)"); - $finish; - end - - if (S_THREADS > S_ACCEPT) begin - $warning("Warning: requested thread count larger than accept count; limiting thread count to accept count (instance %m)"); - end - - if (M_REGIONS < 1) begin - $error("Error: need at least 1 region (instance %m)"); - $finish; - end - - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin - $error("Error: address width out of range (instance %m)"); - $finish; - end - end - - $display("Addressing configuration for axi_crossbar_addr instance %m"); - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32]) begin - $display("%2d (%2d): %x / %02d -- %x-%x", - i/M_REGIONS, i%M_REGIONS, - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH], - M_ADDR_WIDTH[i*32 +: 32], - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])) - ); - end - end - - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if ((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & (2**M_ADDR_WIDTH[i*32 +: 32]-1)) != 0) begin - $display("Region not aligned:"); - $display("%2d (%2d): %x / %2d -- %x-%x", - i/M_REGIONS, i%M_REGIONS, - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH], - M_ADDR_WIDTH[i*32 +: 32], - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])) - ); - $error("Error: address range not aligned (instance %m)"); - $finish; - end - end - - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - for (j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[j*32 +: 32]) begin - if (((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])))) - && ((M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32])) <= (M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))))) begin - $display("Overlapping regions:"); - $display("%2d (%2d): %x / %2d -- %x-%x", - i/M_REGIONS, i%M_REGIONS, - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH], - M_ADDR_WIDTH[i*32 +: 32], - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])) - ); - $display("%2d (%2d): %x / %2d -- %x-%x", - j/M_REGIONS, j%M_REGIONS, - M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH], - M_ADDR_WIDTH[j*32 +: 32], - M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]), - M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])) - ); - $error("Error: address ranges overlap (instance %m)"); - $finish; - end - end - end - end -end - -localparam [2:0] - STATE_IDLE = 3'd0, - STATE_DECODE = 3'd1; - -reg [2:0] state_reg = STATE_IDLE, state_next; - -reg s_axi_aready_reg = 0, s_axi_aready_next; - -reg [3:0] m_axi_aregion_reg = 4'd0, m_axi_aregion_next; -reg [CL_M_COUNT-1:0] m_select_reg = 0, m_select_next; -reg m_axi_avalid_reg = 1'b0, m_axi_avalid_next; -reg m_decerr_reg = 1'b0, m_decerr_next; -reg m_wc_valid_reg = 1'b0, m_wc_valid_next; -reg m_rc_valid_reg = 1'b0, m_rc_valid_next; - -assign s_axi_aready = s_axi_aready_reg; - -assign m_axi_aregion = m_axi_aregion_reg; -assign m_select = m_select_reg; -assign m_axi_avalid = m_axi_avalid_reg; - -assign m_wc_select = m_select_reg; -assign m_wc_decerr = m_decerr_reg; -assign m_wc_valid = m_wc_valid_reg; - -assign m_rc_decerr = m_decerr_reg; -assign m_rc_valid = m_rc_valid_reg; - -reg match; -reg trans_start; -reg trans_complete; - -reg [$clog2(S_ACCEPT+1)-1:0] trans_count_reg = 0; -wire trans_limit = trans_count_reg >= S_ACCEPT && !trans_complete; - -// transfer ID thread tracking -reg [ID_WIDTH-1:0] thread_id_reg[S_INT_THREADS-1:0]; -reg [CL_M_COUNT-1:0] thread_m_reg[S_INT_THREADS-1:0]; -reg [3:0] thread_region_reg[S_INT_THREADS-1:0]; -reg [$clog2(S_ACCEPT+1)-1:0] thread_count_reg[S_INT_THREADS-1:0]; - -wire [S_INT_THREADS-1:0] thread_active; -wire [S_INT_THREADS-1:0] thread_match; -wire [S_INT_THREADS-1:0] thread_match_dest; -wire [S_INT_THREADS-1:0] thread_cpl_match; -wire [S_INT_THREADS-1:0] thread_trans_start; -wire [S_INT_THREADS-1:0] thread_trans_complete; - -generate - genvar n; - - for (n = 0; n < S_INT_THREADS; n = n + 1) begin - initial begin - thread_count_reg[n] <= 0; - end - - assign thread_active[n] = thread_count_reg[n] != 0; - assign thread_match[n] = thread_active[n] && thread_id_reg[n] == s_axi_aid; - assign thread_match_dest[n] = thread_match[n] && thread_m_reg[n] == m_select_next && (M_REGIONS < 2 || thread_region_reg[n] == m_axi_aregion_next); - assign thread_cpl_match[n] = thread_active[n] && thread_id_reg[n] == s_cpl_id; - assign thread_trans_start[n] = (thread_match[n] || (!thread_active[n] && !thread_match && !(thread_trans_start & ({S_INT_THREADS{1'b1}} >> (S_INT_THREADS-n))))) && trans_start; - assign thread_trans_complete[n] = thread_cpl_match[n] && trans_complete; - - always @(posedge clk) begin - if (rst) begin - thread_count_reg[n] <= 0; - end else begin - if (thread_trans_start[n] && !thread_trans_complete[n]) begin - thread_count_reg[n] <= thread_count_reg[n] + 1; - end else if (!thread_trans_start[n] && thread_trans_complete[n]) begin - thread_count_reg[n] <= thread_count_reg[n] - 1; - end - end - - if (thread_trans_start[n]) begin - thread_id_reg[n] <= s_axi_aid; - thread_m_reg[n] <= m_select_next; - thread_region_reg[n] <= m_axi_aregion_next; - end - end - end -endgenerate - -always @* begin - state_next = STATE_IDLE; - - match = 1'b0; - trans_start = 1'b0; - trans_complete = 1'b0; - - s_axi_aready_next = 1'b0; - - m_axi_aregion_next = m_axi_aregion_reg; - m_select_next = m_select_reg; - m_axi_avalid_next = m_axi_avalid_reg && !m_axi_aready; - m_decerr_next = m_decerr_reg; - m_wc_valid_next = m_wc_valid_reg && !m_wc_ready; - m_rc_valid_next = m_rc_valid_reg && !m_rc_ready; - - case (state_reg) - STATE_IDLE: begin - // idle state, store values - s_axi_aready_next = 1'b0; - - if (s_axi_avalid && !s_axi_aready) begin - match = 1'b0; - for (i = 0; i < M_COUNT; i = i + 1) begin - for (j = 0; j < M_REGIONS; j = j + 1) begin - if (M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32] && (!M_SECURE[i] || !s_axi_aprot[1]) && (M_CONNECT & (1 << (S+i*S_COUNT))) && (s_axi_aaddr >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32]) == (M_BASE_ADDR_INT[(i*M_REGIONS+j)*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32])) begin - m_select_next = i; - m_axi_aregion_next = j; - match = 1'b1; - end - end - end - - if (match) begin - // address decode successful - if (!trans_limit && (thread_match_dest || (!(&thread_active) && !thread_match))) begin - // transaction limit not reached - m_axi_avalid_next = 1'b1; - m_decerr_next = 1'b0; - m_wc_valid_next = WC_OUTPUT; - m_rc_valid_next = 1'b0; - trans_start = 1'b1; - state_next = STATE_DECODE; - end else begin - // transaction limit reached; block in idle - state_next = STATE_IDLE; - end - end else begin - // decode error - m_axi_avalid_next = 1'b0; - m_decerr_next = 1'b1; - m_wc_valid_next = WC_OUTPUT; - m_rc_valid_next = 1'b1; - state_next = STATE_DECODE; - end - end else begin - state_next = STATE_IDLE; - end - end - STATE_DECODE: begin - if (!m_axi_avalid_next && (!m_wc_valid_next || !WC_OUTPUT) && !m_rc_valid_next) begin - s_axi_aready_next = 1'b1; - state_next = STATE_IDLE; - end else begin - state_next = STATE_DECODE; - end - end - endcase - - // manage completions - trans_complete = s_cpl_valid; -end - -always @(posedge clk) begin - if (rst) begin - state_reg <= STATE_IDLE; - s_axi_aready_reg <= 1'b0; - m_axi_avalid_reg <= 1'b0; - m_wc_valid_reg <= 1'b0; - m_rc_valid_reg <= 1'b0; - - trans_count_reg <= 0; - end else begin - state_reg <= state_next; - s_axi_aready_reg <= s_axi_aready_next; - m_axi_avalid_reg <= m_axi_avalid_next; - m_wc_valid_reg <= m_wc_valid_next; - m_rc_valid_reg <= m_rc_valid_next; - - if (trans_start && !trans_complete) begin - trans_count_reg <= trans_count_reg + 1; - end else if (!trans_start && trans_complete) begin - trans_count_reg <= trans_count_reg - 1; - end - end - - m_axi_aregion_reg <= m_axi_aregion_next; - m_select_reg <= m_select_next; - m_decerr_reg <= m_decerr_next; -end - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar_rd.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar_rd.v deleted file mode 100644 index 2b1410ac..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar_rd.v +++ /dev/null @@ -1,569 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 crossbar (read) - */ -module axi_crossbar_rd # -( - // Number of AXI inputs (slave interfaces) - parameter S_COUNT = 4, - // Number of AXI outputs (master interfaces) - parameter M_COUNT = 4, - // Width of data bus in bits - parameter DATA_WIDTH = 32, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // Width of wstrb (width of data bus in words) - parameter STRB_WIDTH = (DATA_WIDTH/8), - // Input ID field width (from AXI masters) - parameter S_ID_WIDTH = 8, - // Output ID field width (towards AXI slaves) - // Additional bits required for response routing - parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), - // Propagate aruser signal - parameter ARUSER_ENABLE = 0, - // Width of aruser signal - parameter ARUSER_WIDTH = 1, - // Propagate ruser signal - parameter RUSER_ENABLE = 0, - // Width of ruser signal - parameter RUSER_WIDTH = 1, - // Number of concurrent unique IDs for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_THREADS = {S_COUNT{32'd2}}, - // Number of concurrent operations for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_ACCEPT = {S_COUNT{32'd16}}, - // Number of regions per master interface - parameter M_REGIONS = 1, - // Master interface base addresses - // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits - // set to zero for default addressing based on M_ADDR_WIDTH - parameter M_BASE_ADDR = 0, - // Master interface address widths - // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits - parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}}, - // Read connections between interfaces - // M_COUNT concatenated fields of S_COUNT bits - parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, - // Number of concurrent operations for each master interface - // M_COUNT concatenated fields of 32 bits - parameter M_ISSUE = {M_COUNT{32'd4}}, - // Secure master (fail operations based on awprot/arprot) - // M_COUNT bits - parameter M_SECURE = {M_COUNT{1'b0}}, - // Slave interface AR channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_AR_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface R channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_R_REG_TYPE = {S_COUNT{2'd2}}, - // Master interface AR channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, - // Master interface R channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_R_REG_TYPE = {M_COUNT{2'd0}} -) -( - input wire clk, - input wire rst, - - /* - * AXI slave interfaces - */ - input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_arid, - input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr, - input wire [S_COUNT*8-1:0] s_axi_arlen, - input wire [S_COUNT*3-1:0] s_axi_arsize, - input wire [S_COUNT*2-1:0] s_axi_arburst, - input wire [S_COUNT-1:0] s_axi_arlock, - input wire [S_COUNT*4-1:0] s_axi_arcache, - input wire [S_COUNT*3-1:0] s_axi_arprot, - input wire [S_COUNT*4-1:0] s_axi_arqos, - input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser, - input wire [S_COUNT-1:0] s_axi_arvalid, - output wire [S_COUNT-1:0] s_axi_arready, - output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_rid, - output wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata, - output wire [S_COUNT*2-1:0] s_axi_rresp, - output wire [S_COUNT-1:0] s_axi_rlast, - output wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser, - output wire [S_COUNT-1:0] s_axi_rvalid, - input wire [S_COUNT-1:0] s_axi_rready, - - /* - * AXI master interfaces - */ - output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_arid, - output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr, - output wire [M_COUNT*8-1:0] m_axi_arlen, - output wire [M_COUNT*3-1:0] m_axi_arsize, - output wire [M_COUNT*2-1:0] m_axi_arburst, - output wire [M_COUNT-1:0] m_axi_arlock, - output wire [M_COUNT*4-1:0] m_axi_arcache, - output wire [M_COUNT*3-1:0] m_axi_arprot, - output wire [M_COUNT*4-1:0] m_axi_arqos, - output wire [M_COUNT*4-1:0] m_axi_arregion, - output wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser, - output wire [M_COUNT-1:0] m_axi_arvalid, - input wire [M_COUNT-1:0] m_axi_arready, - input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_rid, - input wire [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata, - input wire [M_COUNT*2-1:0] m_axi_rresp, - input wire [M_COUNT-1:0] m_axi_rlast, - input wire [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser, - input wire [M_COUNT-1:0] m_axi_rvalid, - output wire [M_COUNT-1:0] m_axi_rready -); - -parameter CL_S_COUNT = $clog2(S_COUNT); -parameter CL_M_COUNT = $clog2(M_COUNT); -parameter M_COUNT_P1 = M_COUNT+1; -parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1); - -integer i; - -// check configuration -initial begin - if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin - $error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)"); - $finish; - end - - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin - $error("Error: value out of range (instance %m)"); - $finish; - end - end -end - -wire [S_COUNT*S_ID_WIDTH-1:0] int_s_axi_arid; -wire [S_COUNT*ADDR_WIDTH-1:0] int_s_axi_araddr; -wire [S_COUNT*8-1:0] int_s_axi_arlen; -wire [S_COUNT*3-1:0] int_s_axi_arsize; -wire [S_COUNT*2-1:0] int_s_axi_arburst; -wire [S_COUNT-1:0] int_s_axi_arlock; -wire [S_COUNT*4-1:0] int_s_axi_arcache; -wire [S_COUNT*3-1:0] int_s_axi_arprot; -wire [S_COUNT*4-1:0] int_s_axi_arqos; -wire [S_COUNT*4-1:0] int_s_axi_arregion; -wire [S_COUNT*ARUSER_WIDTH-1:0] int_s_axi_aruser; -wire [S_COUNT-1:0] int_s_axi_arvalid; -wire [S_COUNT-1:0] int_s_axi_arready; - -wire [S_COUNT*M_COUNT-1:0] int_axi_arvalid; -wire [M_COUNT*S_COUNT-1:0] int_axi_arready; - -wire [M_COUNT*M_ID_WIDTH-1:0] int_m_axi_rid; -wire [M_COUNT*DATA_WIDTH-1:0] int_m_axi_rdata; -wire [M_COUNT*2-1:0] int_m_axi_rresp; -wire [M_COUNT-1:0] int_m_axi_rlast; -wire [M_COUNT*RUSER_WIDTH-1:0] int_m_axi_ruser; -wire [M_COUNT-1:0] int_m_axi_rvalid; -wire [M_COUNT-1:0] int_m_axi_rready; - -wire [M_COUNT*S_COUNT-1:0] int_axi_rvalid; -wire [S_COUNT*M_COUNT-1:0] int_axi_rready; - -generate - - genvar m, n; - - for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces - // address decode and admission control - wire [CL_M_COUNT-1:0] a_select; - - wire m_axi_avalid; - wire m_axi_aready; - - wire m_rc_decerr; - wire m_rc_valid; - wire m_rc_ready; - - wire [S_ID_WIDTH-1:0] s_cpl_id; - wire s_cpl_valid; - - axi_crossbar_addr #( - .S(m), - .S_COUNT(S_COUNT), - .M_COUNT(M_COUNT), - .ADDR_WIDTH(ADDR_WIDTH), - .ID_WIDTH(S_ID_WIDTH), - .S_THREADS(S_THREADS[m*32 +: 32]), - .S_ACCEPT(S_ACCEPT[m*32 +: 32]), - .M_REGIONS(M_REGIONS), - .M_BASE_ADDR(M_BASE_ADDR), - .M_ADDR_WIDTH(M_ADDR_WIDTH), - .M_CONNECT(M_CONNECT), - .M_SECURE(M_SECURE), - .WC_OUTPUT(0) - ) - addr_inst ( - .clk(clk), - .rst(rst), - - /* - * Address input - */ - .s_axi_aid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_aaddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .s_axi_aprot(int_s_axi_arprot[m*3 +: 3]), - .s_axi_aqos(int_s_axi_arqos[m*4 +: 4]), - .s_axi_avalid(int_s_axi_arvalid[m]), - .s_axi_aready(int_s_axi_arready[m]), - - /* - * Address output - */ - .m_axi_aregion(int_s_axi_arregion[m*4 +: 4]), - .m_select(a_select), - .m_axi_avalid(m_axi_avalid), - .m_axi_aready(m_axi_aready), - - /* - * Write command output - */ - .m_wc_select(), - .m_wc_decerr(), - .m_wc_valid(), - .m_wc_ready(1'b1), - - /* - * Response command output - */ - .m_rc_decerr(m_rc_decerr), - .m_rc_valid(m_rc_valid), - .m_rc_ready(m_rc_ready), - - /* - * Completion input - */ - .s_cpl_id(s_cpl_id), - .s_cpl_valid(s_cpl_valid) - ); - - assign int_axi_arvalid[m*M_COUNT +: M_COUNT] = m_axi_avalid << a_select; - assign m_axi_aready = int_axi_arready[a_select*S_COUNT+m]; - - // decode error handling - reg [S_ID_WIDTH-1:0] decerr_m_axi_rid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_rid_next; - reg decerr_m_axi_rlast_reg = 1'b0, decerr_m_axi_rlast_next; - reg decerr_m_axi_rvalid_reg = 1'b0, decerr_m_axi_rvalid_next; - wire decerr_m_axi_rready; - - reg [7:0] decerr_len_reg = 8'd0, decerr_len_next; - - assign m_rc_ready = !decerr_m_axi_rvalid_reg; - - always @* begin - decerr_len_next = decerr_len_reg; - decerr_m_axi_rid_next = decerr_m_axi_rid_reg; - decerr_m_axi_rlast_next = decerr_m_axi_rlast_reg; - decerr_m_axi_rvalid_next = decerr_m_axi_rvalid_reg; - - if (decerr_m_axi_rvalid_reg) begin - if (decerr_m_axi_rready) begin - if (decerr_len_reg > 0) begin - decerr_len_next = decerr_len_reg-1; - decerr_m_axi_rlast_next = (decerr_len_next == 0); - decerr_m_axi_rvalid_next = 1'b1; - end else begin - decerr_m_axi_rvalid_next = 1'b0; - end - end - end else if (m_rc_valid && m_rc_ready) begin - decerr_len_next = int_s_axi_arlen[m*8 +: 8]; - decerr_m_axi_rid_next = int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]; - decerr_m_axi_rlast_next = (decerr_len_next == 0); - decerr_m_axi_rvalid_next = 1'b1; - end - end - - always @(posedge clk) begin - if (rst) begin - decerr_m_axi_rvalid_reg <= 1'b0; - end else begin - decerr_m_axi_rvalid_reg <= decerr_m_axi_rvalid_next; - end - - decerr_m_axi_rid_reg <= decerr_m_axi_rid_next; - decerr_m_axi_rlast_reg <= decerr_m_axi_rlast_next; - decerr_len_reg <= decerr_len_next; - end - - // read response arbitration - wire [M_COUNT_P1-1:0] r_request; - wire [M_COUNT_P1-1:0] r_acknowledge; - wire [M_COUNT_P1-1:0] r_grant; - wire r_grant_valid; - wire [CL_M_COUNT_P1-1:0] r_grant_encoded; - - arbiter #( - .PORTS(M_COUNT_P1), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_BLOCK(1), - .ARB_BLOCK_ACK(1), - .ARB_LSB_HIGH_PRIORITY(1) - ) - r_arb_inst ( - .clk(clk), - .rst(rst), - .request(r_request), - .acknowledge(r_acknowledge), - .grant(r_grant), - .grant_valid(r_grant_valid), - .grant_encoded(r_grant_encoded) - ); - - // read response mux - wire [S_ID_WIDTH-1:0] m_axi_rid_mux = {decerr_m_axi_rid_reg, int_m_axi_rid} >> r_grant_encoded*M_ID_WIDTH; - wire [DATA_WIDTH-1:0] m_axi_rdata_mux = {{DATA_WIDTH{1'b0}}, int_m_axi_rdata} >> r_grant_encoded*DATA_WIDTH; - wire [1:0] m_axi_rresp_mux = {2'b11, int_m_axi_rresp} >> r_grant_encoded*2; - wire m_axi_rlast_mux = {decerr_m_axi_rlast_reg, int_m_axi_rlast} >> r_grant_encoded; - wire [RUSER_WIDTH-1:0] m_axi_ruser_mux = {{RUSER_WIDTH{1'b0}}, int_m_axi_ruser} >> r_grant_encoded*RUSER_WIDTH; - wire m_axi_rvalid_mux = ({decerr_m_axi_rvalid_reg, int_m_axi_rvalid} >> r_grant_encoded) & r_grant_valid; - wire m_axi_rready_mux; - - assign int_axi_rready[m*M_COUNT +: M_COUNT] = (r_grant_valid && m_axi_rready_mux) << r_grant_encoded; - assign decerr_m_axi_rready = (r_grant_valid && m_axi_rready_mux) && (r_grant_encoded == M_COUNT_P1-1); - - for (n = 0; n < M_COUNT; n = n + 1) begin - assign r_request[n] = int_axi_rvalid[n*S_COUNT+m] && !r_grant[n]; - assign r_acknowledge[n] = r_grant[n] && int_axi_rvalid[n*S_COUNT+m] && m_axi_rlast_mux && m_axi_rready_mux; - end - - assign r_request[M_COUNT_P1-1] = decerr_m_axi_rvalid_reg && !r_grant[M_COUNT_P1-1]; - assign r_acknowledge[M_COUNT_P1-1] = r_grant[M_COUNT_P1-1] && decerr_m_axi_rvalid_reg && decerr_m_axi_rlast_reg && m_axi_rready_mux; - - assign s_cpl_id = m_axi_rid_mux; - assign s_cpl_valid = m_axi_rvalid_mux && m_axi_rready_mux && m_axi_rlast_mux; - - // S side register - axi_register_rd #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .ID_WIDTH(S_ID_WIDTH), - .ARUSER_ENABLE(ARUSER_ENABLE), - .ARUSER_WIDTH(ARUSER_WIDTH), - .RUSER_ENABLE(RUSER_ENABLE), - .RUSER_WIDTH(RUSER_WIDTH), - .AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]), - .R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2]) - ) - reg_inst ( - .clk(clk), - .rst(rst), - .s_axi_arid(s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_araddr(s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .s_axi_arlen(s_axi_arlen[m*8 +: 8]), - .s_axi_arsize(s_axi_arsize[m*3 +: 3]), - .s_axi_arburst(s_axi_arburst[m*2 +: 2]), - .s_axi_arlock(s_axi_arlock[m]), - .s_axi_arcache(s_axi_arcache[m*4 +: 4]), - .s_axi_arprot(s_axi_arprot[m*3 +: 3]), - .s_axi_arqos(s_axi_arqos[m*4 +: 4]), - .s_axi_arregion(4'd0), - .s_axi_aruser(s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]), - .s_axi_arvalid(s_axi_arvalid[m]), - .s_axi_arready(s_axi_arready[m]), - .s_axi_rid(s_axi_rid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_rdata(s_axi_rdata[m*DATA_WIDTH +: DATA_WIDTH]), - .s_axi_rresp(s_axi_rresp[m*2 +: 2]), - .s_axi_rlast(s_axi_rlast[m]), - .s_axi_ruser(s_axi_ruser[m*RUSER_WIDTH +: RUSER_WIDTH]), - .s_axi_rvalid(s_axi_rvalid[m]), - .s_axi_rready(s_axi_rready[m]), - .m_axi_arid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .m_axi_araddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .m_axi_arlen(int_s_axi_arlen[m*8 +: 8]), - .m_axi_arsize(int_s_axi_arsize[m*3 +: 3]), - .m_axi_arburst(int_s_axi_arburst[m*2 +: 2]), - .m_axi_arlock(int_s_axi_arlock[m]), - .m_axi_arcache(int_s_axi_arcache[m*4 +: 4]), - .m_axi_arprot(int_s_axi_arprot[m*3 +: 3]), - .m_axi_arqos(int_s_axi_arqos[m*4 +: 4]), - .m_axi_arregion(), - .m_axi_aruser(int_s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]), - .m_axi_arvalid(int_s_axi_arvalid[m]), - .m_axi_arready(int_s_axi_arready[m]), - .m_axi_rid(m_axi_rid_mux), - .m_axi_rdata(m_axi_rdata_mux), - .m_axi_rresp(m_axi_rresp_mux), - .m_axi_rlast(m_axi_rlast_mux), - .m_axi_ruser(m_axi_ruser_mux), - .m_axi_rvalid(m_axi_rvalid_mux), - .m_axi_rready(m_axi_rready_mux) - ); - end // s_ifaces - - for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces - // in-flight transaction count - wire trans_start; - wire trans_complete; - reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0; - - wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete; - - always @(posedge clk) begin - if (rst) begin - trans_count_reg <= 0; - end else begin - if (trans_start && !trans_complete) begin - trans_count_reg <= trans_count_reg + 1; - end else if (!trans_start && trans_complete) begin - trans_count_reg <= trans_count_reg - 1; - end - end - end - - // address arbitration - wire [S_COUNT-1:0] a_request; - wire [S_COUNT-1:0] a_acknowledge; - wire [S_COUNT-1:0] a_grant; - wire a_grant_valid; - wire [CL_S_COUNT-1:0] a_grant_encoded; - - arbiter #( - .PORTS(S_COUNT), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_BLOCK(1), - .ARB_BLOCK_ACK(1), - .ARB_LSB_HIGH_PRIORITY(1) - ) - a_arb_inst ( - .clk(clk), - .rst(rst), - .request(a_request), - .acknowledge(a_acknowledge), - .grant(a_grant), - .grant_valid(a_grant_valid), - .grant_encoded(a_grant_encoded) - ); - - // address mux - wire [M_ID_WIDTH-1:0] s_axi_arid_mux = int_s_axi_arid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH); - wire [ADDR_WIDTH-1:0] s_axi_araddr_mux = int_s_axi_araddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH]; - wire [7:0] s_axi_arlen_mux = int_s_axi_arlen[a_grant_encoded*8 +: 8]; - wire [2:0] s_axi_arsize_mux = int_s_axi_arsize[a_grant_encoded*3 +: 3]; - wire [1:0] s_axi_arburst_mux = int_s_axi_arburst[a_grant_encoded*2 +: 2]; - wire s_axi_arlock_mux = int_s_axi_arlock[a_grant_encoded]; - wire [3:0] s_axi_arcache_mux = int_s_axi_arcache[a_grant_encoded*4 +: 4]; - wire [2:0] s_axi_arprot_mux = int_s_axi_arprot[a_grant_encoded*3 +: 3]; - wire [3:0] s_axi_arqos_mux = int_s_axi_arqos[a_grant_encoded*4 +: 4]; - wire [3:0] s_axi_arregion_mux = int_s_axi_arregion[a_grant_encoded*4 +: 4]; - wire [ARUSER_WIDTH-1:0] s_axi_aruser_mux = int_s_axi_aruser[a_grant_encoded*ARUSER_WIDTH +: ARUSER_WIDTH]; - wire s_axi_arvalid_mux = int_axi_arvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid; - wire s_axi_arready_mux; - - assign int_axi_arready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_arready_mux) << a_grant_encoded; - - for (m = 0; m < S_COUNT; m = m + 1) begin - assign a_request[m] = int_axi_arvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit; - assign a_acknowledge[m] = a_grant[m] && int_axi_arvalid[m*M_COUNT+n] && s_axi_arready_mux; - end - - assign trans_start = s_axi_arvalid_mux && s_axi_arready_mux && a_grant_valid; - - // read response forwarding - wire [CL_S_COUNT-1:0] r_select = m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH; - - assign int_axi_rvalid[n*S_COUNT +: S_COUNT] = int_m_axi_rvalid[n] << r_select; - assign int_m_axi_rready[n] = int_axi_rready[r_select*M_COUNT+n]; - - assign trans_complete = int_m_axi_rvalid[n] && int_m_axi_rready[n] && int_m_axi_rlast[n]; - - // M side register - axi_register_rd #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .ID_WIDTH(M_ID_WIDTH), - .ARUSER_ENABLE(ARUSER_ENABLE), - .ARUSER_WIDTH(ARUSER_WIDTH), - .RUSER_ENABLE(RUSER_ENABLE), - .RUSER_WIDTH(RUSER_WIDTH), - .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]), - .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2]) - ) - reg_inst ( - .clk(clk), - .rst(rst), - .s_axi_arid(s_axi_arid_mux), - .s_axi_araddr(s_axi_araddr_mux), - .s_axi_arlen(s_axi_arlen_mux), - .s_axi_arsize(s_axi_arsize_mux), - .s_axi_arburst(s_axi_arburst_mux), - .s_axi_arlock(s_axi_arlock_mux), - .s_axi_arcache(s_axi_arcache_mux), - .s_axi_arprot(s_axi_arprot_mux), - .s_axi_arqos(s_axi_arqos_mux), - .s_axi_arregion(s_axi_arregion_mux), - .s_axi_aruser(s_axi_aruser_mux), - .s_axi_arvalid(s_axi_arvalid_mux), - .s_axi_arready(s_axi_arready_mux), - .s_axi_rid(int_m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .s_axi_rdata(int_m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]), - .s_axi_rresp(int_m_axi_rresp[n*2 +: 2]), - .s_axi_rlast(int_m_axi_rlast[n]), - .s_axi_ruser(int_m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]), - .s_axi_rvalid(int_m_axi_rvalid[n]), - .s_axi_rready(int_m_axi_rready[n]), - .m_axi_arid(m_axi_arid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .m_axi_araddr(m_axi_araddr[n*ADDR_WIDTH +: ADDR_WIDTH]), - .m_axi_arlen(m_axi_arlen[n*8 +: 8]), - .m_axi_arsize(m_axi_arsize[n*3 +: 3]), - .m_axi_arburst(m_axi_arburst[n*2 +: 2]), - .m_axi_arlock(m_axi_arlock[n]), - .m_axi_arcache(m_axi_arcache[n*4 +: 4]), - .m_axi_arprot(m_axi_arprot[n*3 +: 3]), - .m_axi_arqos(m_axi_arqos[n*4 +: 4]), - .m_axi_arregion(m_axi_arregion[n*4 +: 4]), - .m_axi_aruser(m_axi_aruser[n*ARUSER_WIDTH +: ARUSER_WIDTH]), - .m_axi_arvalid(m_axi_arvalid[n]), - .m_axi_arready(m_axi_arready[n]), - .m_axi_rid(m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .m_axi_rdata(m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]), - .m_axi_rresp(m_axi_rresp[n*2 +: 2]), - .m_axi_rlast(m_axi_rlast[n]), - .m_axi_ruser(m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]), - .m_axi_rvalid(m_axi_rvalid[n]), - .m_axi_rready(m_axi_rready[n]) - ); - end // m_ifaces - -endgenerate - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar_wr.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar_wr.v deleted file mode 100644 index 5f556653..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_crossbar_wr.v +++ /dev/null @@ -1,678 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 crossbar (write) - */ -module axi_crossbar_wr # -( - // Number of AXI inputs (slave interfaces) - parameter S_COUNT = 4, - // Number of AXI outputs (master interfaces) - parameter M_COUNT = 4, - // Width of data bus in bits - parameter DATA_WIDTH = 32, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // Width of wstrb (width of data bus in words) - parameter STRB_WIDTH = (DATA_WIDTH/8), - // Input ID field width (from AXI masters) - parameter S_ID_WIDTH = 8, - // Output ID field width (towards AXI slaves) - // Additional bits required for response routing - parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), - // Propagate awuser signal - parameter AWUSER_ENABLE = 0, - // Width of awuser signal - parameter AWUSER_WIDTH = 1, - // Propagate wuser signal - parameter WUSER_ENABLE = 0, - // Width of wuser signal - parameter WUSER_WIDTH = 1, - // Propagate buser signal - parameter BUSER_ENABLE = 0, - // Width of buser signal - parameter BUSER_WIDTH = 1, - // Number of concurrent unique IDs for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_THREADS = {S_COUNT{32'd2}}, - // Number of concurrent operations for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_ACCEPT = {S_COUNT{32'd16}}, - // Number of regions per master interface - parameter M_REGIONS = 1, - // Master interface base addresses - // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits - // set to zero for default addressing based on M_ADDR_WIDTH - parameter M_BASE_ADDR = 0, - // Master interface address widths - // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits - parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}}, - // Write connections between interfaces - // M_COUNT concatenated fields of S_COUNT bits - parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, - // Number of concurrent operations for each master interface - // M_COUNT concatenated fields of 32 bits - parameter M_ISSUE = {M_COUNT{32'd4}}, - // Secure master (fail operations based on awprot/arprot) - // M_COUNT bits - parameter M_SECURE = {M_COUNT{1'b0}}, - // Slave interface AW channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_AW_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface W channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_W_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface B channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_B_REG_TYPE = {S_COUNT{2'd1}}, - // Master interface AW channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, - // Master interface W channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, - // Master interface B channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_B_REG_TYPE = {M_COUNT{2'd0}} -) -( - input wire clk, - input wire rst, - - /* - * AXI slave interfaces - */ - input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_awid, - input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr, - input wire [S_COUNT*8-1:0] s_axi_awlen, - input wire [S_COUNT*3-1:0] s_axi_awsize, - input wire [S_COUNT*2-1:0] s_axi_awburst, - input wire [S_COUNT-1:0] s_axi_awlock, - input wire [S_COUNT*4-1:0] s_axi_awcache, - input wire [S_COUNT*3-1:0] s_axi_awprot, - input wire [S_COUNT*4-1:0] s_axi_awqos, - input wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser, - input wire [S_COUNT-1:0] s_axi_awvalid, - output wire [S_COUNT-1:0] s_axi_awready, - input wire [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata, - input wire [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb, - input wire [S_COUNT-1:0] s_axi_wlast, - input wire [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser, - input wire [S_COUNT-1:0] s_axi_wvalid, - output wire [S_COUNT-1:0] s_axi_wready, - output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_bid, - output wire [S_COUNT*2-1:0] s_axi_bresp, - output wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser, - output wire [S_COUNT-1:0] s_axi_bvalid, - input wire [S_COUNT-1:0] s_axi_bready, - - /* - * AXI master interfaces - */ - output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_awid, - output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [M_COUNT*8-1:0] m_axi_awlen, - output wire [M_COUNT*3-1:0] m_axi_awsize, - output wire [M_COUNT*2-1:0] m_axi_awburst, - output wire [M_COUNT-1:0] m_axi_awlock, - output wire [M_COUNT*4-1:0] m_axi_awcache, - output wire [M_COUNT*3-1:0] m_axi_awprot, - output wire [M_COUNT*4-1:0] m_axi_awqos, - output wire [M_COUNT*4-1:0] m_axi_awregion, - output wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser, - output wire [M_COUNT-1:0] m_axi_awvalid, - input wire [M_COUNT-1:0] m_axi_awready, - output wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata, - output wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb, - output wire [M_COUNT-1:0] m_axi_wlast, - output wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser, - output wire [M_COUNT-1:0] m_axi_wvalid, - input wire [M_COUNT-1:0] m_axi_wready, - input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_bid, - input wire [M_COUNT*2-1:0] m_axi_bresp, - input wire [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser, - input wire [M_COUNT-1:0] m_axi_bvalid, - output wire [M_COUNT-1:0] m_axi_bready -); - -parameter CL_S_COUNT = $clog2(S_COUNT); -parameter CL_M_COUNT = $clog2(M_COUNT); -parameter M_COUNT_P1 = M_COUNT+1; -parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1); - -integer i; - -// check configuration -initial begin - if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin - $error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)"); - $finish; - end - - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin - $error("Error: value out of range (instance %m)"); - $finish; - end - end -end - -wire [S_COUNT*S_ID_WIDTH-1:0] int_s_axi_awid; -wire [S_COUNT*ADDR_WIDTH-1:0] int_s_axi_awaddr; -wire [S_COUNT*8-1:0] int_s_axi_awlen; -wire [S_COUNT*3-1:0] int_s_axi_awsize; -wire [S_COUNT*2-1:0] int_s_axi_awburst; -wire [S_COUNT-1:0] int_s_axi_awlock; -wire [S_COUNT*4-1:0] int_s_axi_awcache; -wire [S_COUNT*3-1:0] int_s_axi_awprot; -wire [S_COUNT*4-1:0] int_s_axi_awqos; -wire [S_COUNT*4-1:0] int_s_axi_awregion; -wire [S_COUNT*AWUSER_WIDTH-1:0] int_s_axi_awuser; -wire [S_COUNT-1:0] int_s_axi_awvalid; -wire [S_COUNT-1:0] int_s_axi_awready; - -wire [S_COUNT*M_COUNT-1:0] int_axi_awvalid; -wire [M_COUNT*S_COUNT-1:0] int_axi_awready; - -wire [S_COUNT*DATA_WIDTH-1:0] int_s_axi_wdata; -wire [S_COUNT*STRB_WIDTH-1:0] int_s_axi_wstrb; -wire [S_COUNT-1:0] int_s_axi_wlast; -wire [S_COUNT*WUSER_WIDTH-1:0] int_s_axi_wuser; -wire [S_COUNT-1:0] int_s_axi_wvalid; -wire [S_COUNT-1:0] int_s_axi_wready; - -wire [S_COUNT*M_COUNT-1:0] int_axi_wvalid; -wire [M_COUNT*S_COUNT-1:0] int_axi_wready; - -wire [M_COUNT*M_ID_WIDTH-1:0] int_m_axi_bid; -wire [M_COUNT*2-1:0] int_m_axi_bresp; -wire [M_COUNT*BUSER_WIDTH-1:0] int_m_axi_buser; -wire [M_COUNT-1:0] int_m_axi_bvalid; -wire [M_COUNT-1:0] int_m_axi_bready; - -wire [M_COUNT*S_COUNT-1:0] int_axi_bvalid; -wire [S_COUNT*M_COUNT-1:0] int_axi_bready; - -generate - - genvar m, n; - - for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces - // address decode and admission control - wire [CL_M_COUNT-1:0] a_select; - - wire m_axi_avalid; - wire m_axi_aready; - - wire [CL_M_COUNT-1:0] m_wc_select; - wire m_wc_decerr; - wire m_wc_valid; - wire m_wc_ready; - - wire m_rc_decerr; - wire m_rc_valid; - wire m_rc_ready; - - wire [S_ID_WIDTH-1:0] s_cpl_id; - wire s_cpl_valid; - - axi_crossbar_addr #( - .S(m), - .S_COUNT(S_COUNT), - .M_COUNT(M_COUNT), - .ADDR_WIDTH(ADDR_WIDTH), - .ID_WIDTH(S_ID_WIDTH), - .S_THREADS(S_THREADS[m*32 +: 32]), - .S_ACCEPT(S_ACCEPT[m*32 +: 32]), - .M_REGIONS(M_REGIONS), - .M_BASE_ADDR(M_BASE_ADDR), - .M_ADDR_WIDTH(M_ADDR_WIDTH), - .M_CONNECT(M_CONNECT), - .M_SECURE(M_SECURE), - .WC_OUTPUT(1) - ) - addr_inst ( - .clk(clk), - .rst(rst), - - /* - * Address input - */ - .s_axi_aid(int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_aaddr(int_s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .s_axi_aprot(int_s_axi_awprot[m*3 +: 3]), - .s_axi_aqos(int_s_axi_awqos[m*4 +: 4]), - .s_axi_avalid(int_s_axi_awvalid[m]), - .s_axi_aready(int_s_axi_awready[m]), - - /* - * Address output - */ - .m_axi_aregion(int_s_axi_awregion[m*4 +: 4]), - .m_select(a_select), - .m_axi_avalid(m_axi_avalid), - .m_axi_aready(m_axi_aready), - - /* - * Write command output - */ - .m_wc_select(m_wc_select), - .m_wc_decerr(m_wc_decerr), - .m_wc_valid(m_wc_valid), - .m_wc_ready(m_wc_ready), - - /* - * Response command output - */ - .m_rc_decerr(m_rc_decerr), - .m_rc_valid(m_rc_valid), - .m_rc_ready(m_rc_ready), - - /* - * Completion input - */ - .s_cpl_id(s_cpl_id), - .s_cpl_valid(s_cpl_valid) - ); - - assign int_axi_awvalid[m*M_COUNT +: M_COUNT] = m_axi_avalid << a_select; - assign m_axi_aready = int_axi_awready[a_select*S_COUNT+m]; - - // write command handling - reg [CL_M_COUNT-1:0] w_select_reg = 0, w_select_next; - reg w_drop_reg = 1'b0, w_drop_next; - reg w_select_valid_reg = 1'b0, w_select_valid_next; - - assign m_wc_ready = !w_select_valid_reg; - - always @* begin - w_select_next = w_select_reg; - w_drop_next = w_drop_reg && !(int_s_axi_wvalid[m] && int_s_axi_wready[m] && int_s_axi_wlast[m]); - w_select_valid_next = w_select_valid_reg && !(int_s_axi_wvalid[m] && int_s_axi_wready[m] && int_s_axi_wlast[m]); - - if (m_wc_valid && !w_select_valid_reg) begin - w_select_next = m_wc_select; - w_drop_next = m_wc_decerr; - w_select_valid_next = m_wc_valid; - end - end - - always @(posedge clk) begin - if (rst) begin - w_select_valid_reg <= 1'b0; - end else begin - w_select_valid_reg <= w_select_valid_next; - end - - w_select_reg <= w_select_next; - w_drop_reg <= w_drop_next; - end - - // write data forwarding - assign int_axi_wvalid[m*M_COUNT +: M_COUNT] = (int_s_axi_wvalid[m] && w_select_valid_reg && !w_drop_reg) << w_select_reg; - assign int_s_axi_wready[m] = int_axi_wready[w_select_reg*S_COUNT+m] || w_drop_reg; - - // decode error handling - reg [S_ID_WIDTH-1:0] decerr_m_axi_bid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_bid_next; - reg decerr_m_axi_bvalid_reg = 1'b0, decerr_m_axi_bvalid_next; - wire decerr_m_axi_bready; - - assign m_rc_ready = !decerr_m_axi_bvalid_reg; - - always @* begin - decerr_m_axi_bid_next = decerr_m_axi_bid_reg; - decerr_m_axi_bvalid_next = decerr_m_axi_bvalid_reg; - - if (decerr_m_axi_bvalid_reg) begin - if (decerr_m_axi_bready) begin - decerr_m_axi_bvalid_next = 1'b0; - end - end else if (m_rc_valid && m_rc_ready) begin - decerr_m_axi_bid_next = int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]; - decerr_m_axi_bvalid_next = 1'b1; - end - end - - always @(posedge clk) begin - if (rst) begin - decerr_m_axi_bvalid_reg <= 1'b0; - end else begin - decerr_m_axi_bvalid_reg <= decerr_m_axi_bvalid_next; - end - - decerr_m_axi_bid_reg <= decerr_m_axi_bid_next; - end - - // write response arbitration - wire [M_COUNT_P1-1:0] b_request; - wire [M_COUNT_P1-1:0] b_acknowledge; - wire [M_COUNT_P1-1:0] b_grant; - wire b_grant_valid; - wire [CL_M_COUNT_P1-1:0] b_grant_encoded; - - arbiter #( - .PORTS(M_COUNT_P1), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_BLOCK(1), - .ARB_BLOCK_ACK(1), - .ARB_LSB_HIGH_PRIORITY(1) - ) - b_arb_inst ( - .clk(clk), - .rst(rst), - .request(b_request), - .acknowledge(b_acknowledge), - .grant(b_grant), - .grant_valid(b_grant_valid), - .grant_encoded(b_grant_encoded) - ); - - // write response mux - wire [S_ID_WIDTH-1:0] m_axi_bid_mux = {decerr_m_axi_bid_reg, int_m_axi_bid} >> b_grant_encoded*M_ID_WIDTH; - wire [1:0] m_axi_bresp_mux = {2'b11, int_m_axi_bresp} >> b_grant_encoded*2; - wire [BUSER_WIDTH-1:0] m_axi_buser_mux = {{BUSER_WIDTH{1'b0}}, int_m_axi_buser} >> b_grant_encoded*BUSER_WIDTH; - wire m_axi_bvalid_mux = ({decerr_m_axi_bvalid_reg, int_m_axi_bvalid} >> b_grant_encoded) & b_grant_valid; - wire m_axi_bready_mux; - - assign int_axi_bready[m*M_COUNT +: M_COUNT] = (b_grant_valid && m_axi_bready_mux) << b_grant_encoded; - assign decerr_m_axi_bready = (b_grant_valid && m_axi_bready_mux) && (b_grant_encoded == M_COUNT_P1-1); - - for (n = 0; n < M_COUNT; n = n + 1) begin - assign b_request[n] = int_axi_bvalid[n*S_COUNT+m] && !b_grant[n]; - assign b_acknowledge[n] = b_grant[n] && int_axi_bvalid[n*S_COUNT+m] && m_axi_bready_mux; - end - - assign b_request[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1]; - assign b_acknowledge[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && m_axi_bready_mux; - - assign s_cpl_id = m_axi_bid_mux; - assign s_cpl_valid = m_axi_bvalid_mux && m_axi_bready_mux; - - // S side register - axi_register_wr #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .ID_WIDTH(S_ID_WIDTH), - .AWUSER_ENABLE(AWUSER_ENABLE), - .AWUSER_WIDTH(AWUSER_WIDTH), - .WUSER_ENABLE(WUSER_ENABLE), - .WUSER_WIDTH(WUSER_WIDTH), - .BUSER_ENABLE(BUSER_ENABLE), - .BUSER_WIDTH(BUSER_WIDTH), - .AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]), - .W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]), - .B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2]) - ) - reg_inst ( - .clk(clk), - .rst(rst), - .s_axi_awid(s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_awaddr(s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .s_axi_awlen(s_axi_awlen[m*8 +: 8]), - .s_axi_awsize(s_axi_awsize[m*3 +: 3]), - .s_axi_awburst(s_axi_awburst[m*2 +: 2]), - .s_axi_awlock(s_axi_awlock[m]), - .s_axi_awcache(s_axi_awcache[m*4 +: 4]), - .s_axi_awprot(s_axi_awprot[m*3 +: 3]), - .s_axi_awqos(s_axi_awqos[m*4 +: 4]), - .s_axi_awregion(4'd0), - .s_axi_awuser(s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]), - .s_axi_awvalid(s_axi_awvalid[m]), - .s_axi_awready(s_axi_awready[m]), - .s_axi_wdata(s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]), - .s_axi_wstrb(s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]), - .s_axi_wlast(s_axi_wlast[m]), - .s_axi_wuser(s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]), - .s_axi_wvalid(s_axi_wvalid[m]), - .s_axi_wready(s_axi_wready[m]), - .s_axi_bid(s_axi_bid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_bresp(s_axi_bresp[m*2 +: 2]), - .s_axi_buser(s_axi_buser[m*BUSER_WIDTH +: BUSER_WIDTH]), - .s_axi_bvalid(s_axi_bvalid[m]), - .s_axi_bready(s_axi_bready[m]), - .m_axi_awid(int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .m_axi_awaddr(int_s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .m_axi_awlen(int_s_axi_awlen[m*8 +: 8]), - .m_axi_awsize(int_s_axi_awsize[m*3 +: 3]), - .m_axi_awburst(int_s_axi_awburst[m*2 +: 2]), - .m_axi_awlock(int_s_axi_awlock[m]), - .m_axi_awcache(int_s_axi_awcache[m*4 +: 4]), - .m_axi_awprot(int_s_axi_awprot[m*3 +: 3]), - .m_axi_awqos(int_s_axi_awqos[m*4 +: 4]), - .m_axi_awregion(), - .m_axi_awuser(int_s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]), - .m_axi_awvalid(int_s_axi_awvalid[m]), - .m_axi_awready(int_s_axi_awready[m]), - .m_axi_wdata(int_s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]), - .m_axi_wstrb(int_s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]), - .m_axi_wlast(int_s_axi_wlast[m]), - .m_axi_wuser(int_s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]), - .m_axi_wvalid(int_s_axi_wvalid[m]), - .m_axi_wready(int_s_axi_wready[m]), - .m_axi_bid(m_axi_bid_mux), - .m_axi_bresp(m_axi_bresp_mux), - .m_axi_buser(m_axi_buser_mux), - .m_axi_bvalid(m_axi_bvalid_mux), - .m_axi_bready(m_axi_bready_mux) - ); - end // s_ifaces - - for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces - // in-flight transaction count - wire trans_start; - wire trans_complete; - reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0; - - wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete; - - always @(posedge clk) begin - if (rst) begin - trans_count_reg <= 0; - end else begin - if (trans_start && !trans_complete) begin - trans_count_reg <= trans_count_reg + 1; - end else if (!trans_start && trans_complete) begin - trans_count_reg <= trans_count_reg - 1; - end - end - end - - // address arbitration - reg [CL_S_COUNT-1:0] w_select_reg = 0, w_select_next; - reg w_select_valid_reg = 1'b0, w_select_valid_next; - reg w_select_new_reg = 1'b0, w_select_new_next; - - wire [S_COUNT-1:0] a_request; - wire [S_COUNT-1:0] a_acknowledge; - wire [S_COUNT-1:0] a_grant; - wire a_grant_valid; - wire [CL_S_COUNT-1:0] a_grant_encoded; - - arbiter #( - .PORTS(S_COUNT), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_BLOCK(1), - .ARB_BLOCK_ACK(1), - .ARB_LSB_HIGH_PRIORITY(1) - ) - a_arb_inst ( - .clk(clk), - .rst(rst), - .request(a_request), - .acknowledge(a_acknowledge), - .grant(a_grant), - .grant_valid(a_grant_valid), - .grant_encoded(a_grant_encoded) - ); - - // address mux - wire [M_ID_WIDTH-1:0] s_axi_awid_mux = int_s_axi_awid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH); - wire [ADDR_WIDTH-1:0] s_axi_awaddr_mux = int_s_axi_awaddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH]; - wire [7:0] s_axi_awlen_mux = int_s_axi_awlen[a_grant_encoded*8 +: 8]; - wire [2:0] s_axi_awsize_mux = int_s_axi_awsize[a_grant_encoded*3 +: 3]; - wire [1:0] s_axi_awburst_mux = int_s_axi_awburst[a_grant_encoded*2 +: 2]; - wire s_axi_awlock_mux = int_s_axi_awlock[a_grant_encoded]; - wire [3:0] s_axi_awcache_mux = int_s_axi_awcache[a_grant_encoded*4 +: 4]; - wire [2:0] s_axi_awprot_mux = int_s_axi_awprot[a_grant_encoded*3 +: 3]; - wire [3:0] s_axi_awqos_mux = int_s_axi_awqos[a_grant_encoded*4 +: 4]; - wire [3:0] s_axi_awregion_mux = int_s_axi_awregion[a_grant_encoded*4 +: 4]; - wire [AWUSER_WIDTH-1:0] s_axi_awuser_mux = int_s_axi_awuser[a_grant_encoded*AWUSER_WIDTH +: AWUSER_WIDTH]; - wire s_axi_awvalid_mux = int_axi_awvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid; - wire s_axi_awready_mux; - - assign int_axi_awready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_awready_mux) << a_grant_encoded; - - for (m = 0; m < S_COUNT; m = m + 1) begin - assign a_request[m] = int_axi_awvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit && !w_select_valid_next; - assign a_acknowledge[m] = a_grant[m] && int_axi_awvalid[m*M_COUNT+n] && s_axi_awready_mux; - end - - assign trans_start = s_axi_awvalid_mux && s_axi_awready_mux && a_grant_valid; - - // write data mux - wire [DATA_WIDTH-1:0] s_axi_wdata_mux = int_s_axi_wdata[w_select_reg*DATA_WIDTH +: DATA_WIDTH]; - wire [STRB_WIDTH-1:0] s_axi_wstrb_mux = int_s_axi_wstrb[w_select_reg*STRB_WIDTH +: STRB_WIDTH]; - wire s_axi_wlast_mux = int_s_axi_wlast[w_select_reg]; - wire [WUSER_WIDTH-1:0] s_axi_wuser_mux = int_s_axi_wuser[w_select_reg*WUSER_WIDTH +: WUSER_WIDTH]; - wire s_axi_wvalid_mux = int_axi_wvalid[w_select_reg*M_COUNT+n] && w_select_valid_reg; - wire s_axi_wready_mux; - - assign int_axi_wready[n*S_COUNT +: S_COUNT] = (w_select_valid_reg && s_axi_wready_mux) << w_select_reg; - - // write data routing - always @* begin - w_select_next = w_select_reg; - w_select_valid_next = w_select_valid_reg && !(s_axi_wvalid_mux && s_axi_wready_mux && s_axi_wlast_mux); - w_select_new_next = w_select_new_reg || !a_grant_valid || a_acknowledge; - - if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin - w_select_next = a_grant_encoded; - w_select_valid_next = a_grant_valid; - w_select_new_next = 1'b0; - end - end - - always @(posedge clk) begin - if (rst) begin - w_select_valid_reg <= 1'b0; - w_select_new_reg <= 1'b1; - end else begin - w_select_valid_reg <= w_select_valid_next; - w_select_new_reg <= w_select_new_next; - end - - w_select_reg <= w_select_next; - end - - // write response forwarding - wire [CL_S_COUNT-1:0] b_select = m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH; - - assign int_axi_bvalid[n*S_COUNT +: S_COUNT] = int_m_axi_bvalid[n] << b_select; - assign int_m_axi_bready[n] = int_axi_bready[b_select*M_COUNT+n]; - - assign trans_complete = int_m_axi_bvalid[n] && int_m_axi_bready[n]; - - // M side register - axi_register_wr #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .ID_WIDTH(M_ID_WIDTH), - .AWUSER_ENABLE(AWUSER_ENABLE), - .AWUSER_WIDTH(AWUSER_WIDTH), - .WUSER_ENABLE(WUSER_ENABLE), - .WUSER_WIDTH(WUSER_WIDTH), - .BUSER_ENABLE(BUSER_ENABLE), - .BUSER_WIDTH(BUSER_WIDTH), - .AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]), - .W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]), - .B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2]) - ) - reg_inst ( - .clk(clk), - .rst(rst), - .s_axi_awid(s_axi_awid_mux), - .s_axi_awaddr(s_axi_awaddr_mux), - .s_axi_awlen(s_axi_awlen_mux), - .s_axi_awsize(s_axi_awsize_mux), - .s_axi_awburst(s_axi_awburst_mux), - .s_axi_awlock(s_axi_awlock_mux), - .s_axi_awcache(s_axi_awcache_mux), - .s_axi_awprot(s_axi_awprot_mux), - .s_axi_awqos(s_axi_awqos_mux), - .s_axi_awregion(s_axi_awregion_mux), - .s_axi_awuser(s_axi_awuser_mux), - .s_axi_awvalid(s_axi_awvalid_mux), - .s_axi_awready(s_axi_awready_mux), - .s_axi_wdata(s_axi_wdata_mux), - .s_axi_wstrb(s_axi_wstrb_mux), - .s_axi_wlast(s_axi_wlast_mux), - .s_axi_wuser(s_axi_wuser_mux), - .s_axi_wvalid(s_axi_wvalid_mux), - .s_axi_wready(s_axi_wready_mux), - .s_axi_bid(int_m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .s_axi_bresp(int_m_axi_bresp[n*2 +: 2]), - .s_axi_buser(int_m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]), - .s_axi_bvalid(int_m_axi_bvalid[n]), - .s_axi_bready(int_m_axi_bready[n]), - .m_axi_awid(m_axi_awid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .m_axi_awaddr(m_axi_awaddr[n*ADDR_WIDTH +: ADDR_WIDTH]), - .m_axi_awlen(m_axi_awlen[n*8 +: 8]), - .m_axi_awsize(m_axi_awsize[n*3 +: 3]), - .m_axi_awburst(m_axi_awburst[n*2 +: 2]), - .m_axi_awlock(m_axi_awlock[n]), - .m_axi_awcache(m_axi_awcache[n*4 +: 4]), - .m_axi_awprot(m_axi_awprot[n*3 +: 3]), - .m_axi_awqos(m_axi_awqos[n*4 +: 4]), - .m_axi_awregion(m_axi_awregion[n*4 +: 4]), - .m_axi_awuser(m_axi_awuser[n*AWUSER_WIDTH +: AWUSER_WIDTH]), - .m_axi_awvalid(m_axi_awvalid[n]), - .m_axi_awready(m_axi_awready[n]), - .m_axi_wdata(m_axi_wdata[n*DATA_WIDTH +: DATA_WIDTH]), - .m_axi_wstrb(m_axi_wstrb[n*STRB_WIDTH +: STRB_WIDTH]), - .m_axi_wlast(m_axi_wlast[n]), - .m_axi_wuser(m_axi_wuser[n*WUSER_WIDTH +: WUSER_WIDTH]), - .m_axi_wvalid(m_axi_wvalid[n]), - .m_axi_wready(m_axi_wready[n]), - .m_axi_bid(m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .m_axi_bresp(m_axi_bresp[n*2 +: 2]), - .m_axi_buser(m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]), - .m_axi_bvalid(m_axi_bvalid[n]), - .m_axi_bready(m_axi_bready[n]) - ); - end // m_ifaces - -endgenerate - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_pipeline.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_pipeline.v deleted file mode 100644 index 7f3d08fe..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_pipeline.v +++ /dev/null @@ -1,214 +0,0 @@ -module axi_pipeline #( - parameter - C_M_AXI_ID_WIDTH = 8, - C_M_AXI_ADDR_WIDTH = 32, - C_M_AXI_DATA_WIDTH = 512, - C_M_AXI_WSTRB_WIDTH = (512 / 8), - - PIPELINE_LEVEL = 3, - EnableReadChannel = 1, - EnableWriteChannel = 1 -) -( - input ap_clk, - - // pipeline in - input in_AWVALID, - output in_AWREADY, - input [C_M_AXI_ADDR_WIDTH - 1:0] in_AWADDR, - input [1:0] in_AWBURST, - input [7:0] in_AWLEN, - input [2:0] in_AWSIZE, - input [C_M_AXI_ID_WIDTH - 1:0] in_AWID, - - input in_WVALID, - output in_WREADY, - input [C_M_AXI_DATA_WIDTH - 1:0] in_WDATA, - input [C_M_AXI_WSTRB_WIDTH - 1:0] in_WSTRB, - input in_WLAST, - - output in_BVALID, - input in_BREADY, - output [1:0] in_BRESP, - output [C_M_AXI_ID_WIDTH - 1:0] in_BID, - - input in_ARVALID, - output in_ARREADY, - input [C_M_AXI_ADDR_WIDTH - 1:0] in_ARADDR, - input [1:0] in_ARBURST, - input [7:0] in_ARLEN, - input [2:0] in_ARSIZE, - input [C_M_AXI_ID_WIDTH - 1:0] in_ARID, - - output in_RVALID, - input in_RREADY, - output [C_M_AXI_DATA_WIDTH - 1:0] in_RDATA, - output in_RLAST, - output [C_M_AXI_ID_WIDTH - 1:0] in_RID, - output [1:0] in_RRESP, - - // pipeline out - output out_AWVALID, - input out_AWREADY, - output [C_M_AXI_ADDR_WIDTH - 1:0] out_AWADDR, - output [1:0] out_AWBURST, - output [7:0] out_AWLEN, - output [2:0] out_AWSIZE, - output [C_M_AXI_ID_WIDTH - 1:0] out_AWID, - - output out_WVALID, - input out_WREADY, - output [C_M_AXI_DATA_WIDTH - 1:0] out_WDATA, - output [C_M_AXI_WSTRB_WIDTH - 1:0] out_WSTRB, - output out_WLAST, - - input out_BVALID, - output out_BREADY, - input [1:0] out_BRESP, - input [C_M_AXI_ID_WIDTH - 1:0] out_BID, - - output out_ARVALID, - input out_ARREADY, - output [C_M_AXI_ADDR_WIDTH - 1:0] out_ARADDR, - output [1:0] out_ARBURST, - output [7:0] out_ARLEN, - output [2:0] out_ARSIZE, - output [C_M_AXI_ID_WIDTH - 1:0] out_ARID, - - input out_RVALID, - output out_RREADY, - input [C_M_AXI_DATA_WIDTH - 1:0] out_RDATA, - input out_RLAST, - input [C_M_AXI_ID_WIDTH - 1:0] out_RID, - input [1:0] out_RRESP -); - - relay_station - #( - .DATA_WIDTH ( C_M_AXI_ADDR_WIDTH + C_M_AXI_ID_WIDTH + 8 + 3 + 2 ), - .DEPTH ( 2 ), - .ADDR_WIDTH ( 1 ), - .LEVEL ( PIPELINE_LEVEL ), - .CONNECT ( EnableWriteChannel ) - ) - AW_pipeline - ( - .clk ( ap_clk ), - .reset ( 1'b0 ), - .if_read_ce ( 1'b1 ), - .if_write_ce ( 1'b1 ), - - .if_din ( {in_AWADDR, in_AWID, in_AWLEN, in_AWSIZE, in_AWBURST} ), - .if_full_n ( in_AWREADY ), - .if_write ( in_AWVALID ), - - .if_dout ( {out_AWADDR, out_AWID, out_AWLEN, out_AWSIZE, out_AWBURST} ), - .if_empty_n ( out_AWVALID ), - .if_read ( out_AWREADY ) - ); - - relay_station - #( - .DATA_WIDTH( - C_M_AXI_DATA_WIDTH + C_M_AXI_WSTRB_WIDTH + 1 - ), - .DEPTH(2), - .ADDR_WIDTH(1), - .LEVEL( PIPELINE_LEVEL ), - .CONNECT ( EnableWriteChannel ) - ) - W_pipeline - ( - .clk (ap_clk), - .reset ( 1'b0 ), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({in_WDATA, in_WSTRB, in_WLAST}), - .if_full_n ( in_WREADY), - .if_write ( in_WVALID), - - .if_dout ({out_WDATA, out_WSTRB, out_WLAST}), - .if_empty_n (out_WVALID), - .if_read (out_WREADY) - ); - - relay_station - #( - .DATA_WIDTH( - C_M_AXI_ADDR_WIDTH + C_M_AXI_ID_WIDTH + 8 + 3 + 2 - ), - .DEPTH(2), - .ADDR_WIDTH(1), - .LEVEL( PIPELINE_LEVEL ), - .CONNECT( EnableReadChannel ) - ) - AR_pipeline - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({ in_ARADDR, in_ARID, in_ARLEN, in_ARSIZE, in_ARBURST}), - .if_full_n ( in_ARREADY), - .if_write ( in_ARVALID), - - .if_dout ({out_ARADDR, out_ARID, out_ARLEN, out_ARSIZE, out_ARBURST}), - .if_empty_n (out_ARVALID), - .if_read (out_ARREADY) - ); - - relay_station - #( - .DATA_WIDTH( - C_M_AXI_DATA_WIDTH + 1 + C_M_AXI_ID_WIDTH + 2 - ), - .DEPTH(2), - .ADDR_WIDTH(1), - .LEVEL( PIPELINE_LEVEL ), - .CONNECT( EnableReadChannel ) - ) - R_pipeline - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({out_RDATA, out_RLAST, out_RID, out_RRESP}), - .if_full_n ( out_RREADY), - .if_write ( out_RVALID), - - .if_dout ({in_RDATA, in_RLAST, in_RID, in_RRESP}), - .if_empty_n (in_RVALID), - .if_read (in_RREADY) - ); - - relay_station - #( - .DATA_WIDTH( - 2 + C_M_AXI_ID_WIDTH - ), - .DEPTH(2), - .ADDR_WIDTH(1), - .LEVEL( PIPELINE_LEVEL ), - .CONNECT( EnableWriteChannel ) - ) - B_pipeline - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({out_BRESP, out_BID}), - .if_full_n (out_BREADY), - .if_write (out_BVALID), - - .if_dout ({ in_BRESP, in_BID}), - .if_empty_n (in_BVALID), - .if_read (in_BREADY) - ); - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_register_rd.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_register_rd.v deleted file mode 100644 index c0df03a0..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_register_rd.v +++ /dev/null @@ -1,530 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 register (read) - */ -module axi_register_rd # -( - // Width of data bus in bits - parameter DATA_WIDTH = 32, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // Width of wstrb (width of data bus in words) - parameter STRB_WIDTH = (DATA_WIDTH/8), - // Width of ID signal - parameter ID_WIDTH = 8, - // Propagate aruser signal - parameter ARUSER_ENABLE = 0, - // Width of aruser signal - parameter ARUSER_WIDTH = 1, - // Propagate ruser signal - parameter RUSER_ENABLE = 0, - // Width of ruser signal - parameter RUSER_WIDTH = 1, - // AR channel register type - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter AR_REG_TYPE = 1, - // R channel register type - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter R_REG_TYPE = 2 -) -( - input wire clk, - input wire rst, - - /* - * AXI slave interface - */ - input wire [ID_WIDTH-1:0] s_axi_arid, - input wire [ADDR_WIDTH-1:0] s_axi_araddr, - input wire [7:0] s_axi_arlen, - input wire [2:0] s_axi_arsize, - input wire [1:0] s_axi_arburst, - input wire s_axi_arlock, - input wire [3:0] s_axi_arcache, - input wire [2:0] s_axi_arprot, - input wire [3:0] s_axi_arqos, - input wire [3:0] s_axi_arregion, - input wire [ARUSER_WIDTH-1:0] s_axi_aruser, - input wire s_axi_arvalid, - output wire s_axi_arready, - output wire [ID_WIDTH-1:0] s_axi_rid, - output wire [DATA_WIDTH-1:0] s_axi_rdata, - output wire [1:0] s_axi_rresp, - output wire s_axi_rlast, - output wire [RUSER_WIDTH-1:0] s_axi_ruser, - output wire s_axi_rvalid, - input wire s_axi_rready, - - /* - * AXI master interface - */ - output wire [ID_WIDTH-1:0] m_axi_arid, - output wire [ADDR_WIDTH-1:0] m_axi_araddr, - output wire [7:0] m_axi_arlen, - output wire [2:0] m_axi_arsize, - output wire [1:0] m_axi_arburst, - output wire m_axi_arlock, - output wire [3:0] m_axi_arcache, - output wire [2:0] m_axi_arprot, - output wire [3:0] m_axi_arqos, - output wire [3:0] m_axi_arregion, - output wire [ARUSER_WIDTH-1:0] m_axi_aruser, - output wire m_axi_arvalid, - input wire m_axi_arready, - input wire [ID_WIDTH-1:0] m_axi_rid, - input wire [DATA_WIDTH-1:0] m_axi_rdata, - input wire [1:0] m_axi_rresp, - input wire m_axi_rlast, - input wire [RUSER_WIDTH-1:0] m_axi_ruser, - input wire m_axi_rvalid, - output wire m_axi_rready -); - -generate - -// AR channel - -if (AR_REG_TYPE > 1) begin -// skid buffer, no bubble cycles - -// datapath registers -reg s_axi_arready_reg = 1'b0; - -reg [ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] m_axi_arlen_reg = 8'd0; -reg [2:0] m_axi_arsize_reg = 3'd0; -reg [1:0] m_axi_arburst_reg = 2'd0; -reg m_axi_arlock_reg = 1'b0; -reg [3:0] m_axi_arcache_reg = 4'd0; -reg [2:0] m_axi_arprot_reg = 3'd0; -reg [3:0] m_axi_arqos_reg = 4'd0; -reg [3:0] m_axi_arregion_reg = 4'd0; -reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}}; -reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next; - -reg [ID_WIDTH-1:0] temp_m_axi_arid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] temp_m_axi_araddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] temp_m_axi_arlen_reg = 8'd0; -reg [2:0] temp_m_axi_arsize_reg = 3'd0; -reg [1:0] temp_m_axi_arburst_reg = 2'd0; -reg temp_m_axi_arlock_reg = 1'b0; -reg [3:0] temp_m_axi_arcache_reg = 4'd0; -reg [2:0] temp_m_axi_arprot_reg = 3'd0; -reg [3:0] temp_m_axi_arqos_reg = 4'd0; -reg [3:0] temp_m_axi_arregion_reg = 4'd0; -reg [ARUSER_WIDTH-1:0] temp_m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}}; -reg temp_m_axi_arvalid_reg = 1'b0, temp_m_axi_arvalid_next; - -// datapath control -reg store_axi_ar_input_to_output; -reg store_axi_ar_input_to_temp; -reg store_axi_ar_temp_to_output; - -assign s_axi_arready = s_axi_arready_reg; - -assign m_axi_arid = m_axi_arid_reg; -assign m_axi_araddr = m_axi_araddr_reg; -assign m_axi_arlen = m_axi_arlen_reg; -assign m_axi_arsize = m_axi_arsize_reg; -assign m_axi_arburst = m_axi_arburst_reg; -assign m_axi_arlock = m_axi_arlock_reg; -assign m_axi_arcache = m_axi_arcache_reg; -assign m_axi_arprot = m_axi_arprot_reg; -assign m_axi_arqos = m_axi_arqos_reg; -assign m_axi_arregion = m_axi_arregion_reg; -assign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}}; -assign m_axi_arvalid = m_axi_arvalid_reg; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -wire s_axi_arready_early = m_axi_arready | (~temp_m_axi_arvalid_reg & (~m_axi_arvalid_reg | ~s_axi_arvalid)); - -always @* begin - // transfer sink ready state to source - m_axi_arvalid_next = m_axi_arvalid_reg; - temp_m_axi_arvalid_next = temp_m_axi_arvalid_reg; - - store_axi_ar_input_to_output = 1'b0; - store_axi_ar_input_to_temp = 1'b0; - store_axi_ar_temp_to_output = 1'b0; - - if (s_axi_arready_reg) begin - // input is ready - if (m_axi_arready | ~m_axi_arvalid_reg) begin - // output is ready or currently not valid, transfer data to output - m_axi_arvalid_next = s_axi_arvalid; - store_axi_ar_input_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_m_axi_arvalid_next = s_axi_arvalid; - store_axi_ar_input_to_temp = 1'b1; - end - end else if (m_axi_arready) begin - // input is not ready, but output is ready - m_axi_arvalid_next = temp_m_axi_arvalid_reg; - temp_m_axi_arvalid_next = 1'b0; - store_axi_ar_temp_to_output = 1'b1; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_arready_reg <= 1'b0; - m_axi_arvalid_reg <= 1'b0; - temp_m_axi_arvalid_reg <= 1'b0; - end else begin - s_axi_arready_reg <= s_axi_arready_early; - m_axi_arvalid_reg <= m_axi_arvalid_next; - temp_m_axi_arvalid_reg <= temp_m_axi_arvalid_next; - end - - // datapath - if (store_axi_ar_input_to_output) begin - m_axi_arid_reg <= s_axi_arid; - m_axi_araddr_reg <= s_axi_araddr; - m_axi_arlen_reg <= s_axi_arlen; - m_axi_arsize_reg <= s_axi_arsize; - m_axi_arburst_reg <= s_axi_arburst; - m_axi_arlock_reg <= s_axi_arlock; - m_axi_arcache_reg <= s_axi_arcache; - m_axi_arprot_reg <= s_axi_arprot; - m_axi_arqos_reg <= s_axi_arqos; - m_axi_arregion_reg <= s_axi_arregion; - m_axi_aruser_reg <= s_axi_aruser; - end else if (store_axi_ar_temp_to_output) begin - m_axi_arid_reg <= temp_m_axi_arid_reg; - m_axi_araddr_reg <= temp_m_axi_araddr_reg; - m_axi_arlen_reg <= temp_m_axi_arlen_reg; - m_axi_arsize_reg <= temp_m_axi_arsize_reg; - m_axi_arburst_reg <= temp_m_axi_arburst_reg; - m_axi_arlock_reg <= temp_m_axi_arlock_reg; - m_axi_arcache_reg <= temp_m_axi_arcache_reg; - m_axi_arprot_reg <= temp_m_axi_arprot_reg; - m_axi_arqos_reg <= temp_m_axi_arqos_reg; - m_axi_arregion_reg <= temp_m_axi_arregion_reg; - m_axi_aruser_reg <= temp_m_axi_aruser_reg; - end - - if (store_axi_ar_input_to_temp) begin - temp_m_axi_arid_reg <= s_axi_arid; - temp_m_axi_araddr_reg <= s_axi_araddr; - temp_m_axi_arlen_reg <= s_axi_arlen; - temp_m_axi_arsize_reg <= s_axi_arsize; - temp_m_axi_arburst_reg <= s_axi_arburst; - temp_m_axi_arlock_reg <= s_axi_arlock; - temp_m_axi_arcache_reg <= s_axi_arcache; - temp_m_axi_arprot_reg <= s_axi_arprot; - temp_m_axi_arqos_reg <= s_axi_arqos; - temp_m_axi_arregion_reg <= s_axi_arregion; - temp_m_axi_aruser_reg <= s_axi_aruser; - end -end - -end else if (AR_REG_TYPE == 1) begin -// simple register, inserts bubble cycles - -// datapath registers -reg s_axi_arready_reg = 1'b0; - -reg [ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] m_axi_arlen_reg = 8'd0; -reg [2:0] m_axi_arsize_reg = 3'd0; -reg [1:0] m_axi_arburst_reg = 2'd0; -reg m_axi_arlock_reg = 1'b0; -reg [3:0] m_axi_arcache_reg = 4'd0; -reg [2:0] m_axi_arprot_reg = 3'd0; -reg [3:0] m_axi_arqos_reg = 4'd0; -reg [3:0] m_axi_arregion_reg = 4'd0; -reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}}; -reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next; - -// datapath control -reg store_axi_ar_input_to_output; - -assign s_axi_arready = s_axi_arready_reg; - -assign m_axi_arid = m_axi_arid_reg; -assign m_axi_araddr = m_axi_araddr_reg; -assign m_axi_arlen = m_axi_arlen_reg; -assign m_axi_arsize = m_axi_arsize_reg; -assign m_axi_arburst = m_axi_arburst_reg; -assign m_axi_arlock = m_axi_arlock_reg; -assign m_axi_arcache = m_axi_arcache_reg; -assign m_axi_arprot = m_axi_arprot_reg; -assign m_axi_arqos = m_axi_arqos_reg; -assign m_axi_arregion = m_axi_arregion_reg; -assign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}}; -assign m_axi_arvalid = m_axi_arvalid_reg; - -// enable ready input next cycle if output buffer will be empty -wire s_axi_arready_early = !m_axi_arvalid_next; - -always @* begin - // transfer sink ready state to source - m_axi_arvalid_next = m_axi_arvalid_reg; - - store_axi_ar_input_to_output = 1'b0; - - if (s_axi_arready_reg) begin - m_axi_arvalid_next = s_axi_arvalid; - store_axi_ar_input_to_output = 1'b1; - end else if (m_axi_arready) begin - m_axi_arvalid_next = 1'b0; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_arready_reg <= 1'b0; - m_axi_arvalid_reg <= 1'b0; - end else begin - s_axi_arready_reg <= s_axi_arready_early; - m_axi_arvalid_reg <= m_axi_arvalid_next; - end - - // datapath - if (store_axi_ar_input_to_output) begin - m_axi_arid_reg <= s_axi_arid; - m_axi_araddr_reg <= s_axi_araddr; - m_axi_arlen_reg <= s_axi_arlen; - m_axi_arsize_reg <= s_axi_arsize; - m_axi_arburst_reg <= s_axi_arburst; - m_axi_arlock_reg <= s_axi_arlock; - m_axi_arcache_reg <= s_axi_arcache; - m_axi_arprot_reg <= s_axi_arprot; - m_axi_arqos_reg <= s_axi_arqos; - m_axi_arregion_reg <= s_axi_arregion; - m_axi_aruser_reg <= s_axi_aruser; - end -end - -end else begin - - // bypass AR channel - assign m_axi_arid = s_axi_arid; - assign m_axi_araddr = s_axi_araddr; - assign m_axi_arlen = s_axi_arlen; - assign m_axi_arsize = s_axi_arsize; - assign m_axi_arburst = s_axi_arburst; - assign m_axi_arlock = s_axi_arlock; - assign m_axi_arcache = s_axi_arcache; - assign m_axi_arprot = s_axi_arprot; - assign m_axi_arqos = s_axi_arqos; - assign m_axi_arregion = s_axi_arregion; - assign m_axi_aruser = ARUSER_ENABLE ? s_axi_aruser : {ARUSER_WIDTH{1'b0}}; - assign m_axi_arvalid = s_axi_arvalid; - assign s_axi_arready = m_axi_arready; - -end - -// R channel - -if (R_REG_TYPE > 1) begin -// skid buffer, no bubble cycles - -// datapath registers -reg m_axi_rready_reg = 1'b0; - -reg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}}; -reg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}}; -reg [1:0] s_axi_rresp_reg = 2'b0; -reg s_axi_rlast_reg = 1'b0; -reg [RUSER_WIDTH-1:0] s_axi_ruser_reg = {RUSER_WIDTH{1'b0}}; -reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next; - -reg [ID_WIDTH-1:0] temp_s_axi_rid_reg = {ID_WIDTH{1'b0}}; -reg [DATA_WIDTH-1:0] temp_s_axi_rdata_reg = {DATA_WIDTH{1'b0}}; -reg [1:0] temp_s_axi_rresp_reg = 2'b0; -reg temp_s_axi_rlast_reg = 1'b0; -reg [RUSER_WIDTH-1:0] temp_s_axi_ruser_reg = {RUSER_WIDTH{1'b0}}; -reg temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next; - -// datapath control -reg store_axi_r_input_to_output; -reg store_axi_r_input_to_temp; -reg store_axi_r_temp_to_output; - -assign m_axi_rready = m_axi_rready_reg; - -assign s_axi_rid = s_axi_rid_reg; -assign s_axi_rdata = s_axi_rdata_reg; -assign s_axi_rresp = s_axi_rresp_reg; -assign s_axi_rlast = s_axi_rlast_reg; -assign s_axi_ruser = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}}; -assign s_axi_rvalid = s_axi_rvalid_reg; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -wire m_axi_rready_early = s_axi_rready | (~temp_s_axi_rvalid_reg & (~s_axi_rvalid_reg | ~m_axi_rvalid)); - -always @* begin - // transfer sink ready state to source - s_axi_rvalid_next = s_axi_rvalid_reg; - temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg; - - store_axi_r_input_to_output = 1'b0; - store_axi_r_input_to_temp = 1'b0; - store_axi_r_temp_to_output = 1'b0; - - if (m_axi_rready_reg) begin - // input is ready - if (s_axi_rready | ~s_axi_rvalid_reg) begin - // output is ready or currently not valid, transfer data to output - s_axi_rvalid_next = m_axi_rvalid; - store_axi_r_input_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_s_axi_rvalid_next = m_axi_rvalid; - store_axi_r_input_to_temp = 1'b1; - end - end else if (s_axi_rready) begin - // input is not ready, but output is ready - s_axi_rvalid_next = temp_s_axi_rvalid_reg; - temp_s_axi_rvalid_next = 1'b0; - store_axi_r_temp_to_output = 1'b1; - end -end - -always @(posedge clk) begin - if (rst) begin - m_axi_rready_reg <= 1'b0; - s_axi_rvalid_reg <= 1'b0; - temp_s_axi_rvalid_reg <= 1'b0; - end else begin - m_axi_rready_reg <= m_axi_rready_early; - s_axi_rvalid_reg <= s_axi_rvalid_next; - temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next; - end - - // datapath - if (store_axi_r_input_to_output) begin - s_axi_rid_reg <= m_axi_rid; - s_axi_rdata_reg <= m_axi_rdata; - s_axi_rresp_reg <= m_axi_rresp; - s_axi_rlast_reg <= m_axi_rlast; - s_axi_ruser_reg <= m_axi_ruser; - end else if (store_axi_r_temp_to_output) begin - s_axi_rid_reg <= temp_s_axi_rid_reg; - s_axi_rdata_reg <= temp_s_axi_rdata_reg; - s_axi_rresp_reg <= temp_s_axi_rresp_reg; - s_axi_rlast_reg <= temp_s_axi_rlast_reg; - s_axi_ruser_reg <= temp_s_axi_ruser_reg; - end - - if (store_axi_r_input_to_temp) begin - temp_s_axi_rid_reg <= m_axi_rid; - temp_s_axi_rdata_reg <= m_axi_rdata; - temp_s_axi_rresp_reg <= m_axi_rresp; - temp_s_axi_rlast_reg <= m_axi_rlast; - temp_s_axi_ruser_reg <= m_axi_ruser; - end -end - -end else if (R_REG_TYPE == 1) begin -// simple register, inserts bubble cycles - -// datapath registers -reg m_axi_rready_reg = 1'b0; - -reg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}}; -reg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}}; -reg [1:0] s_axi_rresp_reg = 2'b0; -reg s_axi_rlast_reg = 1'b0; -reg [RUSER_WIDTH-1:0] s_axi_ruser_reg = {RUSER_WIDTH{1'b0}}; -reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next; - -// datapath control -reg store_axi_r_input_to_output; - -assign m_axi_rready = m_axi_rready_reg; - -assign s_axi_rid = s_axi_rid_reg; -assign s_axi_rdata = s_axi_rdata_reg; -assign s_axi_rresp = s_axi_rresp_reg; -assign s_axi_rlast = s_axi_rlast_reg; -assign s_axi_ruser = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}}; -assign s_axi_rvalid = s_axi_rvalid_reg; - -// enable ready input next cycle if output buffer will be empty -wire m_axi_rready_early = !s_axi_rvalid_next; - -always @* begin - // transfer sink ready state to source - s_axi_rvalid_next = s_axi_rvalid_reg; - - store_axi_r_input_to_output = 1'b0; - - if (m_axi_rready_reg) begin - s_axi_rvalid_next = m_axi_rvalid; - store_axi_r_input_to_output = 1'b1; - end else if (s_axi_rready) begin - s_axi_rvalid_next = 1'b0; - end -end - -always @(posedge clk) begin - if (rst) begin - m_axi_rready_reg <= 1'b0; - s_axi_rvalid_reg <= 1'b0; - end else begin - m_axi_rready_reg <= m_axi_rready_early; - s_axi_rvalid_reg <= s_axi_rvalid_next; - end - - // datapath - if (store_axi_r_input_to_output) begin - s_axi_rid_reg <= m_axi_rid; - s_axi_rdata_reg <= m_axi_rdata; - s_axi_rresp_reg <= m_axi_rresp; - s_axi_rlast_reg <= m_axi_rlast; - s_axi_ruser_reg <= m_axi_ruser; - end -end - -end else begin - - // bypass R channel - assign s_axi_rid = m_axi_rid; - assign s_axi_rdata = m_axi_rdata; - assign s_axi_rresp = m_axi_rresp; - assign s_axi_rlast = m_axi_rlast; - assign s_axi_ruser = RUSER_ENABLE ? m_axi_ruser : {RUSER_WIDTH{1'b0}}; - assign s_axi_rvalid = m_axi_rvalid; - assign m_axi_rready = s_axi_rready; - -end - -endgenerate - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_register_wr.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_register_wr.v deleted file mode 100644 index 9176d6ba..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/axi_register_wr.v +++ /dev/null @@ -1,691 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 register (write) - */ -module axi_register_wr # -( - // Width of data bus in bits - parameter DATA_WIDTH = 32, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // Width of wstrb (width of data bus in words) - parameter STRB_WIDTH = (DATA_WIDTH/8), - // Width of ID signal - parameter ID_WIDTH = 8, - // Propagate awuser signal - parameter AWUSER_ENABLE = 0, - // Width of awuser signal - parameter AWUSER_WIDTH = 1, - // Propagate wuser signal - parameter WUSER_ENABLE = 0, - // Width of wuser signal - parameter WUSER_WIDTH = 1, - // Propagate buser signal - parameter BUSER_ENABLE = 0, - // Width of buser signal - parameter BUSER_WIDTH = 1, - // AW channel register type - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter AW_REG_TYPE = 1, - // W channel register type - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter W_REG_TYPE = 2, - // B channel register type - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter B_REG_TYPE = 1 -) -( - input wire clk, - input wire rst, - - /* - * AXI slave interface - */ - input wire [ID_WIDTH-1:0] s_axi_awid, - input wire [ADDR_WIDTH-1:0] s_axi_awaddr, - input wire [7:0] s_axi_awlen, - input wire [2:0] s_axi_awsize, - input wire [1:0] s_axi_awburst, - input wire s_axi_awlock, - input wire [3:0] s_axi_awcache, - input wire [2:0] s_axi_awprot, - input wire [3:0] s_axi_awqos, - input wire [3:0] s_axi_awregion, - input wire [AWUSER_WIDTH-1:0] s_axi_awuser, - input wire s_axi_awvalid, - output wire s_axi_awready, - input wire [DATA_WIDTH-1:0] s_axi_wdata, - input wire [STRB_WIDTH-1:0] s_axi_wstrb, - input wire s_axi_wlast, - input wire [WUSER_WIDTH-1:0] s_axi_wuser, - input wire s_axi_wvalid, - output wire s_axi_wready, - output wire [ID_WIDTH-1:0] s_axi_bid, - output wire [1:0] s_axi_bresp, - output wire [BUSER_WIDTH-1:0] s_axi_buser, - output wire s_axi_bvalid, - input wire s_axi_bready, - - /* - * AXI master interface - */ - output wire [ID_WIDTH-1:0] m_axi_awid, - output wire [ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [7:0] m_axi_awlen, - output wire [2:0] m_axi_awsize, - output wire [1:0] m_axi_awburst, - output wire m_axi_awlock, - output wire [3:0] m_axi_awcache, - output wire [2:0] m_axi_awprot, - output wire [3:0] m_axi_awqos, - output wire [3:0] m_axi_awregion, - output wire [AWUSER_WIDTH-1:0] m_axi_awuser, - output wire m_axi_awvalid, - input wire m_axi_awready, - output wire [DATA_WIDTH-1:0] m_axi_wdata, - output wire [STRB_WIDTH-1:0] m_axi_wstrb, - output wire m_axi_wlast, - output wire [WUSER_WIDTH-1:0] m_axi_wuser, - output wire m_axi_wvalid, - input wire m_axi_wready, - input wire [ID_WIDTH-1:0] m_axi_bid, - input wire [1:0] m_axi_bresp, - input wire [BUSER_WIDTH-1:0] m_axi_buser, - input wire m_axi_bvalid, - output wire m_axi_bready -); - -generate - -// AW channel - -if (AW_REG_TYPE > 1) begin -// skid buffer, no bubble cycles - -// datapath registers -reg s_axi_awready_reg = 1'b0; - -reg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] m_axi_awlen_reg = 8'd0; -reg [2:0] m_axi_awsize_reg = 3'd0; -reg [1:0] m_axi_awburst_reg = 2'd0; -reg m_axi_awlock_reg = 1'b0; -reg [3:0] m_axi_awcache_reg = 4'd0; -reg [2:0] m_axi_awprot_reg = 3'd0; -reg [3:0] m_axi_awqos_reg = 4'd0; -reg [3:0] m_axi_awregion_reg = 4'd0; -reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}}; -reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next; - -reg [ID_WIDTH-1:0] temp_m_axi_awid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] temp_m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] temp_m_axi_awlen_reg = 8'd0; -reg [2:0] temp_m_axi_awsize_reg = 3'd0; -reg [1:0] temp_m_axi_awburst_reg = 2'd0; -reg temp_m_axi_awlock_reg = 1'b0; -reg [3:0] temp_m_axi_awcache_reg = 4'd0; -reg [2:0] temp_m_axi_awprot_reg = 3'd0; -reg [3:0] temp_m_axi_awqos_reg = 4'd0; -reg [3:0] temp_m_axi_awregion_reg = 4'd0; -reg [AWUSER_WIDTH-1:0] temp_m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}}; -reg temp_m_axi_awvalid_reg = 1'b0, temp_m_axi_awvalid_next; - -// datapath control -reg store_axi_aw_input_to_output; -reg store_axi_aw_input_to_temp; -reg store_axi_aw_temp_to_output; - -assign s_axi_awready = s_axi_awready_reg; - -assign m_axi_awid = m_axi_awid_reg; -assign m_axi_awaddr = m_axi_awaddr_reg; -assign m_axi_awlen = m_axi_awlen_reg; -assign m_axi_awsize = m_axi_awsize_reg; -assign m_axi_awburst = m_axi_awburst_reg; -assign m_axi_awlock = m_axi_awlock_reg; -assign m_axi_awcache = m_axi_awcache_reg; -assign m_axi_awprot = m_axi_awprot_reg; -assign m_axi_awqos = m_axi_awqos_reg; -assign m_axi_awregion = m_axi_awregion_reg; -assign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}}; -assign m_axi_awvalid = m_axi_awvalid_reg; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -wire s_axi_awready_early = m_axi_awready | (~temp_m_axi_awvalid_reg & (~m_axi_awvalid_reg | ~s_axi_awvalid)); - -always @* begin - // transfer sink ready state to source - m_axi_awvalid_next = m_axi_awvalid_reg; - temp_m_axi_awvalid_next = temp_m_axi_awvalid_reg; - - store_axi_aw_input_to_output = 1'b0; - store_axi_aw_input_to_temp = 1'b0; - store_axi_aw_temp_to_output = 1'b0; - - if (s_axi_awready_reg) begin - // input is ready - if (m_axi_awready | ~m_axi_awvalid_reg) begin - // output is ready or currently not valid, transfer data to output - m_axi_awvalid_next = s_axi_awvalid; - store_axi_aw_input_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_m_axi_awvalid_next = s_axi_awvalid; - store_axi_aw_input_to_temp = 1'b1; - end - end else if (m_axi_awready) begin - // input is not ready, but output is ready - m_axi_awvalid_next = temp_m_axi_awvalid_reg; - temp_m_axi_awvalid_next = 1'b0; - store_axi_aw_temp_to_output = 1'b1; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_awready_reg <= 1'b0; - m_axi_awvalid_reg <= 1'b0; - temp_m_axi_awvalid_reg <= 1'b0; - end else begin - s_axi_awready_reg <= s_axi_awready_early; - m_axi_awvalid_reg <= m_axi_awvalid_next; - temp_m_axi_awvalid_reg <= temp_m_axi_awvalid_next; - end - - // datapath - if (store_axi_aw_input_to_output) begin - m_axi_awid_reg <= s_axi_awid; - m_axi_awaddr_reg <= s_axi_awaddr; - m_axi_awlen_reg <= s_axi_awlen; - m_axi_awsize_reg <= s_axi_awsize; - m_axi_awburst_reg <= s_axi_awburst; - m_axi_awlock_reg <= s_axi_awlock; - m_axi_awcache_reg <= s_axi_awcache; - m_axi_awprot_reg <= s_axi_awprot; - m_axi_awqos_reg <= s_axi_awqos; - m_axi_awregion_reg <= s_axi_awregion; - m_axi_awuser_reg <= s_axi_awuser; - end else if (store_axi_aw_temp_to_output) begin - m_axi_awid_reg <= temp_m_axi_awid_reg; - m_axi_awaddr_reg <= temp_m_axi_awaddr_reg; - m_axi_awlen_reg <= temp_m_axi_awlen_reg; - m_axi_awsize_reg <= temp_m_axi_awsize_reg; - m_axi_awburst_reg <= temp_m_axi_awburst_reg; - m_axi_awlock_reg <= temp_m_axi_awlock_reg; - m_axi_awcache_reg <= temp_m_axi_awcache_reg; - m_axi_awprot_reg <= temp_m_axi_awprot_reg; - m_axi_awqos_reg <= temp_m_axi_awqos_reg; - m_axi_awregion_reg <= temp_m_axi_awregion_reg; - m_axi_awuser_reg <= temp_m_axi_awuser_reg; - end - - if (store_axi_aw_input_to_temp) begin - temp_m_axi_awid_reg <= s_axi_awid; - temp_m_axi_awaddr_reg <= s_axi_awaddr; - temp_m_axi_awlen_reg <= s_axi_awlen; - temp_m_axi_awsize_reg <= s_axi_awsize; - temp_m_axi_awburst_reg <= s_axi_awburst; - temp_m_axi_awlock_reg <= s_axi_awlock; - temp_m_axi_awcache_reg <= s_axi_awcache; - temp_m_axi_awprot_reg <= s_axi_awprot; - temp_m_axi_awqos_reg <= s_axi_awqos; - temp_m_axi_awregion_reg <= s_axi_awregion; - temp_m_axi_awuser_reg <= s_axi_awuser; - end -end - -end else if (AW_REG_TYPE == 1) begin -// simple register, inserts bubble cycles - -// datapath registers -reg s_axi_awready_reg = 1'b0; - -reg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] m_axi_awlen_reg = 8'd0; -reg [2:0] m_axi_awsize_reg = 3'd0; -reg [1:0] m_axi_awburst_reg = 2'd0; -reg m_axi_awlock_reg = 1'b0; -reg [3:0] m_axi_awcache_reg = 4'd0; -reg [2:0] m_axi_awprot_reg = 3'd0; -reg [3:0] m_axi_awqos_reg = 4'd0; -reg [3:0] m_axi_awregion_reg = 4'd0; -reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}}; -reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next; - -// datapath control -reg store_axi_aw_input_to_output; - -assign s_axi_awready = s_axi_awready_reg; - -assign m_axi_awid = m_axi_awid_reg; -assign m_axi_awaddr = m_axi_awaddr_reg; -assign m_axi_awlen = m_axi_awlen_reg; -assign m_axi_awsize = m_axi_awsize_reg; -assign m_axi_awburst = m_axi_awburst_reg; -assign m_axi_awlock = m_axi_awlock_reg; -assign m_axi_awcache = m_axi_awcache_reg; -assign m_axi_awprot = m_axi_awprot_reg; -assign m_axi_awqos = m_axi_awqos_reg; -assign m_axi_awregion = m_axi_awregion_reg; -assign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}}; -assign m_axi_awvalid = m_axi_awvalid_reg; - -// enable ready input next cycle if output buffer will be empty -wire s_axi_awready_eawly = !m_axi_awvalid_next; - -always @* begin - // transfer sink ready state to source - m_axi_awvalid_next = m_axi_awvalid_reg; - - store_axi_aw_input_to_output = 1'b0; - - if (s_axi_awready_reg) begin - m_axi_awvalid_next = s_axi_awvalid; - store_axi_aw_input_to_output = 1'b1; - end else if (m_axi_awready) begin - m_axi_awvalid_next = 1'b0; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_awready_reg <= 1'b0; - m_axi_awvalid_reg <= 1'b0; - end else begin - s_axi_awready_reg <= s_axi_awready_eawly; - m_axi_awvalid_reg <= m_axi_awvalid_next; - end - - // datapath - if (store_axi_aw_input_to_output) begin - m_axi_awid_reg <= s_axi_awid; - m_axi_awaddr_reg <= s_axi_awaddr; - m_axi_awlen_reg <= s_axi_awlen; - m_axi_awsize_reg <= s_axi_awsize; - m_axi_awburst_reg <= s_axi_awburst; - m_axi_awlock_reg <= s_axi_awlock; - m_axi_awcache_reg <= s_axi_awcache; - m_axi_awprot_reg <= s_axi_awprot; - m_axi_awqos_reg <= s_axi_awqos; - m_axi_awregion_reg <= s_axi_awregion; - m_axi_awuser_reg <= s_axi_awuser; - end -end - -end else begin - - // bypass AW channel - assign m_axi_awid = s_axi_awid; - assign m_axi_awaddr = s_axi_awaddr; - assign m_axi_awlen = s_axi_awlen; - assign m_axi_awsize = s_axi_awsize; - assign m_axi_awburst = s_axi_awburst; - assign m_axi_awlock = s_axi_awlock; - assign m_axi_awcache = s_axi_awcache; - assign m_axi_awprot = s_axi_awprot; - assign m_axi_awqos = s_axi_awqos; - assign m_axi_awregion = s_axi_awregion; - assign m_axi_awuser = AWUSER_ENABLE ? s_axi_awuser : {AWUSER_WIDTH{1'b0}}; - assign m_axi_awvalid = s_axi_awvalid; - assign s_axi_awready = m_axi_awready; - -end - -// W channel - -if (W_REG_TYPE > 1) begin -// skid buffer, no bubble cycles - -// datapath registers -reg s_axi_wready_reg = 1'b0; - -reg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}}; -reg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}}; -reg m_axi_wlast_reg = 1'b0; -reg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}}; -reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next; - -reg [DATA_WIDTH-1:0] temp_m_axi_wdata_reg = {DATA_WIDTH{1'b0}}; -reg [STRB_WIDTH-1:0] temp_m_axi_wstrb_reg = {STRB_WIDTH{1'b0}}; -reg temp_m_axi_wlast_reg = 1'b0; -reg [WUSER_WIDTH-1:0] temp_m_axi_wuser_reg = {WUSER_WIDTH{1'b0}}; -reg temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next; - -// datapath control -reg store_axi_w_input_to_output; -reg store_axi_w_input_to_temp; -reg store_axi_w_temp_to_output; - -assign s_axi_wready = s_axi_wready_reg; - -assign m_axi_wdata = m_axi_wdata_reg; -assign m_axi_wstrb = m_axi_wstrb_reg; -assign m_axi_wlast = m_axi_wlast_reg; -assign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}}; -assign m_axi_wvalid = m_axi_wvalid_reg; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -wire s_axi_wready_early = m_axi_wready | (~temp_m_axi_wvalid_reg & (~m_axi_wvalid_reg | ~s_axi_wvalid)); - -always @* begin - // transfer sink ready state to source - m_axi_wvalid_next = m_axi_wvalid_reg; - temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg; - - store_axi_w_input_to_output = 1'b0; - store_axi_w_input_to_temp = 1'b0; - store_axi_w_temp_to_output = 1'b0; - - if (s_axi_wready_reg) begin - // input is ready - if (m_axi_wready | ~m_axi_wvalid_reg) begin - // output is ready or currently not valid, transfer data to output - m_axi_wvalid_next = s_axi_wvalid; - store_axi_w_input_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_m_axi_wvalid_next = s_axi_wvalid; - store_axi_w_input_to_temp = 1'b1; - end - end else if (m_axi_wready) begin - // input is not ready, but output is ready - m_axi_wvalid_next = temp_m_axi_wvalid_reg; - temp_m_axi_wvalid_next = 1'b0; - store_axi_w_temp_to_output = 1'b1; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_wready_reg <= 1'b0; - m_axi_wvalid_reg <= 1'b0; - temp_m_axi_wvalid_reg <= 1'b0; - end else begin - s_axi_wready_reg <= s_axi_wready_early; - m_axi_wvalid_reg <= m_axi_wvalid_next; - temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next; - end - - // datapath - if (store_axi_w_input_to_output) begin - m_axi_wdata_reg <= s_axi_wdata; - m_axi_wstrb_reg <= s_axi_wstrb; - m_axi_wlast_reg <= s_axi_wlast; - m_axi_wuser_reg <= s_axi_wuser; - end else if (store_axi_w_temp_to_output) begin - m_axi_wdata_reg <= temp_m_axi_wdata_reg; - m_axi_wstrb_reg <= temp_m_axi_wstrb_reg; - m_axi_wlast_reg <= temp_m_axi_wlast_reg; - m_axi_wuser_reg <= temp_m_axi_wuser_reg; - end - - if (store_axi_w_input_to_temp) begin - temp_m_axi_wdata_reg <= s_axi_wdata; - temp_m_axi_wstrb_reg <= s_axi_wstrb; - temp_m_axi_wlast_reg <= s_axi_wlast; - temp_m_axi_wuser_reg <= s_axi_wuser; - end -end - -end else if (W_REG_TYPE == 1) begin -// simple register, inserts bubble cycles - -// datapath registers -reg s_axi_wready_reg = 1'b0; - -reg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}}; -reg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}}; -reg m_axi_wlast_reg = 1'b0; -reg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}}; -reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next; - -// datapath control -reg store_axi_w_input_to_output; - -assign s_axi_wready = s_axi_wready_reg; - -assign m_axi_wdata = m_axi_wdata_reg; -assign m_axi_wstrb = m_axi_wstrb_reg; -assign m_axi_wlast = m_axi_wlast_reg; -assign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}}; -assign m_axi_wvalid = m_axi_wvalid_reg; - -// enable ready input next cycle if output buffer will be empty -wire s_axi_wready_ewly = !m_axi_wvalid_next; - -always @* begin - // transfer sink ready state to source - m_axi_wvalid_next = m_axi_wvalid_reg; - - store_axi_w_input_to_output = 1'b0; - - if (s_axi_wready_reg) begin - m_axi_wvalid_next = s_axi_wvalid; - store_axi_w_input_to_output = 1'b1; - end else if (m_axi_wready) begin - m_axi_wvalid_next = 1'b0; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_wready_reg <= 1'b0; - m_axi_wvalid_reg <= 1'b0; - end else begin - s_axi_wready_reg <= s_axi_wready_ewly; - m_axi_wvalid_reg <= m_axi_wvalid_next; - end - - // datapath - if (store_axi_w_input_to_output) begin - m_axi_wdata_reg <= s_axi_wdata; - m_axi_wstrb_reg <= s_axi_wstrb; - m_axi_wlast_reg <= s_axi_wlast; - m_axi_wuser_reg <= s_axi_wuser; - end -end - -end else begin - - // bypass W channel - assign m_axi_wdata = s_axi_wdata; - assign m_axi_wstrb = s_axi_wstrb; - assign m_axi_wlast = s_axi_wlast; - assign m_axi_wuser = WUSER_ENABLE ? s_axi_wuser : {WUSER_WIDTH{1'b0}}; - assign m_axi_wvalid = s_axi_wvalid; - assign s_axi_wready = m_axi_wready; - -end - -// B channel - -if (B_REG_TYPE > 1) begin -// skid buffer, no bubble cycles - -// datapath registers -reg m_axi_bready_reg = 1'b0; - -reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}; -reg [1:0] s_axi_bresp_reg = 2'b0; -reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}}; -reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next; - -reg [ID_WIDTH-1:0] temp_s_axi_bid_reg = {ID_WIDTH{1'b0}}; -reg [1:0] temp_s_axi_bresp_reg = 2'b0; -reg [BUSER_WIDTH-1:0] temp_s_axi_buser_reg = {BUSER_WIDTH{1'b0}}; -reg temp_s_axi_bvalid_reg = 1'b0, temp_s_axi_bvalid_next; - -// datapath control -reg store_axi_b_input_to_output; -reg store_axi_b_input_to_temp; -reg store_axi_b_temp_to_output; - -assign m_axi_bready = m_axi_bready_reg; - -assign s_axi_bid = s_axi_bid_reg; -assign s_axi_bresp = s_axi_bresp_reg; -assign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}}; -assign s_axi_bvalid = s_axi_bvalid_reg; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -wire m_axi_bready_early = s_axi_bready | (~temp_s_axi_bvalid_reg & (~s_axi_bvalid_reg | ~m_axi_bvalid)); - -always @* begin - // transfer sink ready state to source - s_axi_bvalid_next = s_axi_bvalid_reg; - temp_s_axi_bvalid_next = temp_s_axi_bvalid_reg; - - store_axi_b_input_to_output = 1'b0; - store_axi_b_input_to_temp = 1'b0; - store_axi_b_temp_to_output = 1'b0; - - if (m_axi_bready_reg) begin - // input is ready - if (s_axi_bready | ~s_axi_bvalid_reg) begin - // output is ready or currently not valid, transfer data to output - s_axi_bvalid_next = m_axi_bvalid; - store_axi_b_input_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_s_axi_bvalid_next = m_axi_bvalid; - store_axi_b_input_to_temp = 1'b1; - end - end else if (s_axi_bready) begin - // input is not ready, but output is ready - s_axi_bvalid_next = temp_s_axi_bvalid_reg; - temp_s_axi_bvalid_next = 1'b0; - store_axi_b_temp_to_output = 1'b1; - end -end - -always @(posedge clk) begin - if (rst) begin - m_axi_bready_reg <= 1'b0; - s_axi_bvalid_reg <= 1'b0; - temp_s_axi_bvalid_reg <= 1'b0; - end else begin - m_axi_bready_reg <= m_axi_bready_early; - s_axi_bvalid_reg <= s_axi_bvalid_next; - temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next; - end - - // datapath - if (store_axi_b_input_to_output) begin - s_axi_bid_reg <= m_axi_bid; - s_axi_bresp_reg <= m_axi_bresp; - s_axi_buser_reg <= m_axi_buser; - end else if (store_axi_b_temp_to_output) begin - s_axi_bid_reg <= temp_s_axi_bid_reg; - s_axi_bresp_reg <= temp_s_axi_bresp_reg; - s_axi_buser_reg <= temp_s_axi_buser_reg; - end - - if (store_axi_b_input_to_temp) begin - temp_s_axi_bid_reg <= m_axi_bid; - temp_s_axi_bresp_reg <= m_axi_bresp; - temp_s_axi_buser_reg <= m_axi_buser; - end -end - -end else if (B_REG_TYPE == 1) begin -// simple register, inserts bubble cycles - -// datapath registers -reg m_axi_bready_reg = 1'b0; - -reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}; -reg [1:0] s_axi_bresp_reg = 2'b0; -reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}}; -reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next; - -// datapath control -reg store_axi_b_input_to_output; - -assign m_axi_bready = m_axi_bready_reg; - -assign s_axi_bid = s_axi_bid_reg; -assign s_axi_bresp = s_axi_bresp_reg; -assign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}}; -assign s_axi_bvalid = s_axi_bvalid_reg; - -// enable ready input next cycle if output buffer will be empty -wire m_axi_bready_early = !s_axi_bvalid_next; - -always @* begin - // transfer sink ready state to source - s_axi_bvalid_next = s_axi_bvalid_reg; - - store_axi_b_input_to_output = 1'b0; - - if (m_axi_bready_reg) begin - s_axi_bvalid_next = m_axi_bvalid; - store_axi_b_input_to_output = 1'b1; - end else if (s_axi_bready) begin - s_axi_bvalid_next = 1'b0; - end -end - -always @(posedge clk) begin - if (rst) begin - m_axi_bready_reg <= 1'b0; - s_axi_bvalid_reg <= 1'b0; - end else begin - m_axi_bready_reg <= m_axi_bready_early; - s_axi_bvalid_reg <= s_axi_bvalid_next; - end - - // datapath - if (store_axi_b_input_to_output) begin - s_axi_bid_reg <= m_axi_bid; - s_axi_bresp_reg <= m_axi_bresp; - s_axi_buser_reg <= m_axi_buser; - end -end - -end else begin - - // bypass B channel - assign s_axi_bid = m_axi_bid; - assign s_axi_bresp = m_axi_bresp; - assign s_axi_buser = BUSER_ENABLE ? m_axi_buser : {BUSER_WIDTH{1'b0}}; - assign s_axi_bvalid = m_axi_bvalid; - assign m_axi_bready = s_axi_bready; - -end - -endgenerate - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_float_v16.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_float_v16.v deleted file mode 100644 index c04fd3cb..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_float_v16.v +++ /dev/null @@ -1,193 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="black_hole_float_v16_black_hole_float_v16,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.215450,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=6,HLS_SYN_LUT=43,HLS_VERSION=2022_2}" *) - -module black_hole_float_v16 ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_in_s_dout, - fifo_in_s_empty_n, - fifo_in_s_read, - fifo_in_peek_dout, - fifo_in_peek_empty_n, - fifo_in_peek_read -); - -parameter ap_ST_fsm_state1 = 3'd1; -parameter ap_ST_fsm_state2 = 3'd2; -parameter ap_ST_fsm_state3 = 3'd4; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [512:0] fifo_in_s_dout; -input fifo_in_s_empty_n; -output fifo_in_s_read; -input [512:0] fifo_in_peek_dout; -input fifo_in_peek_empty_n; -output fifo_in_peek_read; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg fifo_in_s_read; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_start; -wire grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_done; -wire grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_idle; -wire grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_ready; -wire grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_fifo_in_s_read; -reg grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_start_reg; -wire ap_CS_fsm_state2; -wire ap_CS_fsm_state3; -reg [2:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 3'd1; -#0 grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_start_reg = 1'b0; -end - -black_hole_float_v16_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_start), - .ap_done(grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_done), - .ap_idle(grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_idle), - .ap_ready(grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_ready), - .fifo_in_s_dout(fifo_in_s_dout), - .fifo_in_s_empty_n(fifo_in_s_empty_n), - .fifo_in_s_read(grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_fifo_in_s_read) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state2)) begin - grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_start_reg <= 1'b1; - end else if ((grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_ready == 1'b1)) begin - grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_start_reg <= 1'b0; - end - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if ((grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_done == 1'b0)) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -always @ (*) begin - if (((grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_in_s_read = grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_fifo_in_s_read; - end else begin - fifo_in_s_read = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state3; - end - ap_ST_fsm_state3 : begin - if (((grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign fifo_in_peek_read = 1'b0; - -assign grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_start = grp_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_fu_44_ap_start_reg; - -endmodule //black_hole_float_v16 diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_float_v16_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_float_v16_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.v deleted file mode 100644 index 37ca67f9..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_float_v16_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.v +++ /dev/null @@ -1,118 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module black_hole_float_v16_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_in_s_dout, - fifo_in_s_empty_n, - fifo_in_s_read -); - -parameter ap_ST_fsm_state1 = 2'd1; -parameter ap_ST_fsm_state2 = 2'd2; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [512:0] fifo_in_s_dout; -input fifo_in_s_empty_n; -output fifo_in_s_read; - -reg ap_done; -reg ap_idle; -reg fifo_in_s_read; - -(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire ap_CS_fsm_state2; -reg [1:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 2'd1; -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((fifo_in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - fifo_in_s_read = 1'b1; - end else begin - fifo_in_s_read = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state2; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_ready = 1'b0; - -endmodule //black_hole_float_v16_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_int.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_int.v deleted file mode 100644 index 3fadb780..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_int.v +++ /dev/null @@ -1,193 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="black_hole_int_black_hole_int,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.215450,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=6,HLS_SYN_LUT=43,HLS_VERSION=2022_2}" *) - -module black_hole_int ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_in_s_dout, - fifo_in_s_empty_n, - fifo_in_s_read, - fifo_in_peek_dout, - fifo_in_peek_empty_n, - fifo_in_peek_read -); - -parameter ap_ST_fsm_state1 = 3'd1; -parameter ap_ST_fsm_state2 = 3'd2; -parameter ap_ST_fsm_state3 = 3'd4; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [32:0] fifo_in_s_dout; -input fifo_in_s_empty_n; -output fifo_in_s_read; -input [32:0] fifo_in_peek_dout; -input fifo_in_peek_empty_n; -output fifo_in_peek_read; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg fifo_in_s_read; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_start; -wire grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_done; -wire grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_idle; -wire grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_ready; -wire grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_fifo_in_s_read; -reg grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_start_reg; -wire ap_CS_fsm_state2; -wire ap_CS_fsm_state3; -reg [2:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 3'd1; -#0 grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_start_reg = 1'b0; -end - -black_hole_int_black_hole_int_Pipeline_VITIS_LOOP_399_1 grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_start), - .ap_done(grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_done), - .ap_idle(grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_idle), - .ap_ready(grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_ready), - .fifo_in_s_dout(fifo_in_s_dout), - .fifo_in_s_empty_n(fifo_in_s_empty_n), - .fifo_in_s_read(grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_fifo_in_s_read) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state2)) begin - grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_start_reg <= 1'b1; - end else if ((grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_ready == 1'b1)) begin - grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_start_reg <= 1'b0; - end - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if ((grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_done == 1'b0)) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -always @ (*) begin - if (((grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - fifo_in_s_read = grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_fifo_in_s_read; - end else begin - fifo_in_s_read = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state3; - end - ap_ST_fsm_state3 : begin - if (((grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign fifo_in_peek_read = 1'b0; - -assign grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_start = grp_black_hole_int_Pipeline_VITIS_LOOP_399_1_fu_44_ap_start_reg; - -endmodule //black_hole_int diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_int_black_hole_int_Pipeline_VITIS_LOOP_399_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_int_black_hole_int_Pipeline_VITIS_LOOP_399_1.v deleted file mode 100644 index b836045f..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/black_hole_int_black_hole_int_Pipeline_VITIS_LOOP_399_1.v +++ /dev/null @@ -1,118 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module black_hole_int_black_hole_int_Pipeline_VITIS_LOOP_399_1 ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - fifo_in_s_dout, - fifo_in_s_empty_n, - fifo_in_s_read -); - -parameter ap_ST_fsm_state1 = 2'd1; -parameter ap_ST_fsm_state2 = 2'd2; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [32:0] fifo_in_s_dout; -input fifo_in_s_empty_n; -output fifo_in_s_read; - -reg ap_done; -reg ap_idle; -reg fifo_in_s_read; - -(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire ap_CS_fsm_state2; -reg [1:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 2'd1; -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((fifo_in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - fifo_in_s_read = 1'b1; - end else begin - fifo_in_s_read = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state2; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_ready = 1'b0; - -endmodule //black_hole_int_black_hole_int_Pipeline_VITIS_LOOP_399_1 diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/detect_burst.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/detect_burst.v deleted file mode 100644 index 8abeaa66..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/detect_burst.v +++ /dev/null @@ -1,156 +0,0 @@ -`default_nettype none - -// Detect burst from address stream. -module detect_burst #( - parameter AddrWidth = 64, - parameter DataWidthBytesLog = 6, - parameter WaitTimeWidth = 4, - parameter BurstLenWidth = 8 -) ( - input wire clk, - input wire rst, - - input wire [WaitTimeWidth-1:0] max_wait_time, - input wire [BurstLenWidth-1:0] max_burst_len, // 0 disables detection - - input wire [AddrWidth-1:0] addr_dout, - input wire addr_empty_n, - output reg addr_read, - - output wire [BurstLenWidth+AddrWidth-1:0] addr_din, - input wire addr_full_n, - output wire addr_write, - - output wire [BurstLenWidth-1:0] burst_len_0_din, - input wire burst_len_0_full_n, - output wire burst_len_0_write, - - output wire [BurstLenWidth-1:0] burst_len_1_din, - input wire burst_len_1_full_n, - output wire burst_len_1_write -); - // parameter - localparam NextAddrWidth = AddrWidth - DataWidthBytesLog; - - // state - reg [AddrWidth-1:0] base_addr; - reg base_valid; - reg [BurstLenWidth-1:0] burst_len; - reg [WaitTimeWidth-1:0] wait_time; - reg [NextAddrWidth-1:0] next_addr; - - // logic - reg write_enable; - reg [AddrWidth-1:0] base_addr_next; - reg base_valid_next; - reg [BurstLenWidth-1:0] burst_len_next; - reg [WaitTimeWidth-1:0] wait_time_next; - - wire [NextAddrWidth-1:0] next_addr_next = - base_addr_next[AddrWidth-1:DataWidthBytesLog] + - {{(NextAddrWidth-BurstLenWidth){1'b0}}, burst_len_next} + - {{(NextAddrWidth-1){1'b0}}, 1'b1}; - - assign addr_write = write_enable; - assign burst_len_0_write = write_enable; - assign burst_len_1_write = write_enable; - assign addr_din = {burst_len, base_addr}; - assign burst_len_0_din = burst_len; - assign burst_len_1_din = burst_len; - - // register the input for timing closure - reg addr_empty_n_q; - reg [AddrWidth-1:0] addr_dout_q; - always @(posedge clk) begin - if (addr_full_n && burst_len_0_full_n && burst_len_1_full_n) begin - addr_empty_n_q <= addr_empty_n; - addr_dout_q <= addr_dout; - end - end - wire [AddrWidth-1:0] curr_addr = addr_dout_q; - - always @* begin - // defaults - addr_read = 1'b0; - if (!addr_full_n || !burst_len_0_full_n || !burst_len_1_full_n) begin - addr_read = 1'b0; - end else if (addr_empty_n) begin - // read new item if non-empty - addr_read = 1'b1; - end else if (base_valid) begin - addr_read = 1'b0; - end - end - - always @* begin - // defaults - write_enable = 1'b0; - base_addr_next = base_addr; - base_valid_next = base_valid; - wait_time_next = wait_time; - burst_len_next = burst_len; - if (!addr_full_n || !burst_len_0_full_n || !burst_len_1_full_n) begin - // output FIFO full, do nothing - end else if (addr_empty_n_q) begin - wait_time_next = 0; - if (!base_valid) begin - base_addr_next = curr_addr; - base_valid_next = 1'b1; - - write_enable = 1'b0; - burst_len_next = burst_len; - end else begin - if (next_addr == curr_addr[AddrWidth-1:DataWidthBytesLog] && - burst_len < max_burst_len) begin - burst_len_next = burst_len + 1; - - write_enable = 1'b0; - base_addr_next = base_addr; - base_valid_next = base_valid; - end else begin - // no more burst detected - write_enable = 1'b1; - burst_len_next = 0; - base_addr_next = curr_addr; - - base_valid_next = base_valid; - end - end - end else if (base_valid) begin - if (wait_time < max_wait_time) begin - wait_time_next = wait_time + 1; - - write_enable = 1'b0; - base_addr_next = base_addr; - base_valid_next = base_valid; - burst_len_next = burst_len; - end else begin - write_enable = 1'b1; - wait_time_next = 0; - base_valid_next = 1'b0; - burst_len_next = 0; - - base_addr_next = base_addr; - end - end - end - - always @(posedge clk) begin - if (rst) begin - base_addr <= {AddrWidth{1'b0}}; - base_valid <= 1'd0; - burst_len <= {BurstLenWidth{1'b0}}; - wait_time <= {WaitTimeWidth{1'b0}}; - next_addr <= {{(NextAddrWidth-1){1'b0}}, 1'b1}; - end else begin - base_addr <= base_addr_next; - base_valid <= base_valid_next; - burst_len <= burst_len_next; - wait_time <= wait_time_next; - next_addr <= next_addr_next; - end - end - -endmodule // detect_burst - -`default_nettype wire diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo.v deleted file mode 100644 index d2559d97..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo.v +++ /dev/null @@ -1,107 +0,0 @@ -`default_nettype none - -// first-word fall-through (FWFT) FIFO -module fifo #( - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 5, - parameter DEPTH = 32 -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - -generate - if (DEPTH == 1) begin : d1 - fifo_fwd #( - .DATA_WIDTH(DATA_WIDTH) - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end else if (DATA_WIDTH >= 36 && DEPTH >= 4096) begin : uram - fifo_bram #( - .MEM_STYLE ("ultra"), - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .DEPTH (DEPTH) - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end else if (DEPTH >=128) begin : bram - fifo_bram #( - .MEM_STYLE ("block"), - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .DEPTH (DEPTH) - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end else begin : srl - fifo_srl #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .DEPTH (DEPTH) - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end -endgenerate - -endmodule // fifo - -`default_nettype wire diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo_bram.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo_bram.v deleted file mode 100644 index 8b5aea64..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo_bram.v +++ /dev/null @@ -1,151 +0,0 @@ -`default_nettype none - -// first-word fall-through (FWFT) FIFO using block RAM -// based on HLS generated code -module fifo_bram #( - parameter MEM_STYLE = "auto", - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 5, - parameter DEPTH = 32 -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - -(* ram_style = MEM_STYLE *) -reg [DATA_WIDTH-1:0] mem[0:DEPTH-1]; -reg [DATA_WIDTH-1:0] q_buf; -reg [ADDR_WIDTH-1:0] waddr; -reg [ADDR_WIDTH-1:0] raddr; -wire [ADDR_WIDTH-1:0] wnext; -wire [ADDR_WIDTH-1:0] rnext; -wire push; -wire pop; -reg [ADDR_WIDTH-1:0] used; -reg full_n; -reg empty_n; -reg [DATA_WIDTH-1:0] q_tmp; -reg show_ahead; -reg [DATA_WIDTH-1:0] dout_buf; -reg dout_valid; - -localparam DepthM1 = DEPTH[ADDR_WIDTH-1:0] - 1'd1; - -assign if_full_n = full_n; -assign if_empty_n = dout_valid; -assign if_dout = dout_buf; -assign push = full_n & if_write_ce & if_write; -assign pop = empty_n & if_read_ce & (~dout_valid | if_read); -assign wnext = !push ? waddr : - (waddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : waddr + 1'd1; -assign rnext = !pop ? raddr : - (raddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : raddr + 1'd1; - -// waddr -always @(posedge clk) begin - if (reset) - waddr <= {ADDR_WIDTH{1'b0}}; - else - waddr <= wnext; -end - -// raddr -always @(posedge clk) begin - if (reset) - raddr <= {ADDR_WIDTH{1'b0}}; - else - raddr <= rnext; -end - -// used -always @(posedge clk) begin - if (reset) - used <= {ADDR_WIDTH{1'b0}}; - else if (push && !pop) - used <= used + 1'b1; - else if (!push && pop) - used <= used - 1'b1; -end - -// full_n -always @(posedge clk) begin - if (reset) - full_n <= 1'b1; - else if (push && !pop) - full_n <= (used != DepthM1); - else if (!push && pop) - full_n <= 1'b1; -end - -// empty_n -always @(posedge clk) begin - if (reset) - empty_n <= 1'b0; - else if (push && !pop) - empty_n <= 1'b1; - else if (!push && pop) - empty_n <= (used != {{(ADDR_WIDTH-1){1'b0}},1'b1}); -end - -// mem -always @(posedge clk) begin - if (push) - mem[waddr] <= if_din; -end - -// q_buf -always @(posedge clk) begin - q_buf <= mem[rnext]; -end - -// q_tmp -always @(posedge clk) begin - if (reset) - q_tmp <= {DATA_WIDTH{1'b0}}; - else if (push) - q_tmp <= if_din; -end - -// show_ahead -always @(posedge clk) begin - if (reset) - show_ahead <= 1'b0; - else if (push && used == {{(ADDR_WIDTH-1){1'b0}},pop}) - show_ahead <= 1'b1; - else - show_ahead <= 1'b0; -end - -// dout_buf -always @(posedge clk) begin - if (reset) - dout_buf <= {DATA_WIDTH{1'b0}}; - else if (pop) - dout_buf <= show_ahead? q_tmp : q_buf; -end - -// dout_valid -always @(posedge clk) begin - if (reset) - dout_valid <= 1'b0; - else if (pop) - dout_valid <= 1'b1; - else if (if_read_ce & if_read) - dout_valid <= 1'b0; -end - -endmodule // fifo_bram - -`default_nettype wire diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo_fwd.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo_fwd.v deleted file mode 100644 index 870695ea..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo_fwd.v +++ /dev/null @@ -1,58 +0,0 @@ -`default_nettype none - -// first-word fall-through (FWFT) FIFO with latency=0 and depth=1 -module fifo_fwd #( - parameter MEM_STYLE = "", // ignored - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 0, // ignored - parameter DEPTH = 1 // ignored -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - reg [DATA_WIDTH-1:0] mem; - reg is_mem_valid; - - // If mem is valid, the FIFO is not empty and is full; if read, mem becomes - // invalid. If mem is not valid, the FIFO is not empty if and only if written - // and is not full; if written but not read, mem becomes valid. - - assign if_empty_n = is_mem_valid || (if_write && if_write_ce); - assign if_full_n = !is_mem_valid; - assign if_dout = is_mem_valid ? mem : if_din; - - always @(posedge clk) begin - if (reset) begin - is_mem_valid <= 1'b0; - end else begin - if (is_mem_valid) begin - if (if_read && if_read_ce) begin - is_mem_valid <= 1'b0; - end - end else begin - if (if_write && if_write_ce && !(if_read && if_read_ce)) begin - is_mem_valid <= 1'b1; - end - end - - if (if_write && if_write_ce) begin - mem <= if_din; - end - end - end - -endmodule // fifo_fwd - -`default_nettype wire diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo_srl.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo_srl.v deleted file mode 100644 index 8ed7a247..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/fifo_srl.v +++ /dev/null @@ -1,84 +0,0 @@ -`default_nettype none - -// first-word fall-through (FWFT) FIFO using shift register LUT -// based on HLS generated code -module fifo_srl #( - parameter MEM_STYLE = "shiftreg", - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 5, - parameter DEPTH = 32 -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - parameter REAL_DEPTH = DEPTH < 4 ? 4 : DEPTH; - parameter REAL_ADDR_WIDTH = $clog2(REAL_DEPTH)+1; - - wire [REAL_ADDR_WIDTH - 1:0] shift_reg_addr; - wire [DATA_WIDTH - 1:0] shift_reg_data; - wire [DATA_WIDTH - 1:0] shift_reg_q; - wire shift_reg_ce; - reg [REAL_ADDR_WIDTH:0] out_ptr; - reg internal_empty_n; - reg internal_full_n; - - (* shreg_extract = "yes" *) reg [DATA_WIDTH-1:0] mem [0:REAL_DEPTH-1]; - - assign if_empty_n = internal_empty_n; - assign if_full_n = internal_full_n; - assign shift_reg_data = if_din; - assign if_dout = shift_reg_q; - - assign shift_reg_addr = out_ptr[REAL_ADDR_WIDTH] == 1'b0 ? out_ptr[REAL_ADDR_WIDTH-1:0] : {REAL_ADDR_WIDTH{1'b0}}; - assign shift_reg_ce = (if_write & if_write_ce) & internal_full_n; - - assign shift_reg_q = mem[shift_reg_addr]; - - always @(posedge clk) begin - if (reset) begin - out_ptr <= ~{REAL_ADDR_WIDTH+1{1'b0}}; - internal_empty_n <= 1'b0; - internal_full_n <= 1'b1; - end else begin - if (((if_read && if_read_ce) && internal_empty_n) && - (!(if_write && if_write_ce) || !internal_full_n)) begin - out_ptr <= out_ptr - 1'b1; - if (out_ptr == {(REAL_ADDR_WIDTH+1){1'b0}}) - internal_empty_n <= 1'b0; - internal_full_n <= 1'b1; - end - else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && - ((if_write & if_write_ce) == 1 & internal_full_n == 1)) - begin - out_ptr <= out_ptr + 1'b1; - internal_empty_n <= 1'b1; - if (out_ptr == REAL_DEPTH - {{(REAL_ADDR_WIDTH-1){1'b0}}, 2'd2}) - internal_full_n <= 1'b0; - end - end - end - - integer i; - always @(posedge clk) begin - if (shift_reg_ce) begin - for (i = 0; i < REAL_DEPTH - 1; i = i + 1) - mem[i + 1] <= mem[i]; - mem[0] <= shift_reg_data; - end - end - -endmodule // fifo_srl - -`default_nettype wire diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/generate_last.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/generate_last.v deleted file mode 100644 index f592117d..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/generate_last.v +++ /dev/null @@ -1,71 +0,0 @@ -`default_nettype none - -module generate_last #( - parameter BurstLenWidth = 8 -) ( - input wire clk, - input wire rst, - - input wire [BurstLenWidth-1:0] burst_len_dout, - input wire burst_len_empty_n, - output reg burst_len_read, - - output reg last_din, - input wire last_full_n, - output reg last_write -); - - // state - reg busy; - reg [BurstLenWidth-1:0] count; - - // logic - reg busy_next; - reg [BurstLenWidth-1:0] count_next; - - always @* begin - busy_next = busy; - count_next = count; - burst_len_read = 1'b0; - last_write = 1'b0; - - if (last_full_n) begin - if (busy == 1'b0) begin - if (burst_len_empty_n) begin - // read from burst_len - burst_len_read = 1'b1; - count_next = burst_len_dout; - - // write to last - last_write = 1'b1; - last_din = ~|count_next; - - // change busy - if (|count_next) busy_next = 1'b1; - end - end else begin - count_next = count - 1'b1; - - // write to last - last_write = 1'b1; - last_din = ~|count_next; - - // change busy - if (~|count_next) busy_next = 1'b0; - end - end - end - - always @(posedge clk) begin - if (rst) begin - busy <= 1'b0; - count <= {BurstLenWidth{1'b0}}; - end else begin - busy <= busy_next; - count <= count_next; - end - end - -endmodule // generate_last - -`default_nettype wire diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/priority_encoder.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/priority_encoder.v deleted file mode 100644 index cf82512b..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/priority_encoder.v +++ /dev/null @@ -1,92 +0,0 @@ -/* - -Copyright (c) 2014-2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Priority encoder module - */ -module priority_encoder # -( - parameter WIDTH = 4, - // LSB priority selection - parameter LSB_HIGH_PRIORITY = 0 -) -( - input wire [WIDTH-1:0] input_unencoded, - output wire output_valid, - output wire [$clog2(WIDTH)-1:0] output_encoded, - output wire [WIDTH-1:0] output_unencoded -); - -parameter LEVELS = WIDTH > 2 ? $clog2(WIDTH) : 1; -parameter W = 2**LEVELS; - -// pad input to even power of two -wire [W-1:0] input_padded = {{W-WIDTH{1'b0}}, input_unencoded}; - -wire [W/2-1:0] stage_valid[LEVELS-1:0]; -wire [W/2-1:0] stage_enc[LEVELS-1:0]; - -generate - genvar l, n; - - // process input bits; generate valid bit and encoded bit for each pair - for (n = 0; n < W/2; n = n + 1) begin : loop_in - assign stage_valid[0][n] = |input_padded[n*2+1:n*2]; - if (LSB_HIGH_PRIORITY) begin - // bit 0 is highest priority - assign stage_enc[0][n] = !input_padded[n*2+0]; - end else begin - // bit 0 is lowest priority - assign stage_enc[0][n] = input_padded[n*2+1]; - end - end - - // compress down to single valid bit and encoded bus - for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels - for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress - assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2]; - if (LSB_HIGH_PRIORITY) begin - // bit 0 is highest priority - assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]}; - end else begin - // bit 0 is lowest priority - assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]}; - end - end - end -endgenerate - -assign output_valid = stage_valid[LEVELS-1]; -assign output_encoded = stage_enc[LEVELS-1]; -assign output_unencoded = 1 << output_encoded; - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A.v deleted file mode 100644 index 4512bcfd..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A.v +++ /dev/null @@ -1,374 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="read_A_read_A,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=40036,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=132,HLS_SYN_LUT=346,HLS_VERSION=2022_2}" *) - -module read_A ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - A_read_addr_din, - A_read_addr_full_n, - A_read_addr_write, - A_read_data_s_dout, - A_read_data_s_empty_n, - A_read_data_s_read, - A_read_data_peek_dout, - A_read_data_peek_empty_n, - A_read_data_peek_read, - A_write_addr_din, - A_write_addr_full_n, - A_write_addr_write, - A_write_data_din, - A_write_data_full_n, - A_write_data_write, - A_write_resp_s_dout, - A_write_resp_s_empty_n, - A_write_resp_s_read, - A_write_resp_peek_dout, - A_write_resp_peek_empty_n, - A_write_resp_peek_read, - fifo_A_din, - fifo_A_full_n, - fifo_A_write, - A_len, - P_N -); - -parameter ap_ST_fsm_state1 = 6'd1; -parameter ap_ST_fsm_state2 = 6'd2; -parameter ap_ST_fsm_state3 = 6'd4; -parameter ap_ST_fsm_state4 = 6'd8; -parameter ap_ST_fsm_state5 = 6'd16; -parameter ap_ST_fsm_state6 = 6'd32; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -output [64:0] A_read_addr_din; -input A_read_addr_full_n; -output A_read_addr_write; -input [512:0] A_read_data_s_dout; -input A_read_data_s_empty_n; -output A_read_data_s_read; -input [512:0] A_read_data_peek_dout; -input A_read_data_peek_empty_n; -output A_read_data_peek_read; -output [64:0] A_write_addr_din; -input A_write_addr_full_n; -output A_write_addr_write; -output [512:0] A_write_data_din; -input A_write_data_full_n; -output A_write_data_write; -input [8:0] A_write_resp_s_dout; -input A_write_resp_s_empty_n; -output A_write_resp_s_read; -input [8:0] A_write_resp_peek_dout; -input A_write_resp_peek_empty_n; -output A_write_resp_peek_read; -output [512:0] fifo_A_din; -input fifo_A_full_n; -output fifo_A_write; -input [31:0] A_len; -input [31:0] P_N; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg A_read_addr_write; -reg A_read_data_s_read; -reg fifo_A_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [5:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire ap_CS_fsm_state4; -wire signed [29:0] grp_fu_261_p2; -reg signed [29:0] rp_time_N_reg_289; -wire grp_read_A_Pipeline_rd_A_fu_166_ap_start; -wire grp_read_A_Pipeline_rd_A_fu_166_ap_done; -wire grp_read_A_Pipeline_rd_A_fu_166_ap_idle; -wire grp_read_A_Pipeline_rd_A_fu_166_ap_ready; -wire [512:0] grp_read_A_Pipeline_rd_A_fu_166_fifo_A_din; -wire grp_read_A_Pipeline_rd_A_fu_166_fifo_A_write; -wire grp_read_A_Pipeline_rd_A_fu_166_A_read_data_s_read; -wire [64:0] grp_read_A_Pipeline_rd_A_fu_166_A_read_addr_din; -wire grp_read_A_Pipeline_rd_A_fu_166_A_read_addr_write; -reg grp_read_A_Pipeline_rd_A_fu_166_ap_start_reg; -wire ap_CS_fsm_state5; -wire [0:0] icmp_ln97_fu_245_p2; -wire ap_CS_fsm_state6; -reg [27:0] rp_fu_86; -wire [27:0] rp_2_fu_250_p2; -wire [15:0] N16_fu_181_p4; -wire [0:0] icmp_ln93_fu_191_p2; -wire signed [15:0] rp_time_fu_197_p3; -wire [15:0] N_fu_177_p1; -wire [16:0] zext_ln94_fu_209_p1; -wire [16:0] add_ln95_fu_213_p2; -wire [13:0] lshr_ln_fu_219_p4; -wire [29:0] zext_ln97_fu_241_p1; -wire [13:0] grp_fu_261_p1; -reg [5:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -wire ap_ST_fsm_state3_blk; -wire ap_ST_fsm_state4_blk; -wire ap_ST_fsm_state5_blk; -reg ap_ST_fsm_state6_blk; -wire [29:0] grp_fu_261_p10; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 6'd1; -#0 grp_read_A_Pipeline_rd_A_fu_166_ap_start_reg = 1'b0; -end - -read_A_read_A_Pipeline_rd_A grp_read_A_Pipeline_rd_A_fu_166( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_read_A_Pipeline_rd_A_fu_166_ap_start), - .ap_done(grp_read_A_Pipeline_rd_A_fu_166_ap_done), - .ap_idle(grp_read_A_Pipeline_rd_A_fu_166_ap_idle), - .ap_ready(grp_read_A_Pipeline_rd_A_fu_166_ap_ready), - .A_len(A_len), - .fifo_A_din(grp_read_A_Pipeline_rd_A_fu_166_fifo_A_din), - .fifo_A_full_n(fifo_A_full_n), - .fifo_A_write(grp_read_A_Pipeline_rd_A_fu_166_fifo_A_write), - .A_read_data_s_dout(A_read_data_s_dout), - .A_read_data_s_empty_n(A_read_data_s_empty_n), - .A_read_data_s_read(grp_read_A_Pipeline_rd_A_fu_166_A_read_data_s_read), - .A_read_addr_din(grp_read_A_Pipeline_rd_A_fu_166_A_read_addr_din), - .A_read_addr_full_n(A_read_addr_full_n), - .A_read_addr_write(grp_read_A_Pipeline_rd_A_fu_166_A_read_addr_write) -); - -read_A_mul_mul_16s_14ns_30_4_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 16 ), - .din1_WIDTH( 14 ), - .dout_WIDTH( 30 )) -mul_mul_16s_14ns_30_4_1_U5( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .din0(rp_time_fu_197_p3), - .din1(grp_fu_261_p1), - .ce(1'b1), - .dout(grp_fu_261_p2) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_read_A_Pipeline_rd_A_fu_166_ap_start_reg <= 1'b0; - end else begin - if (((icmp_ln97_fu_245_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state5))) begin - grp_read_A_Pipeline_rd_A_fu_166_ap_start_reg <= 1'b1; - end else if ((grp_read_A_Pipeline_rd_A_fu_166_ap_ready == 1'b1)) begin - grp_read_A_Pipeline_rd_A_fu_166_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - rp_fu_86 <= 28'd0; - end else if (((icmp_ln97_fu_245_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state5))) begin - rp_fu_86 <= rp_2_fu_250_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state4)) begin - rp_time_N_reg_289 <= grp_fu_261_p2; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - A_read_addr_write = grp_read_A_Pipeline_rd_A_fu_166_A_read_addr_write; - end else begin - A_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - A_read_data_s_read = grp_read_A_Pipeline_rd_A_fu_166_A_read_data_s_read; - end else begin - A_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -assign ap_ST_fsm_state3_blk = 1'b0; - -assign ap_ST_fsm_state4_blk = 1'b0; - -assign ap_ST_fsm_state5_blk = 1'b0; - -always @ (*) begin - if ((grp_read_A_Pipeline_rd_A_fu_166_ap_done == 1'b0)) begin - ap_ST_fsm_state6_blk = 1'b1; - end else begin - ap_ST_fsm_state6_blk = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln97_fu_245_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state5))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln97_fu_245_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state5))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - fifo_A_write = grp_read_A_Pipeline_rd_A_fu_166_fifo_A_write; - end else begin - fifo_A_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state3; - end - ap_ST_fsm_state3 : begin - ap_NS_fsm = ap_ST_fsm_state4; - end - ap_ST_fsm_state4 : begin - ap_NS_fsm = ap_ST_fsm_state5; - end - ap_ST_fsm_state5 : begin - if (((icmp_ln97_fu_245_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state5))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state6; - end - end - ap_ST_fsm_state6 : begin - if (((grp_read_A_Pipeline_rd_A_fu_166_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state6))) begin - ap_NS_fsm = ap_ST_fsm_state5; - end else begin - ap_NS_fsm = ap_ST_fsm_state6; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign A_read_addr_din = grp_read_A_Pipeline_rd_A_fu_166_A_read_addr_din; - -assign A_read_data_peek_read = 1'b0; - -assign A_write_addr_din = 65'd0; - -assign A_write_addr_write = 1'b0; - -assign A_write_data_din = 513'd0; - -assign A_write_data_write = 1'b0; - -assign A_write_resp_peek_read = 1'b0; - -assign A_write_resp_s_read = 1'b0; - -assign N16_fu_181_p4 = {{P_N[31:16]}}; - -assign N_fu_177_p1 = P_N[15:0]; - -assign add_ln95_fu_213_p2 = (zext_ln94_fu_209_p1 + 17'd7); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; - -assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; - -assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign fifo_A_din = grp_read_A_Pipeline_rd_A_fu_166_fifo_A_din; - -assign grp_fu_261_p1 = grp_fu_261_p10; - -assign grp_fu_261_p10 = lshr_ln_fu_219_p4; - -assign grp_read_A_Pipeline_rd_A_fu_166_ap_start = grp_read_A_Pipeline_rd_A_fu_166_ap_start_reg; - -assign icmp_ln93_fu_191_p2 = ((N16_fu_181_p4 == 16'd0) ? 1'b1 : 1'b0); - -assign icmp_ln97_fu_245_p2 = (($signed(zext_ln97_fu_241_p1) < $signed(rp_time_N_reg_289)) ? 1'b1 : 1'b0); - -assign lshr_ln_fu_219_p4 = {{add_ln95_fu_213_p2[16:3]}}; - -assign rp_2_fu_250_p2 = (rp_fu_86 + 28'd1); - -assign rp_time_fu_197_p3 = ((icmp_ln93_fu_191_p2[0:0] == 1'b1) ? 16'd1 : N16_fu_181_p4); - -assign zext_ln94_fu_209_p1 = N_fu_177_p1; - -assign zext_ln97_fu_241_p1 = rp_fu_86; - -endmodule //read_A diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A_flow_control_loop_pipe_sequential_init.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A_flow_control_loop_pipe_sequential_init.v deleted file mode 100644 index 712338d5..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A_flow_control_loop_pipe_sequential_init.v +++ /dev/null @@ -1,104 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module read_A_flow_control_loop_pipe_sequential_init( - ap_clk, - ap_rst, - ap_start, - ap_ready, - ap_done, - ap_start_int, - ap_ready_int, - ap_done_int, - ap_continue_int, - ap_loop_init, - ap_loop_exit_ready, - ap_loop_exit_done -); - -input ap_clk; -input ap_rst; - -//Block level handshake with outside loop -input ap_start; -output ap_ready; -output ap_done; - -//Block level handshake with loop body -output ap_start_int; -input ap_ready_int; -input ap_done_int; -output ap_continue_int; - -//Init live in variables -output ap_loop_init; -wire ap_loop_init; -reg ap_loop_init_int; -reg ap_done; -reg ap_done_cache; - -//Exit signal from loop body -input ap_loop_exit_ready; -input ap_loop_exit_done; - -// power-on initialization -initial begin -#0 ap_loop_init_int = 1'b1; -#0 ap_done_cache = 1'b0; -end - -assign ap_start_int = ap_start; - -assign ap_continue_int = 1'b1; - -assign ap_ready = ap_loop_exit_ready; - -//ap_loop_init is valid for the first II -//of the first loop run so as to enable -//the init block ops which are pushed into -//the first state of the pipeline region -always @ (posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_loop_exit_done == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_ready_int == 1'b1) begin - ap_loop_init_int <= 1'b0; - end -end - -assign ap_loop_init = ap_loop_init_int & ap_start; - -// if no ap_continue port and current module is not top module, -// ap_done handshakes with ap_start. Internally, flow control sends out -// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle. -// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int -// is asserted, so DUT can start the next run -always @(posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_done_cache <= 1'b0; - end else if (ap_done_int == 1'b1) begin - ap_done_cache <= 1'b1; - end else if (ap_start_int == 1'b1) begin - ap_done_cache <= 1'b0; - end -end - -// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start -always @(*) -begin - if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A_mul_mul_16s_14ns_30_4_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A_mul_mul_16s_14ns_30_4_1.v deleted file mode 100644 index 41c196e8..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A_mul_mul_16s_14ns_30_4_1.v +++ /dev/null @@ -1,62 +0,0 @@ - -`timescale 1 ns / 1 ps - - module read_A_mul_mul_16s_14ns_30_4_1_DSP48_0(clk, rst, ce, a, b, p); -input clk; -input rst; -input ce; -input signed [16 - 1 : 0] a; -input [14 - 1 : 0] b; -output signed [30 - 1 : 0] p; - -reg signed [30 - 1 : 0] p_reg; - -reg signed [16 - 1 : 0] a_reg; -reg [14 - 1 : 0] b_reg; - -reg signed [30 - 1 : 0] p_reg_tmp; - -always @ (posedge clk) begin - if (ce) begin - a_reg <= a; - b_reg <= b; - p_reg_tmp <= a_reg * $signed({1'b0, b_reg}); - p_reg <= p_reg_tmp; - end -end - -assign p = p_reg; - -endmodule -`timescale 1 ns / 1 ps -module read_A_mul_mul_16s_14ns_30_4_1( - clk, - reset, - ce, - din0, - din1, - dout); - -parameter ID = 32'd1; -parameter NUM_STAGE = 32'd1; -parameter din0_WIDTH = 32'd1; -parameter din1_WIDTH = 32'd1; -parameter dout_WIDTH = 32'd1; -input clk; -input reset; -input ce; -input[din0_WIDTH - 1:0] din0; -input[din1_WIDTH - 1:0] din1; -output[dout_WIDTH - 1:0] dout; - - - -read_A_mul_mul_16s_14ns_30_4_1_DSP48_0 read_A_mul_mul_16s_14ns_30_4_1_DSP48_0_U( - .clk( clk ), - .rst( reset ), - .ce( ce ), - .a( din0 ), - .b( din1 ), - .p( dout )); - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A_read_A_Pipeline_rd_A.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A_read_A_Pipeline_rd_A.v deleted file mode 100644 index ce65c67b..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_A_read_A_Pipeline_rd_A.v +++ /dev/null @@ -1,303 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module read_A_read_A_Pipeline_rd_A ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - A_len, - fifo_A_din, - fifo_A_full_n, - fifo_A_write, - A_read_data_s_dout, - A_read_data_s_empty_n, - A_read_data_s_read, - A_read_addr_din, - A_read_addr_full_n, - A_read_addr_write -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [31:0] A_len; -output [512:0] fifo_A_din; -input fifo_A_full_n; -output fifo_A_write; -input [512:0] A_read_data_s_dout; -input A_read_data_s_empty_n; -output A_read_data_s_read; -output [64:0] A_read_addr_din; -input A_read_addr_full_n; -output A_read_addr_write; - -reg ap_idle; -reg fifo_A_write; -reg A_read_data_s_read; -reg A_read_addr_write; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -wire ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln101_fu_128_p2; -reg ap_condition_exit_pp0_iter1_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -wire ap_block_pp0_stage0_11001; -reg [31:0] i_resp_fu_54; -wire [31:0] i_resp_2_fu_191_p2; -wire [0:0] and_ln47_fu_168_p2; -wire ap_loop_init; -wire ap_block_pp0_stage0; -reg [31:0] i_req_fu_58; -wire [31:0] i_req_2_fu_157_p2; -wire [0:0] and_ln43_fu_138_p2; -wire ap_block_pp0_stage0_01001; -wire [0:0] tmp_4_nbreadreq_fu_91_p3; -wire signed [31:0] icmp_ln43_fu_133_p0; -wire [0:0] icmp_ln43_fu_133_p2; -wire [0:0] and_ln43_fu_138_p1; -wire signed [31:0] sext_ln44_fu_144_p0; -wire signed [63:0] sext_ln44_fu_144_p1; -wire signed [31:0] i_req_2_fu_157_p0; -wire [0:0] and_ln47_fu_168_p0; -wire [511:0] trunc_ln78_fu_178_p1; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -reg ap_condition_190; -reg ap_condition_193; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -read_A_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter1_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter1_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - i_req_fu_58 <= 32'd0; - end else if ((1'b1 == ap_condition_190)) begin - i_req_fu_58 <= i_req_2_fu_157_p2; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - i_resp_fu_54 <= 32'd0; - end else if ((1'b1 == ap_condition_193)) begin - i_resp_fu_54 <= i_resp_2_fu_191_p2; - end - end -end - -always @ (*) begin - if (((1'd1 == and_ln43_fu_138_p2) & (icmp_ln101_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == A_read_addr_full_n) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - A_read_addr_write = 1'b1; - end else begin - A_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln47_fu_168_p2) & (icmp_ln101_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == A_read_data_s_empty_n) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - A_read_data_s_read = 1'b1; - end else begin - A_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln101_fu_128_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter1_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter1_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_start_int == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln47_fu_168_p2) & (fifo_A_full_n == 1'b1) & (icmp_ln101_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_A_write = 1'b1; - end else begin - fifo_A_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign A_read_addr_din = {{1'd0}, {sext_ln44_fu_144_p1}}; - -assign and_ln43_fu_138_p1 = A_read_addr_full_n; - -assign and_ln43_fu_138_p2 = (icmp_ln43_fu_133_p2 & and_ln43_fu_138_p1); - -assign and_ln47_fu_168_p0 = fifo_A_full_n; - -assign and_ln47_fu_168_p2 = (tmp_4_nbreadreq_fu_91_p3 & and_ln47_fu_168_p0); - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_01001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_condition_190 = ((1'd1 == and_ln43_fu_138_p2) & (icmp_ln101_fu_128_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -always @ (*) begin - ap_condition_193 = ((1'd1 == and_ln47_fu_168_p2) & (icmp_ln101_fu_128_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter1_stage0; - -assign fifo_A_din = {{1'd0}, {trunc_ln78_fu_178_p1}}; - -assign i_req_2_fu_157_p0 = i_req_fu_58; - -assign i_req_2_fu_157_p2 = ($signed(i_req_2_fu_157_p0) + $signed(32'd1)); - -assign i_resp_2_fu_191_p2 = (i_resp_fu_54 + 32'd1); - -assign icmp_ln101_fu_128_p2 = (($signed(i_resp_fu_54) < $signed(A_len)) ? 1'b1 : 1'b0); - -assign icmp_ln43_fu_133_p0 = i_req_fu_58; - -assign icmp_ln43_fu_133_p2 = (($signed(icmp_ln43_fu_133_p0) < $signed(A_len)) ? 1'b1 : 1'b0); - -assign sext_ln44_fu_144_p0 = i_req_fu_58; - -assign sext_ln44_fu_144_p1 = sext_ln44_fu_144_p0; - -assign tmp_4_nbreadreq_fu_91_p3 = A_read_data_s_empty_n; - -assign trunc_ln78_fu_178_p1 = A_read_data_s_dout[511:0]; - -endmodule //read_A_read_A_Pipeline_rd_A diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B.v deleted file mode 100644 index 548809b5..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B.v +++ /dev/null @@ -1,380 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="read_B_read_B,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=2000035,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=348,HLS_SYN_LUT=403,HLS_VERSION=2022_2}" *) - -module read_B ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - B_read_addr_din, - B_read_addr_full_n, - B_read_addr_write, - B_read_data_s_dout, - B_read_data_s_empty_n, - B_read_data_s_read, - B_read_data_peek_dout, - B_read_data_peek_empty_n, - B_read_data_peek_read, - B_write_addr_din, - B_write_addr_full_n, - B_write_addr_write, - B_write_data_din, - B_write_data_full_n, - B_write_data_write, - B_write_resp_s_dout, - B_write_resp_s_empty_n, - B_write_resp_s_read, - B_write_resp_peek_dout, - B_write_resp_peek_empty_n, - B_write_resp_peek_read, - fifo_B_din, - fifo_B_full_n, - fifo_B_write, - K, - P_N -); - -parameter ap_ST_fsm_state1 = 5'd1; -parameter ap_ST_fsm_state2 = 5'd2; -parameter ap_ST_fsm_state3 = 5'd4; -parameter ap_ST_fsm_state4 = 5'd8; -parameter ap_ST_fsm_state5 = 5'd16; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -output [64:0] B_read_addr_din; -input B_read_addr_full_n; -output B_read_addr_write; -input [512:0] B_read_data_s_dout; -input B_read_data_s_empty_n; -output B_read_data_s_read; -input [512:0] B_read_data_peek_dout; -input B_read_data_peek_empty_n; -output B_read_data_peek_read; -output [64:0] B_write_addr_din; -input B_write_addr_full_n; -output B_write_addr_write; -output [512:0] B_write_data_din; -input B_write_data_full_n; -output B_write_data_write; -input [8:0] B_write_resp_s_dout; -input B_write_resp_s_empty_n; -output B_write_resp_s_read; -input [8:0] B_write_resp_peek_dout; -input B_write_resp_peek_empty_n; -output B_write_resp_peek_read; -output [512:0] fifo_B_din; -input fifo_B_full_n; -output fifo_B_write; -input [31:0] K; -input [31:0] P_N; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg B_read_addr_write; -reg B_read_data_s_read; -reg fifo_B_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [4:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -reg [15:0] N16_reg_290; -reg signed [28:0] trunc_ln_reg_296; -reg [13:0] lshr_ln_reg_301; -wire ap_CS_fsm_state2; -wire [15:0] rp_time_fu_253_p3; -reg [15:0] rp_time_reg_316; -wire ap_CS_fsm_state3; -wire [31:0] grp_fu_242_p2; -reg [31:0] num_ite_B_reg_321; -wire grp_read_B_Pipeline_rd_B_fu_170_ap_start; -wire grp_read_B_Pipeline_rd_B_fu_170_ap_done; -wire grp_read_B_Pipeline_rd_B_fu_170_ap_idle; -wire grp_read_B_Pipeline_rd_B_fu_170_ap_ready; -wire [512:0] grp_read_B_Pipeline_rd_B_fu_170_fifo_B_din; -wire grp_read_B_Pipeline_rd_B_fu_170_fifo_B_write; -wire grp_read_B_Pipeline_rd_B_fu_170_B_read_data_s_read; -wire [64:0] grp_read_B_Pipeline_rd_B_fu_170_B_read_addr_din; -wire grp_read_B_Pipeline_rd_B_fu_170_B_read_addr_write; -reg grp_read_B_Pipeline_rd_B_fu_170_ap_start_reg; -wire ap_CS_fsm_state4; -wire [0:0] icmp_ln98_fu_267_p2; -wire ap_CS_fsm_state5; -reg [14:0] rp_fu_90; -wire [14:0] rp_2_fu_272_p2; -wire [15:0] N_fu_181_p1; -wire [31:0] add_ln96_fu_199_p2; -wire [16:0] zext_ln95_fu_195_p1; -wire [16:0] add_ln96_1_fu_215_p2; -wire [13:0] grp_fu_242_p0; -wire [0:0] icmp_ln94_fu_248_p2; -wire [15:0] zext_ln98_fu_263_p1; -reg [4:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -wire ap_ST_fsm_state3_blk; -wire ap_ST_fsm_state4_blk; -reg ap_ST_fsm_state5_blk; -wire [31:0] grp_fu_242_p00; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 5'd1; -#0 grp_read_B_Pipeline_rd_B_fu_170_ap_start_reg = 1'b0; -end - -read_B_read_B_Pipeline_rd_B grp_read_B_Pipeline_rd_B_fu_170( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_read_B_Pipeline_rd_B_fu_170_ap_start), - .ap_done(grp_read_B_Pipeline_rd_B_fu_170_ap_done), - .ap_idle(grp_read_B_Pipeline_rd_B_fu_170_ap_idle), - .ap_ready(grp_read_B_Pipeline_rd_B_fu_170_ap_ready), - .num_ite_B(num_ite_B_reg_321), - .fifo_B_din(grp_read_B_Pipeline_rd_B_fu_170_fifo_B_din), - .fifo_B_full_n(fifo_B_full_n), - .fifo_B_write(grp_read_B_Pipeline_rd_B_fu_170_fifo_B_write), - .B_read_data_s_dout(B_read_data_s_dout), - .B_read_data_s_empty_n(B_read_data_s_empty_n), - .B_read_data_s_read(grp_read_B_Pipeline_rd_B_fu_170_B_read_data_s_read), - .B_read_addr_din(grp_read_B_Pipeline_rd_B_fu_170_B_read_addr_din), - .B_read_addr_full_n(B_read_addr_full_n), - .B_read_addr_write(grp_read_B_Pipeline_rd_B_fu_170_B_read_addr_write) -); - -read_B_mul_14ns_29s_32_2_1 #( - .ID( 1 ), - .NUM_STAGE( 2 ), - .din0_WIDTH( 14 ), - .din1_WIDTH( 29 ), - .dout_WIDTH( 32 )) -mul_14ns_29s_32_2_1_U5( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .din0(grp_fu_242_p0), - .din1(trunc_ln_reg_296), - .ce(1'b1), - .dout(grp_fu_242_p2) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_read_B_Pipeline_rd_B_fu_170_ap_start_reg <= 1'b0; - end else begin - if (((1'b1 == ap_CS_fsm_state4) & (icmp_ln98_fu_267_p2 == 1'd1))) begin - grp_read_B_Pipeline_rd_B_fu_170_ap_start_reg <= 1'b1; - end else if ((grp_read_B_Pipeline_rd_B_fu_170_ap_ready == 1'b1)) begin - grp_read_B_Pipeline_rd_B_fu_170_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - rp_fu_90 <= 15'd0; - end else if (((1'b1 == ap_CS_fsm_state4) & (icmp_ln98_fu_267_p2 == 1'd1))) begin - rp_fu_90 <= rp_2_fu_272_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state1)) begin - N16_reg_290 <= {{P_N[31:16]}}; - lshr_ln_reg_301 <= {{add_ln96_1_fu_215_p2[16:3]}}; - trunc_ln_reg_296 <= {{add_ln96_fu_199_p2[31:3]}}; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - num_ite_B_reg_321 <= grp_fu_242_p2; - rp_time_reg_316 <= rp_time_fu_253_p3; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state5)) begin - B_read_addr_write = grp_read_B_Pipeline_rd_B_fu_170_B_read_addr_write; - end else begin - B_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state5)) begin - B_read_data_s_read = grp_read_B_Pipeline_rd_B_fu_170_B_read_data_s_read; - end else begin - B_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -assign ap_ST_fsm_state3_blk = 1'b0; - -assign ap_ST_fsm_state4_blk = 1'b0; - -always @ (*) begin - if ((grp_read_B_Pipeline_rd_B_fu_170_ap_done == 1'b0)) begin - ap_ST_fsm_state5_blk = 1'b1; - end else begin - ap_ST_fsm_state5_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state4) & (icmp_ln98_fu_267_p2 == 1'd0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state4) & (icmp_ln98_fu_267_p2 == 1'd0))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state5)) begin - fifo_B_write = grp_read_B_Pipeline_rd_B_fu_170_fifo_B_write; - end else begin - fifo_B_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state3; - end - ap_ST_fsm_state3 : begin - ap_NS_fsm = ap_ST_fsm_state4; - end - ap_ST_fsm_state4 : begin - if (((1'b1 == ap_CS_fsm_state4) & (icmp_ln98_fu_267_p2 == 1'd0))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state5; - end - end - ap_ST_fsm_state5 : begin - if (((grp_read_B_Pipeline_rd_B_fu_170_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state5))) begin - ap_NS_fsm = ap_ST_fsm_state4; - end else begin - ap_NS_fsm = ap_ST_fsm_state5; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign B_read_addr_din = grp_read_B_Pipeline_rd_B_fu_170_B_read_addr_din; - -assign B_read_data_peek_read = 1'b0; - -assign B_write_addr_din = 65'd0; - -assign B_write_addr_write = 1'b0; - -assign B_write_data_din = 513'd0; - -assign B_write_data_write = 1'b0; - -assign B_write_resp_peek_read = 1'b0; - -assign B_write_resp_s_read = 1'b0; - -assign N_fu_181_p1 = P_N[15:0]; - -assign add_ln96_1_fu_215_p2 = (zext_ln95_fu_195_p1 + 17'd7); - -assign add_ln96_fu_199_p2 = (K + 32'd7); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; - -assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign fifo_B_din = grp_read_B_Pipeline_rd_B_fu_170_fifo_B_din; - -assign grp_fu_242_p0 = grp_fu_242_p00; - -assign grp_fu_242_p00 = lshr_ln_reg_301; - -assign grp_read_B_Pipeline_rd_B_fu_170_ap_start = grp_read_B_Pipeline_rd_B_fu_170_ap_start_reg; - -assign icmp_ln94_fu_248_p2 = ((N16_reg_290 == 16'd0) ? 1'b1 : 1'b0); - -assign icmp_ln98_fu_267_p2 = (($signed(zext_ln98_fu_263_p1) < $signed(rp_time_reg_316)) ? 1'b1 : 1'b0); - -assign rp_2_fu_272_p2 = (rp_fu_90 + 15'd1); - -assign rp_time_fu_253_p3 = ((icmp_ln94_fu_248_p2[0:0] == 1'b1) ? 16'd1 : N16_reg_290); - -assign zext_ln95_fu_195_p1 = N_fu_181_p1; - -assign zext_ln98_fu_263_p1 = rp_fu_90; - -endmodule //read_B diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B_flow_control_loop_pipe_sequential_init.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B_flow_control_loop_pipe_sequential_init.v deleted file mode 100644 index b42b1d9d..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B_flow_control_loop_pipe_sequential_init.v +++ /dev/null @@ -1,104 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module read_B_flow_control_loop_pipe_sequential_init( - ap_clk, - ap_rst, - ap_start, - ap_ready, - ap_done, - ap_start_int, - ap_ready_int, - ap_done_int, - ap_continue_int, - ap_loop_init, - ap_loop_exit_ready, - ap_loop_exit_done -); - -input ap_clk; -input ap_rst; - -//Block level handshake with outside loop -input ap_start; -output ap_ready; -output ap_done; - -//Block level handshake with loop body -output ap_start_int; -input ap_ready_int; -input ap_done_int; -output ap_continue_int; - -//Init live in variables -output ap_loop_init; -wire ap_loop_init; -reg ap_loop_init_int; -reg ap_done; -reg ap_done_cache; - -//Exit signal from loop body -input ap_loop_exit_ready; -input ap_loop_exit_done; - -// power-on initialization -initial begin -#0 ap_loop_init_int = 1'b1; -#0 ap_done_cache = 1'b0; -end - -assign ap_start_int = ap_start; - -assign ap_continue_int = 1'b1; - -assign ap_ready = ap_loop_exit_ready; - -//ap_loop_init is valid for the first II -//of the first loop run so as to enable -//the init block ops which are pushed into -//the first state of the pipeline region -always @ (posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_loop_exit_done == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_ready_int == 1'b1) begin - ap_loop_init_int <= 1'b0; - end -end - -assign ap_loop_init = ap_loop_init_int & ap_start; - -// if no ap_continue port and current module is not top module, -// ap_done handshakes with ap_start. Internally, flow control sends out -// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle. -// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int -// is asserted, so DUT can start the next run -always @(posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_done_cache <= 1'b0; - end else if (ap_done_int == 1'b1) begin - ap_done_cache <= 1'b1; - end else if (ap_start_int == 1'b1) begin - ap_done_cache <= 1'b0; - end -end - -// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start -always @(*) -begin - if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B_mul_14ns_29s_32_2_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B_mul_14ns_29s_32_2_1.v deleted file mode 100644 index 2e5508d9..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B_mul_14ns_29s_32_2_1.v +++ /dev/null @@ -1,30 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module read_B_mul_14ns_29s_32_2_1(clk, ce, reset, din0, din1, dout); -parameter ID = 1; -parameter NUM_STAGE = 1; -parameter din0_WIDTH = 14; -parameter din1_WIDTH = 12; -parameter dout_WIDTH = 26; -input clk; -input ce; -input reset; -input [din0_WIDTH - 1 : 0] din0; -input signed [din1_WIDTH - 1 : 0] din1; -output[dout_WIDTH - 1 : 0] dout; -reg signed [dout_WIDTH - 1 : 0] dout; -wire signed [dout_WIDTH - 1 : 0] tmp_product; - -assign tmp_product = $signed({1'b0, din0}) * $signed(din1); -always @ (posedge clk) begin - if (ce) begin - dout <= tmp_product; - end -end -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B_read_B_Pipeline_rd_B.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B_read_B_Pipeline_rd_B.v deleted file mode 100644 index f2e5b480..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_B_read_B_Pipeline_rd_B.v +++ /dev/null @@ -1,303 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module read_B_read_B_Pipeline_rd_B ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - num_ite_B, - fifo_B_din, - fifo_B_full_n, - fifo_B_write, - B_read_data_s_dout, - B_read_data_s_empty_n, - B_read_data_s_read, - B_read_addr_din, - B_read_addr_full_n, - B_read_addr_write -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [31:0] num_ite_B; -output [512:0] fifo_B_din; -input fifo_B_full_n; -output fifo_B_write; -input [512:0] B_read_data_s_dout; -input B_read_data_s_empty_n; -output B_read_data_s_read; -output [64:0] B_read_addr_din; -input B_read_addr_full_n; -output B_read_addr_write; - -reg ap_idle; -reg fifo_B_write; -reg B_read_data_s_read; -reg B_read_addr_write; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -wire ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln102_fu_128_p2; -reg ap_condition_exit_pp0_iter1_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -wire ap_block_pp0_stage0_11001; -reg [31:0] i_resp_fu_54; -wire [31:0] i_resp_2_fu_191_p2; -wire [0:0] and_ln47_fu_168_p2; -wire ap_loop_init; -wire ap_block_pp0_stage0; -reg [31:0] i_req_fu_58; -wire [31:0] i_req_2_fu_157_p2; -wire [0:0] and_ln43_fu_138_p2; -wire ap_block_pp0_stage0_01001; -wire [0:0] tmp_4_nbreadreq_fu_91_p3; -wire signed [31:0] icmp_ln43_fu_133_p0; -wire [0:0] icmp_ln43_fu_133_p2; -wire [0:0] and_ln43_fu_138_p1; -wire signed [31:0] sext_ln44_fu_144_p0; -wire signed [63:0] sext_ln44_fu_144_p1; -wire signed [31:0] i_req_2_fu_157_p0; -wire [0:0] and_ln47_fu_168_p0; -wire [511:0] trunc_ln146_fu_178_p1; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -reg ap_condition_190; -reg ap_condition_193; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -read_B_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter1_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter1_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - i_req_fu_58 <= 32'd0; - end else if ((1'b1 == ap_condition_190)) begin - i_req_fu_58 <= i_req_2_fu_157_p2; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - i_resp_fu_54 <= 32'd0; - end else if ((1'b1 == ap_condition_193)) begin - i_resp_fu_54 <= i_resp_2_fu_191_p2; - end - end -end - -always @ (*) begin - if (((1'd1 == and_ln43_fu_138_p2) & (icmp_ln102_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == B_read_addr_full_n) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - B_read_addr_write = 1'b1; - end else begin - B_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln47_fu_168_p2) & (icmp_ln102_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == B_read_data_s_empty_n) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - B_read_data_s_read = 1'b1; - end else begin - B_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln102_fu_128_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter1_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter1_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_start_int == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln47_fu_168_p2) & (fifo_B_full_n == 1'b1) & (icmp_ln102_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_B_write = 1'b1; - end else begin - fifo_B_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign B_read_addr_din = {{1'd0}, {sext_ln44_fu_144_p1}}; - -assign and_ln43_fu_138_p1 = B_read_addr_full_n; - -assign and_ln43_fu_138_p2 = (icmp_ln43_fu_133_p2 & and_ln43_fu_138_p1); - -assign and_ln47_fu_168_p0 = fifo_B_full_n; - -assign and_ln47_fu_168_p2 = (tmp_4_nbreadreq_fu_91_p3 & and_ln47_fu_168_p0); - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_01001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_condition_190 = ((1'd1 == and_ln43_fu_138_p2) & (icmp_ln102_fu_128_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -always @ (*) begin - ap_condition_193 = ((1'd1 == and_ln47_fu_168_p2) & (icmp_ln102_fu_128_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter1_stage0; - -assign fifo_B_din = {{1'd0}, {trunc_ln146_fu_178_p1}}; - -assign i_req_2_fu_157_p0 = i_req_fu_58; - -assign i_req_2_fu_157_p2 = ($signed(i_req_2_fu_157_p0) + $signed(32'd1)); - -assign i_resp_2_fu_191_p2 = (i_resp_fu_54 + 32'd1); - -assign icmp_ln102_fu_128_p2 = (($signed(i_resp_fu_54) < $signed(num_ite_B)) ? 1'b1 : 1'b0); - -assign icmp_ln43_fu_133_p0 = i_req_fu_58; - -assign icmp_ln43_fu_133_p2 = (($signed(icmp_ln43_fu_133_p0) < $signed(num_ite_B)) ? 1'b1 : 1'b0); - -assign sext_ln44_fu_144_p0 = i_req_fu_58; - -assign sext_ln44_fu_144_p1 = sext_ln44_fu_144_p0; - -assign tmp_4_nbreadreq_fu_91_p3 = B_read_data_s_empty_n; - -assign trunc_ln146_fu_178_p1 = B_read_data_s_dout[511:0]; - -endmodule //read_B_read_B_Pipeline_rd_B diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C.v deleted file mode 100644 index 2e536fec..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C.v +++ /dev/null @@ -1,457 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="read_C_read_C,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=2000036,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=153,HLS_SYN_LUT=391,HLS_VERSION=2022_2}" *) - -module read_C ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - C_read_addr_din, - C_read_addr_full_n, - C_read_addr_write, - C_read_data_s_dout, - C_read_data_s_empty_n, - C_read_data_s_read, - C_read_data_peek_dout, - C_read_data_peek_empty_n, - C_read_data_peek_read, - C_write_addr_din, - C_write_addr_full_n, - C_write_addr_write, - C_write_data_din, - C_write_data_full_n, - C_write_data_write, - C_write_resp_s_dout, - C_write_resp_s_empty_n, - C_write_resp_s_read, - C_write_resp_peek_dout, - C_write_resp_peek_empty_n, - C_write_resp_peek_read, - fifo_C_din, - fifo_C_full_n, - fifo_C_write, - M, - P_N, - wrC_inst_din, - wrC_inst_full_n, - wrC_inst_write -); - -parameter ap_ST_fsm_state1 = 6'd1; -parameter ap_ST_fsm_state2 = 6'd2; -parameter ap_ST_fsm_state3 = 6'd4; -parameter ap_ST_fsm_state4 = 6'd8; -parameter ap_ST_fsm_state5 = 6'd16; -parameter ap_ST_fsm_state6 = 6'd32; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -output [64:0] C_read_addr_din; -input C_read_addr_full_n; -output C_read_addr_write; -input [512:0] C_read_data_s_dout; -input C_read_data_s_empty_n; -output C_read_data_s_read; -input [512:0] C_read_data_peek_dout; -input C_read_data_peek_empty_n; -output C_read_data_peek_read; -output [64:0] C_write_addr_din; -input C_write_addr_full_n; -output C_write_addr_write; -output [512:0] C_write_data_din; -input C_write_data_full_n; -output C_write_data_write; -input [8:0] C_write_resp_s_dout; -input C_write_resp_s_empty_n; -output C_write_resp_s_read; -input [8:0] C_write_resp_peek_dout; -input C_write_resp_peek_empty_n; -output C_write_resp_peek_read; -output [512:0] fifo_C_din; -input fifo_C_full_n; -output fifo_C_write; -input [31:0] M; -input [31:0] P_N; -output [32:0] wrC_inst_din; -input wrC_inst_full_n; -output wrC_inst_write; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg C_read_addr_write; -reg C_read_data_s_read; -reg fifo_C_write; -reg[32:0] wrC_inst_din; -reg wrC_inst_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [5:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -reg wrC_inst_blk_n; -wire ap_CS_fsm_state2; -reg [15:0] N16_reg_341; -wire [15:0] rp_time_fu_293_p3; -reg [15:0] rp_time_reg_357; -wire ap_CS_fsm_state4; -wire signed [31:0] grp_fu_323_p2; -reg [31:0] num_ite_C_reg_362; -wire grp_read_C_Pipeline_rd_C_fu_197_ap_start; -wire grp_read_C_Pipeline_rd_C_fu_197_ap_done; -wire grp_read_C_Pipeline_rd_C_fu_197_ap_idle; -wire grp_read_C_Pipeline_rd_C_fu_197_ap_ready; -wire [512:0] grp_read_C_Pipeline_rd_C_fu_197_fifo_C_din; -wire grp_read_C_Pipeline_rd_C_fu_197_fifo_C_write; -wire grp_read_C_Pipeline_rd_C_fu_197_C_read_data_s_read; -wire [64:0] grp_read_C_Pipeline_rd_C_fu_197_C_read_addr_din; -wire grp_read_C_Pipeline_rd_C_fu_197_C_read_addr_write; -reg grp_read_C_Pipeline_rd_C_fu_197_ap_start_reg; -wire ap_CS_fsm_state5; -wire [0:0] icmp_ln107_fu_307_p2; -wire ap_CS_fsm_state6; -reg [14:0] rp_fu_102; -wire [14:0] rp_2_fu_312_p2; -reg ap_block_state1; -wire [32:0] p_s_fu_212_p3; -wire [32:0] p_0_fu_280_p3; -wire [15:0] N_fu_208_p1; -wire [31:0] add_ln105_fu_235_p2; -wire signed [27:0] trunc_ln_fu_241_p4; -wire [16:0] zext_ln104_fu_231_p1; -wire [16:0] add_ln105_1_fu_255_p2; -wire [13:0] lshr_ln_fu_261_p4; -wire [0:0] icmp_ln103_fu_288_p2; -wire [15:0] zext_ln107_fu_303_p1; -wire [13:0] grp_fu_323_p0; -reg grp_fu_323_ce; -wire ap_CS_fsm_state3; -reg [5:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -reg ap_ST_fsm_state2_blk; -wire ap_ST_fsm_state3_blk; -wire ap_ST_fsm_state4_blk; -wire ap_ST_fsm_state5_blk; -reg ap_ST_fsm_state6_blk; -wire [31:0] grp_fu_323_p00; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 6'd1; -#0 grp_read_C_Pipeline_rd_C_fu_197_ap_start_reg = 1'b0; -end - -read_C_read_C_Pipeline_rd_C grp_read_C_Pipeline_rd_C_fu_197( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_read_C_Pipeline_rd_C_fu_197_ap_start), - .ap_done(grp_read_C_Pipeline_rd_C_fu_197_ap_done), - .ap_idle(grp_read_C_Pipeline_rd_C_fu_197_ap_idle), - .ap_ready(grp_read_C_Pipeline_rd_C_fu_197_ap_ready), - .num_ite_C(num_ite_C_reg_362), - .fifo_C_din(grp_read_C_Pipeline_rd_C_fu_197_fifo_C_din), - .fifo_C_full_n(fifo_C_full_n), - .fifo_C_write(grp_read_C_Pipeline_rd_C_fu_197_fifo_C_write), - .C_read_data_s_dout(C_read_data_s_dout), - .C_read_data_s_empty_n(C_read_data_s_empty_n), - .C_read_data_s_read(grp_read_C_Pipeline_rd_C_fu_197_C_read_data_s_read), - .C_read_addr_din(grp_read_C_Pipeline_rd_C_fu_197_C_read_addr_din), - .C_read_addr_full_n(C_read_addr_full_n), - .C_read_addr_write(grp_read_C_Pipeline_rd_C_fu_197_C_read_addr_write) -); - -read_C_mul_mul_14ns_28s_32_4_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 14 ), - .din1_WIDTH( 28 ), - .dout_WIDTH( 32 )) -mul_mul_14ns_28s_32_4_1_U5( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .din0(grp_fu_323_p0), - .din1(trunc_ln_fu_241_p4), - .ce(grp_fu_323_ce), - .dout(grp_fu_323_p2) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_read_C_Pipeline_rd_C_fu_197_ap_start_reg <= 1'b0; - end else begin - if (((1'b1 == ap_CS_fsm_state5) & (icmp_ln107_fu_307_p2 == 1'd1))) begin - grp_read_C_Pipeline_rd_C_fu_197_ap_start_reg <= 1'b1; - end else if ((grp_read_C_Pipeline_rd_C_fu_197_ap_ready == 1'b1)) begin - grp_read_C_Pipeline_rd_C_fu_197_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if ((~((wrC_inst_full_n == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - rp_fu_102 <= 15'd0; - end else if (((1'b1 == ap_CS_fsm_state5) & (icmp_ln107_fu_307_p2 == 1'd1))) begin - rp_fu_102 <= rp_2_fu_312_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state1)) begin - N16_reg_341 <= {{P_N[31:16]}}; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state4)) begin - num_ite_C_reg_362 <= grp_fu_323_p2; - rp_time_reg_357 <= rp_time_fu_293_p3; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - C_read_addr_write = grp_read_C_Pipeline_rd_C_fu_197_C_read_addr_write; - end else begin - C_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - C_read_data_s_read = grp_read_C_Pipeline_rd_C_fu_197_C_read_data_s_read; - end else begin - C_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if (((wrC_inst_full_n == 1'b0) | (ap_start == 1'b0))) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -always @ (*) begin - if ((wrC_inst_full_n == 1'b0)) begin - ap_ST_fsm_state2_blk = 1'b1; - end else begin - ap_ST_fsm_state2_blk = 1'b0; - end -end - -assign ap_ST_fsm_state3_blk = 1'b0; - -assign ap_ST_fsm_state4_blk = 1'b0; - -assign ap_ST_fsm_state5_blk = 1'b0; - -always @ (*) begin - if ((grp_read_C_Pipeline_rd_C_fu_197_ap_done == 1'b0)) begin - ap_ST_fsm_state6_blk = 1'b1; - end else begin - ap_ST_fsm_state6_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state5) & (icmp_ln107_fu_307_p2 == 1'd0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state5) & (icmp_ln107_fu_307_p2 == 1'd0))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - fifo_C_write = grp_read_C_Pipeline_rd_C_fu_197_fifo_C_write; - end else begin - fifo_C_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | ((wrC_inst_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state2)) | (~((wrC_inst_full_n == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin - grp_fu_323_ce = 1'b1; - end else begin - grp_fu_323_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin - wrC_inst_blk_n = wrC_inst_full_n; - end else begin - wrC_inst_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((wrC_inst_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - wrC_inst_din = p_0_fu_280_p3; - end else if ((~((wrC_inst_full_n == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - wrC_inst_din = p_s_fu_212_p3; - end else begin - wrC_inst_din = 'bx; - end -end - -always @ (*) begin - if ((((wrC_inst_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state2)) | (~((wrC_inst_full_n == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin - wrC_inst_write = 1'b1; - end else begin - wrC_inst_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if ((~((wrC_inst_full_n == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - if (((wrC_inst_full_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - ap_NS_fsm = ap_ST_fsm_state3; - end else begin - ap_NS_fsm = ap_ST_fsm_state2; - end - end - ap_ST_fsm_state3 : begin - ap_NS_fsm = ap_ST_fsm_state4; - end - ap_ST_fsm_state4 : begin - ap_NS_fsm = ap_ST_fsm_state5; - end - ap_ST_fsm_state5 : begin - if (((1'b1 == ap_CS_fsm_state5) & (icmp_ln107_fu_307_p2 == 1'd0))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state6; - end - end - ap_ST_fsm_state6 : begin - if (((grp_read_C_Pipeline_rd_C_fu_197_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state6))) begin - ap_NS_fsm = ap_ST_fsm_state5; - end else begin - ap_NS_fsm = ap_ST_fsm_state6; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign C_read_addr_din = grp_read_C_Pipeline_rd_C_fu_197_C_read_addr_din; - -assign C_read_data_peek_read = 1'b0; - -assign C_write_addr_din = 65'd0; - -assign C_write_addr_write = 1'b0; - -assign C_write_data_din = 513'd0; - -assign C_write_data_write = 1'b0; - -assign C_write_resp_peek_read = 1'b0; - -assign C_write_resp_s_read = 1'b0; - -assign N_fu_208_p1 = P_N[15:0]; - -assign add_ln105_1_fu_255_p2 = (zext_ln104_fu_231_p1 + 17'd7); - -assign add_ln105_fu_235_p2 = (M + 32'd15); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; - -assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; - -assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; - -always @ (*) begin - ap_block_state1 = ((wrC_inst_full_n == 1'b0) | (ap_start == 1'b0)); -end - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign fifo_C_din = grp_read_C_Pipeline_rd_C_fu_197_fifo_C_din; - -assign grp_fu_323_p0 = grp_fu_323_p00; - -assign grp_fu_323_p00 = lshr_ln_fu_261_p4; - -assign grp_read_C_Pipeline_rd_C_fu_197_ap_start = grp_read_C_Pipeline_rd_C_fu_197_ap_start_reg; - -assign icmp_ln103_fu_288_p2 = ((N16_reg_341 == 16'd0) ? 1'b1 : 1'b0); - -assign icmp_ln107_fu_307_p2 = (($signed(zext_ln107_fu_303_p1) < $signed(rp_time_reg_357)) ? 1'b1 : 1'b0); - -assign lshr_ln_fu_261_p4 = {{add_ln105_1_fu_255_p2[16:3]}}; - -assign p_0_fu_280_p3 = {{1'd0}, {P_N}}; - -assign p_s_fu_212_p3 = {{1'd0}, {M}}; - -assign rp_2_fu_312_p2 = (rp_fu_102 + 15'd1); - -assign rp_time_fu_293_p3 = ((icmp_ln103_fu_288_p2[0:0] == 1'b1) ? 16'd1 : N16_reg_341); - -assign trunc_ln_fu_241_p4 = {{add_ln105_fu_235_p2[31:4]}}; - -assign zext_ln104_fu_231_p1 = N_fu_208_p1; - -assign zext_ln107_fu_303_p1 = rp_fu_102; - -endmodule //read_C diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C_flow_control_loop_pipe_sequential_init.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C_flow_control_loop_pipe_sequential_init.v deleted file mode 100644 index d347ecf7..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C_flow_control_loop_pipe_sequential_init.v +++ /dev/null @@ -1,104 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module read_C_flow_control_loop_pipe_sequential_init( - ap_clk, - ap_rst, - ap_start, - ap_ready, - ap_done, - ap_start_int, - ap_ready_int, - ap_done_int, - ap_continue_int, - ap_loop_init, - ap_loop_exit_ready, - ap_loop_exit_done -); - -input ap_clk; -input ap_rst; - -//Block level handshake with outside loop -input ap_start; -output ap_ready; -output ap_done; - -//Block level handshake with loop body -output ap_start_int; -input ap_ready_int; -input ap_done_int; -output ap_continue_int; - -//Init live in variables -output ap_loop_init; -wire ap_loop_init; -reg ap_loop_init_int; -reg ap_done; -reg ap_done_cache; - -//Exit signal from loop body -input ap_loop_exit_ready; -input ap_loop_exit_done; - -// power-on initialization -initial begin -#0 ap_loop_init_int = 1'b1; -#0 ap_done_cache = 1'b0; -end - -assign ap_start_int = ap_start; - -assign ap_continue_int = 1'b1; - -assign ap_ready = ap_loop_exit_ready; - -//ap_loop_init is valid for the first II -//of the first loop run so as to enable -//the init block ops which are pushed into -//the first state of the pipeline region -always @ (posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_loop_exit_done == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_ready_int == 1'b1) begin - ap_loop_init_int <= 1'b0; - end -end - -assign ap_loop_init = ap_loop_init_int & ap_start; - -// if no ap_continue port and current module is not top module, -// ap_done handshakes with ap_start. Internally, flow control sends out -// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle. -// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int -// is asserted, so DUT can start the next run -always @(posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_done_cache <= 1'b0; - end else if (ap_done_int == 1'b1) begin - ap_done_cache <= 1'b1; - end else if (ap_start_int == 1'b1) begin - ap_done_cache <= 1'b0; - end -end - -// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start -always @(*) -begin - if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C_mul_mul_14ns_28s_32_4_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C_mul_mul_14ns_28s_32_4_1.v deleted file mode 100644 index 59c84132..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C_mul_mul_14ns_28s_32_4_1.v +++ /dev/null @@ -1,62 +0,0 @@ - -`timescale 1 ns / 1 ps - - module read_C_mul_mul_14ns_28s_32_4_1_DSP48_0(clk, rst, ce, a, b, p); -input clk; -input rst; -input ce; -input [14 - 1 : 0] a; -input signed [28 - 1 : 0] b; -output signed [32 - 1 : 0] p; - -reg signed [32 - 1 : 0] p_reg; - -reg [14 - 1 : 0] a_reg; -reg signed [28 - 1 : 0] b_reg; - -reg signed [32 - 1 : 0] p_reg_tmp; - -always @ (posedge clk) begin - if (ce) begin - a_reg <= a; - b_reg <= b; - p_reg_tmp <= $signed({1'b0, a_reg}) * b_reg; - p_reg <= p_reg_tmp; - end -end - -assign p = p_reg; - -endmodule -`timescale 1 ns / 1 ps -module read_C_mul_mul_14ns_28s_32_4_1( - clk, - reset, - ce, - din0, - din1, - dout); - -parameter ID = 32'd1; -parameter NUM_STAGE = 32'd1; -parameter din0_WIDTH = 32'd1; -parameter din1_WIDTH = 32'd1; -parameter dout_WIDTH = 32'd1; -input clk; -input reset; -input ce; -input[din0_WIDTH - 1:0] din0; -input[din1_WIDTH - 1:0] din1; -output[dout_WIDTH - 1:0] dout; - - - -read_C_mul_mul_14ns_28s_32_4_1_DSP48_0 read_C_mul_mul_14ns_28s_32_4_1_DSP48_0_U( - .clk( clk ), - .rst( reset ), - .ce( ce ), - .a( din0 ), - .b( din1 ), - .p( dout )); - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C_read_C_Pipeline_rd_C.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C_read_C_Pipeline_rd_C.v deleted file mode 100644 index 35ca451d..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_C_read_C_Pipeline_rd_C.v +++ /dev/null @@ -1,303 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module read_C_read_C_Pipeline_rd_C ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - num_ite_C, - fifo_C_din, - fifo_C_full_n, - fifo_C_write, - C_read_data_s_dout, - C_read_data_s_empty_n, - C_read_data_s_read, - C_read_addr_din, - C_read_addr_full_n, - C_read_addr_write -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [31:0] num_ite_C; -output [512:0] fifo_C_din; -input fifo_C_full_n; -output fifo_C_write; -input [512:0] C_read_data_s_dout; -input C_read_data_s_empty_n; -output C_read_data_s_read; -output [64:0] C_read_addr_din; -input C_read_addr_full_n; -output C_read_addr_write; - -reg ap_idle; -reg fifo_C_write; -reg C_read_data_s_read; -reg C_read_addr_write; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -wire ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln111_fu_128_p2; -reg ap_condition_exit_pp0_iter1_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -wire ap_block_pp0_stage0_11001; -reg [31:0] i_resp_fu_54; -wire [31:0] i_resp_2_fu_191_p2; -wire [0:0] and_ln47_fu_168_p2; -wire ap_loop_init; -wire ap_block_pp0_stage0; -reg [31:0] i_req_fu_58; -wire [31:0] i_req_2_fu_157_p2; -wire [0:0] and_ln43_fu_138_p2; -wire ap_block_pp0_stage0_01001; -wire [0:0] tmp_8_nbreadreq_fu_91_p3; -wire signed [31:0] icmp_ln43_fu_133_p0; -wire [0:0] icmp_ln43_fu_133_p2; -wire [0:0] and_ln43_fu_138_p1; -wire signed [31:0] sext_ln44_fu_144_p0; -wire signed [63:0] sext_ln44_fu_144_p1; -wire signed [31:0] i_req_2_fu_157_p0; -wire [0:0] and_ln47_fu_168_p0; -wire [511:0] trunc_ln146_fu_178_p1; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -reg ap_condition_190; -reg ap_condition_193; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -read_C_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter1_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter1_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - i_req_fu_58 <= 32'd0; - end else if ((1'b1 == ap_condition_190)) begin - i_req_fu_58 <= i_req_2_fu_157_p2; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - i_resp_fu_54 <= 32'd0; - end else if ((1'b1 == ap_condition_193)) begin - i_resp_fu_54 <= i_resp_2_fu_191_p2; - end - end -end - -always @ (*) begin - if (((1'd1 == and_ln43_fu_138_p2) & (icmp_ln111_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == C_read_addr_full_n) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - C_read_addr_write = 1'b1; - end else begin - C_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln47_fu_168_p2) & (icmp_ln111_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == C_read_data_s_empty_n) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - C_read_data_s_read = 1'b1; - end else begin - C_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln111_fu_128_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter1_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter1_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_start_int == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln47_fu_168_p2) & (fifo_C_full_n == 1'b1) & (icmp_ln111_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_C_write = 1'b1; - end else begin - fifo_C_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign C_read_addr_din = {{1'd0}, {sext_ln44_fu_144_p1}}; - -assign and_ln43_fu_138_p1 = C_read_addr_full_n; - -assign and_ln43_fu_138_p2 = (icmp_ln43_fu_133_p2 & and_ln43_fu_138_p1); - -assign and_ln47_fu_168_p0 = fifo_C_full_n; - -assign and_ln47_fu_168_p2 = (tmp_8_nbreadreq_fu_91_p3 & and_ln47_fu_168_p0); - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_01001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_condition_190 = ((1'd1 == and_ln43_fu_138_p2) & (icmp_ln111_fu_128_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -always @ (*) begin - ap_condition_193 = ((1'd1 == and_ln47_fu_168_p2) & (icmp_ln111_fu_128_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter1_stage0; - -assign fifo_C_din = {{1'd0}, {trunc_ln146_fu_178_p1}}; - -assign i_req_2_fu_157_p0 = i_req_fu_58; - -assign i_req_2_fu_157_p2 = ($signed(i_req_2_fu_157_p0) + $signed(32'd1)); - -assign i_resp_2_fu_191_p2 = (i_resp_fu_54 + 32'd1); - -assign icmp_ln111_fu_128_p2 = (($signed(i_resp_fu_54) < $signed(num_ite_C)) ? 1'b1 : 1'b0); - -assign icmp_ln43_fu_133_p0 = i_req_fu_58; - -assign icmp_ln43_fu_133_p2 = (($signed(icmp_ln43_fu_133_p0) < $signed(num_ite_C)) ? 1'b1 : 1'b0); - -assign sext_ln44_fu_144_p0 = i_req_fu_58; - -assign sext_ln44_fu_144_p1 = sext_ln44_fu_144_p0; - -assign tmp_8_nbreadreq_fu_91_p3 = C_read_data_s_empty_n; - -assign trunc_ln146_fu_178_p1 = C_read_data_s_dout[511:0]; - -endmodule //read_C_read_C_Pipeline_rd_C diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr.v deleted file mode 100644 index 7dfacc79..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr.v +++ /dev/null @@ -1,484 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="read_edge_list_ptr_read_edge_list_ptr,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=3236,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=164,HLS_SYN_LUT=422,HLS_VERSION=2022_2}" *) - -module read_edge_list_ptr ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - num_ite, - M, - P_N, - K, - edge_list_ptr_read_addr_din, - edge_list_ptr_read_addr_full_n, - edge_list_ptr_read_addr_write, - edge_list_ptr_read_data_s_dout, - edge_list_ptr_read_data_s_empty_n, - edge_list_ptr_read_data_s_read, - edge_list_ptr_read_data_peek_dout, - edge_list_ptr_read_data_peek_empty_n, - edge_list_ptr_read_data_peek_read, - edge_list_ptr_write_addr_din, - edge_list_ptr_write_addr_full_n, - edge_list_ptr_write_addr_write, - edge_list_ptr_write_data_din, - edge_list_ptr_write_data_full_n, - edge_list_ptr_write_data_write, - edge_list_ptr_write_resp_s_dout, - edge_list_ptr_write_resp_s_empty_n, - edge_list_ptr_write_resp_s_read, - edge_list_ptr_write_resp_peek_dout, - edge_list_ptr_write_resp_peek_empty_n, - edge_list_ptr_write_resp_peek_read, - fifo_edge_list_ptr_din, - fifo_edge_list_ptr_full_n, - fifo_edge_list_ptr_write, - PE_inst_din, - PE_inst_full_n, - PE_inst_write -); - -parameter ap_ST_fsm_state1 = 6'd1; -parameter ap_ST_fsm_state2 = 6'd2; -parameter ap_ST_fsm_state3 = 6'd4; -parameter ap_ST_fsm_state4 = 6'd8; -parameter ap_ST_fsm_state5 = 6'd16; -parameter ap_ST_fsm_state6 = 6'd32; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [31:0] num_ite; -input [31:0] M; -input [31:0] P_N; -input [31:0] K; -output [64:0] edge_list_ptr_read_addr_din; -input edge_list_ptr_read_addr_full_n; -output edge_list_ptr_read_addr_write; -input [32:0] edge_list_ptr_read_data_s_dout; -input edge_list_ptr_read_data_s_empty_n; -output edge_list_ptr_read_data_s_read; -input [32:0] edge_list_ptr_read_data_peek_dout; -input edge_list_ptr_read_data_peek_empty_n; -output edge_list_ptr_read_data_peek_read; -output [64:0] edge_list_ptr_write_addr_din; -input edge_list_ptr_write_addr_full_n; -output edge_list_ptr_write_addr_write; -output [32:0] edge_list_ptr_write_data_din; -input edge_list_ptr_write_data_full_n; -output edge_list_ptr_write_data_write; -input [8:0] edge_list_ptr_write_resp_s_dout; -input edge_list_ptr_write_resp_s_empty_n; -output edge_list_ptr_write_resp_s_read; -input [8:0] edge_list_ptr_write_resp_peek_dout; -input edge_list_ptr_write_resp_peek_empty_n; -output edge_list_ptr_write_resp_peek_read; -output [32:0] fifo_edge_list_ptr_din; -input fifo_edge_list_ptr_full_n; -output fifo_edge_list_ptr_write; -output [32:0] PE_inst_din; -input PE_inst_full_n; -output PE_inst_write; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg edge_list_ptr_read_addr_write; -reg edge_list_ptr_read_data_s_read; -reg fifo_edge_list_ptr_write; -reg[32:0] PE_inst_din; -reg PE_inst_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [5:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -reg PE_inst_blk_n; -wire ap_CS_fsm_state2; -wire ap_CS_fsm_state3; -wire ap_CS_fsm_state4; -wire [31:0] num_ite_plus1_fu_312_p2; -reg [31:0] num_ite_plus1_reg_373; -wire signed [29:0] grp_fu_340_p2; -reg signed [29:0] rp_time_N_reg_378; -wire grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_start; -wire grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_done; -wire grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_idle; -wire grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_ready; -wire [32:0] grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_fifo_edge_list_ptr_din; -wire grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_fifo_edge_list_ptr_write; -wire grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_edge_list_ptr_read_data_s_read; -wire [64:0] grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_edge_list_ptr_read_addr_din; -wire grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_edge_list_ptr_read_addr_write; -reg grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_start_reg; -wire ap_CS_fsm_state5; -wire [0:0] icmp_ln105_fu_324_p2; -wire ap_CS_fsm_state6; -reg [27:0] rp_fu_98; -wire [27:0] rp_2_fu_329_p2; -reg ap_block_state1; -wire [32:0] p_s_fu_220_p3; -wire [32:0] p_2_fu_286_p3; -wire [32:0] p_3_fu_295_p3; -wire [32:0] p_0_fu_303_p3; -wire [15:0] N_fu_216_p1; -wire [15:0] N16_fu_233_p4; -wire [0:0] icmp_ln101_fu_243_p2; -wire signed [15:0] rp_time_fu_249_p3; -wire [16:0] zext_ln99_fu_229_p1; -wire [16:0] add_ln103_fu_261_p2; -wire [13:0] lshr_ln_fu_267_p4; -wire [29:0] zext_ln105_fu_320_p1; -wire [13:0] grp_fu_340_p1; -reg grp_fu_340_ce; -reg [5:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -reg ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -reg ap_ST_fsm_state4_blk; -wire ap_ST_fsm_state5_blk; -reg ap_ST_fsm_state6_blk; -wire [29:0] grp_fu_340_p10; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 6'd1; -#0 grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_start_reg = 1'b0; -end - -read_edge_list_ptr_read_edge_list_ptr_Pipeline_rd_ptr grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_start), - .ap_done(grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_done), - .ap_idle(grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_idle), - .ap_ready(grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_ready), - .num_ite_plus1(num_ite_plus1_reg_373), - .fifo_edge_list_ptr_din(grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_fifo_edge_list_ptr_din), - .fifo_edge_list_ptr_full_n(fifo_edge_list_ptr_full_n), - .fifo_edge_list_ptr_write(grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_fifo_edge_list_ptr_write), - .edge_list_ptr_read_data_s_dout(edge_list_ptr_read_data_s_dout), - .edge_list_ptr_read_data_s_empty_n(edge_list_ptr_read_data_s_empty_n), - .edge_list_ptr_read_data_s_read(grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_edge_list_ptr_read_data_s_read), - .edge_list_ptr_read_addr_din(grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_edge_list_ptr_read_addr_din), - .edge_list_ptr_read_addr_full_n(edge_list_ptr_read_addr_full_n), - .edge_list_ptr_read_addr_write(grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_edge_list_ptr_read_addr_write) -); - -read_edge_list_ptr_mul_mul_16s_14ns_30_4_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 16 ), - .din1_WIDTH( 14 ), - .dout_WIDTH( 30 )) -mul_mul_16s_14ns_30_4_1_U5( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .din0(rp_time_fu_249_p3), - .din1(grp_fu_340_p1), - .ce(grp_fu_340_ce), - .dout(grp_fu_340_p2) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_start_reg <= 1'b0; - end else begin - if (((1'b1 == ap_CS_fsm_state5) & (icmp_ln105_fu_324_p2 == 1'd1))) begin - grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_start_reg <= 1'b1; - end else if ((grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_ready == 1'b1)) begin - grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if ((~((1'b0 == PE_inst_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - rp_fu_98 <= 28'd0; - end else if (((1'b1 == ap_CS_fsm_state5) & (icmp_ln105_fu_324_p2 == 1'd1))) begin - rp_fu_98 <= rp_2_fu_329_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state4)) begin - num_ite_plus1_reg_373 <= num_ite_plus1_fu_312_p2; - rp_time_N_reg_378 <= grp_fu_340_p2; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin - PE_inst_blk_n = PE_inst_full_n; - end else begin - PE_inst_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state4) & (1'b1 == PE_inst_full_n))) begin - PE_inst_din = p_0_fu_303_p3; - end else if (((1'b1 == ap_CS_fsm_state3) & (1'b1 == PE_inst_full_n))) begin - PE_inst_din = p_3_fu_295_p3; - end else if (((1'b1 == ap_CS_fsm_state2) & (1'b1 == PE_inst_full_n))) begin - PE_inst_din = p_2_fu_286_p3; - end else if ((~((1'b0 == PE_inst_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - PE_inst_din = p_s_fu_220_p3; - end else begin - PE_inst_din = 'bx; - end -end - -always @ (*) begin - if ((((1'b1 == ap_CS_fsm_state4) & (1'b1 == PE_inst_full_n)) | ((1'b1 == ap_CS_fsm_state3) & (1'b1 == PE_inst_full_n)) | ((1'b1 == ap_CS_fsm_state2) & (1'b1 == PE_inst_full_n)) | (~((1'b0 == PE_inst_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin - PE_inst_write = 1'b1; - end else begin - PE_inst_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == PE_inst_full_n) | (ap_start == 1'b0))) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -always @ (*) begin - if ((1'b0 == PE_inst_full_n)) begin - ap_ST_fsm_state2_blk = 1'b1; - end else begin - ap_ST_fsm_state2_blk = 1'b0; - end -end - -always @ (*) begin - if ((1'b0 == PE_inst_full_n)) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -always @ (*) begin - if ((1'b0 == PE_inst_full_n)) begin - ap_ST_fsm_state4_blk = 1'b1; - end else begin - ap_ST_fsm_state4_blk = 1'b0; - end -end - -assign ap_ST_fsm_state5_blk = 1'b0; - -always @ (*) begin - if ((grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_done == 1'b0)) begin - ap_ST_fsm_state6_blk = 1'b1; - end else begin - ap_ST_fsm_state6_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state5) & (icmp_ln105_fu_324_p2 == 1'd0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state5) & (icmp_ln105_fu_324_p2 == 1'd0))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - edge_list_ptr_read_addr_write = grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_edge_list_ptr_read_addr_write; - end else begin - edge_list_ptr_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - edge_list_ptr_read_data_s_read = grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_edge_list_ptr_read_data_s_read; - end else begin - edge_list_ptr_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - fifo_edge_list_ptr_write = grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_fifo_edge_list_ptr_write; - end else begin - fifo_edge_list_ptr_write = 1'b0; - end -end - -always @ (*) begin - if ((((1'b1 == ap_CS_fsm_state4) & (1'b1 == PE_inst_full_n)) | ((1'b1 == ap_CS_fsm_state3) & (1'b1 == PE_inst_full_n)) | ((1'b1 == ap_CS_fsm_state2) & (1'b1 == PE_inst_full_n)) | (~((1'b0 == PE_inst_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin - grp_fu_340_ce = 1'b1; - end else begin - grp_fu_340_ce = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if ((~((1'b0 == PE_inst_full_n) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - if (((1'b1 == ap_CS_fsm_state2) & (1'b1 == PE_inst_full_n))) begin - ap_NS_fsm = ap_ST_fsm_state3; - end else begin - ap_NS_fsm = ap_ST_fsm_state2; - end - end - ap_ST_fsm_state3 : begin - if (((1'b1 == ap_CS_fsm_state3) & (1'b1 == PE_inst_full_n))) begin - ap_NS_fsm = ap_ST_fsm_state4; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - ap_ST_fsm_state4 : begin - if (((1'b1 == ap_CS_fsm_state4) & (1'b1 == PE_inst_full_n))) begin - ap_NS_fsm = ap_ST_fsm_state5; - end else begin - ap_NS_fsm = ap_ST_fsm_state4; - end - end - ap_ST_fsm_state5 : begin - if (((1'b1 == ap_CS_fsm_state5) & (icmp_ln105_fu_324_p2 == 1'd0))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state6; - end - end - ap_ST_fsm_state6 : begin - if (((1'b1 == ap_CS_fsm_state6) & (grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_done == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state5; - end else begin - ap_NS_fsm = ap_ST_fsm_state6; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign N16_fu_233_p4 = {{P_N[31:16]}}; - -assign N_fu_216_p1 = P_N[15:0]; - -assign add_ln103_fu_261_p2 = (zext_ln99_fu_229_p1 + 17'd7); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; - -assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; - -assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; - -always @ (*) begin - ap_block_state1 = ((1'b0 == PE_inst_full_n) | (ap_start == 1'b0)); -end - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign edge_list_ptr_read_addr_din = grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_edge_list_ptr_read_addr_din; - -assign edge_list_ptr_read_data_peek_read = 1'b0; - -assign edge_list_ptr_write_addr_din = 65'd0; - -assign edge_list_ptr_write_addr_write = 1'b0; - -assign edge_list_ptr_write_data_din = 33'd0; - -assign edge_list_ptr_write_data_write = 1'b0; - -assign edge_list_ptr_write_resp_peek_read = 1'b0; - -assign edge_list_ptr_write_resp_s_read = 1'b0; - -assign fifo_edge_list_ptr_din = grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_fifo_edge_list_ptr_din; - -assign grp_fu_340_p1 = grp_fu_340_p10; - -assign grp_fu_340_p10 = lshr_ln_fu_267_p4; - -assign grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_start = grp_read_edge_list_ptr_Pipeline_rd_ptr_fu_205_ap_start_reg; - -assign icmp_ln101_fu_243_p2 = ((N16_fu_233_p4 == 16'd0) ? 1'b1 : 1'b0); - -assign icmp_ln105_fu_324_p2 = (($signed(zext_ln105_fu_320_p1) < $signed(rp_time_N_reg_378)) ? 1'b1 : 1'b0); - -assign lshr_ln_fu_267_p4 = {{add_ln103_fu_261_p2[16:3]}}; - -assign num_ite_plus1_fu_312_p2 = (num_ite + 32'd1); - -assign p_0_fu_303_p3 = {{1'd0}, {K}}; - -assign p_2_fu_286_p3 = {{1'd0}, {M}}; - -assign p_3_fu_295_p3 = {{1'd0}, {P_N}}; - -assign p_s_fu_220_p3 = {{1'd0}, {num_ite}}; - -assign rp_2_fu_329_p2 = (rp_fu_98 + 28'd1); - -assign rp_time_fu_249_p3 = ((icmp_ln101_fu_243_p2[0:0] == 1'b1) ? 16'd1 : N16_fu_233_p4); - -assign zext_ln105_fu_320_p1 = rp_fu_98; - -assign zext_ln99_fu_229_p1 = N_fu_216_p1; - -endmodule //read_edge_list_ptr diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr_flow_control_loop_pipe_sequential_init.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr_flow_control_loop_pipe_sequential_init.v deleted file mode 100644 index e13e855f..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr_flow_control_loop_pipe_sequential_init.v +++ /dev/null @@ -1,104 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module read_edge_list_ptr_flow_control_loop_pipe_sequential_init( - ap_clk, - ap_rst, - ap_start, - ap_ready, - ap_done, - ap_start_int, - ap_ready_int, - ap_done_int, - ap_continue_int, - ap_loop_init, - ap_loop_exit_ready, - ap_loop_exit_done -); - -input ap_clk; -input ap_rst; - -//Block level handshake with outside loop -input ap_start; -output ap_ready; -output ap_done; - -//Block level handshake with loop body -output ap_start_int; -input ap_ready_int; -input ap_done_int; -output ap_continue_int; - -//Init live in variables -output ap_loop_init; -wire ap_loop_init; -reg ap_loop_init_int; -reg ap_done; -reg ap_done_cache; - -//Exit signal from loop body -input ap_loop_exit_ready; -input ap_loop_exit_done; - -// power-on initialization -initial begin -#0 ap_loop_init_int = 1'b1; -#0 ap_done_cache = 1'b0; -end - -assign ap_start_int = ap_start; - -assign ap_continue_int = 1'b1; - -assign ap_ready = ap_loop_exit_ready; - -//ap_loop_init is valid for the first II -//of the first loop run so as to enable -//the init block ops which are pushed into -//the first state of the pipeline region -always @ (posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_loop_exit_done == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_ready_int == 1'b1) begin - ap_loop_init_int <= 1'b0; - end -end - -assign ap_loop_init = ap_loop_init_int & ap_start; - -// if no ap_continue port and current module is not top module, -// ap_done handshakes with ap_start. Internally, flow control sends out -// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle. -// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int -// is asserted, so DUT can start the next run -always @(posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_done_cache <= 1'b0; - end else if (ap_done_int == 1'b1) begin - ap_done_cache <= 1'b1; - end else if (ap_start_int == 1'b1) begin - ap_done_cache <= 1'b0; - end -end - -// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start -always @(*) -begin - if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr_mul_mul_16s_14ns_30_4_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr_mul_mul_16s_14ns_30_4_1.v deleted file mode 100644 index 362acc6a..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr_mul_mul_16s_14ns_30_4_1.v +++ /dev/null @@ -1,62 +0,0 @@ - -`timescale 1 ns / 1 ps - - module read_edge_list_ptr_mul_mul_16s_14ns_30_4_1_DSP48_0(clk, rst, ce, a, b, p); -input clk; -input rst; -input ce; -input signed [16 - 1 : 0] a; -input [14 - 1 : 0] b; -output signed [30 - 1 : 0] p; - -reg signed [30 - 1 : 0] p_reg; - -reg signed [16 - 1 : 0] a_reg; -reg [14 - 1 : 0] b_reg; - -reg signed [30 - 1 : 0] p_reg_tmp; - -always @ (posedge clk) begin - if (ce) begin - a_reg <= a; - b_reg <= b; - p_reg_tmp <= a_reg * $signed({1'b0, b_reg}); - p_reg <= p_reg_tmp; - end -end - -assign p = p_reg; - -endmodule -`timescale 1 ns / 1 ps -module read_edge_list_ptr_mul_mul_16s_14ns_30_4_1( - clk, - reset, - ce, - din0, - din1, - dout); - -parameter ID = 32'd1; -parameter NUM_STAGE = 32'd1; -parameter din0_WIDTH = 32'd1; -parameter din1_WIDTH = 32'd1; -parameter dout_WIDTH = 32'd1; -input clk; -input reset; -input ce; -input[din0_WIDTH - 1:0] din0; -input[din1_WIDTH - 1:0] din1; -output[dout_WIDTH - 1:0] dout; - - - -read_edge_list_ptr_mul_mul_16s_14ns_30_4_1_DSP48_0 read_edge_list_ptr_mul_mul_16s_14ns_30_4_1_DSP48_0_U( - .clk( clk ), - .rst( reset ), - .ce( ce ), - .a( din0 ), - .b( din1 ), - .p( dout )); - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr_read_edge_list_ptr_Pipeline_rd_ptr.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr_read_edge_list_ptr_Pipeline_rd_ptr.v deleted file mode 100644 index fffbc6e3..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/read_edge_list_ptr_read_edge_list_ptr_Pipeline_rd_ptr.v +++ /dev/null @@ -1,303 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module read_edge_list_ptr_read_edge_list_ptr_Pipeline_rd_ptr ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - num_ite_plus1, - fifo_edge_list_ptr_din, - fifo_edge_list_ptr_full_n, - fifo_edge_list_ptr_write, - edge_list_ptr_read_data_s_dout, - edge_list_ptr_read_data_s_empty_n, - edge_list_ptr_read_data_s_read, - edge_list_ptr_read_addr_din, - edge_list_ptr_read_addr_full_n, - edge_list_ptr_read_addr_write -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [31:0] num_ite_plus1; -output [32:0] fifo_edge_list_ptr_din; -input fifo_edge_list_ptr_full_n; -output fifo_edge_list_ptr_write; -input [32:0] edge_list_ptr_read_data_s_dout; -input edge_list_ptr_read_data_s_empty_n; -output edge_list_ptr_read_data_s_read; -output [64:0] edge_list_ptr_read_addr_din; -input edge_list_ptr_read_addr_full_n; -output edge_list_ptr_read_addr_write; - -reg ap_idle; -reg fifo_edge_list_ptr_write; -reg edge_list_ptr_read_data_s_read; -reg edge_list_ptr_read_addr_write; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -wire ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln109_fu_128_p2; -reg ap_condition_exit_pp0_iter1_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -wire ap_block_pp0_stage0_11001; -reg [31:0] i_resp_fu_54; -wire [31:0] i_resp_2_fu_191_p2; -wire [0:0] and_ln47_fu_168_p2; -wire ap_loop_init; -wire ap_block_pp0_stage0; -reg [31:0] i_req_fu_58; -wire [31:0] i_req_2_fu_157_p2; -wire [0:0] and_ln43_fu_138_p2; -wire ap_block_pp0_stage0_01001; -wire [0:0] tmp_4_nbreadreq_fu_91_p3; -wire signed [31:0] icmp_ln43_fu_133_p0; -wire [0:0] icmp_ln43_fu_133_p2; -wire [0:0] and_ln43_fu_138_p1; -wire signed [31:0] sext_ln44_fu_144_p0; -wire signed [63:0] sext_ln44_fu_144_p1; -wire signed [31:0] i_req_2_fu_157_p0; -wire [0:0] and_ln47_fu_168_p0; -wire [31:0] trunc_ln78_fu_178_p1; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -reg ap_condition_190; -reg ap_condition_193; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -read_edge_list_ptr_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter1_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter1_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - i_req_fu_58 <= 32'd0; - end else if ((1'b1 == ap_condition_190)) begin - i_req_fu_58 <= i_req_2_fu_157_p2; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - i_resp_fu_54 <= 32'd0; - end else if ((1'b1 == ap_condition_193)) begin - i_resp_fu_54 <= i_resp_2_fu_191_p2; - end - end -end - -always @ (*) begin - if (((icmp_ln109_fu_128_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter1_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter1_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_start_int == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln43_fu_138_p2) & (edge_list_ptr_read_addr_full_n == 1'b1) & (icmp_ln109_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - edge_list_ptr_read_addr_write = 1'b1; - end else begin - edge_list_ptr_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln47_fu_168_p2) & (edge_list_ptr_read_data_s_empty_n == 1'b1) & (icmp_ln109_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - edge_list_ptr_read_data_s_read = 1'b1; - end else begin - edge_list_ptr_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln47_fu_168_p2) & (fifo_edge_list_ptr_full_n == 1'b1) & (icmp_ln109_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_edge_list_ptr_write = 1'b1; - end else begin - fifo_edge_list_ptr_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign and_ln43_fu_138_p1 = edge_list_ptr_read_addr_full_n; - -assign and_ln43_fu_138_p2 = (icmp_ln43_fu_133_p2 & and_ln43_fu_138_p1); - -assign and_ln47_fu_168_p0 = fifo_edge_list_ptr_full_n; - -assign and_ln47_fu_168_p2 = (tmp_4_nbreadreq_fu_91_p3 & and_ln47_fu_168_p0); - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_01001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_condition_190 = ((1'd1 == and_ln43_fu_138_p2) & (icmp_ln109_fu_128_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -always @ (*) begin - ap_condition_193 = ((1'd1 == and_ln47_fu_168_p2) & (icmp_ln109_fu_128_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter1_stage0; - -assign edge_list_ptr_read_addr_din = {{1'd0}, {sext_ln44_fu_144_p1}}; - -assign fifo_edge_list_ptr_din = {{1'd0}, {trunc_ln78_fu_178_p1}}; - -assign i_req_2_fu_157_p0 = i_req_fu_58; - -assign i_req_2_fu_157_p2 = ($signed(i_req_2_fu_157_p0) + $signed(32'd1)); - -assign i_resp_2_fu_191_p2 = (i_resp_fu_54 + 32'd1); - -assign icmp_ln109_fu_128_p2 = (($signed(i_resp_fu_54) < $signed(num_ite_plus1)) ? 1'b1 : 1'b0); - -assign icmp_ln43_fu_133_p0 = i_req_fu_58; - -assign icmp_ln43_fu_133_p2 = (($signed(icmp_ln43_fu_133_p0) < $signed(num_ite_plus1)) ? 1'b1 : 1'b0); - -assign sext_ln44_fu_144_p0 = i_req_fu_58; - -assign sext_ln44_fu_144_p1 = sext_ln44_fu_144_p0; - -assign tmp_4_nbreadreq_fu_91_p3 = edge_list_ptr_read_data_s_empty_n; - -assign trunc_ln78_fu_178_p1 = edge_list_ptr_read_data_s_dout[31:0]; - -endmodule //read_edge_list_ptr_read_edge_list_ptr_Pipeline_rd_ptr diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/relay_station.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/relay_station.v deleted file mode 100644 index 632152cc..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/relay_station.v +++ /dev/null @@ -1,525 +0,0 @@ -`default_nettype none - -// first-word fall-through (FWFT) FIFO that is friendly for floorplanning -module relay_station #( - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 5, - parameter DEPTH = 2, - parameter LEVEL = 2, - parameter CONNECT = 1 // add api to disconnect the relay station -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - - wire full_n [LEVEL:0]; - wire empty_n [LEVEL:0]; - wire [DATA_WIDTH-1:0] data [LEVEL:0]; - - // both full_n and write are registered, thus one level of relay_station cause - // two additional latency for the almost full fifo - parameter GRACE_PERIOD = LEVEL * 2; - parameter REAL_DEPTH = GRACE_PERIOD + DEPTH + 4; - parameter REAL_ADDR_WIDTH = $clog2(REAL_DEPTH); - - genvar i; - generate - if (CONNECT > 0) begin - if (LEVEL > 0) begin - - for (i = 0; i < LEVEL; i = i + 1) begin : inst - if (i < LEVEL - 1) begin - fifo_reg #( - .DATA_WIDTH(DATA_WIDTH) - ) unit ( - .clk(clk), - .reset(reset), - - // connect to fifo[i+1] - .if_empty_n(empty_n[i+1]), - .if_read_ce(if_read_ce), - .if_read (full_n[i+1]), - .if_dout (data[i+1]), - - // connect to fifo[i-1] - .if_full_n (full_n[i]), - .if_write_ce(if_write_ce), - .if_write (empty_n[i]), - .if_din (data[i]) - ); - - end else begin - (* keep = "true" *) fifo_almost_full #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(REAL_ADDR_WIDTH), - .DEPTH(REAL_DEPTH), - .GRACE_PERIOD(GRACE_PERIOD) - ) unit ( - .clk(clk), - .reset(reset), - - // connect to fifo[i+1] - .if_empty_n(empty_n[i+1]), - .if_read_ce(if_read_ce), - .if_read (full_n[i+1]), - .if_dout (data[i+1]), - - // connect to fifo[i-1] - .if_full_n (full_n[i]), - .if_write_ce(if_write_ce), - .if_write (empty_n[i]), - .if_din (data[i]) - ); - end - end - - // write - assign if_full_n = full_n[0]; // output - assign empty_n[0] = if_write & full_n[0]; // input - assign data[0] = if_din; // input - - // read - assign if_empty_n = empty_n[LEVEL]; // output - assign full_n[LEVEL] = if_read; // input - assign if_dout = data[LEVEL]; // output - - end - - // LEVEL == 0 - else begin - assign if_full_n = if_read; // output - assign if_empty_n = if_write; // output - assign if_dout = if_din; // output - end - end - - // disconnect the relay station - else begin - assign if_full_n = 0; // output - assign if_empty_n = 0; // output - // leave the dout port dangling to facilitate pruning - // assign if_dout = 0; // output - end - endgenerate - -endmodule // relay_station - -///////////////////////////////////////////////////////////// - -module fifo_reg #( - parameter DATA_WIDTH = 32 -) ( - input wire clk, - input wire reset, - - // write - (* keep = "true" *) - output reg if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - (* keep = "true" *) - output reg if_empty_n, - input wire if_read_ce, - input wire if_read, - (* keep = "true" *) - output reg [DATA_WIDTH-1:0] if_dout -); - - always @ (posedge clk) begin - if_dout <= if_din; - if_empty_n <= if_write; - if_full_n <= if_read; - end - -endmodule - -///////////////////////////////////////////////////////////////// - -// first-word fall-through (FWFT) FIFO -module fifo_almost_full #( - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 5, - parameter DEPTH = 32, - parameter GRACE_PERIOD = 2 -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - -generate - if (DATA_WIDTH >= 36 && DEPTH >= 4096) begin : uram - fifo_bram_almost_full #( - .MEM_STYLE ("ultra"), - .DATA_WIDTH (DATA_WIDTH), - .ADDR_WIDTH (ADDR_WIDTH), - .DEPTH (DEPTH), - .GRACE_PERIOD(GRACE_PERIOD) - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end else if (DEPTH >= 128) begin : bram - fifo_bram_almost_full #( - .MEM_STYLE ("block"), - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .DEPTH (DEPTH), - .GRACE_PERIOD(GRACE_PERIOD) /*********/ - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end else begin : srl - fifo_srl_almost_full #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .DEPTH (DEPTH), - .GRACE_PERIOD(GRACE_PERIOD) /*********/ - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end -endgenerate - -endmodule // fifo - -///////////////////////////////////////////////////////////////// - -module fifo_srl_almost_full ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - -parameter MEM_STYLE = "shiftreg"; -parameter DATA_WIDTH = 32'd32; -parameter ADDR_WIDTH = 32'd4; -parameter DEPTH = 5'd16; - -/*******************************************/ -parameter GRACE_PERIOD = 2; -/*******************************************/ - -parameter REAL_DEPTH = DEPTH < 4 ? 4 : DEPTH; -parameter REAL_ADDR_WIDTH = $clog2(REAL_DEPTH)+1; - -wire[REAL_ADDR_WIDTH - 1:0] shiftReg_addr ; -wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; -wire shiftReg_ce; -reg[REAL_ADDR_WIDTH:0] mOutPtr = ~{(REAL_ADDR_WIDTH+1){1'b0}}; -reg internal_empty_n = 0, internal_full_n = 1; - -assign if_empty_n = internal_empty_n; - -/*******************************************/ -// assign if_full_n = internal_full_n; -reg almost_full_q; -wire almost_full = mOutPtr >= REAL_DEPTH - 1 - GRACE_PERIOD - 1 && mOutPtr != ~{REAL_ADDR_WIDTH+1{1'b0}}; -always @ (posedge clk) almost_full_q <= almost_full; -assign if_full_n = ~almost_full_q; -/*******************************************/ - -assign shiftReg_data = if_din; -assign if_dout = shiftReg_q; - -always @ (posedge clk) begin - if (reset == 1'b1) - begin - mOutPtr <= ~{REAL_ADDR_WIDTH+1{1'b0}}; - internal_empty_n <= 1'b0; - internal_full_n <= 1'b1; - end - else begin - if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && - ((if_write & if_write_ce) == 0 | internal_full_n == 0)) - begin - mOutPtr <= mOutPtr - 5'd1; - if (mOutPtr == 0) - internal_empty_n <= 1'b0; - internal_full_n <= 1'b1; - end - else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && - ((if_write & if_write_ce) == 1 & internal_full_n == 1)) - begin - mOutPtr <= mOutPtr + 5'd1; - internal_empty_n <= 1'b1; - if (mOutPtr == REAL_DEPTH - 5'd2) - internal_full_n <= 1'b0; - end - end -end - -assign shiftReg_addr = mOutPtr[REAL_ADDR_WIDTH] == 1'b0 ? mOutPtr[REAL_ADDR_WIDTH-1:0]:{REAL_ADDR_WIDTH{1'b0}}; -assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; - -fifo_srl_almost_full_internal -#( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(REAL_ADDR_WIDTH), - .DEPTH(REAL_DEPTH)) -U_fifo_w32_d16_A_ram ( - .clk(clk), - .data(shiftReg_data), - .ce(shiftReg_ce), - .a(shiftReg_addr), - .q(shiftReg_q)); - -endmodule - -module fifo_srl_almost_full_internal ( - input wire clk, - input wire [DATA_WIDTH-1:0] data, - input wire ce, - input wire [ADDR_WIDTH-1:0] a, - output wire [DATA_WIDTH-1:0] q -); - -parameter DATA_WIDTH = 32'd32; -parameter ADDR_WIDTH = 32'd4; -parameter DEPTH = 5'd16; - -(* shreg_extract = "yes" *) reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1]; -integer i; - -always @ (posedge clk) - begin - if (ce) - begin - for (i=0;i= DEPTH - 1 - GRACE_PERIOD); -//assign if_full_n = full_n; -assign if_full_n = ~almost_full; -/**************************************/ - -assign if_empty_n = dout_valid; -assign if_dout = dout_buf; -assign push = full_n & if_write_ce & if_write; -assign pop = empty_n & if_read_ce & (~dout_valid | if_read); -assign wnext = !push ? waddr : - (waddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : waddr + 1'd1; -assign rnext = !pop ? raddr : - (raddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : raddr + 1'd1; - - - -// waddr -always @(posedge clk) begin - if (reset) - waddr <= {ADDR_WIDTH{1'b0}}; - else - waddr <= wnext; -end - -// raddr -always @(posedge clk) begin - if (reset) - raddr <= {ADDR_WIDTH{1'b0}}; - else - raddr <= rnext; -end - -// used -always @(posedge clk) begin - if (reset) - used <= {ADDR_WIDTH{1'b0}}; - else if (push && !pop) - used <= used + 1'b1; - else if (!push && pop) - used <= used - 1'b1; -end - -// full_n -always @(posedge clk) begin - if (reset) - full_n <= 1'b1; - else if (push && !pop) - full_n <= (used != DepthM1); - else if (!push && pop) - full_n <= 1'b1; -end - -// empty_n -always @(posedge clk) begin - if (reset) - empty_n <= 1'b0; - else if (push && !pop) - empty_n <= 1'b1; - else if (!push && pop) - empty_n <= (used != {{(ADDR_WIDTH-1){1'b0}},1'b1}); -end - -// mem -always @(posedge clk) begin - if (push) - mem[waddr] <= if_din; -end - -// q_buf -always @(posedge clk) begin - q_buf <= mem[rnext]; -end - -// q_tmp -always @(posedge clk) begin - if (reset) - q_tmp <= {DATA_WIDTH{1'b0}}; - else if (push) - q_tmp <= if_din; -end - -// show_ahead -always @(posedge clk) begin - if (reset) - show_ahead <= 1'b0; - else if (push && used == {{(ADDR_WIDTH-1){1'b0}},pop}) - show_ahead <= 1'b1; - else - show_ahead <= 1'b0; -end - -// dout_buf -always @(posedge clk) begin - if (reset) - dout_buf <= {DATA_WIDTH{1'b0}}; - else if (pop) - dout_buf <= show_ahead? q_tmp : q_buf; -end - -// dout_valid -always @(posedge clk) begin - if (reset) - dout_valid <= 1'b0; - else if (pop) - dout_valid <= 1'b1; - else if (if_read_ce & if_read) - dout_valid <= 1'b0; -end - -endmodule // fifo_bram - -`default_nettype wire diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C.v deleted file mode 100644 index 51a8c8db..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C.v +++ /dev/null @@ -1,472 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="write_C_write_C,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.414450,HLS_SYN_LAT=2000038,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=197,HLS_SYN_LUT=448,HLS_VERSION=2022_2}" *) - -module write_C ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - wrC_inst_s_dout, - wrC_inst_s_empty_n, - wrC_inst_s_read, - wrC_inst_peek_dout, - wrC_inst_peek_empty_n, - wrC_inst_peek_read, - fifo_C_s_dout, - fifo_C_s_empty_n, - fifo_C_s_read, - fifo_C_peek_dout, - fifo_C_peek_empty_n, - fifo_C_peek_read, - C_out_read_addr_din, - C_out_read_addr_full_n, - C_out_read_addr_write, - C_out_read_data_s_dout, - C_out_read_data_s_empty_n, - C_out_read_data_s_read, - C_out_read_data_peek_dout, - C_out_read_data_peek_empty_n, - C_out_read_data_peek_read, - C_out_write_addr_din, - C_out_write_addr_full_n, - C_out_write_addr_write, - C_out_write_data_din, - C_out_write_data_full_n, - C_out_write_data_write, - C_out_write_resp_s_dout, - C_out_write_resp_s_empty_n, - C_out_write_resp_s_read, - C_out_write_resp_peek_dout, - C_out_write_resp_peek_empty_n, - C_out_write_resp_peek_read -); - -parameter ap_ST_fsm_state1 = 8'd1; -parameter ap_ST_fsm_state2 = 8'd2; -parameter ap_ST_fsm_state3 = 8'd4; -parameter ap_ST_fsm_state4 = 8'd8; -parameter ap_ST_fsm_state5 = 8'd16; -parameter ap_ST_fsm_state6 = 8'd32; -parameter ap_ST_fsm_state7 = 8'd64; -parameter ap_ST_fsm_state8 = 8'd128; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [32:0] wrC_inst_s_dout; -input wrC_inst_s_empty_n; -output wrC_inst_s_read; -input [32:0] wrC_inst_peek_dout; -input wrC_inst_peek_empty_n; -output wrC_inst_peek_read; -input [512:0] fifo_C_s_dout; -input fifo_C_s_empty_n; -output fifo_C_s_read; -input [512:0] fifo_C_peek_dout; -input fifo_C_peek_empty_n; -output fifo_C_peek_read; -output [64:0] C_out_read_addr_din; -input C_out_read_addr_full_n; -output C_out_read_addr_write; -input [512:0] C_out_read_data_s_dout; -input C_out_read_data_s_empty_n; -output C_out_read_data_s_read; -input [512:0] C_out_read_data_peek_dout; -input C_out_read_data_peek_empty_n; -output C_out_read_data_peek_read; -output [64:0] C_out_write_addr_din; -input C_out_write_addr_full_n; -output C_out_write_addr_write; -output [512:0] C_out_write_data_din; -input C_out_write_data_full_n; -output C_out_write_data_write; -input [8:0] C_out_write_resp_s_dout; -input C_out_write_resp_s_empty_n; -output C_out_write_resp_s_read; -input [8:0] C_out_write_resp_peek_dout; -input C_out_write_resp_peek_empty_n; -output C_out_write_resp_peek_read; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg wrC_inst_s_read; -reg fifo_C_s_read; -reg C_out_write_addr_write; -reg C_out_write_data_write; -reg C_out_write_resp_s_read; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [7:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -reg wrC_inst_s_blk_n; -wire ap_CS_fsm_state2; -reg signed [27:0] trunc_ln_reg_318; -reg [15:0] N16_reg_323; -reg [13:0] lshr_ln_reg_329; -wire ap_CS_fsm_state3; -wire [15:0] rp_time_fu_275_p3; -reg [15:0] rp_time_reg_344; -wire ap_CS_fsm_state6; -wire signed [31:0] grp_fu_305_p2; -reg [31:0] num_ite_C_reg_349; -wire grp_write_C_Pipeline_wr_C_fu_192_ap_start; -wire grp_write_C_Pipeline_wr_C_fu_192_ap_done; -wire grp_write_C_Pipeline_wr_C_fu_192_ap_idle; -wire grp_write_C_Pipeline_wr_C_fu_192_ap_ready; -wire grp_write_C_Pipeline_wr_C_fu_192_C_out_write_resp_s_read; -wire grp_write_C_Pipeline_wr_C_fu_192_fifo_C_s_read; -wire [64:0] grp_write_C_Pipeline_wr_C_fu_192_C_out_write_addr_din; -wire grp_write_C_Pipeline_wr_C_fu_192_C_out_write_addr_write; -wire [512:0] grp_write_C_Pipeline_wr_C_fu_192_C_out_write_data_din; -wire grp_write_C_Pipeline_wr_C_fu_192_C_out_write_data_write; -reg grp_write_C_Pipeline_wr_C_fu_192_ap_start_reg; -wire ap_CS_fsm_state7; -wire [0:0] icmp_ln115_fu_289_p2; -wire ap_CS_fsm_state8; -reg [14:0] rp_fu_94; -wire [14:0] rp_2_fu_294_p2; -reg ap_block_state1; -wire [31:0] M_fu_205_p1; -wire [31:0] add_ln113_fu_209_p2; -wire [15:0] N_fu_230_p1; -wire [16:0] zext_ln112_fu_244_p1; -wire [16:0] add_ln113_1_fu_248_p2; -wire [0:0] icmp_ln111_fu_270_p2; -wire [15:0] zext_ln115_fu_285_p1; -wire [13:0] grp_fu_305_p0; -reg [7:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -reg ap_ST_fsm_state2_blk; -wire ap_ST_fsm_state3_blk; -wire ap_ST_fsm_state4_blk; -wire ap_ST_fsm_state5_blk; -wire ap_ST_fsm_state6_blk; -wire ap_ST_fsm_state7_blk; -reg ap_ST_fsm_state8_blk; -wire [31:0] grp_fu_305_p00; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 8'd1; -#0 grp_write_C_Pipeline_wr_C_fu_192_ap_start_reg = 1'b0; -end - -write_C_write_C_Pipeline_wr_C grp_write_C_Pipeline_wr_C_fu_192( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_write_C_Pipeline_wr_C_fu_192_ap_start), - .ap_done(grp_write_C_Pipeline_wr_C_fu_192_ap_done), - .ap_idle(grp_write_C_Pipeline_wr_C_fu_192_ap_idle), - .ap_ready(grp_write_C_Pipeline_wr_C_fu_192_ap_ready), - .num_ite_C(num_ite_C_reg_349), - .C_out_write_resp_s_dout(C_out_write_resp_s_dout), - .C_out_write_resp_s_empty_n(C_out_write_resp_s_empty_n), - .C_out_write_resp_s_read(grp_write_C_Pipeline_wr_C_fu_192_C_out_write_resp_s_read), - .fifo_C_s_dout(fifo_C_s_dout), - .fifo_C_s_empty_n(fifo_C_s_empty_n), - .fifo_C_s_read(grp_write_C_Pipeline_wr_C_fu_192_fifo_C_s_read), - .C_out_write_addr_din(grp_write_C_Pipeline_wr_C_fu_192_C_out_write_addr_din), - .C_out_write_addr_full_n(C_out_write_addr_full_n), - .C_out_write_addr_write(grp_write_C_Pipeline_wr_C_fu_192_C_out_write_addr_write), - .C_out_write_data_din(grp_write_C_Pipeline_wr_C_fu_192_C_out_write_data_din), - .C_out_write_data_full_n(C_out_write_data_full_n), - .C_out_write_data_write(grp_write_C_Pipeline_wr_C_fu_192_C_out_write_data_write) -); - -write_C_mul_mul_14ns_28s_32_4_1 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 14 ), - .din1_WIDTH( 28 ), - .dout_WIDTH( 32 )) -mul_mul_14ns_28s_32_4_1_U6( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .din0(grp_fu_305_p0), - .din1(trunc_ln_reg_318), - .ce(1'b1), - .dout(grp_fu_305_p2) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_write_C_Pipeline_wr_C_fu_192_ap_start_reg <= 1'b0; - end else begin - if (((1'b1 == ap_CS_fsm_state7) & (icmp_ln115_fu_289_p2 == 1'd1))) begin - grp_write_C_Pipeline_wr_C_fu_192_ap_start_reg <= 1'b1; - end else if ((grp_write_C_Pipeline_wr_C_fu_192_ap_ready == 1'b1)) begin - grp_write_C_Pipeline_wr_C_fu_192_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if ((~((wrC_inst_s_empty_n == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - rp_fu_94 <= 15'd0; - end else if (((1'b1 == ap_CS_fsm_state7) & (icmp_ln115_fu_289_p2 == 1'd1))) begin - rp_fu_94 <= rp_2_fu_294_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state2)) begin - N16_reg_323 <= {{wrC_inst_s_dout[31:16]}}; - lshr_ln_reg_329 <= {{add_ln113_1_fu_248_p2[16:3]}}; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - num_ite_C_reg_349 <= grp_fu_305_p2; - rp_time_reg_344 <= rp_time_fu_275_p3; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state1)) begin - trunc_ln_reg_318 <= {{add_ln113_fu_209_p2[31:4]}}; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state8)) begin - C_out_write_addr_write = grp_write_C_Pipeline_wr_C_fu_192_C_out_write_addr_write; - end else begin - C_out_write_addr_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state8)) begin - C_out_write_data_write = grp_write_C_Pipeline_wr_C_fu_192_C_out_write_data_write; - end else begin - C_out_write_data_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state8)) begin - C_out_write_resp_s_read = grp_write_C_Pipeline_wr_C_fu_192_C_out_write_resp_s_read; - end else begin - C_out_write_resp_s_read = 1'b0; - end -end - -always @ (*) begin - if (((wrC_inst_s_empty_n == 1'b0) | (ap_start == 1'b0))) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -always @ (*) begin - if ((wrC_inst_s_empty_n == 1'b0)) begin - ap_ST_fsm_state2_blk = 1'b1; - end else begin - ap_ST_fsm_state2_blk = 1'b0; - end -end - -assign ap_ST_fsm_state3_blk = 1'b0; - -assign ap_ST_fsm_state4_blk = 1'b0; - -assign ap_ST_fsm_state5_blk = 1'b0; - -assign ap_ST_fsm_state6_blk = 1'b0; - -assign ap_ST_fsm_state7_blk = 1'b0; - -always @ (*) begin - if ((grp_write_C_Pipeline_wr_C_fu_192_ap_done == 1'b0)) begin - ap_ST_fsm_state8_blk = 1'b1; - end else begin - ap_ST_fsm_state8_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state7) & (icmp_ln115_fu_289_p2 == 1'd0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state7) & (icmp_ln115_fu_289_p2 == 1'd0))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state8)) begin - fifo_C_s_read = grp_write_C_Pipeline_wr_C_fu_192_fifo_C_s_read; - end else begin - fifo_C_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin - wrC_inst_s_blk_n = wrC_inst_s_empty_n; - end else begin - wrC_inst_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if ((((wrC_inst_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state2)) | (~((wrC_inst_s_empty_n == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin - wrC_inst_s_read = 1'b1; - end else begin - wrC_inst_s_read = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if ((~((wrC_inst_s_empty_n == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - if (((wrC_inst_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin - ap_NS_fsm = ap_ST_fsm_state3; - end else begin - ap_NS_fsm = ap_ST_fsm_state2; - end - end - ap_ST_fsm_state3 : begin - ap_NS_fsm = ap_ST_fsm_state4; - end - ap_ST_fsm_state4 : begin - ap_NS_fsm = ap_ST_fsm_state5; - end - ap_ST_fsm_state5 : begin - ap_NS_fsm = ap_ST_fsm_state6; - end - ap_ST_fsm_state6 : begin - ap_NS_fsm = ap_ST_fsm_state7; - end - ap_ST_fsm_state7 : begin - if (((1'b1 == ap_CS_fsm_state7) & (icmp_ln115_fu_289_p2 == 1'd0))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state8; - end - end - ap_ST_fsm_state8 : begin - if (((1'b1 == ap_CS_fsm_state8) & (grp_write_C_Pipeline_wr_C_fu_192_ap_done == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state7; - end else begin - ap_NS_fsm = ap_ST_fsm_state8; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign C_out_read_addr_din = 65'd0; - -assign C_out_read_addr_write = 1'b0; - -assign C_out_read_data_peek_read = 1'b0; - -assign C_out_read_data_s_read = 1'b0; - -assign C_out_write_addr_din = grp_write_C_Pipeline_wr_C_fu_192_C_out_write_addr_din; - -assign C_out_write_data_din = grp_write_C_Pipeline_wr_C_fu_192_C_out_write_data_din; - -assign C_out_write_resp_peek_read = 1'b0; - -assign M_fu_205_p1 = wrC_inst_s_dout[31:0]; - -assign N_fu_230_p1 = wrC_inst_s_dout[15:0]; - -assign add_ln113_1_fu_248_p2 = (zext_ln112_fu_244_p1 + 17'd7); - -assign add_ln113_fu_209_p2 = (M_fu_205_p1 + 32'd15); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; - -assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; - -assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; - -always @ (*) begin - ap_block_state1 = ((wrC_inst_s_empty_n == 1'b0) | (ap_start == 1'b0)); -end - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign fifo_C_peek_read = 1'b0; - -assign grp_fu_305_p0 = grp_fu_305_p00; - -assign grp_fu_305_p00 = lshr_ln_reg_329; - -assign grp_write_C_Pipeline_wr_C_fu_192_ap_start = grp_write_C_Pipeline_wr_C_fu_192_ap_start_reg; - -assign icmp_ln111_fu_270_p2 = ((N16_reg_323 == 16'd0) ? 1'b1 : 1'b0); - -assign icmp_ln115_fu_289_p2 = (($signed(zext_ln115_fu_285_p1) < $signed(rp_time_reg_344)) ? 1'b1 : 1'b0); - -assign rp_2_fu_294_p2 = (rp_fu_94 + 15'd1); - -assign rp_time_fu_275_p3 = ((icmp_ln111_fu_270_p2[0:0] == 1'b1) ? 16'd1 : N16_reg_323); - -assign wrC_inst_peek_read = 1'b0; - -assign zext_ln112_fu_244_p1 = N_fu_230_p1; - -assign zext_ln115_fu_285_p1 = rp_fu_94; - -endmodule //write_C diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C_flow_control_loop_pipe_sequential_init.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C_flow_control_loop_pipe_sequential_init.v deleted file mode 100644 index 85ef1b7c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C_flow_control_loop_pipe_sequential_init.v +++ /dev/null @@ -1,104 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module write_C_flow_control_loop_pipe_sequential_init( - ap_clk, - ap_rst, - ap_start, - ap_ready, - ap_done, - ap_start_int, - ap_ready_int, - ap_done_int, - ap_continue_int, - ap_loop_init, - ap_loop_exit_ready, - ap_loop_exit_done -); - -input ap_clk; -input ap_rst; - -//Block level handshake with outside loop -input ap_start; -output ap_ready; -output ap_done; - -//Block level handshake with loop body -output ap_start_int; -input ap_ready_int; -input ap_done_int; -output ap_continue_int; - -//Init live in variables -output ap_loop_init; -wire ap_loop_init; -reg ap_loop_init_int; -reg ap_done; -reg ap_done_cache; - -//Exit signal from loop body -input ap_loop_exit_ready; -input ap_loop_exit_done; - -// power-on initialization -initial begin -#0 ap_loop_init_int = 1'b1; -#0 ap_done_cache = 1'b0; -end - -assign ap_start_int = ap_start; - -assign ap_continue_int = 1'b1; - -assign ap_ready = ap_loop_exit_ready; - -//ap_loop_init is valid for the first II -//of the first loop run so as to enable -//the init block ops which are pushed into -//the first state of the pipeline region -always @ (posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_loop_exit_done == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_ready_int == 1'b1) begin - ap_loop_init_int <= 1'b0; - end -end - -assign ap_loop_init = ap_loop_init_int & ap_start; - -// if no ap_continue port and current module is not top module, -// ap_done handshakes with ap_start. Internally, flow control sends out -// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle. -// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int -// is asserted, so DUT can start the next run -always @(posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_done_cache <= 1'b0; - end else if (ap_done_int == 1'b1) begin - ap_done_cache <= 1'b1; - end else if (ap_start_int == 1'b1) begin - ap_done_cache <= 1'b0; - end -end - -// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start -always @(*) -begin - if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C_mul_mul_14ns_28s_32_4_1.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C_mul_mul_14ns_28s_32_4_1.v deleted file mode 100644 index f19eee65..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C_mul_mul_14ns_28s_32_4_1.v +++ /dev/null @@ -1,62 +0,0 @@ - -`timescale 1 ns / 1 ps - - module write_C_mul_mul_14ns_28s_32_4_1_DSP48_0(clk, rst, ce, a, b, p); -input clk; -input rst; -input ce; -input [14 - 1 : 0] a; -input signed [28 - 1 : 0] b; -output signed [32 - 1 : 0] p; - -reg signed [32 - 1 : 0] p_reg; - -reg [14 - 1 : 0] a_reg; -reg signed [28 - 1 : 0] b_reg; - -reg signed [32 - 1 : 0] p_reg_tmp; - -always @ (posedge clk) begin - if (ce) begin - a_reg <= a; - b_reg <= b; - p_reg_tmp <= $signed({1'b0, a_reg}) * b_reg; - p_reg <= p_reg_tmp; - end -end - -assign p = p_reg; - -endmodule -`timescale 1 ns / 1 ps -module write_C_mul_mul_14ns_28s_32_4_1( - clk, - reset, - ce, - din0, - din1, - dout); - -parameter ID = 32'd1; -parameter NUM_STAGE = 32'd1; -parameter din0_WIDTH = 32'd1; -parameter din1_WIDTH = 32'd1; -parameter dout_WIDTH = 32'd1; -input clk; -input reset; -input ce; -input[din0_WIDTH - 1:0] din0; -input[din1_WIDTH - 1:0] din1; -output[dout_WIDTH - 1:0] dout; - - - -write_C_mul_mul_14ns_28s_32_4_1_DSP48_0 write_C_mul_mul_14ns_28s_32_4_1_DSP48_0_U( - .clk( clk ), - .rst( reset ), - .ce( ce ), - .a( din0 ), - .b( din1 ), - .p( dout )); - -endmodule diff --git a/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C_write_C_Pipeline_wr_C.v b/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C_write_C_Pipeline_wr_C.v deleted file mode 100644 index 37a221c4..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/hdl/write_C_write_C_Pipeline_wr_C.v +++ /dev/null @@ -1,334 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module write_C_write_C_Pipeline_wr_C ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - num_ite_C, - C_out_write_resp_s_dout, - C_out_write_resp_s_empty_n, - C_out_write_resp_s_read, - fifo_C_s_dout, - fifo_C_s_empty_n, - fifo_C_s_read, - C_out_write_addr_din, - C_out_write_addr_full_n, - C_out_write_addr_write, - C_out_write_data_din, - C_out_write_data_full_n, - C_out_write_data_write -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [31:0] num_ite_C; -input [8:0] C_out_write_resp_s_dout; -input C_out_write_resp_s_empty_n; -output C_out_write_resp_s_read; -input [512:0] fifo_C_s_dout; -input fifo_C_s_empty_n; -output fifo_C_s_read; -output [64:0] C_out_write_addr_din; -input C_out_write_addr_full_n; -output C_out_write_addr_write; -output [512:0] C_out_write_data_din; -input C_out_write_data_full_n; -output C_out_write_data_write; - -reg ap_idle; -reg C_out_write_resp_s_read; -reg fifo_C_s_read; -reg C_out_write_addr_write; -reg C_out_write_data_write; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -wire ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln119_fu_140_p2; -reg ap_condition_exit_pp0_iter1_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -wire ap_block_pp0_stage0_11001; -reg [31:0] i_resp_fu_60; -wire [31:0] i_resp_5_fu_241_p3; -wire ap_loop_init; -wire ap_block_pp0_stage0; -reg [31:0] i_req_fu_64; -wire [31:0] i_req_2_fu_198_p2; -wire [0:0] and_ln122_2_fu_162_p2; -wire [0:0] tmp_nbreadreq_fu_74_p3; -wire ap_block_pp0_stage0_01001; -wire [0:0] C_out_write_resp_s_read_nbread_fu_118_p2_0; -wire signed [31:0] icmp_ln122_fu_145_p0; -wire [0:0] and_ln122_1_fu_150_p0; -wire [0:0] and_ln122_1_fu_150_p1; -wire [0:0] and_ln122_1_fu_150_p2; -wire [0:0] and_ln122_fu_156_p2; -wire [0:0] icmp_ln122_fu_145_p2; -wire signed [31:0] sext_ln124_fu_168_p0; -wire signed [63:0] sext_ln124_fu_168_p1; -wire [511:0] trunc_ln146_fu_185_p1; -wire signed [31:0] i_req_2_fu_198_p0; -wire [7:0] elem_val_fu_217_p1; -wire [8:0] zext_ln132_fu_221_p1; -wire [8:0] add_ln132_fu_225_p2; -wire [31:0] zext_ln132_1_fu_231_p1; -wire [31:0] i_resp_4_fu_235_p2; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -reg ap_condition_227; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -write_C_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter1_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter1_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - i_req_fu_64 <= 32'd0; - end else if ((1'b1 == ap_condition_227)) begin - i_req_fu_64 <= i_req_2_fu_198_p2; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - i_resp_fu_60 <= 32'd0; - end else if (((icmp_ln119_fu_140_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin - i_resp_fu_60 <= i_resp_5_fu_241_p3; - end - end -end - -always @ (*) begin - if (((1'd1 == and_ln122_2_fu_162_p2) & (icmp_ln119_fu_140_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == C_out_write_addr_full_n) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - C_out_write_addr_write = 1'b1; - end else begin - C_out_write_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln122_2_fu_162_p2) & (icmp_ln119_fu_140_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == C_out_write_data_full_n) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - C_out_write_data_write = 1'b1; - end else begin - C_out_write_data_write = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln119_fu_140_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == C_out_write_resp_s_empty_n) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - C_out_write_resp_s_read = 1'b1; - end else begin - C_out_write_resp_s_read = 1'b0; - end -end - -always @ (*) begin - if (((icmp_ln119_fu_140_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter1_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter1_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (ap_start_int == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((1'd1 == and_ln122_2_fu_162_p2) & (fifo_C_s_empty_n == 1'b1) & (icmp_ln119_fu_140_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - fifo_C_s_read = 1'b1; - end else begin - fifo_C_s_read = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign C_out_write_addr_din = {{1'd0}, {sext_ln124_fu_168_p1}}; - -assign C_out_write_data_din = {{1'd0}, {trunc_ln146_fu_185_p1}}; - -assign C_out_write_resp_s_read_nbread_fu_118_p2_0 = C_out_write_resp_s_empty_n; - -assign add_ln132_fu_225_p2 = (zext_ln132_fu_221_p1 + 9'd1); - -assign and_ln122_1_fu_150_p0 = C_out_write_addr_full_n; - -assign and_ln122_1_fu_150_p1 = C_out_write_data_full_n; - -assign and_ln122_1_fu_150_p2 = (and_ln122_1_fu_150_p1 & and_ln122_1_fu_150_p0); - -assign and_ln122_2_fu_162_p2 = (icmp_ln122_fu_145_p2 & and_ln122_fu_156_p2); - -assign and_ln122_fu_156_p2 = (tmp_nbreadreq_fu_74_p3 & and_ln122_1_fu_150_p2); - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_01001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_condition_227 = ((1'd1 == and_ln122_2_fu_162_p2) & (icmp_ln119_fu_140_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter1_stage0; - -assign elem_val_fu_217_p1 = C_out_write_resp_s_dout[7:0]; - -assign i_req_2_fu_198_p0 = i_req_fu_64; - -assign i_req_2_fu_198_p2 = ($signed(i_req_2_fu_198_p0) + $signed(32'd1)); - -assign i_resp_4_fu_235_p2 = (zext_ln132_1_fu_231_p1 + i_resp_fu_60); - -assign i_resp_5_fu_241_p3 = ((C_out_write_resp_s_read_nbread_fu_118_p2_0[0:0] == 1'b1) ? i_resp_4_fu_235_p2 : i_resp_fu_60); - -assign icmp_ln119_fu_140_p2 = (($signed(i_resp_fu_60) < $signed(num_ite_C)) ? 1'b1 : 1'b0); - -assign icmp_ln122_fu_145_p0 = i_req_fu_64; - -assign icmp_ln122_fu_145_p2 = (($signed(icmp_ln122_fu_145_p0) < $signed(num_ite_C)) ? 1'b1 : 1'b0); - -assign sext_ln124_fu_168_p0 = i_req_fu_64; - -assign sext_ln124_fu_168_p1 = sext_ln124_fu_168_p0; - -assign tmp_nbreadreq_fu_74_p3 = fifo_C_s_empty_n; - -assign trunc_ln146_fu_185_p1 = fifo_C_s_dout[511:0]; - -assign zext_ln132_1_fu_231_p1 = add_ln132_fu_225_p2; - -assign zext_ln132_fu_221_p1 = elem_val_fu_217_p1; - -endmodule //write_C_write_C_Pipeline_wr_C diff --git a/benchmarks/tapa_flow/sextans/design/generated/log/tapac.INFO b/benchmarks/tapa_flow/sextans/design/generated/log/tapac.INFO deleted file mode 120000 index a4197cac..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/log/tapac.INFO +++ /dev/null @@ -1 +0,0 @@ -tapac.inglewood.Licheng-Guo.log.INFO.20240329-144003.2834442 \ No newline at end of file diff --git a/benchmarks/tapa_flow/sextans/design/generated/log/tapac.inglewood.Licheng-Guo.log.INFO.20240329-144003.2834442 b/benchmarks/tapa_flow/sextans/design/generated/log/tapac.inglewood.Licheng-Guo.log.INFO.20240329-144003.2834442 deleted file mode 100644 index ef96fb78..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/log/tapac.inglewood.Licheng-Guo.log.INFO.20240329-144003.2834442 +++ /dev/null @@ -1,3487 +0,0 @@ -I0329 14:40:03.060 tapa.util:184] logging level set to INFO -I0329 14:40:03.061 tapa.tapac:407] Executing all steps of tapac -I0329 14:40:03.061 tapa.tapac:521] running translated command: `tapa --work-dir=generated analyze --input=src/sextans.cpp --top=Sextans synth --part-num=xcu280-fsvh2892-2L-e --clock-period=3.33 link pack --output=generated/Sextans.xo` -I0329 14:40:03.062 tapa.util:184] logging level set to INFO -I0329 14:40:03.062 tapa.util:184] logging level set to INFO -I0329 14:40:03.062 tapa.tapa:54] tapa version: 0.0.20240120.1 -I0329 14:40:03.062 tapa.tapa:54] tapa version: 0.0.20240120.1 -I0329 14:40:03.062 tapa.tapa:58] Python recursion limit set to 3000 -I0329 14:40:03.062 tapa.tapa:58] Python recursion limit set to 3000 -I0329 14:40:03.142 tapa.steps.analyze:151] added vendor include path `/opt/tools/xilinx/Vitis_HLS/2022.2/include` -I0329 14:40:03.142 tapa.steps.analyze:151] added vendor include path `/opt/tools/xilinx/Vitis_HLS/2022.2/include` -I0329 14:40:03.143 tapa.steps.analyze:248] Running tapacc command: /usr/bin/tapacc generated/flatten/flatten-f5eeaffa-sextans.cpp -top Sextans -- -std=c++17 -I /home/Licheng-Guo/dev/tapa/backend/python/tapa/../../../src -isystem /opt/tools/xilinx/Vitis_HLS/2022.2/include -stdlib=libc++ -isystem /usr/lib/llvm-17/include/c++/v1/ -isystem /usr/include/clang/17/include/ -isystem /usr/lib/clang/17/include/ -I0329 14:40:03.143 tapa.steps.analyze:248] Running tapacc command: /usr/bin/tapacc generated/flatten/flatten-f5eeaffa-sextans.cpp -top Sextans -- -std=c++17 -I /home/Licheng-Guo/dev/tapa/backend/python/tapa/../../../src -isystem /opt/tools/xilinx/Vitis_HLS/2022.2/include -stdlib=libc++ -isystem /usr/lib/llvm-17/include/c++/v1/ -isystem /usr/include/clang/17/include/ -isystem /usr/lib/clang/17/include/ -I0329 14:40:06.925 tapa.steps.common:92] writing TAPA graph to json `generated/graph.json`. -I0329 14:40:06.925 tapa.steps.common:92] writing TAPA graph to json `generated/graph.json`. -I0329 14:40:06.934 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0329 14:40:06.934 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0329 14:40:06.934 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0329 14:40:06.934 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0329 14:40:06.934 tapa.core:184] extracting HLS C++ files -I0329 14:40:06.934 tapa.core:184] extracting HLS C++ files -I0329 14:40:07.558 tapa.core:216] running HLS -I0329 14:40:07.558 tapa.core:216] running HLS -I0329 14:40:07.561 tapa.core:262] spawn 128 workers for parallel HLS synthesis of the tasks -I0329 14:40:07.561 tapa.core:262] spawn 128 workers for parallel HLS synthesis of the tasks -I0329 14:40:53.393 tapa.core:277] extracting RTL files -I0329 14:40:53.393 tapa.core:277] extracting RTL files -I0329 14:40:53.456 tapa.core:308] parsing RTL files and populating tasks -I0329 14:40:53.456 tapa.core:308] parsing RTL files and populating tasks -D0329 14:40:54.755 tapa.core:317] parsing FloatvAddFloatv -D0329 14:40:54.755 tapa.core:317] parsing FloatvAddFloatv -D0329 14:40:54.756 tapa.core:321] populating FloatvAddFloatv -D0329 14:40:54.756 tapa.core:321] populating FloatvAddFloatv -D0329 14:40:54.759 tapa.core:317] parsing FloatvMultConst -D0329 14:40:54.759 tapa.core:317] parsing FloatvMultConst -D0329 14:40:54.760 tapa.core:321] populating FloatvMultConst -D0329 14:40:54.760 tapa.core:321] populating FloatvMultConst -D0329 14:40:54.760 tapa.core:317] parsing Merger -D0329 14:40:54.760 tapa.core:317] parsing Merger -D0329 14:40:54.760 tapa.core:321] populating Merger -D0329 14:40:54.760 tapa.core:321] populating Merger -D0329 14:40:54.760 tapa.core:317] parsing PEG_Bmtx -D0329 14:40:54.760 tapa.core:317] parsing PEG_Bmtx -D0329 14:40:54.761 tapa.core:321] populating PEG_Bmtx -D0329 14:40:54.761 tapa.core:321] populating PEG_Bmtx -D0329 14:40:54.761 tapa.core:317] parsing PEG_Cmtx -D0329 14:40:54.761 tapa.core:317] parsing PEG_Cmtx -D0329 14:40:54.762 tapa.core:321] populating PEG_Cmtx -D0329 14:40:54.762 tapa.core:321] populating PEG_Cmtx -D0329 14:40:54.762 tapa.core:317] parsing Scatter_1_2 -D0329 14:40:54.762 tapa.core:317] parsing Scatter_1_2 -D0329 14:40:54.762 tapa.core:321] populating Scatter_1_2 -D0329 14:40:54.762 tapa.core:321] populating Scatter_1_2 -D0329 14:40:54.762 tapa.core:317] parsing black_hole_float_v16 -D0329 14:40:54.762 tapa.core:317] parsing black_hole_float_v16 -D0329 14:40:54.764 tapa.core:321] populating black_hole_float_v16 -D0329 14:40:54.764 tapa.core:321] populating black_hole_float_v16 -D0329 14:40:54.764 tapa.core:317] parsing black_hole_int -D0329 14:40:54.764 tapa.core:317] parsing black_hole_int -D0329 14:40:54.765 tapa.core:321] populating black_hole_int -D0329 14:40:54.765 tapa.core:321] populating black_hole_int -D0329 14:40:54.765 tapa.core:317] parsing read_A -D0329 14:40:54.765 tapa.core:317] parsing read_A -D0329 14:40:54.765 tapa.core:321] populating read_A -D0329 14:40:54.765 tapa.core:321] populating read_A -D0329 14:40:54.765 tapa.core:317] parsing read_B -D0329 14:40:54.765 tapa.core:317] parsing read_B -D0329 14:40:54.766 tapa.core:321] populating read_B -D0329 14:40:54.766 tapa.core:321] populating read_B -D0329 14:40:54.766 tapa.core:317] parsing read_C -D0329 14:40:54.766 tapa.core:317] parsing read_C -D0329 14:40:54.766 tapa.core:321] populating read_C -D0329 14:40:54.766 tapa.core:321] populating read_C -D0329 14:40:54.766 tapa.core:317] parsing read_edge_list_ptr -D0329 14:40:54.766 tapa.core:317] parsing read_edge_list_ptr -D0329 14:40:54.767 tapa.core:321] populating read_edge_list_ptr -D0329 14:40:54.767 tapa.core:321] populating read_edge_list_ptr -D0329 14:40:54.767 tapa.core:317] parsing write_C -D0329 14:40:54.767 tapa.core:317] parsing write_C -D0329 14:40:54.767 tapa.core:321] populating write_C -D0329 14:40:54.767 tapa.core:321] populating write_C -D0329 14:40:54.767 tapa.core:317] parsing Sextans -D0329 14:40:54.767 tapa.core:317] parsing Sextans -D0329 14:40:54.768 tapa.core:321] populating Sextans -D0329 14:40:54.768 tapa.core:321] populating Sextans -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_0.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_0.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_1.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_1.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_2.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_2.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_3.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_3.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_4' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_4.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_4' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_4.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_5' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_5.A' -D0329 14:40:54.774 tapa.task:149] mmap argument 'Sextans.edge_list_ch_5' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_5.A' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.edge_list_ch_6' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_6.A' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.edge_list_ch_6' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_6.A' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.edge_list_ch_7' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_7.A' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.edge_list_ch_7' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_A_7.A' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_B_ch_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_B_0.B' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_B_ch_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_B_0.B' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_B_ch_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_B_1.B' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_B_ch_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_B_1.B' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_B_ch_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_B_2.B' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_B_ch_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_B_2.B' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_B_ch_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_B_3.B' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_B_ch_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_B_3.B' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_0.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_0.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_1.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_1.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_2.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_2.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_3.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_3.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_4' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_4.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_4' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_4.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_5' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_5.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_5' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_5.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_6' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_6.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_6' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_6.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_7' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_7.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_in_7' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_C_7.C' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.edge_list_ptr' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_edge_list_ptr_0.edge_list_ptr' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.edge_list_ptr' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'read_edge_list_ptr_0.edge_list_ptr' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_0.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_0.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_1.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_1.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_2.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_2.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_3.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_3.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_4' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_4.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_4' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_4.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_5' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_5.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_5' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_5.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_6' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_6.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_6' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_6.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_7' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_7.C_out' -D0329 14:40:54.775 tapa.task:149] mmap argument 'Sextans.mat_C_ch_7' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'write_C_7.C_out' -I0329 14:40:54.776 tapa.core:325] instrumenting upper-level RTL -I0329 14:40:54.776 tapa.core:325] instrumenting upper-level RTL -I0329 14:40:54.776 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0329 14:40:54.776 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0329 14:40:54.778 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0329 14:40:54.778 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0329 14:40:54.778 tapa.core:452] top task register level set to 0 -I0329 14:40:54.778 tapa.core:452] top task register level set to 0 -I0329 14:40:54.778 tapa.core:456] instrumenting top-level RTL -I0329 14:40:54.778 tapa.core:456] instrumenting top-level RTL -D0329 14:40:54.781 tapa.core:529] instantiating FIFOs in Sextans -D0329 14:40:54.781 tapa.core:529] instantiating FIFOs in Sextans -D0329 14:40:54.782 tapa.core:542] instantiating Sextans.PE_inst_Sextans[0] -D0329 14:40:54.782 tapa.core:542] instantiating Sextans.PE_inst_Sextans[0] -D0329 14:40:54.782 tapa.core:542] instantiating Sextans.PE_inst_Sextans[10] -D0329 14:40:54.782 tapa.core:542] instantiating Sextans.PE_inst_Sextans[10] -D0329 14:40:54.783 tapa.core:542] instantiating Sextans.PE_inst_Sextans[11] -D0329 14:40:54.783 tapa.core:542] instantiating Sextans.PE_inst_Sextans[11] -D0329 14:40:54.783 tapa.core:542] instantiating Sextans.PE_inst_Sextans[12] -D0329 14:40:54.783 tapa.core:542] instantiating Sextans.PE_inst_Sextans[12] -D0329 14:40:54.783 tapa.core:542] instantiating Sextans.PE_inst_Sextans[13] -D0329 14:40:54.783 tapa.core:542] instantiating Sextans.PE_inst_Sextans[13] -D0329 14:40:54.783 tapa.core:542] instantiating Sextans.PE_inst_Sextans[14] -D0329 14:40:54.783 tapa.core:542] instantiating Sextans.PE_inst_Sextans[14] -D0329 14:40:54.784 tapa.core:542] instantiating Sextans.PE_inst_Sextans[15] -D0329 14:40:54.784 tapa.core:542] instantiating Sextans.PE_inst_Sextans[15] -D0329 14:40:54.784 tapa.core:542] instantiating Sextans.PE_inst_Sextans[16] -D0329 14:40:54.784 tapa.core:542] instantiating Sextans.PE_inst_Sextans[16] -D0329 14:40:54.784 tapa.core:542] instantiating Sextans.PE_inst_Sextans[1] -D0329 14:40:54.784 tapa.core:542] instantiating Sextans.PE_inst_Sextans[1] -D0329 14:40:54.784 tapa.core:542] instantiating Sextans.PE_inst_Sextans[2] -D0329 14:40:54.784 tapa.core:542] instantiating Sextans.PE_inst_Sextans[2] -D0329 14:40:54.784 tapa.core:542] instantiating Sextans.PE_inst_Sextans[3] -D0329 14:40:54.784 tapa.core:542] instantiating Sextans.PE_inst_Sextans[3] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[4] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[4] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[5] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[5] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[6] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[6] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[7] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[7] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[8] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[8] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[9] -D0329 14:40:54.785 tapa.core:542] instantiating Sextans.PE_inst_Sextans[9] -D0329 14:40:54.786 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[0] -D0329 14:40:54.786 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[0] -D0329 14:40:54.786 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[10] -D0329 14:40:54.786 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[10] -D0329 14:40:54.786 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[11] -D0329 14:40:54.786 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[11] -D0329 14:40:54.786 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[12] -D0329 14:40:54.786 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[12] -D0329 14:40:54.786 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[13] -D0329 14:40:54.786 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[13] -D0329 14:40:54.787 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[14] -D0329 14:40:54.787 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[14] -D0329 14:40:54.787 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[15] -D0329 14:40:54.787 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[15] -D0329 14:40:54.787 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[1] -D0329 14:40:54.787 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[1] -D0329 14:40:54.787 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[2] -D0329 14:40:54.787 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[2] -D0329 14:40:54.787 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[3] -D0329 14:40:54.787 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[3] -D0329 14:40:54.788 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[4] -D0329 14:40:54.788 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[4] -D0329 14:40:54.788 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[5] -D0329 14:40:54.788 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[5] -D0329 14:40:54.788 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[6] -D0329 14:40:54.788 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[6] -D0329 14:40:54.788 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[7] -D0329 14:40:54.788 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[7] -D0329 14:40:54.788 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[8] -D0329 14:40:54.788 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[8] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[9] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.PE_inst_to_Cmtx_Sextans[9] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.fifo_A_Sextans[0] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.fifo_A_Sextans[0] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.fifo_A_Sextans[1] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.fifo_A_Sextans[1] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.fifo_A_Sextans[2] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.fifo_A_Sextans[2] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.fifo_A_Sextans[3] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.fifo_A_Sextans[3] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.fifo_A_Sextans[4] -D0329 14:40:54.789 tapa.core:542] instantiating Sextans.fifo_A_Sextans[4] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_Sextans[5] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_Sextans[5] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_Sextans[6] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_Sextans[6] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_Sextans[7] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_Sextans[7] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[0] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[0] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[10] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[10] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[11] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[11] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[12] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[12] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[13] -D0329 14:40:54.790 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[13] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[14] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[14] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[15] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[15] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[1] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[1] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[2] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[2] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[3] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[3] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[4] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[4] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[5] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[5] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[6] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[6] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[7] -D0329 14:40:54.791 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[7] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[8] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[8] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[9] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_A_pe_Sextans[9] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[0] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[0] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[10] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[10] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[11] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[11] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[12] -D0329 14:40:54.792 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[12] -D0329 14:40:54.793 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[13] -D0329 14:40:54.793 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[13] -D0329 14:40:54.793 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[14] -D0329 14:40:54.793 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[14] -D0329 14:40:54.793 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[15] -D0329 14:40:54.793 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[15] -D0329 14:40:54.793 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[16] -D0329 14:40:54.793 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[16] -D0329 14:40:54.793 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[17] -D0329 14:40:54.793 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[17] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[18] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[18] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[19] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[19] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[1] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[1] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[20] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[20] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[21] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[21] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[22] -D0329 14:40:54.794 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[22] -D0329 14:40:54.795 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[23] -D0329 14:40:54.795 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[23] -D0329 14:40:54.795 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[24] -D0329 14:40:54.795 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[24] -D0329 14:40:54.795 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[25] -D0329 14:40:54.795 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[25] -D0329 14:40:54.795 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[26] -D0329 14:40:54.795 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[26] -D0329 14:40:54.795 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[27] -D0329 14:40:54.795 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[27] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[28] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[28] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[29] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[29] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[2] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[2] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[30] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[30] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[31] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[31] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[32] -D0329 14:40:54.796 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[32] -D0329 14:40:54.797 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[33] -D0329 14:40:54.797 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[33] -D0329 14:40:54.797 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[34] -D0329 14:40:54.797 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[34] -D0329 14:40:54.797 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[35] -D0329 14:40:54.797 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[35] -D0329 14:40:54.797 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[36] -D0329 14:40:54.797 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[36] -D0329 14:40:54.797 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[37] -D0329 14:40:54.797 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[37] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[38] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[38] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[39] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[39] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[3] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[3] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[40] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[40] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[41] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[41] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[42] -D0329 14:40:54.798 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[42] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[43] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[43] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[44] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[44] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[45] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[45] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[46] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[46] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[47] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[47] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[48] -D0329 14:40:54.799 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[48] -D0329 14:40:54.800 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[49] -D0329 14:40:54.800 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[49] -D0329 14:40:54.800 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[4] -D0329 14:40:54.800 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[4] -D0329 14:40:54.800 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[50] -D0329 14:40:54.800 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[50] -D0329 14:40:54.800 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[51] -D0329 14:40:54.800 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[51] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[52] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[52] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[53] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[53] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[54] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[54] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[55] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[55] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[56] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[56] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[57] -D0329 14:40:54.801 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[57] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[58] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[58] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[59] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[59] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[5] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[5] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[60] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[60] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[61] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[61] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[62] -D0329 14:40:54.802 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[62] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[63] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[63] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[64] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[64] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[65] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[65] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[66] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[66] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[67] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[67] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[6] -D0329 14:40:54.803 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[6] -D0329 14:40:54.804 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[7] -D0329 14:40:54.804 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[7] -D0329 14:40:54.804 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[8] -D0329 14:40:54.804 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[8] -D0329 14:40:54.804 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[9] -D0329 14:40:54.804 tapa.core:542] instantiating Sextans.fifo_B_pe_Sextans[9] -D0329 14:40:54.804 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[0] -D0329 14:40:54.804 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[0] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[1] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[1] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[2] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[2] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[3] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[3] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[4] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[4] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[5] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[5] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[6] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[6] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[7] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_Sextans[7] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[0] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[0] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[1] -D0329 14:40:54.805 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[1] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[2] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[2] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[3] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[3] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[4] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[4] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[5] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[5] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[6] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[6] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[7] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_Sextans[7] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[0] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[0] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[1] -D0329 14:40:54.806 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[1] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[2] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[2] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[3] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[3] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[4] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[4] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[5] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[5] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[6] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[6] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[7] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_ch_result_alpha_Sextans[7] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[0] -D0329 14:40:54.807 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[0] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[10] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[10] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[11] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[11] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[12] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[12] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[13] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[13] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[14] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[14] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[15] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[15] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[1] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[1] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[2] -D0329 14:40:54.808 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[2] -D0329 14:40:54.809 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[3] -D0329 14:40:54.809 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[3] -D0329 14:40:54.809 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[4] -D0329 14:40:54.809 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[4] -D0329 14:40:54.809 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[5] -D0329 14:40:54.809 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[5] -D0329 14:40:54.809 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[6] -D0329 14:40:54.809 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[6] -D0329 14:40:54.809 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[7] -D0329 14:40:54.809 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[7] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[8] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[8] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[9] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_pe_Sextans[9] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[0] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[0] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[1] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[1] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[2] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[2] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[3] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[3] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[4] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[4] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[5] -D0329 14:40:54.810 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[5] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[6] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[6] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[7] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_Sextans[7] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[0] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[0] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[1] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[1] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[2] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[2] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[3] -D0329 14:40:54.811 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[3] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[4] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[4] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[5] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[5] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[6] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[6] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[7] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_C_read_in_beta_Sextans[7] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[0] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[0] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[10] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[10] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[11] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[11] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[12] -D0329 14:40:54.812 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[12] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[13] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[13] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[14] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[14] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[15] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[15] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[16] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[16] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[17] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[17] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[18] -D0329 14:40:54.813 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[18] -D0329 14:40:54.814 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[19] -D0329 14:40:54.814 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[19] -D0329 14:40:54.814 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[1] -D0329 14:40:54.814 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[1] -D0329 14:40:54.814 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[20] -D0329 14:40:54.814 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[20] -D0329 14:40:54.814 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[21] -D0329 14:40:54.814 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[21] -D0329 14:40:54.814 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[22] -D0329 14:40:54.814 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[22] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[23] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[23] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[24] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[24] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[25] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[25] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[26] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[26] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[27] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[27] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[28] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[28] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[29] -D0329 14:40:54.815 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[29] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[2] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[2] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[30] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[30] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[31] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[31] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[32] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[32] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[33] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[33] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[34] -D0329 14:40:54.816 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[34] -D0329 14:40:54.817 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[35] -D0329 14:40:54.817 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[35] -D0329 14:40:54.817 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[36] -D0329 14:40:54.817 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[36] -D0329 14:40:54.817 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[37] -D0329 14:40:54.817 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[37] -D0329 14:40:54.817 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[38] -D0329 14:40:54.817 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[38] -D0329 14:40:54.817 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[39] -D0329 14:40:54.817 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[39] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[3] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[3] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[40] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[40] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[41] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[41] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[42] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[42] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[43] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[43] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[44] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[44] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[45] -D0329 14:40:54.818 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[45] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[46] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[46] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[47] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[47] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[48] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[48] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[49] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[49] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[4] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[4] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[50] -D0329 14:40:54.819 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[50] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[51] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[51] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[52] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[52] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[53] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[53] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[54] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[54] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[55] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[55] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[56] -D0329 14:40:54.820 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[56] -D0329 14:40:54.821 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[57] -D0329 14:40:54.821 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[57] -D0329 14:40:54.821 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[58] -D0329 14:40:54.821 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[58] -D0329 14:40:54.821 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[59] -D0329 14:40:54.821 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[59] -D0329 14:40:54.821 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[5] -D0329 14:40:54.821 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[5] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[60] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[60] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[61] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[61] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[62] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[62] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[63] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[63] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[6] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[6] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[7] -D0329 14:40:54.822 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[7] -D0329 14:40:54.823 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[8] -D0329 14:40:54.823 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[8] -D0329 14:40:54.823 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[9] -D0329 14:40:54.823 tapa.core:542] instantiating Sextans.fifo_aBvec_Sextans[9] -D0329 14:40:54.823 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[0] -D0329 14:40:54.823 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[0] -D0329 14:40:54.823 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[10] -D0329 14:40:54.823 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[10] -D0329 14:40:54.823 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[11] -D0329 14:40:54.823 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[11] -D0329 14:40:54.824 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[12] -D0329 14:40:54.824 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[12] -D0329 14:40:54.824 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[13] -D0329 14:40:54.824 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[13] -D0329 14:40:54.824 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[14] -D0329 14:40:54.824 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[14] -D0329 14:40:54.824 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[15] -D0329 14:40:54.824 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[15] -D0329 14:40:54.824 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[16] -D0329 14:40:54.824 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[16] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[1] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[1] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[2] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[2] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[3] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[3] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[4] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[4] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[5] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[5] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[6] -D0329 14:40:54.825 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[6] -D0329 14:40:54.826 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[7] -D0329 14:40:54.826 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[7] -D0329 14:40:54.826 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[8] -D0329 14:40:54.826 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[8] -D0329 14:40:54.826 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[9] -D0329 14:40:54.826 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_Sextans[9] -D0329 14:40:54.826 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[0] -D0329 14:40:54.826 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[0] -D0329 14:40:54.826 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[10] -D0329 14:40:54.826 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[10] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[11] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[11] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[12] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[12] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[13] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[13] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[14] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[14] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[15] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[15] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[1] -D0329 14:40:54.827 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[1] -D0329 14:40:54.828 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[2] -D0329 14:40:54.828 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[2] -D0329 14:40:54.828 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[3] -D0329 14:40:54.828 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[3] -D0329 14:40:54.828 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[4] -D0329 14:40:54.828 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[4] -D0329 14:40:54.828 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[5] -D0329 14:40:54.828 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[5] -D0329 14:40:54.828 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[6] -D0329 14:40:54.828 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[6] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[7] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[7] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[8] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[8] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[9] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.fifo_edge_list_ptr_to_Cmtx_Sextans[9] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[0] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[0] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[1] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[1] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[2] -D0329 14:40:54.829 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[2] -D0329 14:40:54.830 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[3] -D0329 14:40:54.830 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[3] -D0329 14:40:54.830 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[4] -D0329 14:40:54.830 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[4] -D0329 14:40:54.830 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[5] -D0329 14:40:54.830 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[5] -D0329 14:40:54.830 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[6] -D0329 14:40:54.830 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[6] -D0329 14:40:54.830 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[7] -D0329 14:40:54.830 tapa.core:542] instantiating Sextans.wrC_inst_Sextans[7] -D0329 14:40:54.830 tapa.core:507] connecting Sextans's children tasks -D0329 14:40:54.830 tapa.core:507] connecting Sextans's children tasks -D0329 14:40:54.983 tapa.core:598] instantiating children tasks in Sextans -D0329 14:40:54.983 tapa.core:598] instantiating children tasks in Sextans -D0329 14:40:55.012 tapa.core:671] pipelined signal: M => FloatvMultConst_0___M -D0329 14:40:55.012 tapa.core:671] pipelined signal: M => FloatvMultConst_0___M -D0329 14:40:55.012 tapa.core:671] pipelined signal: P_N => FloatvMultConst_0___P_N -D0329 14:40:55.012 tapa.core:671] pipelined signal: P_N => FloatvMultConst_0___P_N -D0329 14:40:55.012 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_0___beta_u -D0329 14:40:55.012 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_0___beta_u -D0329 14:40:55.013 tapa.core:671] pipelined signal: M => FloatvMultConst_1___M -D0329 14:40:55.013 tapa.core:671] pipelined signal: M => FloatvMultConst_1___M -D0329 14:40:55.013 tapa.core:671] pipelined signal: P_N => FloatvMultConst_1___P_N -D0329 14:40:55.013 tapa.core:671] pipelined signal: P_N => FloatvMultConst_1___P_N -D0329 14:40:55.013 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_1___beta_u -D0329 14:40:55.013 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_1___beta_u -D0329 14:40:55.014 tapa.core:671] pipelined signal: M => FloatvMultConst_2___M -D0329 14:40:55.014 tapa.core:671] pipelined signal: M => FloatvMultConst_2___M -D0329 14:40:55.014 tapa.core:671] pipelined signal: P_N => FloatvMultConst_2___P_N -D0329 14:40:55.014 tapa.core:671] pipelined signal: P_N => FloatvMultConst_2___P_N -D0329 14:40:55.014 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_2___beta_u -D0329 14:40:55.014 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_2___beta_u -D0329 14:40:55.015 tapa.core:671] pipelined signal: M => FloatvMultConst_3___M -D0329 14:40:55.015 tapa.core:671] pipelined signal: M => FloatvMultConst_3___M -D0329 14:40:55.015 tapa.core:671] pipelined signal: P_N => FloatvMultConst_3___P_N -D0329 14:40:55.015 tapa.core:671] pipelined signal: P_N => FloatvMultConst_3___P_N -D0329 14:40:55.015 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_3___beta_u -D0329 14:40:55.015 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_3___beta_u -D0329 14:40:55.016 tapa.core:671] pipelined signal: M => FloatvMultConst_4___M -D0329 14:40:55.016 tapa.core:671] pipelined signal: M => FloatvMultConst_4___M -D0329 14:40:55.016 tapa.core:671] pipelined signal: P_N => FloatvMultConst_4___P_N -D0329 14:40:55.016 tapa.core:671] pipelined signal: P_N => FloatvMultConst_4___P_N -D0329 14:40:55.017 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_4___beta_u -D0329 14:40:55.017 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_4___beta_u -D0329 14:40:55.017 tapa.core:671] pipelined signal: M => FloatvMultConst_5___M -D0329 14:40:55.017 tapa.core:671] pipelined signal: M => FloatvMultConst_5___M -D0329 14:40:55.018 tapa.core:671] pipelined signal: P_N => FloatvMultConst_5___P_N -D0329 14:40:55.018 tapa.core:671] pipelined signal: P_N => FloatvMultConst_5___P_N -D0329 14:40:55.018 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_5___beta_u -D0329 14:40:55.018 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_5___beta_u -D0329 14:40:55.019 tapa.core:671] pipelined signal: M => FloatvMultConst_6___M -D0329 14:40:55.019 tapa.core:671] pipelined signal: M => FloatvMultConst_6___M -D0329 14:40:55.019 tapa.core:671] pipelined signal: P_N => FloatvMultConst_6___P_N -D0329 14:40:55.019 tapa.core:671] pipelined signal: P_N => FloatvMultConst_6___P_N -D0329 14:40:55.019 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_6___beta_u -D0329 14:40:55.019 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_6___beta_u -D0329 14:40:55.020 tapa.core:671] pipelined signal: M => FloatvMultConst_7___M -D0329 14:40:55.020 tapa.core:671] pipelined signal: M => FloatvMultConst_7___M -D0329 14:40:55.020 tapa.core:671] pipelined signal: P_N => FloatvMultConst_7___P_N -D0329 14:40:55.020 tapa.core:671] pipelined signal: P_N => FloatvMultConst_7___P_N -D0329 14:40:55.020 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_7___beta_u -D0329 14:40:55.020 tapa.core:671] pipelined signal: beta_u => FloatvMultConst_7___beta_u -D0329 14:40:55.021 tapa.core:671] pipelined signal: M => FloatvMultConst_8___M -D0329 14:40:55.021 tapa.core:671] pipelined signal: M => FloatvMultConst_8___M -D0329 14:40:55.021 tapa.core:671] pipelined signal: P_N => FloatvMultConst_8___P_N -D0329 14:40:55.021 tapa.core:671] pipelined signal: P_N => FloatvMultConst_8___P_N -D0329 14:40:55.021 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_8___alpha_u -D0329 14:40:55.021 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_8___alpha_u -D0329 14:40:55.022 tapa.core:671] pipelined signal: M => FloatvMultConst_9___M -D0329 14:40:55.022 tapa.core:671] pipelined signal: M => FloatvMultConst_9___M -D0329 14:40:55.022 tapa.core:671] pipelined signal: P_N => FloatvMultConst_9___P_N -D0329 14:40:55.022 tapa.core:671] pipelined signal: P_N => FloatvMultConst_9___P_N -D0329 14:40:55.022 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_9___alpha_u -D0329 14:40:55.022 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_9___alpha_u -D0329 14:40:55.023 tapa.core:671] pipelined signal: M => FloatvMultConst_10___M -D0329 14:40:55.023 tapa.core:671] pipelined signal: M => FloatvMultConst_10___M -D0329 14:40:55.023 tapa.core:671] pipelined signal: P_N => FloatvMultConst_10___P_N -D0329 14:40:55.023 tapa.core:671] pipelined signal: P_N => FloatvMultConst_10___P_N -D0329 14:40:55.023 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_10___alpha_u -D0329 14:40:55.023 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_10___alpha_u -D0329 14:40:55.024 tapa.core:671] pipelined signal: M => FloatvMultConst_11___M -D0329 14:40:55.024 tapa.core:671] pipelined signal: M => FloatvMultConst_11___M -D0329 14:40:55.024 tapa.core:671] pipelined signal: P_N => FloatvMultConst_11___P_N -D0329 14:40:55.024 tapa.core:671] pipelined signal: P_N => FloatvMultConst_11___P_N -D0329 14:40:55.025 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_11___alpha_u -D0329 14:40:55.025 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_11___alpha_u -D0329 14:40:55.026 tapa.core:671] pipelined signal: M => FloatvMultConst_12___M -D0329 14:40:55.026 tapa.core:671] pipelined signal: M => FloatvMultConst_12___M -D0329 14:40:55.026 tapa.core:671] pipelined signal: P_N => FloatvMultConst_12___P_N -D0329 14:40:55.026 tapa.core:671] pipelined signal: P_N => FloatvMultConst_12___P_N -D0329 14:40:55.026 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_12___alpha_u -D0329 14:40:55.026 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_12___alpha_u -D0329 14:40:55.027 tapa.core:671] pipelined signal: M => FloatvMultConst_13___M -D0329 14:40:55.027 tapa.core:671] pipelined signal: M => FloatvMultConst_13___M -D0329 14:40:55.027 tapa.core:671] pipelined signal: P_N => FloatvMultConst_13___P_N -D0329 14:40:55.027 tapa.core:671] pipelined signal: P_N => FloatvMultConst_13___P_N -D0329 14:40:55.027 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_13___alpha_u -D0329 14:40:55.027 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_13___alpha_u -D0329 14:40:55.028 tapa.core:671] pipelined signal: M => FloatvMultConst_14___M -D0329 14:40:55.028 tapa.core:671] pipelined signal: M => FloatvMultConst_14___M -D0329 14:40:55.028 tapa.core:671] pipelined signal: P_N => FloatvMultConst_14___P_N -D0329 14:40:55.028 tapa.core:671] pipelined signal: P_N => FloatvMultConst_14___P_N -D0329 14:40:55.029 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_14___alpha_u -D0329 14:40:55.029 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_14___alpha_u -D0329 14:40:55.029 tapa.core:671] pipelined signal: M => FloatvMultConst_15___M -D0329 14:40:55.029 tapa.core:671] pipelined signal: M => FloatvMultConst_15___M -D0329 14:40:55.030 tapa.core:671] pipelined signal: P_N => FloatvMultConst_15___P_N -D0329 14:40:55.030 tapa.core:671] pipelined signal: P_N => FloatvMultConst_15___P_N -D0329 14:40:55.030 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_15___alpha_u -D0329 14:40:55.030 tapa.core:671] pipelined signal: alpha_u => FloatvMultConst_15___alpha_u -D0329 14:40:55.213 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_0___NUM_A_LEN -D0329 14:40:55.213 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_0___NUM_A_LEN -D0329 14:40:55.214 tapa.core:671] pipelined signal: P_N => read_A_0___P_N -D0329 14:40:55.214 tapa.core:671] pipelined signal: P_N => read_A_0___P_N -D0329 14:40:55.214 tapa.core:671] pipelined signal: edge_list_ch_0 => read_A_0___edge_list_ch_0 -D0329 14:40:55.214 tapa.core:671] pipelined signal: edge_list_ch_0 => read_A_0___edge_list_ch_0 -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_din` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_din` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_write` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_write` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.214 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_din` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_din` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_write` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_write` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_din` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_din` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_write` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_write` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.215 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.216 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_din` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.216 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_din` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.216 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.216 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_write` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_addr_write` is connected to async_mmap port `edge_list_ch_0.read_addr` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_0.read_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_din` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_din` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_write` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_addr_write` is connected to async_mmap port `edge_list_ch_0.write_addr` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_din` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_din` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_write` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.217 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_data_write` is connected to async_mmap port `edge_list_ch_0.write_data` -D0329 14:40:55.218 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.218 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.218 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.218 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.218 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.218 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.218 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.218 tapa.verilog.xilinx.async_mmap:81] `read_A_0.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.218 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.218 tapa.verilog.xilinx.async_mmap:71] `read_A_0.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_0.write_resp` -D0329 14:40:55.218 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_1___NUM_A_LEN -D0329 14:40:55.218 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_1___NUM_A_LEN -D0329 14:40:55.218 tapa.core:671] pipelined signal: P_N => read_A_1___P_N -D0329 14:40:55.218 tapa.core:671] pipelined signal: P_N => read_A_1___P_N -D0329 14:40:55.219 tapa.core:671] pipelined signal: edge_list_ch_1 => read_A_1___edge_list_ch_1 -D0329 14:40:55.219 tapa.core:671] pipelined signal: edge_list_ch_1 => read_A_1___edge_list_ch_1 -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_din` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_din` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_write` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_write` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_din` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_din` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_write` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.219 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_write` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_din` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_din` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_write` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_write` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.220 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.221 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_din` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.221 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_din` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.221 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.221 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.221 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_write` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.221 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_addr_write` is connected to async_mmap port `edge_list_ch_1.read_addr` -D0329 14:40:55.221 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.221 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_1.read_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_din` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_din` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_write` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_addr_write` is connected to async_mmap port `edge_list_ch_1.write_addr` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_din` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_din` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_write` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_data_write` is connected to async_mmap port `edge_list_ch_1.write_data` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.222 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.223 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.223 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.223 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.223 tapa.verilog.xilinx.async_mmap:81] `read_A_1.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.223 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.223 tapa.verilog.xilinx.async_mmap:71] `read_A_1.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_1.write_resp` -D0329 14:40:55.223 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_2___NUM_A_LEN -D0329 14:40:55.223 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_2___NUM_A_LEN -D0329 14:40:55.223 tapa.core:671] pipelined signal: P_N => read_A_2___P_N -D0329 14:40:55.223 tapa.core:671] pipelined signal: P_N => read_A_2___P_N -D0329 14:40:55.223 tapa.core:671] pipelined signal: edge_list_ch_2 => read_A_2___edge_list_ch_2 -D0329 14:40:55.223 tapa.core:671] pipelined signal: edge_list_ch_2 => read_A_2___edge_list_ch_2 -D0329 14:40:55.223 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_din` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.223 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_din` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_write` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_write` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_din` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_din` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_write` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_write` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_din` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_din` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.224 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_write` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_write` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.225 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_din` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_din` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_write` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_addr_write` is connected to async_mmap port `edge_list_ch_2.read_addr` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.226 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_2.read_data` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_din` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_din` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_write` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_addr_write` is connected to async_mmap port `edge_list_ch_2.write_addr` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_din` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_din` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_write` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_data_write` is connected to async_mmap port `edge_list_ch_2.write_data` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:81] `read_A_2.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.227 tapa.verilog.xilinx.async_mmap:71] `read_A_2.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_2.write_resp` -D0329 14:40:55.228 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_3___NUM_A_LEN -D0329 14:40:55.228 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_3___NUM_A_LEN -D0329 14:40:55.228 tapa.core:671] pipelined signal: P_N => read_A_3___P_N -D0329 14:40:55.228 tapa.core:671] pipelined signal: P_N => read_A_3___P_N -D0329 14:40:55.228 tapa.core:671] pipelined signal: edge_list_ch_3 => read_A_3___edge_list_ch_3 -D0329 14:40:55.228 tapa.core:671] pipelined signal: edge_list_ch_3 => read_A_3___edge_list_ch_3 -D0329 14:40:55.228 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_din` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.228 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_din` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.228 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.228 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.228 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_write` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.228 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_write` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_din` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_din` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_write` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_write` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_din` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_din` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_write` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_write` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.229 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.230 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.230 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.230 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.230 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.230 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.230 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_din` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_din` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_write` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_addr_write` is connected to async_mmap port `edge_list_ch_3.read_addr` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_3.read_data` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_din` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_din` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.231 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_write` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_addr_write` is connected to async_mmap port `edge_list_ch_3.write_addr` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_din` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_din` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_write` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_data_write` is connected to async_mmap port `edge_list_ch_3.write_data` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:81] `read_A_3.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.232 tapa.verilog.xilinx.async_mmap:71] `read_A_3.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_3.write_resp` -D0329 14:40:55.233 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_4___NUM_A_LEN -D0329 14:40:55.233 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_4___NUM_A_LEN -D0329 14:40:55.233 tapa.core:671] pipelined signal: P_N => read_A_4___P_N -D0329 14:40:55.233 tapa.core:671] pipelined signal: P_N => read_A_4___P_N -D0329 14:40:55.233 tapa.core:671] pipelined signal: edge_list_ch_4 => read_A_4___edge_list_ch_4 -D0329 14:40:55.233 tapa.core:671] pipelined signal: edge_list_ch_4 => read_A_4___edge_list_ch_4 -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_din` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_din` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_write` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_write` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.233 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_din` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_din` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_write` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_write` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_din` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_din` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_write` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_write` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.234 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.235 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_din` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.235 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_din` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_write` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_addr_write` is connected to async_mmap port `edge_list_ch_4.read_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_4.read_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_din` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_din` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_write` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_addr_write` is connected to async_mmap port `edge_list_ch_4.write_addr` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_din` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_din` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.236 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_write` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_data_write` is connected to async_mmap port `edge_list_ch_4.write_data` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:81] `read_A_4.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.237 tapa.verilog.xilinx.async_mmap:71] `read_A_4.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_4.write_resp` -D0329 14:40:55.237 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_5___NUM_A_LEN -D0329 14:40:55.237 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_5___NUM_A_LEN -D0329 14:40:55.237 tapa.core:671] pipelined signal: P_N => read_A_5___P_N -D0329 14:40:55.237 tapa.core:671] pipelined signal: P_N => read_A_5___P_N -D0329 14:40:55.238 tapa.core:671] pipelined signal: edge_list_ch_5 => read_A_5___edge_list_ch_5 -D0329 14:40:55.238 tapa.core:671] pipelined signal: edge_list_ch_5 => read_A_5___edge_list_ch_5 -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_din` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_din` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_write` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_write` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_din` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_din` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.238 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_write` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_write` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_din` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_din` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_write` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_write` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.239 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.240 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_din` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.240 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_din` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.240 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.240 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.240 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_write` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.240 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_addr_write` is connected to async_mmap port `edge_list_ch_5.read_addr` -D0329 14:40:55.240 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.240 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.240 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.240 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_5.read_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_din` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_din` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_write` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_addr_write` is connected to async_mmap port `edge_list_ch_5.write_addr` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_din` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_din` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_write` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_data_write` is connected to async_mmap port `edge_list_ch_5.write_data` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.241 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.242 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.242 tapa.verilog.xilinx.async_mmap:81] `read_A_5.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.242 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.242 tapa.verilog.xilinx.async_mmap:71] `read_A_5.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_5.write_resp` -D0329 14:40:55.242 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_6___NUM_A_LEN -D0329 14:40:55.242 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_6___NUM_A_LEN -D0329 14:40:55.242 tapa.core:671] pipelined signal: P_N => read_A_6___P_N -D0329 14:40:55.242 tapa.core:671] pipelined signal: P_N => read_A_6___P_N -D0329 14:40:55.242 tapa.core:671] pipelined signal: edge_list_ch_6 => read_A_6___edge_list_ch_6 -D0329 14:40:55.242 tapa.core:671] pipelined signal: edge_list_ch_6 => read_A_6___edge_list_ch_6 -D0329 14:40:55.242 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_din` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.242 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_din` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_write` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_write` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_din` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_din` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_write` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_write` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_din` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_din` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.243 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_write` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_write` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.244 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_din` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_din` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_write` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_addr_write` is connected to async_mmap port `edge_list_ch_6.read_addr` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.245 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_6.read_data` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_din` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_din` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_write` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_addr_write` is connected to async_mmap port `edge_list_ch_6.write_addr` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_din` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_din` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_write` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_data_write` is connected to async_mmap port `edge_list_ch_6.write_data` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:81] `read_A_6.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.246 tapa.verilog.xilinx.async_mmap:71] `read_A_6.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_6.write_resp` -D0329 14:40:55.247 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_7___NUM_A_LEN -D0329 14:40:55.247 tapa.core:671] pipelined signal: NUM_A_LEN => read_A_7___NUM_A_LEN -D0329 14:40:55.247 tapa.core:671] pipelined signal: P_N => read_A_7___P_N -D0329 14:40:55.247 tapa.core:671] pipelined signal: P_N => read_A_7___P_N -D0329 14:40:55.247 tapa.core:671] pipelined signal: edge_list_ch_7 => read_A_7___edge_list_ch_7 -D0329 14:40:55.247 tapa.core:671] pipelined signal: edge_list_ch_7 => read_A_7___edge_list_ch_7 -D0329 14:40:55.247 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_din` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.247 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_din` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.247 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.247 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.247 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_write` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.247 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_write` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.247 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.247 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_din` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_din` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_write` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_write` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_din` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_din` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_write` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_write` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.248 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.249 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.249 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.249 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.249 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_din` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_din` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_full_n` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_write` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_addr_write` is connected to async_mmap port `edge_list_ch_7.read_addr` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_dout` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_read_data_peek_dout` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_empty_n` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_read_data_s_read` is connected to async_mmap port `edge_list_ch_7.read_data` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_din` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.250 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_din` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_full_n` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_write` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_addr_write` is connected to async_mmap port `edge_list_ch_7.write_addr` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_din` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_din` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_full_n` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_write` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_data_write` is connected to async_mmap port `edge_list_ch_7.write_data` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_dout` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_write_resp_peek_dout` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:81] `read_A_7.A_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.251 tapa.verilog.xilinx.async_mmap:71] `read_A_7.A_write_resp_s_read` is connected to async_mmap port `edge_list_ch_7.write_resp` -D0329 14:40:55.252 tapa.core:671] pipelined signal: K => read_B_0___K -D0329 14:40:55.252 tapa.core:671] pipelined signal: K => read_B_0___K -D0329 14:40:55.252 tapa.core:671] pipelined signal: P_N => read_B_0___P_N -D0329 14:40:55.252 tapa.core:671] pipelined signal: P_N => read_B_0___P_N -D0329 14:40:55.252 tapa.core:671] pipelined signal: mat_B_ch_0 => read_B_0___mat_B_ch_0 -D0329 14:40:55.252 tapa.core:671] pipelined signal: mat_B_ch_0 => read_B_0___mat_B_ch_0 -D0329 14:40:55.252 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_din` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.252 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_din` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.252 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.252 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.252 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_write` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.252 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_write` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.252 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.252 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.252 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.252 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_din` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_din` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_write` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_write` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_din` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_din` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_write` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_write` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.253 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.254 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.254 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_din` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_din` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_write` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_addr_write` is connected to async_mmap port `mat_B_ch_0.read_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_0.read_data` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_din` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_din` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_write` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.255 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_addr_write` is connected to async_mmap port `mat_B_ch_0.write_addr` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_din` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_din` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_write` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_data_write` is connected to async_mmap port `mat_B_ch_0.write_data` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:81] `read_B_0.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.256 tapa.verilog.xilinx.async_mmap:71] `read_B_0.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_0.write_resp` -D0329 14:40:55.256 tapa.core:671] pipelined signal: K => read_B_1___K -D0329 14:40:55.256 tapa.core:671] pipelined signal: K => read_B_1___K -D0329 14:40:55.257 tapa.core:671] pipelined signal: P_N => read_B_1___P_N -D0329 14:40:55.257 tapa.core:671] pipelined signal: P_N => read_B_1___P_N -D0329 14:40:55.257 tapa.core:671] pipelined signal: mat_B_ch_1 => read_B_1___mat_B_ch_1 -D0329 14:40:55.257 tapa.core:671] pipelined signal: mat_B_ch_1 => read_B_1___mat_B_ch_1 -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_din` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_din` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_write` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_write` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.257 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_din` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_din` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_write` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_write` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_din` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_din` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_write` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_write` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.258 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.259 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_din` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.259 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_din` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_write` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_addr_write` is connected to async_mmap port `mat_B_ch_1.read_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_1.read_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_din` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_din` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_write` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_addr_write` is connected to async_mmap port `mat_B_ch_1.write_addr` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_din` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_din` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.260 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_write` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_data_write` is connected to async_mmap port `mat_B_ch_1.write_data` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:81] `read_B_1.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.261 tapa.verilog.xilinx.async_mmap:71] `read_B_1.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_1.write_resp` -D0329 14:40:55.261 tapa.core:671] pipelined signal: K => read_B_2___K -D0329 14:40:55.261 tapa.core:671] pipelined signal: K => read_B_2___K -D0329 14:40:55.261 tapa.core:671] pipelined signal: P_N => read_B_2___P_N -D0329 14:40:55.261 tapa.core:671] pipelined signal: P_N => read_B_2___P_N -D0329 14:40:55.262 tapa.core:671] pipelined signal: mat_B_ch_2 => read_B_2___mat_B_ch_2 -D0329 14:40:55.262 tapa.core:671] pipelined signal: mat_B_ch_2 => read_B_2___mat_B_ch_2 -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_din` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_din` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_write` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_write` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_din` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_din` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_write` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.262 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_write` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_din` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_din` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_write` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_write` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.263 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.264 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_din` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.264 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_din` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.264 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.264 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.264 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_write` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.264 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_addr_write` is connected to async_mmap port `mat_B_ch_2.read_addr` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_2.read_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_din` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_din` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_write` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_addr_write` is connected to async_mmap port `mat_B_ch_2.write_addr` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_din` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_din` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_write` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_data_write` is connected to async_mmap port `mat_B_ch_2.write_data` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.265 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.266 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.266 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.266 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.266 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.266 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.266 tapa.verilog.xilinx.async_mmap:81] `read_B_2.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.266 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.266 tapa.verilog.xilinx.async_mmap:71] `read_B_2.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_2.write_resp` -D0329 14:40:55.266 tapa.core:671] pipelined signal: K => read_B_3___K -D0329 14:40:55.266 tapa.core:671] pipelined signal: K => read_B_3___K -D0329 14:40:55.266 tapa.core:671] pipelined signal: P_N => read_B_3___P_N -D0329 14:40:55.266 tapa.core:671] pipelined signal: P_N => read_B_3___P_N -D0329 14:40:55.266 tapa.core:671] pipelined signal: mat_B_ch_3 => read_B_3___mat_B_ch_3 -D0329 14:40:55.266 tapa.core:671] pipelined signal: mat_B_ch_3 => read_B_3___mat_B_ch_3 -D0329 14:40:55.266 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_din` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.266 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_din` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_write` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_write` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_din` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_din` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_write` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_write` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_din` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_din` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.267 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_write` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_write` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.268 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_din` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_din` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_full_n` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_write` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_addr_write` is connected to async_mmap port `mat_B_ch_3.read_addr` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_dout` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_read_data_peek_dout` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.269 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_empty_n` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_read_data_peek_empty_n` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_read_data_s_read` is connected to async_mmap port `mat_B_ch_3.read_data` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_din` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_din` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_full_n` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_write` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_addr_write` is connected to async_mmap port `mat_B_ch_3.write_addr` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_din` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.270 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_din` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_full_n` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_write` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_data_write` is connected to async_mmap port `mat_B_ch_3.write_data` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_dout` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_write_resp_peek_dout` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_empty_n` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:81] `read_B_3.B_write_resp_peek_empty_n` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.271 tapa.verilog.xilinx.async_mmap:71] `read_B_3.B_write_resp_s_read` is connected to async_mmap port `mat_B_ch_3.write_resp` -D0329 14:40:55.271 tapa.core:671] pipelined signal: M => read_C_0___M -D0329 14:40:55.271 tapa.core:671] pipelined signal: M => read_C_0___M -D0329 14:40:55.272 tapa.core:671] pipelined signal: P_N => read_C_0___P_N -D0329 14:40:55.272 tapa.core:671] pipelined signal: P_N => read_C_0___P_N -D0329 14:40:55.272 tapa.core:671] pipelined signal: mat_C_ch_in_0 => read_C_0___mat_C_ch_in_0 -D0329 14:40:55.272 tapa.core:671] pipelined signal: mat_C_ch_in_0 => read_C_0___mat_C_ch_in_0 -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.272 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.273 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.274 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.274 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_0.read_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_0.read_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_0.write_addr` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.275 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_0.write_data` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:81] `read_C_0.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.276 tapa.verilog.xilinx.async_mmap:71] `read_C_0.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_0.write_resp` -D0329 14:40:55.276 tapa.core:671] pipelined signal: M => read_C_1___M -D0329 14:40:55.276 tapa.core:671] pipelined signal: M => read_C_1___M -D0329 14:40:55.277 tapa.core:671] pipelined signal: P_N => read_C_1___P_N -D0329 14:40:55.277 tapa.core:671] pipelined signal: P_N => read_C_1___P_N -D0329 14:40:55.277 tapa.core:671] pipelined signal: mat_C_ch_in_1 => read_C_1___mat_C_ch_in_1 -D0329 14:40:55.277 tapa.core:671] pipelined signal: mat_C_ch_in_1 => read_C_1___mat_C_ch_in_1 -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.277 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.278 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.279 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.279 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_1.read_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_1.read_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_1.write_addr` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.280 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_1.write_data` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:81] `read_C_1.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.281 tapa.verilog.xilinx.async_mmap:71] `read_C_1.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_1.write_resp` -D0329 14:40:55.281 tapa.core:671] pipelined signal: M => read_C_2___M -D0329 14:40:55.281 tapa.core:671] pipelined signal: M => read_C_2___M -D0329 14:40:55.282 tapa.core:671] pipelined signal: P_N => read_C_2___P_N -D0329 14:40:55.282 tapa.core:671] pipelined signal: P_N => read_C_2___P_N -D0329 14:40:55.282 tapa.core:671] pipelined signal: mat_C_ch_in_2 => read_C_2___mat_C_ch_in_2 -D0329 14:40:55.282 tapa.core:671] pipelined signal: mat_C_ch_in_2 => read_C_2___mat_C_ch_in_2 -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.282 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.283 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_2.read_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_2.read_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_2.write_addr` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.285 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_2.write_data` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:81] `read_C_2.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.286 tapa.verilog.xilinx.async_mmap:71] `read_C_2.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_2.write_resp` -D0329 14:40:55.286 tapa.core:671] pipelined signal: M => read_C_3___M -D0329 14:40:55.286 tapa.core:671] pipelined signal: M => read_C_3___M -D0329 14:40:55.287 tapa.core:671] pipelined signal: P_N => read_C_3___P_N -D0329 14:40:55.287 tapa.core:671] pipelined signal: P_N => read_C_3___P_N -D0329 14:40:55.287 tapa.core:671] pipelined signal: mat_C_ch_in_3 => read_C_3___mat_C_ch_in_3 -D0329 14:40:55.287 tapa.core:671] pipelined signal: mat_C_ch_in_3 => read_C_3___mat_C_ch_in_3 -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.287 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.288 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.289 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.289 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_3.read_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_3.read_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_3.write_addr` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.290 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_3.write_data` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:81] `read_C_3.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.291 tapa.verilog.xilinx.async_mmap:71] `read_C_3.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_3.write_resp` -D0329 14:40:55.291 tapa.core:671] pipelined signal: M => read_C_4___M -D0329 14:40:55.291 tapa.core:671] pipelined signal: M => read_C_4___M -D0329 14:40:55.292 tapa.core:671] pipelined signal: P_N => read_C_4___P_N -D0329 14:40:55.292 tapa.core:671] pipelined signal: P_N => read_C_4___P_N -D0329 14:40:55.292 tapa.core:671] pipelined signal: mat_C_ch_in_4 => read_C_4___mat_C_ch_in_4 -D0329 14:40:55.292 tapa.core:671] pipelined signal: mat_C_ch_in_4 => read_C_4___mat_C_ch_in_4 -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.292 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.293 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.294 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.294 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_4.read_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_4.read_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_4.write_addr` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.295 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_4.write_data` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:81] `read_C_4.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.296 tapa.verilog.xilinx.async_mmap:71] `read_C_4.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_4.write_resp` -D0329 14:40:55.296 tapa.core:671] pipelined signal: M => read_C_5___M -D0329 14:40:55.296 tapa.core:671] pipelined signal: M => read_C_5___M -D0329 14:40:55.297 tapa.core:671] pipelined signal: P_N => read_C_5___P_N -D0329 14:40:55.297 tapa.core:671] pipelined signal: P_N => read_C_5___P_N -D0329 14:40:55.297 tapa.core:671] pipelined signal: mat_C_ch_in_5 => read_C_5___mat_C_ch_in_5 -D0329 14:40:55.297 tapa.core:671] pipelined signal: mat_C_ch_in_5 => read_C_5___mat_C_ch_in_5 -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.297 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.298 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_5.read_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_5.read_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_5.write_addr` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.300 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_5.write_data` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:81] `read_C_5.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.301 tapa.verilog.xilinx.async_mmap:71] `read_C_5.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_5.write_resp` -D0329 14:40:55.301 tapa.core:671] pipelined signal: M => read_C_6___M -D0329 14:40:55.301 tapa.core:671] pipelined signal: M => read_C_6___M -D0329 14:40:55.302 tapa.core:671] pipelined signal: P_N => read_C_6___P_N -D0329 14:40:55.302 tapa.core:671] pipelined signal: P_N => read_C_6___P_N -D0329 14:40:55.302 tapa.core:671] pipelined signal: mat_C_ch_in_6 => read_C_6___mat_C_ch_in_6 -D0329 14:40:55.302 tapa.core:671] pipelined signal: mat_C_ch_in_6 => read_C_6___mat_C_ch_in_6 -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.302 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.303 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_6.read_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_6.read_data` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.305 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_6.write_addr` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_6.write_data` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:81] `read_C_6.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.306 tapa.verilog.xilinx.async_mmap:71] `read_C_6.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_6.write_resp` -D0329 14:40:55.306 tapa.core:671] pipelined signal: M => read_C_7___M -D0329 14:40:55.306 tapa.core:671] pipelined signal: M => read_C_7___M -D0329 14:40:55.307 tapa.core:671] pipelined signal: P_N => read_C_7___P_N -D0329 14:40:55.307 tapa.core:671] pipelined signal: P_N => read_C_7___P_N -D0329 14:40:55.307 tapa.core:671] pipelined signal: mat_C_ch_in_7 => read_C_7___mat_C_ch_in_7 -D0329 14:40:55.307 tapa.core:671] pipelined signal: mat_C_ch_in_7 => read_C_7___mat_C_ch_in_7 -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.307 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.308 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_din` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_full_n` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_addr_write` is connected to async_mmap port `mat_C_ch_in_7.read_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_dout` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_read_data_s_read` is connected to async_mmap port `mat_C_ch_in_7.read_data` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_din` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_full_n` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.310 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_addr_write` is connected to async_mmap port `mat_C_ch_in_7.write_addr` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_din` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_full_n` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_data_write` is connected to async_mmap port `mat_C_ch_in_7.write_data` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:81] `read_C_7.C_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.311 tapa.verilog.xilinx.async_mmap:71] `read_C_7.C_write_resp_s_read` is connected to async_mmap port `mat_C_ch_in_7.write_resp` -D0329 14:40:55.312 tapa.core:671] pipelined signal: K => read_edge_list_ptr_0___K -D0329 14:40:55.312 tapa.core:671] pipelined signal: K => read_edge_list_ptr_0___K -D0329 14:40:55.312 tapa.core:671] pipelined signal: M => read_edge_list_ptr_0___M -D0329 14:40:55.312 tapa.core:671] pipelined signal: M => read_edge_list_ptr_0___M -D0329 14:40:55.312 tapa.core:671] pipelined signal: NUM_ITE => read_edge_list_ptr_0___NUM_ITE -D0329 14:40:55.312 tapa.core:671] pipelined signal: NUM_ITE => read_edge_list_ptr_0___NUM_ITE -D0329 14:40:55.312 tapa.core:671] pipelined signal: P_N => read_edge_list_ptr_0___P_N -D0329 14:40:55.312 tapa.core:671] pipelined signal: P_N => read_edge_list_ptr_0___P_N -D0329 14:40:55.312 tapa.core:671] pipelined signal: edge_list_ptr => read_edge_list_ptr_0___edge_list_ptr -D0329 14:40:55.312 tapa.core:671] pipelined signal: edge_list_ptr => read_edge_list_ptr_0___edge_list_ptr -D0329 14:40:55.312 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_din` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.312 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_din` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.312 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_full_n` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.312 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_full_n` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.312 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_write` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.312 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_write` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_dout` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_dout` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_read_data_peek_dout` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_read_data_peek_dout` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_empty_n` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_empty_n` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_read` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_read` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_din` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_din` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_full_n` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_full_n` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_write` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_write` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_din` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_din` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_full_n` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_full_n` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_write` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.313 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_write` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.314 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_dout` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.314 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_dout` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.314 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_write_resp_peek_dout` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.314 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_write_resp_peek_dout` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.314 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.314 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.314 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.314 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.314 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_read` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.314 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_read` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.315 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_din` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.315 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_din` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.315 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_full_n` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.315 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_full_n` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.315 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_write` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.315 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_addr_write` is connected to async_mmap port `edge_list_ptr.read_addr` -D0329 14:40:55.315 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_dout` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.315 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_dout` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.315 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_read_data_peek_dout` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.315 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_read_data_peek_dout` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_empty_n` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_empty_n` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_read_data_peek_empty_n` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_read` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_read_data_s_read` is connected to async_mmap port `edge_list_ptr.read_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_din` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_din` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_full_n` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_full_n` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_write` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_addr_write` is connected to async_mmap port `edge_list_ptr.write_addr` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_din` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_din` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_full_n` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_full_n` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_write` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_data_write` is connected to async_mmap port `edge_list_ptr.write_data` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_dout` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_dout` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_write_resp_peek_dout` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.316 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_write_resp_peek_dout` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_empty_n` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:81] `read_edge_list_ptr_0.edge_list_ptr_write_resp_peek_empty_n` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_read` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:71] `read_edge_list_ptr_0.edge_list_ptr_write_resp_s_read` is connected to async_mmap port `edge_list_ptr.write_resp` -D0329 14:40:55.317 tapa.core:671] pipelined signal: mat_C_ch_0 => write_C_0___mat_C_ch_0 -D0329 14:40:55.317 tapa.core:671] pipelined signal: mat_C_ch_0 => write_C_0___mat_C_ch_0 -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.317 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.318 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.319 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.319 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.319 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.319 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.319 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.319 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.319 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.319 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.320 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.320 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.320 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.320 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.320 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.320 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_0.read_addr` -D0329 14:40:55.320 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.320 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.320 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.320 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_0.read_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_0.write_addr` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_0.write_data` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.321 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.322 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.322 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.322 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.322 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.322 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.322 tapa.verilog.xilinx.async_mmap:81] `write_C_0.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.322 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.322 tapa.verilog.xilinx.async_mmap:71] `write_C_0.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_0.write_resp` -D0329 14:40:55.322 tapa.core:671] pipelined signal: mat_C_ch_1 => write_C_1___mat_C_ch_1 -D0329 14:40:55.322 tapa.core:671] pipelined signal: mat_C_ch_1 => write_C_1___mat_C_ch_1 -D0329 14:40:55.322 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.322 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.323 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.324 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.325 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.325 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.325 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.325 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_1.read_addr` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_1.read_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_1.write_addr` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.326 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_1.write_data` -D0329 14:40:55.327 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.327 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.327 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.327 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.327 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.327 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.327 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.327 tapa.verilog.xilinx.async_mmap:81] `write_C_1.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.327 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.327 tapa.verilog.xilinx.async_mmap:71] `write_C_1.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_1.write_resp` -D0329 14:40:55.327 tapa.core:671] pipelined signal: mat_C_ch_2 => write_C_2___mat_C_ch_2 -D0329 14:40:55.327 tapa.core:671] pipelined signal: mat_C_ch_2 => write_C_2___mat_C_ch_2 -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.328 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.329 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.330 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.330 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_2.read_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_2.read_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_2.write_addr` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.331 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_2.write_data` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:81] `write_C_2.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.332 tapa.verilog.xilinx.async_mmap:71] `write_C_2.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_2.write_resp` -D0329 14:40:55.333 tapa.core:671] pipelined signal: mat_C_ch_3 => write_C_3___mat_C_ch_3 -D0329 14:40:55.333 tapa.core:671] pipelined signal: mat_C_ch_3 => write_C_3___mat_C_ch_3 -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.333 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.334 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_3.read_addr` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_3.read_data` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.336 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_3.write_addr` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_3.write_data` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:81] `write_C_3.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.337 tapa.verilog.xilinx.async_mmap:71] `write_C_3.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_3.write_resp` -D0329 14:40:55.338 tapa.core:671] pipelined signal: mat_C_ch_4 => write_C_4___mat_C_ch_4 -D0329 14:40:55.338 tapa.core:671] pipelined signal: mat_C_ch_4 => write_C_4___mat_C_ch_4 -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.338 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.339 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.340 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.340 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_4.read_addr` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.341 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_4.read_data` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_4.write_addr` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_4.write_data` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:81] `write_C_4.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.342 tapa.verilog.xilinx.async_mmap:71] `write_C_4.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_4.write_resp` -D0329 14:40:55.343 tapa.core:671] pipelined signal: mat_C_ch_5 => write_C_5___mat_C_ch_5 -D0329 14:40:55.343 tapa.core:671] pipelined signal: mat_C_ch_5 => write_C_5___mat_C_ch_5 -D0329 14:40:55.343 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.343 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.343 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.343 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.343 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.343 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.343 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.343 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.343 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.343 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.344 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.345 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.345 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.345 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.345 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.345 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.345 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.346 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.346 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.346 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.346 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.346 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.346 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_5.read_addr` -D0329 14:40:55.346 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.346 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.346 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.346 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_5.read_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_5.write_addr` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_5.write_data` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.347 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.348 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.348 tapa.verilog.xilinx.async_mmap:81] `write_C_5.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.348 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.348 tapa.verilog.xilinx.async_mmap:71] `write_C_5.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_5.write_resp` -D0329 14:40:55.348 tapa.core:671] pipelined signal: mat_C_ch_6 => write_C_6___mat_C_ch_6 -D0329 14:40:55.348 tapa.core:671] pipelined signal: mat_C_ch_6 => write_C_6___mat_C_ch_6 -D0329 14:40:55.348 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.348 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.348 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.348 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.348 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.348 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.349 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.350 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.350 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.350 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.350 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.350 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.350 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.350 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.350 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.351 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.351 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.351 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.351 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.351 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.351 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_6.read_addr` -D0329 14:40:55.351 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.351 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_6.read_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_6.write_addr` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_6.write_data` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.352 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.353 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.353 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.353 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.353 tapa.verilog.xilinx.async_mmap:81] `write_C_6.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.353 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.353 tapa.verilog.xilinx.async_mmap:71] `write_C_6.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_6.write_resp` -D0329 14:40:55.353 tapa.core:671] pipelined signal: mat_C_ch_7 => write_C_7___mat_C_ch_7 -D0329 14:40:55.353 tapa.core:671] pipelined signal: mat_C_ch_7 => write_C_7___mat_C_ch_7 -D0329 14:40:55.353 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.353 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.354 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.355 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.356 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.356 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_din` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.356 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.356 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_full_n` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_addr_write` is connected to async_mmap port `mat_C_ch_7.read_addr` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_dout` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_read_data_peek_dout` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_empty_n` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_read_data_peek_empty_n` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_read_data_s_read` is connected to async_mmap port `mat_C_ch_7.read_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_din` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_full_n` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_addr_write` is connected to async_mmap port `mat_C_ch_7.write_addr` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_din` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_full_n` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.357 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_data_write` is connected to async_mmap port `mat_C_ch_7.write_data` -D0329 14:40:55.358 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.358 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_dout` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.358 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.358 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_write_resp_peek_dout` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.358 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.358 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_empty_n` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.358 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.358 tapa.verilog.xilinx.async_mmap:81] `write_C_7.C_out_write_resp_peek_empty_n` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.358 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.358 tapa.verilog.xilinx.async_mmap:71] `write_C_7.C_out_write_resp_s_read` is connected to async_mmap port `mat_C_ch_7.write_resp` -D0329 14:40:55.358 tapa.core:852] Set the address width of async_mmap to 64 -D0329 14:40:55.358 tapa.core:852] Set the address width of async_mmap to 64 -I0329 14:40:56.045 tapa.core:465] generating report -I0329 14:40:56.045 tapa.core:465] generating report -I0329 14:40:56.055 tapa.core:473] writing generated auxiliary RTL files -I0329 14:40:56.055 tapa.core:473] writing generated auxiliary RTL files -I0329 14:40:56.056 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0329 14:40:56.056 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0329 14:40:56.056 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0329 14:40:56.056 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0329 14:40:56.056 tapa.core:481] packaging RTL code -I0329 14:40:56.056 tapa.core:481] packaging RTL code -D0329 14:40:56.056 tapa.verilog.xilinx:70] RTL ports of Sextans: -D0329 14:40:56.056 tapa.verilog.xilinx:70] RTL ports of Sextans: -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ptr, ctype: int*, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ptr, ctype: int*, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_0, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_0, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_1, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_1, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_2, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_2, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_3, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_3, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_4, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_4, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_5, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.056 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_5, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_6, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_6, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_7, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: edge_list_ch_7, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_B_ch_0, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_B_ch_0, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_B_ch_1, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_B_ch_1, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_B_ch_2, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_B_ch_2, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_B_ch_3, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_B_ch_3, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_0, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_0, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_1, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_1, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_2, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_2, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_3, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_3, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_4, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_4, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_5, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_5, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_6, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_6, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_7, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_in_7, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_0, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_0, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_1, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_1, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_2, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_2, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_3, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_3, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_4, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.057 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_4, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_5, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_5, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_6, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_6, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_7, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: mat_C_ch_7, ctype: float_v16*, width: 512, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: NUM_ITE, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: NUM_ITE, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: NUM_A_LEN, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: NUM_A_LEN, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: M, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: M, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: K, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: K, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: P_N, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: P_N, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: alpha_u, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: alpha_u, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: beta_u, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.058 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: beta_u, ctype: const int, width: 32, chan_count: None, chan_size: None -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: FloatvMultConst.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: FloatvMultConst.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: read_B_mul_14ns_29s_32_2_1.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: read_B_mul_14ns_29s_32_2_1.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: read_C_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: read_C_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: axi_crossbar.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: axi_crossbar.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: read_A_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: read_A_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: Scatter_1_2_Scatter_1_2_Pipeline_VITIS_LOOP_405_1.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: Scatter_1_2_Scatter_1_2_Pipeline_VITIS_LOOP_405_1.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: black_hole_float_v16.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: black_hole_float_v16.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: Scatter_1_2.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: Scatter_1_2.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: black_hole_int.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: black_hole_int.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: read_B_read_B_Pipeline_rd_B.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: read_B_read_B_Pipeline_rd_B.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: async_mmap.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: async_mmap.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: PEG_Cmtx.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: PEG_Cmtx.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: axi_pipeline.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: axi_pipeline.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: PEG_Cmtx_local_C_V_RAM_2P_URAM_1R1W.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: fifo_srl.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: fifo_srl.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: axi_register_rd.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: axi_register_rd.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: Merger_Merger_Pipeline_VITIS_LOOP_410_1.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: Merger_Merger_Pipeline_VITIS_LOOP_410_1.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: detect_burst.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: detect_burst.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip.tcl -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1_ip.tcl -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: read_C_mul_mul_14ns_28s_32_4_1.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: read_C_mul_mul_14ns_28s_32_4_1.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: axi_crossbar_rd.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: axi_crossbar_rd.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: FloatvAddFloatv_FloatvAddFloatv_Pipeline_cc.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: FloatvAddFloatv_FloatvAddFloatv_Pipeline_cc.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: relay_station.v -D0329 14:40:56.059 haoda.backend.xilinx:163] packing: relay_station.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: black_hole_int_black_hole_int_Pipeline_VITIS_LOOP_399_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: black_hole_int_black_hole_int_Pipeline_VITIS_LOOP_399_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: generate_last.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: generate_last.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_3.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_3.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx_PEG_Bmtx_Pipeline_computation.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx_PEG_Bmtx_Pipeline_computation.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: read_edge_list_ptr_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: read_edge_list_ptr_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: FloatvMultConst_mul_32s_14ns_32_2_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: FloatvMultConst_mul_32s_14ns_32_2_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx_fmul_32ns_32ns_32_4_max_dsp_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: Sextans_fsm.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: Sextans_fsm.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip.tcl -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: FloatvAddFloatv_fadd_32ns_32ns_32_7_full_dsp_1_ip.tcl -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: FloatvMultConst_FloatvMultConst_Pipeline_cc.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: FloatvMultConst_FloatvMultConst_Pipeline_cc.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: Merger.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: Merger.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_mux_42_64_1_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_mux_42_64_1_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: FloatvMultConst_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: FloatvMultConst_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: read_A_read_A_Pipeline_rd_A.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: read_A_read_A_Pipeline_rd_A.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_mul_mul_16s_14ns_30_4_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_mul_mul_16s_14ns_30_4_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: read_B_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: read_B_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: write_C.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: write_C.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: fifo_bram.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: fifo_bram.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: read_edge_list_ptr_mul_mul_16s_14ns_30_4_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: read_edge_list_ptr_mul_mul_16s_14ns_30_4_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: write_C_mul_mul_14ns_28s_32_4_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: write_C_mul_mul_14ns_28s_32_4_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: priority_encoder.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: priority_encoder.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: black_hole_float_v16_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: black_hole_float_v16_black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: arbiter.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: arbiter.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_PEG_Cmtx_Pipeline_init_C.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_PEG_Cmtx_Pipeline_init_C.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: write_C_write_C_Pipeline_wr_C.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: write_C_write_C_Pipeline_wr_C.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_PEG_Cmtx_Pipeline_write_C_outer.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Cmtx_PEG_Cmtx_Pipeline_write_C_outer.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: axi_register_wr.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: axi_register_wr.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: read_C_read_C_Pipeline_rd_C.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: read_C_read_C_Pipeline_rd_C.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx_PEG_Bmtx_Pipeline_read_B.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx_PEG_Bmtx_Pipeline_read_B.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx_mul_mul_16s_14ns_30_4_1.v -D0329 14:40:56.060 haoda.backend.xilinx:163] packing: PEG_Bmtx_mul_mul_16s_14ns_30_4_1.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: axi_crossbar_wr.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: axi_crossbar_wr.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_A_mul_mul_16s_14ns_30_4_1.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_A_mul_mul_16s_14ns_30_4_1.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: Sextans.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: Sextans.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: PEG_Bmtx_local_B_RAM_AUTO_1R1W.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: PEG_Bmtx_local_B_RAM_AUTO_1R1W.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: write_C_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: write_C_flow_control_loop_pipe_sequential_init.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_4.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_4.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_edge_list_ptr.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_edge_list_ptr.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: PEG_Bmtx_mux_42_32_1_1.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: PEG_Bmtx_mux_42_32_1_1.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip.tcl -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: FloatvMultConst_fmul_32ns_32ns_32_4_max_dsp_1_ip.tcl -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_A.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_A.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_edge_list_ptr_read_edge_list_ptr_Pipeline_rd_ptr.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_edge_list_ptr_read_edge_list_ptr_Pipeline_rd_ptr.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_C.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_C.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: FloatvMultConst_mul_mul_16s_28s_32_4_1.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: FloatvMultConst_mul_mul_16s_28s_32_4_1.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_B.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: read_B.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: FloatvAddFloatv.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: FloatvAddFloatv.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: Sextans_control_s_axi.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: Sextans_control_s_axi.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: PEG_Cmtx_PEG_Cmtx_Pipeline_computation.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: PEG_Cmtx_PEG_Cmtx_Pipeline_computation.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip.tcl -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: PEG_Cmtx_fadd_32ns_32ns_32_7_full_dsp_1_ip.tcl -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: fifo_fwd.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: fifo_fwd.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: fifo.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: fifo.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: axi_crossbar_addr.v -D0329 14:40:56.061 haoda.backend.xilinx:163] packing: axi_crossbar_addr.v -I0329 14:41:30.936 tapa.core:489] packaging HLS report -I0329 14:41:30.936 tapa.core:489] packaging HLS report -D0329 14:41:30.939 tapa.core:494] packing report/PEG_Cmtx_Pipeline_computation_csynth.xml -D0329 14:41:30.939 tapa.core:494] packing report/PEG_Cmtx_Pipeline_computation_csynth.xml -D0329 14:41:30.940 tapa.core:494] packing report/Merger_Pipeline_VITIS_LOOP_410_1_csynth.xml -D0329 14:41:30.940 tapa.core:494] packing report/Merger_Pipeline_VITIS_LOOP_410_1_csynth.xml -D0329 14:41:30.940 tapa.core:494] packing report/read_B_csynth.xml -D0329 14:41:30.940 tapa.core:494] packing report/read_B_csynth.xml -D0329 14:41:30.941 tapa.core:494] packing report/read_C_csynth.xml -D0329 14:41:30.941 tapa.core:494] packing report/read_C_csynth.xml -D0329 14:41:30.941 tapa.core:494] packing report/write_C_csynth.xml -D0329 14:41:30.941 tapa.core:494] packing report/write_C_csynth.xml -D0329 14:41:30.942 tapa.core:494] packing report/read_B_Pipeline_rd_B_csynth.xml -D0329 14:41:30.942 tapa.core:494] packing report/read_B_Pipeline_rd_B_csynth.xml -D0329 14:41:30.943 tapa.core:494] packing report/read_edge_list_ptr_Pipeline_rd_ptr_csynth.xml -D0329 14:41:30.943 tapa.core:494] packing report/read_edge_list_ptr_Pipeline_rd_ptr_csynth.xml -D0329 14:41:30.943 tapa.core:494] packing report/read_A_csynth.xml -D0329 14:41:30.943 tapa.core:494] packing report/read_A_csynth.xml -D0329 14:41:30.944 tapa.core:494] packing report/read_edge_list_ptr_csynth.xml -D0329 14:41:30.944 tapa.core:494] packing report/read_edge_list_ptr_csynth.xml -D0329 14:41:30.944 tapa.core:494] packing report/FloatvAddFloatv_Pipeline_cc_csynth.xml -D0329 14:41:30.944 tapa.core:494] packing report/FloatvAddFloatv_Pipeline_cc_csynth.xml -D0329 14:41:30.945 tapa.core:494] packing report/black_hole_int_Pipeline_VITIS_LOOP_399_1_csynth.xml -D0329 14:41:30.945 tapa.core:494] packing report/black_hole_int_Pipeline_VITIS_LOOP_399_1_csynth.xml -D0329 14:41:30.945 tapa.core:494] packing report/black_hole_float_v16_csynth.xml -D0329 14:41:30.945 tapa.core:494] packing report/black_hole_float_v16_csynth.xml -D0329 14:41:30.946 tapa.core:494] packing report/FloatvMultConst_csynth.xml -D0329 14:41:30.946 tapa.core:494] packing report/FloatvMultConst_csynth.xml -D0329 14:41:30.946 tapa.core:494] packing report/FloatvAddFloatv_csynth.xml -D0329 14:41:30.946 tapa.core:494] packing report/FloatvAddFloatv_csynth.xml -D0329 14:41:30.946 tapa.core:494] packing report/PEG_Bmtx_Pipeline_read_B_csynth.xml -D0329 14:41:30.946 tapa.core:494] packing report/PEG_Bmtx_Pipeline_read_B_csynth.xml -D0329 14:41:30.949 tapa.core:494] packing report/Scatter_1_2_Pipeline_VITIS_LOOP_405_1_csynth.xml -D0329 14:41:30.949 tapa.core:494] packing report/Scatter_1_2_Pipeline_VITIS_LOOP_405_1_csynth.xml -D0329 14:41:30.950 tapa.core:494] packing report/PEG_Bmtx_Pipeline_computation_csynth.xml -D0329 14:41:30.950 tapa.core:494] packing report/PEG_Bmtx_Pipeline_computation_csynth.xml -D0329 14:41:30.952 tapa.core:494] packing report/PEG_Bmtx_csynth.xml -D0329 14:41:30.952 tapa.core:494] packing report/PEG_Bmtx_csynth.xml -D0329 14:41:30.953 tapa.core:494] packing report/read_C_Pipeline_rd_C_csynth.xml -D0329 14:41:30.953 tapa.core:494] packing report/read_C_Pipeline_rd_C_csynth.xml -D0329 14:41:30.954 tapa.core:494] packing report/FloatvMultConst_Pipeline_cc_csynth.xml -D0329 14:41:30.954 tapa.core:494] packing report/FloatvMultConst_Pipeline_cc_csynth.xml -D0329 14:41:30.954 tapa.core:494] packing report/read_A_Pipeline_rd_A_csynth.xml -D0329 14:41:30.954 tapa.core:494] packing report/read_A_Pipeline_rd_A_csynth.xml -D0329 14:41:30.955 tapa.core:494] packing report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_csynth.xml -D0329 14:41:30.955 tapa.core:494] packing report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_csynth.xml -D0329 14:41:30.955 tapa.core:494] packing report/black_hole_int_csynth.xml -D0329 14:41:30.955 tapa.core:494] packing report/black_hole_int_csynth.xml -D0329 14:41:30.955 tapa.core:494] packing report/Sextans_csynth.xml -D0329 14:41:30.955 tapa.core:494] packing report/Sextans_csynth.xml -D0329 14:41:30.956 tapa.core:494] packing report/write_C_Pipeline_wr_C_csynth.xml -D0329 14:41:30.956 tapa.core:494] packing report/write_C_Pipeline_wr_C_csynth.xml -D0329 14:41:30.956 tapa.core:494] packing report/Scatter_1_2_csynth.xml -D0329 14:41:30.956 tapa.core:494] packing report/Scatter_1_2_csynth.xml -D0329 14:41:30.957 tapa.core:494] packing report/Merger_csynth.xml -D0329 14:41:30.957 tapa.core:494] packing report/Merger_csynth.xml -D0329 14:41:30.957 tapa.core:494] packing report/PEG_Cmtx_Pipeline_init_C_csynth.xml -D0329 14:41:30.957 tapa.core:494] packing report/PEG_Cmtx_Pipeline_init_C_csynth.xml -D0329 14:41:30.958 tapa.core:494] packing report/PEG_Cmtx_Pipeline_write_C_outer_csynth.xml -D0329 14:41:30.958 tapa.core:494] packing report/PEG_Cmtx_Pipeline_write_C_outer_csynth.xml -D0329 14:41:30.959 tapa.core:494] packing report/PEG_Cmtx_csynth.xml -D0329 14:41:30.959 tapa.core:494] packing report/PEG_Cmtx_csynth.xml -I0329 14:41:30.960 tapa.core:497] generated the v++ xo file at generated/Sextans.xo -I0329 14:41:30.960 tapa.core:497] generated the v++ xo file at generated/Sextans.xo diff --git a/benchmarks/tapa_flow/sextans/design/generated/report.json b/benchmarks/tapa_flow/sextans/design/generated/report.json deleted file mode 100644 index 247190dc..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report.json +++ /dev/null @@ -1,195 +0,0 @@ -{ - "area": { - "breakdown": { - "FloatvAddFloatv": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 32, - "FF": 6704, - "LUT": 3644, - "URAM": 0 - } - }, - "count": 8 - }, - "FloatvMultConst": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 51, - "FF": 3704, - "LUT": 1602, - "URAM": 0 - } - }, - "count": 16 - }, - "Merger": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 0, - "FF": 6, - "LUT": 69, - "URAM": 0 - } - }, - "count": 8 - }, - "PEG_Bmtx": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 128, - "DSP": 97, - "FF": 8088, - "LUT": 9745, - "URAM": 0 - } - }, - "count": 16 - }, - "PEG_Cmtx": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 65, - "FF": 17721, - "LUT": 11573, - "URAM": 32 - } - }, - "count": 16 - }, - "Scatter_1_2": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 0, - "FF": 6, - "LUT": 67, - "URAM": 0 - } - }, - "count": 8 - }, - "black_hole_float_v16": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 0, - "FF": 6, - "LUT": 43, - "URAM": 0 - } - }, - "count": 4 - }, - "black_hole_int": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 0, - "FF": 6, - "LUT": 43, - "URAM": 0 - } - }, - "count": 2 - }, - "read_A": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 1, - "FF": 132, - "LUT": 346, - "URAM": 0 - } - }, - "count": 8 - }, - "read_B": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 2, - "FF": 348, - "LUT": 403, - "URAM": 0 - } - }, - "count": 4 - }, - "read_C": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 1, - "FF": 153, - "LUT": 391, - "URAM": 0 - } - }, - "count": 8 - }, - "read_edge_list_ptr": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 1, - "FF": 164, - "LUT": 422, - "URAM": 0 - } - }, - "count": 1 - }, - "write_C": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 1, - "FF": 197, - "LUT": 448, - "URAM": 0 - } - }, - "count": 8 - } - }, - "source": "hls", - "total": { - "BRAM_18K": 2048, - "DSP": 3697, - "FF": 533716, - "LUT": 412932, - "URAM": 512 - } - }, - "name": "Sextans", - "performance": { - "clock_period": "3.656", - "critical_path": { - "PEG_Bmtx": { - "clock_period": "3.656", - "source": "hls" - } - }, - "source": "hls" - }, - "schema": "v0.0.20210922" -} diff --git a/benchmarks/tapa_flow/sextans/design/generated/report.yaml b/benchmarks/tapa_flow/sextans/design/generated/report.yaml deleted file mode 100644 index b5eb9b89..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report.yaml +++ /dev/null @@ -1,148 +0,0 @@ -schema: v0.0.20210922 -name: Sextans -performance: - source: hls - clock_period: '3.656' - critical_path: - PEG_Bmtx: - source: hls - clock_period: '3.656' -area: - source: hls - total: - BRAM_18K: 2048 - DSP: 3697 - FF: 533716 - LUT: 412932 - URAM: 512 - breakdown: - FloatvAddFloatv: - count: 8 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 32 - FF: 6704 - LUT: 3644 - URAM: 0 - FloatvMultConst: - count: 16 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 51 - FF: 3704 - LUT: 1602 - URAM: 0 - Merger: - count: 8 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 0 - FF: 6 - LUT: 69 - URAM: 0 - PEG_Bmtx: - count: 16 - area: - source: hls - total: - BRAM_18K: 128 - DSP: 97 - FF: 8088 - LUT: 9745 - URAM: 0 - PEG_Cmtx: - count: 16 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 65 - FF: 17721 - LUT: 11573 - URAM: 32 - Scatter_1_2: - count: 8 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 0 - FF: 6 - LUT: 67 - URAM: 0 - black_hole_float_v16: - count: 4 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 0 - FF: 6 - LUT: 43 - URAM: 0 - black_hole_int: - count: 2 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 0 - FF: 6 - LUT: 43 - URAM: 0 - read_A: - count: 8 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 1 - FF: 132 - LUT: 346 - URAM: 0 - read_B: - count: 4 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 2 - FF: 348 - LUT: 403 - URAM: 0 - read_C: - count: 8 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 1 - FF: 153 - LUT: 391 - URAM: 0 - read_edge_list_ptr: - count: 1 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 1 - FF: 164 - LUT: 422 - URAM: 0 - write_C: - count: 8 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 1 - FF: 197 - LUT: 448 - URAM: 0 diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv.sched.adb.xml deleted file mode 100644 index 8a7fe77b..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv.sched.adb.xml +++ /dev/null @@ -1,342 +0,0 @@ -FloatvAddFloatv - - - - - - - - - - - - - - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv.verbose.sched.rpt.xml deleted file mode 100644 index e2821f48..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv.verbose.sched.rpt.xml +++ /dev/null @@ -1,45 +0,0 @@ - - -

    -Fri Mar 29 14:40:35 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -FloatvAddFloatv (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.342 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -?, ?, ?, ?, ?, ?, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -
    -     -
    -     -
    -     -
    - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv_Pipeline_cc.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv_Pipeline_cc.sched.adb.xml deleted file mode 100644 index 4bf2cc9c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv_Pipeline_cc.sched.adb.xml +++ /dev/null @@ -1,4126 +0,0 @@ -FloatvAddFloatv_Pipeline_cc - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -LogicGate - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - - - - -NULL - - - - - - - -, void %if.then - -]]> - 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- -
    -Fri Mar 29 14:40:34 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -FloatvAddFloatv (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.342 ns, 0.90 ns -
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    -     - -
    - -, min, max, min, max, min, max, Type -?, ?, ?, ?, ?, ?, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -?, ?, 9, 1, 1, inf, yes -
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    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv_Pipeline_cc_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv_Pipeline_cc_csynth.xml deleted file mode 100644 index 7d117412..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvAddFloatv_Pipeline_cc_csynth.xml +++ /dev/null @@ -1,233 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -FloatvAddFloatv_Pipeline_cc -3.33 -0.90 -vivado - - - -no - -ns -2.342 - - -clock cycles -undef -undef -undef -undef -undef -undef -undef -undef - - - -2.43 -inf -undef -undef -1 -9 - - - - - - - - -32 -6700 -3597 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -FloatvAddFloatv_Pipeline_cc -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -FloatvAddFloatv_Pipeline_cc -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -FloatvAddFloatv_Pipeline_cc -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -FloatvAddFloatv_Pipeline_cc -return value - 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    -Fri Mar 29 14:40:35 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -FloatvMultConst (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
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    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.461 ns, 0.90 ns -
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- - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvMultConst_Pipeline_cc.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/FloatvMultConst_Pipeline_cc.verbose.sched.rpt.xml deleted file mode 100644 index f9c9f695..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvMultConst_Pipeline_cc.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
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    - -
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    -     - -
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    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvMultConst_Pipeline_cc_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/FloatvMultConst_Pipeline_cc_csynth.xml deleted file mode 100644 index 4d37080d..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/FloatvMultConst_Pipeline_cc_csynth.xml +++ /dev/null @@ -1,222 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -FloatvMultConst_Pipeline_cc -3.33 -0.90 -vivado - - - -no - -ns -2.322 - - -clock cycles -undef -undef -undef -undef -undef -undef -undef -undef - - - -2.43 -undef -undef -undef -1 -6 - - - - - - - - -48 -3420 -1394 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -FloatvMultConst_Pipeline_cc -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -FloatvMultConst_Pipeline_cc -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -FloatvMultConst_Pipeline_cc -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -FloatvMultConst_Pipeline_cc -return value - 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    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
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    -Fri Mar 29 14:40:35 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -Merger (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
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    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/Merger_Pipeline_VITIS_LOOP_410_1_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/Merger_Pipeline_VITIS_LOOP_410_1_csynth.xml deleted file mode 100644 index 6ef8f2ad..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/Merger_Pipeline_VITIS_LOOP_410_1_csynth.xml +++ /dev/null @@ -1,233 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -Merger_Pipeline_VITIS_LOOP_410_1 -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -undef -undef -undef -undef -undef -undef -undef -undef - - - -2.43 -inf -undef -undef -1 -1 - - - - - - - - -2 -22 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -Merger_Pipeline_VITIS_LOOP_410_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -Merger_Pipeline_VITIS_LOOP_410_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -Merger_Pipeline_VITIS_LOOP_410_1 -return value - -ap_ctrl_hs - -in -1 -control - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -Cmp - - - - - - - - - - - -Sel - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -DSP48 - - - - - - - - - - - - - - -DSP48 - - - - - - - - - - - - - - -DSP48 - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -DSP48 - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -Adder - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx.verbose.sched.rpt.xml deleted file mode 100644 index b7c0cb90..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx.verbose.sched.rpt.xml +++ /dev/null @@ -1,47 +0,0 @@ - - -
    -Fri Mar 29 14:40:43 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -PEG_Bmtx (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 3.656 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -28, 570807, 0.102 us, 2.087 ms, 29, 570808, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -21, 570800, 21 ~ 35675, -, -, 1 ~ 16, no -18, 35672, 18 ~ 728, -, -, 1 ~ 49, no -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx_Pipeline_computation.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx_Pipeline_computation.sched.adb.xml deleted file mode 100644 index f84f695d..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx_Pipeline_computation.sched.adb.xml +++ /dev/null @@ -1,10765 +0,0 @@ -PEG_Bmtx_Pipeline_computation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -RAM - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - 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- - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -RAM - 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- - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -Sel - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -Sel - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -Sel - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx_Pipeline_computation.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx_Pipeline_computation.verbose.sched.rpt.xml deleted file mode 100644 index 6f2323c1..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx_Pipeline_computation.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:40 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -PEG_Bmtx (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.355 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -9, 208, 29.970 ns, 0.693 us, 9, 208, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -7, 206, 8, 1, 1, 1 ~ 200, yes -
    -     -
    -     -
    -     -
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- - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Cmp - - - - - - - - - - - -LogicGate - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - 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-NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -RAM - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx_Pipeline_read_B.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx_Pipeline_read_B.verbose.sched.rpt.xml deleted file mode 100644 index 061bfb87..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Bmtx_Pipeline_read_B.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:39 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -PEG_Bmtx (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
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    - -, min, max, min, max, min, max, Type -3, 514, 9.990 ns, 1.712 us, 3, 514, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -1, 512, 1, 1, 1, 1 ~ 512, yes -
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-NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -DSP48 - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Cmtx.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Cmtx.verbose.sched.rpt.xml deleted file mode 100644 index 10f01209..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Cmtx.verbose.sched.rpt.xml +++ /dev/null @@ -1,47 +0,0 @@ - - -
    -Fri Mar 29 14:40:39 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -PEG_Cmtx (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.583 ns, 0.90 ns -
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    - -, min, max, min, max, min, max, Type -33, 209527, 0.110 us, 0.698 ms, 34, 209528, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -26, 209520, 26 ~ 13095, -, -, 1 ~ 16, no -15, 10486, 15 ~ 214, -, -, 1 ~ 49, no -
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    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Cmtx_Pipeline_computation.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Cmtx_Pipeline_computation.sched.adb.xml deleted file mode 100644 index fbae5d5c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/PEG_Cmtx_Pipeline_computation.sched.adb.xml +++ /dev/null @@ -1,9157 +0,0 @@ -PEG_Cmtx_Pipeline_computation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - 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    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.342 ns, 0.90 ns -
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- -
    -Fri Mar 29 14:40:37 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -PEG_Cmtx (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 1.722 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -3, 802, 9.990 ns, 2.671 us, 3, 802, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -1, 800, 2, 1, 1, 1 ~ 800, yes -
    -     -
    -     -
    -     -
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    -Fri Mar 29 14:40:39 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -PEG_Cmtx (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.175 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -4, 1803, 13.320 ns, 6.004 us, 4, 1803, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -2, 1801, 3, 1, 1, 1 ~ 1800, yes -
    -     -
    -     -
    -     -
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- - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/Sextans.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/Sextans.verbose.sched.rpt.xml deleted file mode 100644 index 25fd1ed2..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/Sextans.verbose.sched.rpt.xml +++ /dev/null @@ -1,45 +0,0 @@ - - -
    -Fri Mar 29 14:40:34 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -Sextans (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 1.000 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -0, 0, 0 ns, 0 ns, 1, 1, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/Sextans_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/Sextans_csynth.xml deleted file mode 100644 index 16f68b46..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/Sextans_csynth.xml +++ /dev/null @@ -1,276 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -Sextans -3.33 -0.90 -vivado - - - -no - -ns -1.000 - - -clock cycles -0 -0 -0 -0 ns -0 ns -0 ns -1 -1 - - - - - -0 -2332 -4200 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -s_axi_control_AWVALID -control -scalar -s_axi -in -1 -unknown -int -1 - - -s_axi_control_AWREADY -control -scalar -s_axi -out -1 -unknown -int -1 - - -s_axi_control_AWADDR -control -scalar -s_axi -in -9 -unknown -int -1 - - -s_axi_control_WVALID -control -scalar -s_axi -in -1 -unknown -int -1 - - -s_axi_control_WREADY -control -scalar -s_axi -out -1 -unknown -int -1 - - -s_axi_control_WDATA -control -scalar -s_axi -in -32 -unknown -int -1 - - -s_axi_control_WSTRB -control -scalar -s_axi -in -4 -unknown -int -1 - - -s_axi_control_ARVALID -control -scalar -s_axi -in -1 -unknown -int -1 - - -s_axi_control_ARREADY -control -scalar -s_axi -out -1 -unknown -int -1 - - -s_axi_control_ARADDR -control -scalar -s_axi -in -9 -unknown -int -1 - - -s_axi_control_RVALID -control -scalar -s_axi -out -1 -unknown -int -1 - - -s_axi_control_RREADY -control -scalar -s_axi -in -1 -unknown -int -1 - - -s_axi_control_RDATA -control -scalar -s_axi -out -32 -unknown -int -1 - - -s_axi_control_RRESP -control -scalar -s_axi -out -2 -unknown -int -1 - - -s_axi_control_BVALID -control -scalar -s_axi -out -1 -unknown -int -1 - - -s_axi_control_BREADY -control -scalar -s_axi -in -1 -unknown -int -1 - - -s_axi_control_BRESP -control -scalar -s_axi -out -2 -unknown -int -1 - - -ap_clk -Sextans -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst_n -Sextans -return value - -ap_ctrl_hs - -in -1 -control - - -interrupt -Sextans -return value - -ap_ctrl_hs - -out -1 -unknown - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16.sched.adb.xml deleted file mode 100644 index a67b562a..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16.sched.adb.xml +++ /dev/null @@ -1,207 +0,0 @@ -black_hole_float_v16 - - - - - - - - - - - - - - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16.verbose.sched.rpt.xml deleted file mode 100644 index ded4e815..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16.verbose.sched.rpt.xml +++ /dev/null @@ -1,45 +0,0 @@ - - -
    -Fri Mar 29 14:40:34 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -black_hole_float_v16 (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 1.215 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -?, ?, ?, ?, ?, ?, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.sched.adb.xml deleted file mode 100644 index 0cdf35e6..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.sched.adb.xml +++ /dev/null @@ -1,129 +0,0 @@ -black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.verbose.sched.rpt.xml deleted file mode 100644 index d0d3b3a3..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:34 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -black_hole_float_v16 (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 1.215 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -?, ?, ?, ?, ?, ?, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -?, ?, 1, 1, 1, inf, yes -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_csynth.xml deleted file mode 100644 index b6cd8b25..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_Pipeline_VITIS_LOOP_400_1_csynth.xml +++ /dev/null @@ -1,167 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 -3.33 -0.90 -vivado - - - -no - -ns -1.215 - - -clock cycles -undef -undef -undef -undef -undef -undef -undef -undef - - - -2.43 -inf -undef -undef -1 -1 - - - - - - - - -2 -14 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -black_hole_float_v16_Pipeline_VITIS_LOOP_400_1 -return value - -ap_ctrl_hs - -out -1 -control - - -fifo_in_s_dout -fifo_in_s -pointer - -ap_fifo - -in -513 -control - - -fifo_in_s_empty_n -fifo_in_s -pointer - -ap_fifo - -in -1 -control - - -fifo_in_s_read -fifo_in_s -pointer - -ap_fifo - -out -1 -control - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_csynth.xml deleted file mode 100644 index 6202f2f9..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_float_v16_csynth.xml +++ /dev/null @@ -1,194 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -black_hole_float_v16 -3.33 -0.90 -vivado - - - -no - -ns -1.215 - - -clock cycles -undef -undef -undef -undef -undef -undef -undef -undef - - - - - -6 -43 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -black_hole_float_v16 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst_n -black_hole_float_v16 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -black_hole_float_v16 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -black_hole_float_v16 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -black_hole_float_v16 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -black_hole_float_v16 -return value - -ap_ctrl_hs - -out -1 -control - - -fifo_in_s_dout -fifo_in_s -pointer - -ap_fifo - -in -513 -control -int - - -fifo_in_s_empty_n -fifo_in_s -pointer - -ap_fifo - -in -1 -control -int - - -fifo_in_s_read -fifo_in_s -pointer - -ap_fifo - -out -1 -control -int - - -fifo_in_peek_dout -fifo_in_peek -pointer - -ap_fifo - -in -513 -control -int - - -fifo_in_peek_empty_n -fifo_in_peek -pointer - -ap_fifo - -in -1 -control -int - - -fifo_in_peek_read -fifo_in_peek -pointer - -ap_fifo - -out -1 -control -int - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int.sched.adb.xml deleted file mode 100644 index 8b52c060..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int.sched.adb.xml +++ /dev/null @@ -1,207 +0,0 @@ -black_hole_int - - - - - - - - - - - - - - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int.verbose.sched.rpt.xml deleted file mode 100644 index c4c67e70..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int.verbose.sched.rpt.xml +++ /dev/null @@ -1,45 +0,0 @@ - - -
    -Fri Mar 29 14:40:34 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -black_hole_int (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 1.215 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -?, ?, ?, ?, ?, ?, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_Pipeline_VITIS_LOOP_399_1.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_Pipeline_VITIS_LOOP_399_1.sched.adb.xml deleted file mode 100644 index 7ccbb4bf..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_Pipeline_VITIS_LOOP_399_1.sched.adb.xml +++ /dev/null @@ -1,129 +0,0 @@ -black_hole_int_Pipeline_VITIS_LOOP_399_1 - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_Pipeline_VITIS_LOOP_399_1.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_Pipeline_VITIS_LOOP_399_1.verbose.sched.rpt.xml deleted file mode 100644 index c78f7420..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_Pipeline_VITIS_LOOP_399_1.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:34 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -black_hole_int (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 1.215 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -?, ?, ?, ?, ?, ?, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -?, ?, 1, 1, 1, inf, yes -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_Pipeline_VITIS_LOOP_399_1_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_Pipeline_VITIS_LOOP_399_1_csynth.xml deleted file mode 100644 index ca1974bb..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_Pipeline_VITIS_LOOP_399_1_csynth.xml +++ /dev/null @@ -1,167 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -black_hole_int_Pipeline_VITIS_LOOP_399_1 -3.33 -0.90 -vivado - - - -no - -ns -1.215 - - -clock cycles -undef -undef -undef -undef -undef -undef -undef -undef - - - -2.43 -inf -undef -undef -1 -1 - - - - - - - - -2 -14 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -black_hole_int_Pipeline_VITIS_LOOP_399_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -black_hole_int_Pipeline_VITIS_LOOP_399_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -black_hole_int_Pipeline_VITIS_LOOP_399_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -black_hole_int_Pipeline_VITIS_LOOP_399_1 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -black_hole_int_Pipeline_VITIS_LOOP_399_1 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -black_hole_int_Pipeline_VITIS_LOOP_399_1 -return value - -ap_ctrl_hs - -out -1 -control - - -fifo_in_s_dout -fifo_in_s -pointer - -ap_fifo - -in -33 -control - - -fifo_in_s_empty_n -fifo_in_s -pointer - -ap_fifo - -in -1 -control - - -fifo_in_s_read -fifo_in_s -pointer - -ap_fifo - -out -1 -control - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_csynth.xml deleted file mode 100644 index dabbf39e..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/black_hole_int_csynth.xml +++ /dev/null @@ -1,194 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -black_hole_int -3.33 -0.90 -vivado - - - -no - -ns -1.215 - - -clock cycles -undef -undef -undef -undef -undef -undef -undef -undef - - - - - -6 -43 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -black_hole_int -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst_n -black_hole_int -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -black_hole_int -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -black_hole_int -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -black_hole_int -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -black_hole_int -return value - -ap_ctrl_hs - -out -1 -control - - -fifo_in_s_dout -fifo_in_s -pointer - -ap_fifo - -in -33 -control -int - - -fifo_in_s_empty_n -fifo_in_s -pointer - -ap_fifo - -in -1 -control -int - - -fifo_in_s_read -fifo_in_s -pointer - -ap_fifo - -out -1 -control -int - - -fifo_in_peek_dout -fifo_in_peek -pointer - -ap_fifo - -in -33 -control -int - - -fifo_in_peek_empty_n -fifo_in_peek -pointer - -ap_fifo - -in -1 -control -int - - -fifo_in_peek_read -fifo_in_peek -pointer - -ap_fifo - -out -1 -control -int - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/csynth.xml deleted file mode 100644 index 99859c2c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/csynth.xml +++ /dev/null @@ -1,1339 +0,0 @@ - - - 2022.2 - - - ns - virtexuplus - xcu280-fsvh2892-2L-e - Sextans - 3.33 - 0.90 - vivado - - - no - - ns - 1.000 - - - clock cycles - 0 - 0 - 0 - 0 ns - 0 ns - 0 ns - 1 - 1 - - - - - 0 - 2332 - 4200 - 0 - 0 - - - 4032 - 9024 - 2607360 - 1303680 - 960 - - - - - s_axi_control_AWVALID - control - scalar - s_axi - in - 1 - unknown - int - 1 - - - s_axi_control_AWREADY - control - scalar - s_axi - out - 1 - unknown - int - 1 - - - s_axi_control_AWADDR - control - scalar - s_axi - in - 9 - unknown - int - 1 - - - s_axi_control_WVALID - control - scalar - s_axi - in - 1 - unknown - int - 1 - - - s_axi_control_WREADY - control - scalar - s_axi - out - 1 - unknown - int - 1 - - - s_axi_control_WDATA - control - scalar - s_axi - in - 32 - unknown - int - 1 - - - s_axi_control_WSTRB - control - scalar - s_axi - in - 4 - unknown - int - 1 - - - s_axi_control_ARVALID - control - scalar - s_axi - in - 1 - unknown - int - 1 - - - s_axi_control_ARREADY - control - scalar - s_axi - out - 1 - unknown - int - 1 - - - s_axi_control_ARADDR - control - scalar - s_axi - in - 9 - unknown - int - 1 - - - s_axi_control_RVALID - control - scalar - s_axi - out - 1 - unknown - int - 1 - - - s_axi_control_RREADY - control - scalar - s_axi - in - 1 - unknown - int - 1 - - - s_axi_control_RDATA - control - scalar - s_axi - out - 32 - unknown - int - 1 - - - s_axi_control_RRESP - control - scalar - s_axi - out - 2 - unknown - int - 1 - - - s_axi_control_BVALID - control - scalar - s_axi - out - 1 - unknown - int - 1 - - - s_axi_control_BREADY - control - scalar - s_axi - in - 1 - unknown - int - 1 - - - s_axi_control_BRESP - control - scalar - s_axi - out - 2 - unknown - int - 1 - - - ap_clk - Sextans - return value - - ap_ctrl_hs - - in - 1 - control - - - ap_rst_n - Sextans - return value - - ap_ctrl_hs - - in - 1 - control - - - interrupt - Sextans - return value - - ap_ctrl_hs - - out - 1 - unknown - - - - - Sextans - - - - - Sextans - - - 3.33 - 0.90 - 1.000 - - - 0 - 0 - 0 - 0 ns - 0 ns - 0 ns - 1 - no - - - - - 0 - 4032 - 0 - 2332 - 2607360 - ~0 - 4200 - 1303680 - ~0 - 0 - 960 - 0 - 0 - 9024 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - s_axi_control_ARADDR - s_axi_control_ARREADY - s_axi_control_ARVALID - s_axi_control_AWADDR - s_axi_control_AWREADY - s_axi_control_AWVALID - s_axi_control_BREADY - s_axi_control_BRESP - s_axi_control_BVALID - s_axi_control_RDATA - s_axi_control_RREADY - s_axi_control_RRESP - s_axi_control_RVALID - s_axi_control_WDATA - s_axi_control_WREADY - s_axi_control_WSTRB - s_axi_control_WVALID - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - s_axi_control - ap_rst_n - - - CLK - - - ap_clk - - - - - ACTIVE_LOW - - - RST - - - ap_rst_n - - - - - LEVEL_HIGH - - - INTERRUPT - - - interrupt - - - - -
    - - - Interface, Data Width, Address Width, Offset, Register - 32, 9, 16, 0, , , , , -
    -     - - - Interface, Register, Offset, Width, Access, Description, Bit Fields - CTRL, 0x00, 32, RW, Control signals, 0=AP_START 1=AP_DONE 2=AP_IDLE 3=AP_READY 7=AUTO_RESTART 9=INTERRUPT - GIER, 0x04, 32, RW, Global Interrupt Enable Register, 0=Enable - IP_IER, 0x08, 32, RW, IP Interrupt Enable Register, 0=CHAN0_INT_EN 1=CHAN1_INT_EN - IP_ISR, 0x0c, 32, RW, IP Interrupt Status Register, 0=CHAN0_INT_ST 1=CHAN1_INT_ST - edge_list_ptr_1, 0x10, 32, W, Data signal of edge_list_ptr, - edge_list_ptr_2, 0x14, 32, W, Data signal of edge_list_ptr, - edge_list_ch_0_1, 0x1c, 32, W, Data signal of edge_list_ch_0, - edge_list_ch_0_2, 0x20, 32, W, Data signal of edge_list_ch_0, - edge_list_ch_1_1, 0x28, 32, W, Data signal of edge_list_ch_1, - edge_list_ch_1_2, 0x2c, 32, W, Data signal of edge_list_ch_1, - edge_list_ch_2_1, 0x34, 32, W, Data signal of edge_list_ch_2, - edge_list_ch_2_2, 0x38, 32, W, Data signal of edge_list_ch_2, - edge_list_ch_3_1, 0x40, 32, W, Data signal of edge_list_ch_3, - edge_list_ch_3_2, 0x44, 32, W, Data signal of edge_list_ch_3, - edge_list_ch_4_1, 0x4c, 32, W, Data signal of edge_list_ch_4, - edge_list_ch_4_2, 0x50, 32, W, Data signal of edge_list_ch_4, - edge_list_ch_5_1, 0x58, 32, W, Data signal of edge_list_ch_5, - edge_list_ch_5_2, 0x5c, 32, W, Data signal of edge_list_ch_5, - edge_list_ch_6_1, 0x64, 32, W, Data signal of edge_list_ch_6, - edge_list_ch_6_2, 0x68, 32, W, Data signal of edge_list_ch_6, - edge_list_ch_7_1, 0x70, 32, W, Data signal of edge_list_ch_7, - edge_list_ch_7_2, 0x74, 32, W, Data signal of edge_list_ch_7, - mat_B_ch_0_1, 0x7c, 32, W, Data signal of mat_B_ch_0, - mat_B_ch_0_2, 0x80, 32, W, Data signal of mat_B_ch_0, - mat_B_ch_1_1, 0x88, 32, W, Data signal of mat_B_ch_1, - mat_B_ch_1_2, 0x8c, 32, W, Data signal of mat_B_ch_1, - mat_B_ch_2_1, 0x94, 32, W, Data signal of mat_B_ch_2, - mat_B_ch_2_2, 0x98, 32, W, Data signal of mat_B_ch_2, - mat_B_ch_3_1, 0xa0, 32, W, Data signal of mat_B_ch_3, - mat_B_ch_3_2, 0xa4, 32, W, Data signal of mat_B_ch_3, - mat_C_ch_in_0_1, 0xac, 32, W, Data signal of mat_C_ch_in_0, - mat_C_ch_in_0_2, 0xb0, 32, W, Data signal of mat_C_ch_in_0, - mat_C_ch_in_1_1, 0xb8, 32, W, Data signal of mat_C_ch_in_1, - mat_C_ch_in_1_2, 0xbc, 32, W, Data signal of mat_C_ch_in_1, - mat_C_ch_in_2_1, 0xc4, 32, W, Data signal of mat_C_ch_in_2, - mat_C_ch_in_2_2, 0xc8, 32, W, Data signal of mat_C_ch_in_2, - mat_C_ch_in_3_1, 0xd0, 32, W, Data signal of mat_C_ch_in_3, - mat_C_ch_in_3_2, 0xd4, 32, W, Data signal of mat_C_ch_in_3, - mat_C_ch_in_4_1, 0xdc, 32, W, Data signal of mat_C_ch_in_4, - mat_C_ch_in_4_2, 0xe0, 32, W, Data signal of mat_C_ch_in_4, - mat_C_ch_in_5_1, 0xe8, 32, W, Data signal of mat_C_ch_in_5, - mat_C_ch_in_5_2, 0xec, 32, W, Data signal of mat_C_ch_in_5, - mat_C_ch_in_6_1, 0xf4, 32, W, Data signal of mat_C_ch_in_6, - mat_C_ch_in_6_2, 0xf8, 32, W, Data signal of mat_C_ch_in_6, - mat_C_ch_in_7_1, 0x100, 32, W, Data signal of mat_C_ch_in_7, - mat_C_ch_in_7_2, 0x104, 32, W, Data signal of mat_C_ch_in_7, - mat_C_ch_0_1, 0x10c, 32, W, Data signal of mat_C_ch_0, - mat_C_ch_0_2, 0x110, 32, W, Data signal of mat_C_ch_0, - mat_C_ch_1_1, 0x118, 32, W, Data signal of mat_C_ch_1, - mat_C_ch_1_2, 0x11c, 32, W, Data signal of mat_C_ch_1, - mat_C_ch_2_1, 0x124, 32, W, Data signal of mat_C_ch_2, - mat_C_ch_2_2, 0x128, 32, W, Data signal of mat_C_ch_2, - mat_C_ch_3_1, 0x130, 32, W, Data signal of mat_C_ch_3, - mat_C_ch_3_2, 0x134, 32, W, Data signal of mat_C_ch_3, - mat_C_ch_4_1, 0x13c, 32, W, Data signal of mat_C_ch_4, - mat_C_ch_4_2, 0x140, 32, W, Data signal of mat_C_ch_4, - mat_C_ch_5_1, 0x148, 32, W, Data signal of mat_C_ch_5, - mat_C_ch_5_2, 0x14c, 32, W, Data signal of mat_C_ch_5, - mat_C_ch_6_1, 0x154, 32, W, Data signal of mat_C_ch_6, - mat_C_ch_6_2, 0x158, 32, W, Data signal of mat_C_ch_6, - mat_C_ch_7_1, 0x160, 32, W, Data signal of mat_C_ch_7, - mat_C_ch_7_2, 0x164, 32, W, Data signal of mat_C_ch_7, - NUM_ITE, 0x16c, 32, W, Data signal of NUM_ITE, - NUM_A_LEN, 0x174, 32, W, Data signal of NUM_A_LEN, - M, 0x17c, 32, W, Data signal of M, - K, 0x184, 32, W, Data signal of K, - P_N, 0x18c, 32, W, Data signal of P_N, - alpha_u, 0x194, 32, W, Data signal of alpha_u, - beta_u, 0x19c, 32, W, Data signal of beta_u, -
    -     - - - Interface, Type, Ports - clock, ap_clk, - reset, ap_rst_n, - interrupt, interrupt, - ap_ctrl_hs, , -
    -     -
    -     - -
    - - - Argument, Direction, Datatype - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, int const - in, int const - in, int const - in, int const - in, int const - in, int const - in, int const -
    -     - - - Argument, HW Interface, HW Type, HW Info - s_axi_control, register, name=edge_list_ptr_1 offset=0x10 range=32, - s_axi_control, register, name=edge_list_ptr_2 offset=0x14 range=32, - s_axi_control, register, name=edge_list_ch_0_1 offset=0x1c range=32, - s_axi_control, register, name=edge_list_ch_0_2 offset=0x20 range=32, - s_axi_control, register, name=edge_list_ch_1_1 offset=0x28 range=32, - s_axi_control, register, name=edge_list_ch_1_2 offset=0x2c range=32, - s_axi_control, register, name=edge_list_ch_2_1 offset=0x34 range=32, - s_axi_control, register, name=edge_list_ch_2_2 offset=0x38 range=32, - s_axi_control, register, name=edge_list_ch_3_1 offset=0x40 range=32, - s_axi_control, register, name=edge_list_ch_3_2 offset=0x44 range=32, - s_axi_control, register, name=edge_list_ch_4_1 offset=0x4c range=32, - s_axi_control, register, name=edge_list_ch_4_2 offset=0x50 range=32, - s_axi_control, register, name=edge_list_ch_5_1 offset=0x58 range=32, - s_axi_control, register, name=edge_list_ch_5_2 offset=0x5c range=32, - s_axi_control, register, name=edge_list_ch_6_1 offset=0x64 range=32, - s_axi_control, register, name=edge_list_ch_6_2 offset=0x68 range=32, - s_axi_control, register, name=edge_list_ch_7_1 offset=0x70 range=32, - s_axi_control, register, name=edge_list_ch_7_2 offset=0x74 range=32, - s_axi_control, register, name=mat_B_ch_0_1 offset=0x7c range=32, - s_axi_control, register, name=mat_B_ch_0_2 offset=0x80 range=32, - s_axi_control, register, name=mat_B_ch_1_1 offset=0x88 range=32, - s_axi_control, register, name=mat_B_ch_1_2 offset=0x8c range=32, - s_axi_control, register, name=mat_B_ch_2_1 offset=0x94 range=32, - s_axi_control, register, name=mat_B_ch_2_2 offset=0x98 range=32, - s_axi_control, register, name=mat_B_ch_3_1 offset=0xa0 range=32, - s_axi_control, register, name=mat_B_ch_3_2 offset=0xa4 range=32, - s_axi_control, register, name=mat_C_ch_in_0_1 offset=0xac range=32, - s_axi_control, register, name=mat_C_ch_in_0_2 offset=0xb0 range=32, - s_axi_control, register, name=mat_C_ch_in_1_1 offset=0xb8 range=32, - s_axi_control, register, name=mat_C_ch_in_1_2 offset=0xbc range=32, - s_axi_control, register, name=mat_C_ch_in_2_1 offset=0xc4 range=32, - s_axi_control, register, name=mat_C_ch_in_2_2 offset=0xc8 range=32, - s_axi_control, register, name=mat_C_ch_in_3_1 offset=0xd0 range=32, - s_axi_control, register, name=mat_C_ch_in_3_2 offset=0xd4 range=32, - s_axi_control, register, name=mat_C_ch_in_4_1 offset=0xdc range=32, - s_axi_control, register, name=mat_C_ch_in_4_2 offset=0xe0 range=32, - s_axi_control, register, name=mat_C_ch_in_5_1 offset=0xe8 range=32, - s_axi_control, register, name=mat_C_ch_in_5_2 offset=0xec range=32, - s_axi_control, register, name=mat_C_ch_in_6_1 offset=0xf4 range=32, - s_axi_control, register, name=mat_C_ch_in_6_2 offset=0xf8 range=32, - s_axi_control, register, name=mat_C_ch_in_7_1 offset=0x100 range=32, - s_axi_control, register, name=mat_C_ch_in_7_2 offset=0x104 range=32, - s_axi_control, register, name=mat_C_ch_0_1 offset=0x10c range=32, - s_axi_control, register, name=mat_C_ch_0_2 offset=0x110 range=32, - s_axi_control, register, name=mat_C_ch_1_1 offset=0x118 range=32, - s_axi_control, register, name=mat_C_ch_1_2 offset=0x11c range=32, - s_axi_control, register, name=mat_C_ch_2_1 offset=0x124 range=32, - s_axi_control, register, name=mat_C_ch_2_2 offset=0x128 range=32, - s_axi_control, register, name=mat_C_ch_3_1 offset=0x130 range=32, - s_axi_control, register, name=mat_C_ch_3_2 offset=0x134 range=32, - s_axi_control, register, name=mat_C_ch_4_1 offset=0x13c range=32, - s_axi_control, register, name=mat_C_ch_4_2 offset=0x140 range=32, - s_axi_control, register, name=mat_C_ch_5_1 offset=0x148 range=32, - s_axi_control, register, name=mat_C_ch_5_2 offset=0x14c range=32, - s_axi_control, register, name=mat_C_ch_6_1 offset=0x154 range=32, - s_axi_control, register, name=mat_C_ch_6_2 offset=0x158 range=32, - s_axi_control, register, name=mat_C_ch_7_1 offset=0x160 range=32, - s_axi_control, register, name=mat_C_ch_7_2 offset=0x164 range=32, - s_axi_control, register, name=NUM_ITE offset=0x16c range=32, - s_axi_control, register, name=NUM_A_LEN offset=0x174 range=32, - s_axi_control, register, name=M offset=0x17c range=32, - s_axi_control, register, name=K offset=0x184 range=32, - s_axi_control, register, name=P_N offset=0x18c range=32, - s_axi_control, register, name=alpha_u offset=0x194 range=32, - s_axi_control, register, name=beta_u offset=0x19c range=32, -
    -     -
    -     - -
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    -Fri Mar 29 14:40:35 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -read_A (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
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    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
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    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_A_Pipeline_rd_A.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_A_Pipeline_rd_A.sched.adb.xml deleted file mode 100644 index b275395b..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_A_Pipeline_rd_A.sched.adb.xml +++ /dev/null @@ -1,674 +0,0 @@ -read_A_Pipeline_rd_A - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -Cmp - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_A_Pipeline_rd_A.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_A_Pipeline_rd_A.verbose.sched.rpt.xml deleted file mode 100644 index a29b093c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_A_Pipeline_rd_A.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:34 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -read_A (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
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    -     -
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-ap_ctrl_hs - -out -1 -control - - -ap_idle -read_A_Pipeline_rd_A -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -read_A_Pipeline_rd_A -return value - -ap_ctrl_hs - -out -1 -control - - -A_len -A_len -scalar - -ap_none - -in -32 -data - - -fifo_A_din -fifo_A -pointer - -ap_fifo - -out -513 -control - - -fifo_A_full_n -fifo_A -pointer - -ap_fifo - -in -1 -control - - -fifo_A_write -fifo_A -pointer - -ap_fifo - -out -1 -control - - -A_read_data_s_dout -A_read_data_s -pointer - -ap_fifo - -in -513 -control - - -A_read_data_s_empty_n -A_read_data_s -pointer - -ap_fifo - -in -1 -control - - -A_read_data_s_read -A_read_data_s -pointer - -ap_fifo - -out -1 -control - - -A_read_addr_din -A_read_addr -pointer - -ap_fifo - -out -65 -control - - -A_read_addr_full_n -A_read_addr -pointer - -ap_fifo - -in -1 -control - - -A_read_addr_write -A_read_addr -pointer - -ap_fifo - -out -1 -control - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_A_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_A_csynth.xml deleted file mode 100644 index 08cf10dc..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_A_csynth.xml +++ /dev/null @@ -1,465 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -read_A -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -9 -40036 -160068 -29.970 ns -0.133 ms -0.533 ms -10 -160069 - - - -2.43 - - -1 -16 - - - - -5 -160064 - - - - -16 -533013 - - - - -5 -10004 - - - - - - - - - - -1 -132 -346 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -read_A -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst_n -read_A -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -read_A -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -read_A -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -read_A -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -read_A -return value - -ap_ctrl_hs - -out -1 -control - - -A_read_addr_din -A_read_addr -pointer - -ap_fifo - -out -65 -control -int - - -A_read_addr_full_n -A_read_addr -pointer - -ap_fifo - -in -1 -control -int - - -A_read_addr_write -A_read_addr -pointer - -ap_fifo - -out -1 -control -int - - -A_read_data_s_dout -A_read_data_s -pointer - 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-ap_fifo - -in -9 -control -int - - -A_write_resp_s_empty_n -A_write_resp_s -pointer - -ap_fifo - -in -1 -control -int - - -A_write_resp_s_read -A_write_resp_s -pointer - -ap_fifo - -out -1 -control -int - - -A_write_resp_peek_dout -A_write_resp_peek -pointer - -ap_fifo - -in -9 -control -int - - -A_write_resp_peek_empty_n -A_write_resp_peek -pointer - -ap_fifo - -in -1 -control -int - - -A_write_resp_peek_read -A_write_resp_peek -pointer - -ap_fifo - -out -1 -control -int - - -fifo_A_din -fifo_A -pointer - -ap_fifo - -out -513 -control -int - - -fifo_A_full_n -fifo_A -pointer - -ap_fifo - -in -1 -control -int - - -fifo_A_write -fifo_A -pointer - -ap_fifo - -out -1 -control -int - - -A_len -A_len -scalar - -ap_none - -in -32 -data -int - - -P_N -P_N -scalar - -ap_none - -in -32 -data -int - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_B.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_B.sched.adb.xml deleted file mode 100644 index 79c09891..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_B.sched.adb.xml +++ /dev/null @@ -1,971 +0,0 @@ -read_B - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Multiplier - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -Cmp - - - - - - - - - - - -Sel - - - - - - - - - - - -Multiplier - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_B.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_B.verbose.sched.rpt.xml deleted file mode 100644 index 3342b298..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_B.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:35 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -read_B (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -8, 8000067, 26.640 ns, 26.640 ms, 9, 8000068, no -
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    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -5, 8000064, 5 ~ 500004, -, -, 1 ~ 16, no -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_B_Pipeline_rd_B.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_B_Pipeline_rd_B.sched.adb.xml deleted file mode 100644 index 46a69083..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_B_Pipeline_rd_B.sched.adb.xml +++ /dev/null @@ -1,674 +0,0 @@ -read_B_Pipeline_rd_B - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -Cmp - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_B_Pipeline_rd_B.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_B_Pipeline_rd_B.verbose.sched.rpt.xml deleted file mode 100644 index dfd0a7a8..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_B_Pipeline_rd_B.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:35 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -read_B (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -3, 500002, 9.990 ns, 1.665 ms, 3, 500002, no -
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    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -1, 500000, 1, 1, 1, 1 ~ 500000, yes -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_B_Pipeline_rd_B_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_B_Pipeline_rd_B_csynth.xml deleted file mode 100644 index bfb2d648..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_B_Pipeline_rd_B_csynth.xml +++ /dev/null @@ -1,259 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -read_B_Pipeline_rd_B -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -3 -250002 -500002 -9.990 ns -0.833 ms -1.665 ms -3 -500002 - - - -2.43 - - -1 -500000 - - - - -1 -500000 - - - - -3 -1664999 - - -1 -1 - - - - - - - - -67 -166 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -read_B_Pipeline_rd_B -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -read_B_Pipeline_rd_B -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -read_B_Pipeline_rd_B -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -read_B_Pipeline_rd_B -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -read_B_Pipeline_rd_B -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -read_B_Pipeline_rd_B -return value - -ap_ctrl_hs - -out -1 -control - - -num_ite_B -num_ite_B -scalar - -ap_none - -in -32 -data - - -fifo_B_din -fifo_B -pointer - -ap_fifo - -out -513 -control - - -fifo_B_full_n -fifo_B -pointer - -ap_fifo - -in -1 -control - - -fifo_B_write -fifo_B -pointer - -ap_fifo - -out -1 -control - - -B_read_data_s_dout -B_read_data_s -pointer - -ap_fifo - -in -513 -control - - -B_read_data_s_empty_n -B_read_data_s -pointer - -ap_fifo - -in -1 -control - - -B_read_data_s_read -B_read_data_s -pointer - -ap_fifo - -out -1 -control - - -B_read_addr_din -B_read_addr -pointer - -ap_fifo - -out -65 -control - - -B_read_addr_full_n -B_read_addr -pointer - -ap_fifo - -in -1 -control - - -B_read_addr_write -B_read_addr -pointer - -ap_fifo - -out -1 -control - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_B_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_B_csynth.xml deleted file mode 100644 index a581a084..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_B_csynth.xml +++ /dev/null @@ -1,465 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -read_B -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -8 -2000035 -8000067 -26.640 ns -6.660 ms -26.640 ms -9 -8000068 - - - -2.43 - - -1 -16 - - - - -5 -8000064 - - - - -16 -26640212 - - - - -5 -500004 - - - - - - - - - - -2 -348 -403 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -read_B -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst_n -read_B -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -read_B -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -read_B -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -read_B -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -read_B -return value - -ap_ctrl_hs - -out -1 -control - - -B_read_addr_din -B_read_addr -pointer - -ap_fifo - -out -65 -control -int - - -B_read_addr_full_n -B_read_addr -pointer - -ap_fifo - -in -1 -control -int - - -B_read_addr_write -B_read_addr -pointer - -ap_fifo - -out -1 -control -int - - -B_read_data_s_dout -B_read_data_s -pointer - -ap_fifo - -in -513 -control -int - - -B_read_data_s_empty_n -B_read_data_s -pointer - -ap_fifo - -in -1 -control -int - - -B_read_data_s_read -B_read_data_s -pointer - -ap_fifo - -out -1 -control -int - - -B_read_data_peek_dout -B_read_data_peek -pointer - -ap_fifo - -in -513 -control -int - - -B_read_data_peek_empty_n -B_read_data_peek -pointer - -ap_fifo - -in -1 -control -int - - -B_read_data_peek_read -B_read_data_peek -pointer - -ap_fifo - -out -1 -control -int - - -B_write_addr_din -B_write_addr -pointer - -ap_fifo - -out -65 -control -int - - -B_write_addr_full_n -B_write_addr -pointer - -ap_fifo - -in -1 -control -int - - -B_write_addr_write -B_write_addr -pointer - -ap_fifo - -out -1 -control -int - - -B_write_data_din -B_write_data -pointer - -ap_fifo - -out -513 -control -int - - -B_write_data_full_n -B_write_data -pointer - -ap_fifo - -in -1 -control -int - - -B_write_data_write -B_write_data -pointer - -ap_fifo - -out -1 -control -int - - -B_write_resp_s_dout -B_write_resp_s -pointer - -ap_fifo - -in -9 -control -int - - -B_write_resp_s_empty_n -B_write_resp_s -pointer - -ap_fifo - -in -1 -control -int - - -B_write_resp_s_read -B_write_resp_s -pointer - -ap_fifo - -out -1 -control -int - - -B_write_resp_peek_dout -B_write_resp_peek -pointer - -ap_fifo - -in -9 -control -int - - -B_write_resp_peek_empty_n -B_write_resp_peek -pointer - -ap_fifo - -in -1 -control -int - - -B_write_resp_peek_read -B_write_resp_peek -pointer - -ap_fifo - -out -1 -control -int - - -fifo_B_din -fifo_B -pointer - -ap_fifo - -out -513 -control -int - - -fifo_B_full_n -fifo_B -pointer - -ap_fifo - -in -1 -control -int - - -fifo_B_write -fifo_B -pointer - -ap_fifo - -out -1 -control -int - - -K -K -scalar - -ap_none - -in -32 -data -int - - -P_N -P_N -scalar - -ap_none - -in -32 -data -int - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_C.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_C.sched.adb.xml deleted file mode 100644 index 3b9f26ea..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_C.sched.adb.xml +++ /dev/null @@ -1,1115 +0,0 @@ -read_C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -DSP48 - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -DSP48 - - - - - - - - - - - - - - -DSP48 - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -Cmp - - - - - - - - - - - -Sel - - - - - - - - - - - -DSP48 - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_C.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_C.verbose.sched.rpt.xml deleted file mode 100644 index aa11a199..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_C.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:35 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -read_C (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -9, 8000068, 29.970 ns, 26.640 ms, 10, 8000069, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -5, 8000064, 5 ~ 500004, -, -, 1 ~ 16, no -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_C_Pipeline_rd_C.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_C_Pipeline_rd_C.sched.adb.xml deleted file mode 100644 index 6cb6a08a..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_C_Pipeline_rd_C.sched.adb.xml +++ /dev/null @@ -1,674 +0,0 @@ -read_C_Pipeline_rd_C - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -Cmp - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_C_Pipeline_rd_C.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_C_Pipeline_rd_C.verbose.sched.rpt.xml deleted file mode 100644 index c0b385fb..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_C_Pipeline_rd_C.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:35 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -read_C (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -3, 500002, 9.990 ns, 1.665 ms, 3, 500002, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -1, 500000, 1, 1, 1, 1 ~ 500000, yes -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_C_Pipeline_rd_C_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_C_Pipeline_rd_C_csynth.xml deleted file mode 100644 index 836a9b27..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_C_Pipeline_rd_C_csynth.xml +++ /dev/null @@ -1,259 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -read_C_Pipeline_rd_C -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -3 -250002 -500002 -9.990 ns -0.833 ms -1.665 ms -3 -500002 - - - -2.43 - - -1 -500000 - - - - -1 -500000 - - - - -3 -1664999 - - -1 -1 - - - - - - - - -67 -166 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -read_C_Pipeline_rd_C -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -read_C_Pipeline_rd_C -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -read_C_Pipeline_rd_C -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -read_C_Pipeline_rd_C -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -read_C_Pipeline_rd_C -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -read_C_Pipeline_rd_C -return value - -ap_ctrl_hs - -out -1 -control - - -num_ite_C -num_ite_C -scalar - -ap_none - -in -32 -data - - -fifo_C_din -fifo_C -pointer - -ap_fifo - -out -513 -control - - -fifo_C_full_n -fifo_C -pointer - -ap_fifo - -in -1 -control - - -fifo_C_write -fifo_C -pointer - -ap_fifo - -out -1 -control - - -C_read_data_s_dout -C_read_data_s -pointer - -ap_fifo - -in -513 -control - - -C_read_data_s_empty_n -C_read_data_s -pointer - -ap_fifo - -in -1 -control - - -C_read_data_s_read -C_read_data_s -pointer - -ap_fifo - -out -1 -control - - -C_read_addr_din -C_read_addr -pointer - -ap_fifo - -out -65 -control - - -C_read_addr_full_n -C_read_addr -pointer - -ap_fifo - -in -1 -control - - -C_read_addr_write -C_read_addr -pointer - -ap_fifo - -out -1 -control - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_C_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_C_csynth.xml deleted file mode 100644 index 2df6879f..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_C_csynth.xml +++ /dev/null @@ -1,501 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -read_C -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -9 -2000036 -8000068 -29.970 ns -6.660 ms -26.640 ms -10 -8000069 - - - -2.43 - - -1 -16 - - - - -5 -8000064 - - - - -16 -26640212 - - - - -5 -500004 - - - - - - - - - - -1 -153 -391 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -read_C -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst_n -read_C -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -read_C -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -read_C -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -read_C -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -read_C -return value - -ap_ctrl_hs - -out -1 -control - - -C_read_addr_din -C_read_addr -pointer - -ap_fifo - -out -65 -control -int - - -C_read_addr_full_n -C_read_addr -pointer - -ap_fifo - -in -1 -control -int - - -C_read_addr_write -C_read_addr -pointer - -ap_fifo - -out -1 -control -int - - -C_read_data_s_dout -C_read_data_s -pointer - -ap_fifo - -in -513 -control -int - - -C_read_data_s_empty_n -C_read_data_s -pointer - -ap_fifo - -in -1 -control -int - - -C_read_data_s_read -C_read_data_s -pointer - -ap_fifo - -out -1 -control -int - - -C_read_data_peek_dout -C_read_data_peek -pointer - -ap_fifo - -in -513 -control -int - - -C_read_data_peek_empty_n -C_read_data_peek -pointer - -ap_fifo - -in -1 -control -int - - -C_read_data_peek_read -C_read_data_peek -pointer - -ap_fifo - -out -1 -control -int - - -C_write_addr_din -C_write_addr -pointer - -ap_fifo - -out -65 -control -int - - -C_write_addr_full_n -C_write_addr -pointer - -ap_fifo - -in -1 -control -int - - -C_write_addr_write -C_write_addr -pointer - -ap_fifo - -out -1 -control -int - - -C_write_data_din -C_write_data -pointer - -ap_fifo - -out -513 -control -int - - -C_write_data_full_n -C_write_data -pointer - -ap_fifo - -in -1 -control -int - - -C_write_data_write -C_write_data -pointer - -ap_fifo - -out -1 -control -int - - -C_write_resp_s_dout -C_write_resp_s -pointer - -ap_fifo - -in -9 -control -int - - -C_write_resp_s_empty_n -C_write_resp_s -pointer - -ap_fifo - -in -1 -control -int - - -C_write_resp_s_read -C_write_resp_s -pointer - -ap_fifo - -out -1 -control -int - - -C_write_resp_peek_dout -C_write_resp_peek -pointer - -ap_fifo - -in -9 -control -int - - -C_write_resp_peek_empty_n -C_write_resp_peek -pointer - -ap_fifo - -in -1 -control -int - - -C_write_resp_peek_read -C_write_resp_peek -pointer - -ap_fifo - -out -1 -control -int - - -fifo_C_din -fifo_C -pointer - -ap_fifo - -out -513 -control -int - - -fifo_C_full_n -fifo_C -pointer - -ap_fifo - -in -1 -control -int - - -fifo_C_write -fifo_C -pointer - -ap_fifo - -out -1 -control -int - - -M -M -scalar - -ap_none - -in -32 -data -int - - -P_N -P_N -scalar - -ap_none - -in -32 -data -int - - -wrC_inst_din -wrC_inst -pointer - -ap_fifo - -out -33 -control -int - - -wrC_inst_full_n -wrC_inst -pointer - -ap_fifo - -in -1 -control -int - - -wrC_inst_write -wrC_inst -pointer - -ap_fifo - -out -1 -control -int - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr.sched.adb.xml deleted file mode 100644 index ee9d8bad..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr.sched.adb.xml +++ /dev/null @@ -1,1250 +0,0 @@ -read_edge_list_ptr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Sel - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -DSP48 - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -DSP48 - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -DSP48 - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -Adder - - - - - - - - - - - -DSP48 - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr.verbose.sched.rpt.xml deleted file mode 100644 index 0e834655..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:34 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -read_edge_list_ptr (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -9, 12868, 29.970 ns, 42.850 us, 10, 12869, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -5, 12864, 5 ~ 804, -, -, 1 ~ 16, no -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_Pipeline_rd_ptr.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_Pipeline_rd_ptr.sched.adb.xml deleted file mode 100644 index 108ed861..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_Pipeline_rd_ptr.sched.adb.xml +++ /dev/null @@ -1,674 +0,0 @@ -read_edge_list_ptr_Pipeline_rd_ptr - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -Cmp - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_Pipeline_rd_ptr.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_Pipeline_rd_ptr.verbose.sched.rpt.xml deleted file mode 100644 index 968c630e..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_Pipeline_rd_ptr.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:34 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -read_edge_list_ptr (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -3, 802, 9.990 ns, 2.671 us, 3, 802, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -1, 800, 1, 1, 1, 1 ~ 800, yes -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_Pipeline_rd_ptr_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_Pipeline_rd_ptr_csynth.xml deleted file mode 100644 index 2cbaf15c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_Pipeline_rd_ptr_csynth.xml +++ /dev/null @@ -1,259 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -read_edge_list_ptr_Pipeline_rd_ptr -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -3 -402 -802 -9.990 ns -1.339 us -2.671 us -3 -802 - - - -2.43 - - -1 -800 - - - - -1 -800 - - - - -3 -2663 - - -1 -1 - - - - - - - - -67 -166 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -read_edge_list_ptr_Pipeline_rd_ptr -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -read_edge_list_ptr_Pipeline_rd_ptr -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -read_edge_list_ptr_Pipeline_rd_ptr -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -read_edge_list_ptr_Pipeline_rd_ptr -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -read_edge_list_ptr_Pipeline_rd_ptr -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -read_edge_list_ptr_Pipeline_rd_ptr -return value - -ap_ctrl_hs - -out -1 -control - - -num_ite_plus1 -num_ite_plus1 -scalar - -ap_none - -in -32 -data - - -fifo_edge_list_ptr_din -fifo_edge_list_ptr -pointer - -ap_fifo - -out -33 -control - - -fifo_edge_list_ptr_full_n -fifo_edge_list_ptr -pointer - -ap_fifo - -in -1 -control - - -fifo_edge_list_ptr_write -fifo_edge_list_ptr -pointer - -ap_fifo - -out -1 -control - - -edge_list_ptr_read_data_s_dout -edge_list_ptr_read_data_s -pointer - -ap_fifo - -in -33 -control - - -edge_list_ptr_read_data_s_empty_n -edge_list_ptr_read_data_s -pointer - -ap_fifo - -in -1 -control - - -edge_list_ptr_read_data_s_read -edge_list_ptr_read_data_s -pointer - -ap_fifo - -out -1 -control - - -edge_list_ptr_read_addr_din -edge_list_ptr_read_addr -pointer - -ap_fifo - -out -65 -control - - -edge_list_ptr_read_addr_full_n -edge_list_ptr_read_addr -pointer - -ap_fifo - -in -1 -control - - -edge_list_ptr_read_addr_write -edge_list_ptr_read_addr -pointer - -ap_fifo - -out -1 -control - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_csynth.xml deleted file mode 100644 index 539c6ab3..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/read_edge_list_ptr_csynth.xml +++ /dev/null @@ -1,525 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -read_edge_list_ptr -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -9 -3236 -12868 -29.970 ns -10.776 us -42.850 us -10 -12869 - - - -2.43 - - -1 -16 - - - - -5 -12864 - - - - -16 -42837 - - - - -5 -804 - - - - - - - - - - -1 -164 -422 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -read_edge_list_ptr -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst_n -read_edge_list_ptr -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -read_edge_list_ptr -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -read_edge_list_ptr -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -read_edge_list_ptr -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -read_edge_list_ptr -return value - -ap_ctrl_hs - -out -1 -control - - -num_ite -num_ite -scalar - -ap_none - -in -32 -data -int - - -M -M -scalar - -ap_none - -in -32 -data -int - - -P_N -P_N -scalar - -ap_none - -in -32 -data -int - - -K -K -scalar - -ap_none - -in -32 -data -int - - -edge_list_ptr_read_addr_din -edge_list_ptr_read_addr -pointer - -ap_fifo - -out -65 -control -int - - -edge_list_ptr_read_addr_full_n -edge_list_ptr_read_addr -pointer - -ap_fifo - -in -1 -control -int - - -edge_list_ptr_read_addr_write -edge_list_ptr_read_addr -pointer - -ap_fifo - -out -1 -control -int - - -edge_list_ptr_read_data_s_dout -edge_list_ptr_read_data_s -pointer - -ap_fifo - -in -33 -control -int - - -edge_list_ptr_read_data_s_empty_n -edge_list_ptr_read_data_s -pointer - -ap_fifo - -in -1 -control -int - - -edge_list_ptr_read_data_s_read -edge_list_ptr_read_data_s -pointer - -ap_fifo - -out -1 -control -int - - -edge_list_ptr_read_data_peek_dout -edge_list_ptr_read_data_peek -pointer - -ap_fifo - -in -33 -control -int - - -edge_list_ptr_read_data_peek_empty_n -edge_list_ptr_read_data_peek -pointer - -ap_fifo - -in -1 -control -int - - -edge_list_ptr_read_data_peek_read -edge_list_ptr_read_data_peek -pointer - -ap_fifo - -out -1 -control -int - - -edge_list_ptr_write_addr_din -edge_list_ptr_write_addr -pointer - -ap_fifo - -out -65 -control -int - - -edge_list_ptr_write_addr_full_n -edge_list_ptr_write_addr -pointer - -ap_fifo - -in -1 -control -int - - -edge_list_ptr_write_addr_write -edge_list_ptr_write_addr -pointer - -ap_fifo - -out -1 -control -int - - -edge_list_ptr_write_data_din -edge_list_ptr_write_data -pointer - -ap_fifo - -out -33 -control -int - - -edge_list_ptr_write_data_full_n -edge_list_ptr_write_data -pointer - -ap_fifo - -in -1 -control -int - - -edge_list_ptr_write_data_write -edge_list_ptr_write_data -pointer - -ap_fifo - -out -1 -control -int - - -edge_list_ptr_write_resp_s_dout -edge_list_ptr_write_resp_s -pointer - -ap_fifo - -in -9 -control -int - - -edge_list_ptr_write_resp_s_empty_n -edge_list_ptr_write_resp_s -pointer - -ap_fifo - -in -1 -control -int - - -edge_list_ptr_write_resp_s_read -edge_list_ptr_write_resp_s -pointer - -ap_fifo - -out -1 -control -int - - -edge_list_ptr_write_resp_peek_dout -edge_list_ptr_write_resp_peek -pointer - -ap_fifo - -in -9 -control -int - - -edge_list_ptr_write_resp_peek_empty_n -edge_list_ptr_write_resp_peek -pointer - -ap_fifo - -in -1 -control -int - - -edge_list_ptr_write_resp_peek_read -edge_list_ptr_write_resp_peek -pointer - -ap_fifo - -out -1 -control -int - - -fifo_edge_list_ptr_din -fifo_edge_list_ptr -pointer - -ap_fifo - -out -33 -control -int - - -fifo_edge_list_ptr_full_n -fifo_edge_list_ptr -pointer - -ap_fifo - -in -1 -control -int - - -fifo_edge_list_ptr_write -fifo_edge_list_ptr -pointer - -ap_fifo - -out -1 -control -int - - -PE_inst_din -PE_inst -pointer - -ap_fifo - -out -33 -control -int - - -PE_inst_full_n -PE_inst -pointer - -ap_fifo - -in -1 -control -int - - -PE_inst_write -PE_inst -pointer - -ap_fifo - -out -1 -control -int - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/write_C.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/write_C.sched.adb.xml deleted file mode 100644 index 4b1609b4..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/write_C.sched.adb.xml +++ /dev/null @@ -1,1118 +0,0 @@ -write_C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -DSP48 - - - - - - - - - - - - - - -DSP48 - - - - - - - - - - - - - - -DSP48 - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -Cmp - - - - - - - - - - - -Sel - - - - - - - - - - - -DSP48 - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/write_C.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/write_C.verbose.sched.rpt.xml deleted file mode 100644 index feaacff3..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/write_C.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:35 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -write_C (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 3.414 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -11, 8000070, 37.559 ns, 27.316 ms, 12, 8000071, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -5, 8000064, 5 ~ 500004, -, -, 1 ~ 16, no -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/write_C_Pipeline_wr_C.sched.adb.xml b/benchmarks/tapa_flow/sextans/design/generated/report/write_C_Pipeline_wr_C.sched.adb.xml deleted file mode 100644 index ace6239c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/write_C_Pipeline_wr_C.sched.adb.xml +++ /dev/null @@ -1,798 +0,0 @@ -write_C_Pipeline_wr_C - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -Cmp - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -LogicGate - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - -Adder - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -Adder - - - - - - - - - - - - -NULL - - - - - - - - - - - - -Adder - - - - - - - - - - - - -Sel - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/write_C_Pipeline_wr_C.verbose.sched.rpt.xml b/benchmarks/tapa_flow/sextans/design/generated/report/write_C_Pipeline_wr_C.verbose.sched.rpt.xml deleted file mode 100644 index d6ee6d4c..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/write_C_Pipeline_wr_C.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
    -Fri Mar 29 14:40:35 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -write_C (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
    - -
    - -
    - -Clock, Target, Estimated, Uncertainty -3.33 ns, 3.414 ns, 0.90 ns -
    -     -
    -     - -
    - -, min, max, min, max, min, max, Type -3, 500002, 10.243 ns, 1.707 ms, 3, 500002, no -
    -     - -
    - -Instance, Module, min, max, min, max, min, max, Type -
    -     - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -1, 500000, 1, 1, 1, 1 ~ 500000, yes -
    -     -
    -     -
    -     -
    -     diff --git a/benchmarks/tapa_flow/sextans/design/generated/report/write_C_Pipeline_wr_C_csynth.xml b/benchmarks/tapa_flow/sextans/design/generated/report/write_C_Pipeline_wr_C_csynth.xml deleted file mode 100644 index 19dd02c1..00000000 --- a/benchmarks/tapa_flow/sextans/design/generated/report/write_C_Pipeline_wr_C_csynth.xml +++ /dev/null @@ -1,292 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -write_C_Pipeline_wr_C -3.33 -0.90 -vivado - - - -no - -ns -3.414 - - -clock cycles -3 -250002 -500002 -10.243 ns -0.854 ms -1.707 ms -3 -500002 - - - -2.43 - - -1 -500000 - - - - -1 -500000 - - - - -3 -1707224 - - -1 -1 - - - - - - - - -67 -216 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -write_C_Pipeline_wr_C -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -write_C_Pipeline_wr_C -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -write_C_Pipeline_wr_C -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done 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z=s)-^*gs(zWuJ&t?N3yu_9uF#_Gd@*5Lz=pLh=z8v*-If5BvU!NW%Vv;SiLA{fW%K z{_Kc9fG3Ywo9IADkRn%d$&f^`|8V0p=vn=G=s9&Kr2XzoIvQ^s2mu5v+b$ z=m>|R&Ji30_502dDE3V^=m=1;Ab4(q7x3F~DE=oM0$fD-pCVUniNSC2ayQ@u+{Qe! l`^Js}I|}S5u%p0^0y_%qD6pfzjsiOh>?p9Kz;-F{{{jBS{bc|E diff --git a/benchmarks/tapa_flow/sextans/design/run_tapa.sh b/benchmarks/tapa_flow/sextans/design/run_tapa.sh index cf9dcccc..54aec1b4 100644 --- a/benchmarks/tapa_flow/sextans/design/run_tapa.sh +++ b/benchmarks/tapa_flow/sextans/design/run_tapa.sh @@ -1,14 +1,12 @@ # Copyright 2024 RapidStream Design Automation, Inc. # All Rights Reserved. -WORK_DIR=generated - -tapac \ - --work-dir ${WORK_DIR} \ +tapa compile \ --top Sextans \ - --part-num xcu280-fsvh2892-2L-e \ + --part-num xcu55c-fsvh2892-2L-e \ --clock-period 3.33 \ - -o ${WORK_DIR}/Sextans.xo \ - --connectivity config/link_config.ini \ - src/sextans.cpp \ - 2>&1 | tee ${WORK_DIR}/tapa.log + -o generated/Sextans.xo \ + -f src/sextans.cpp \ + 2>&1 | tee tapa.log + +# change `src/serpens.cpp` to `src/serpens-noconst.cpp` to generate the design without aggressively passing constants through handshake interfaces. diff --git a/benchmarks/tapa_flow/sextans/run.py b/benchmarks/tapa_flow/sextans/run.py deleted file mode 100644 index 14317fec..00000000 --- a/benchmarks/tapa_flow/sextans/run.py +++ /dev/null @@ -1,143 +0,0 @@ -__copyright__ = """ -Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. -The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -""" - -from rapidstream import get_u280_vitis_device_factory, RapidStreamTAPA -import os - -CURR_DIR = os.path.dirname(os.path.abspath(__file__)) -INI_PATH = f"{CURR_DIR}/design/config/link_config.ini" -VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1" -XO_PATH = f"{CURR_DIR}/design/generated/Sextans.xo" - - -factory = get_u280_vitis_device_factory(VITIS_PLATFORM) - -# Reserve resource for the HBM Memory Sub-System. -# The HMSS is not part of the user kernel so the partition optimization process -# is unaware of its existence. We need to manually reserve resources for it. -# For 512-bit HBM channels, each HBM channel uses approximately the following resources: -# AREA_PER_HBM_CHANNEL = { -# "LUT": 5000, -# "FF": 6500, -# "BRAM": 0, -# "URAM": 0, -# "DSP": 0, -# } -factory.reduce_slot_area(1, 0, lut=5000 * 16, ff=6500 * 16) -factory.reduce_slot_area(0, 0, lut=8000 * 15, ff=6500 * 13, bram_18k=400, dsp=1000) - -# For this U280 platform, the right most DSP column on the boundary between -# dynamic/static region is not usable. So we need to adjust the DSP count -# to reflect the actual available DSPs. -print("Reducing DSP of (1, 1) to make it less congested") -factory.reduce_slot_area(1, 1, dsp=100) - -rs = RapidStreamTAPA(f"{CURR_DIR}/build/{os.path.basename(__file__)}") - -rs.set_virtual_device(factory.generate_virtual_device()) -rs.add_xo_file(XO_PATH) -rs.set_vitis_platform(VITIS_PLATFORM) -rs.set_vitis_connectivity_config(INI_PATH) - -rs.set_top_module_name("Sextans") -rs.add_clock("ap_clk", 3.33) - -rs.add_flatten_targets(["Sextans"]) - -# Bind ports to HBM 16-31 -right_slot = "SLOT_X1Y0:SLOT_X1Y0" -left_slot = "SLOT_X0Y0:SLOT_X0Y0" - -# The config file binds the following argument to HBM 0 - 15 -# Thus we need to constrain them to the left side of SLR 0 -# sp=Sextans.edge_list_ptr:HBM[0] -# sp=Sextans.edge_list_ch_0:HBM[1] -# sp=Sextans.edge_list_ch_1:HBM[2] -# sp=Sextans.edge_list_ch_2:HBM[3] -# sp=Sextans.edge_list_ch_3:HBM[4] -# sp=Sextans.edge_list_ch_4:HBM[5] -# sp=Sextans.edge_list_ch_5:HBM[6] -# sp=Sextans.edge_list_ch_6:HBM[7] -# sp=Sextans.edge_list_ch_7:HBM[8] -# sp=Sextans.mat_B_ch_0:HBM[9] -# sp=Sextans.mat_B_ch_1:HBM[10] -# sp=Sextans.mat_B_ch_2:HBM[11] -# sp=Sextans.mat_B_ch_3:HBM[12] - -left_args = [ - "edge_list_ptr", - "edge_list_ch_0", - "edge_list_ch_1", - "edge_list_ch_2", - "edge_list_ch_3", - "edge_list_ch_4", - "edge_list_ch_5", - "edge_list_ch_6", - "edge_list_ch_7", - "mat_B_ch_0", - "mat_B_ch_1", - "mat_B_ch_2", - "mat_B_ch_3", -] -for arg in left_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", left_slot) - -# The config file binds the following argument to HBM 16 - 31 -# Thus we need to constrain them to the right side of SLR 0 -# sp=Sextans.mat_C_ch_0:HBM[16] -# sp=Sextans.mat_C_ch_1:HBM[17] -# sp=Sextans.mat_C_ch_2:HBM[18] -# sp=Sextans.mat_C_ch_3:HBM[19] -# sp=Sextans.mat_C_ch_4:HBM[20] -# sp=Sextans.mat_C_ch_5:HBM[21] -# sp=Sextans.mat_C_ch_6:HBM[22] -# sp=Sextans.mat_C_ch_7:HBM[23] -# sp=Sextans.mat_C_ch_in_0:HBM[24] -# sp=Sextans.mat_C_ch_in_1:HBM[25] -# sp=Sextans.mat_C_ch_in_2:HBM[26] -# sp=Sextans.mat_C_ch_in_3:HBM[27] -# sp=Sextans.mat_C_ch_in_4:HBM[28] -# sp=Sextans.mat_C_ch_in_5:HBM[29] -# sp=Sextans.mat_C_ch_in_6:HBM[30] -# sp=Sextans.mat_C_ch_in_7:HBM[31] - -right_args = [ - "mat_C_ch_0", - "mat_C_ch_1", - "mat_C_ch_2", - "mat_C_ch_3", - "mat_C_ch_4", - "mat_C_ch_5", - "mat_C_ch_6", - "mat_C_ch_7", - "mat_C_ch_in_0", - "mat_C_ch_in_1", - "mat_C_ch_in_2", - "mat_C_ch_in_3", - "mat_C_ch_in_4", - "mat_C_ch_in_5", - "mat_C_ch_in_6", - "mat_C_ch_in_7", -] -for arg in right_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", right_slot) - -# Constrain the remaining control ports. -# All ports must be constrained to a specific slot: -rs.assign_port_to_region("s_axi_control_.*", left_slot) -rs.assign_port_to_region("ap_clk", left_slot) -rs.assign_port_to_region("ap_rst_n", left_slot) -rs.assign_port_to_region("interrupt", left_slot) - -# Xustomize the placement strategy: -rs.set_placement_strategy("EarlyBlockPlacement") - -# Allow two parallel Vitis implementation -rs.run_dse( - max_workers=2, - max_dse_limit=0.85, - min_dse_limit=0.75, - partition_strategy="flat", -) diff --git a/benchmarks/tapa_flow/sextans/run_u55c.py b/benchmarks/tapa_flow/sextans/run_u55c.py new file mode 100644 index 00000000..f356c7b6 --- /dev/null +++ b/benchmarks/tapa_flow/sextans/run_u55c.py @@ -0,0 +1,22 @@ +__copyright__ = """ +Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. +""" + +from pathlib import Path +from rapidstream import get_u55c_vitis_device_factory + +CURR_DIR = Path(__file__).parent +CURR_FILE = Path(__file__).name + +VITIS_PLATFORM = ( + "xilinx_u55c_gen3x16_xdma_3_202210_1" # "xilinx_u280_gen3x16_xdma_1_202211_1" +) + +factory = get_u55c_vitis_device_factory(VITIS_PLATFORM) + +factory.reduce_slot_area(1, 0, lut=50000, ff=60000) +factory.reduce_slot_area(0, 0, lut=50000, ff=60000) +factory.reduce_slot_area(1, 1, dsp=100) + +factory.generate_virtual_device(Path(f"{CURR_DIR}/build/{CURR_FILE}/device.json")) diff --git a/benchmarks/tapa_flow/stencil_sasa/high_congestion/Makefile b/benchmarks/tapa_flow/stencil_sasa/high_congestion/Makefile index 3dbead17..49a72757 100644 --- a/benchmarks/tapa_flow/stencil_sasa/high_congestion/Makefile +++ b/benchmarks/tapa_flow/stencil_sasa/high_congestion/Makefile @@ -3,8 +3,8 @@ ROOT_DIR := $(shell git rev-parse --show-toplevel) KERNEL_NAME := unikernel -RS_SCRIPT := $(CURDIR)/run.py -AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json +RS_SCRIPT := $(CURDIR)/run_u55c.py +AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json IMPL_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json LINK_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini PLATFORM := xilinx_u55c_gen3x16_xdma_3_202210_1 @@ -26,21 +26,22 @@ all: $(RS_TARGET) cd $(RSPATH) && $(RSPYTHON) $(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG) -c clk_kernel_00_unbuffered_net -p 3.333 @echo $(SUCCESS) -$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) +$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) $(AB_CONFIG) mkdir -p $(TEMP_DIR) cd $(RSPATH) && $(RSXX)-tapaopt \ --work-dir $(TEMP_DIR) \ --tapa-xo-path $< \ --device-config $(DEVICE_CONFIG) \ --floorplan-config $(AB_CONFIG) \ - --single-reg \ --run-impl \ --implementation-config $(IMPL_CONFIG) \ --connectivity-ini $(LINK_CONFIG) -$(DEVICE_CONFIG):$(AB_CONFIG) +device:$(DEVICE_CONFIG) + +$(DEVICE_CONFIG): $(RS_SCRIPT) mkdir -p $(TEMP_DIR) - cd $(RSPATH) && $(RSPYTHON) $(RS_SCRIPT) + cd $(RSPATH) && $(RSPYTHON) $< show_groups: rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \ diff --git a/benchmarks/tapa_flow/stencil_sasa/high_congestion/README.md b/benchmarks/tapa_flow/stencil_sasa/high_congestion/README.md index f581aac4..f67cdf5b 100644 --- a/benchmarks/tapa_flow/stencil_sasa/high_congestion/README.md +++ b/benchmarks/tapa_flow/stencil_sasa/high_congestion/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -24,150 +24,66 @@ In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. We utilize TAPA to generate the `.xo` file. If you have not installed TAPA, we've already compiled the C++ source to `.xo` using TAPA. The original C++ source files are located in [design/src](design/src). The generated `.xo` file can be found at [design/generated/unikernel.xo](design/generated/unikernel.xo). To compile C++ to `.xo` using TAPA, we use the script [design/run_tapa.sh](design/run_tapa.sh), with the detailed commands shown below. For your convenience, we have also backed up all the generated metadata by TAPA in the [design/generated](design/generated/) directory. ```bash -WORK_DIR=generated -tapac \ - --work-dir ${WORK_DIR} \ - --top unikernel \ - --part-num xcu280-fsvh2892-2L-e \ - --clock-period 3.33 \ - -o ${WORK_DIR}/unikernel.xo \ - --connectivity config/link_config.ini \ - src/unikernel.cpp \ - 2>&1 | tee tapa.log +mkdir -p build/run_u55c.py +cd build/run_u55c.py && tapa compile \ +--top unikernel \ +--part-num xcu55c-fsvh2892-2L-e \ +--clock-period 3.33 \ +-o unikernel.xo \ +-f $< \ +2>&1 | tee tapa.log + ``` -### Step 2: Use Rapidstream to Optimize `.xo` Design +### Step 2: Define Virtual Device -The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. -The RapidStream flow for TAPA requires the following key inputs: +In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each +containing 16 clock regions of logic. In actual implementations, the available resource of each slot is reduced + based on the platform specifics, as some resources are reserved for shell logic. -- **Platform**: The Vitis platform (e.g., `xilinx_u280_gen3x16_xdma_1_202211_1`). -- **Device**: virtual device define by calling rapidstream APIs based on platform (e.g., `get_u280_vitis_device_factory`). -- **.xo file**: The `.xo` file generated by TAPA -- **Connectivity** (.ini): Include the configuration file for `v++` ([link_config.ini](design/config/run.py/link_config.ini)). -- **top_module_name**: Top module name for the kernel. -- **Clock**: All the clock and frequencies. -- **Flatten Module**: Within a design, not all modules need to be optimized. The flatten module name is the target module rapidstream will optimize. - -The Python snippet below shows how we initiate rapidstream instance to set up the rapidstream environment. - -```Python -from rapidstream import get_u280_vitis_device_factory, RapidStreamTAPA -import os - -CURR_DIR = os.path.dirname(os.path.abspath(__file__)) -INI_PATH = f"{CURR_DIR}/design/config/link_config.ini" -VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1" -XO_PATH = f"{CURR_DIR}/design/generated/unikernel.xo" -kernel_name = "unikernel" -factory = get_u280_vitis_device_factory(VITIS_PLATFORM) -rs = RapidStreamTAPA(f"{CURR_DIR}/build") -rs.set_virtual_device(factory.generate_virtual_device()) -rs.add_xo_file(XO_PATH) -rs.set_vitis_platform(VITIS_PLATFORM) -rs.set_vitis_connectivity_config(INI_PATH) -rs.set_top_module_name(kernel_name) -rs.add_clock("ap_clk", 3.33) -rs.add_flatten_targets([kernel_name]) -``` +AU55C Device -The HBM AXI port connection is described in [design/config/link_config.ini](design/config/run.py/link_config.ini). +To generate a `device.json` file that details the device features, such as slot resources and + locations, you can either run the `run_u55c.py` script by invoking RapidStream as shown below or + simply enter `make device` in the terminal. ```bash -[connectivity] -sp=unikernel.in_0:HBM[0] -sp=unikernel.out_0:HBM[1] -sp=unikernel.in_1:HBM[2] -sp=unikernel.out_1:HBM[3] -sp=unikernel.in_2:HBM[4] -sp=unikernel.out_2:HBM[5] -sp=unikernel.in_3:HBM[6] -sp=unikernel.out_3:HBM[7] -sp=unikernel.in_4:HBM[8] -sp=unikernel.out_4:HBM[9] -sp=unikernel.in_5:HBM[10] -sp=unikernel.out_5:HBM[11] -sp=unikernel.in_6:HBM[12] -sp=unikernel.out_6:HBM[13] -sp=unikernel.in_7:HBM[14] -sp=unikernel.out_7:HBM[15] -sp=unikernel.in_8:HBM[17] -sp=unikernel.out_8:HBM[18] -sp=unikernel.in_9:HBM[19] -sp=unikernel.out_9:HBM[20] -sp=unikernel.in_10:HBM[21] -sp=unikernel.out_10:HBM[22] -sp=unikernel.in_11:HBM[23] -sp=unikernel.out_11:HBM[24] -sp=unikernel.in_12:HBM[25] -sp=unikernel.out_12:HBM[26] -sp=unikernel.in_13:HBM[27] -sp=unikernel.out_13:HBM[28] -sp=unikernel.in_14:HBM[29] -sp=unikernel.out_14:HBM[30] +rapidstream run_u55c.py ``` -As a result, it is necessary to assign the kernel ports to the appropriate slots. The Python code below demonstrates this process. For comprehensive linking details, please refer to the [design/config/link_config.ini](design/config/run.py/link_config.ini) file. - - ```Python -right_slot = "SLOT_X1Y0:SLOT_X1Y0" -left_slot = "SLOT_X0Y0:SLOT_X0Y0" -left_args = [ - "in_0", - "out_0", - "in_1", - "out_1", - "in_2", - "out_2", - "in_3", - "out_3", - "in_4", - "out_4", - "in_5", - "out_5", - "in_6", - "out_6", - "in_7", - "out_7", -] -for arg in left_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", left_slot) -right_args = [ - "in_8", - "out_8", - "in_9", - "out_9", - "in_10", - "out_10", - "in_11", - "out_11", - "in_12", - "out_12", - "in_13", - "out_13", - "in_14", - "out_14", -] -for arg in right_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", right_slot) -rs.assign_port_to_region("s_axi_control_.*", left_slot) -rs.assign_port_to_region("ap_clk", left_slot) -rs.assign_port_to_region("ap_rst_n", left_slot) -rs.assign_port_to_region("interrupt", left_slot) -``` -For the complete detail, please refore to [./run.py](./run.py) file. Call the rapidstream by launching the command below or `make all`. +### Step 3: Use Rapidstream to Optimize `.xo` Design + +The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. +The RapidStream flow for TAPA requires the following key inputs: + +- **tapa-xo-path**: The path to the tapa-generated `xo` file (unikernel.xo). +- **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). +- **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is +the same for vitis link configure file. + +We encapulate the rapidstream command for TAPA as `rapidstream-tapaopt` for invoking. +You can run the command below or execute `make all` supported by our [Makefile](Makefile). ```bash -rapidstream run.py +rapidstream-tapaopt --work-dir build/run_u55c.py \ + --tapa-xo-path build/run_u55c.py/unikernel.xo \ + --device-config build/run_u55c.py/device.json \ + --floorplan-config design/config/run_u55c.py/floorplan_config.json \ + --implementation-config design/config/run_u55c.py/impl_config.json \ + --connectivity-ini design/config/run_u55c.py/link_config.ini ``` + If everything is successful, you should at least get one optimized `.xclbin` file. -### Step 3: Check the Group Module Report + +### Step 4: Check the Group Module Report RapidStream mandates a clear distinction between communication and computation within user designs. diff --git a/benchmarks/tapa_flow/stencil_sasa/high_congestion/autobridge_fail b/benchmarks/tapa_flow/stencil_sasa/high_congestion/autobridge_fail deleted file mode 100644 index e69de29b..00000000 diff --git a/benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run.py/ab_config.json b/benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run_u55c.py/floorplan_config.json similarity index 100% rename from benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run.py/ab_config.json rename to benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run_u55c.py/floorplan_config.json diff --git a/benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run_u55c.py/impl_config.json b/benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run_u55c.py/impl_config.json new file mode 100644 index 00000000..3c481977 --- /dev/null +++ b/benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run_u55c.py/impl_config.json @@ -0,0 +1,7 @@ +{ + "max_workers": 2, + "port_to_clock_period": { + "ap_clk": 3.33 + }, + "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1" +} diff --git a/benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run.py/link_config.ini b/benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run_u55c.py/link_config.ini similarity index 100% rename from benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run.py/link_config.ini rename to benchmarks/tapa_flow/stencil_sasa/high_congestion/design/config/run_u55c.py/link_config.ini diff --git a/benchmarks/tapa_flow/stencil_sasa/high_congestion/run.py b/benchmarks/tapa_flow/stencil_sasa/high_congestion/run_u55c.py similarity index 100% rename from benchmarks/tapa_flow/stencil_sasa/high_congestion/run.py rename to benchmarks/tapa_flow/stencil_sasa/high_congestion/run_u55c.py diff --git a/benchmarks/tapa_flow/stencil_sasa/low_congestion/Makefile b/benchmarks/tapa_flow/stencil_sasa/low_congestion/Makefile index 3dbead17..49a72757 100644 --- a/benchmarks/tapa_flow/stencil_sasa/low_congestion/Makefile +++ b/benchmarks/tapa_flow/stencil_sasa/low_congestion/Makefile @@ -3,8 +3,8 @@ ROOT_DIR := $(shell git rev-parse --show-toplevel) KERNEL_NAME := unikernel -RS_SCRIPT := $(CURDIR)/run.py -AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json +RS_SCRIPT := $(CURDIR)/run_u55c.py +AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json IMPL_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json LINK_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini PLATFORM := xilinx_u55c_gen3x16_xdma_3_202210_1 @@ -26,21 +26,22 @@ all: $(RS_TARGET) cd $(RSPATH) && $(RSPYTHON) $(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG) -c clk_kernel_00_unbuffered_net -p 3.333 @echo $(SUCCESS) -$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) +$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) $(AB_CONFIG) mkdir -p $(TEMP_DIR) cd $(RSPATH) && $(RSXX)-tapaopt \ --work-dir $(TEMP_DIR) \ --tapa-xo-path $< \ --device-config $(DEVICE_CONFIG) \ --floorplan-config $(AB_CONFIG) \ - --single-reg \ --run-impl \ --implementation-config $(IMPL_CONFIG) \ --connectivity-ini $(LINK_CONFIG) -$(DEVICE_CONFIG):$(AB_CONFIG) +device:$(DEVICE_CONFIG) + +$(DEVICE_CONFIG): $(RS_SCRIPT) mkdir -p $(TEMP_DIR) - cd $(RSPATH) && $(RSPYTHON) $(RS_SCRIPT) + cd $(RSPATH) && $(RSPYTHON) $< show_groups: rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \ diff --git a/benchmarks/tapa_flow/stencil_sasa/low_congestion/README.md b/benchmarks/tapa_flow/stencil_sasa/low_congestion/README.md index 6056f318..f67cdf5b 100644 --- a/benchmarks/tapa_flow/stencil_sasa/low_congestion/README.md +++ b/benchmarks/tapa_flow/stencil_sasa/low_congestion/README.md @@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. +- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA. - Optimize the .xo file with RapidStream to obtain an optimized .xo file. - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. @@ -24,139 +24,66 @@ In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. We utilize TAPA to generate the `.xo` file. If you have not installed TAPA, we've already compiled the C++ source to `.xo` using TAPA. The original C++ source files are located in [design/src](design/src). The generated `.xo` file can be found at [design/generated/unikernel.xo](design/generated/unikernel.xo). To compile C++ to `.xo` using TAPA, we use the script [design/run_tapa.sh](design/run_tapa.sh), with the detailed commands shown below. For your convenience, we have also backed up all the generated metadata by TAPA in the [design/generated](design/generated/) directory. ```bash -WORK_DIR=generated -tapac \ - --work-dir ${WORK_DIR} \ - --top unikernel \ - --part-num xcu280-fsvh2892-2L-e \ - --clock-period 3.33 \ - -o ${WORK_DIR}/unikernel.xo \ - --connectivity config/link_config.ini \ - src/unikernel.cpp \ - 2>&1 | tee tapa.log +mkdir -p build/run_u55c.py +cd build/run_u55c.py && tapa compile \ +--top unikernel \ +--part-num xcu55c-fsvh2892-2L-e \ +--clock-period 3.33 \ +-o unikernel.xo \ +-f $< \ +2>&1 | tee tapa.log + ``` -### Step 2: Use Rapidstream to Optimize `.xo` Design +### Step 2: Define Virtual Device -The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. -The RapidStream flow for TAPA requires the following key inputs: +In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each +containing 16 clock regions of logic. In actual implementations, the available resource of each slot is reduced + based on the platform specifics, as some resources are reserved for shell logic. -- **Platform**: The Vitis platform (e.g., `xilinx_u280_gen3x16_xdma_1_202211_1`). -- **Device**: virtual device define by calling rapidstream APIs based on platform (e.g., `get_u280_vitis_device_factory`). -- **.xo file**: The `.xo` file generated by TAPA -- **Connectivity** (.ini): Include the configuration file for `v++` ([link_config.ini](design/config/run.py/link_config.ini)). -- **top_module_name**: Top module name for the kernel. -- **Clock**: All the clock and frequencies. -- **Flatten Module**: Within a design, not all modules need to be optimized. The flatten module name is the target module rapidstream will optimize. - -The Python snippet below shows how we initiate rapidstream instance to set up the rapidstream environment. - -```Python -from rapidstream import get_u280_vitis_device_factory, RapidStreamTAPA -import os - -CURR_DIR = os.path.dirname(os.path.abspath(__file__)) -INI_PATH = f"{CURR_DIR}/design/config/link_config.ini" -VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1" -XO_PATH = f"{CURR_DIR}/design/generated/unikernel.xo" -kernel_name = "unikernel" -factory = get_u280_vitis_device_factory(VITIS_PLATFORM) -rs = RapidStreamTAPA(f"{CURR_DIR}/build") -rs.set_virtual_device(factory.generate_virtual_device()) -rs.add_xo_file(XO_PATH) -rs.set_vitis_platform(VITIS_PLATFORM) -rs.set_vitis_connectivity_config(INI_PATH) -rs.set_top_module_name(kernel_name) -rs.add_clock("ap_clk", 3.33) -rs.add_flatten_targets([kernel_name]) -``` +AU55C Device -The HBM AXI port connection is described in [design/config/link_config.ini](design/config/run.py/link_config.ini). +To generate a `device.json` file that details the device features, such as slot resources and + locations, you can either run the `run_u55c.py` script by invoking RapidStream as shown below or + simply enter `make device` in the terminal. ```bash -[connectivity] -sp=unikernel.in_0:HBM[0] -sp=unikernel.out_0:HBM[1] -sp=unikernel.in_1:HBM[2] -sp=unikernel.out_1:HBM[3] -sp=unikernel.in_3:HBM[4] -sp=unikernel.out_3:HBM[5] -sp=unikernel.in_6:HBM[6] -sp=unikernel.out_6:HBM[7] -sp=unikernel.in_9:HBM[8] -sp=unikernel.out_9:HBM[9] -sp=unikernel.in_11:HBM[10] -sp=unikernel.out_11:HBM[11] -sp=unikernel.in_2:HBM[12] -sp=unikernel.out_2:HBM[13] -sp=unikernel.in_4:HBM[18] -sp=unikernel.out_4:HBM[19] -sp=unikernel.in_5:HBM[20] -sp=unikernel.out_5:HBM[21] -sp=unikernel.in_7:HBM[22] -sp=unikernel.out_7:HBM[23] -sp=unikernel.in_8:HBM[24] -sp=unikernel.out_8:HBM[25] -sp=unikernel.in_10:HBM[26] -sp=unikernel.out_10:HBM[27] +rapidstream run_u55c.py ``` -As a result, it is necessary to assign the kernel ports to the appropriate slots. The Python code below demonstrates this process. For comprehensive linking details, please refer to the [design/config/link_config.ini](design/config/run.py/link_config.ini) file. - - ```Python -right_slot = "SLOT_X1Y0:SLOT_X1Y0" -left_slot = "SLOT_X0Y0:SLOT_X0Y0" -left_args = [ - "in_0", - "out_0", - "in_1", - "out_1", - "in_3", - "out_3", - "in_6", - "out_6", - "in_9", - "out_9", - "in_11", - "out_11", - "in_2", - "out_2", -] -for arg in left_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", left_slot) -right_args = [ - "in_4", - "out_4", - "in_5", - "out_5", - "in_7", - "out_7", - "in_8", - "out_8", - "in_10", - "out_10", -] -for arg in right_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", right_slot) -rs.assign_port_to_region("s_axi_control_.*", left_slot) -rs.assign_port_to_region("ap_clk", left_slot) -rs.assign_port_to_region("ap_rst_n", left_slot) -rs.assign_port_to_region("interrupt", left_slot) -``` -For the complete detail, please refore to [./run.py](./run.py) file. Call the rapidstream by launching the command below or `make all`. +### Step 3: Use Rapidstream to Optimize `.xo` Design + +The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. +The RapidStream flow for TAPA requires the following key inputs: + +- **tapa-xo-path**: The path to the tapa-generated `xo` file (unikernel.xo). +- **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.). +- **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is +the same for vitis link configure file. + +We encapulate the rapidstream command for TAPA as `rapidstream-tapaopt` for invoking. +You can run the command below or execute `make all` supported by our [Makefile](Makefile). ```bash -rapidstream run.py +rapidstream-tapaopt --work-dir build/run_u55c.py \ + --tapa-xo-path build/run_u55c.py/unikernel.xo \ + --device-config build/run_u55c.py/device.json \ + --floorplan-config design/config/run_u55c.py/floorplan_config.json \ + --implementation-config design/config/run_u55c.py/impl_config.json \ + --connectivity-ini design/config/run_u55c.py/link_config.ini ``` + If everything is successful, you should at least get one optimized `.xclbin` file. -### Step 3: Check the Group Module Report +### Step 4: Check the Group Module Report RapidStream mandates a clear distinction between communication and computation within user designs. diff --git a/benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run.py/ab_config.json b/benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run_u55c.py/floorplan_config.json similarity index 100% rename from benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run.py/ab_config.json rename to benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run_u55c.py/floorplan_config.json diff --git a/benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run_u55c.py/impl_config.json b/benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run_u55c.py/impl_config.json new file mode 100644 index 00000000..3c481977 --- /dev/null +++ b/benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run_u55c.py/impl_config.json @@ -0,0 +1,7 @@ +{ + "max_workers": 2, + "port_to_clock_period": { + "ap_clk": 3.33 + }, + "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1" +} diff --git a/benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run.py/link_config.ini b/benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run_u55c.py/link_config.ini similarity index 100% rename from benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run.py/link_config.ini rename to benchmarks/tapa_flow/stencil_sasa/low_congestion/design/config/run_u55c.py/link_config.ini diff --git a/benchmarks/tapa_flow/stencil_sasa/low_congestion/run.py b/benchmarks/tapa_flow/stencil_sasa/low_congestion/run_u55c.py similarity index 100% rename from benchmarks/tapa_flow/stencil_sasa/low_congestion/run.py rename to benchmarks/tapa_flow/stencil_sasa/low_congestion/run_u55c.py diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/Makefile b/benchmarks/vitis_flow/vck5000_VecAdd/Makefile new file mode 100644 index 00000000..4cd0c472 --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/Makefile @@ -0,0 +1,83 @@ +# Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +# The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. + + +#ROOT_DIR := $(shell git rev-parse --show-toplevel) +PLATFORM := xilinx_vck5000_gen4x8_qdma_2_202220_1 +PLATFORM_REPO_PATHS := /opt/xilinx/platforms +XPFM_FILE := $(PLATFORM_REPO_PATHS)/$(PLATFORM)/$(PLATFORM).xpfm +SRC_DIR := $(CURDIR)/design +TARGET := hw +TEMP_DIR := $(CURDIR)/build +AIE_OBJ := $(TEMP_DIR)/libadf.a +KERNEL_NAMES := krnl_input_mover krnl_output_mover +XO_OBJS := $(foreach kernel,$(KERNEL_NAMES),$(TEMP_DIR)/$(kernel)_$(TARGET).xo) +EXECUTABLE := $(TEMP_DIR)/host_overlay.exe +XSA_OBJ := $(TEMP_DIR)/overlay_$(TARGET).xsa +XCLBIN := $(TEMP_DIR)/overlay_$(TARGET).xclbin +AXX := aiecompiler +AX86XX := x86simulator +CXXFLAGS := -std=c++17 -Wno-deprecated-declarations +CXXFLAGS += -I$(XILINX_XRT)/include -I$(XILINX_HLS)/include +LDFLAGS := -L$(XILINX_XRT)/lib +LDFLAGS += $(LDFLAGS) -lxrt_coreutil +VPP := v++ +CXX := g++ + + +all:$(EXECUTABLE) $(XCLBIN) + +$(EXECUTABLE): $(SRC_DIR)/host/host_overlay.cpp + @mkdir -p $(TEMP_DIR) + cd $(TEMP_DIR) && $(CXX) -o $(EXECUTABLE) $^ $(CXXFLAGS) $(LDFLAGS) + +$(XCLBIN): $(XSA_OBJ) $(AIE_OBJ) + cd $(TEMP_DIR) && $(VPP) -p -t $(TARGET) -f $(PLATFORM) $^ -o $@ --package.boot_mode=ospi + +$(XSA_OBJ): $(XO_OBJS) $(AIE_OBJ) + @mkdir -p $(TEMP_DIR) + @cd $(TEMP_DIR) && $(VPP) -l \ + --kernel_frequency 200 \ + --platform $(PLATFORM) \ + -t $(TARGET) \ + -g \ + --save-temps \ + --config $(SRC_DIR)/cfg/xclbin_overlay.cfg \ + -o $@ \ + $^ + +$(XO_OBJS):$(TEMP_DIR)/%_$(TARGET).xo:$(SRC_DIR)/hls/%.cpp + @mkdir -p $(TEMP_DIR) + @cd $(TEMP_DIR) && $(VPP) --platform $(PLATFORM) -t $(TARGET) -c -k $* -o $@ $< + +ASIM: $(AIE_OBJ) + @echo "INFO:Running aiesimulator..." + @cd $(TEMP_DIR) && aiesimulator --pkg-dir=$(TEMP_DIR)/Work --profile + +$(AIE_OBJ): $(SRC_DIR)/aie/* + @mkdir -p $(TEMP_DIR)/Work + @cd $(TEMP_DIR) && $(AXX) \ + --target=$(TARGET) \ + --platform=$(XPFM_FILE) \ + --include="$(SRC_DIR)/aie" \ + --workdir=$(TEMP_DIR)/Work \ + $(SRC_DIR)/aie/graph.cpp + +run: + @cd $(TEMP_DIR) && ./host_overlay.exe $(XCLBIN) + +x86_compile: + @mkdir -p $(TEMP_DIR)/Work + @cd $(TEMP_DIR) && aiecompiler \ + --target=x86sim \ + --include="$(SRC_DIR)" \ + --include="$(CURDIR)/common" \ + --workdir=$(TEMP_DIR)/Work \ + $(SRC_DIR)/graph.cpp + +run_x86: + @cd $(TEMP_DIR) && x86simulator --pkg-dir=./Work --dump + @diff ../data/s3_exp.txt $(TEMP_DIR)/data/s3_act.txt + +clean: + -@rm -rf $(TEMP_DIR) diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/data/gen.py b/benchmarks/vitis_flow/vck5000_VecAdd/data/gen.py new file mode 100644 index 00000000..a8145b40 --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/data/gen.py @@ -0,0 +1,27 @@ +__copyright__ = """ +Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. +""" + +NUM = 16 + +with open("s0.txt", "w") as f: + f.write(f" 1 {NUM} 0 0\n") + f.write(" 0 0 0 0\n") + f.write(" 0 0 0 0\n") + f.write(" 0 0 0 0\n") + +with open("s1.txt", "w") as f: + for i in range(NUM): + str_out = str(i) + f.write(f"{str_out.rjust(4)}\n") + + +with open("s2.txt", "w") as f: + for i in range(NUM): + str_out = str(i) + f.write(f"{str_out.rjust(4)}\n") + +with open("s3_exp.txt", "w") as f: + for i in range(NUM): + f.write(f"{i*2} \n") diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/common.h b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/common.h new file mode 100644 index 00000000..48f942c3 --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/common.h @@ -0,0 +1,18 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +#pragma once +#include +#include + +//Definitions that are needed by both the AIE and host sources + +//S0 control packet, 16 word (64 bytes) total +struct overlay_S0_control +{ + //Parameters + uint32_t VEC_NUM; // The number of vectors of the inputs + uint32_t VEC_LEN; // The vector length of the inputs + uint32_t RSVD[14]; // reserved words to fill up the 64 byte packets +}; diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/graph.cpp b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/graph.cpp new file mode 100644 index 00000000..2dd651d9 --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/graph.cpp @@ -0,0 +1,20 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#include "graph.h" + +using namespace adf; + +graph_overlay my_graph; + +int main(int argc, char ** argv) +{ + my_graph.init(); +#if defined(__X86SIM__) + my_graph.run(1); +#else + my_graph.run(); +#endif + my_graph.end(); + return 0; +} diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/graph.h b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/graph.h new file mode 100644 index 00000000..1beb23de --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/graph.h @@ -0,0 +1,121 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#pragma once +#include + +#include "kernel_vadd.h" + + +#include "kernel_lshift.h" + + +#include "kernel_rshift.h" +#include "kernel_rshift_last.h" + + +using namespace adf; + +#define SHIFT_NUM (4) + +// 16 x 32 bits = 64 bytes +#define DATA_SIZE (64) +#define OCCUPANCY (0.9) +#define STARTCOL (0) +#define STARTROW (0) +#define MAXCOL (50) + +class graph_overlay: public graph +{ + +private: + kernel k_vadd; + kernel k_lshift[SHIFT_NUM]; + kernel k_rshift[SHIFT_NUM]; + +public: + input_plio p_s0; + input_plio p_s1; + input_plio p_s2; + output_plio p_s3; + + graph_overlay() + { + // create kernel + k_vadd = kernel::create(kernel_vadd); + source(k_vadd) = "../design/aie/kernel_vadd.cpp"; + headers(k_vadd) = {"../design/aie/kernel_vadd.h","../design/aie/common.h"}; + runtime(k_vadd) = OCCUPANCY; + + for(int i=0; i(k_lshift[i]) = OCCUPANCY; + } + + for(int i=0; i(k_rshift[i]) = OCCUPANCY; + } + + k_rshift[SHIFT_NUM-1] = kernel::create(kernel_rshift_last); + source(k_rshift[SHIFT_NUM-1]) = "../design/aie/kernel_rshift_last.cpp"; + headers(k_rshift[SHIFT_NUM-1]) = {"../design/aie/kernel_rshift_last.h","../design/aie/common.h"}; + runtime(k_rshift[SHIFT_NUM-1]) = OCCUPANCY; + + // Constrain the kernel to fixed locations + + for(int i=0; i(k_lshift[i]) = tile(STARTCOL+col_offset, STARTROW+2*row_offset); + location(k_rshift[i]) = tile(STARTCOL+col_offset, STARTROW+2*row_offset+1); + } + + + + // create port + p_s0 = input_plio::create("s0", plio_128_bits, "../data/s0.txt"); + p_s1 = input_plio::create("s1", plio_32_bits, "../data/s1.txt"); + p_s2 = input_plio::create("s2", plio_32_bits, "../data/s2.txt"); + p_s3 = output_plio::create("s3", plio_32_bits, "../data/s3_act.txt"); + + + // connect port and kernel + connect>(p_s0.out[0], k_vadd.in[0]); + connect>(p_s1.out[0], k_vadd.in[1]); + connect>(p_s2.out[0], k_vadd.in[2]); + connect (k_vadd.out[0], k_lshift[0].in[0]); + + connect (k_vadd.out[1], k_lshift[0].in[1]); + connect s_experi(k_lshift[0].out[0], k_rshift[0].in[0]); + //fifo_depth(s_experi) = 64; + + for(int i=0; i (k_rshift[i].out[0], k_lshift[i+1].in[0]); + connect (k_lshift[i+1].out[0], k_rshift[i+1].in[0]); + } + + for(int i=0; i (k_lshift[i].out[1], k_rshift[i].in[1]); + connect (k_rshift[i].out[1], k_lshift[i+1].in[1]); + } + + connect (k_lshift[SHIFT_NUM-1].out[1], k_rshift[SHIFT_NUM-1].in[1]); + connect>(k_rshift[SHIFT_NUM-1].out[0], p_s3.in[0]); + + }; + +}; diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_lshift.cpp b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_lshift.cpp new file mode 100644 index 00000000..89457e92 --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_lshift.cpp @@ -0,0 +1,49 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#include "kernel_lshift.h" +#include "common.h" +#include + +using namespace std; + +//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// VecAdd krnl to perform s1 << 1 +// Input window w_s0: control packet. 64 bytes +// Input window w_s1: intput 1 window, 32bits x s0.VEC_LEN +// Output window w_s2: output window, 32bits x s0.VEC_LEN +void kernel_lshift( + input_stream* s0, + input_stream* s1, + output_stream* s2, + output_stream* s3 +){ + + //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + //Acquire S0 control packet + //window_acquire(w_s0); + //window_acquire(w_s2); + + uint32_t VEC_NUM = readincr(s0); + uint32_t VEC_LEN = readincr(s0); + + writeincr(s2, VEC_NUM); + writeincr(s2, VEC_LEN); + + //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + //Process data + for (int i = 0; i < VEC_NUM; i++) // processing data of input vectors + { + // The input window size will be 32bits x s0.VEC_LEN + for (int j = 0; j < VEC_LEN; j++) + { + uint32_t in1 = readincr(s1); + writeincr(s3, (in1<<1)); + //printf("[KERNEL_LSHIFT] processing %d, %d\n", j, *(out+j)); + } + + } + + printf("%s: finish processing\n", __FILE__); + +} diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_lshift.h b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_lshift.h new file mode 100644 index 00000000..9b2a5fd1 --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_lshift.h @@ -0,0 +1,13 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +#pragma once +#include + +void kernel_lshift( + input_stream* s0, + input_stream* s1, + output_stream* s2, + output_stream* s3 +); diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift.cpp b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift.cpp new file mode 100644 index 00000000..f8eab5da --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift.cpp @@ -0,0 +1,49 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#include "kernel_rshift.h" +#include "common.h" +#include + +using namespace std; + +//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// VecAdd krnl to perform s1 << 1 +// Input window w_s0: control packet. 64 bytes +// Input window w_s1: intput 1 window, 32bits x s0.VEC_LEN +// Output window w_s2: output window, 32bits x s0.VEC_LEN +void kernel_rshift( + input_stream* s0, + input_stream* s1, + output_stream* s2, + output_stream* s3 +){ + + //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + //Acquire S0 control packet + //window_acquire(w_s0); + //window_acquire(w_s2); + + uint32_t VEC_NUM = readincr(s0); + uint32_t VEC_LEN = readincr(s0); + + writeincr(s2, VEC_NUM); + writeincr(s2, VEC_LEN); + + //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + //Process data + for (int i = 0; i < VEC_NUM; i++) // processing data of input vectors + { + // The input window size will be 32bits x s0.VEC_LEN + for (int j = 0; j < VEC_LEN; j++) + { + uint32_t in1 = readincr(s1); + writeincr(s3, (in1>>1)); + //printf("[KERNEL_LSHIFT] processing %d, %d\n", j, *(out+j)); + } + + } + + printf("%s: finish processing\n", __FILE__); + +} diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift.h b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift.h new file mode 100644 index 00000000..ac791f7c --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift.h @@ -0,0 +1,13 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +#pragma once +#include + +void kernel_rshift( + input_stream* s0, + input_stream* s1, + output_stream* s2, + output_stream* s3 +); diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift_last.cpp b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift_last.cpp new file mode 100644 index 00000000..9027b27e --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift_last.cpp @@ -0,0 +1,48 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#include "kernel_rshift_last.h" +#include "common.h" +#include + +using namespace std; + +//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// VecAdd krnl to perform s1 << 1 +// Input window w_s0: control packet. 64 bytes +// Input window w_s1: intput 1 window, 32bits x s0.VEC_LEN +// Output window w_s2: output window, 32bits x s0.VEC_LEN +void kernel_rshift_last( + input_stream* s0, + input_stream* s1, + output_window_uint32* restrict w_s3 +){ + + //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + //Acquire S0 control packet + //window_acquire(w_s0); + //window_acquire(w_s2); + + uint32_t VEC_NUM = readincr(s0); + uint32_t VEC_LEN = readincr(s0); + + //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + //Process data + for (int i = 0; i < VEC_NUM; i++) // processing data of input vectors + { + + uint32_t* restrict out =reinterpret_cast(w_s3->ptr); + + // The input window size will be 32bits x s0.VEC_LEN + for (int j = 0; j < VEC_LEN; j++) + { + uint32_t in1 = readincr(s1); + *(out+j) = (in1>>1); + //printf("[KERNEL_LSHIFT] processing %d, %d\n", j, *(out+j)); + } + + } + + printf("%s: finish processing\n", __FILE__); + +} diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift_last.h b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift_last.h new file mode 100644 index 00000000..ce9d3ecd --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_rshift_last.h @@ -0,0 +1,12 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +#pragma once +#include + +void kernel_rshift_last( + input_stream* s0, + input_stream* s1, + output_window_uint32* restrict w_s3 +); diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_vadd.cpp b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_vadd.cpp new file mode 100644 index 00000000..9c03c146 --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_vadd.cpp @@ -0,0 +1,65 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#include "kernel_vadd.h" +#include "common.h" + +using namespace std; + +//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// VecAdd krnl to perform s1 + s2 +// Input window w_s0: control packet. 64 bytes +// Input window w_s1: intput 1 window, 32bits x s0.VEC_LEN +// Input window w_s2: intput 2 window, 32bits x s0.VEC_LEN +// Output window w_s3: output window, 64 bytes +// Output window w_s4: output window, 32bits x s0.VEC_LEN +void kernel_vadd( + input_window_uint32* restrict w_s0, + input_window_uint32* restrict w_s1, + input_window_uint32* restrict w_s2, + output_stream* s3, + output_stream* s4 + ){ + + //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + //Acquire S0 control packet + //window_acquire(w_s0); + //window_acquire(w_s3); + + overlay_S0_control& s0_ctrl(*reinterpret_cast(w_s0->ptr)); + printf("[KERNEL_VADD] s0_ctrl.VEC_NUM = %d\n", s0_ctrl.VEC_NUM); + + writeincr(s3, s0_ctrl.VEC_NUM); + writeincr(s3, s0_ctrl.VEC_LEN); + + //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + //Process data + for (int i = 0; i < s0_ctrl.VEC_NUM; i++) // processing data of input vectors + { + + // The input window size will be 32bits x s0.VEC_LEN + //window_acquire(w_s1); + //window_acquire(w_s2); + //window_acquire(w_s4); + + //Get working pointers into the acquired S1/S2 windows + uint32_t* restrict in1 =reinterpret_cast(w_s1->ptr); + uint32_t* restrict in2 =reinterpret_cast(w_s2->ptr); + + + for (int j = 0; j < s0_ctrl.VEC_LEN; j++) {// processing data of input vectors + writeincr(s4, *(in1+j) + *(in2+j)); + printf("[KERNEL_VADD] processing %d\n", j); + } + + //window_release(w_s1); + //window_release(w_s2); + //window_release(w_s4); + + } + + //All done, release S0 window + //window_release(w_s0); + //window_release(w_s3); + +} diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_vadd.h b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_vadd.h new file mode 100644 index 00000000..28f9fe19 --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/aie/kernel_vadd.h @@ -0,0 +1,14 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +#pragma once +#include + +void kernel_vadd( + input_window_uint32* restrict w_s0, + input_window_uint32* restrict w_s1, + input_window_uint32* restrict w_s2, + output_stream* s3, + output_stream* s4 +); diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/cfg/xclbin_overlay.cfg b/benchmarks/vitis_flow/vck5000_VecAdd/design/cfg/xclbin_overlay.cfg new file mode 100644 index 00000000..6a25f212 --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/cfg/xclbin_overlay.cfg @@ -0,0 +1,20 @@ +[connectivity] +nk=krnl_output_mover:1:krnl_output_mover_0 +nk=krnl_input_mover:1:krnl_input_mover_0 + +slr = krnl_output_mover_0:SLR0 +slr = krnl_input_mover_0:SLR0 + +sp = krnl_input_mover_0.m_axi_gmem1:MC_NOC0 +sp = krnl_input_mover_0.m_axi_gmem2:MC_NOC0 +sp = krnl_input_mover_0.m_axi_gmem3:MC_NOC0 +sp = krnl_output_mover_0.m_axi_gmem1:MC_NOC0 + +stream_connect=krnl_input_mover_0.stream_s1:ai_engine_0.s0 +stream_connect=krnl_input_mover_0.stream_s2:ai_engine_0.s1 +stream_connect=krnl_input_mover_0.stream_s3:ai_engine_0.s2 +stream_connect=ai_engine_0.s3:krnl_output_mover_0.stream_s1 + +[vivado] +# use following line to improve the hw_emu running speed affected by platform +prop=fileset.sim_1.xsim.elaborate.xelab.more_options={-override_timeprecision -timescale=1ns/1ps} diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/hls/krnl_input_mover.cpp b/benchmarks/vitis_flow/vck5000_VecAdd/design/hls/krnl_input_mover.cpp new file mode 100644 index 00000000..3b215a32 --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/hls/krnl_input_mover.cpp @@ -0,0 +1,74 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#include +#include +#include + + +extern "C" { + + void krnl_input_mover( + int mem_in1_size, + int mem_in2_size, + int mem_in3_size, + + ap_int<32>* mem_in1, + ap_int<32>* mem_in2, + ap_int<32>* mem_in3, + + hls::stream >& stream_s1, + hls::stream >& stream_s2, + hls::stream >& stream_s3 + ) + { + #pragma HLS INTERFACE m_axi port=mem_in1 offset=slave bundle=gmem1 + #pragma HLS INTERFACE m_axi port=mem_in2 offset=slave bundle=gmem2 + #pragma HLS INTERFACE m_axi port=mem_in3 offset=slave bundle=gmem3 + + #pragma HLS INTERFACE axis port=stream_s1 + #pragma HLS INTERFACE axis port=stream_s2 + #pragma HLS INTERFACE axis port=stream_s3 + + #pragma HLS INTERFACE s_axilite port=mem_in1_size bundle=control + #pragma HLS INTERFACE s_axilite port=mem_in2_size bundle=control + #pragma HLS INTERFACE s_axilite port=mem_in3_size bundle=control + + #pragma HLS INTERFACE s_axilite port=mem_in1 bundle=control + #pragma HLS INTERFACE s_axilite port=mem_in2 bundle=control + #pragma HLS INTERFACE s_axilite port=mem_in3 bundle=control + + #pragma HLS INTERFACE s_axilite port=return bundle=control + + #pragma HLS DATAFLOW + + for(int i=0; i x1; + x1.data=mem_in1[i]; + x1.keep_all(); + stream_s1.write(x1); + } + + for(int i=0; i x2; + x2.data=mem_in2[i]; + x2.keep_all(); + stream_s2.write(x2); + } + + for(int i=0; i x3; + x3.data=mem_in3[i]; + x3.keep_all(); + stream_s3.write(x3); + } + + } + +} diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/hls/krnl_output_mover.cpp b/benchmarks/vitis_flow/vck5000_VecAdd/design/hls/krnl_output_mover.cpp new file mode 100644 index 00000000..8dc773ba --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/hls/krnl_output_mover.cpp @@ -0,0 +1,41 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#include +#include +#include + + +extern "C" { + + void krnl_output_mover( + int mem_out1_size, + + ap_int<32>* mem_out1, + + hls::stream >& stream_s1 + ) + { + #pragma HLS INTERFACE m_axi port=mem_out1 offset=slave bundle=gmem1 + + #pragma HLS INTERFACE axis port=stream_s1 + + #pragma HLS INTERFACE s_axilite port=mem_out1_size bundle=control + + #pragma HLS INTERFACE s_axilite port=mem_out1 bundle=control + + #pragma HLS INTERFACE s_axilite port=return bundle=control + + #pragma HLS DATAFLOW + + for(int i=0; i x1; + x1 = stream_s1.read(); + mem_out1[i] = x1.data; + } + + } + +} diff --git a/benchmarks/vitis_flow/vck5000_VecAdd/design/host/host_overlay.cpp b/benchmarks/vitis_flow/vck5000_VecAdd/design/host/host_overlay.cpp new file mode 100644 index 00000000..4a1de2dd --- /dev/null +++ b/benchmarks/vitis_flow/vck5000_VecAdd/design/host/host_overlay.cpp @@ -0,0 +1,113 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#include +#include +#include +#include +#include +#include "experimental/xrt_kernel.h" +#include "experimental/xrt_uuid.h" + +// Kernel arguments index definition +#define krnl_input_mover_size1 0 +#define krnl_input_mover_size2 1 +#define krnl_input_mover_size3 2 +#define krnl_input_mover_ptr1 3 +#define krnl_input_mover_ptr2 4 +#define krnl_input_mover_ptr3 5 + +#define krnl_output_mover_size 0 +#define krnl_output_mover_ptr 1 + +#define DEVICE_ID 0 +#define DATA_SIZE 16 + +// print command line help +void print_help(void) { + std::cout << std::endl << " Usage: host_everlay.exe -i JPEGFILE [-c COLOR]" << std::endl << std::endl; +} + + +// Main program body +int main(int argc, char *argv[]) { +struct timeval start, end; + + int buffer_size_in_bytes = DATA_SIZE * sizeof(int); + + std::string binaryFile; + if (argc < 2){ + std::cout << argc << std::endl; + print_help(); + }else{ + binaryFile = argv[argc-1]; + } + + + auto device = xrt::device(DEVICE_ID); + std::cout << "device name: " << device.get_info() << "\n"; + std::cout << "device bdf: " << device.get_info() << "\n"; + + + // Load xclbin + std::cout << "Load " << binaryFile << std::endl; + xrt::uuid xclbin_uuid = device.load_xclbin(binaryFile); + + // create kernel objects + std::cout << "Create kernels" << std::endl; + xrt::kernel krnl_input_mover = xrt::kernel(device, xclbin_uuid, "krnl_input_mover"); + xrt::kernel krnl_output_mover = xrt::kernel(device, xclbin_uuid, "krnl_output_mover"); + + auto bank_grp_in_buf1 = krnl_input_mover.group_id(krnl_input_mover_ptr1); + auto bank_grp_in_buf2 = krnl_input_mover.group_id(krnl_input_mover_ptr2); + auto bank_grp_in_buf3 = krnl_input_mover.group_id(krnl_input_mover_ptr3); + auto bank_grp_out_buf = krnl_output_mover.group_id(krnl_output_mover_ptr); + + auto input_buffer1 = xrt::bo(device, 64, bank_grp_in_buf1); + auto input_buffer2 = xrt::bo(device, buffer_size_in_bytes, bank_grp_in_buf2); + auto input_buffer3 = xrt::bo(device, buffer_size_in_bytes, bank_grp_in_buf3); + auto output_buffer = xrt::bo(device, buffer_size_in_bytes, bank_grp_out_buf); + + + auto input_buffer1_mapped = input_buffer1.map(); + auto input_buffer2_mapped = input_buffer2.map(); + auto input_buffer3_mapped = input_buffer3.map(); + auto output_buffer_mapped = output_buffer.map(); + + input_buffer1_mapped[0] = 1; + input_buffer1_mapped[1] = DATA_SIZE; + + for (auto i=2; i<16; ++i) { input_buffer1_mapped[i] = 0; } + for (auto i=0; i + +RapidStream Logo + +# TAPA Design + +## Introduction + +Rapidsteam is fully compatible with [TAPA](https://github.com/rapidstream-org/rapidstream-tapa). +In this recipe, we illustrate how to create a Xilinx objective file (`.xo`) using TAPA, then optimize the `.xo` file with Rapidstream, and finally utilize the optimized output in the ongoing Vitis development process. + + +## Xilinx Object Files + +[Vitis compiled object files (`.xo`)](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Design-Topology) are IP packages used in the AMD Vitis kernel development flow for programming the programmable logic (PL) region of target devices. These files can be [generated from HLS C++ code](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Developing-PL-Kernels-using-C) using the `v++` command, [packed from RTL code](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/RTL-Kernel-Development-Flow), or created using third-party frameworks like [RapidStream TAPA](https://github.com/rapidstream-org/rapidstream-tapa). In this example, we use `RapidStream TAPA` to generate the `VecAdd.xo` file, but the same flow applies to object files generated through other methods. + + +## Tutorial + +### Step 1: C++ Simulation + +Since our +design calls Xilinx Libraries, we need to source the Vitis environment before running the simulation. + +```bash +source /Vitis/2023.2/settings64.sh +``` + +Before generating the `.xo` file, we recommend running a C++ simulation to verify the correctness of the design. This step is optional but highly recommended. Run the following command or `make csim` to perform C++ simulation: + +```bash +tapa g++ design/main.cpp design/VecAdd.cpp \ +-I /opt/tools/xilinx/Vitis_HLS/2023.2/include \ +-o build/run_u55c.py/main.exe -O2 +./build/run_u55c.py/main.exe +``` + +Your should see the following output: + +```bash +I20241010 15:14:52.494259 4113880 task.h:66] running software simulation with TAPA library +kernel time: 0.0197967 s +PASS! +``` + +### Step 2: Generate the Xilinx Object File (`.xo`) + +We use TAPA on top of 2023.2 to generate the `.xo` file. Run the following command or run `make xo`: + +```bash +source /Vitis/2023.2/settings64.sh +mkdir -p build/run_u55c.py +cd build/run_u55c.py && tapa compile \ +--top VecAdd \ +--part-num xcu280-fsvh2892-2L-e \ +--clock-period 3.33 \ +-o VecAdd.xo \ +-f design/VecAdd.cpp \ +2>&1 | tee tapa.log +``` + +### Step 3 (Optional): Use Vitis --link to Generate the `.xclbin` File + +With the `.xo` file generated, you can use `v++ -link` to generate the `.xclbin` file. Run the following command or execute `make hw`: + +```bash +v++ -l -t hw \ + --platform xilinx_u280_gen3x16_xdma_1_202211_1 \ + --kernel VecAdd \ + --connectivity.nk VecAdd:1:VecAdd \ + --config design/link_config.ini \ + --temp_dir build \ + -o build/VecAdd.xclbin \ + build/VecAdd.xo +``` + +If your machines is equipped with the target FPGA device, you can deploy the optimized design on the FPGA by running the following command: + +```bash +./app.exe +``` + +:warning: **Note**: This step can take hours to complete. We recommend using the RapidStream flow to optimize the `.xo` file instead of generating the `.xclbin` file if you are familiar with AMD Vitis flow. + + +### Step 4: Define Virtual Device + +In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each +containing 16 clock regions of logic. In actual implementations, the available slots are reduced + based on the platform specifics, as some resources are reserved for shell logic. + +AU55C Device + +To generate a `device.json` file that details the device features, such as slot resources and + locations, you can either run the `run_u55c.py` script by invoking RapidStream as shown below or + simply enter `make device` in the terminal. + +```bash +rapidstream run_u55c.py +``` + + +### Step 5: Use Rapidstream to Optimize `.xo` Design + +The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. +The RapidStream flow for TAPA requires the following key inputs: + +- **tapa-xo-path**: The path to the tapa-generated `xo` file (VecAdd.xo). +- **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is +the same for vitis link configure file. + +We encapulate the rapidstream command for TAPA as `rapidstream-tapaop` for invoking. +You can run the command below or execute `make all` supported by our [Makefile](Makefile). + +```bash +rapidstream-tapaopt --work-dir build/run_u55c.py \ + --tapa-xo-path ./VecAdd.xo \ + --device-config build/run_u55c.py/device.json \ + --floorplan-config ../../design/config/run_u55c.py/ab_config.json \ + --implementation-config ../../ design/config/run_u55c.py/impl_config.json \ + --connectivity-ini ../../design/config/run_u55c.py/link_config.ini +``` + +When finished, you can locate these files using the following command: + +```bash +find ./build/run_u55c.py/ -name *.xo +``` + +If everything is successful, you should at least get one optimized `.xo` file located in `./build/dse/candidate_0/exported/VecAdd.xo`. + +### Step 7: Check the Group Module Report + + +RapidStream mandates a clear distinction between communication and computation within user designs. + +- In `Group modules`, users are tasked solely with defining inter-submodule communication. For those familiar with Vivado IP Integrator flow, crafting a Group module mirrors the process of connecting IPs in IPI. RapidStream subsequently integrates appropriate pipeline registers into these Group modules. + +- In `Leaf modules`, users retain the flexibility to implement diverse computational patterns, as RapidStream leaves these Leaf modules unchanged. + +For further details, please consult the [code style](https://docs.rapidstream-da.com/required-coding-style/) section in our Documentation. + +To generate a report on group types, execute the commands below or `run make show_groups`: + +```bash +rapidstream ../../common/util/get_group.py \ + -i build/passes/0-imported.json \ + -o build/module_types.csv +``` + +The module types for your design can be found in `build/module_types.csv`. Below, we list the four Group modules. In this design, `VecAdd` serves as a Group module, while the other three modules are added by RapidStream. + +| Module Name | Group Type | +|:--------------------------------:|:--------------:| +| VecAdd | grouped_module | +| __rs_VecAdd_aux | aux_module | +| ... | verilog_module | + + +### Step 8: Use Vitis --link with the Optimized `.xo` File + +With the optimized `.xo` file generated, you can use `v++ -link` to generate the `.xclbin` file. Run the following command or run `make`: + +```bash +v++ -l -t hw \ + --platform xilinx_u280_gen3x16_xdma_1_202211_1 \ + --kernel VecAdd \ + --connectivity.nk VecAdd:1:VecAdd \ + --config design/link_config.ini \ + --temp_dir build/rapidstream \ + -o build/VecAdd_rs_opt.xclbin \ + ./build/dse/candidate_0/exported/VecAdd.xo +``` + + +To examine the timing results for each design point, use this command: + +```bash +find ./build -name *.xclbin.info +``` + + + +If your machines is equipped with the target FPGA device, you can deploy the optimized design on the FPGA by running the following command: + +```bash +make host +./app.exe +``` + +## Next Step + + **Click here to [go back to Getting Started](../README.md)** diff --git a/getting_started/aie_source/data/bkgen.py b/getting_started/aie_source/data/bkgen.py new file mode 100755 index 00000000..c88fe98a --- /dev/null +++ b/getting_started/aie_source/data/bkgen.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +__copyright__ = """ +Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. +""" + +M = 2 +K = 8 +N = 64 + +with open("s0.txt", "w") as f: + for row in range(1, M + 1): + for col in range(1, K + 1): + str_out = str(f"{row}000{col}") + f.write(f"{str_out.rjust(4)}\n") + +with open("s1.txt", "w") as f: + for row in range(1, K + 1): + for col in range(1, N + 1): + str_out = str(f"{row}000{col}") + f.write(f"{str_out.rjust(4)}\n") + + +with open("s2_exp.txt", "w") as f: + for i in range(K): + f.write(f"{i*i} \n") diff --git a/getting_started/aie_source/data/gen.py b/getting_started/aie_source/data/gen.py new file mode 100755 index 00000000..cdedb5c2 --- /dev/null +++ b/getting_started/aie_source/data/gen.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +__copyright__ = """ +Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. +""" + +NUM = 256 + +# with open("s0.txt", "w") as f: +# f.write(f" 1 {NUM} 0 0\n") +# f.write(" 0 0 0 0\n") +# f.write(" 0 0 0 0\n") +# f.write(" 0 0 0 0\n") + +with open("s0.txt", "w") as f: + for i in range(NUM): + for j in range(4): + f.write(f"{i*4+j} ") + f.write("\n") + +with open("s1.txt", "w") as f: + for i in range(NUM): + for j in range(4): + f.write(f"{i*4+j} ") + f.write("\n") + + +with open("s2_exp.txt", "w") as f: + for i in range(NUM): + f.write(f"{i+i} \n") diff --git a/getting_started/aie_source/data/matmul.py b/getting_started/aie_source/data/matmul.py new file mode 100755 index 00000000..2c815d5b --- /dev/null +++ b/getting_started/aie_source/data/matmul.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +__copyright__ = """ +Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. +""" +import numpy as np + +M = 2 +K = 4 +N = 8 + +A = np.array([i for i in range(M * K)]).reshape(M, K) +B = np.array([i for i in range(K * N)]).reshape(K, N) +print(A) +print(B) + + +# Multiply matrices +result = np.matmul(A, B) # or you can use matrix_a @ matrix_b +print(result) diff --git a/getting_started/aie_source/design/aie/VecAdd.cpp b/getting_started/aie_source/design/aie/VecAdd.cpp new file mode 100644 index 00000000..911fc241 --- /dev/null +++ b/getting_started/aie_source/design/aie/VecAdd.cpp @@ -0,0 +1,20 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#include "VecAdd.h" + +using namespace adf; + +VecAdd my_graph; + +int main(int argc, char ** argv) +{ + my_graph.init(); +#if defined(__X86SIM__) + my_graph.run(1); +#else + my_graph.run(); +#endif + my_graph.end(); + return 0; +} diff --git a/getting_started/aie_source/design/aie/VecAdd.h b/getting_started/aie_source/design/aie/VecAdd.h new file mode 100644 index 00000000..8f72dc86 --- /dev/null +++ b/getting_started/aie_source/design/aie/VecAdd.h @@ -0,0 +1,74 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + +#pragma once +#include +#include "common.h" +#include "add_kernel.h" +#include "read_mem.h" +#include "write_mem.h" + + +using namespace adf; + + + +class VecAdd: public graph +{ + +private: + kernel k_vadd; + kernel k_read_mem1; + kernel k_read_mem2; + kernel k_write_mem; + +public: + input_plio p_s0; + input_plio p_s1; + output_plio p_s2; + + VecAdd() + { + // create kernel + k_read_mem1 = kernel::create(read_mem); + source(k_read_mem1) = "../design/aie/read_mem.cpp"; + headers(k_read_mem1) = {"../design/aie/read_mem.h","../design/aie/common.h"}; + runtime(k_read_mem1) = OCCUPANCY; + + k_read_mem2 = kernel::create(read_mem); + source(k_read_mem2) = "../design/aie/read_mem.cpp"; + headers(k_read_mem2) = {"../design/aie/read_mem.h","../design/aie/common.h"}; + runtime(k_read_mem2) = OCCUPANCY; + + k_vadd = kernel::create(add_kernel); + source(k_vadd) = "../design/aie/add_kernel.cpp"; + headers(k_vadd) = {"../design/aie/add_kernel.h","../design/aie/common.h"}; + runtime(k_vadd) = OCCUPANCY; + + k_write_mem = kernel::create(write_mem); + source(k_write_mem) = "../design/aie/write_mem.cpp"; + headers(k_write_mem) = {"../design/aie/write_mem.h","../design/aie/common.h"}; + runtime(k_write_mem) = OCCUPANCY; + + + location(k_read_mem1) = tile(5, 1); + location(k_read_mem2) = tile(4, 1); + location(k_vadd) = tile(5, 2); + location(k_write_mem) = tile(4, 2); + + // create port + p_s0 = input_plio::create("s0", plio_32_bits, "../data/s0.txt"); + p_s1 = input_plio::create("s1", plio_32_bits, "../data/s1.txt"); + p_s2 = output_plio::create("s2", plio_32_bits, "../data/s2_act.txt"); + + + // connect port and kernel + connect>(p_s0.out[0], k_read_mem1.in[0]); + connect>(p_s1.out[0], k_read_mem2.in[0]); + connect (k_read_mem1.out[0], k_vadd.in[0]); + connect (k_read_mem2.out[0], k_vadd.in[1]); + connect (k_vadd.out[0], k_write_mem.in[0]); + connect>(k_write_mem.out[0], p_s2.in[0]); + }; + +}; diff --git a/getting_started/aie_source/design/aie/add_kernel.cpp b/getting_started/aie_source/design/aie/add_kernel.cpp new file mode 100644 index 00000000..7de66c39 --- /dev/null +++ b/getting_started/aie_source/design/aie/add_kernel.cpp @@ -0,0 +1,17 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +// Includes +#include "add_kernel.h" +#include "common.h" + +void add_kernel( + input_stream* stream_in1, + input_stream* stream_in2, + output_stream* stream_out) { + + for (int i = 0; i < DATA_NUM; i++) { + writeincr(stream_out, readincr(stream_in1) + readincr(stream_in2)); + } +} diff --git a/getting_started/aie_source/design/aie/add_kernel.h b/getting_started/aie_source/design/aie/add_kernel.h new file mode 100644 index 00000000..bb8cb0f2 --- /dev/null +++ b/getting_started/aie_source/design/aie/add_kernel.h @@ -0,0 +1,8 @@ +#pragma once +#include + +void add_kernel( + input_stream* stream_in1, + input_stream* stream_in2, + output_stream* stream_out +); diff --git a/getting_started/aie_source/design/aie/common.h b/getting_started/aie_source/design/aie/common.h new file mode 100644 index 00000000..b046147c --- /dev/null +++ b/getting_started/aie_source/design/aie/common.h @@ -0,0 +1,14 @@ + +#pragma once +#include +#include + +#define DATA_NUM 256 + +// size of data in bytes +// uint32 is 4 bytes +#define DATA_SIZE (DATA_NUM*4) +#define OCCUPANCY (0.9) +#define STARTCOL (0) +#define STARTROW (0) +#define MAXCOL (50) diff --git a/getting_started/aie_source/design/aie/read_mem.cpp b/getting_started/aie_source/design/aie/read_mem.cpp new file mode 100644 index 00000000..190e5583 --- /dev/null +++ b/getting_started/aie_source/design/aie/read_mem.cpp @@ -0,0 +1,16 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +// Includes +#include "read_mem.h" +#include "common.h" + +void read_mem( + input_window* restrict mem_in, + output_stream* stream_out) { + + for (int i = 0; i < DATA_NUM; i++) { + writeincr(stream_out, window_readincr(mem_in)); + } +} diff --git a/getting_started/aie_source/design/aie/read_mem.h b/getting_started/aie_source/design/aie/read_mem.h new file mode 100644 index 00000000..fe52314e --- /dev/null +++ b/getting_started/aie_source/design/aie/read_mem.h @@ -0,0 +1,7 @@ +#pragma once +#include + +void read_mem( + input_window* restrict mem_in, + output_stream* stream_out +); diff --git a/getting_started/aie_source/design/aie/write_mem.cpp b/getting_started/aie_source/design/aie/write_mem.cpp new file mode 100644 index 00000000..e13b54c2 --- /dev/null +++ b/getting_started/aie_source/design/aie/write_mem.cpp @@ -0,0 +1,17 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +// Includes +#include "write_mem.h" +#include "common.h" + +void write_mem( + input_stream* stream_in, + output_window* restrict mem_out +) { + + for (int i = 0; i < DATA_NUM; i++) { + window_writeincr(mem_out, readincr(stream_in)); + } +} diff --git a/getting_started/aie_source/design/aie/write_mem.h b/getting_started/aie_source/design/aie/write_mem.h new file mode 100644 index 00000000..b73c0261 --- /dev/null +++ b/getting_started/aie_source/design/aie/write_mem.h @@ -0,0 +1,7 @@ +#pragma once +#include + +void write_mem( + input_stream* stream_in, + output_window* restrict mem_out +); diff --git a/getting_started/aie_source/design/config/run_u55c.py/floorplan_config.json b/getting_started/aie_source/design/config/run_u55c.py/floorplan_config.json new file mode 100644 index 00000000..d4e0f55d --- /dev/null +++ b/getting_started/aie_source/design/config/run_u55c.py/floorplan_config.json @@ -0,0 +1,14 @@ +{ + "dse_range_max": 0.8, + "dse_range_min": 0.7, + "partition_strategy": "flat", + "port_pre_assignments": { + ".*mem_in1_.*": "HBM[16]", + ".*mem_in2_.*": "HBM[17]", + ".*mem_out_.*": "HBM[18]", + "ap_clk": "CLK_RST", + "ap_rst_n": "CLK_RST", + "interrupt": "CLK_RST", + "s_axi_control_.*": "S_AXI_CONTROL" + } +} diff --git a/getting_started/aie_source/design/config/run_u55c.py/impl_config.json b/getting_started/aie_source/design/config/run_u55c.py/impl_config.json new file mode 100644 index 00000000..3c481977 --- /dev/null +++ b/getting_started/aie_source/design/config/run_u55c.py/impl_config.json @@ -0,0 +1,7 @@ +{ + "max_workers": 2, + "port_to_clock_period": { + "ap_clk": 3.33 + }, + "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1" +} diff --git a/getting_started/tapa_source/design/link_config.ini b/getting_started/aie_source/design/config/run_u55c.py/link_config.ini similarity index 100% rename from getting_started/tapa_source/design/link_config.ini rename to getting_started/aie_source/design/config/run_u55c.py/link_config.ini diff --git a/getting_started/aie_source/design/main.cpp b/getting_started/aie_source/design/main.cpp new file mode 100644 index 00000000..90279e0a --- /dev/null +++ b/getting_started/aie_source/design/main.cpp @@ -0,0 +1,49 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +#include +#include +#include +#include +#include + +#include +#include + +using std::clog; +using std::endl; +using std::vector; + +#define DATA_NUM 4096 + +void VecAdd(tapa::mmap mem_in1, tapa::mmap mem_in2, tapa::mmap mem_out); +DEFINE_string(bitstream, "", "path to bitstream file, run csim if empty"); + +int main(int argc, char **argv) +{ + vector mem_in1(DATA_NUM); + vector mem_in2(DATA_NUM); + vector mem_out(DATA_NUM); + vector out_golden(DATA_NUM); + + for(int i=0; i(rand() % DATA_NUM); + mem_in2[i] = static_cast(rand() % DATA_NUM); + out_golden[i] = mem_in1[i] + mem_in2[i]; + } + + int64_t kernel_time_ns = tapa::invoke( + VecAdd, FLAGS_bitstream, tapa::read_only_mmap(mem_in1), + tapa::read_only_mmap(mem_in2), tapa::write_only_mmap(mem_out)); + + for(int i=0; i + +RapidStream Logo + +# TAPA Design + +## Introduction + +Rapidsteam is fully compatible with [TAPA](https://github.com/rapidstream-org/rapidstream-tapa). +In this recipe, we illustrate how to create a Xilinx objective file (`.xo`) using TAPA, then optimize the `.xo` file with Rapidstream, and finally utilize the optimized output in the ongoing Vitis development process. + + +## Xilinx Object Files + +[Vitis compiled object files (`.xo`)](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Design-Topology) are IP packages used in the AMD Vitis kernel development flow for programming the programmable logic (PL) region of target devices. These files can be [generated from HLS C++ code](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Developing-PL-Kernels-using-C) using the `v++` command, [packed from RTL code](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/RTL-Kernel-Development-Flow), or created using third-party frameworks like [RapidStream TAPA](https://github.com/rapidstream-org/rapidstream-tapa). In this example, we use `RapidStream TAPA` to generate the `VecAdd.xo` file, but the same flow applies to object files generated through other methods. + + +## Tutorial + +### Step 1: C++ Simulation + +Since our +design calls Xilinx Libraries, we need to source the Vitis environment before running the simulation. + +```bash +source /Vitis/2023.2/settings64.sh +``` + +Before generating the `.xo` file, we recommend running a C++ simulation to verify the correctness of the design. This step is optional but highly recommended. Run the following command or `make csim` to perform C++ simulation: + +```bash +tapa g++ design/main.cpp design/VecAdd.cpp \ +-I /opt/tools/xilinx/Vitis_HLS/2023.2/include \ +-o build/run_u55c.py/main.exe -O2 +./build/run_u55c.py/main.exe +``` + +Your should see the following output: + +```bash +I20241010 15:14:52.494259 4113880 task.h:66] running software simulation with TAPA library +kernel time: 0.0197967 s +PASS! +``` + +### Step 2: Generate the Xilinx Object File (`.xo`) + +We use TAPA on top of 2023.2 to generate the `.xo` file. Run the following command or run `make xo`: + +```bash +source /Vitis/2023.2/settings64.sh +mkdir -p build/run_u55c.py +cd build/run_u55c.py && tapa compile \ +--top VecAdd \ +--part-num xcu280-fsvh2892-2L-e \ +--clock-period 3.33 \ +-o VecAdd.xo \ +-f design/VecAdd.cpp \ +2>&1 | tee tapa.log +``` + +### Step 3 (Optional): Use Vitis --link to Generate the `.xclbin` File + +With the `.xo` file generated, you can use `v++ -link` to generate the `.xclbin` file. Run the following command or execute `make hw`: + +```bash +v++ -l -t hw \ + --platform xilinx_u280_gen3x16_xdma_1_202211_1 \ + --kernel VecAdd \ + --connectivity.nk VecAdd:1:VecAdd \ + --config design/link_config.ini \ + --temp_dir build \ + -o build/VecAdd.xclbin \ + build/VecAdd.xo +``` + +If your machines is equipped with the target FPGA device, you can deploy the optimized design on the FPGA by running the following command: + +```bash +./app.exe +``` + +:warning: **Note**: This step can take hours to complete. We recommend using the RapidStream flow to optimize the `.xo` file instead of generating the `.xclbin` file if you are familiar with AMD Vitis flow. + + +### Step 4: Define Virtual Device + +In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each +containing 16 clock regions of logic. In actual implementations, the available slots are reduced + based on the platform specifics, as some resources are reserved for shell logic. + +AU55C Device + +To generate a `device.json` file that details the device features, such as slot resources and + locations, you can either run the `run_u55c.py` script by invoking RapidStream as shown below or + simply enter `make device` in the terminal. + +```bash +rapidstream run_u55c.py +``` + + +### Step 5: Use Rapidstream to Optimize `.xo` Design + +The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. +The RapidStream flow for TAPA requires the following key inputs: + +- **tapa-xo-path**: The path to the tapa-generated `xo` file (VecAdd.xo). +- **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is +the same for vitis link configure file. + +We encapulate the rapidstream command for TAPA as `rapidstream-tapaop` for invoking. +You can run the command below or execute `make all` supported by our [Makefile](Makefile). + +```bash +rapidstream-tapaopt --work-dir build/run_u55c.py \ + --tapa-xo-path ./VecAdd.xo \ + --device-config build/run_u55c.py/device.json \ + --floorplan-config ../../design/config/run_u55c.py/ab_config.json \ + --implementation-config ../../ design/config/run_u55c.py/impl_config.json \ + --connectivity-ini ../../design/config/run_u55c.py/link_config.ini +``` + +When finished, you can locate these files using the following command: + +```bash +find ./build/run_u55c.py/ -name *.xo +``` + +If everything is successful, you should at least get one optimized `.xo` file located in `./build/dse/candidate_0/exported/VecAdd.xo`. + +### Step 7: Check the Group Module Report + + +RapidStream mandates a clear distinction between communication and computation within user designs. + +- In `Group modules`, users are tasked solely with defining inter-submodule communication. For those familiar with Vivado IP Integrator flow, crafting a Group module mirrors the process of connecting IPs in IPI. RapidStream subsequently integrates appropriate pipeline registers into these Group modules. + +- In `Leaf modules`, users retain the flexibility to implement diverse computational patterns, as RapidStream leaves these Leaf modules unchanged. + +For further details, please consult the [code style](https://docs.rapidstream-da.com/required-coding-style/) section in our Documentation. + +To generate a report on group types, execute the commands below or `run make show_groups`: + +```bash +rapidstream ../../common/util/get_group.py \ + -i build/passes/0-imported.json \ + -o build/module_types.csv +``` + +The module types for your design can be found in `build/module_types.csv`. Below, we list the four Group modules. In this design, `VecAdd` serves as a Group module, while the other three modules are added by RapidStream. + +| Module Name | Group Type | +|:--------------------------------:|:--------------:| +| VecAdd | grouped_module | +| __rs_VecAdd_aux | aux_module | +| ... | verilog_module | + + +### Step 8: Use Vitis --link with the Optimized `.xo` File + +With the optimized `.xo` file generated, you can use `v++ -link` to generate the `.xclbin` file. Run the following command or run `make`: + +```bash +v++ -l -t hw \ + --platform xilinx_u280_gen3x16_xdma_1_202211_1 \ + --kernel VecAdd \ + --connectivity.nk VecAdd:1:VecAdd \ + --config design/link_config.ini \ + --temp_dir build/rapidstream \ + -o build/VecAdd_rs_opt.xclbin \ + ./build/dse/candidate_0/exported/VecAdd.xo +``` + + +To examine the timing results for each design point, use this command: + +```bash +find ./build -name *.xclbin.info +``` + + + +If your machines is equipped with the target FPGA device, you can deploy the optimized design on the FPGA by running the following command: + +```bash +make host +./app.exe +``` + +## Next Step + + **Click here to [go back to Getting Started](../README.md)** diff --git a/getting_started/aie_source_gmio/data/bkgen.py b/getting_started/aie_source_gmio/data/bkgen.py new file mode 100755 index 00000000..c88fe98a --- /dev/null +++ b/getting_started/aie_source_gmio/data/bkgen.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +__copyright__ = """ +Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. +""" + +M = 2 +K = 8 +N = 64 + +with open("s0.txt", "w") as f: + for row in range(1, M + 1): + for col in range(1, K + 1): + str_out = str(f"{row}000{col}") + f.write(f"{str_out.rjust(4)}\n") + +with open("s1.txt", "w") as f: + for row in range(1, K + 1): + for col in range(1, N + 1): + str_out = str(f"{row}000{col}") + f.write(f"{str_out.rjust(4)}\n") + + +with open("s2_exp.txt", "w") as f: + for i in range(K): + f.write(f"{i*i} \n") diff --git a/getting_started/aie_source_gmio/data/gen.py b/getting_started/aie_source_gmio/data/gen.py new file mode 100755 index 00000000..cdedb5c2 --- /dev/null +++ b/getting_started/aie_source_gmio/data/gen.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +__copyright__ = """ +Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. +""" + +NUM = 256 + +# with open("s0.txt", "w") as f: +# f.write(f" 1 {NUM} 0 0\n") +# f.write(" 0 0 0 0\n") +# f.write(" 0 0 0 0\n") +# f.write(" 0 0 0 0\n") + +with open("s0.txt", "w") as f: + for i in range(NUM): + for j in range(4): + f.write(f"{i*4+j} ") + f.write("\n") + +with open("s1.txt", "w") as f: + for i in range(NUM): + for j in range(4): + f.write(f"{i*4+j} ") + f.write("\n") + + +with open("s2_exp.txt", "w") as f: + for i in range(NUM): + f.write(f"{i+i} \n") diff --git a/getting_started/aie_source_gmio/data/matmul.py b/getting_started/aie_source_gmio/data/matmul.py new file mode 100755 index 00000000..2c815d5b --- /dev/null +++ b/getting_started/aie_source_gmio/data/matmul.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +__copyright__ = """ +Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. +""" +import numpy as np + +M = 2 +K = 4 +N = 8 + +A = np.array([i for i in range(M * K)]).reshape(M, K) +B = np.array([i for i in range(K * N)]).reshape(K, N) +print(A) +print(B) + + +# Multiply matrices +result = np.matmul(A, B) # or you can use matrix_a @ matrix_b +print(result) diff --git a/getting_started/aie_source_gmio/design/aie/VecAdd.cpp b/getting_started/aie_source_gmio/design/aie/VecAdd.cpp new file mode 100644 index 00000000..ed9065c5 --- /dev/null +++ b/getting_started/aie_source_gmio/design/aie/VecAdd.cpp @@ -0,0 +1,49 @@ + +#include +#include "common.h" +#include "VecAdd.h" +#if !defined(__AIESIM__) && !defined(__X86SIM__) && !defined(__ADF_FRONTEND__) + #include "adf/adf_api/XRTConfig.h" + #include "experimental/xrt_kernel.h" +#endif + +VecAdd gr; +int main(int argc, char ** argv) +{ +#if !defined(__AIESIM__) && !defined(__X86SIM__) && !defined(__ADF_FRONTEND__) + // Create XRT device handle for ADF API + char* xclbinFilename = argv[1]; + auto dhdl = xrtDeviceOpen(0);//device index=0 + xrtDeviceLoadXclbinFile(dhdl,xclbinFilename); + xuid_t uuid; + xrtDeviceGetXclbinUUID(dhdl, uuid); + adf::registerXRT(dhdl, uuid); +#endif + gr.init(); + + const int BLOCK_SIZE=DATA_NUM; + int32 *inputArray1=(int32*)adf::GMIO::malloc(BLOCK_SIZE*sizeof(int32)); + int32 *inputArray2=(int32*)adf::GMIO::malloc(BLOCK_SIZE*sizeof(int32)); + int32 *outputArray=(int32*)adf::GMIO::malloc(BLOCK_SIZE*sizeof(int32)); + // provide input data to AI Engine in inputArray + for (int i=0; i +#include "common.h" +#include "add_kernel.h" +#include "read_mem.h" +#include "write_mem.h" + +using namespace adf; + +class VecAdd: public adf::graph +{ +private: + kernel k_vadd; + kernel k_read_mem1; + kernel k_read_mem2; + kernel k_write_mem; + +public: + input_gmio m_s0; + input_gmio m_s1; + output_gmio m_s2; + + VecAdd() + { + // create kernel + k_read_mem1 = kernel::create(read_mem); + source(k_read_mem1) = "read_mem.cpp"; + headers(k_read_mem1) = {"read_mem.h","common.h"}; + runtime(k_read_mem1) = OCCUPANCY; + + k_read_mem2 = kernel::create(read_mem); + source(k_read_mem2) = "read_mem.cpp"; + headers(k_read_mem2) = {"read_mem.h","common.h"}; + runtime(k_read_mem2) = OCCUPANCY; + + k_vadd = kernel::create(add_kernel); + source(k_vadd) = "add_kernel.cpp"; + headers(k_vadd) = {"add_kernel.h","common.h"}; + runtime(k_vadd) = OCCUPANCY; + + k_write_mem = kernel::create(write_mem); + source(k_write_mem) = "write_mem.cpp"; + headers(k_write_mem) = {"write_mem.h","common.h"}; + runtime(k_write_mem) = OCCUPANCY; + + + location(k_read_mem1) = tile(5, 1); + location(k_read_mem2) = tile(4, 1); + location(k_vadd) = tile(5, 2); + location(k_write_mem) = tile(4, 2); + + m_s0 = input_gmio::create("m_s0", 64, 1000); + m_s1 = input_gmio::create("m_s1", 64, 1000); + m_s2 = output_gmio::create("m_s2", 64, 1000); + + connect>(m_s0.out[0], k_read_mem1.in[0]); + connect>(m_s1.out[0], k_read_mem2.in[0]); + connect (k_read_mem1.out[0], k_vadd.in[0]); + connect (k_read_mem2.out[0], k_vadd.in[1]); + connect (k_vadd.out[0], k_write_mem.in[0]); + connect>(k_write_mem.out[0], m_s2.in[0]); +}; }; diff --git a/getting_started/aie_source_gmio/design/aie/add_kernel.cpp b/getting_started/aie_source_gmio/design/aie/add_kernel.cpp new file mode 100644 index 00000000..7de66c39 --- /dev/null +++ b/getting_started/aie_source_gmio/design/aie/add_kernel.cpp @@ -0,0 +1,17 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +// Includes +#include "add_kernel.h" +#include "common.h" + +void add_kernel( + input_stream* stream_in1, + input_stream* stream_in2, + output_stream* stream_out) { + + for (int i = 0; i < DATA_NUM; i++) { + writeincr(stream_out, readincr(stream_in1) + readincr(stream_in2)); + } +} diff --git a/getting_started/aie_source_gmio/design/aie/add_kernel.h b/getting_started/aie_source_gmio/design/aie/add_kernel.h new file mode 100644 index 00000000..bb8cb0f2 --- /dev/null +++ b/getting_started/aie_source_gmio/design/aie/add_kernel.h @@ -0,0 +1,8 @@ +#pragma once +#include + +void add_kernel( + input_stream* stream_in1, + input_stream* stream_in2, + output_stream* stream_out +); diff --git a/getting_started/aie_source_gmio/design/aie/common.h b/getting_started/aie_source_gmio/design/aie/common.h new file mode 100644 index 00000000..b046147c --- /dev/null +++ b/getting_started/aie_source_gmio/design/aie/common.h @@ -0,0 +1,14 @@ + +#pragma once +#include +#include + +#define DATA_NUM 256 + +// size of data in bytes +// uint32 is 4 bytes +#define DATA_SIZE (DATA_NUM*4) +#define OCCUPANCY (0.9) +#define STARTCOL (0) +#define STARTROW (0) +#define MAXCOL (50) diff --git a/getting_started/aie_source_gmio/design/aie/read_mem.cpp b/getting_started/aie_source_gmio/design/aie/read_mem.cpp new file mode 100644 index 00000000..190e5583 --- /dev/null +++ b/getting_started/aie_source_gmio/design/aie/read_mem.cpp @@ -0,0 +1,16 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +// Includes +#include "read_mem.h" +#include "common.h" + +void read_mem( + input_window* restrict mem_in, + output_stream* stream_out) { + + for (int i = 0; i < DATA_NUM; i++) { + writeincr(stream_out, window_readincr(mem_in)); + } +} diff --git a/getting_started/aie_source_gmio/design/aie/read_mem.h b/getting_started/aie_source_gmio/design/aie/read_mem.h new file mode 100644 index 00000000..fe52314e --- /dev/null +++ b/getting_started/aie_source_gmio/design/aie/read_mem.h @@ -0,0 +1,7 @@ +#pragma once +#include + +void read_mem( + input_window* restrict mem_in, + output_stream* stream_out +); diff --git a/getting_started/aie_source_gmio/design/aie/weighted_sum.cc b/getting_started/aie_source_gmio/design/aie/weighted_sum.cc new file mode 100644 index 00000000..919b6732 --- /dev/null +++ b/getting_started/aie_source_gmio/design/aie/weighted_sum.cc @@ -0,0 +1,16 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +// Includes +#include "weighted_sum.h" + +void weighted_sum( + input_window* restrict mem_in, + output_window* mem_out) { + + uint32 sum = 0; + for (int i = 0; i < 256; i++) { + window_writeincr(mem_out, window_readincr(mem_in)+1); + } +} diff --git a/getting_started/aie_source_gmio/design/aie/weighted_sum.h b/getting_started/aie_source_gmio/design/aie/weighted_sum.h new file mode 100644 index 00000000..3d75139f --- /dev/null +++ b/getting_started/aie_source_gmio/design/aie/weighted_sum.h @@ -0,0 +1,6 @@ +#pragma once +#include + +void weighted_sum( + input_window* restrict mem_in, + output_window* mem_out); diff --git a/getting_started/aie_source_gmio/design/aie/write_mem.cpp b/getting_started/aie_source_gmio/design/aie/write_mem.cpp new file mode 100644 index 00000000..e13b54c2 --- /dev/null +++ b/getting_started/aie_source_gmio/design/aie/write_mem.cpp @@ -0,0 +1,17 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +// Includes +#include "write_mem.h" +#include "common.h" + +void write_mem( + input_stream* stream_in, + output_window* restrict mem_out +) { + + for (int i = 0; i < DATA_NUM; i++) { + window_writeincr(mem_out, readincr(stream_in)); + } +} diff --git a/getting_started/aie_source_gmio/design/aie/write_mem.h b/getting_started/aie_source_gmio/design/aie/write_mem.h new file mode 100644 index 00000000..b73c0261 --- /dev/null +++ b/getting_started/aie_source_gmio/design/aie/write_mem.h @@ -0,0 +1,7 @@ +#pragma once +#include + +void write_mem( + input_stream* stream_in, + output_window* restrict mem_out +); diff --git a/getting_started/aie_source_gmio/design/config/run_u55c.py/floorplan_config.json b/getting_started/aie_source_gmio/design/config/run_u55c.py/floorplan_config.json new file mode 100644 index 00000000..d4e0f55d --- /dev/null +++ b/getting_started/aie_source_gmio/design/config/run_u55c.py/floorplan_config.json @@ -0,0 +1,14 @@ +{ + "dse_range_max": 0.8, + "dse_range_min": 0.7, + "partition_strategy": "flat", + "port_pre_assignments": { + ".*mem_in1_.*": "HBM[16]", + ".*mem_in2_.*": "HBM[17]", + ".*mem_out_.*": "HBM[18]", + "ap_clk": "CLK_RST", + "ap_rst_n": "CLK_RST", + "interrupt": "CLK_RST", + "s_axi_control_.*": "S_AXI_CONTROL" + } +} diff --git a/getting_started/aie_source_gmio/design/config/run_u55c.py/impl_config.json b/getting_started/aie_source_gmio/design/config/run_u55c.py/impl_config.json new file mode 100644 index 00000000..3c481977 --- /dev/null +++ b/getting_started/aie_source_gmio/design/config/run_u55c.py/impl_config.json @@ -0,0 +1,7 @@ +{ + "max_workers": 2, + "port_to_clock_period": { + "ap_clk": 3.33 + }, + "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1" +} diff --git a/getting_started/aie_source_gmio/design/config/run_u55c.py/link_config.ini b/getting_started/aie_source_gmio/design/config/run_u55c.py/link_config.ini new file mode 100644 index 00000000..c1298b0b --- /dev/null +++ b/getting_started/aie_source_gmio/design/config/run_u55c.py/link_config.ini @@ -0,0 +1,4 @@ +[connectivity] +sp=VecAdd.mem_in1:HBM[16] +sp=VecAdd.mem_in2:HBM[17] +sp=VecAdd.mem_out:HBM[18] diff --git a/getting_started/aie_source_gmio/design/main.cpp b/getting_started/aie_source_gmio/design/main.cpp new file mode 100644 index 00000000..90279e0a --- /dev/null +++ b/getting_started/aie_source_gmio/design/main.cpp @@ -0,0 +1,49 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +#include +#include +#include +#include +#include + +#include +#include + +using std::clog; +using std::endl; +using std::vector; + +#define DATA_NUM 4096 + +void VecAdd(tapa::mmap mem_in1, tapa::mmap mem_in2, tapa::mmap mem_out); +DEFINE_string(bitstream, "", "path to bitstream file, run csim if empty"); + +int main(int argc, char **argv) +{ + vector mem_in1(DATA_NUM); + vector mem_in2(DATA_NUM); + vector mem_out(DATA_NUM); + vector out_golden(DATA_NUM); + + for(int i=0; i(rand() % DATA_NUM); + mem_in2[i] = static_cast(rand() % DATA_NUM); + out_golden[i] = mem_in1[i] + mem_in2[i]; + } + + int64_t kernel_time_ns = tapa::invoke( + VecAdd, FLAGS_bitstream, tapa::read_only_mmap(mem_in1), + tapa::read_only_mmap(mem_in2), tapa::write_only_mmap(mem_out)); + + for(int i=0; i +VP1552 Layout ## Tutorial diff --git a/getting_started/device_factory_vitis_platform/README.md b/getting_started/device_factory_vitis_platform/README.md index dd54e2f1..78c47aa1 100644 --- a/getting_started/device_factory_vitis_platform/README.md +++ b/getting_started/device_factory_vitis_platform/README.md @@ -79,7 +79,7 @@ For this setup, we define 8 slots for the virtual device based on units of clock device = factory.generate_virtual_device() ``` -RapidStream Logo +u250 virtual device ## Tutorial Run command to extract resources of each slot of the platform: diff --git a/getting_started/mixed_sources/README.md b/getting_started/mixed_sources/README.md index f76d186d..9f9242bf 100644 --- a/getting_started/mixed_sources/README.md +++ b/getting_started/mixed_sources/README.md @@ -117,7 +117,7 @@ make hls You can find the HLS-generated Verilog files under `build` for different kernels. The interface information is automatically inferred from the HLS reports, such as -`./build/kernel_add/solution/syn/report/kernel_add_csynth.rpt` +`./build/run.py/kernel_add/solution/syn/report/kernel_add_csynth.rpt` This liminates the need for manual pragma additions to the RTL files. For instance, `stream_*` interfaces with HLS `axis` protocols will be inferred as handshake interfaces. RapidStream uses `.xml` files instead of `.rpt` files for this purpose. The `.rpt` screenshot here is for a readable demonstration purpose: @@ -209,7 +209,7 @@ When execution is completed, we found the target modules are assigned to target The final OoC implementation layout is as below. -U50 Partitioning Scheme +U50 Partitioning Scheme ### Step 3: Check the Group Module Report @@ -237,25 +237,22 @@ The module types for your design can be found in `build/module_types.csv`. Below |:--------------------------------:|:--------------:| | VecAddMix | grouped_module | |__rs_ap_ctrl_start_ready_pipeline | grouped_module | -|__rs_ff_pipeline | grouped_module | -|__rs_hs_pipeline | grouped_module | - ### Step 4: Check results The RapidStream flow performs design space exploration and creates optimized design checkpoint (`.dcp`) files. If you execution is successful, you should find the post-routed dcp located at: ```bash -build/dse/candidate_0/route.dcp +build/run.py/dse/candidate_0/route.dcp ``` To review the timing results for each generated design point, use this command: ```bash -find ./build/dse -name timing_summary.rpt +find build/run.py/dse -name timing_summary.rpt ``` -These commands will help you locate and analyze the relevant files within the `./build/dse` directory. +These commands will help you locate and analyze the relevant files within the `./build/run.py/dse` directory. ## Next Step diff --git a/getting_started/tapa_aie_source/Makefile b/getting_started/tapa_aie_source/Makefile new file mode 100644 index 00000000..95830c59 --- /dev/null +++ b/getting_started/tapa_aie_source/Makefile @@ -0,0 +1,138 @@ +# Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +# The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. + +ROOT_DIR := $(shell git rev-parse --show-toplevel) +#/opt/xilinx/platforms/xilinx_vck5000_gen4x8_qdma_2_202220_1/xilinx_vck5000_gen4x8_qdma_2_202220_1.xpfm +PART_NUM := xcu280-fsvh2892-2L-e +PLATFORM := xilinx_vck5000_gen4x8_qdma_2_202220_1 +PLATFORM_REPO_PATHS := /opt/xilinx/platforms +XPFM_FILE := $(PLATFORM_REPO_PATHS)/$(PLATFORM)/$(PLATFORM).xpfm +GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py +KERNEL_NAME := VecAdd +RS_SCRIPT := $(CURDIR)/run_u55c.py +SRC_DIR := $(CURDIR)/design +AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json +IMPL_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json +LINK_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini +FIX_NOC_TCL := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/fix_noc.tcl +TARGET := hw +TEMP_DIR := $(CURDIR)/build/$(notdir $(RS_SCRIPT)) +KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo +KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin +RS_XCLBIN := $(TEMP_DIR)/dse/solution_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin +INCLUDE := -I $(XILINX_HLS)/include +CFLAGS := $(INCLUDE) $(OPT_LEVEL) +CXX := g++ +HOST := app.exe +RS_TARGET := $(TEMP_DIR)/dse/solution_0/updated.xo +TIMING_RPT := impl_1_hw_bb_locked_timing_summary_routed.rpt +SUCCESS := "Build Successful" +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +BUILD_LOG := $(TEMP_DIR)/build.json +RSXX := rapidstream +RSPATH := $(CURDIR) +RSPYTHON := rapidstream +DEVICE_CONFIG := $(TEMP_DIR)/device.json +AIE_OBJ := $(TEMP_DIR)/libadf.a +AXX := aiecompiler + +all:clean $(KERNEL_XO) + +all1: $(RS_XCLBIN) + $(RSXX) $(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG) -c clk_kernel_00_unbuffered_net -p 3.333 + echo $(SUCCESS) + +$(RS_XCLBIN): $(RS_TARGET) + v++ -l -t ${TARGET} \ + --platform $(PLATFORM) \ + --kernel $(KERNEL_NAME) \ + --connectivity.nk $(KERNEL_NAME):1:$(KERNEL_NAME) \ + --config $(LINK_CONFIG) \ + --temp_dir $(TEMP_DIR) \ + -o $@ \ + $^ + +$(RS_TARGET):$(KERNEL_XO) $(DEVICE_CONFIG) $(AB_CONFIG) + mkdir -p $(TEMP_DIR) + cd $(RSPATH) && $(RSXX)-tapaopt \ + --work-dir $(TEMP_DIR) \ + --tapa-xo-path $< \ + --device-config $(DEVICE_CONFIG) \ + --floorplan-config $(AB_CONFIG) \ + --implementation-config $(IMPL_CONFIG) \ + --connectivity-ini $(LINK_CONFIG) + +device: $(DEVICE_CONFIG) + +$(DEVICE_CONFIG):$(RS_SCRIPT) + mkdir -p $(TEMP_DIR) + cd $(RSPATH) && $(RSPYTHON) $(RS_SCRIPT) + +hw: $(KERNEL_XCLBIN) + +$(KERNEL_XCLBIN): $(KERNEL_XO) + v++ -l -t ${TARGET} \ + --platform $(PLATFORM) \ + --kernel $(KERNEL_NAME) \ + --connectivity.nk $(KERNEL_NAME):1:$(KERNEL_NAME) \ + --config $(LINK_CONFIG) \ + --temp_dir $(TEMP_DIR) \ + -o $@ \ + $^ + +xo:$(KERNEL_XO) + +#-o $(KERNEL_NAME).xo +# + +#--flow-type pl \ +# --flow-type aie \ + +$(KERNEL_XO):$(SRC_DIR)/$(KERNEL_NAME).cpp + mkdir -p $(TEMP_DIR) + cd $(TEMP_DIR) && tapa compile \ + --top $(KERNEL_NAME) \ + --platform $(PLATFORM) \ + --flow-type aie \ + --clock-period 3.33 \ + --keep-hls-work-dir \ + -f $< \ + 2>&1 | tee tapa.log + +csim:$(TEMP_DIR)/main.exe + $(TEMP_DIR)/main.exe + +$(TEMP_DIR)/main.exe: $(SRC_DIR)/main.cpp $(SRC_DIR)/VecAdd.cpp + mkdir -p $(TEMP_DIR) + cd $(TEMP_DIR) && tapa g++ $^ $(INCLUDE) -o $@ -O2 + + +show_groups: + @echo $(RS_KERNEL_XCLBIN) + $(RSXX) $(GRP_UTIL) -i $(TEMP_DIR)/passes/1-importer.json \ + -o $(TEMP_DIR)/module_types.csv + +cp: + @cp $(CURDIR)/../aie_source_gmio/design/aie/*.h $(TEMP_DIR)/work.out/cpp/ + @mv $(TEMP_DIR)/work.out/cpp/VecAdd.cpp $(TEMP_DIR)/work.out/cpp/VecAdd.h + @cp $(CURDIR)/../aie_source_gmio/design/aie/VecAdd.cpp $(TEMP_DIR)/work.out/cpp/ + @echo "Copied files" + +aie_compile:$(AIE_OBJ) + +$(AIE_OBJ): $(TEMP_DIR)/work.out/cpp/* + @mkdir -p $(TEMP_DIR)/Work + @cd $(TEMP_DIR) && $(AXX) \ + --target=$(TARGET) \ + --platform=$(XPFM_FILE) \ + --include="$(TEMP_DIR)/work.out/cpp" \ + --workdir=$(TEMP_DIR)/Work \ + $(TEMP_DIR)/work.out/cpp/VecAdd.cpp + + +clean: + rm -rf $(TEMP_DIR) *.log + rm -rf build + rm -rf .Xil .run + rm -rf *.exe + rm -rf .ipcache diff --git a/getting_started/tapa_aie_source/README.md b/getting_started/tapa_aie_source/README.md new file mode 100644 index 00000000..6dcfef6f --- /dev/null +++ b/getting_started/tapa_aie_source/README.md @@ -0,0 +1,199 @@ + + +RapidStream Logo + +# TAPA Design + +## Introduction + +Rapidsteam is fully compatible with [TAPA](https://github.com/rapidstream-org/rapidstream-tapa). +In this recipe, we illustrate how to create a Xilinx objective file (`.xo`) using TAPA, then optimize the `.xo` file with Rapidstream, and finally utilize the optimized output in the ongoing Vitis development process. + + +## Xilinx Object Files + +[Vitis compiled object files (`.xo`)](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Design-Topology) are IP packages used in the AMD Vitis kernel development flow for programming the programmable logic (PL) region of target devices. These files can be [generated from HLS C++ code](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Developing-PL-Kernels-using-C) using the `v++` command, [packed from RTL code](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/RTL-Kernel-Development-Flow), or created using third-party frameworks like [RapidStream TAPA](https://github.com/rapidstream-org/rapidstream-tapa). In this example, we use `RapidStream TAPA` to generate the `VecAdd.xo` file, but the same flow applies to object files generated through other methods. + + +## Tutorial + +### Step 1: C++ Simulation + +Since our +design calls Xilinx Libraries, we need to source the Vitis environment before running the simulation. + +```bash +source /Vitis/2023.2/settings64.sh +``` + +Before generating the `.xo` file, we recommend running a C++ simulation to verify the correctness of the design. This step is optional but highly recommended. Run the following command or `make csim` to perform C++ simulation: + +```bash +tapa g++ design/main.cpp design/VecAdd.cpp \ +-I /opt/tools/xilinx/Vitis_HLS/2023.2/include \ +-o build/run_u55c.py/main.exe -O2 +./build/run_u55c.py/main.exe +``` + +Your should see the following output: + +```bash +I20241010 15:14:52.494259 4113880 task.h:66] running software simulation with TAPA library +kernel time: 0.0197967 s +PASS! +``` + +### Step 2: Generate the Xilinx Object File (`.xo`) + +We use TAPA on top of 2023.2 to generate the `.xo` file. Run the following command or run `make xo`: + +```bash +source /Vitis/2023.2/settings64.sh +mkdir -p build/run_u55c.py +cd build/run_u55c.py && tapa compile \ +--top VecAdd \ +--part-num xcu280-fsvh2892-2L-e \ +--clock-period 3.33 \ +-o VecAdd.xo \ +-f design/VecAdd.cpp \ +2>&1 | tee tapa.log +``` + +### Step 3 (Optional): Use Vitis --link to Generate the `.xclbin` File + +With the `.xo` file generated, you can use `v++ -link` to generate the `.xclbin` file. Run the following command or execute `make hw`: + +```bash +v++ -l -t hw \ + --platform xilinx_u280_gen3x16_xdma_1_202211_1 \ + --kernel VecAdd \ + --connectivity.nk VecAdd:1:VecAdd \ + --config design/link_config.ini \ + --temp_dir build \ + -o build/VecAdd.xclbin \ + build/VecAdd.xo +``` + +If your machines is equipped with the target FPGA device, you can deploy the optimized design on the FPGA by running the following command: + +```bash +./app.exe +``` + +:warning: **Note**: This step can take hours to complete. We recommend using the RapidStream flow to optimize the `.xo` file instead of generating the `.xclbin` file if you are familiar with AMD Vitis flow. + + +### Step 4: Define Virtual Device + +In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each +containing 16 clock regions of logic. In actual implementations, the available slots are reduced + based on the platform specifics, as some resources are reserved for shell logic. + +AU55C Device + +To generate a `device.json` file that details the device features, such as slot resources and + locations, you can either run the `run_u55c.py` script by invoking RapidStream as shown below or + simply enter `make device` in the terminal. + +```bash +rapidstream run_u55c.py +``` + + +### Step 5: Use Rapidstream to Optimize `.xo` Design + +The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. +The RapidStream flow for TAPA requires the following key inputs: + +- **tapa-xo-path**: The path to the tapa-generated `xo` file (VecAdd.xo). +- **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is +the same for vitis link configure file. + +We encapulate the rapidstream command for TAPA as `rapidstream-tapaop` for invoking. +You can run the command below or execute `make all` supported by our [Makefile](Makefile). + +```bash +rapidstream-tapaopt --work-dir build/run_u55c.py \ + --tapa-xo-path ./VecAdd.xo \ + --device-config build/run_u55c.py/device.json \ + --floorplan-config ../../design/config/run_u55c.py/ab_config.json \ + --implementation-config ../../ design/config/run_u55c.py/impl_config.json \ + --connectivity-ini ../../design/config/run_u55c.py/link_config.ini +``` + +When finished, you can locate these files using the following command: + +```bash +find ./build/run_u55c.py/ -name *.xo +``` + +If everything is successful, you should at least get one optimized `.xo` file located in `./build/dse/candidate_0/exported/VecAdd.xo`. + +### Step 7: Check the Group Module Report + + +RapidStream mandates a clear distinction between communication and computation within user designs. + +- In `Group modules`, users are tasked solely with defining inter-submodule communication. For those familiar with Vivado IP Integrator flow, crafting a Group module mirrors the process of connecting IPs in IPI. RapidStream subsequently integrates appropriate pipeline registers into these Group modules. + +- In `Leaf modules`, users retain the flexibility to implement diverse computational patterns, as RapidStream leaves these Leaf modules unchanged. + +For further details, please consult the [code style](https://docs.rapidstream-da.com/required-coding-style/) section in our Documentation. + +To generate a report on group types, execute the commands below or `run make show_groups`: + +```bash +rapidstream ../../common/util/get_group.py \ + -i build/passes/0-imported.json \ + -o build/module_types.csv +``` + +The module types for your design can be found in `build/module_types.csv`. Below, we list the four Group modules. In this design, `VecAdd` serves as a Group module, while the other three modules are added by RapidStream. + +| Module Name | Group Type | +|:--------------------------------:|:--------------:| +| VecAdd | grouped_module | +| __rs_VecAdd_aux | aux_module | +| ... | verilog_module | + + +### Step 8: Use Vitis --link with the Optimized `.xo` File + +With the optimized `.xo` file generated, you can use `v++ -link` to generate the `.xclbin` file. Run the following command or run `make`: + +```bash +v++ -l -t hw \ + --platform xilinx_u280_gen3x16_xdma_1_202211_1 \ + --kernel VecAdd \ + --connectivity.nk VecAdd:1:VecAdd \ + --config design/link_config.ini \ + --temp_dir build/rapidstream \ + -o build/VecAdd_rs_opt.xclbin \ + ./build/dse/candidate_0/exported/VecAdd.xo +``` + + +To examine the timing results for each design point, use this command: + +```bash +find ./build -name *.xclbin.info +``` + + + +If your machines is equipped with the target FPGA device, you can deploy the optimized design on the FPGA by running the following command: + +```bash +make host +./app.exe +``` + +## Next Step + + **Click here to [go back to Getting Started](../README.md)** diff --git a/getting_started/tapa_aie_source/design/VecAdd.cpp b/getting_started/tapa_aie_source/design/VecAdd.cpp new file mode 100644 index 00000000..e00b3cff --- /dev/null +++ b/getting_started/tapa_aie_source/design/VecAdd.cpp @@ -0,0 +1,49 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +// Includes +#include +#include +#define DATA_NUM 4096 + +[[tapa::target("aie", "xilinx")]] void read_mem(tapa::mmap f, tapa::ostream& g) { + + for (int i = 0; i < DATA_NUM; i++) { + g << f[i]; + } +} + + +[[tapa::target("aie", "xilinx")]] void +add_kernel(tapa::istream& a, + tapa::istream& b, + tapa::ostream& c) { + + // Compute the addition + [[tapa::pipeline(1)]] for (int i = 0; i < DATA_NUM; i++) { + c.write(a.read() + b.read()); + } +} + +[[tapa::target("aie", "xilinx")]] void write_mem(tapa::istream& d, tapa::mmape) { + + for (int i = 0; i < DATA_NUM; i++) { + d >> e[i]; + } +} + + +[[tapa::target("aie", "xilinx")]] void VecAdd(tapa::mmap mem_in1, tapa::mmap mem_in2, tapa::mmap mem_out) { + + tapa::stream stream_in1("input_stream_1"); + tapa::stream stream_in2("input_stream_2"); + tapa::stream stream_out("output_stream"); + + tapa::task() + .invoke(read_mem, mem_in1, stream_in1) + .invoke(read_mem, mem_in2, stream_in2) + .invoke(add_kernel, stream_in1, stream_in2, stream_out) + .invoke(write_mem, stream_out, mem_out); + +} diff --git a/getting_started/tapa_aie_source/design/config/run_u55c.py/floorplan_config.json b/getting_started/tapa_aie_source/design/config/run_u55c.py/floorplan_config.json new file mode 100644 index 00000000..d4e0f55d --- /dev/null +++ b/getting_started/tapa_aie_source/design/config/run_u55c.py/floorplan_config.json @@ -0,0 +1,14 @@ +{ + "dse_range_max": 0.8, + "dse_range_min": 0.7, + "partition_strategy": "flat", + "port_pre_assignments": { + ".*mem_in1_.*": "HBM[16]", + ".*mem_in2_.*": "HBM[17]", + ".*mem_out_.*": "HBM[18]", + "ap_clk": "CLK_RST", + "ap_rst_n": "CLK_RST", + "interrupt": "CLK_RST", + "s_axi_control_.*": "S_AXI_CONTROL" + } +} diff --git a/getting_started/tapa_aie_source/design/config/run_u55c.py/impl_config.json b/getting_started/tapa_aie_source/design/config/run_u55c.py/impl_config.json new file mode 100644 index 00000000..3c481977 --- /dev/null +++ b/getting_started/tapa_aie_source/design/config/run_u55c.py/impl_config.json @@ -0,0 +1,7 @@ +{ + "max_workers": 2, + "port_to_clock_period": { + "ap_clk": 3.33 + }, + "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1" +} diff --git a/getting_started/tapa_aie_source/design/config/run_u55c.py/link_config.ini b/getting_started/tapa_aie_source/design/config/run_u55c.py/link_config.ini new file mode 100644 index 00000000..c1298b0b --- /dev/null +++ b/getting_started/tapa_aie_source/design/config/run_u55c.py/link_config.ini @@ -0,0 +1,4 @@ +[connectivity] +sp=VecAdd.mem_in1:HBM[16] +sp=VecAdd.mem_in2:HBM[17] +sp=VecAdd.mem_out:HBM[18] diff --git a/getting_started/tapa_aie_source/design/main.cpp b/getting_started/tapa_aie_source/design/main.cpp new file mode 100644 index 00000000..90279e0a --- /dev/null +++ b/getting_started/tapa_aie_source/design/main.cpp @@ -0,0 +1,49 @@ +// Copyright 2024 RapidStream Design Automation, Inc. +// All Rights Reserved. + + +#include +#include +#include +#include +#include + +#include +#include + +using std::clog; +using std::endl; +using std::vector; + +#define DATA_NUM 4096 + +void VecAdd(tapa::mmap mem_in1, tapa::mmap mem_in2, tapa::mmap mem_out); +DEFINE_string(bitstream, "", "path to bitstream file, run csim if empty"); + +int main(int argc, char **argv) +{ + vector mem_in1(DATA_NUM); + vector mem_in2(DATA_NUM); + vector mem_out(DATA_NUM); + vector out_golden(DATA_NUM); + + for(int i=0; i(rand() % DATA_NUM); + mem_in2[i] = static_cast(rand() % DATA_NUM); + out_golden[i] = mem_in1[i] + mem_in2[i]; + } + + int64_t kernel_time_ns = tapa::invoke( + VecAdd, FLAGS_bitstream, tapa::read_only_mmap(mem_in1), + tapa::read_only_mmap(mem_in2), tapa::write_only_mmap(mem_out)); + + for(int i=0; i /* clang -E -fkeep-system-includes */ + +#include /* clang -E -fkeep-system-includes */ +[[tapa::target("aie", "xilinx")]] void read_mem(tapa::mmap f, + tapa::ostream &g) { + for (int i = 0; i < 4096; i++) { + g << f[i]; + } +} +[[tapa::target("aie", "xilinx")]] void add_kernel(tapa::istream &a, + tapa::istream &b, + tapa::ostream &c) { + // Compute the addition + [[tapa::pipeline(1)]] for (int i = 0; i < 4096; i++) { + c << (a.read() + b.read()); + } +} +[[tapa::target("aie", "xilinx")]] void write_mem(tapa::istream &d, + tapa::mmap e) { + for (int i = 0; i < 4096; i++) { + d >> e[i]; + } +} +[[tapa::target("aie", "xilinx")]] void +VecAdd(tapa::mmap mem_in1, tapa::mmap mem_in2, + tapa::mmap mem_out) { + tapa::stream stream_in1("input_stream_1"); + tapa::stream stream_in2("input_stream_2"); + tapa::stream stream_out("output_stream"); + tapa::task() + .invoke(read_mem, mem_in1, stream_in1) + .invoke(read_mem, mem_in2, stream_in2) + .invoke(add_kernel, stream_in1, stream_in2, stream_out) + .invoke(write_mem, stream_out, mem_out); +} diff --git a/getting_started/tapa_aie_source/run_u55c.py b/getting_started/tapa_aie_source/run_u55c.py new file mode 100644 index 00000000..8ea706e5 --- /dev/null +++ b/getting_started/tapa_aie_source/run_u55c.py @@ -0,0 +1,42 @@ +__copyright__ = """ +Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. +The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. +""" + +from rapidstream import get_u55c_vitis_device_factory +import os +from pathlib import Path + +CURR_DIR = os.path.dirname(os.path.abspath(__file__)) +CURR_FILE = os.path.basename(__file__) + +VITIS_PLATFORM = "xilinx_u55c_gen3x16_xdma_3_202210_1" +XO_PATH = f"{CURR_DIR}/design/generated/data_decoding.xo" + +factory = get_u55c_vitis_device_factory(VITIS_PLATFORM) + +# Reserve resource for the HBM Memory Sub-System. +# The HMSS is not part of the user kernel so the partition optimization process +# is unaware of its existence. We need to manually reserve resources for it. +# For 512-bit HBM channels, each HBM channel uses approximately the following resources: +# AREA_PER_HBM_CHANNEL = { +# "LUT": 5000, +# "FF": 6500, +# "BRAM": 0, +# "URAM": 0, +# "DSP": 0, +# } +factory.reduce_slot_area(0, 0, lut=150800) +factory.reduce_slot_area(0, 1, lut=146960) +factory.reduce_slot_area(0, 2, lut=146960) +factory.reduce_slot_area(1, 0, lut=128000) +factory.reduce_slot_area(1, 1, lut=107840) +factory.reduce_slot_area(1, 2, lut=115120) + + +# For this U280 platform, the right most DSP column on the boundary between +# dynamic/static region is not usable. So we need to adjust the DSP count +# to reflect the actual available DSPs. +print("Reducing DSP of (1, 1) to make it less congested") +factory.reduce_slot_area(1, 1, dsp=100) +factory.generate_virtual_device(Path(f"{CURR_DIR}/build/{CURR_FILE}/device.json")) diff --git a/getting_started/tapa_source/Makefile b/getting_started/tapa_source/Makefile index 31e0b601..1f685445 100644 --- a/getting_started/tapa_source/Makefile +++ b/getting_started/tapa_source/Makefile @@ -6,13 +6,17 @@ PLATFORM := xilinx_u280_gen3x16_xdma_1_202211_1 PART_NUM := xcu280-fsvh2892-2L-e GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py KERNEL_NAME := VecAdd -SRC_DIR := $(CURDIR)/design +RS_SCRIPT := $(CURDIR)/run_u55c.py +SRC_DIR := $(CURDIR)/design +AB_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json +IMPL_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json +LINK_CONFIG := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini +FIX_NOC_TCL := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/fix_noc.tcl TARGET := hw -RS_SCRIPT := $(CURDIR)/run.py TEMP_DIR := $(CURDIR)/build/$(notdir $(RS_SCRIPT)) KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin -RS_KERNEL_XCLBIN := $(TEMP_DIR)/dse/candidate_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin +RS_KERNEL_XCLBIN := $(TEMP_DIR)/dse/solution_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin INCLUDE := -I $(XILINX_HLS)/include CFLAGS := $(INCLUDE) $(OPT_LEVEL) CXX := g++ @@ -23,34 +27,62 @@ SUCCESS := "Build Successful" SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py BUILD_LOG := $(TEMP_DIR)/build.json RSXX := rapidstream +RSPATH := $(CURDIR) +RSPYTHON := rapidstream +DEVICE_CONFIG := $(TEMP_DIR)/device.json all: $(RS_KERNEL_XCLBIN) $(RSXX) $(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG) -c clk_kernel_00_unbuffered_net -p 3.333 echo $(SUCCESS) -$(RS_KERNEL_XCLBIN):$(SRC_DIR)/$(KERNEL_NAME).xo + +$(RS_KERNEL_XCLBIN):$(KERNEL_XO) $(DEVICE_CONFIG) $(AB_CONFIG) mkdir -p $(TEMP_DIR) - $(RSXX) $(RS_SCRIPT) + cd $(RSPATH) && $(RSXX)-tapaopt \ + --work-dir $(TEMP_DIR) \ + --tapa-xo-path $< \ + --device-config $(DEVICE_CONFIG) \ + --floorplan-config $(AB_CONFIG) \ + --implementation-config $(IMPL_CONFIG) \ + --run-impl \ + --connectivity-ini $(LINK_CONFIG) +$(DEVICE_CONFIG):$(RS_SCRIPT) + mkdir -p $(TEMP_DIR) + cd $(RSPATH) && $(RSPYTHON) $(RS_SCRIPT) -sw_emu: $(KERNEL_XCLBIN) $(HOST) - XCL_EMULATION_MODE=sw_emu ./app.exe $< +hw: $(KERNEL_XCLBIN) +$(KERNEL_XCLBIN): $(KERNEL_XO) + v++ -l -t ${TARGET} \ + --platform $(PLATFORM) \ + --kernel $(KERNEL_NAME) \ + --connectivity.nk $(KERNEL_NAME):1:$(KERNEL_NAME) \ + --config $(LINK_CONFIG) \ + --temp_dir $(TEMP_DIR) \ + -o $@ \ + $^ xo:$(KERNEL_XO) -$(KERNEL_XO): $(SRC_DIR)/$(KERNEL_NAME).cpp - tapac -o $@ $< \ +$(KERNEL_XO):$(SRC_DIR)/$(KERNEL_NAME).cpp + mkdir -p $(TEMP_DIR) + cd $(TEMP_DIR) && tapa compile \ + --top $(KERNEL_NAME) \ --part-num $(PART_NUM) \ --clock-period 3.33 \ - --top $(KERNEL_NAME) \ - --work-dir $(TEMP_DIR) + -o $(KERNEL_NAME).xo \ + -f $< \ + 2>&1 | tee tapa.log -csim:$(SRC_DIR)/main.cpp $(SRC_DIR)/VecAdd.cpp - mkdir -p $(TEMP_DIR) - $(CXX) -o $(TEMP_DIR)/main.exe -O2 $^ -ltapa -lfrt -lglog -lgflags -lOpenCL +csim:$(TEMP_DIR)/main.exe $(TEMP_DIR)/main.exe +$(TEMP_DIR)/main.exe: $(SRC_DIR)/main.cpp $(SRC_DIR)/VecAdd.cpp + mkdir -p $(TEMP_DIR) + cd $(TEMP_DIR) && tapa g++ $^ $(INCLUDE) -o $@ -O2 + + show_groups: @echo $(RS_KERNEL_XCLBIN) $(RSXX) $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \ diff --git a/getting_started/tapa_source/README.md b/getting_started/tapa_source/README.md index 34b7825d..6dcfef6f 100644 --- a/getting_started/tapa_source/README.md +++ b/getting_started/tapa_source/README.md @@ -5,22 +5,17 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L RapidStream Logo -# AMD Vitis Design +# TAPA Design ## Introduction -Rapidsteam is fully compatible with AMD Vitis by taking Vitis object files (`.xo`) as input, performing optimization and generating optimized `.xo` files as output. Therefore, users can use `v++ -link` to continue their Vitis development flow. - -rapidstream_xo.png - -In this recipe, we illustrate how to create a Vitis objective file (`.xo`) using Vitis, then optimize the `.xo` file with Rapidstream, and finally utilize the optimized output in the ongoing Vitis development process. +Rapidsteam is fully compatible with [TAPA](https://github.com/rapidstream-org/rapidstream-tapa). +In this recipe, we illustrate how to create a Xilinx objective file (`.xo`) using TAPA, then optimize the `.xo` file with Rapidstream, and finally utilize the optimized output in the ongoing Vitis development process. ## Xilinx Object Files -[Vitis compiled object files (`.xo`)](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Design-Topology) are IP packages used in the AMD Vitis kernel development flow for programming the programmable logic (PL) region of target devices. - -These files can be [generated from HLS C++ code](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Developing-PL-Kernels-using-C) using the `v++` command, [packed from RTL code](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/RTL-Kernel-Development-Flow), or created using third-party frameworks like [TAPA](https://github.com/UCLA-VAST/tapa). In this example, we use `v++` to generate the `VecAdd.xo` file, but the same flow applies to object files generated through other methods. +[Vitis compiled object files (`.xo`)](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Design-Topology) are IP packages used in the AMD Vitis kernel development flow for programming the programmable logic (PL) region of target devices. These files can be [generated from HLS C++ code](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/Developing-PL-Kernels-using-C) using the `v++` command, [packed from RTL code](https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration/RTL-Kernel-Development-Flow), or created using third-party frameworks like [RapidStream TAPA](https://github.com/rapidstream-org/rapidstream-tapa). In this example, we use `RapidStream TAPA` to generate the `VecAdd.xo` file, but the same flow applies to object files generated through other methods. ## Tutorial @@ -37,83 +32,37 @@ source /Vitis/2023.2/settings64.sh Before generating the `.xo` file, we recommend running a C++ simulation to verify the correctness of the design. This step is optional but highly recommended. Run the following command or `make csim` to perform C++ simulation: ```bash -g++ -I ${XILINX_HLS}/include ./design/VecAdd.cpp ./design/main.cpp -o main.exe -./main.exe +tapa g++ design/main.cpp design/VecAdd.cpp \ +-I /opt/tools/xilinx/Vitis_HLS/2023.2/include \ +-o build/run_u55c.py/main.exe -O2 +./build/run_u55c.py/main.exe ``` Your should see the following output: ```bash +I20241010 15:14:52.494259 4113880 task.h:66] running software simulation with TAPA library +kernel time: 0.0197967 s PASS! -INFO [HLS SIM]: The maximum depth reached by any hls::stream() instance in the design is 4096 -``` - -### Step 2: Targeting Vitis Software Emulation - -AMD Vitis provides an easy way to target software emulation for debugging and performance analysis. To target software emulation, your need to source Vitis and XRT environment setting up scripts and run the following command or run `make TARGET=sw_emu sw_emu`: - -```bash -source /Vitis/2023.2/settings64.sh -source /opt/xilinx/xrt/setup.sh - -v++ -c -t sw_emu \ - --platform xilinx_u280_gen3x16_xdma_1_202211_1 \ - -k VecAdd \ - --temp_dir build \ - -o build/VecAdd.xo \ - design/VecAdd.cpp design/VecAdd.h - -v++ -l -t sw_emu \ - --platform xilinx_u280_gen3x16_xdma_1_202211_1 \ - --kernel VecAdd \ - --connectivity.nk VecAdd:1:VecAdd \ - --config design/link_config.ini \ - --temp_dir build \ - -o build/VecAdd.xclbin \ - build/VecAdd.xo - -g++ -Wall -g -std=c++11 design/host.cpp -o app.exe \ - -I${XILINX_XRT}/include/ \ - -I${XILINX_VIVADO}/include/ \ - -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ - -XCL_EMULATION_MODE=sw_emu ./app.exe build/VecAdd.xclbin -``` - -You would see the following output: - -```bash -Trying to program device[0]: xilinx:pcie-hw-em:7v3:1.0 -Kernel Name: VecAdd, CU Number: 0, Thread creation status: success -Device[0]: xclbin is loaded successfully! -Kernel Name: VecAdd, CU Number: 0, State: Start -Kernel Name: VecAdd, CU Number: 0, State: Running -Kernel Name: VecAdd, CU Number: 0, State: Idle -TEST PASSED! -device process sw_emu_device done -Kernel Name: VecAdd, CU Number: 0, Status: Shutdown -INFO [HLS SIM]: The maximum depth reached by any hls::stream() instance in the design is 4096 ``` -:warning: **Note**: Clean the sw_emu `.xo` file before next steps by running `make clean`. - -### Step 3: Generate the Xilinx Object File (`.xo`) +### Step 2: Generate the Xilinx Object File (`.xo`) -We use Vitis 2023.2 to generate the `.xo` file. Run the following command or run `make xo`: +We use TAPA on top of 2023.2 to generate the `.xo` file. Run the following command or run `make xo`: ```bash source /Vitis/2023.2/settings64.sh -make clean -cd /getting_started/vitis_source -v++ -c -t hw \ - --platform xilinx_u280_gen3x16_xdma_1_202211_1 \ - -k VecAdd \ - --temp_dir build \ - -o build/VecAdd.xo \ - design/VecAdd.cpp design/VecAdd.h +mkdir -p build/run_u55c.py +cd build/run_u55c.py && tapa compile \ +--top VecAdd \ +--part-num xcu280-fsvh2892-2L-e \ +--clock-period 3.33 \ +-o VecAdd.xo \ +-f design/VecAdd.cpp \ +2>&1 | tee tapa.log ``` -### Step 4 (Optional): Use Vitis --link to Generate the `.xclbin` File +### Step 3 (Optional): Use Vitis --link to Generate the `.xclbin` File With the `.xo` file generated, you can use `v++ -link` to generate the `.xclbin` file. Run the following command or execute `make hw`: @@ -137,33 +86,56 @@ If your machines is equipped with the target FPGA device, you can deploy the opt :warning: **Note**: This step can take hours to complete. We recommend using the RapidStream flow to optimize the `.xo` file instead of generating the `.xclbin` file if you are familiar with AMD Vitis flow. -### Step 5: Call RapidStream to Optimize the Design +### Step 4: Define Virtual Device + +In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each +containing 16 clock regions of logic. In actual implementations, the available slots are reduced + based on the platform specifics, as some resources are reserved for shell logic. + +AU55C Device + +To generate a `device.json` file that details the device features, such as slot resources and + locations, you can either run the `run_u55c.py` script by invoking RapidStream as shown below or + simply enter `make device` in the terminal. + +```bash +rapidstream run_u55c.py +``` + + +### Step 5: Use Rapidstream to Optimize `.xo` Design -The RapidStream flow conducts design space exploration and generates optimized `.xo` files by taking the Vitis generated `.xo` as the input. The RapidStream flow for Vitis requires four key inputs: +The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. +The RapidStream flow for TAPA requires the following key inputs: -1. **Device**: Specify the Vitis platform name for `v++`. -2. **Xilinx Object file** (.xo): Provide the file generated by `v++` or Vivado. -3. **Connectivity** (.ini): Include the configuration file for `v++` ([link_config.ini](./design/link_config.ini)). -4. **Clock targets**: Define the desired clock frequencies. -5. RapidStream automatically handles all other aspects of the flow. +- **tapa-xo-path**: The path to the tapa-generated `xo` file (VecAdd.xo). +- **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform. +- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design. +- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.). +- **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is +the same for vitis link configure file. -Please refer to [run.py](./run.py) for the complete RapidStream flow. -To execute the flow and generate optimized `.xo` files, -Run the following command or execute `make rs_opt`: +We encapulate the rapidstream command for TAPA as `rapidstream-tapaop` for invoking. +You can run the command below or execute `make all` supported by our [Makefile](Makefile). ```bash -rapidstream ./run.py +rapidstream-tapaopt --work-dir build/run_u55c.py \ + --tapa-xo-path ./VecAdd.xo \ + --device-config build/run_u55c.py/device.json \ + --floorplan-config ../../design/config/run_u55c.py/ab_config.json \ + --implementation-config ../../ design/config/run_u55c.py/impl_config.json \ + --connectivity-ini ../../design/config/run_u55c.py/link_config.ini ``` When finished, you can locate these files using the following command: ```bash -find ./build/dse/ -name *.xo +find ./build/run_u55c.py/ -name *.xo ``` If everything is successful, you should at least get one optimized `.xo` file located in `./build/dse/candidate_0/exported/VecAdd.xo`. -### Step 6: Check the Group Module Report +### Step 7: Check the Group Module Report RapidStream mandates a clear distinction between communication and computation within user designs. @@ -187,12 +159,11 @@ The module types for your design can be found in `build/module_types.csv`. Below | Module Name | Group Type | |:--------------------------------:|:--------------:| | VecAdd | grouped_module | -|__rs_ap_ctrl_start_ready_pipeline | grouped_module | -|__rs_ff_pipeline | grouped_module | -|__rs_hs_pipeline | grouped_module | +| __rs_VecAdd_aux | aux_module | +| ... | verilog_module | -### Step 7: Use Vitis --link with the Optimized `.xo` File +### Step 8: Use Vitis --link with the Optimized `.xo` File With the optimized `.xo` file generated, you can use `v++ -link` to generate the `.xclbin` file. Run the following command or run `make`: diff --git a/getting_started/tapa_source/design/config/run_u55c.py/floorplan_config.json b/getting_started/tapa_source/design/config/run_u55c.py/floorplan_config.json new file mode 100644 index 00000000..d4e0f55d --- /dev/null +++ b/getting_started/tapa_source/design/config/run_u55c.py/floorplan_config.json @@ -0,0 +1,14 @@ +{ + "dse_range_max": 0.8, + "dse_range_min": 0.7, + "partition_strategy": "flat", + "port_pre_assignments": { + ".*mem_in1_.*": "HBM[16]", + ".*mem_in2_.*": "HBM[17]", + ".*mem_out_.*": "HBM[18]", + "ap_clk": "CLK_RST", + "ap_rst_n": "CLK_RST", + "interrupt": "CLK_RST", + "s_axi_control_.*": "S_AXI_CONTROL" + } +} diff --git a/getting_started/tapa_source/design/config/run_u55c.py/impl_config.json b/getting_started/tapa_source/design/config/run_u55c.py/impl_config.json new file mode 100644 index 00000000..3c481977 --- /dev/null +++ b/getting_started/tapa_source/design/config/run_u55c.py/impl_config.json @@ -0,0 +1,7 @@ +{ + "max_workers": 2, + "port_to_clock_period": { + "ap_clk": 3.33 + }, + "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1" +} diff --git a/getting_started/tapa_source/design/config/run_u55c.py/link_config.ini b/getting_started/tapa_source/design/config/run_u55c.py/link_config.ini new file mode 100644 index 00000000..c1298b0b --- /dev/null +++ b/getting_started/tapa_source/design/config/run_u55c.py/link_config.ini @@ -0,0 +1,4 @@ +[connectivity] +sp=VecAdd.mem_in1:HBM[16] +sp=VecAdd.mem_in2:HBM[17] +sp=VecAdd.mem_out:HBM[18] diff --git a/getting_started/tapa_source/design/main.cpp b/getting_started/tapa_source/design/main.cpp index b66af06f..90279e0a 100644 --- a/getting_started/tapa_source/design/main.cpp +++ b/getting_started/tapa_source/design/main.cpp @@ -15,21 +15,21 @@ using std::clog; using std::endl; using std::vector; -#define DATA_SIZE 4096 +#define DATA_NUM 4096 void VecAdd(tapa::mmap mem_in1, tapa::mmap mem_in2, tapa::mmap mem_out); DEFINE_string(bitstream, "", "path to bitstream file, run csim if empty"); int main(int argc, char **argv) { - vector mem_in1(DATA_SIZE); - vector mem_in2(DATA_SIZE); - vector mem_out(DATA_SIZE); - vector out_golden(DATA_SIZE); - - for(int i=0; i(rand() % DATA_SIZE); - mem_in2[i] = static_cast(rand() % DATA_SIZE); + vector mem_in1(DATA_NUM); + vector mem_in2(DATA_NUM); + vector mem_out(DATA_NUM); + vector out_golden(DATA_NUM); + + for(int i=0; i(rand() % DATA_NUM); + mem_in2[i] = static_cast(rand() % DATA_NUM); out_golden[i] = mem_in1[i] + mem_in2[i]; } @@ -37,7 +37,7 @@ int main(int argc, char **argv) VecAdd, FLAGS_bitstream, tapa::read_only_mmap(mem_in1), tapa::read_only_mmap(mem_in2), tapa::write_only_mmap(mem_out)); - for(int i=0; i