diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_aggregate_SPLIT.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_aggregate_SPLIT.cpp index 6495fdaf..4af28d4d 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_aggregate_SPLIT.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_aggregate_SPLIT.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_arb_forwarder.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_arb_forwarder.cpp index 8e24ee19..6de36ec0 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_arb_forwarder.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_arb_forwarder.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_arbiter_ratemonitor.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_arbiter_ratemonitor.cpp index 37bb4d41..d6f5fc93 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_arbiter_ratemonitor.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_arbiter_ratemonitor.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_hier_arbiter_atom.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_hier_arbiter_atom.cpp index 00fa65e4..c9846bf8 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_hier_arbiter_atom.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/bloom_hier_arbiter_atom.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/computeHash_Computer.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/computeHash_Computer.cpp index 448624a4..4b6e9984 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/computeHash_Computer.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/computeHash_Computer.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/computeHash_Feeder.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/computeHash_Feeder.cpp index 1c71945e..967430f9 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/computeHash_Feeder.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/computeHash_Feeder.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/loadBV.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/loadBV.cpp index fb5d0059..65c882a8 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/loadBV.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/loadBV.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/loadKey.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/loadKey.cpp index e00c09e2..f016a3f2 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/loadKey.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/loadKey.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/packOutput.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/packOutput.cpp index 1f865cc8..1c1a80f7 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/packOutput.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/packOutput.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/queryResult_per_hash.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/queryResult_per_hash.cpp index fab9dcbe..4d409aa1 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/queryResult_per_hash.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/queryResult_per_hash.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/shuffle_TtoS_per_hash.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/shuffle_TtoS_per_hash.cpp index 7e59d47b..72af4adb 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/shuffle_TtoS_per_hash.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/shuffle_TtoS_per_hash.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/shuffle_reordering_per_hash.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/shuffle_reordering_per_hash.cpp index a2be7479..588a927c 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/shuffle_reordering_per_hash.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/shuffle_reordering_per_hash.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/workload.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/workload.cpp index 58908f1b..6891694f 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/workload.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/workload.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/writeOutput_synchronous.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/writeOutput_synchronous.cpp index 2905acac..70b90b1a 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/writeOutput_synchronous.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/cpp/writeOutput_synchronous.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/flatten/flatten-bca92fa8-multistream_MurmurHash3.cpp b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/flatten/flatten-d2a06f17-multistream_MurmurHash3.cpp similarity index 98% rename from benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/flatten/flatten-bca92fa8-multistream_MurmurHash3.cpp rename to benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/flatten/flatten-d2a06f17-multistream_MurmurHash3.cpp index 26df122c..c6f8127f 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/flatten/flatten-bca92fa8-multistream_MurmurHash3.cpp +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/flatten/flatten-d2a06f17-multistream_MurmurHash3.cpp @@ -65,7 +65,7 @@ typedef struct { } PACKED_HASH_DTYPE; /************************/ const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/; - const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; + const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_; typedef struct { ap_uint<(32)> s0_k0; ap_uint<(32)> s0_k1; @@ -111,7 +111,7 @@ typedef struct { /* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO. * So that FIFO will get filled, and the shuffle unit wont be able to handle it. * We need at least NUM_STM FIFO elements between arbiter and shuffle. */ -const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; +const int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1; const int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram) const int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5); const int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1); diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/graph.json b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/graph.json index 906141cb..17aece16 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/graph.json +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/graph.json @@ -8,79 +8,79 @@ ], "tasks": { "bloom_aggregate_SPLIT": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n){\n\n\n#pragma HLS disaggregate variable = reconstruct_stream\n#pragma HLS array_partition variable = reconstruct_stream complete\n#pragma HLS interface ap_fifo port = reconstruct_stream[0]._\n#pragma HLS aggregate variable = reconstruct_stream[0]._ bit\n#pragma HLS interface ap_fifo port = reconstruct_stream[0]._peek\n#pragma HLS aggregate variable = reconstruct_stream[0]._peek bit\nvoid(reconstruct_stream[0]._.empty());\nvoid(reconstruct_stream[0]._peek.empty());\n#pragma HLS interface ap_fifo port = reconstruct_stream[1]._\n#pragma HLS aggregate variable = reconstruct_stream[1]._ bit\n#pragma HLS interface ap_fifo port = reconstruct_stream[1]._peek\n#pragma HLS aggregate variable = reconstruct_stream[1]._peek bit\nvoid(reconstruct_stream[1]._.empty());\nvoid(reconstruct_stream[1]._peek.empty());\n#pragma HLS interface ap_fifo port = reconstruct_stream[2]._\n#pragma HLS aggregate variable = reconstruct_stream[2]._ bit\n#pragma HLS interface ap_fifo port = reconstruct_stream[2]._peek\n#pragma HLS aggregate variable = reconstruct_stream[2]._peek bit\nvoid(reconstruct_stream[2]._.empty());\nvoid(reconstruct_stream[2]._peek.empty());\n\n#pragma HLS disaggregate variable = aggregate_stream\n#pragma HLS interface ap_fifo port = aggregate_stream._\n#pragma HLS aggregate variable = aggregate_stream._ bit\nvoid(aggregate_stream._.full());\n\n int num_writes_TOTAL = 0;\n int num_reads = 0;\n int all_hashes_available = 0;\n uint32_t result = 1;\n while (num_writes_TOTAL < KEYPAIRS_PER_STM)\n {\n#pragma HLS PIPELINE=1\n // Check if all of our hash values are available:\n all_hashes_available = 1;\n for (int i = 0; i < (3); ++i) {\n if (reconstruct_stream[i].empty()) {\n all_hashes_available = 0;\n }\n }\n if (all_hashes_available)\n {\n result = 1;\n for (int i = 0; i < (3); ++i) {\n result &= reconstruct_stream[i].read();\n }\n num_reads++;\n aggregate_stream.write(result);\n num_writes_TOTAL++;\n }\n }\n return;\n}\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n){\n\n\n#pragma HLS disaggregate variable = reconstruct_stream\n#pragma HLS array_partition variable = reconstruct_stream complete\n#pragma HLS interface ap_fifo port = reconstruct_stream[0]._\n#pragma HLS aggregate variable = reconstruct_stream[0]._ bit\n#pragma HLS interface ap_fifo port = reconstruct_stream[0]._peek\n#pragma HLS aggregate variable = reconstruct_stream[0]._peek bit\nvoid(reconstruct_stream[0]._.empty());\nvoid(reconstruct_stream[0]._peek.empty());\n#pragma HLS interface ap_fifo port = reconstruct_stream[1]._\n#pragma HLS aggregate variable = reconstruct_stream[1]._ bit\n#pragma HLS interface ap_fifo port = reconstruct_stream[1]._peek\n#pragma HLS aggregate variable = reconstruct_stream[1]._peek bit\nvoid(reconstruct_stream[1]._.empty());\nvoid(reconstruct_stream[1]._peek.empty());\n#pragma HLS interface ap_fifo port = reconstruct_stream[2]._\n#pragma HLS aggregate variable = reconstruct_stream[2]._ bit\n#pragma HLS interface ap_fifo port = reconstruct_stream[2]._peek\n#pragma HLS aggregate variable = reconstruct_stream[2]._peek bit\nvoid(reconstruct_stream[2]._.empty());\nvoid(reconstruct_stream[2]._peek.empty());\n\n#pragma HLS disaggregate variable = aggregate_stream\n#pragma HLS interface ap_fifo port = aggregate_stream._\n#pragma HLS aggregate variable = aggregate_stream._ bit\nvoid(aggregate_stream._.full());\n\n int num_writes_TOTAL = 0;\n int num_reads = 0;\n int all_hashes_available = 0;\n uint32_t result = 1;\n while (num_writes_TOTAL < KEYPAIRS_PER_STM)\n {\n#pragma HLS PIPELINE=1\n // Check if all of our hash values are available:\n all_hashes_available = 1;\n for (int i = 0; i < (3); ++i) {\n if (reconstruct_stream[i].empty()) {\n all_hashes_available = 0;\n }\n }\n if (all_hashes_available)\n {\n result = 1;\n for (int i = 0; i < (3); ++i) {\n result &= reconstruct_stream[i].read();\n }\n num_reads++;\n aggregate_stream.write(result);\n num_writes_TOTAL++;\n }\n }\n return;\n}\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "bloom_arb_forwarder": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n){\n\n\n#pragma HLS disaggregate variable = hash_stream\n#pragma HLS array_partition variable = hash_stream complete\n#pragma HLS interface ap_fifo port = hash_stream[0]._\n#pragma HLS aggregate variable = hash_stream[0]._ bit\n#pragma HLS interface ap_fifo port = hash_stream[0]._peek\n#pragma HLS aggregate variable = hash_stream[0]._peek bit\nvoid(hash_stream[0]._.empty());\nvoid(hash_stream[0]._peek.empty());\n#pragma HLS interface ap_fifo port = hash_stream[1]._\n#pragma HLS aggregate variable = hash_stream[1]._ bit\n#pragma HLS interface ap_fifo port = hash_stream[1]._peek\n#pragma HLS aggregate variable = hash_stream[1]._peek bit\nvoid(hash_stream[1]._.empty());\nvoid(hash_stream[1]._peek.empty());\n#pragma HLS interface ap_fifo port = hash_stream[2]._\n#pragma HLS aggregate variable = hash_stream[2]._ bit\n#pragma HLS interface ap_fifo port = hash_stream[2]._peek\n#pragma HLS aggregate variable = hash_stream[2]._peek bit\nvoid(hash_stream[2]._.empty());\nvoid(hash_stream[2]._peek.empty());\n#pragma HLS interface ap_fifo port = hash_stream[3]._\n#pragma HLS aggregate variable = hash_stream[3]._ bit\n#pragma HLS interface ap_fifo port = hash_stream[3]._peek\n#pragma HLS aggregate variable = hash_stream[3]._peek bit\nvoid(hash_stream[3]._.empty());\nvoid(hash_stream[3]._peek.empty());\n#pragma HLS interface ap_fifo port = hash_stream[4]._\n#pragma HLS aggregate variable = hash_stream[4]._ bit\n#pragma HLS interface ap_fifo port = hash_stream[4]._peek\n#pragma HLS aggregate variable = hash_stream[4]._peek bit\nvoid(hash_stream[4]._.empty());\nvoid(hash_stream[4]._peek.empty());\n\n#pragma HLS disaggregate variable = arb_stream\n#pragma HLS array_partition variable = arb_stream complete\n#pragma HLS interface ap_fifo port = arb_stream[0]._\n#pragma HLS aggregate variable = arb_stream[0]._ bit\nvoid(arb_stream[0]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[1]._\n#pragma HLS aggregate variable = arb_stream[1]._ bit\nvoid(arb_stream[1]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[2]._\n#pragma HLS aggregate variable = arb_stream[2]._ bit\nvoid(arb_stream[2]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[3]._\n#pragma HLS aggregate variable = arb_stream[3]._ bit\nvoid(arb_stream[3]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[4]._\n#pragma HLS aggregate variable = arb_stream[4]._ bit\nvoid(arb_stream[4]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[5]._\n#pragma HLS aggregate variable = arb_stream[5]._ bit\nvoid(arb_stream[5]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[6]._\n#pragma HLS aggregate variable = arb_stream[6]._ bit\nvoid(arb_stream[6]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[7]._\n#pragma HLS aggregate variable = arb_stream[7]._ bit\nvoid(arb_stream[7]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[8]._\n#pragma HLS aggregate variable = arb_stream[8]._ bit\nvoid(arb_stream[8]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[9]._\n#pragma HLS aggregate variable = arb_stream[9]._ bit\nvoid(arb_stream[9]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[10]._\n#pragma HLS aggregate variable = arb_stream[10]._ bit\nvoid(arb_stream[10]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[11]._\n#pragma HLS aggregate variable = arb_stream[11]._ bit\nvoid(arb_stream[11]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[12]._\n#pragma HLS aggregate variable = arb_stream[12]._ bit\nvoid(arb_stream[12]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[13]._\n#pragma HLS aggregate variable = arb_stream[13]._ bit\nvoid(arb_stream[13]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[14]._\n#pragma HLS aggregate variable = arb_stream[14]._ bit\nvoid(arb_stream[14]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[15]._\n#pragma HLS aggregate variable = arb_stream[15]._ bit\nvoid(arb_stream[15]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[16]._\n#pragma HLS aggregate variable = arb_stream[16]._ bit\nvoid(arb_stream[16]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[17]._\n#pragma HLS aggregate variable = arb_stream[17]._ bit\nvoid(arb_stream[17]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[18]._\n#pragma HLS aggregate variable = arb_stream[18]._ bit\nvoid(arb_stream[18]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[19]._\n#pragma HLS aggregate variable = arb_stream[19]._ bit\nvoid(arb_stream[19]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[20]._\n#pragma HLS aggregate variable = arb_stream[20]._ bit\nvoid(arb_stream[20]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[21]._\n#pragma HLS aggregate variable = arb_stream[21]._ bit\nvoid(arb_stream[21]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[22]._\n#pragma HLS aggregate variable = arb_stream[22]._ bit\nvoid(arb_stream[22]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[23]._\n#pragma HLS aggregate variable = arb_stream[23]._ bit\nvoid(arb_stream[23]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[24]._\n#pragma HLS aggregate variable = arb_stream[24]._ bit\nvoid(arb_stream[24]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[25]._\n#pragma HLS aggregate variable = arb_stream[25]._ bit\nvoid(arb_stream[25]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[26]._\n#pragma HLS aggregate variable = arb_stream[26]._ bit\nvoid(arb_stream[26]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[27]._\n#pragma HLS aggregate variable = arb_stream[27]._ bit\nvoid(arb_stream[27]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[28]._\n#pragma HLS aggregate variable = arb_stream[28]._ bit\nvoid(arb_stream[28]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[29]._\n#pragma HLS aggregate variable = arb_stream[29]._ bit\nvoid(arb_stream[29]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[30]._\n#pragma HLS aggregate variable = arb_stream[30]._ bit\nvoid(arb_stream[30]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[31]._\n#pragma HLS aggregate variable = arb_stream[31]._ bit\nvoid(arb_stream[31]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[32]._\n#pragma HLS aggregate variable = arb_stream[32]._ bit\nvoid(arb_stream[32]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[33]._\n#pragma HLS aggregate variable = arb_stream[33]._ bit\nvoid(arb_stream[33]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[34]._\n#pragma HLS aggregate variable = arb_stream[34]._ bit\nvoid(arb_stream[34]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[35]._\n#pragma HLS aggregate variable = arb_stream[35]._ bit\nvoid(arb_stream[35]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[36]._\n#pragma HLS aggregate variable = arb_stream[36]._ bit\nvoid(arb_stream[36]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[37]._\n#pragma HLS aggregate variable = arb_stream[37]._ bit\nvoid(arb_stream[37]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[38]._\n#pragma HLS aggregate variable = arb_stream[38]._ bit\nvoid(arb_stream[38]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[39]._\n#pragma HLS aggregate variable = arb_stream[39]._ bit\nvoid(arb_stream[39]._.full());\n\n typedef struct {\n ap_uint<1> valid;\n PACKED_HASH_DTYPE value;\n uint32_t target_partition_idx;\n } XBAR_DTYPE;\n const int READ_STOP_COUNT = (5) * KEYPAIRS_PER_STM;\n const int WRITE_STOP_COUNT = KEYPAIRS_PER_STM;\n int total_num_reads = 0;\n int total_num_writes = 0;\n int num_writes_per_stm[(5)];\n#pragma HLS ARRAY_PARTITION variable=num_writes_per_stm dim=0 complete\n /* TAPA Known-issue: Static keyword fails CSIM because this\n isnt thread-safe. But when running the HW build, it will \n instantiate several copies of this function. So this is OK.\n */\n static\n ap_uint reads_per_input[(5)];\n#pragma HLS ARRAY_PARTITION variable=reads_per_input dim=0 complete\n /* TAPA Known-issue: Static keyword fails CSIM because this\n isnt thread-safe. But when running the HW build, it will \n instantiate several copies of this function. So this is OK.\n */\n static\n XBAR_DTYPE xbar[(5)];\n#pragma HLS ARRAY_PARTITION variable=xbar dim=0 complete\n INIT_LOOP:\n for (int i = 0; i < (5); ++i)\n {\n reads_per_input[i] = 0;\n num_writes_per_stm[i] = 0;\n xbar[i].valid = 0;\n }\n MAIN_LOOP:\n while (total_num_reads < READ_STOP_COUNT ||\n num_writes_per_stm[0] < WRITE_STOP_COUNT ||\n num_writes_per_stm[1] < WRITE_STOP_COUNT ||\n num_writes_per_stm[2] < WRITE_STOP_COUNT ||\n num_writes_per_stm[3] < WRITE_STOP_COUNT ||\n num_writes_per_stm[4] < WRITE_STOP_COUNT\n ) {\n#pragma HLS PIPELINE II=1\n RD_LOGIC:\n for (int strm_idx = 0; strm_idx < (5); ++strm_idx) {\n#pragma HLS UNROLL\n // Metadata:\n ap_uint cur_input_idx;\n ap_uint cur_strm_idx;\n METADATA_DTYPE cur_metadata;\n PACKED_HASH_DTYPE packed_hashval;\n if (xbar[strm_idx].valid == 1)\n {\n // Dont replace this value.\n }\n else if (!hash_stream[strm_idx].empty())\n {\n // Hash and partition data:\n ap_uint tmp_hash = hash_stream[strm_idx].read();\n ap_uint idx_inside_partition = tmp_hash % ( (BV_LENGTH-1)/((3)*(8) /* each sub bv is further partitioned into this chunks*/) + 1);\n int partition_idx = (tmp_hash / ( (BV_LENGTH-1)/((3)*(8) /* each sub bv is further partitioned into this chunks*/) + 1));\n total_num_reads++;\n reads_per_input[strm_idx]++;\n // Pack metadata\n cur_metadata.sidx = strm_idx;\n cur_metadata.iidx = reads_per_input[strm_idx];\n // Pack final payload\n packed_hashval.md = cur_metadata;\n packed_hashval.hash = idx_inside_partition;\n xbar[strm_idx].valid = 1;\n xbar[strm_idx].value = packed_hashval;\n xbar[strm_idx].target_partition_idx = partition_idx;\n }\n }\n WR_LOGIC:\n for (int partition_idx = 0; partition_idx < (8) /* each sub bv is further partitioned into this chunks*/; ++partition_idx)\n {\n#pragma HLS UNROLL\n bool found = false;\n uint32_t found_strm_idx = 0;\n for (int strm_idx = 0; strm_idx < (5); ++strm_idx)\n {\n#pragma HLS UNROLL\n int out_fifo_idx = partition_idx*(5) + strm_idx;\n if (xbar[strm_idx].valid == 1 &&\n xbar[strm_idx].target_partition_idx == partition_idx)\n {\n if (arb_stream[out_fifo_idx].try_write( xbar[strm_idx].value ))\n {\n num_writes_per_stm[strm_idx]++;\n xbar[strm_idx].valid = 0;\n }\n }\n }\n }\n }\n}\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n){\n\n\n#pragma HLS disaggregate variable = hash_stream\n#pragma HLS array_partition variable = hash_stream complete\n#pragma HLS interface ap_fifo port = hash_stream[0]._\n#pragma HLS aggregate variable = hash_stream[0]._ bit\n#pragma HLS interface ap_fifo port = hash_stream[0]._peek\n#pragma HLS aggregate variable = hash_stream[0]._peek bit\nvoid(hash_stream[0]._.empty());\nvoid(hash_stream[0]._peek.empty());\n#pragma HLS interface ap_fifo port = hash_stream[1]._\n#pragma HLS aggregate variable = hash_stream[1]._ bit\n#pragma HLS interface ap_fifo port = hash_stream[1]._peek\n#pragma HLS aggregate variable = hash_stream[1]._peek bit\nvoid(hash_stream[1]._.empty());\nvoid(hash_stream[1]._peek.empty());\n#pragma HLS interface ap_fifo port = hash_stream[2]._\n#pragma HLS aggregate variable = hash_stream[2]._ bit\n#pragma HLS interface ap_fifo port = hash_stream[2]._peek\n#pragma HLS aggregate variable = hash_stream[2]._peek bit\nvoid(hash_stream[2]._.empty());\nvoid(hash_stream[2]._peek.empty());\n#pragma HLS interface ap_fifo port = hash_stream[3]._\n#pragma HLS aggregate variable = hash_stream[3]._ bit\n#pragma HLS interface ap_fifo port = hash_stream[3]._peek\n#pragma HLS aggregate variable = hash_stream[3]._peek bit\nvoid(hash_stream[3]._.empty());\nvoid(hash_stream[3]._peek.empty());\n#pragma HLS interface ap_fifo port = hash_stream[4]._\n#pragma HLS aggregate variable = hash_stream[4]._ bit\n#pragma HLS interface ap_fifo port = hash_stream[4]._peek\n#pragma HLS aggregate variable = hash_stream[4]._peek bit\nvoid(hash_stream[4]._.empty());\nvoid(hash_stream[4]._peek.empty());\n\n#pragma HLS disaggregate variable = arb_stream\n#pragma HLS array_partition variable = arb_stream complete\n#pragma HLS interface ap_fifo port = arb_stream[0]._\n#pragma HLS aggregate variable = arb_stream[0]._ bit\nvoid(arb_stream[0]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[1]._\n#pragma HLS aggregate variable = arb_stream[1]._ bit\nvoid(arb_stream[1]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[2]._\n#pragma HLS aggregate variable = arb_stream[2]._ bit\nvoid(arb_stream[2]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[3]._\n#pragma HLS aggregate variable = arb_stream[3]._ bit\nvoid(arb_stream[3]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[4]._\n#pragma HLS aggregate variable = arb_stream[4]._ bit\nvoid(arb_stream[4]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[5]._\n#pragma HLS aggregate variable = arb_stream[5]._ bit\nvoid(arb_stream[5]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[6]._\n#pragma HLS aggregate variable = arb_stream[6]._ bit\nvoid(arb_stream[6]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[7]._\n#pragma HLS aggregate variable = arb_stream[7]._ bit\nvoid(arb_stream[7]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[8]._\n#pragma HLS aggregate variable = arb_stream[8]._ bit\nvoid(arb_stream[8]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[9]._\n#pragma HLS aggregate variable = arb_stream[9]._ bit\nvoid(arb_stream[9]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[10]._\n#pragma HLS aggregate variable = arb_stream[10]._ bit\nvoid(arb_stream[10]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[11]._\n#pragma HLS aggregate variable = arb_stream[11]._ bit\nvoid(arb_stream[11]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[12]._\n#pragma HLS aggregate variable = arb_stream[12]._ bit\nvoid(arb_stream[12]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[13]._\n#pragma HLS aggregate variable = arb_stream[13]._ bit\nvoid(arb_stream[13]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[14]._\n#pragma HLS aggregate variable = arb_stream[14]._ bit\nvoid(arb_stream[14]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[15]._\n#pragma HLS aggregate variable = arb_stream[15]._ bit\nvoid(arb_stream[15]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[16]._\n#pragma HLS aggregate variable = arb_stream[16]._ bit\nvoid(arb_stream[16]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[17]._\n#pragma HLS aggregate variable = arb_stream[17]._ bit\nvoid(arb_stream[17]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[18]._\n#pragma HLS aggregate variable = arb_stream[18]._ bit\nvoid(arb_stream[18]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[19]._\n#pragma HLS aggregate variable = arb_stream[19]._ bit\nvoid(arb_stream[19]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[20]._\n#pragma HLS aggregate variable = arb_stream[20]._ bit\nvoid(arb_stream[20]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[21]._\n#pragma HLS aggregate variable = arb_stream[21]._ bit\nvoid(arb_stream[21]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[22]._\n#pragma HLS aggregate variable = arb_stream[22]._ bit\nvoid(arb_stream[22]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[23]._\n#pragma HLS aggregate variable = arb_stream[23]._ bit\nvoid(arb_stream[23]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[24]._\n#pragma HLS aggregate variable = arb_stream[24]._ bit\nvoid(arb_stream[24]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[25]._\n#pragma HLS aggregate variable = arb_stream[25]._ bit\nvoid(arb_stream[25]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[26]._\n#pragma HLS aggregate variable = arb_stream[26]._ bit\nvoid(arb_stream[26]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[27]._\n#pragma HLS aggregate variable = arb_stream[27]._ bit\nvoid(arb_stream[27]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[28]._\n#pragma HLS aggregate variable = arb_stream[28]._ bit\nvoid(arb_stream[28]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[29]._\n#pragma HLS aggregate variable = arb_stream[29]._ bit\nvoid(arb_stream[29]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[30]._\n#pragma HLS aggregate variable = arb_stream[30]._ bit\nvoid(arb_stream[30]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[31]._\n#pragma HLS aggregate variable = arb_stream[31]._ bit\nvoid(arb_stream[31]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[32]._\n#pragma HLS aggregate variable = arb_stream[32]._ bit\nvoid(arb_stream[32]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[33]._\n#pragma HLS aggregate variable = arb_stream[33]._ bit\nvoid(arb_stream[33]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[34]._\n#pragma HLS aggregate variable = arb_stream[34]._ bit\nvoid(arb_stream[34]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[35]._\n#pragma HLS aggregate variable = arb_stream[35]._ bit\nvoid(arb_stream[35]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[36]._\n#pragma HLS aggregate variable = arb_stream[36]._ bit\nvoid(arb_stream[36]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[37]._\n#pragma HLS aggregate variable = arb_stream[37]._ bit\nvoid(arb_stream[37]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[38]._\n#pragma HLS aggregate variable = arb_stream[38]._ bit\nvoid(arb_stream[38]._.full());\n#pragma HLS interface ap_fifo port = arb_stream[39]._\n#pragma HLS aggregate variable = arb_stream[39]._ bit\nvoid(arb_stream[39]._.full());\n\n typedef struct {\n ap_uint<1> valid;\n PACKED_HASH_DTYPE value;\n uint32_t target_partition_idx;\n } XBAR_DTYPE;\n const int READ_STOP_COUNT = (5) * KEYPAIRS_PER_STM;\n const int WRITE_STOP_COUNT = KEYPAIRS_PER_STM;\n int total_num_reads = 0;\n int total_num_writes = 0;\n int num_writes_per_stm[(5)];\n#pragma HLS ARRAY_PARTITION variable=num_writes_per_stm dim=0 complete\n /* TAPA Known-issue: Static keyword fails CSIM because this\n isnt thread-safe. But when running the HW build, it will\n instantiate several copies of this function. So this is OK.\n */\n static\n ap_uint reads_per_input[(5)];\n#pragma HLS ARRAY_PARTITION variable=reads_per_input dim=0 complete\n /* TAPA Known-issue: Static keyword fails CSIM because this\n isnt thread-safe. But when running the HW build, it will\n instantiate several copies of this function. So this is OK.\n */\n static\n XBAR_DTYPE xbar[(5)];\n#pragma HLS ARRAY_PARTITION variable=xbar dim=0 complete\n INIT_LOOP:\n for (int i = 0; i < (5); ++i)\n {\n reads_per_input[i] = 0;\n num_writes_per_stm[i] = 0;\n xbar[i].valid = 0;\n }\n MAIN_LOOP:\n while (total_num_reads < READ_STOP_COUNT ||\n num_writes_per_stm[0] < WRITE_STOP_COUNT ||\n num_writes_per_stm[1] < WRITE_STOP_COUNT ||\n num_writes_per_stm[2] < WRITE_STOP_COUNT ||\n num_writes_per_stm[3] < WRITE_STOP_COUNT ||\n num_writes_per_stm[4] < WRITE_STOP_COUNT\n ) {\n#pragma HLS PIPELINE II=1\n RD_LOGIC:\n for (int strm_idx = 0; strm_idx < (5); ++strm_idx) {\n#pragma HLS UNROLL\n // Metadata:\n ap_uint cur_input_idx;\n ap_uint cur_strm_idx;\n METADATA_DTYPE cur_metadata;\n PACKED_HASH_DTYPE packed_hashval;\n if (xbar[strm_idx].valid == 1)\n {\n // Dont replace this value.\n }\n else if (!hash_stream[strm_idx].empty())\n {\n // Hash and partition data:\n ap_uint tmp_hash = hash_stream[strm_idx].read();\n ap_uint idx_inside_partition = tmp_hash % ( (BV_LENGTH-1)/((3)*(8) /* each sub bv is further partitioned into this chunks*/) + 1);\n int partition_idx = (tmp_hash / ( (BV_LENGTH-1)/((3)*(8) /* each sub bv is further partitioned into this chunks*/) + 1));\n total_num_reads++;\n reads_per_input[strm_idx]++;\n // Pack metadata\n cur_metadata.sidx = strm_idx;\n cur_metadata.iidx = reads_per_input[strm_idx];\n // Pack final payload\n packed_hashval.md = cur_metadata;\n packed_hashval.hash = idx_inside_partition;\n xbar[strm_idx].valid = 1;\n xbar[strm_idx].value = packed_hashval;\n xbar[strm_idx].target_partition_idx = partition_idx;\n }\n }\n WR_LOGIC:\n for (int partition_idx = 0; partition_idx < (8) /* each sub bv is further partitioned into this chunks*/; ++partition_idx)\n {\n#pragma HLS UNROLL\n bool found = false;\n uint32_t found_strm_idx = 0;\n for (int strm_idx = 0; strm_idx < (5); ++strm_idx)\n {\n#pragma HLS UNROLL\n int out_fifo_idx = partition_idx*(5) + strm_idx;\n if (xbar[strm_idx].valid == 1 &&\n xbar[strm_idx].target_partition_idx == partition_idx)\n {\n if (arb_stream[out_fifo_idx].try_write( xbar[strm_idx].value ))\n {\n num_writes_per_stm[strm_idx]++;\n xbar[strm_idx].valid = 0;\n }\n }\n }\n }\n }\n}\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "bloom_arbiter_ratemonitor": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n){\n\n\n\n#pragma HLS disaggregate variable = arb_stream_in\n#pragma HLS array_partition variable = arb_stream_in complete\n#pragma HLS interface ap_fifo port = arb_stream_in[0]._\n#pragma HLS aggregate variable = arb_stream_in[0]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[0]._peek\n#pragma HLS aggregate variable = arb_stream_in[0]._peek bit\nvoid(arb_stream_in[0]._.empty());\nvoid(arb_stream_in[0]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[1]._\n#pragma HLS aggregate variable = arb_stream_in[1]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[1]._peek\n#pragma HLS aggregate variable = arb_stream_in[1]._peek bit\nvoid(arb_stream_in[1]._.empty());\nvoid(arb_stream_in[1]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[2]._\n#pragma HLS aggregate variable = arb_stream_in[2]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[2]._peek\n#pragma HLS aggregate variable = arb_stream_in[2]._peek bit\nvoid(arb_stream_in[2]._.empty());\nvoid(arb_stream_in[2]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[3]._\n#pragma HLS aggregate variable = arb_stream_in[3]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[3]._peek\n#pragma HLS aggregate variable = arb_stream_in[3]._peek bit\nvoid(arb_stream_in[3]._.empty());\nvoid(arb_stream_in[3]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[4]._\n#pragma HLS aggregate variable = arb_stream_in[4]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[4]._peek\n#pragma HLS aggregate variable = arb_stream_in[4]._peek bit\nvoid(arb_stream_in[4]._.empty());\nvoid(arb_stream_in[4]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[5]._\n#pragma HLS aggregate variable = arb_stream_in[5]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[5]._peek\n#pragma HLS aggregate variable = arb_stream_in[5]._peek bit\nvoid(arb_stream_in[5]._.empty());\nvoid(arb_stream_in[5]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[6]._\n#pragma HLS aggregate variable = arb_stream_in[6]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[6]._peek\n#pragma HLS aggregate variable = arb_stream_in[6]._peek bit\nvoid(arb_stream_in[6]._.empty());\nvoid(arb_stream_in[6]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[7]._\n#pragma HLS aggregate variable = arb_stream_in[7]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[7]._peek\n#pragma HLS aggregate variable = arb_stream_in[7]._peek bit\nvoid(arb_stream_in[7]._.empty());\nvoid(arb_stream_in[7]._peek.empty());\n\n#pragma HLS disaggregate variable = arb_stream_out\n#pragma HLS array_partition variable = arb_stream_out complete\n#pragma HLS interface ap_fifo port = arb_stream_out[0]._\n#pragma HLS aggregate variable = arb_stream_out[0]._ bit\nvoid(arb_stream_out[0]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[1]._\n#pragma HLS aggregate variable = arb_stream_out[1]._ bit\nvoid(arb_stream_out[1]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[2]._\n#pragma HLS aggregate variable = arb_stream_out[2]._ bit\nvoid(arb_stream_out[2]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[3]._\n#pragma HLS aggregate variable = arb_stream_out[3]._ bit\nvoid(arb_stream_out[3]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[4]._\n#pragma HLS aggregate variable = arb_stream_out[4]._ bit\nvoid(arb_stream_out[4]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[5]._\n#pragma HLS aggregate variable = arb_stream_out[5]._ bit\nvoid(arb_stream_out[5]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[6]._\n#pragma HLS aggregate variable = arb_stream_out[6]._ bit\nvoid(arb_stream_out[6]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[7]._\n#pragma HLS aggregate variable = arb_stream_out[7]._ bit\nvoid(arb_stream_out[7]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_0\n#pragma HLS array_partition variable = fdbk_stream_0 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_0[0]._\n#pragma HLS aggregate variable = fdbk_stream_0[0]._ bit\nvoid(fdbk_stream_0[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_0[1]._\n#pragma HLS aggregate variable = fdbk_stream_0[1]._ bit\nvoid(fdbk_stream_0[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_0[2]._\n#pragma HLS aggregate variable = fdbk_stream_0[2]._ bit\nvoid(fdbk_stream_0[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_0[3]._\n#pragma HLS aggregate variable = fdbk_stream_0[3]._ bit\nvoid(fdbk_stream_0[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_1\n#pragma HLS array_partition variable = fdbk_stream_1 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_1[0]._\n#pragma HLS aggregate variable = fdbk_stream_1[0]._ bit\nvoid(fdbk_stream_1[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_1[1]._\n#pragma HLS aggregate variable = fdbk_stream_1[1]._ bit\nvoid(fdbk_stream_1[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_1[2]._\n#pragma HLS aggregate variable = fdbk_stream_1[2]._ bit\nvoid(fdbk_stream_1[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_1[3]._\n#pragma HLS aggregate variable = fdbk_stream_1[3]._ bit\nvoid(fdbk_stream_1[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_2\n#pragma HLS array_partition variable = fdbk_stream_2 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_2[0]._\n#pragma HLS aggregate variable = fdbk_stream_2[0]._ bit\nvoid(fdbk_stream_2[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_2[1]._\n#pragma HLS aggregate variable = fdbk_stream_2[1]._ bit\nvoid(fdbk_stream_2[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_2[2]._\n#pragma HLS aggregate variable = fdbk_stream_2[2]._ bit\nvoid(fdbk_stream_2[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_2[3]._\n#pragma HLS aggregate variable = fdbk_stream_2[3]._ bit\nvoid(fdbk_stream_2[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_3\n#pragma HLS array_partition variable = fdbk_stream_3 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_3[0]._\n#pragma HLS aggregate variable = fdbk_stream_3[0]._ bit\nvoid(fdbk_stream_3[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_3[1]._\n#pragma HLS aggregate variable = fdbk_stream_3[1]._ bit\nvoid(fdbk_stream_3[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_3[2]._\n#pragma HLS aggregate variable = fdbk_stream_3[2]._ bit\nvoid(fdbk_stream_3[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_3[3]._\n#pragma HLS aggregate variable = fdbk_stream_3[3]._ bit\nvoid(fdbk_stream_3[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_4\n#pragma HLS array_partition variable = fdbk_stream_4 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_4[0]._\n#pragma HLS aggregate variable = fdbk_stream_4[0]._ bit\nvoid(fdbk_stream_4[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_4[1]._\n#pragma HLS aggregate variable = fdbk_stream_4[1]._ bit\nvoid(fdbk_stream_4[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_4[2]._\n#pragma HLS aggregate variable = fdbk_stream_4[2]._ bit\nvoid(fdbk_stream_4[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_4[3]._\n#pragma HLS aggregate variable = fdbk_stream_4[3]._ bit\nvoid(fdbk_stream_4[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_5\n#pragma HLS array_partition variable = fdbk_stream_5 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_5[0]._\n#pragma HLS aggregate variable = fdbk_stream_5[0]._ bit\nvoid(fdbk_stream_5[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_5[1]._\n#pragma HLS aggregate variable = fdbk_stream_5[1]._ bit\nvoid(fdbk_stream_5[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_5[2]._\n#pragma HLS aggregate variable = fdbk_stream_5[2]._ bit\nvoid(fdbk_stream_5[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_5[3]._\n#pragma HLS aggregate variable = fdbk_stream_5[3]._ bit\nvoid(fdbk_stream_5[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_6\n#pragma HLS array_partition variable = fdbk_stream_6 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_6[0]._\n#pragma HLS aggregate variable = fdbk_stream_6[0]._ bit\nvoid(fdbk_stream_6[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_6[1]._\n#pragma HLS aggregate variable = fdbk_stream_6[1]._ bit\nvoid(fdbk_stream_6[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_6[2]._\n#pragma HLS aggregate variable = fdbk_stream_6[2]._ bit\nvoid(fdbk_stream_6[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_6[3]._\n#pragma HLS aggregate variable = fdbk_stream_6[3]._ bit\nvoid(fdbk_stream_6[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_7\n#pragma HLS array_partition variable = fdbk_stream_7 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_7[0]._\n#pragma HLS aggregate variable = fdbk_stream_7[0]._ bit\nvoid(fdbk_stream_7[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_7[1]._\n#pragma HLS aggregate variable = fdbk_stream_7[1]._ bit\nvoid(fdbk_stream_7[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_7[2]._\n#pragma HLS aggregate variable = fdbk_stream_7[2]._ bit\nvoid(fdbk_stream_7[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_7[3]._\n#pragma HLS aggregate variable = fdbk_stream_7[3]._ bit\nvoid(fdbk_stream_7[3]._.full());\n\n int WRITE_STOP_COUNT = 0;\n /* Depending on which level this ratemon is in, \n * it expects a different number of writes.\n */\n WRITE_STOP_COUNT = (5) * KEYPAIRS_PER_STM;\n int writes_per_partition[(8) /* each sub bv is further partitioned into this chunks*/] = {};\n int CRASH_COMPILATION_IF_MISTAKE;\n typedef struct {\n ap_uint valid;\n PACKED_HASH_DTYPE value;\n } XBAR_DTYPE;\n typedef enum {\n WR_FEEDBACK,\n WR_OUTPUT\n } RATEMON_MODE;\n XBAR_DTYPE xbar[(8) /* each sub bv is further partitioned into this chunks*/];\n#pragma HLS ARRAY_PARTITION variable=xbar dim=0 complete\n ap_uint min_output_idx[(5)];\n#pragma HLS ARRAY_PARTITION variable=min_output_idx dim=0 complete\n ap_uint idx_tracker[(5)][(8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/];\n#pragma HLS ARRAY_PARTITION variable=idx_tracker dim=0 complete\n INIT_LOOP:\n for (int i = 0; i < (8) /* each sub bv is further partitioned into this chunks*/; ++i) {\n xbar[i].valid = 0;\n writes_per_partition[i] = 0;\n }\n INIT_LOOP_2:\n for (int i = 0; i < (5); ++i) {\n min_output_idx[i] = 0;\n for (int j = 0; j < (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; ++j) {\n idx_tracker[i][j] = 0;\n }\n }\n MAIN_LOOP:\n while (\n writes_per_partition[0] +\n writes_per_partition[1] +\n writes_per_partition[2] +\n writes_per_partition[3] +\n writes_per_partition[4] +\n writes_per_partition[5] +\n writes_per_partition[6] +\n writes_per_partition[7]\n < WRITE_STOP_COUNT)\n {\n#pragma HLS PIPELINE II=1\n RATEMON_FEEDBACK_DTYPE feedback;\n RD_INPUTS:\n for (int partition_idx = 0; partition_idx < (8) /* each sub bv is further partitioned into this chunks*/; ++partition_idx) {\n ap_uint cur_input_idx;\n ap_uint cur_strm_idx;\n METADATA_DTYPE cur_metadata;\n if (xbar[partition_idx].valid == 0 &&\n !arb_stream_in[partition_idx].empty()\n ){\n xbar[partition_idx].valid = 1;\n xbar[partition_idx].value = arb_stream_in[partition_idx].read();\n }\n }\n ///////////////////////\n // WR_OUTPUTS:\n ///////////////////////\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[0].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[0].valid && xbar[0].value.md.sidx == sidx && !arb_stream_out[0].full()) { xbar[0].valid = 0; arb_stream_out[0].write(xbar[0].value); idx_tracker[sidx][offset] = 1; writes_per_partition[0]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[1].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[1].valid && xbar[1].value.md.sidx == sidx && !arb_stream_out[1].full()) { xbar[1].valid = 0; arb_stream_out[1].write(xbar[1].value); idx_tracker[sidx][offset] = 1; writes_per_partition[1]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[2].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[2].valid && xbar[2].value.md.sidx == sidx && !arb_stream_out[2].full()) { xbar[2].valid = 0; arb_stream_out[2].write(xbar[2].value); idx_tracker[sidx][offset] = 1; writes_per_partition[2]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[3].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[3].valid && xbar[3].value.md.sidx == sidx && !arb_stream_out[3].full()) { xbar[3].valid = 0; arb_stream_out[3].write(xbar[3].value); idx_tracker[sidx][offset] = 1; writes_per_partition[3]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[4].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[4].valid && xbar[4].value.md.sidx == sidx && !arb_stream_out[4].full()) { xbar[4].valid = 0; arb_stream_out[4].write(xbar[4].value); idx_tracker[sidx][offset] = 1; writes_per_partition[4]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[5].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[5].valid && xbar[5].value.md.sidx == sidx && !arb_stream_out[5].full()) { xbar[5].valid = 0; arb_stream_out[5].write(xbar[5].value); idx_tracker[sidx][offset] = 1; writes_per_partition[5]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[6].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[6].valid && xbar[6].value.md.sidx == sidx && !arb_stream_out[6].full()) { xbar[6].valid = 0; arb_stream_out[6].write(xbar[6].value); idx_tracker[sidx][offset] = 1; writes_per_partition[6]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[7].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[7].valid && xbar[7].value.md.sidx == sidx && !arb_stream_out[7].full()) { xbar[7].valid = 0; arb_stream_out[7].write(xbar[7].value); idx_tracker[sidx][offset] = 1; writes_per_partition[7]++; break; } }\n ///////////////////////\n // UPDATE_IDCES:\n ///////////////////////\n int shuf_idx0 = (min_output_idx[0] + 1) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (idx_tracker[0][shuf_idx0] == 1) { min_output_idx[0] += 1; idx_tracker[0][shuf_idx0] = 0; } /*#ifdef __DO_DEBUG_PRINTS__ //printf(\"ARBITER RATEMON %d %c kp%d - Updating min_output_idx[%d]=%d\\n\", // arb_idx, // ratemon_ID, // kp_idx, // STM, // min_output_idx[STM].to_int() //); //#endif \n*/ int shuf_idx1 = (min_output_idx[1] + 1) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (idx_tracker[1][shuf_idx1] == 1) { min_output_idx[1] += 1; idx_tracker[1][shuf_idx1] = 0; } /*#ifdef __DO_DEBUG_PRINTS__ //printf(\"ARBITER RATEMON %d %c kp%d - Updating min_output_idx[%d]=%d\\n\", // arb_idx, // ratemon_ID, // kp_idx, // STM, // min_output_idx[STM].to_int() //); //#endif \n*/ int shuf_idx2 = (min_output_idx[2] + 1) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (idx_tracker[2][shuf_idx2] == 1) { min_output_idx[2] += 1; idx_tracker[2][shuf_idx2] = 0; } /*#ifdef __DO_DEBUG_PRINTS__ //printf(\"ARBITER RATEMON %d %c kp%d - Updating min_output_idx[%d]=%d\\n\", // arb_idx, // ratemon_ID, // kp_idx, // STM, // min_output_idx[STM].to_int() //); //#endif \n*/ int shuf_idx3 = (min_output_idx[3] + 1) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (idx_tracker[3][shuf_idx3] == 1) { min_output_idx[3] += 1; idx_tracker[3][shuf_idx3] = 0; } /*#ifdef __DO_DEBUG_PRINTS__ //printf(\"ARBITER RATEMON %d %c kp%d - Updating min_output_idx[%d]=%d\\n\", // arb_idx, // ratemon_ID, // kp_idx, // STM, // min_output_idx[STM].to_int() //); //#endif \n*/ int shuf_idx4 = (min_output_idx[4] + 1) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (idx_tracker[4][shuf_idx4] == 1) { min_output_idx[4] += 1; idx_tracker[4][shuf_idx4] = 0; } /*#ifdef __DO_DEBUG_PRINTS__ //printf(\"ARBITER RATEMON %d %c kp%d - Updating min_output_idx[%d]=%d\\n\", // arb_idx, // ratemon_ID, // kp_idx, // STM, // min_output_idx[STM].to_int() //); //#endif \n*/\n WRITE_FEEDBACK:\n /* For the ratemonitors NOT in the last level, we dont \n * have the data from all 4 streams. So dont attempt to ratelimit\n * based on data we cant get.\n */\n feedback.strm0_out_idx = min_output_idx[0];\n feedback.strm1_out_idx = min_output_idx[1];\n feedback.strm2_out_idx = min_output_idx[2];\n feedback.strm3_out_idx = min_output_idx[3];\n feedback.strm4_out_idx = min_output_idx[4];\n for (int i = 0; i < ((5) - 1); ++i) {\n fdbk_stream_0[i].try_write(feedback);\n fdbk_stream_1[i].try_write(feedback);\n fdbk_stream_2[i].try_write(feedback);\n fdbk_stream_3[i].try_write(feedback);\n fdbk_stream_4[i].try_write(feedback);\n fdbk_stream_5[i].try_write(feedback);\n fdbk_stream_6[i].try_write(feedback);\n fdbk_stream_7[i].try_write(feedback);\n }\n }\n}\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n){\n\n\n\n#pragma HLS disaggregate variable = arb_stream_in\n#pragma HLS array_partition variable = arb_stream_in complete\n#pragma HLS interface ap_fifo port = arb_stream_in[0]._\n#pragma HLS aggregate variable = arb_stream_in[0]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[0]._peek\n#pragma HLS aggregate variable = arb_stream_in[0]._peek bit\nvoid(arb_stream_in[0]._.empty());\nvoid(arb_stream_in[0]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[1]._\n#pragma HLS aggregate variable = arb_stream_in[1]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[1]._peek\n#pragma HLS aggregate variable = arb_stream_in[1]._peek bit\nvoid(arb_stream_in[1]._.empty());\nvoid(arb_stream_in[1]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[2]._\n#pragma HLS aggregate variable = arb_stream_in[2]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[2]._peek\n#pragma HLS aggregate variable = arb_stream_in[2]._peek bit\nvoid(arb_stream_in[2]._.empty());\nvoid(arb_stream_in[2]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[3]._\n#pragma HLS aggregate variable = arb_stream_in[3]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[3]._peek\n#pragma HLS aggregate variable = arb_stream_in[3]._peek bit\nvoid(arb_stream_in[3]._.empty());\nvoid(arb_stream_in[3]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[4]._\n#pragma HLS aggregate variable = arb_stream_in[4]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[4]._peek\n#pragma HLS aggregate variable = arb_stream_in[4]._peek bit\nvoid(arb_stream_in[4]._.empty());\nvoid(arb_stream_in[4]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[5]._\n#pragma HLS aggregate variable = arb_stream_in[5]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[5]._peek\n#pragma HLS aggregate variable = arb_stream_in[5]._peek bit\nvoid(arb_stream_in[5]._.empty());\nvoid(arb_stream_in[5]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[6]._\n#pragma HLS aggregate variable = arb_stream_in[6]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[6]._peek\n#pragma HLS aggregate variable = arb_stream_in[6]._peek bit\nvoid(arb_stream_in[6]._.empty());\nvoid(arb_stream_in[6]._peek.empty());\n#pragma HLS interface ap_fifo port = arb_stream_in[7]._\n#pragma HLS aggregate variable = arb_stream_in[7]._ bit\n#pragma HLS interface ap_fifo port = arb_stream_in[7]._peek\n#pragma HLS aggregate variable = arb_stream_in[7]._peek bit\nvoid(arb_stream_in[7]._.empty());\nvoid(arb_stream_in[7]._peek.empty());\n\n#pragma HLS disaggregate variable = arb_stream_out\n#pragma HLS array_partition variable = arb_stream_out complete\n#pragma HLS interface ap_fifo port = arb_stream_out[0]._\n#pragma HLS aggregate variable = arb_stream_out[0]._ bit\nvoid(arb_stream_out[0]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[1]._\n#pragma HLS aggregate variable = arb_stream_out[1]._ bit\nvoid(arb_stream_out[1]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[2]._\n#pragma HLS aggregate variable = arb_stream_out[2]._ bit\nvoid(arb_stream_out[2]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[3]._\n#pragma HLS aggregate variable = arb_stream_out[3]._ bit\nvoid(arb_stream_out[3]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[4]._\n#pragma HLS aggregate variable = arb_stream_out[4]._ bit\nvoid(arb_stream_out[4]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[5]._\n#pragma HLS aggregate variable = arb_stream_out[5]._ bit\nvoid(arb_stream_out[5]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[6]._\n#pragma HLS aggregate variable = arb_stream_out[6]._ bit\nvoid(arb_stream_out[6]._.full());\n#pragma HLS interface ap_fifo port = arb_stream_out[7]._\n#pragma HLS aggregate variable = arb_stream_out[7]._ bit\nvoid(arb_stream_out[7]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_0\n#pragma HLS array_partition variable = fdbk_stream_0 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_0[0]._\n#pragma HLS aggregate variable = fdbk_stream_0[0]._ bit\nvoid(fdbk_stream_0[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_0[1]._\n#pragma HLS aggregate variable = fdbk_stream_0[1]._ bit\nvoid(fdbk_stream_0[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_0[2]._\n#pragma HLS aggregate variable = fdbk_stream_0[2]._ bit\nvoid(fdbk_stream_0[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_0[3]._\n#pragma HLS aggregate variable = fdbk_stream_0[3]._ bit\nvoid(fdbk_stream_0[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_1\n#pragma HLS array_partition variable = fdbk_stream_1 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_1[0]._\n#pragma HLS aggregate variable = fdbk_stream_1[0]._ bit\nvoid(fdbk_stream_1[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_1[1]._\n#pragma HLS aggregate variable = fdbk_stream_1[1]._ bit\nvoid(fdbk_stream_1[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_1[2]._\n#pragma HLS aggregate variable = fdbk_stream_1[2]._ bit\nvoid(fdbk_stream_1[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_1[3]._\n#pragma HLS aggregate variable = fdbk_stream_1[3]._ bit\nvoid(fdbk_stream_1[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_2\n#pragma HLS array_partition variable = fdbk_stream_2 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_2[0]._\n#pragma HLS aggregate variable = fdbk_stream_2[0]._ bit\nvoid(fdbk_stream_2[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_2[1]._\n#pragma HLS aggregate variable = fdbk_stream_2[1]._ bit\nvoid(fdbk_stream_2[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_2[2]._\n#pragma HLS aggregate variable = fdbk_stream_2[2]._ bit\nvoid(fdbk_stream_2[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_2[3]._\n#pragma HLS aggregate variable = fdbk_stream_2[3]._ bit\nvoid(fdbk_stream_2[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_3\n#pragma HLS array_partition variable = fdbk_stream_3 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_3[0]._\n#pragma HLS aggregate variable = fdbk_stream_3[0]._ bit\nvoid(fdbk_stream_3[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_3[1]._\n#pragma HLS aggregate variable = fdbk_stream_3[1]._ bit\nvoid(fdbk_stream_3[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_3[2]._\n#pragma HLS aggregate variable = fdbk_stream_3[2]._ bit\nvoid(fdbk_stream_3[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_3[3]._\n#pragma HLS aggregate variable = fdbk_stream_3[3]._ bit\nvoid(fdbk_stream_3[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_4\n#pragma HLS array_partition variable = fdbk_stream_4 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_4[0]._\n#pragma HLS aggregate variable = fdbk_stream_4[0]._ bit\nvoid(fdbk_stream_4[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_4[1]._\n#pragma HLS aggregate variable = fdbk_stream_4[1]._ bit\nvoid(fdbk_stream_4[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_4[2]._\n#pragma HLS aggregate variable = fdbk_stream_4[2]._ bit\nvoid(fdbk_stream_4[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_4[3]._\n#pragma HLS aggregate variable = fdbk_stream_4[3]._ bit\nvoid(fdbk_stream_4[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_5\n#pragma HLS array_partition variable = fdbk_stream_5 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_5[0]._\n#pragma HLS aggregate variable = fdbk_stream_5[0]._ bit\nvoid(fdbk_stream_5[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_5[1]._\n#pragma HLS aggregate variable = fdbk_stream_5[1]._ bit\nvoid(fdbk_stream_5[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_5[2]._\n#pragma HLS aggregate variable = fdbk_stream_5[2]._ bit\nvoid(fdbk_stream_5[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_5[3]._\n#pragma HLS aggregate variable = fdbk_stream_5[3]._ bit\nvoid(fdbk_stream_5[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_6\n#pragma HLS array_partition variable = fdbk_stream_6 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_6[0]._\n#pragma HLS aggregate variable = fdbk_stream_6[0]._ bit\nvoid(fdbk_stream_6[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_6[1]._\n#pragma HLS aggregate variable = fdbk_stream_6[1]._ bit\nvoid(fdbk_stream_6[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_6[2]._\n#pragma HLS aggregate variable = fdbk_stream_6[2]._ bit\nvoid(fdbk_stream_6[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_6[3]._\n#pragma HLS aggregate variable = fdbk_stream_6[3]._ bit\nvoid(fdbk_stream_6[3]._.full());\n\n#pragma HLS disaggregate variable = fdbk_stream_7\n#pragma HLS array_partition variable = fdbk_stream_7 complete\n#pragma HLS interface ap_fifo port = fdbk_stream_7[0]._\n#pragma HLS aggregate variable = fdbk_stream_7[0]._ bit\nvoid(fdbk_stream_7[0]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_7[1]._\n#pragma HLS aggregate variable = fdbk_stream_7[1]._ bit\nvoid(fdbk_stream_7[1]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_7[2]._\n#pragma HLS aggregate variable = fdbk_stream_7[2]._ bit\nvoid(fdbk_stream_7[2]._.full());\n#pragma HLS interface ap_fifo port = fdbk_stream_7[3]._\n#pragma HLS aggregate variable = fdbk_stream_7[3]._ bit\nvoid(fdbk_stream_7[3]._.full());\n\n int WRITE_STOP_COUNT = 0;\n /* Depending on which level this ratemon is in,\n * it expects a different number of writes.\n */\n WRITE_STOP_COUNT = (5) * KEYPAIRS_PER_STM;\n int writes_per_partition[(8) /* each sub bv is further partitioned into this chunks*/] = {};\n int CRASH_COMPILATION_IF_MISTAKE;\n typedef struct {\n ap_uint valid;\n PACKED_HASH_DTYPE value;\n } XBAR_DTYPE;\n typedef enum {\n WR_FEEDBACK,\n WR_OUTPUT\n } RATEMON_MODE;\n XBAR_DTYPE xbar[(8) /* each sub bv is further partitioned into this chunks*/];\n#pragma HLS ARRAY_PARTITION variable=xbar dim=0 complete\n ap_uint min_output_idx[(5)];\n#pragma HLS ARRAY_PARTITION variable=min_output_idx dim=0 complete\n ap_uint idx_tracker[(5)][(8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/];\n#pragma HLS ARRAY_PARTITION variable=idx_tracker dim=0 complete\n INIT_LOOP:\n for (int i = 0; i < (8) /* each sub bv is further partitioned into this chunks*/; ++i) {\n xbar[i].valid = 0;\n writes_per_partition[i] = 0;\n }\n INIT_LOOP_2:\n for (int i = 0; i < (5); ++i) {\n min_output_idx[i] = 0;\n for (int j = 0; j < (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; ++j) {\n idx_tracker[i][j] = 0;\n }\n }\n MAIN_LOOP:\n while (\n writes_per_partition[0] +\n writes_per_partition[1] +\n writes_per_partition[2] +\n writes_per_partition[3] +\n writes_per_partition[4] +\n writes_per_partition[5] +\n writes_per_partition[6] +\n writes_per_partition[7]\n < WRITE_STOP_COUNT)\n {\n#pragma HLS PIPELINE II=1\n RATEMON_FEEDBACK_DTYPE feedback;\n RD_INPUTS:\n for (int partition_idx = 0; partition_idx < (8) /* each sub bv is further partitioned into this chunks*/; ++partition_idx) {\n ap_uint cur_input_idx;\n ap_uint cur_strm_idx;\n METADATA_DTYPE cur_metadata;\n if (xbar[partition_idx].valid == 0 &&\n !arb_stream_in[partition_idx].empty()\n ){\n xbar[partition_idx].valid = 1;\n xbar[partition_idx].value = arb_stream_in[partition_idx].read();\n }\n }\n ///////////////////////\n // WR_OUTPUTS:\n ///////////////////////\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[0].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[0].valid && xbar[0].value.md.sidx == sidx && !arb_stream_out[0].full()) { xbar[0].valid = 0; arb_stream_out[0].write(xbar[0].value); idx_tracker[sidx][offset] = 1; writes_per_partition[0]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[1].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[1].valid && xbar[1].value.md.sidx == sidx && !arb_stream_out[1].full()) { xbar[1].valid = 0; arb_stream_out[1].write(xbar[1].value); idx_tracker[sidx][offset] = 1; writes_per_partition[1]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[2].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[2].valid && xbar[2].value.md.sidx == sidx && !arb_stream_out[2].full()) { xbar[2].valid = 0; arb_stream_out[2].write(xbar[2].value); idx_tracker[sidx][offset] = 1; writes_per_partition[2]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[3].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[3].valid && xbar[3].value.md.sidx == sidx && !arb_stream_out[3].full()) { xbar[3].valid = 0; arb_stream_out[3].write(xbar[3].value); idx_tracker[sidx][offset] = 1; writes_per_partition[3]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[4].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[4].valid && xbar[4].value.md.sidx == sidx && !arb_stream_out[4].full()) { xbar[4].valid = 0; arb_stream_out[4].write(xbar[4].value); idx_tracker[sidx][offset] = 1; writes_per_partition[4]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[5].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[5].valid && xbar[5].value.md.sidx == sidx && !arb_stream_out[5].full()) { xbar[5].valid = 0; arb_stream_out[5].write(xbar[5].value); idx_tracker[sidx][offset] = 1; writes_per_partition[5]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[6].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[6].valid && xbar[6].value.md.sidx == sidx && !arb_stream_out[6].full()) { xbar[6].valid = 0; arb_stream_out[6].write(xbar[6].value); idx_tracker[sidx][offset] = 1; writes_per_partition[6]++; break; } }\n for (int sidx = 0; sidx < (5); ++sidx) { int offset = (xbar[7].value.md.iidx) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (xbar[7].valid && xbar[7].value.md.sidx == sidx && !arb_stream_out[7].full()) { xbar[7].valid = 0; arb_stream_out[7].write(xbar[7].value); idx_tracker[sidx][offset] = 1; writes_per_partition[7]++; break; } }\n ///////////////////////\n // UPDATE_IDCES:\n ///////////////////////\n int shuf_idx0 = (min_output_idx[0] + 1) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (idx_tracker[0][shuf_idx0] == 1) { min_output_idx[0] += 1; idx_tracker[0][shuf_idx0] = 0; } /*#ifdef __DO_DEBUG_PRINTS__ //printf(\"ARBITER RATEMON %d %c kp%d - Updating min_output_idx[%d]=%d\\n\", // arb_idx, // ratemon_ID, // kp_idx, // STM, // min_output_idx[STM].to_int() //); //#endif \n*/ int shuf_idx1 = (min_output_idx[1] + 1) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (idx_tracker[1][shuf_idx1] == 1) { min_output_idx[1] += 1; idx_tracker[1][shuf_idx1] = 0; } /*#ifdef __DO_DEBUG_PRINTS__ //printf(\"ARBITER RATEMON %d %c kp%d - Updating min_output_idx[%d]=%d\\n\", // arb_idx, // ratemon_ID, // kp_idx, // STM, // min_output_idx[STM].to_int() //); //#endif \n*/ int shuf_idx2 = (min_output_idx[2] + 1) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (idx_tracker[2][shuf_idx2] == 1) { min_output_idx[2] += 1; idx_tracker[2][shuf_idx2] = 0; } /*#ifdef __DO_DEBUG_PRINTS__ //printf(\"ARBITER RATEMON %d %c kp%d - Updating min_output_idx[%d]=%d\\n\", // arb_idx, // ratemon_ID, // kp_idx, // STM, // min_output_idx[STM].to_int() //); //#endif \n*/ int shuf_idx3 = (min_output_idx[3] + 1) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (idx_tracker[3][shuf_idx3] == 1) { min_output_idx[3] += 1; idx_tracker[3][shuf_idx3] = 0; } /*#ifdef __DO_DEBUG_PRINTS__ //printf(\"ARBITER RATEMON %d %c kp%d - Updating min_output_idx[%d]=%d\\n\", // arb_idx, // ratemon_ID, // kp_idx, // STM, // min_output_idx[STM].to_int() //); //#endif \n*/ int shuf_idx4 = (min_output_idx[4] + 1) % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (idx_tracker[4][shuf_idx4] == 1) { min_output_idx[4] += 1; idx_tracker[4][shuf_idx4] = 0; } /*#ifdef __DO_DEBUG_PRINTS__ //printf(\"ARBITER RATEMON %d %c kp%d - Updating min_output_idx[%d]=%d\\n\", // arb_idx, // ratemon_ID, // kp_idx, // STM, // min_output_idx[STM].to_int() //); //#endif \n*/\n WRITE_FEEDBACK:\n /* For the ratemonitors NOT in the last level, we dont\n * have the data from all 4 streams. So dont attempt to ratelimit\n * based on data we cant get.\n */\n feedback.strm0_out_idx = min_output_idx[0];\n feedback.strm1_out_idx = min_output_idx[1];\n feedback.strm2_out_idx = min_output_idx[2];\n feedback.strm3_out_idx = min_output_idx[3];\n feedback.strm4_out_idx = min_output_idx[4];\n for (int i = 0; i < ((5) - 1); ++i) {\n fdbk_stream_0[i].try_write(feedback);\n fdbk_stream_1[i].try_write(feedback);\n fdbk_stream_2[i].try_write(feedback);\n fdbk_stream_3[i].try_write(feedback);\n fdbk_stream_4[i].try_write(feedback);\n fdbk_stream_5[i].try_write(feedback);\n fdbk_stream_6[i].try_write(feedback);\n fdbk_stream_7[i].try_write(feedback);\n }\n }\n}\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "bloom_hier_arbiter_atom": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n){\n\n\n\n\n#pragma HLS disaggregate variable = ratemon_stream\n#pragma HLS interface ap_fifo port = ratemon_stream._\n#pragma HLS aggregate variable = ratemon_stream._ bit\n#pragma HLS interface ap_fifo port = ratemon_stream._peek\n#pragma HLS aggregate variable = ratemon_stream._peek bit\nvoid(ratemon_stream._.empty());\nvoid(ratemon_stream._peek.empty());\n\n#pragma HLS disaggregate variable = in_stream0\n#pragma HLS interface ap_fifo port = in_stream0._\n#pragma HLS aggregate variable = in_stream0._ bit\n#pragma HLS interface ap_fifo port = in_stream0._peek\n#pragma HLS aggregate variable = in_stream0._peek bit\nvoid(in_stream0._.empty());\nvoid(in_stream0._peek.empty());\n\n#pragma HLS disaggregate variable = in_stream1\n#pragma HLS interface ap_fifo port = in_stream1._\n#pragma HLS aggregate variable = in_stream1._ bit\n#pragma HLS interface ap_fifo port = in_stream1._peek\n#pragma HLS aggregate variable = in_stream1._peek bit\nvoid(in_stream1._.empty());\nvoid(in_stream1._peek.empty());\n\n#pragma HLS disaggregate variable = out_stream\n#pragma HLS interface ap_fifo port = out_stream._\n#pragma HLS aggregate variable = out_stream._ bit\nvoid(out_stream._.full());\n\n typedef struct {\n ap_uint<1> valid;\n PACKED_HASH_DTYPE value;\n } XBAR_DTYPE;\n XBAR_DTYPE xbar[2];\n#pragma HLS ARRAY_PARTITION variable=xbar dim=0 complete\n RATEMON_FEEDBACK_DTYPE feedback;\n ap_uint min_output_idx_s0 = 0;\n ap_uint min_output_idx_s1 = 0;\n ap_uint min_output_idx_s2 = 0;\n ap_uint min_output_idx_s3 = 0;\n ap_uint min_output_idx_s4 = 0;\n /* Initialize for SW_EMU... but will this guaranteed work for HW builds?\n * It might not be needed for HW builds because each xbar entry should just\n * be invalidated anyways, after writing.\n */\n INIT_LOOP:\n for (int i = 0; i < 2; ++i) {\n xbar[i].valid = 0;\n }\n MAIN_LOOP:\n while (1) {\n#pragma HLS PIPELINE II=1\n RATEMON_LOGIC:\n if (!ratemon_stream.empty()) {\n feedback = ratemon_stream.read();\n // Manually unroll the min_output_idx logic, to reduce latency within the atoms.\n // With only one variable this takes one more cycle.\n min_output_idx_s0 = feedback.strm0_out_idx;\n min_output_idx_s1 = feedback.strm1_out_idx;\n min_output_idx_s2 = feedback.strm2_out_idx;\n min_output_idx_s3 = feedback.strm3_out_idx;\n min_output_idx_s4 = feedback.strm4_out_idx;\n }\n RD_LOGIC:\n if (xbar[0].valid == 1) {\n // Dont overwrite it\n }\n else if (!in_stream0.empty()) {\n PACKED_HASH_DTYPE packed_val = in_stream0.read();\n xbar[0].value = packed_val;\n xbar[0].valid = 1;\n }\n if (xbar[1].valid == 1) {\n // Dont overwrite it\n }\n else if (!in_stream1.empty()) {\n PACKED_HASH_DTYPE packed_val = in_stream1.read();\n xbar[1].value = packed_val;\n xbar[1].valid = 1;\n }\n WR_LOGIC:\n int valid_idxes = 0;\n int allowed_idx_s0 = min_output_idx_s0 + ((8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/);\n int allowed_idx_s1 = min_output_idx_s1 + ((8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/);\n int allowed_idx_s2 = min_output_idx_s2 + ((8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/);\n int allowed_idx_s3 = min_output_idx_s3 + ((8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/);\n int allowed_idx_s4 = min_output_idx_s4 + ((8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/);\n if (xbar[0].valid &&\n xbar[0].value.md.iidx <= allowed_idx_s0 &&\n xbar[0].value.md.iidx <= allowed_idx_s1 &&\n xbar[0].value.md.iidx <= allowed_idx_s2 &&\n xbar[0].value.md.iidx <= allowed_idx_s3 &&\n xbar[0].value.md.iidx <= allowed_idx_s4\n ) { valid_idxes += 1; }\n if (xbar[1].valid &&\n xbar[1].value.md.iidx <= allowed_idx_s0 &&\n xbar[1].value.md.iidx <= allowed_idx_s1 &&\n xbar[1].value.md.iidx <= allowed_idx_s2 &&\n xbar[1].value.md.iidx <= allowed_idx_s3 &&\n xbar[1].value.md.iidx <= allowed_idx_s4\n ) { valid_idxes += 2; }\n if (valid_idxes == 3) {\n if (xbar[1].value.md.iidx <= xbar[0].value.md.iidx) {\n if (out_stream.try_write(xbar[1].value)) {\n xbar[1].valid = 0;\n }\n }\n else {\n if (out_stream.try_write(xbar[0].value)) {\n xbar[0].valid = 0;\n }\n }\n }\n else if (valid_idxes == 2) {\n if (out_stream.try_write(xbar[1].value)) {\n xbar[1].valid = 0;\n }\n }\n else if (valid_idxes == 1) {\n if (out_stream.try_write(xbar[0].value)) {\n xbar[0].valid = 0;\n }\n }\n }\n}\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n){\n\n\n\n\n#pragma HLS disaggregate variable = ratemon_stream\n#pragma HLS interface ap_fifo port = ratemon_stream._\n#pragma HLS aggregate variable = ratemon_stream._ bit\n#pragma HLS interface ap_fifo port = ratemon_stream._peek\n#pragma HLS aggregate variable = ratemon_stream._peek bit\nvoid(ratemon_stream._.empty());\nvoid(ratemon_stream._peek.empty());\n\n#pragma HLS disaggregate variable = in_stream0\n#pragma HLS interface ap_fifo port = in_stream0._\n#pragma HLS aggregate variable = in_stream0._ bit\n#pragma HLS interface ap_fifo port = in_stream0._peek\n#pragma HLS aggregate variable = in_stream0._peek bit\nvoid(in_stream0._.empty());\nvoid(in_stream0._peek.empty());\n\n#pragma HLS disaggregate variable = in_stream1\n#pragma HLS interface ap_fifo port = in_stream1._\n#pragma HLS aggregate variable = in_stream1._ bit\n#pragma HLS interface ap_fifo port = in_stream1._peek\n#pragma HLS aggregate variable = in_stream1._peek bit\nvoid(in_stream1._.empty());\nvoid(in_stream1._peek.empty());\n\n#pragma HLS disaggregate variable = out_stream\n#pragma HLS interface ap_fifo port = out_stream._\n#pragma HLS aggregate variable = out_stream._ bit\nvoid(out_stream._.full());\n\n typedef struct {\n ap_uint<1> valid;\n PACKED_HASH_DTYPE value;\n } XBAR_DTYPE;\n XBAR_DTYPE xbar[2];\n#pragma HLS ARRAY_PARTITION variable=xbar dim=0 complete\n RATEMON_FEEDBACK_DTYPE feedback;\n ap_uint min_output_idx_s0 = 0;\n ap_uint min_output_idx_s1 = 0;\n ap_uint min_output_idx_s2 = 0;\n ap_uint min_output_idx_s3 = 0;\n ap_uint min_output_idx_s4 = 0;\n /* Initialize for SW_EMU... but will this guaranteed work for HW builds?\n * It might not be needed for HW builds because each xbar entry should just\n * be invalidated anyways, after writing.\n */\n INIT_LOOP:\n for (int i = 0; i < 2; ++i) {\n xbar[i].valid = 0;\n }\n MAIN_LOOP:\n while (1) {\n#pragma HLS PIPELINE II=1\n RATEMON_LOGIC:\n if (!ratemon_stream.empty()) {\n feedback = ratemon_stream.read();\n // Manually unroll the min_output_idx logic, to reduce latency within the atoms.\n // With only one variable this takes one more cycle.\n min_output_idx_s0 = feedback.strm0_out_idx;\n min_output_idx_s1 = feedback.strm1_out_idx;\n min_output_idx_s2 = feedback.strm2_out_idx;\n min_output_idx_s3 = feedback.strm3_out_idx;\n min_output_idx_s4 = feedback.strm4_out_idx;\n }\n RD_LOGIC:\n if (xbar[0].valid == 1) {\n // Dont overwrite it\n }\n else if (!in_stream0.empty()) {\n PACKED_HASH_DTYPE packed_val = in_stream0.read();\n xbar[0].value = packed_val;\n xbar[0].valid = 1;\n }\n if (xbar[1].valid == 1) {\n // Dont overwrite it\n }\n else if (!in_stream1.empty()) {\n PACKED_HASH_DTYPE packed_val = in_stream1.read();\n xbar[1].value = packed_val;\n xbar[1].valid = 1;\n }\n WR_LOGIC:\n int valid_idxes = 0;\n int allowed_idx_s0 = min_output_idx_s0 + ((8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/);\n int allowed_idx_s1 = min_output_idx_s1 + ((8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/);\n int allowed_idx_s2 = min_output_idx_s2 + ((8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/);\n int allowed_idx_s3 = min_output_idx_s3 + ((8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/);\n int allowed_idx_s4 = min_output_idx_s4 + ((8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/);\n if (xbar[0].valid &&\n xbar[0].value.md.iidx <= allowed_idx_s0 &&\n xbar[0].value.md.iidx <= allowed_idx_s1 &&\n xbar[0].value.md.iidx <= allowed_idx_s2 &&\n xbar[0].value.md.iidx <= allowed_idx_s3 &&\n xbar[0].value.md.iidx <= allowed_idx_s4\n ) { valid_idxes += 1; }\n if (xbar[1].valid &&\n xbar[1].value.md.iidx <= allowed_idx_s0 &&\n xbar[1].value.md.iidx <= allowed_idx_s1 &&\n xbar[1].value.md.iidx <= allowed_idx_s2 &&\n xbar[1].value.md.iidx <= allowed_idx_s3 &&\n xbar[1].value.md.iidx <= allowed_idx_s4\n ) { valid_idxes += 2; }\n if (valid_idxes == 3) {\n if (xbar[1].value.md.iidx <= xbar[0].value.md.iidx) {\n if (out_stream.try_write(xbar[1].value)) {\n xbar[1].valid = 0;\n }\n }\n else {\n if (out_stream.try_write(xbar[0].value)) {\n xbar[0].valid = 0;\n }\n }\n }\n else if (valid_idxes == 2) {\n if (out_stream.try_write(xbar[1].value)) {\n xbar[1].valid = 0;\n }\n }\n else if (valid_idxes == 1) {\n if (out_stream.try_write(xbar[0].value)) {\n xbar[0].valid = 0;\n }\n }\n }\n}\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "computeHash_Computer": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n){\n\n\n\n#pragma HLS disaggregate variable = key_stream\n#pragma HLS interface ap_fifo port = key_stream._\n#pragma HLS aggregate variable = key_stream._ bit\n#pragma HLS interface ap_fifo port = key_stream._peek\n#pragma HLS aggregate variable = key_stream._peek bit\nvoid(key_stream._.empty());\nvoid(key_stream._peek.empty());\n\n#pragma HLS disaggregate variable = hash_stream\n#pragma HLS interface ap_fifo port = hash_stream._\n#pragma HLS aggregate variable = hash_stream._ bit\nvoid(hash_stream._.full());\n\n int module_idx = stm_idx*(3) + hash_idx;\n const int WRITE_STOP_COUNT = KEYPAIRS_PER_STM;\n int total_num_writes = 0;\n int input_idx = 0;\n MAIN_LOOP:\n while ( total_num_writes < WRITE_STOP_COUNT){\n#pragma HLS PIPELINE II=1\n ap_uint<(32)> key = key_stream.read();\n uint32_t hash = MurmurHash3_x86_32(key, hash_idx);\n hash %= ( (BV_LENGTH-1)/(3) + 1);\n hash_stream.write(hash);\n total_num_writes++;\n }\n}\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n){\n\n\n\n#pragma HLS disaggregate variable = key_stream\n#pragma HLS interface ap_fifo port = key_stream._\n#pragma HLS aggregate variable = key_stream._ bit\n#pragma HLS interface ap_fifo port = key_stream._peek\n#pragma HLS aggregate variable = key_stream._peek bit\nvoid(key_stream._.empty());\nvoid(key_stream._peek.empty());\n\n#pragma HLS disaggregate variable = hash_stream\n#pragma HLS interface ap_fifo port = hash_stream._\n#pragma HLS aggregate variable = hash_stream._ bit\nvoid(hash_stream._.full());\n\n int module_idx = stm_idx*(3) + hash_idx;\n const int WRITE_STOP_COUNT = KEYPAIRS_PER_STM;\n int total_num_writes = 0;\n int input_idx = 0;\n MAIN_LOOP:\n while ( total_num_writes < WRITE_STOP_COUNT){\n#pragma HLS PIPELINE II=1\n ap_uint<(32)> key = key_stream.read();\n uint32_t hash = MurmurHash3_x86_32(key, hash_idx);\n hash %= ( (BV_LENGTH-1)/(3) + 1);\n hash_stream.write(hash);\n total_num_writes++;\n }\n}\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "computeHash_Feeder": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n){\n\n\n#pragma HLS disaggregate variable = key_in_stream\n#pragma HLS interface ap_fifo port = key_in_stream._\n#pragma HLS aggregate variable = key_in_stream._ bit\n#pragma HLS interface ap_fifo port = key_in_stream._peek\n#pragma HLS aggregate variable = key_in_stream._peek bit\nvoid(key_in_stream._.empty());\nvoid(key_in_stream._peek.empty());\n\n#pragma HLS disaggregate variable = key_out_stream\n#pragma HLS array_partition variable = key_out_stream complete\n#pragma HLS interface ap_fifo port = key_out_stream[0]._\n#pragma HLS aggregate variable = key_out_stream[0]._ bit\nvoid(key_out_stream[0]._.full());\n#pragma HLS interface ap_fifo port = key_out_stream[1]._\n#pragma HLS aggregate variable = key_out_stream[1]._ bit\nvoid(key_out_stream[1]._.full());\n#pragma HLS interface ap_fifo port = key_out_stream[2]._\n#pragma HLS aggregate variable = key_out_stream[2]._ bit\nvoid(key_out_stream[2]._.full());\n\n const int READ_STOP_COUNT = KEYPAIRS_PER_STM;\n const int WRITE_STOP_COUNT = KEYPAIRS_PER_STM*(3);\n int total_num_reads = 0;\n int total_num_writes = 0;\n int input_idx = 0;\n ap_uint<(32)> key;\n bool key_written[(3)];\n#pragma HLS ARRAY_PARTITION variable=key_written dim=0 complete\n INIT_KEY_WRITTEN:\n for (int i = 0; i < (3); ++i) {\n key_written[i] = 1;\n }\n while (total_num_reads < READ_STOP_COUNT ||\n total_num_writes < WRITE_STOP_COUNT\n ) {\n#pragma HLS PIPELINE II=1\n bool do_read = 1;\n HASH_RD_LOOP:\n for(int hash_idx = 0; hash_idx < (3); ++hash_idx){\n if (key_written[hash_idx] == 0) {\n do_read = 0;\n }\n }\n if (do_read &&\n input_idx < KEYPAIRS_PER_STM\n ){\n ///////////////////////////////////\n // READ LOGIC:\n // NOTE: This blocking read is ok because we only have one input stream\n key = key_in_stream.read();\n total_num_reads++;\n input_idx++;\n for (int j = 0; j < (3); ++j) {\n key_written[j] = 0;\n }\n }\n ///////////////////////////////////\n // WRITE LOGIC:\n for (int hash_idx = 0; hash_idx < (3); ++hash_idx) {\n#pragma HLS UNROLL\n if (key_written[hash_idx] == 0) {\n if (key_out_stream[hash_idx].try_write(key)) {\n total_num_writes++;\n key_written[hash_idx] = 1;\n }\n }\n }\n }\n return;\n}\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n){\n\n\n#pragma HLS disaggregate variable = key_in_stream\n#pragma HLS interface ap_fifo port = key_in_stream._\n#pragma HLS aggregate variable = key_in_stream._ bit\n#pragma HLS interface ap_fifo port = key_in_stream._peek\n#pragma HLS aggregate variable = key_in_stream._peek bit\nvoid(key_in_stream._.empty());\nvoid(key_in_stream._peek.empty());\n\n#pragma HLS disaggregate variable = key_out_stream\n#pragma HLS array_partition variable = key_out_stream complete\n#pragma HLS interface ap_fifo port = key_out_stream[0]._\n#pragma HLS aggregate variable = key_out_stream[0]._ bit\nvoid(key_out_stream[0]._.full());\n#pragma HLS interface ap_fifo port = key_out_stream[1]._\n#pragma HLS aggregate variable = key_out_stream[1]._ bit\nvoid(key_out_stream[1]._.full());\n#pragma HLS interface ap_fifo port = key_out_stream[2]._\n#pragma HLS aggregate variable = key_out_stream[2]._ bit\nvoid(key_out_stream[2]._.full());\n\n const int READ_STOP_COUNT = KEYPAIRS_PER_STM;\n const int WRITE_STOP_COUNT = KEYPAIRS_PER_STM*(3);\n int total_num_reads = 0;\n int total_num_writes = 0;\n int input_idx = 0;\n ap_uint<(32)> key;\n bool key_written[(3)];\n#pragma HLS ARRAY_PARTITION variable=key_written dim=0 complete\n INIT_KEY_WRITTEN:\n for (int i = 0; i < (3); ++i) {\n key_written[i] = 1;\n }\n while (total_num_reads < READ_STOP_COUNT ||\n total_num_writes < WRITE_STOP_COUNT\n ) {\n#pragma HLS PIPELINE II=1\n bool do_read = 1;\n HASH_RD_LOOP:\n for(int hash_idx = 0; hash_idx < (3); ++hash_idx){\n if (key_written[hash_idx] == 0) {\n do_read = 0;\n }\n }\n if (do_read &&\n input_idx < KEYPAIRS_PER_STM\n ){\n ///////////////////////////////////\n // READ LOGIC:\n // NOTE: This blocking read is ok because we only have one input stream\n key = key_in_stream.read();\n total_num_reads++;\n input_idx++;\n for (int j = 0; j < (3); ++j) {\n key_written[j] = 0;\n }\n }\n ///////////////////////////////////\n // WRITE LOGIC:\n for (int hash_idx = 0; hash_idx < (3); ++hash_idx) {\n#pragma HLS UNROLL\n if (key_written[hash_idx] == 0) {\n if (key_out_stream[hash_idx].try_write(key)) {\n total_num_writes++;\n key_written[hash_idx] = 1;\n }\n }\n }\n }\n return;\n}\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "loadBV": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n tapa::async_mmap & input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n){\n#pragma HLS disaggregate variable = input_bv\n#pragma HLS interface ap_fifo port = input_bv.read_addr._\n#pragma HLS aggregate variable = input_bv.read_addr._ bit\n#pragma HLS interface ap_fifo port = input_bv.read_data._\n#pragma HLS aggregate variable = input_bv.read_data._ bit\n#pragma HLS interface ap_fifo port = input_bv.write_addr._\n#pragma HLS aggregate variable = input_bv.write_addr._ bit\n#pragma HLS interface ap_fifo port = input_bv.write_data._\n#pragma HLS aggregate variable = input_bv.write_data._ bit\n#pragma HLS interface ap_fifo port = input_bv.write_resp._\n#pragma HLS aggregate variable = input_bv.write_resp._ bit\n#pragma HLS disaggregate variable = input_bv .read_data\n#pragma HLS interface ap_fifo port = input_bv.read_data._peek\n#pragma HLS aggregate variable = input_bv.read_data._peek bit\n#pragma HLS disaggregate variable = input_bv .write_resp\n#pragma HLS interface ap_fifo port = input_bv.write_resp._peek\n#pragma HLS aggregate variable = input_bv.write_resp._peek bit\nvoid(input_bv.read_addr._.full());\nvoid(input_bv.read_data._.empty());\nvoid(input_bv.read_data._peek.empty());\nvoid(input_bv.write_addr._.full());\nvoid(input_bv.write_data._.full());\nvoid(input_bv.write_resp._.empty());\nvoid(input_bv.write_resp._peek.empty());\n\n#pragma HLS disaggregate variable = bv_load_stream_0\n#pragma HLS interface ap_fifo port = bv_load_stream_0._\n#pragma HLS aggregate variable = bv_load_stream_0._ bit\nvoid(bv_load_stream_0._.full());\n\n#pragma HLS disaggregate variable = bv_load_stream_1\n#pragma HLS interface ap_fifo port = bv_load_stream_1._\n#pragma HLS aggregate variable = bv_load_stream_1._ bit\nvoid(bv_load_stream_1._.full());\n\n#pragma HLS disaggregate variable = bv_load_stream_2\n#pragma HLS interface ap_fifo port = bv_load_stream_2._\n#pragma HLS aggregate variable = bv_load_stream_2._ bit\nvoid(bv_load_stream_2._.full());\n\n int section_idx = 0;\n BV_LOAD_DTYPE cur_bv_val;\n for (int i_req = 0, i_resp = 0;\n i_resp < ( (BV_LENGTH-1)/(BV_PACKED_BITWIDTH * (3)) + 1); )\n {\n#pragma HLS PIPELINE II=1\n if (i_req < ( (BV_LENGTH-1)/(BV_PACKED_BITWIDTH * (3)) + 1) && input_bv.read_addr.try_write(i_req)) {\n ++i_req;\n }\n if (!input_bv.read_data.empty()) {\n cur_bv_val = input_bv.read_data.read(nullptr);\n bv_load_stream_0.write(cur_bv_val.section0);\n bv_load_stream_1.write(cur_bv_val.section1);\n bv_load_stream_2.write(cur_bv_val.section2);\n ++i_resp;\n }\n }\n return;\n}\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n tapa::async_mmap & input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n){\n#pragma HLS disaggregate variable = input_bv\n#pragma HLS interface ap_fifo port = input_bv.read_addr._\n#pragma HLS aggregate variable = input_bv.read_addr._ bit\n#pragma HLS interface ap_fifo port = input_bv.read_data._\n#pragma HLS aggregate variable = input_bv.read_data._ bit\n#pragma HLS interface ap_fifo port = input_bv.write_addr._\n#pragma HLS aggregate variable = input_bv.write_addr._ bit\n#pragma HLS interface ap_fifo port = input_bv.write_data._\n#pragma HLS aggregate variable = input_bv.write_data._ bit\n#pragma HLS interface ap_fifo port = input_bv.write_resp._\n#pragma HLS aggregate variable = input_bv.write_resp._ bit\n#pragma HLS disaggregate variable = input_bv .read_data\n#pragma HLS interface ap_fifo port = input_bv.read_data._peek\n#pragma HLS aggregate variable = input_bv.read_data._peek bit\n#pragma HLS disaggregate variable = input_bv .write_resp\n#pragma HLS interface ap_fifo port = input_bv.write_resp._peek\n#pragma HLS aggregate variable = input_bv.write_resp._peek bit\nvoid(input_bv.read_addr._.full());\nvoid(input_bv.read_data._.empty());\nvoid(input_bv.read_data._peek.empty());\nvoid(input_bv.write_addr._.full());\nvoid(input_bv.write_data._.full());\nvoid(input_bv.write_resp._.empty());\nvoid(input_bv.write_resp._peek.empty());\n\n#pragma HLS disaggregate variable = bv_load_stream_0\n#pragma HLS interface ap_fifo port = bv_load_stream_0._\n#pragma HLS aggregate variable = bv_load_stream_0._ bit\nvoid(bv_load_stream_0._.full());\n\n#pragma HLS disaggregate variable = bv_load_stream_1\n#pragma HLS interface ap_fifo port = bv_load_stream_1._\n#pragma HLS aggregate variable = bv_load_stream_1._ bit\nvoid(bv_load_stream_1._.full());\n\n#pragma HLS disaggregate variable = bv_load_stream_2\n#pragma HLS interface ap_fifo port = bv_load_stream_2._\n#pragma HLS aggregate variable = bv_load_stream_2._ bit\nvoid(bv_load_stream_2._.full());\n\n int section_idx = 0;\n BV_LOAD_DTYPE cur_bv_val;\n for (int i_req = 0, i_resp = 0;\n i_resp < ( (BV_LENGTH-1)/(BV_PACKED_BITWIDTH * (3)) + 1); )\n {\n#pragma HLS PIPELINE II=1\n if (i_req < ( (BV_LENGTH-1)/(BV_PACKED_BITWIDTH * (3)) + 1) && input_bv.read_addr.try_write(i_req)) {\n ++i_req;\n }\n if (!input_bv.read_data.empty()) {\n cur_bv_val = input_bv.read_data.read(nullptr);\n bv_load_stream_0.write(cur_bv_val.section0);\n bv_load_stream_1.write(cur_bv_val.section1);\n bv_load_stream_2.write(cur_bv_val.section2);\n ++i_resp;\n }\n }\n return;\n}\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "loadKey": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n tapa::async_mmap & key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n){\n#pragma HLS disaggregate variable = key_in\n#pragma HLS interface ap_fifo port = key_in.read_addr._\n#pragma HLS aggregate variable = key_in.read_addr._ bit\n#pragma HLS interface ap_fifo port = key_in.read_data._\n#pragma HLS aggregate variable = key_in.read_data._ bit\n#pragma HLS interface ap_fifo port = key_in.write_addr._\n#pragma HLS aggregate variable = key_in.write_addr._ bit\n#pragma HLS interface ap_fifo port = key_in.write_data._\n#pragma HLS aggregate variable = key_in.write_data._ bit\n#pragma HLS interface ap_fifo port = key_in.write_resp._\n#pragma HLS aggregate variable = key_in.write_resp._ bit\n#pragma HLS disaggregate variable = key_in .read_data\n#pragma HLS interface ap_fifo port = key_in.read_data._peek\n#pragma HLS aggregate variable = key_in.read_data._peek bit\n#pragma HLS disaggregate variable = key_in .write_resp\n#pragma HLS interface ap_fifo port = key_in.write_resp._peek\n#pragma HLS aggregate variable = key_in.write_resp._peek bit\nvoid(key_in.read_addr._.full());\nvoid(key_in.read_data._.empty());\nvoid(key_in.read_data._peek.empty());\nvoid(key_in.write_addr._.full());\nvoid(key_in.write_data._.full());\nvoid(key_in.write_resp._.empty());\nvoid(key_in.write_resp._peek.empty());\n\n#pragma HLS disaggregate variable = key_stream_kp0\n#pragma HLS array_partition variable = key_stream_kp0 complete\n#pragma HLS interface ap_fifo port = key_stream_kp0[0]._\n#pragma HLS aggregate variable = key_stream_kp0[0]._ bit\nvoid(key_stream_kp0[0]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp0[1]._\n#pragma HLS aggregate variable = key_stream_kp0[1]._ bit\nvoid(key_stream_kp0[1]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp0[2]._\n#pragma HLS aggregate variable = key_stream_kp0[2]._ bit\nvoid(key_stream_kp0[2]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp0[3]._\n#pragma HLS aggregate variable = key_stream_kp0[3]._ bit\nvoid(key_stream_kp0[3]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp0[4]._\n#pragma HLS aggregate variable = key_stream_kp0[4]._ bit\nvoid(key_stream_kp0[4]._.full());\n\n#pragma HLS disaggregate variable = key_stream_kp1\n#pragma HLS array_partition variable = key_stream_kp1 complete\n#pragma HLS interface ap_fifo port = key_stream_kp1[0]._\n#pragma HLS aggregate variable = key_stream_kp1[0]._ bit\nvoid(key_stream_kp1[0]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp1[1]._\n#pragma HLS aggregate variable = key_stream_kp1[1]._ bit\nvoid(key_stream_kp1[1]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp1[2]._\n#pragma HLS aggregate variable = key_stream_kp1[2]._ bit\nvoid(key_stream_kp1[2]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp1[3]._\n#pragma HLS aggregate variable = key_stream_kp1[3]._ bit\nvoid(key_stream_kp1[3]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp1[4]._\n#pragma HLS aggregate variable = key_stream_kp1[4]._ bit\nvoid(key_stream_kp1[4]._.full());\n\n LOAD_DTYPE cur_load;\n for (int i_req = 0, i_resp = 0;\n i_resp < KEYPAIRS_PER_STM; )\n {\n#pragma HLS PIPELINE II=1\n if (i_req < KEYPAIRS_PER_STM && key_in.read_addr.try_write(i_req)) {\n ++i_req;\n }\n if (!key_in.read_data.empty()) {\n cur_load = key_in.read_data.read(nullptr);\n key_stream_kp0[0].write(cur_load.s0_k0); key_stream_kp1[0].write(cur_load.s0_k1);\n key_stream_kp0[1].write(cur_load.s1_k0); key_stream_kp1[1].write(cur_load.s1_k1);\n key_stream_kp0[2].write(cur_load.s2_k0); key_stream_kp1[2].write(cur_load.s2_k1);\n key_stream_kp0[3].write(cur_load.s3_k0); key_stream_kp1[3].write(cur_load.s3_k1);\n key_stream_kp0[4].write(cur_load.s4_k0); key_stream_kp1[4].write(cur_load.s4_k1);\n ++i_resp;\n }\n }\n return;\n}\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n tapa::async_mmap & key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n){\n#pragma HLS disaggregate variable = key_in\n#pragma HLS interface ap_fifo port = key_in.read_addr._\n#pragma HLS aggregate variable = key_in.read_addr._ bit\n#pragma HLS interface ap_fifo port = key_in.read_data._\n#pragma HLS aggregate variable = key_in.read_data._ bit\n#pragma HLS interface ap_fifo port = key_in.write_addr._\n#pragma HLS aggregate variable = key_in.write_addr._ bit\n#pragma HLS interface ap_fifo port = key_in.write_data._\n#pragma HLS aggregate variable = key_in.write_data._ bit\n#pragma HLS interface ap_fifo port = key_in.write_resp._\n#pragma HLS aggregate variable = key_in.write_resp._ bit\n#pragma HLS disaggregate variable = key_in .read_data\n#pragma HLS interface ap_fifo port = key_in.read_data._peek\n#pragma HLS aggregate variable = key_in.read_data._peek bit\n#pragma HLS disaggregate variable = key_in .write_resp\n#pragma HLS interface ap_fifo port = key_in.write_resp._peek\n#pragma HLS aggregate variable = key_in.write_resp._peek bit\nvoid(key_in.read_addr._.full());\nvoid(key_in.read_data._.empty());\nvoid(key_in.read_data._peek.empty());\nvoid(key_in.write_addr._.full());\nvoid(key_in.write_data._.full());\nvoid(key_in.write_resp._.empty());\nvoid(key_in.write_resp._peek.empty());\n\n#pragma HLS disaggregate variable = key_stream_kp0\n#pragma HLS array_partition variable = key_stream_kp0 complete\n#pragma HLS interface ap_fifo port = key_stream_kp0[0]._\n#pragma HLS aggregate variable = key_stream_kp0[0]._ bit\nvoid(key_stream_kp0[0]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp0[1]._\n#pragma HLS aggregate variable = key_stream_kp0[1]._ bit\nvoid(key_stream_kp0[1]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp0[2]._\n#pragma HLS aggregate variable = key_stream_kp0[2]._ bit\nvoid(key_stream_kp0[2]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp0[3]._\n#pragma HLS aggregate variable = key_stream_kp0[3]._ bit\nvoid(key_stream_kp0[3]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp0[4]._\n#pragma HLS aggregate variable = key_stream_kp0[4]._ bit\nvoid(key_stream_kp0[4]._.full());\n\n#pragma HLS disaggregate variable = key_stream_kp1\n#pragma HLS array_partition variable = key_stream_kp1 complete\n#pragma HLS interface ap_fifo port = key_stream_kp1[0]._\n#pragma HLS aggregate variable = key_stream_kp1[0]._ bit\nvoid(key_stream_kp1[0]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp1[1]._\n#pragma HLS aggregate variable = key_stream_kp1[1]._ bit\nvoid(key_stream_kp1[1]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp1[2]._\n#pragma HLS aggregate variable = key_stream_kp1[2]._ bit\nvoid(key_stream_kp1[2]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp1[3]._\n#pragma HLS aggregate variable = key_stream_kp1[3]._ bit\nvoid(key_stream_kp1[3]._.full());\n#pragma HLS interface ap_fifo port = key_stream_kp1[4]._\n#pragma HLS aggregate variable = key_stream_kp1[4]._ bit\nvoid(key_stream_kp1[4]._.full());\n\n LOAD_DTYPE cur_load;\n for (int i_req = 0, i_resp = 0;\n i_resp < KEYPAIRS_PER_STM; )\n {\n#pragma HLS PIPELINE II=1\n if (i_req < KEYPAIRS_PER_STM && key_in.read_addr.try_write(i_req)) {\n ++i_req;\n }\n if (!key_in.read_data.empty()) {\n cur_load = key_in.read_data.read(nullptr);\n key_stream_kp0[0].write(cur_load.s0_k0); key_stream_kp1[0].write(cur_load.s0_k1);\n key_stream_kp0[1].write(cur_load.s1_k0); key_stream_kp1[1].write(cur_load.s1_k1);\n key_stream_kp0[2].write(cur_load.s2_k0); key_stream_kp1[2].write(cur_load.s2_k1);\n key_stream_kp0[3].write(cur_load.s3_k0); key_stream_kp1[3].write(cur_load.s3_k1);\n key_stream_kp0[4].write(cur_load.s4_k0); key_stream_kp1[4].write(cur_load.s4_k1);\n ++i_resp;\n }\n }\n return;\n}\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "packOutput": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) {\n\n\n#pragma HLS disaggregate variable = aggregate_stream\n#pragma HLS interface ap_fifo port = aggregate_stream._\n#pragma HLS aggregate variable = aggregate_stream._ bit\n#pragma HLS interface ap_fifo port = aggregate_stream._peek\n#pragma HLS aggregate variable = aggregate_stream._peek bit\nvoid(aggregate_stream._.empty());\nvoid(aggregate_stream._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream\n#pragma HLS interface ap_fifo port = packed_outputs_stream._\n#pragma HLS aggregate variable = packed_outputs_stream._ bit\nvoid(packed_outputs_stream._.full());\n\n int pk_idx;\n ap_uint<((32))> packed;\n ap_uint val;\n for (int i = 0; i < KEYPAIRS_PER_STM; ++i) {\n pk_idx = i % ((32));\n val = aggregate_stream.read();\n packed.range(pk_idx, pk_idx) = val.range(0, 0);\n if (pk_idx == ((32)) - 1){\n packed_outputs_stream.write(packed);\n packed = 0;\n }\n }\n}\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) {\n\n\n#pragma HLS disaggregate variable = aggregate_stream\n#pragma HLS interface ap_fifo port = aggregate_stream._\n#pragma HLS aggregate variable = aggregate_stream._ bit\n#pragma HLS interface ap_fifo port = aggregate_stream._peek\n#pragma HLS aggregate variable = aggregate_stream._peek bit\nvoid(aggregate_stream._.empty());\nvoid(aggregate_stream._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream\n#pragma HLS interface ap_fifo port = packed_outputs_stream._\n#pragma HLS aggregate variable = packed_outputs_stream._ bit\nvoid(packed_outputs_stream._.full());\n\n int pk_idx;\n ap_uint<((32))> packed;\n ap_uint val;\n for (int i = 0; i < KEYPAIRS_PER_STM; ++i) {\n pk_idx = i % ((32));\n val = aggregate_stream.read();\n packed.range(pk_idx, pk_idx) = val.range(0, 0);\n if (pk_idx == ((32)) - 1){\n packed_outputs_stream.write(packed);\n packed = 0;\n }\n }\n}\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "queryResult_per_hash": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) {\n\n#pragma HLS disaggregate variable = bv_load_stream\n#pragma HLS interface ap_fifo port = bv_load_stream._\n#pragma HLS aggregate variable = bv_load_stream._ bit\n#pragma HLS interface ap_fifo port = bv_load_stream._peek\n#pragma HLS aggregate variable = bv_load_stream._peek bit\nvoid(bv_load_stream._.empty());\nvoid(bv_load_stream._peek.empty());\n\n#pragma HLS disaggregate variable = bv_lookup_stream_kp0\n#pragma HLS array_partition variable = bv_lookup_stream_kp0 complete\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[0]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[0]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[0]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[0]._peek bit\nvoid(bv_lookup_stream_kp0[0]._.empty());\nvoid(bv_lookup_stream_kp0[0]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[1]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[1]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[1]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[1]._peek bit\nvoid(bv_lookup_stream_kp0[1]._.empty());\nvoid(bv_lookup_stream_kp0[1]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[2]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[2]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[2]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[2]._peek bit\nvoid(bv_lookup_stream_kp0[2]._.empty());\nvoid(bv_lookup_stream_kp0[2]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[3]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[3]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[3]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[3]._peek bit\nvoid(bv_lookup_stream_kp0[3]._.empty());\nvoid(bv_lookup_stream_kp0[3]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[4]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[4]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[4]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[4]._peek bit\nvoid(bv_lookup_stream_kp0[4]._.empty());\nvoid(bv_lookup_stream_kp0[4]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[5]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[5]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[5]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[5]._peek bit\nvoid(bv_lookup_stream_kp0[5]._.empty());\nvoid(bv_lookup_stream_kp0[5]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[6]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[6]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[6]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[6]._peek bit\nvoid(bv_lookup_stream_kp0[6]._.empty());\nvoid(bv_lookup_stream_kp0[6]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[7]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[7]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[7]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[7]._peek bit\nvoid(bv_lookup_stream_kp0[7]._.empty());\nvoid(bv_lookup_stream_kp0[7]._peek.empty());\n\n#pragma HLS disaggregate variable = bv_lookup_stream_kp1\n#pragma HLS array_partition variable = bv_lookup_stream_kp1 complete\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[0]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[0]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[0]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[0]._peek bit\nvoid(bv_lookup_stream_kp1[0]._.empty());\nvoid(bv_lookup_stream_kp1[0]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[1]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[1]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[1]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[1]._peek bit\nvoid(bv_lookup_stream_kp1[1]._.empty());\nvoid(bv_lookup_stream_kp1[1]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[2]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[2]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[2]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[2]._peek bit\nvoid(bv_lookup_stream_kp1[2]._.empty());\nvoid(bv_lookup_stream_kp1[2]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[3]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[3]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[3]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[3]._peek bit\nvoid(bv_lookup_stream_kp1[3]._.empty());\nvoid(bv_lookup_stream_kp1[3]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[4]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[4]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[4]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[4]._peek bit\nvoid(bv_lookup_stream_kp1[4]._.empty());\nvoid(bv_lookup_stream_kp1[4]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[5]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[5]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[5]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[5]._peek bit\nvoid(bv_lookup_stream_kp1[5]._.empty());\nvoid(bv_lookup_stream_kp1[5]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[6]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[6]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[6]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[6]._peek bit\nvoid(bv_lookup_stream_kp1[6]._.empty());\nvoid(bv_lookup_stream_kp1[6]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[7]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[7]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[7]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[7]._peek bit\nvoid(bv_lookup_stream_kp1[7]._.empty());\nvoid(bv_lookup_stream_kp1[7]._peek.empty());\n\n#pragma HLS disaggregate variable = query_bv_packed_stream_kp0\n#pragma HLS array_partition variable = query_bv_packed_stream_kp0 complete\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[0]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[0]._ bit\nvoid(query_bv_packed_stream_kp0[0]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[1]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[1]._ bit\nvoid(query_bv_packed_stream_kp0[1]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[2]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[2]._ bit\nvoid(query_bv_packed_stream_kp0[2]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[3]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[3]._ bit\nvoid(query_bv_packed_stream_kp0[3]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[4]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[4]._ bit\nvoid(query_bv_packed_stream_kp0[4]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[5]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[5]._ bit\nvoid(query_bv_packed_stream_kp0[5]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[6]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[6]._ bit\nvoid(query_bv_packed_stream_kp0[6]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[7]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[7]._ bit\nvoid(query_bv_packed_stream_kp0[7]._.full());\n\n#pragma HLS disaggregate variable = query_bv_packed_stream_kp1\n#pragma HLS array_partition variable = query_bv_packed_stream_kp1 complete\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[0]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[0]._ bit\nvoid(query_bv_packed_stream_kp1[0]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[1]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[1]._ bit\nvoid(query_bv_packed_stream_kp1[1]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[2]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[2]._ bit\nvoid(query_bv_packed_stream_kp1[2]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[3]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[3]._ bit\nvoid(query_bv_packed_stream_kp1[3]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[4]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[4]._ bit\nvoid(query_bv_packed_stream_kp1[4]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[5]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[5]._ bit\nvoid(query_bv_packed_stream_kp1[5]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[6]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[6]._ bit\nvoid(query_bv_packed_stream_kp1[6]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[7]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[7]._ bit\nvoid(query_bv_packed_stream_kp1[7]._.full());\n\n const int MAX_NUM_WRITES = (5)*KEYS_PER_STM;\n int num_writes = 0;\n int num_reads = 0;\n ap_uint bv_buf_BRAMS[( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)][( (BV_LENGTH-1)/((3)*BV_PACKED_BITWIDTH*(8) /* each sub bv is further partitioned into this chunks*/) + 1)];\n#pragma HLS BIND_STORAGE variable=bv_buf_BRAMS type=RAM_T2P impl=bram\n#pragma HLS ARRAY_PARTITION variable=bv_buf_BRAMS dim=1 complete\n ap_uint bv_buf_URAMS[((8) /* each sub bv is further partitioned into this chunks*/ / 2)][( (BV_LENGTH-1)/((3)*BV_PACKED_BITWIDTH*(8) /* each sub bv is further partitioned into this chunks*/) + 1)];\n#pragma HLS BIND_STORAGE variable=bv_buf_URAMS type=RAM_T2P impl=uram\n#pragma HLS ARRAY_PARTITION variable=bv_buf_URAMS dim=1 complete\n ap_uint cur_bv_val;\n typedef struct {\n ap_uint<1> valid;\n BV_PLUS_METADATA_PACKED_DTYPE data;\n } TO_WRITE_DTYPE;\n TO_WRITE_DTYPE bram_queried_vals_buf[( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)][2];\n#pragma HLS ARRAY_PARTITION variable=bram_queried_vals_buf dim=0 complete\n TO_WRITE_DTYPE uram_queried_vals_buf[((8) /* each sub bv is further partitioned into this chunks*/ / 2)][2];\n#pragma HLS ARRAY_PARTITION variable=uram_queried_vals_buf dim=0 complete\n INIT_BRAM_QUERIED_VALS_BUF:\n for (int j = 0; j < ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1); ++j) {\n#pragma HLS UNROLL\n bram_queried_vals_buf[j][0].valid=0;\n bram_queried_vals_buf[j][1].valid=0;\n }\n INIT_URAM_QUERIED_VALS_BUF:\n for (int j = 0; j < ((8) /* each sub bv is further partitioned into this chunks*/ / 2); ++j) {\n#pragma HLS UNROLL\n uram_queried_vals_buf[j][0].valid=0;\n uram_queried_vals_buf[j][1].valid=0;\n }\n LOAD_BV_VALUES:\n for (int i = 0; i < ( (BV_LENGTH-1)/((3)*BV_PACKED_BITWIDTH) + 1); ++i) {\n#pragma HLS PIPELINE II=1\n cur_bv_val = bv_load_stream.read();\n int partition_idx = i/( (BV_LENGTH-1)/((3)*BV_PACKED_BITWIDTH*(8) /* each sub bv is further partitioned into this chunks*/) + 1);\n int element_idx = i%( (BV_LENGTH-1)/((3)*BV_PACKED_BITWIDTH*(8) /* each sub bv is further partitioned into this chunks*/) + 1);\n if (partition_idx < ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)) {\n bv_buf_BRAMS[partition_idx][element_idx] = cur_bv_val;\n }\n else {\n bv_buf_URAMS[partition_idx-( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)][element_idx] = cur_bv_val;\n }\n }\n PROCESS_QUERIES:\n while (num_writes < MAX_NUM_WRITES){\n#pragma HLS PIPELINE II=1\n BV_BRAM_PARTITION_LOOP:\n for (int bram_partition_idx = 0; bram_partition_idx < ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1); ++bram_partition_idx) {\n#pragma HLS UNROLL\n //////////////////////////////////////////////////////////\n // READ LOGIC\n // READ PORT 0\n if (!bv_lookup_stream_kp0[bram_partition_idx].empty() &&\n !bram_queried_vals_buf[bram_partition_idx][0].valid)\n {\n PACKED_HASH_DTYPE packed_hash;\n METADATA_DTYPE cur_metadata;\n ap_uint bv_lookup_idx;\n ap_uint cur_bv_val;\n BV_PLUS_METADATA_PACKED_DTYPE data_to_write;\n ap_uint bv_outer_idx;\n ap_uint bv_inner_idx;\n packed_hash = bv_lookup_stream_kp0[bram_partition_idx].read();\n // Unpack the values\n cur_metadata = packed_hash.md;\n bv_lookup_idx = packed_hash.hash;\n // Read the bitvector\n bv_outer_idx = bv_lookup_idx/BV_PACKED_BITWIDTH;\n bv_inner_idx = bv_lookup_idx%BV_PACKED_BITWIDTH;\n cur_bv_val.range(0, 0) =\n bv_buf_BRAMS[bram_partition_idx][bv_outer_idx].range(bv_inner_idx, bv_inner_idx);\n // Pack final payload\n data_to_write.md = cur_metadata;\n data_to_write.bv_val = cur_bv_val;\n bram_queried_vals_buf[bram_partition_idx][0].valid = 1;\n bram_queried_vals_buf[bram_partition_idx][0].data = data_to_write;\n }\n // READ PORT 1\n if (!bv_lookup_stream_kp1[bram_partition_idx].empty() &&\n !bram_queried_vals_buf[bram_partition_idx][1].valid)\n {\n PACKED_HASH_DTYPE packed_hash;\n METADATA_DTYPE cur_metadata;\n ap_uint bv_lookup_idx;\n ap_uint cur_bv_val;\n BV_PLUS_METADATA_PACKED_DTYPE data_to_write;\n ap_uint bv_outer_idx;\n ap_uint bv_inner_idx;\n packed_hash = bv_lookup_stream_kp1[bram_partition_idx].read();\n // Unpack the values\n cur_metadata = packed_hash.md;\n bv_lookup_idx = packed_hash.hash;\n // Read the bitvector\n bv_outer_idx = bv_lookup_idx/BV_PACKED_BITWIDTH;\n bv_inner_idx = bv_lookup_idx%BV_PACKED_BITWIDTH;\n cur_bv_val.range(0, 0) =\n bv_buf_BRAMS[bram_partition_idx][bv_outer_idx].range(bv_inner_idx, bv_inner_idx);\n // Pack final payload\n data_to_write.md = cur_metadata;\n data_to_write.bv_val = cur_bv_val;\n bram_queried_vals_buf[bram_partition_idx][1].valid = 1;\n bram_queried_vals_buf[bram_partition_idx][1].data = data_to_write;\n }\n //////////////////////////////////////////////////////////\n // WRITE LOGIC\n // WRITE PORT 0\n if (bram_queried_vals_buf[bram_partition_idx][0].valid &&\n query_bv_packed_stream_kp0[bram_partition_idx].try_write(\n bram_queried_vals_buf[bram_partition_idx][0].data\n )\n ) {\n ++num_writes;\n bram_queried_vals_buf[bram_partition_idx][0].valid = 0;\n }\n // WRITE PORT 1\n if (bram_queried_vals_buf[bram_partition_idx][1].valid &&\n query_bv_packed_stream_kp1[bram_partition_idx].try_write(\n bram_queried_vals_buf[bram_partition_idx][1].data\n )\n ) {\n ++num_writes;\n bram_queried_vals_buf[bram_partition_idx][1].valid = 0;\n }\n }\n BV_URAM_PARTITION_LOOP:\n for (int uram_partition_idx = 0; uram_partition_idx < ((8) /* each sub bv is further partitioned into this chunks*/ / 2); ++uram_partition_idx) {\n#pragma HLS UNROLL\n //////////////////////////////////////////////////////////\n // READ LOGIC\n // READ PORT 0\n if (!bv_lookup_stream_kp0[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].empty() &&\n !uram_queried_vals_buf[uram_partition_idx][0].valid)\n {\n PACKED_HASH_DTYPE packed_hash;\n METADATA_DTYPE cur_metadata;\n ap_uint bv_lookup_idx;\n ap_uint cur_bv_val;\n BV_PLUS_METADATA_PACKED_DTYPE data_to_write;\n ap_uint bv_outer_idx;\n ap_uint bv_inner_idx;\n packed_hash = bv_lookup_stream_kp0[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].read();\n // Unpack the values\n cur_metadata = packed_hash.md;\n bv_lookup_idx = packed_hash.hash;\n // Read the bitvector\n bv_outer_idx = bv_lookup_idx/BV_PACKED_BITWIDTH;\n bv_inner_idx = bv_lookup_idx%BV_PACKED_BITWIDTH;\n cur_bv_val.range(0, 0) =\n bv_buf_URAMS[uram_partition_idx][bv_outer_idx].range(bv_inner_idx, bv_inner_idx);\n // Pack final payload\n data_to_write.md = cur_metadata;\n data_to_write.bv_val = cur_bv_val;\n uram_queried_vals_buf[uram_partition_idx][0].valid = 1;\n uram_queried_vals_buf[uram_partition_idx][0].data = data_to_write;\n }\n // READ PORT 1\n if (!bv_lookup_stream_kp1[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].empty() &&\n !uram_queried_vals_buf[uram_partition_idx][1].valid)\n {\n PACKED_HASH_DTYPE packed_hash;\n METADATA_DTYPE cur_metadata;\n ap_uint bv_lookup_idx;\n ap_uint cur_bv_val;\n BV_PLUS_METADATA_PACKED_DTYPE data_to_write;\n ap_uint bv_outer_idx;\n ap_uint bv_inner_idx;\n packed_hash = bv_lookup_stream_kp1[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].read();\n // Unpack the values\n cur_metadata = packed_hash.md;\n bv_lookup_idx = packed_hash.hash;\n // Read the bitvector\n bv_outer_idx = bv_lookup_idx/BV_PACKED_BITWIDTH;\n bv_inner_idx = bv_lookup_idx%BV_PACKED_BITWIDTH;\n cur_bv_val.range(0, 0) =\n bv_buf_URAMS[uram_partition_idx][bv_outer_idx].range(bv_inner_idx, bv_inner_idx);\n // Pack final payload\n data_to_write.md = cur_metadata;\n data_to_write.bv_val = cur_bv_val;\n uram_queried_vals_buf[uram_partition_idx][1].valid = 1;\n uram_queried_vals_buf[uram_partition_idx][1].data = data_to_write;\n }\n //////////////////////////////////////////////////////////\n // WRITE LOGIC\n // WRITE PORT 0\n if (uram_queried_vals_buf[uram_partition_idx][0].valid &&\n query_bv_packed_stream_kp0[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].try_write(\n uram_queried_vals_buf[uram_partition_idx][0].data\n )\n ) {\n ++num_writes;\n uram_queried_vals_buf[uram_partition_idx][0].valid = 0;\n }\n // WRITE PORT 1\n if (uram_queried_vals_buf[uram_partition_idx][1].valid &&\n query_bv_packed_stream_kp1[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].try_write(\n uram_queried_vals_buf[uram_partition_idx][1].data\n )\n ) {\n ++num_writes;\n uram_queried_vals_buf[uram_partition_idx][1].valid = 0;\n }\n }\n }\n return;\n}\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) {\n\n#pragma HLS disaggregate variable = bv_load_stream\n#pragma HLS interface ap_fifo port = bv_load_stream._\n#pragma HLS aggregate variable = bv_load_stream._ bit\n#pragma HLS interface ap_fifo port = bv_load_stream._peek\n#pragma HLS aggregate variable = bv_load_stream._peek bit\nvoid(bv_load_stream._.empty());\nvoid(bv_load_stream._peek.empty());\n\n#pragma HLS disaggregate variable = bv_lookup_stream_kp0\n#pragma HLS array_partition variable = bv_lookup_stream_kp0 complete\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[0]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[0]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[0]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[0]._peek bit\nvoid(bv_lookup_stream_kp0[0]._.empty());\nvoid(bv_lookup_stream_kp0[0]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[1]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[1]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[1]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[1]._peek bit\nvoid(bv_lookup_stream_kp0[1]._.empty());\nvoid(bv_lookup_stream_kp0[1]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[2]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[2]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[2]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[2]._peek bit\nvoid(bv_lookup_stream_kp0[2]._.empty());\nvoid(bv_lookup_stream_kp0[2]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[3]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[3]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[3]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[3]._peek bit\nvoid(bv_lookup_stream_kp0[3]._.empty());\nvoid(bv_lookup_stream_kp0[3]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[4]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[4]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[4]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[4]._peek bit\nvoid(bv_lookup_stream_kp0[4]._.empty());\nvoid(bv_lookup_stream_kp0[4]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[5]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[5]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[5]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[5]._peek bit\nvoid(bv_lookup_stream_kp0[5]._.empty());\nvoid(bv_lookup_stream_kp0[5]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[6]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[6]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[6]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[6]._peek bit\nvoid(bv_lookup_stream_kp0[6]._.empty());\nvoid(bv_lookup_stream_kp0[6]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[7]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[7]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp0[7]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp0[7]._peek bit\nvoid(bv_lookup_stream_kp0[7]._.empty());\nvoid(bv_lookup_stream_kp0[7]._peek.empty());\n\n#pragma HLS disaggregate variable = bv_lookup_stream_kp1\n#pragma HLS array_partition variable = bv_lookup_stream_kp1 complete\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[0]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[0]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[0]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[0]._peek bit\nvoid(bv_lookup_stream_kp1[0]._.empty());\nvoid(bv_lookup_stream_kp1[0]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[1]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[1]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[1]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[1]._peek bit\nvoid(bv_lookup_stream_kp1[1]._.empty());\nvoid(bv_lookup_stream_kp1[1]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[2]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[2]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[2]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[2]._peek bit\nvoid(bv_lookup_stream_kp1[2]._.empty());\nvoid(bv_lookup_stream_kp1[2]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[3]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[3]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[3]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[3]._peek bit\nvoid(bv_lookup_stream_kp1[3]._.empty());\nvoid(bv_lookup_stream_kp1[3]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[4]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[4]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[4]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[4]._peek bit\nvoid(bv_lookup_stream_kp1[4]._.empty());\nvoid(bv_lookup_stream_kp1[4]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[5]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[5]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[5]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[5]._peek bit\nvoid(bv_lookup_stream_kp1[5]._.empty());\nvoid(bv_lookup_stream_kp1[5]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[6]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[6]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[6]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[6]._peek bit\nvoid(bv_lookup_stream_kp1[6]._.empty());\nvoid(bv_lookup_stream_kp1[6]._peek.empty());\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[7]._\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[7]._ bit\n#pragma HLS interface ap_fifo port = bv_lookup_stream_kp1[7]._peek\n#pragma HLS aggregate variable = bv_lookup_stream_kp1[7]._peek bit\nvoid(bv_lookup_stream_kp1[7]._.empty());\nvoid(bv_lookup_stream_kp1[7]._peek.empty());\n\n#pragma HLS disaggregate variable = query_bv_packed_stream_kp0\n#pragma HLS array_partition variable = query_bv_packed_stream_kp0 complete\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[0]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[0]._ bit\nvoid(query_bv_packed_stream_kp0[0]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[1]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[1]._ bit\nvoid(query_bv_packed_stream_kp0[1]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[2]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[2]._ bit\nvoid(query_bv_packed_stream_kp0[2]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[3]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[3]._ bit\nvoid(query_bv_packed_stream_kp0[3]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[4]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[4]._ bit\nvoid(query_bv_packed_stream_kp0[4]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[5]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[5]._ bit\nvoid(query_bv_packed_stream_kp0[5]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[6]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[6]._ bit\nvoid(query_bv_packed_stream_kp0[6]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp0[7]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp0[7]._ bit\nvoid(query_bv_packed_stream_kp0[7]._.full());\n\n#pragma HLS disaggregate variable = query_bv_packed_stream_kp1\n#pragma HLS array_partition variable = query_bv_packed_stream_kp1 complete\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[0]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[0]._ bit\nvoid(query_bv_packed_stream_kp1[0]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[1]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[1]._ bit\nvoid(query_bv_packed_stream_kp1[1]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[2]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[2]._ bit\nvoid(query_bv_packed_stream_kp1[2]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[3]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[3]._ bit\nvoid(query_bv_packed_stream_kp1[3]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[4]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[4]._ bit\nvoid(query_bv_packed_stream_kp1[4]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[5]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[5]._ bit\nvoid(query_bv_packed_stream_kp1[5]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[6]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[6]._ bit\nvoid(query_bv_packed_stream_kp1[6]._.full());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream_kp1[7]._\n#pragma HLS aggregate variable = query_bv_packed_stream_kp1[7]._ bit\nvoid(query_bv_packed_stream_kp1[7]._.full());\n\n const int MAX_NUM_WRITES = (5)*KEYS_PER_STM;\n int num_writes = 0;\n int num_reads = 0;\n ap_uint bv_buf_BRAMS[( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)][( (BV_LENGTH-1)/((3)*BV_PACKED_BITWIDTH*(8) /* each sub bv is further partitioned into this chunks*/) + 1)];\n#pragma HLS BIND_STORAGE variable=bv_buf_BRAMS type=RAM_T2P impl=bram\n#pragma HLS ARRAY_PARTITION variable=bv_buf_BRAMS dim=1 complete\n ap_uint bv_buf_URAMS[((8) /* each sub bv is further partitioned into this chunks*/ / 2)][( (BV_LENGTH-1)/((3)*BV_PACKED_BITWIDTH*(8) /* each sub bv is further partitioned into this chunks*/) + 1)];\n#pragma HLS BIND_STORAGE variable=bv_buf_URAMS type=RAM_T2P impl=uram\n#pragma HLS ARRAY_PARTITION variable=bv_buf_URAMS dim=1 complete\n ap_uint cur_bv_val;\n typedef struct {\n ap_uint<1> valid;\n BV_PLUS_METADATA_PACKED_DTYPE data;\n } TO_WRITE_DTYPE;\n TO_WRITE_DTYPE bram_queried_vals_buf[( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)][2];\n#pragma HLS ARRAY_PARTITION variable=bram_queried_vals_buf dim=0 complete\n TO_WRITE_DTYPE uram_queried_vals_buf[((8) /* each sub bv is further partitioned into this chunks*/ / 2)][2];\n#pragma HLS ARRAY_PARTITION variable=uram_queried_vals_buf dim=0 complete\n INIT_BRAM_QUERIED_VALS_BUF:\n for (int j = 0; j < ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1); ++j) {\n#pragma HLS UNROLL\n bram_queried_vals_buf[j][0].valid=0;\n bram_queried_vals_buf[j][1].valid=0;\n }\n INIT_URAM_QUERIED_VALS_BUF:\n for (int j = 0; j < ((8) /* each sub bv is further partitioned into this chunks*/ / 2); ++j) {\n#pragma HLS UNROLL\n uram_queried_vals_buf[j][0].valid=0;\n uram_queried_vals_buf[j][1].valid=0;\n }\n LOAD_BV_VALUES:\n for (int i = 0; i < ( (BV_LENGTH-1)/((3)*BV_PACKED_BITWIDTH) + 1); ++i) {\n#pragma HLS PIPELINE II=1\n cur_bv_val = bv_load_stream.read();\n int partition_idx = i/( (BV_LENGTH-1)/((3)*BV_PACKED_BITWIDTH*(8) /* each sub bv is further partitioned into this chunks*/) + 1);\n int element_idx = i%( (BV_LENGTH-1)/((3)*BV_PACKED_BITWIDTH*(8) /* each sub bv is further partitioned into this chunks*/) + 1);\n if (partition_idx < ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)) {\n bv_buf_BRAMS[partition_idx][element_idx] = cur_bv_val;\n }\n else {\n bv_buf_URAMS[partition_idx-( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)][element_idx] = cur_bv_val;\n }\n }\n PROCESS_QUERIES:\n while (num_writes < MAX_NUM_WRITES){\n#pragma HLS PIPELINE II=1\n BV_BRAM_PARTITION_LOOP:\n for (int bram_partition_idx = 0; bram_partition_idx < ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1); ++bram_partition_idx) {\n#pragma HLS UNROLL\n //////////////////////////////////////////////////////////\n // READ LOGIC\n // READ PORT 0\n if (!bv_lookup_stream_kp0[bram_partition_idx].empty() &&\n !bram_queried_vals_buf[bram_partition_idx][0].valid)\n {\n PACKED_HASH_DTYPE packed_hash;\n METADATA_DTYPE cur_metadata;\n ap_uint bv_lookup_idx;\n ap_uint cur_bv_val;\n BV_PLUS_METADATA_PACKED_DTYPE data_to_write;\n ap_uint bv_outer_idx;\n ap_uint bv_inner_idx;\n packed_hash = bv_lookup_stream_kp0[bram_partition_idx].read();\n // Unpack the values\n cur_metadata = packed_hash.md;\n bv_lookup_idx = packed_hash.hash;\n // Read the bitvector\n bv_outer_idx = bv_lookup_idx/BV_PACKED_BITWIDTH;\n bv_inner_idx = bv_lookup_idx%BV_PACKED_BITWIDTH;\n cur_bv_val.range(0, 0) =\n bv_buf_BRAMS[bram_partition_idx][bv_outer_idx].range(bv_inner_idx, bv_inner_idx);\n // Pack final payload\n data_to_write.md = cur_metadata;\n data_to_write.bv_val = cur_bv_val;\n bram_queried_vals_buf[bram_partition_idx][0].valid = 1;\n bram_queried_vals_buf[bram_partition_idx][0].data = data_to_write;\n }\n // READ PORT 1\n if (!bv_lookup_stream_kp1[bram_partition_idx].empty() &&\n !bram_queried_vals_buf[bram_partition_idx][1].valid)\n {\n PACKED_HASH_DTYPE packed_hash;\n METADATA_DTYPE cur_metadata;\n ap_uint bv_lookup_idx;\n ap_uint cur_bv_val;\n BV_PLUS_METADATA_PACKED_DTYPE data_to_write;\n ap_uint bv_outer_idx;\n ap_uint bv_inner_idx;\n packed_hash = bv_lookup_stream_kp1[bram_partition_idx].read();\n // Unpack the values\n cur_metadata = packed_hash.md;\n bv_lookup_idx = packed_hash.hash;\n // Read the bitvector\n bv_outer_idx = bv_lookup_idx/BV_PACKED_BITWIDTH;\n bv_inner_idx = bv_lookup_idx%BV_PACKED_BITWIDTH;\n cur_bv_val.range(0, 0) =\n bv_buf_BRAMS[bram_partition_idx][bv_outer_idx].range(bv_inner_idx, bv_inner_idx);\n // Pack final payload\n data_to_write.md = cur_metadata;\n data_to_write.bv_val = cur_bv_val;\n bram_queried_vals_buf[bram_partition_idx][1].valid = 1;\n bram_queried_vals_buf[bram_partition_idx][1].data = data_to_write;\n }\n //////////////////////////////////////////////////////////\n // WRITE LOGIC\n // WRITE PORT 0\n if (bram_queried_vals_buf[bram_partition_idx][0].valid &&\n query_bv_packed_stream_kp0[bram_partition_idx].try_write(\n bram_queried_vals_buf[bram_partition_idx][0].data\n )\n ) {\n ++num_writes;\n bram_queried_vals_buf[bram_partition_idx][0].valid = 0;\n }\n // WRITE PORT 1\n if (bram_queried_vals_buf[bram_partition_idx][1].valid &&\n query_bv_packed_stream_kp1[bram_partition_idx].try_write(\n bram_queried_vals_buf[bram_partition_idx][1].data\n )\n ) {\n ++num_writes;\n bram_queried_vals_buf[bram_partition_idx][1].valid = 0;\n }\n }\n BV_URAM_PARTITION_LOOP:\n for (int uram_partition_idx = 0; uram_partition_idx < ((8) /* each sub bv is further partitioned into this chunks*/ / 2); ++uram_partition_idx) {\n#pragma HLS UNROLL\n //////////////////////////////////////////////////////////\n // READ LOGIC\n // READ PORT 0\n if (!bv_lookup_stream_kp0[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].empty() &&\n !uram_queried_vals_buf[uram_partition_idx][0].valid)\n {\n PACKED_HASH_DTYPE packed_hash;\n METADATA_DTYPE cur_metadata;\n ap_uint bv_lookup_idx;\n ap_uint cur_bv_val;\n BV_PLUS_METADATA_PACKED_DTYPE data_to_write;\n ap_uint bv_outer_idx;\n ap_uint bv_inner_idx;\n packed_hash = bv_lookup_stream_kp0[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].read();\n // Unpack the values\n cur_metadata = packed_hash.md;\n bv_lookup_idx = packed_hash.hash;\n // Read the bitvector\n bv_outer_idx = bv_lookup_idx/BV_PACKED_BITWIDTH;\n bv_inner_idx = bv_lookup_idx%BV_PACKED_BITWIDTH;\n cur_bv_val.range(0, 0) =\n bv_buf_URAMS[uram_partition_idx][bv_outer_idx].range(bv_inner_idx, bv_inner_idx);\n // Pack final payload\n data_to_write.md = cur_metadata;\n data_to_write.bv_val = cur_bv_val;\n uram_queried_vals_buf[uram_partition_idx][0].valid = 1;\n uram_queried_vals_buf[uram_partition_idx][0].data = data_to_write;\n }\n // READ PORT 1\n if (!bv_lookup_stream_kp1[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].empty() &&\n !uram_queried_vals_buf[uram_partition_idx][1].valid)\n {\n PACKED_HASH_DTYPE packed_hash;\n METADATA_DTYPE cur_metadata;\n ap_uint bv_lookup_idx;\n ap_uint cur_bv_val;\n BV_PLUS_METADATA_PACKED_DTYPE data_to_write;\n ap_uint bv_outer_idx;\n ap_uint bv_inner_idx;\n packed_hash = bv_lookup_stream_kp1[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].read();\n // Unpack the values\n cur_metadata = packed_hash.md;\n bv_lookup_idx = packed_hash.hash;\n // Read the bitvector\n bv_outer_idx = bv_lookup_idx/BV_PACKED_BITWIDTH;\n bv_inner_idx = bv_lookup_idx%BV_PACKED_BITWIDTH;\n cur_bv_val.range(0, 0) =\n bv_buf_URAMS[uram_partition_idx][bv_outer_idx].range(bv_inner_idx, bv_inner_idx);\n // Pack final payload\n data_to_write.md = cur_metadata;\n data_to_write.bv_val = cur_bv_val;\n uram_queried_vals_buf[uram_partition_idx][1].valid = 1;\n uram_queried_vals_buf[uram_partition_idx][1].data = data_to_write;\n }\n //////////////////////////////////////////////////////////\n // WRITE LOGIC\n // WRITE PORT 0\n if (uram_queried_vals_buf[uram_partition_idx][0].valid &&\n query_bv_packed_stream_kp0[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].try_write(\n uram_queried_vals_buf[uram_partition_idx][0].data\n )\n ) {\n ++num_writes;\n uram_queried_vals_buf[uram_partition_idx][0].valid = 0;\n }\n // WRITE PORT 1\n if (uram_queried_vals_buf[uram_partition_idx][1].valid &&\n query_bv_packed_stream_kp1[uram_partition_idx + ( ((8) /* each sub bv is further partitioned into this chunks*/-1)/2 + 1)].try_write(\n uram_queried_vals_buf[uram_partition_idx][1].data\n )\n ) {\n ++num_writes;\n uram_queried_vals_buf[uram_partition_idx][1].valid = 0;\n }\n }\n }\n return;\n}\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "shuffle_TtoS_per_hash": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n){\n\n\n#pragma HLS disaggregate variable = query_bv_packed_stream\n#pragma HLS array_partition variable = query_bv_packed_stream complete\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[0]._\n#pragma HLS aggregate variable = query_bv_packed_stream[0]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[0]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[0]._peek bit\nvoid(query_bv_packed_stream[0]._.empty());\nvoid(query_bv_packed_stream[0]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[1]._\n#pragma HLS aggregate variable = query_bv_packed_stream[1]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[1]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[1]._peek bit\nvoid(query_bv_packed_stream[1]._.empty());\nvoid(query_bv_packed_stream[1]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[2]._\n#pragma HLS aggregate variable = query_bv_packed_stream[2]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[2]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[2]._peek bit\nvoid(query_bv_packed_stream[2]._.empty());\nvoid(query_bv_packed_stream[2]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[3]._\n#pragma HLS aggregate variable = query_bv_packed_stream[3]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[3]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[3]._peek bit\nvoid(query_bv_packed_stream[3]._.empty());\nvoid(query_bv_packed_stream[3]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[4]._\n#pragma HLS aggregate variable = query_bv_packed_stream[4]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[4]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[4]._peek bit\nvoid(query_bv_packed_stream[4]._.empty());\nvoid(query_bv_packed_stream[4]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[5]._\n#pragma HLS aggregate variable = query_bv_packed_stream[5]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[5]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[5]._peek bit\nvoid(query_bv_packed_stream[5]._.empty());\nvoid(query_bv_packed_stream[5]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[6]._\n#pragma HLS aggregate variable = query_bv_packed_stream[6]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[6]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[6]._peek bit\nvoid(query_bv_packed_stream[6]._.empty());\nvoid(query_bv_packed_stream[6]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[7]._\n#pragma HLS aggregate variable = query_bv_packed_stream[7]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[7]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[7]._peek bit\nvoid(query_bv_packed_stream[7]._.empty());\nvoid(query_bv_packed_stream[7]._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream\n#pragma HLS array_partition variable = inter_shuffle_stream complete\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[0]._\n#pragma HLS aggregate variable = inter_shuffle_stream[0]._ bit\nvoid(inter_shuffle_stream[0]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[1]._\n#pragma HLS aggregate variable = inter_shuffle_stream[1]._ bit\nvoid(inter_shuffle_stream[1]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[2]._\n#pragma HLS aggregate variable = inter_shuffle_stream[2]._ bit\nvoid(inter_shuffle_stream[2]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[3]._\n#pragma HLS aggregate variable = inter_shuffle_stream[3]._ bit\nvoid(inter_shuffle_stream[3]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[4]._\n#pragma HLS aggregate variable = inter_shuffle_stream[4]._ bit\nvoid(inter_shuffle_stream[4]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[5]._\n#pragma HLS aggregate variable = inter_shuffle_stream[5]._ bit\nvoid(inter_shuffle_stream[5]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[6]._\n#pragma HLS aggregate variable = inter_shuffle_stream[6]._ bit\nvoid(inter_shuffle_stream[6]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[7]._\n#pragma HLS aggregate variable = inter_shuffle_stream[7]._ bit\nvoid(inter_shuffle_stream[7]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[8]._\n#pragma HLS aggregate variable = inter_shuffle_stream[8]._ bit\nvoid(inter_shuffle_stream[8]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[9]._\n#pragma HLS aggregate variable = inter_shuffle_stream[9]._ bit\nvoid(inter_shuffle_stream[9]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[10]._\n#pragma HLS aggregate variable = inter_shuffle_stream[10]._ bit\nvoid(inter_shuffle_stream[10]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[11]._\n#pragma HLS aggregate variable = inter_shuffle_stream[11]._ bit\nvoid(inter_shuffle_stream[11]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[12]._\n#pragma HLS aggregate variable = inter_shuffle_stream[12]._ bit\nvoid(inter_shuffle_stream[12]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[13]._\n#pragma HLS aggregate variable = inter_shuffle_stream[13]._ bit\nvoid(inter_shuffle_stream[13]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[14]._\n#pragma HLS aggregate variable = inter_shuffle_stream[14]._ bit\nvoid(inter_shuffle_stream[14]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[15]._\n#pragma HLS aggregate variable = inter_shuffle_stream[15]._ bit\nvoid(inter_shuffle_stream[15]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[16]._\n#pragma HLS aggregate variable = inter_shuffle_stream[16]._ bit\nvoid(inter_shuffle_stream[16]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[17]._\n#pragma HLS aggregate variable = inter_shuffle_stream[17]._ bit\nvoid(inter_shuffle_stream[17]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[18]._\n#pragma HLS aggregate variable = inter_shuffle_stream[18]._ bit\nvoid(inter_shuffle_stream[18]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[19]._\n#pragma HLS aggregate variable = inter_shuffle_stream[19]._ bit\nvoid(inter_shuffle_stream[19]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[20]._\n#pragma HLS aggregate variable = inter_shuffle_stream[20]._ bit\nvoid(inter_shuffle_stream[20]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[21]._\n#pragma HLS aggregate variable = inter_shuffle_stream[21]._ bit\nvoid(inter_shuffle_stream[21]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[22]._\n#pragma HLS aggregate variable = inter_shuffle_stream[22]._ bit\nvoid(inter_shuffle_stream[22]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[23]._\n#pragma HLS aggregate variable = inter_shuffle_stream[23]._ bit\nvoid(inter_shuffle_stream[23]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[24]._\n#pragma HLS aggregate variable = inter_shuffle_stream[24]._ bit\nvoid(inter_shuffle_stream[24]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[25]._\n#pragma HLS aggregate variable = inter_shuffle_stream[25]._ bit\nvoid(inter_shuffle_stream[25]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[26]._\n#pragma HLS aggregate variable = inter_shuffle_stream[26]._ bit\nvoid(inter_shuffle_stream[26]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[27]._\n#pragma HLS aggregate variable = inter_shuffle_stream[27]._ bit\nvoid(inter_shuffle_stream[27]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[28]._\n#pragma HLS aggregate variable = inter_shuffle_stream[28]._ bit\nvoid(inter_shuffle_stream[28]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[29]._\n#pragma HLS aggregate variable = inter_shuffle_stream[29]._ bit\nvoid(inter_shuffle_stream[29]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[30]._\n#pragma HLS aggregate variable = inter_shuffle_stream[30]._ bit\nvoid(inter_shuffle_stream[30]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[31]._\n#pragma HLS aggregate variable = inter_shuffle_stream[31]._ bit\nvoid(inter_shuffle_stream[31]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[32]._\n#pragma HLS aggregate variable = inter_shuffle_stream[32]._ bit\nvoid(inter_shuffle_stream[32]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[33]._\n#pragma HLS aggregate variable = inter_shuffle_stream[33]._ bit\nvoid(inter_shuffle_stream[33]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[34]._\n#pragma HLS aggregate variable = inter_shuffle_stream[34]._ bit\nvoid(inter_shuffle_stream[34]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[35]._\n#pragma HLS aggregate variable = inter_shuffle_stream[35]._ bit\nvoid(inter_shuffle_stream[35]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[36]._\n#pragma HLS aggregate variable = inter_shuffle_stream[36]._ bit\nvoid(inter_shuffle_stream[36]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[37]._\n#pragma HLS aggregate variable = inter_shuffle_stream[37]._ bit\nvoid(inter_shuffle_stream[37]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[38]._\n#pragma HLS aggregate variable = inter_shuffle_stream[38]._ bit\nvoid(inter_shuffle_stream[38]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[39]._\n#pragma HLS aggregate variable = inter_shuffle_stream[39]._ bit\nvoid(inter_shuffle_stream[39]._.full());\n\n typedef struct {\n ap_uint BV;\n ap_uint input_idx;\n bool valid;\n } PEEKED_DTYPE;\n //int next_output_idx[NUM_STM];\n //#pragma HLS ARRAY_PARTITION variable=next_output_idx dim=0 complete\n // This is a buffer for data from each partition.\n // We also introduce a NUM_STM dimension, otherwise we hang.\n PEEKED_DTYPE shuffle_peek_emulator[(8) /* each sub bv is further partitioned into this chunks*/][(5)];\n#pragma HLS ARRAY_PARTITION variable=shuffle_peek_emulator dim=0 complete\n //NEXT_OUTPUT_IDX_INIT:\n //for (int i = 0; i < NUM_STM; ++i) {\n //#pragma HLS UNROLL\n // next_output_idx[i] = 1;\n //}\n PEEK_EMULATOR_INITIALIZATION:\n for (int j=0; j<(8) /* each sub bv is further partitioned into this chunks*/; ++j){\n#pragma HLS UNROLL\n for (int k=0; k<(5); ++k) {\n#pragma HLS UNROLL\n shuffle_peek_emulator[j][k].BV = 0;\n shuffle_peek_emulator[j][k].input_idx = 0;\n shuffle_peek_emulator[j][k].valid = 0;\n }\n }\n while(1)\n {\n#pragma HLS PIPELINE II=1\n ////////////////////////////////////////////\n // READ LOGIC. Read from each partition stream\n ////////////////////////////////////////////\n RD_BV_PARTITION_LOOP:\n for (int partition_idx = 0;\n partition_idx < (8) /* each sub bv is further partitioned into this chunks*/;\n ++partition_idx)\n {\n#pragma HLS UNROLL\n // DATAPACKED TRANSFER:\n ap_uint cur_input_idx;\n ap_uint cur_strm_idx;\n ap_uint cur_bv_val;\n METADATA_DTYPE cur_metadata;\n BV_PLUS_METADATA_PACKED_DTYPE cur_packed_data;\n bool peek_success;\n peek_success = query_bv_packed_stream[partition_idx].try_peek(\n cur_packed_data\n );\n cur_metadata = cur_packed_data.md;\n cur_bv_val = cur_packed_data.bv_val;\n // Unpack metadata\n cur_strm_idx = cur_metadata.sidx;\n cur_input_idx = cur_metadata.iidx;\n // If the current \"peeked\" value is not valid, overwrite it\n // with valid data.\n if (peek_success &&\n shuffle_peek_emulator[partition_idx][cur_strm_idx].valid == 0\n )\n {\n query_bv_packed_stream[partition_idx].read();\n // Write it into the buffer\n shuffle_peek_emulator[partition_idx]\n [cur_strm_idx].valid = 1;\n shuffle_peek_emulator[partition_idx]\n [cur_strm_idx].BV = cur_bv_val;\n shuffle_peek_emulator[partition_idx]\n [cur_strm_idx].input_idx = cur_input_idx;\n }\n }\n ////////////////////////////////////////////\n // WRITE OUTPUTS from the shuffle-buffer\n ////////////////////////////////////////////\n WR_STM_LOOP:\n for (int strm_idx = 0; strm_idx < (5); ++strm_idx)\n {\n WR_BV_PARTITION_LOOP:\n for (int partition_idx = 0;\n partition_idx < (8) /* each sub bv is further partitioned into this chunks*/;\n ++partition_idx)\n {\n#pragma HLS UNROLL\n BV_PLUS_IIDX_PACKED_DTYPE outval;\n outval.bv_val = shuffle_peek_emulator[partition_idx][strm_idx].BV;\n outval.iidx = shuffle_peek_emulator[partition_idx][strm_idx].input_idx;\n if (shuffle_peek_emulator[partition_idx][strm_idx].valid == 1 &&\n inter_shuffle_stream[strm_idx*(8) /* each sub bv is further partitioned into this chunks*/ + partition_idx].try_write(outval)\n ) {\n shuffle_peek_emulator[partition_idx][strm_idx].valid = 0;\n }\n }\n }\n }\n return;\n}\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n){\n\n\n#pragma HLS disaggregate variable = query_bv_packed_stream\n#pragma HLS array_partition variable = query_bv_packed_stream complete\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[0]._\n#pragma HLS aggregate variable = query_bv_packed_stream[0]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[0]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[0]._peek bit\nvoid(query_bv_packed_stream[0]._.empty());\nvoid(query_bv_packed_stream[0]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[1]._\n#pragma HLS aggregate variable = query_bv_packed_stream[1]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[1]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[1]._peek bit\nvoid(query_bv_packed_stream[1]._.empty());\nvoid(query_bv_packed_stream[1]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[2]._\n#pragma HLS aggregate variable = query_bv_packed_stream[2]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[2]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[2]._peek bit\nvoid(query_bv_packed_stream[2]._.empty());\nvoid(query_bv_packed_stream[2]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[3]._\n#pragma HLS aggregate variable = query_bv_packed_stream[3]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[3]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[3]._peek bit\nvoid(query_bv_packed_stream[3]._.empty());\nvoid(query_bv_packed_stream[3]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[4]._\n#pragma HLS aggregate variable = query_bv_packed_stream[4]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[4]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[4]._peek bit\nvoid(query_bv_packed_stream[4]._.empty());\nvoid(query_bv_packed_stream[4]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[5]._\n#pragma HLS aggregate variable = query_bv_packed_stream[5]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[5]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[5]._peek bit\nvoid(query_bv_packed_stream[5]._.empty());\nvoid(query_bv_packed_stream[5]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[6]._\n#pragma HLS aggregate variable = query_bv_packed_stream[6]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[6]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[6]._peek bit\nvoid(query_bv_packed_stream[6]._.empty());\nvoid(query_bv_packed_stream[6]._peek.empty());\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[7]._\n#pragma HLS aggregate variable = query_bv_packed_stream[7]._ bit\n#pragma HLS interface ap_fifo port = query_bv_packed_stream[7]._peek\n#pragma HLS aggregate variable = query_bv_packed_stream[7]._peek bit\nvoid(query_bv_packed_stream[7]._.empty());\nvoid(query_bv_packed_stream[7]._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream\n#pragma HLS array_partition variable = inter_shuffle_stream complete\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[0]._\n#pragma HLS aggregate variable = inter_shuffle_stream[0]._ bit\nvoid(inter_shuffle_stream[0]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[1]._\n#pragma HLS aggregate variable = inter_shuffle_stream[1]._ bit\nvoid(inter_shuffle_stream[1]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[2]._\n#pragma HLS aggregate variable = inter_shuffle_stream[2]._ bit\nvoid(inter_shuffle_stream[2]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[3]._\n#pragma HLS aggregate variable = inter_shuffle_stream[3]._ bit\nvoid(inter_shuffle_stream[3]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[4]._\n#pragma HLS aggregate variable = inter_shuffle_stream[4]._ bit\nvoid(inter_shuffle_stream[4]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[5]._\n#pragma HLS aggregate variable = inter_shuffle_stream[5]._ bit\nvoid(inter_shuffle_stream[5]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[6]._\n#pragma HLS aggregate variable = inter_shuffle_stream[6]._ bit\nvoid(inter_shuffle_stream[6]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[7]._\n#pragma HLS aggregate variable = inter_shuffle_stream[7]._ bit\nvoid(inter_shuffle_stream[7]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[8]._\n#pragma HLS aggregate variable = inter_shuffle_stream[8]._ bit\nvoid(inter_shuffle_stream[8]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[9]._\n#pragma HLS aggregate variable = inter_shuffle_stream[9]._ bit\nvoid(inter_shuffle_stream[9]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[10]._\n#pragma HLS aggregate variable = inter_shuffle_stream[10]._ bit\nvoid(inter_shuffle_stream[10]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[11]._\n#pragma HLS aggregate variable = inter_shuffle_stream[11]._ bit\nvoid(inter_shuffle_stream[11]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[12]._\n#pragma HLS aggregate variable = inter_shuffle_stream[12]._ bit\nvoid(inter_shuffle_stream[12]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[13]._\n#pragma HLS aggregate variable = inter_shuffle_stream[13]._ bit\nvoid(inter_shuffle_stream[13]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[14]._\n#pragma HLS aggregate variable = inter_shuffle_stream[14]._ bit\nvoid(inter_shuffle_stream[14]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[15]._\n#pragma HLS aggregate variable = inter_shuffle_stream[15]._ bit\nvoid(inter_shuffle_stream[15]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[16]._\n#pragma HLS aggregate variable = inter_shuffle_stream[16]._ bit\nvoid(inter_shuffle_stream[16]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[17]._\n#pragma HLS aggregate variable = inter_shuffle_stream[17]._ bit\nvoid(inter_shuffle_stream[17]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[18]._\n#pragma HLS aggregate variable = inter_shuffle_stream[18]._ bit\nvoid(inter_shuffle_stream[18]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[19]._\n#pragma HLS aggregate variable = inter_shuffle_stream[19]._ bit\nvoid(inter_shuffle_stream[19]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[20]._\n#pragma HLS aggregate variable = inter_shuffle_stream[20]._ bit\nvoid(inter_shuffle_stream[20]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[21]._\n#pragma HLS aggregate variable = inter_shuffle_stream[21]._ bit\nvoid(inter_shuffle_stream[21]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[22]._\n#pragma HLS aggregate variable = inter_shuffle_stream[22]._ bit\nvoid(inter_shuffle_stream[22]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[23]._\n#pragma HLS aggregate variable = inter_shuffle_stream[23]._ bit\nvoid(inter_shuffle_stream[23]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[24]._\n#pragma HLS aggregate variable = inter_shuffle_stream[24]._ bit\nvoid(inter_shuffle_stream[24]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[25]._\n#pragma HLS aggregate variable = inter_shuffle_stream[25]._ bit\nvoid(inter_shuffle_stream[25]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[26]._\n#pragma HLS aggregate variable = inter_shuffle_stream[26]._ bit\nvoid(inter_shuffle_stream[26]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[27]._\n#pragma HLS aggregate variable = inter_shuffle_stream[27]._ bit\nvoid(inter_shuffle_stream[27]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[28]._\n#pragma HLS aggregate variable = inter_shuffle_stream[28]._ bit\nvoid(inter_shuffle_stream[28]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[29]._\n#pragma HLS aggregate variable = inter_shuffle_stream[29]._ bit\nvoid(inter_shuffle_stream[29]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[30]._\n#pragma HLS aggregate variable = inter_shuffle_stream[30]._ bit\nvoid(inter_shuffle_stream[30]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[31]._\n#pragma HLS aggregate variable = inter_shuffle_stream[31]._ bit\nvoid(inter_shuffle_stream[31]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[32]._\n#pragma HLS aggregate variable = inter_shuffle_stream[32]._ bit\nvoid(inter_shuffle_stream[32]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[33]._\n#pragma HLS aggregate variable = inter_shuffle_stream[33]._ bit\nvoid(inter_shuffle_stream[33]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[34]._\n#pragma HLS aggregate variable = inter_shuffle_stream[34]._ bit\nvoid(inter_shuffle_stream[34]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[35]._\n#pragma HLS aggregate variable = inter_shuffle_stream[35]._ bit\nvoid(inter_shuffle_stream[35]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[36]._\n#pragma HLS aggregate variable = inter_shuffle_stream[36]._ bit\nvoid(inter_shuffle_stream[36]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[37]._\n#pragma HLS aggregate variable = inter_shuffle_stream[37]._ bit\nvoid(inter_shuffle_stream[37]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[38]._\n#pragma HLS aggregate variable = inter_shuffle_stream[38]._ bit\nvoid(inter_shuffle_stream[38]._.full());\n#pragma HLS interface ap_fifo port = inter_shuffle_stream[39]._\n#pragma HLS aggregate variable = inter_shuffle_stream[39]._ bit\nvoid(inter_shuffle_stream[39]._.full());\n\n typedef struct {\n ap_uint BV;\n ap_uint input_idx;\n bool valid;\n } PEEKED_DTYPE;\n //int next_output_idx[NUM_STM];\n //#pragma HLS ARRAY_PARTITION variable=next_output_idx dim=0 complete\n // This is a buffer for data from each partition.\n // We also introduce a NUM_STM dimension, otherwise we hang.\n PEEKED_DTYPE shuffle_peek_emulator[(8) /* each sub bv is further partitioned into this chunks*/][(5)];\n#pragma HLS ARRAY_PARTITION variable=shuffle_peek_emulator dim=0 complete\n //NEXT_OUTPUT_IDX_INIT:\n //for (int i = 0; i < NUM_STM; ++i) {\n //#pragma HLS UNROLL\n // next_output_idx[i] = 1;\n //}\n PEEK_EMULATOR_INITIALIZATION:\n for (int j=0; j<(8) /* each sub bv is further partitioned into this chunks*/; ++j){\n#pragma HLS UNROLL\n for (int k=0; k<(5); ++k) {\n#pragma HLS UNROLL\n shuffle_peek_emulator[j][k].BV = 0;\n shuffle_peek_emulator[j][k].input_idx = 0;\n shuffle_peek_emulator[j][k].valid = 0;\n }\n }\n while(1)\n {\n#pragma HLS PIPELINE II=1\n ////////////////////////////////////////////\n // READ LOGIC. Read from each partition stream\n ////////////////////////////////////////////\n RD_BV_PARTITION_LOOP:\n for (int partition_idx = 0;\n partition_idx < (8) /* each sub bv is further partitioned into this chunks*/;\n ++partition_idx)\n {\n#pragma HLS UNROLL\n // DATAPACKED TRANSFER:\n ap_uint cur_input_idx;\n ap_uint cur_strm_idx;\n ap_uint cur_bv_val;\n METADATA_DTYPE cur_metadata;\n BV_PLUS_METADATA_PACKED_DTYPE cur_packed_data;\n bool peek_success;\n peek_success = query_bv_packed_stream[partition_idx].try_peek(\n cur_packed_data\n );\n cur_metadata = cur_packed_data.md;\n cur_bv_val = cur_packed_data.bv_val;\n // Unpack metadata\n cur_strm_idx = cur_metadata.sidx;\n cur_input_idx = cur_metadata.iidx;\n // If the current \"peeked\" value is not valid, overwrite it\n // with valid data.\n if (peek_success &&\n shuffle_peek_emulator[partition_idx][cur_strm_idx].valid == 0\n )\n {\n query_bv_packed_stream[partition_idx].read();\n // Write it into the buffer\n shuffle_peek_emulator[partition_idx]\n [cur_strm_idx].valid = 1;\n shuffle_peek_emulator[partition_idx]\n [cur_strm_idx].BV = cur_bv_val;\n shuffle_peek_emulator[partition_idx]\n [cur_strm_idx].input_idx = cur_input_idx;\n }\n }\n ////////////////////////////////////////////\n // WRITE OUTPUTS from the shuffle-buffer\n ////////////////////////////////////////////\n WR_STM_LOOP:\n for (int strm_idx = 0; strm_idx < (5); ++strm_idx)\n {\n WR_BV_PARTITION_LOOP:\n for (int partition_idx = 0;\n partition_idx < (8) /* each sub bv is further partitioned into this chunks*/;\n ++partition_idx)\n {\n#pragma HLS UNROLL\n BV_PLUS_IIDX_PACKED_DTYPE outval;\n outval.bv_val = shuffle_peek_emulator[partition_idx][strm_idx].BV;\n outval.iidx = shuffle_peek_emulator[partition_idx][strm_idx].input_idx;\n if (shuffle_peek_emulator[partition_idx][strm_idx].valid == 1 &&\n inter_shuffle_stream[strm_idx*(8) /* each sub bv is further partitioned into this chunks*/ + partition_idx].try_write(outval)\n ) {\n shuffle_peek_emulator[partition_idx][strm_idx].valid = 0;\n }\n }\n }\n }\n return;\n}\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "shuffle_reordering_per_hash": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n{\n\n\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p0\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p0._\n#pragma HLS aggregate variable = inter_shuffle_stream_p0._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p0._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p0._peek bit\nvoid(inter_shuffle_stream_p0._.empty());\nvoid(inter_shuffle_stream_p0._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p1\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p1._\n#pragma HLS aggregate variable = inter_shuffle_stream_p1._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p1._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p1._peek bit\nvoid(inter_shuffle_stream_p1._.empty());\nvoid(inter_shuffle_stream_p1._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p2\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p2._\n#pragma HLS aggregate variable = inter_shuffle_stream_p2._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p2._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p2._peek bit\nvoid(inter_shuffle_stream_p2._.empty());\nvoid(inter_shuffle_stream_p2._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p3\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p3._\n#pragma HLS aggregate variable = inter_shuffle_stream_p3._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p3._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p3._peek bit\nvoid(inter_shuffle_stream_p3._.empty());\nvoid(inter_shuffle_stream_p3._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p4\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p4._\n#pragma HLS aggregate variable = inter_shuffle_stream_p4._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p4._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p4._peek bit\nvoid(inter_shuffle_stream_p4._.empty());\nvoid(inter_shuffle_stream_p4._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p5\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p5._\n#pragma HLS aggregate variable = inter_shuffle_stream_p5._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p5._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p5._peek bit\nvoid(inter_shuffle_stream_p5._.empty());\nvoid(inter_shuffle_stream_p5._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p6\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p6._\n#pragma HLS aggregate variable = inter_shuffle_stream_p6._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p6._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p6._peek bit\nvoid(inter_shuffle_stream_p6._.empty());\nvoid(inter_shuffle_stream_p6._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p7\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p7._\n#pragma HLS aggregate variable = inter_shuffle_stream_p7._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p7._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p7._peek bit\nvoid(inter_shuffle_stream_p7._.empty());\nvoid(inter_shuffle_stream_p7._peek.empty());\n\n#pragma HLS disaggregate variable = reconstruct_stream\n#pragma HLS interface ap_fifo port = reconstruct_stream._\n#pragma HLS aggregate variable = reconstruct_stream._ bit\nvoid(reconstruct_stream._.full());\n\n typedef struct {\n ap_uint bv;\n ap_uint iidx;\n bool valid;\n } PEEKED_DTYPE;\n int next_output_idx = 1;\n PEEKED_DTYPE shufbuf[(8) /* each sub bv is further partitioned into this chunks*/][(8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/];\n#pragma HLS ARRAY_PARTITION variable=shufbuf dim=0 complete\n PEEK_EMULATOR_INIT:\n for (int p = 0; p < (8) /* each sub bv is further partitioned into this chunks*/; ++p) {\n for (int i = 0; i < (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; ++i) {\n shufbuf[p][i].bv = 0;\n shufbuf[p][i].iidx = 0;\n shufbuf[p][i].valid = 0;\n }\n }\n MAIN_LOOP:\n while(1)\n {\n#pragma HLS PIPELINE II=1\n /////////////////////////////\n // READ LOGIC\n /////////////////////////////\n //#ifdef __DO_DEBUG_PRINTS__\n //printf(\"SHUFFLE ORDERING stm%d kp%d hash%d - read BV %d from partition %d, iidx %d, into buf_idx %d\\n\",\n // stm_idx, kp_idx, shuffle_idx,\n // read_val.bv_val.to_int(),\n // partition_idx,\n // read_val.iidx.to_int(),\n // rd_buf_idx\n //);\n //#endif\n bool peek_success_p0; int rd_buf_idx_p0; BV_PLUS_IIDX_PACKED_DTYPE read_val_p0; peek_success_p0 = inter_shuffle_stream_p0.try_peek(read_val_p0); rd_buf_idx_p0 = read_val_p0.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p0 && shufbuf[0][rd_buf_idx_p0].valid == 0 ) { inter_shuffle_stream_p0.read(); shufbuf[0][rd_buf_idx_p0].bv = read_val_p0.bv_val; shufbuf[0][rd_buf_idx_p0].iidx = read_val_p0.iidx; shufbuf[0][rd_buf_idx_p0].valid = 1; }\n bool peek_success_p1; int rd_buf_idx_p1; BV_PLUS_IIDX_PACKED_DTYPE read_val_p1; peek_success_p1 = inter_shuffle_stream_p1.try_peek(read_val_p1); rd_buf_idx_p1 = read_val_p1.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p1 && shufbuf[1][rd_buf_idx_p1].valid == 0 ) { inter_shuffle_stream_p1.read(); shufbuf[1][rd_buf_idx_p1].bv = read_val_p1.bv_val; shufbuf[1][rd_buf_idx_p1].iidx = read_val_p1.iidx; shufbuf[1][rd_buf_idx_p1].valid = 1; }\n bool peek_success_p2; int rd_buf_idx_p2; BV_PLUS_IIDX_PACKED_DTYPE read_val_p2; peek_success_p2 = inter_shuffle_stream_p2.try_peek(read_val_p2); rd_buf_idx_p2 = read_val_p2.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p2 && shufbuf[2][rd_buf_idx_p2].valid == 0 ) { inter_shuffle_stream_p2.read(); shufbuf[2][rd_buf_idx_p2].bv = read_val_p2.bv_val; shufbuf[2][rd_buf_idx_p2].iidx = read_val_p2.iidx; shufbuf[2][rd_buf_idx_p2].valid = 1; }\n bool peek_success_p3; int rd_buf_idx_p3; BV_PLUS_IIDX_PACKED_DTYPE read_val_p3; peek_success_p3 = inter_shuffle_stream_p3.try_peek(read_val_p3); rd_buf_idx_p3 = read_val_p3.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p3 && shufbuf[3][rd_buf_idx_p3].valid == 0 ) { inter_shuffle_stream_p3.read(); shufbuf[3][rd_buf_idx_p3].bv = read_val_p3.bv_val; shufbuf[3][rd_buf_idx_p3].iidx = read_val_p3.iidx; shufbuf[3][rd_buf_idx_p3].valid = 1; }\n bool peek_success_p4; int rd_buf_idx_p4; BV_PLUS_IIDX_PACKED_DTYPE read_val_p4; peek_success_p4 = inter_shuffle_stream_p4.try_peek(read_val_p4); rd_buf_idx_p4 = read_val_p4.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p4 && shufbuf[4][rd_buf_idx_p4].valid == 0 ) { inter_shuffle_stream_p4.read(); shufbuf[4][rd_buf_idx_p4].bv = read_val_p4.bv_val; shufbuf[4][rd_buf_idx_p4].iidx = read_val_p4.iidx; shufbuf[4][rd_buf_idx_p4].valid = 1; }\n bool peek_success_p5; int rd_buf_idx_p5; BV_PLUS_IIDX_PACKED_DTYPE read_val_p5; peek_success_p5 = inter_shuffle_stream_p5.try_peek(read_val_p5); rd_buf_idx_p5 = read_val_p5.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p5 && shufbuf[5][rd_buf_idx_p5].valid == 0 ) { inter_shuffle_stream_p5.read(); shufbuf[5][rd_buf_idx_p5].bv = read_val_p5.bv_val; shufbuf[5][rd_buf_idx_p5].iidx = read_val_p5.iidx; shufbuf[5][rd_buf_idx_p5].valid = 1; }\n bool peek_success_p6; int rd_buf_idx_p6; BV_PLUS_IIDX_PACKED_DTYPE read_val_p6; peek_success_p6 = inter_shuffle_stream_p6.try_peek(read_val_p6); rd_buf_idx_p6 = read_val_p6.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p6 && shufbuf[6][rd_buf_idx_p6].valid == 0 ) { inter_shuffle_stream_p6.read(); shufbuf[6][rd_buf_idx_p6].bv = read_val_p6.bv_val; shufbuf[6][rd_buf_idx_p6].iidx = read_val_p6.iidx; shufbuf[6][rd_buf_idx_p6].valid = 1; }\n bool peek_success_p7; int rd_buf_idx_p7; BV_PLUS_IIDX_PACKED_DTYPE read_val_p7; peek_success_p7 = inter_shuffle_stream_p7.try_peek(read_val_p7); rd_buf_idx_p7 = read_val_p7.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p7 && shufbuf[7][rd_buf_idx_p7].valid == 0 ) { inter_shuffle_stream_p7.read(); shufbuf[7][rd_buf_idx_p7].bv = read_val_p7.bv_val; shufbuf[7][rd_buf_idx_p7].iidx = read_val_p7.iidx; shufbuf[7][rd_buf_idx_p7].valid = 1; }\n /////////////////////////////\n // WRITE LOGIC\n /////////////////////////////\n bool write_ready = 0;\n int wr_buf_idx = next_output_idx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/;\n int ready_partition_idx = 0;\n for (int partition_idx = 0; partition_idx < (8) /* each sub bv is further partitioned into this chunks*/; ++partition_idx)\n {\n if (shufbuf[partition_idx][wr_buf_idx].valid == 1 &&\n shufbuf[partition_idx][wr_buf_idx].iidx == next_output_idx\n )\n {\n write_ready = 1;\n ready_partition_idx = partition_idx;\n break;\n }\n }\n if (write_ready){\n ap_uint write_success;\n ap_uint v = shufbuf[ready_partition_idx][wr_buf_idx].bv;\n write_success = reconstruct_stream.try_write(v);\n if (write_success) {\n shufbuf[ready_partition_idx][wr_buf_idx].valid = 0;\n if (next_output_idx == KEYPAIRS_PER_STM) {\n next_output_idx = 1;\n }\n else {\n next_output_idx++;\n }\n }\n }\n }\n}\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n{\n\n\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p0\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p0._\n#pragma HLS aggregate variable = inter_shuffle_stream_p0._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p0._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p0._peek bit\nvoid(inter_shuffle_stream_p0._.empty());\nvoid(inter_shuffle_stream_p0._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p1\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p1._\n#pragma HLS aggregate variable = inter_shuffle_stream_p1._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p1._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p1._peek bit\nvoid(inter_shuffle_stream_p1._.empty());\nvoid(inter_shuffle_stream_p1._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p2\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p2._\n#pragma HLS aggregate variable = inter_shuffle_stream_p2._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p2._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p2._peek bit\nvoid(inter_shuffle_stream_p2._.empty());\nvoid(inter_shuffle_stream_p2._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p3\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p3._\n#pragma HLS aggregate variable = inter_shuffle_stream_p3._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p3._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p3._peek bit\nvoid(inter_shuffle_stream_p3._.empty());\nvoid(inter_shuffle_stream_p3._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p4\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p4._\n#pragma HLS aggregate variable = inter_shuffle_stream_p4._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p4._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p4._peek bit\nvoid(inter_shuffle_stream_p4._.empty());\nvoid(inter_shuffle_stream_p4._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p5\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p5._\n#pragma HLS aggregate variable = inter_shuffle_stream_p5._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p5._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p5._peek bit\nvoid(inter_shuffle_stream_p5._.empty());\nvoid(inter_shuffle_stream_p5._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p6\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p6._\n#pragma HLS aggregate variable = inter_shuffle_stream_p6._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p6._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p6._peek bit\nvoid(inter_shuffle_stream_p6._.empty());\nvoid(inter_shuffle_stream_p6._peek.empty());\n\n#pragma HLS disaggregate variable = inter_shuffle_stream_p7\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p7._\n#pragma HLS aggregate variable = inter_shuffle_stream_p7._ bit\n#pragma HLS interface ap_fifo port = inter_shuffle_stream_p7._peek\n#pragma HLS aggregate variable = inter_shuffle_stream_p7._peek bit\nvoid(inter_shuffle_stream_p7._.empty());\nvoid(inter_shuffle_stream_p7._peek.empty());\n\n#pragma HLS disaggregate variable = reconstruct_stream\n#pragma HLS interface ap_fifo port = reconstruct_stream._\n#pragma HLS aggregate variable = reconstruct_stream._ bit\nvoid(reconstruct_stream._.full());\n\n typedef struct {\n ap_uint bv;\n ap_uint iidx;\n bool valid;\n } PEEKED_DTYPE;\n int next_output_idx = 1;\n PEEKED_DTYPE shufbuf[(8) /* each sub bv is further partitioned into this chunks*/][(8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/];\n#pragma HLS ARRAY_PARTITION variable=shufbuf dim=0 complete\n PEEK_EMULATOR_INIT:\n for (int p = 0; p < (8) /* each sub bv is further partitioned into this chunks*/; ++p) {\n for (int i = 0; i < (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; ++i) {\n shufbuf[p][i].bv = 0;\n shufbuf[p][i].iidx = 0;\n shufbuf[p][i].valid = 0;\n }\n }\n MAIN_LOOP:\n while(1)\n {\n#pragma HLS PIPELINE II=1\n /////////////////////////////\n // READ LOGIC\n /////////////////////////////\n //#ifdef __DO_DEBUG_PRINTS__\n //printf(\"SHUFFLE ORDERING stm%d kp%d hash%d - read BV %d from partition %d, iidx %d, into buf_idx %d\\n\",\n // stm_idx, kp_idx, shuffle_idx,\n // read_val.bv_val.to_int(),\n // partition_idx,\n // read_val.iidx.to_int(),\n // rd_buf_idx\n //);\n //#endif\n bool peek_success_p0; int rd_buf_idx_p0; BV_PLUS_IIDX_PACKED_DTYPE read_val_p0; peek_success_p0 = inter_shuffle_stream_p0.try_peek(read_val_p0); rd_buf_idx_p0 = read_val_p0.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p0 && shufbuf[0][rd_buf_idx_p0].valid == 0 ) { inter_shuffle_stream_p0.read(); shufbuf[0][rd_buf_idx_p0].bv = read_val_p0.bv_val; shufbuf[0][rd_buf_idx_p0].iidx = read_val_p0.iidx; shufbuf[0][rd_buf_idx_p0].valid = 1; }\n bool peek_success_p1; int rd_buf_idx_p1; BV_PLUS_IIDX_PACKED_DTYPE read_val_p1; peek_success_p1 = inter_shuffle_stream_p1.try_peek(read_val_p1); rd_buf_idx_p1 = read_val_p1.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p1 && shufbuf[1][rd_buf_idx_p1].valid == 0 ) { inter_shuffle_stream_p1.read(); shufbuf[1][rd_buf_idx_p1].bv = read_val_p1.bv_val; shufbuf[1][rd_buf_idx_p1].iidx = read_val_p1.iidx; shufbuf[1][rd_buf_idx_p1].valid = 1; }\n bool peek_success_p2; int rd_buf_idx_p2; BV_PLUS_IIDX_PACKED_DTYPE read_val_p2; peek_success_p2 = inter_shuffle_stream_p2.try_peek(read_val_p2); rd_buf_idx_p2 = read_val_p2.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p2 && shufbuf[2][rd_buf_idx_p2].valid == 0 ) { inter_shuffle_stream_p2.read(); shufbuf[2][rd_buf_idx_p2].bv = read_val_p2.bv_val; shufbuf[2][rd_buf_idx_p2].iidx = read_val_p2.iidx; shufbuf[2][rd_buf_idx_p2].valid = 1; }\n bool peek_success_p3; int rd_buf_idx_p3; BV_PLUS_IIDX_PACKED_DTYPE read_val_p3; peek_success_p3 = inter_shuffle_stream_p3.try_peek(read_val_p3); rd_buf_idx_p3 = read_val_p3.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p3 && shufbuf[3][rd_buf_idx_p3].valid == 0 ) { inter_shuffle_stream_p3.read(); shufbuf[3][rd_buf_idx_p3].bv = read_val_p3.bv_val; shufbuf[3][rd_buf_idx_p3].iidx = read_val_p3.iidx; shufbuf[3][rd_buf_idx_p3].valid = 1; }\n bool peek_success_p4; int rd_buf_idx_p4; BV_PLUS_IIDX_PACKED_DTYPE read_val_p4; peek_success_p4 = inter_shuffle_stream_p4.try_peek(read_val_p4); rd_buf_idx_p4 = read_val_p4.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p4 && shufbuf[4][rd_buf_idx_p4].valid == 0 ) { inter_shuffle_stream_p4.read(); shufbuf[4][rd_buf_idx_p4].bv = read_val_p4.bv_val; shufbuf[4][rd_buf_idx_p4].iidx = read_val_p4.iidx; shufbuf[4][rd_buf_idx_p4].valid = 1; }\n bool peek_success_p5; int rd_buf_idx_p5; BV_PLUS_IIDX_PACKED_DTYPE read_val_p5; peek_success_p5 = inter_shuffle_stream_p5.try_peek(read_val_p5); rd_buf_idx_p5 = read_val_p5.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p5 && shufbuf[5][rd_buf_idx_p5].valid == 0 ) { inter_shuffle_stream_p5.read(); shufbuf[5][rd_buf_idx_p5].bv = read_val_p5.bv_val; shufbuf[5][rd_buf_idx_p5].iidx = read_val_p5.iidx; shufbuf[5][rd_buf_idx_p5].valid = 1; }\n bool peek_success_p6; int rd_buf_idx_p6; BV_PLUS_IIDX_PACKED_DTYPE read_val_p6; peek_success_p6 = inter_shuffle_stream_p6.try_peek(read_val_p6); rd_buf_idx_p6 = read_val_p6.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p6 && shufbuf[6][rd_buf_idx_p6].valid == 0 ) { inter_shuffle_stream_p6.read(); shufbuf[6][rd_buf_idx_p6].bv = read_val_p6.bv_val; shufbuf[6][rd_buf_idx_p6].iidx = read_val_p6.iidx; shufbuf[6][rd_buf_idx_p6].valid = 1; }\n bool peek_success_p7; int rd_buf_idx_p7; BV_PLUS_IIDX_PACKED_DTYPE read_val_p7; peek_success_p7 = inter_shuffle_stream_p7.try_peek(read_val_p7); rd_buf_idx_p7 = read_val_p7.iidx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/; if (peek_success_p7 && shufbuf[7][rd_buf_idx_p7].valid == 0 ) { inter_shuffle_stream_p7.read(); shufbuf[7][rd_buf_idx_p7].bv = read_val_p7.bv_val; shufbuf[7][rd_buf_idx_p7].iidx = read_val_p7.iidx; shufbuf[7][rd_buf_idx_p7].valid = 1; }\n /////////////////////////////\n // WRITE LOGIC\n /////////////////////////////\n bool write_ready = 0;\n int wr_buf_idx = next_output_idx % (8) /* Number of buffered elements we can have for each hash/partition, in the shuffle buffer.*/;\n int ready_partition_idx = 0;\n for (int partition_idx = 0; partition_idx < (8) /* each sub bv is further partitioned into this chunks*/; ++partition_idx)\n {\n if (shufbuf[partition_idx][wr_buf_idx].valid == 1 &&\n shufbuf[partition_idx][wr_buf_idx].iidx == next_output_idx\n )\n {\n write_ready = 1;\n ready_partition_idx = partition_idx;\n break;\n }\n }\n if (write_ready){\n ap_uint write_success;\n ap_uint v = shufbuf[ready_partition_idx][wr_buf_idx].bv;\n write_success = reconstruct_stream.try_write(v);\n if (write_success) {\n shufbuf[ready_partition_idx][wr_buf_idx].valid = 0;\n if (next_output_idx == KEYPAIRS_PER_STM) {\n next_output_idx = 1;\n }\n else {\n next_output_idx++;\n }\n }\n }\n }\n}\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" }, "workload": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nextern \"C\" {\n\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n{\n\n#pragma HLS interface s_axilite port = input_bv bundle = control\n{ auto val = reinterpret_cast(input_bv); }\n{ auto val = reinterpret_cast(input_bv); }\n\n#pragma HLS interface s_axilite port = key_in bundle = control\n{ auto val = reinterpret_cast(key_in); }\n{ auto val = reinterpret_cast(key_in); }\n\n#pragma HLS interface s_axilite port = out_bits bundle = control\n{ auto val = reinterpret_cast(out_bits); }\n{ auto val = reinterpret_cast(out_bits); }\n\n#pragma HLS interface s_axilite port = UNUSED_DUMMY bundle = control\n{ auto val = reinterpret_cast(UNUSED_DUMMY); }\n\n\n#pragma HLS interface s_axilite port = return bundle = control\n}\n\n\n} // extern \"C\"\n\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nextern \"C\" {\n\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n{\n\n#pragma HLS interface s_axilite port = input_bv bundle = control\n{ auto val = reinterpret_cast(input_bv); }\n{ auto val = reinterpret_cast(input_bv); }\n\n#pragma HLS interface s_axilite port = key_in bundle = control\n{ auto val = reinterpret_cast(key_in); }\n{ auto val = reinterpret_cast(key_in); }\n\n#pragma HLS interface s_axilite port = out_bits bundle = control\n{ auto val = reinterpret_cast(out_bits); }\n{ auto val = reinterpret_cast(out_bits); }\n\n#pragma HLS interface s_axilite port = UNUSED_DUMMY bundle = control\n{ auto val = reinterpret_cast(UNUSED_DUMMY); }\n\n\n#pragma HLS interface s_axilite port = return bundle = control\n}\n\n\n} // extern \"C\"\n\n", "fifos": { "aggregate_stream_kp0_workload[0]": { "consumed_by": [ @@ -11996,7 +11996,6 @@ ] } }, - "frt_interface": "#include \n#include \n#include \n\n\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n uint64_t outmmap\n);\n/*************************************************************************************/\nvoid workload(\n tapa::mmap input_bv\n ,tapa::mmap key_in\n ,tapa::mmap out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n{\n#define TAPAB_APP \"TAPAB_workload\"\n#define TAPAB \"TAPAB\"\n const char* _tapa_bitstream = nullptr;\n if ((_tapa_bitstream = getenv(TAPAB_APP)) ||\n (_tapa_bitstream = getenv(TAPAB))) {\n fpga::Instance _tapa_instance(_tapa_bitstream);\n int _tapa_arg_index = 0;\n for (const auto& _tapa_arg_info : _tapa_instance.GetArgsInfo()) {\n if (false) {\n } else if (_tapa_arg_info.name == \"input_bv\") {\n auto _tapa_arg = fpga::ReadWrite(input_bv.get(), input_bv.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"key_in\") {\n auto _tapa_arg = fpga::ReadWrite(key_in.get(), key_in.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_bits\") {\n auto _tapa_arg = fpga::ReadWrite(out_bits.get(), out_bits.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"UNUSED_DUMMY\") {\n _tapa_instance.SetArg(_tapa_arg_index, UNUSED_DUMMY);\n } else {\n std::stringstream ss;\n ss << \"unknown argument: \" << _tapa_arg_info;\n throw std::runtime_error(ss.str());\n }\n ++_tapa_arg_index;\n }\n _tapa_instance.WriteToDevice();\n _tapa_instance.Exec();\n _tapa_instance.ReadFromDevice();\n _tapa_instance.Finish();\n } else {\n throw std::runtime_error(\"no bitstream found; please set `\" TAPAB_APP\n \"` or `\" TAPAB \"`\");\n }\n}\n", "level": "upper", "ports": [ { @@ -26474,7 +26473,7 @@ "vendor": "xilinx" }, "writeOutput_synchronous": { - "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell \nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( ((512*((3)))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n tapa::mmap outmmap\n){\n#pragma HLS disaggregate variable = packed_outputs_stream_s0_kp0\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s0_kp0._\n#pragma HLS aggregate variable = packed_outputs_stream_s0_kp0._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s0_kp0._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s0_kp0._peek bit\nvoid(packed_outputs_stream_s0_kp0._.empty());\nvoid(packed_outputs_stream_s0_kp0._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s0_kp1\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s0_kp1._\n#pragma HLS aggregate variable = packed_outputs_stream_s0_kp1._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s0_kp1._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s0_kp1._peek bit\nvoid(packed_outputs_stream_s0_kp1._.empty());\nvoid(packed_outputs_stream_s0_kp1._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s1_kp0\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s1_kp0._\n#pragma HLS aggregate variable = packed_outputs_stream_s1_kp0._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s1_kp0._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s1_kp0._peek bit\nvoid(packed_outputs_stream_s1_kp0._.empty());\nvoid(packed_outputs_stream_s1_kp0._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s1_kp1\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s1_kp1._\n#pragma HLS aggregate variable = packed_outputs_stream_s1_kp1._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s1_kp1._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s1_kp1._peek bit\nvoid(packed_outputs_stream_s1_kp1._.empty());\nvoid(packed_outputs_stream_s1_kp1._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s2_kp0\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s2_kp0._\n#pragma HLS aggregate variable = packed_outputs_stream_s2_kp0._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s2_kp0._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s2_kp0._peek bit\nvoid(packed_outputs_stream_s2_kp0._.empty());\nvoid(packed_outputs_stream_s2_kp0._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s2_kp1\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s2_kp1._\n#pragma HLS aggregate variable = packed_outputs_stream_s2_kp1._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s2_kp1._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s2_kp1._peek bit\nvoid(packed_outputs_stream_s2_kp1._.empty());\nvoid(packed_outputs_stream_s2_kp1._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s3_kp0\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s3_kp0._\n#pragma HLS aggregate variable = packed_outputs_stream_s3_kp0._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s3_kp0._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s3_kp0._peek bit\nvoid(packed_outputs_stream_s3_kp0._.empty());\nvoid(packed_outputs_stream_s3_kp0._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s3_kp1\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s3_kp1._\n#pragma HLS aggregate variable = packed_outputs_stream_s3_kp1._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s3_kp1._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s3_kp1._peek bit\nvoid(packed_outputs_stream_s3_kp1._.empty());\nvoid(packed_outputs_stream_s3_kp1._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s4_kp0\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s4_kp0._\n#pragma HLS aggregate variable = packed_outputs_stream_s4_kp0._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s4_kp0._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s4_kp0._peek bit\nvoid(packed_outputs_stream_s4_kp0._.empty());\nvoid(packed_outputs_stream_s4_kp0._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s4_kp1\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s4_kp1._\n#pragma HLS aggregate variable = packed_outputs_stream_s4_kp1._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s4_kp1._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s4_kp1._peek bit\nvoid(packed_outputs_stream_s4_kp1._.empty());\nvoid(packed_outputs_stream_s4_kp1._peek.empty());\n\n#pragma HLS interface m_axi port = outmmap offset = direct bundle = outmmap\n\n STORE_DTYPE to_store;\n for (int i = 0; i < PACKED_OUTPUTS_PER_STM; ++i) {\n to_store.s0_k0 = packed_outputs_stream_s0_kp0.read();\n to_store.s0_k1 = packed_outputs_stream_s0_kp1.read();\n to_store.s1_k0 = packed_outputs_stream_s1_kp0.read();\n to_store.s1_k1 = packed_outputs_stream_s1_kp1.read();\n to_store.s2_k0 = packed_outputs_stream_s2_kp0.read();\n to_store.s2_k1 = packed_outputs_stream_s2_kp1.read();\n to_store.s3_k0 = packed_outputs_stream_s3_kp0.read();\n to_store.s3_k1 = packed_outputs_stream_s3_kp1.read();\n to_store.s4_k0 = packed_outputs_stream_s4_kp0.read();\n to_store.s4_k1 = packed_outputs_stream_s4_kp1.read();\n outmmap[i] = to_store;\n }\n}\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", + "code": "\n//#ifndef __SYNTHESIS__\n// #include \n//#endif\n//#include \n\n\n #include \n\n#include \n\n#include \n\n#include \n\n/*****************************/\n// MACROS USED FOR CALCULATIONS\n// Power of 2 rounding : https://stackoverflow.com/questions/466204/rounding-up-to-next-power-of-2\n/*****************************/\n/*****************************/\n// CONFIGURE ME!\n/*****************************/\n// NOTE: IF THE BV_LENGTH IS NOT A POWER OF TWO, SOME MODULES MAY ACHIEVE POOR II.\nconst int HASHONLY_BITWIDTH = 32;\nconst int BV_PACKED_BITWIDTH = 32; //On-chip memory for BV, packing this many bits into one cell\nconst int BIT_BITWIDTH = 1;\ntypedef struct {\n ap_uint<(32)> k0;\n ap_uint<(32)> k1;\n} TWOKEY_DTYPE;\ntypedef struct {\n ap_uint section0;\n ap_uint section1;\n ap_uint section2;\n ap_uint padding3;\n} BV_LOAD_DTYPE;\n const int STRM_IDX_BITWIDTH = 8;\n const int INPUT_IDX_BITWIDTH = 24;\n const int MAX_INPUT_IDX = ( 1<<(INPUT_IDX_BITWIDTH) ) - 1;\n const int METADATA_BITWIDTH = INPUT_IDX_BITWIDTH + STRM_IDX_BITWIDTH;\n const int MAX_STRM_IDX = ( 1<<(STRM_IDX_BITWIDTH) ) - 1;\n const int PACKED_HASH_BITWIDTH = HASHONLY_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_METADATA_BITWIDTH = BIT_BITWIDTH + METADATA_BITWIDTH;\n const int BV_PLUS_IIDX_BITWIDTH = BIT_BITWIDTH + INPUT_IDX_BITWIDTH;\n /************************/\n //// Packed datatypes. Packed as follows (MSB to LSB): [STRM_IDX, INPUT_IDX, HASH_VALUE]\n //#define PACKED_HASH_DTYPE ap_uint\n //#define BV_PLUS_METADATA_PACKED_DTYPE ap_uint\n //#define METADATA_DTYPE ap_uint\n typedef struct {\n ap_uint iidx;\n ap_uint sidx;\n } METADATA_DTYPE;\n typedef struct {\n ap_uint bv_val;\n METADATA_DTYPE md;\n } BV_PLUS_METADATA_PACKED_DTYPE;\n typedef struct {\n ap_uint bv_val;\n ap_uint iidx;\n } BV_PLUS_IIDX_PACKED_DTYPE;\n typedef struct {\n ap_uint hash;\n METADATA_DTYPE md;\n } PACKED_HASH_DTYPE;\n /************************/\n const int _BV_ROUNDING_FACTOR_ = (3) * BV_PACKED_BITWIDTH * (8) /* each sub bv is further partitioned into this chunks*/;\n const int BV_LENGTH = ( (((1024*1024*4)*(3))-1)/_BV_ROUNDING_FACTOR_ + 1) * _BV_ROUNDING_FACTOR_;\ntypedef struct {\n ap_uint<(32)> s0_k0;\n ap_uint<(32)> s0_k1;\n ap_uint<(32)> s1_k0;\n ap_uint<(32)> s1_k1;\n ap_uint<(32)> s2_k0;\n ap_uint<(32)> s2_k1;\n ap_uint<(32)> s3_k0;\n ap_uint<(32)> s3_k1;\n ap_uint<(32)> s4_k0;\n ap_uint<(32)> s4_k1;\n ap_uint<(32)> padding_5_k0;\n ap_uint<(32)> padding_5_k1;\n ap_uint<(32)> padding_6_k0;\n ap_uint<(32)> padding_6_k1;\n ap_uint<(32)> padding_7_k0;\n ap_uint<(32)> padding_7_k1;\n} LOAD_DTYPE;\n// This naming is potentially confusing - we datapack TWICE.\n// Within each key-stream we pack 32 elements together.\n// Then, we coalesce among key-streams.\ntypedef struct {\n ap_uint<((32))> s0_k0;\n ap_uint<((32))> s0_k1;\n ap_uint<((32))> s1_k0;\n ap_uint<((32))> s1_k1;\n ap_uint<((32))> s2_k0;\n ap_uint<((32))> s2_k1;\n ap_uint<((32))> s3_k0;\n ap_uint<((32))> s3_k1;\n ap_uint<((32))> s4_k0;\n ap_uint<((32))> s4_k1;\n ap_uint<((32))> padding_5_k0;\n ap_uint<((32))> padding_5_k1;\n ap_uint<((32))> padding_6_k0;\n ap_uint<((32))> padding_6_k1;\n ap_uint<((32))> padding_7_k0;\n ap_uint<((32))> padding_7_k1;\n} STORE_DTYPE;\n/***************************************************/\n/***************************************************/\n/***************************************************/\n/* STM_DEPTH: In the worst case, the arbiter can send all of the hashed values to the same FIFO.\n * So that FIFO will get filled, and the shuffle unit wont be able to handle it.\n * We need at least NUM_STM FIFO elements between arbiter and shuffle. */\nconst int KEYS_PER_STM = (( ( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) | (( ( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) | (( ( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) | (( ( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) | (( ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 0) | ((( ((1024*1024*8*(5))-1)/(5) + 1)-1) >> 1) ) >> 2) ) >> 4) ) >> 8) ) >> 16 ) ))+1;\nconst int KEYPAIRS_PER_STM = KEYS_PER_STM/2; // 2 reads per cycle (2port bram)\nconst int TOTAL_NUM_KEYINPUT = KEYS_PER_STM * (5);\nconst int PACKED_OUTPUTS_PER_STM = ( (KEYPAIRS_PER_STM-1)/((32)) + 1);\nconst int PACKED_OUTPAIRS_PER_STM = PACKED_OUTPUTS_PER_STM * 2; // same number of outputs but half the stms if we pair them\nconst int NUM_PACKED_OUTPUTS = PACKED_OUTPUTS_PER_STM * (5) * 2; // 2 reads per cycle (2port bram)\ntypedef struct {\n ap_uint strm0_out_idx;\n ap_uint strm1_out_idx;\n ap_uint strm2_out_idx;\n ap_uint strm3_out_idx;\n ap_uint strm4_out_idx;\n} RATEMON_FEEDBACK_DTYPE;\nvoid loadKey(\n uint64_t key_in\n ,tapa::ostreams, (5)> & key_stream_kp0\n ,tapa::ostreams, (5)> & key_stream_kp1\n);\n/*************************************************************************************/\nvoid loadBV(\n uint64_t input_bv\n ,tapa::ostream > & bv_load_stream_0\n ,tapa::ostream > & bv_load_stream_1\n ,tapa::ostream > & bv_load_stream_2\n);\n/*************************************************************************************/\nuint32_t MurmurHash3_x86_32 (\n ap_uint<(32)> key,\n uint32_t seed\n){\n#pragma HLS inline\n const int nblocks = ((32) / 8) / 4;\n uint32_t h1 = seed;\n const uint32_t c1 = 0xcc9e2d51;\n const uint32_t c2 = 0x1b873593;\n //length is limited as this: KEY_SIZE_IN_BYTES / 4 <= KEY_SIZE_IN_BYTES\n BLOCK_DIVIDING:\n for( int i = 0; i < nblocks; i++){\n#pragma HLS UNROLL\n ap_uint<(32)> tmp;\n tmp.range(31,0) = key.range(32*i+31, 32*i);\n uint32_t k1 = tmp;\n k1 *= c1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //k1 = ROTL32(k1,15);\n k1 = ( (k1 << 15) | (k1 >> (17)) );\n k1 = k1*c2;\n h1 ^= k1;\n // copy-paste the body of the rotl() function, otherwise it doesn't work.\n //h1 = ROTL32(h1,13);\n h1 = ( (h1 << 13) | (h1 >> 19) );\n h1 = h1*5 + 0xe6546b64;\n }\n //Remainder from block division\n uint32_t tail = key[nblocks];\n //Finalization\n h1 ^= ((32) / 8);\n //h1 = fmix32(h1);\n h1 ^= h1>>16;\n h1 *= 0x85ebca6b;\n h1 ^= h1>>13;\n h1 *= 0xc2b2ae35;\n h1 ^= h1>>16;\n uint32_t retval;\n //retval = (uint32_t)key * (seed+3);\n retval = h1;\n return retval;\n}\nvoid computeHash_Feeder(\n int strm_idx,\n int keypair_idx,\n tapa::istream > & key_in_stream,\n tapa::ostreams, (3)> & key_out_stream\n);\nvoid computeHash_Computer(\n int stm_idx,\n int hash_idx,\n int keypair_idx,\n tapa::istream > & key_stream,\n tapa::ostream > & hash_stream\n);\n// CONFIG: need NUM_HASH calls to INVOKE_COMPUTERS_FOR_HASH\n/*************************************************************************************/\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid bloom_arb_forwarder(\n int arb_idx\n ,int kp_idx\n ,tapa::istreams, (5)> & hash_stream\n ,tapa::ostreams & arb_stream\n);\nvoid bloom_hier_arbiter_atom(\n int arb_idx,\n int partition_idx,\n int kp_idx,\n int atom_ID,\n tapa::istream & ratemon_stream,\n tapa::istream & in_stream0,\n tapa::istream & in_stream1,\n tapa::ostream & out_stream\n);\nvoid bloom_arbiter_ratemonitor(\n int arb_idx\n ,int kp_idx\n ,char ratemon_ID\n ,tapa::istreams &arb_stream_in\n ,tapa::ostreams &arb_stream_out\n ,tapa::ostreams &fdbk_stream_0\n ,tapa::ostreams &fdbk_stream_1\n ,tapa::ostreams &fdbk_stream_2\n ,tapa::ostreams &fdbk_stream_3\n ,tapa::ostreams &fdbk_stream_4\n ,tapa::ostreams &fdbk_stream_5\n ,tapa::ostreams &fdbk_stream_6\n ,tapa::ostreams &fdbk_stream_7\n);\nvoid bloom_arbiter_tree_singlepartition(\n int arb_idx\n ,int partition_idx\n ,int kp_idx\n ,tapa::istream &arb_stm0\n ,tapa::istream &arb_stm1\n ,tapa::istream &arb_stm2\n ,tapa::istream &arb_stm3\n ,tapa::istream &arb_stm4\n ,tapa::istreams &ratemon_feedback\n ,tapa::ostream &arbtree_out\n) ;\nvoid bloom_single_arbiter(\n int arb_idx\n , int kp_idx\n , tapa::istreams &in_arb_streams\n , tapa::ostreams &bv_lookup_stream\n) ;\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\n///////// END OF Arbiter //////\n//////////////////////////////////////////////////\n//////////////////////////////////////////////////\nvoid queryResult_per_hash(\n int hash_idx\n ,tapa::istream > & bv_load_stream\n ,tapa::istreams & bv_lookup_stream_kp0\n ,tapa::istreams & bv_lookup_stream_kp1\n ,tapa::ostreams & query_bv_packed_stream_kp0\n ,tapa::ostreams & query_bv_packed_stream_kp1\n) ;\n/*************************************************************************************/\nvoid shuffle_TtoS_per_hash(\n int shuffle_idx\n ,int kp_idx\n ,tapa::istreams & query_bv_packed_stream\n ,tapa::ostreams & inter_shuffle_stream\n);\nvoid shuffle_reordering_per_hash(\n int shuffle_idx\n ,int stm_idx\n ,int kp_idx\n ,tapa::istream & inter_shuffle_stream_p0\n ,tapa::istream & inter_shuffle_stream_p1\n ,tapa::istream & inter_shuffle_stream_p2\n ,tapa::istream & inter_shuffle_stream_p3\n ,tapa::istream & inter_shuffle_stream_p4\n ,tapa::istream & inter_shuffle_stream_p5\n ,tapa::istream & inter_shuffle_stream_p6\n ,tapa::istream & inter_shuffle_stream_p7\n ,tapa::ostream > & reconstruct_stream\n)\n;\nvoid bloom_aggregate_SPLIT(\n int agg_idx,\n int kp_idx,\n tapa::istreams, (3)> & reconstruct_stream,\n tapa::ostream > & aggregate_stream\n);\n/*************************************************************************************/\nvoid packOutput(\n int strm_idx\n ,int kp_idx\n ,tapa::istream > & aggregate_stream\n ,tapa::ostream > & packed_outputs_stream\n) ;\nvoid writeOutput_synchronous(\n tapa::istream >& packed_outputs_stream_s0_kp0,\n tapa::istream >& packed_outputs_stream_s0_kp1,\n tapa::istream >& packed_outputs_stream_s1_kp0,\n tapa::istream >& packed_outputs_stream_s1_kp1,\n tapa::istream >& packed_outputs_stream_s2_kp0,\n tapa::istream >& packed_outputs_stream_s2_kp1,\n tapa::istream >& packed_outputs_stream_s3_kp0,\n tapa::istream >& packed_outputs_stream_s3_kp1,\n tapa::istream >& packed_outputs_stream_s4_kp0,\n tapa::istream >& packed_outputs_stream_s4_kp1,\n tapa::mmap outmmap\n){\n#pragma HLS disaggregate variable = packed_outputs_stream_s0_kp0\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s0_kp0._\n#pragma HLS aggregate variable = packed_outputs_stream_s0_kp0._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s0_kp0._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s0_kp0._peek bit\nvoid(packed_outputs_stream_s0_kp0._.empty());\nvoid(packed_outputs_stream_s0_kp0._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s0_kp1\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s0_kp1._\n#pragma HLS aggregate variable = packed_outputs_stream_s0_kp1._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s0_kp1._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s0_kp1._peek bit\nvoid(packed_outputs_stream_s0_kp1._.empty());\nvoid(packed_outputs_stream_s0_kp1._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s1_kp0\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s1_kp0._\n#pragma HLS aggregate variable = packed_outputs_stream_s1_kp0._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s1_kp0._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s1_kp0._peek bit\nvoid(packed_outputs_stream_s1_kp0._.empty());\nvoid(packed_outputs_stream_s1_kp0._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s1_kp1\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s1_kp1._\n#pragma HLS aggregate variable = packed_outputs_stream_s1_kp1._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s1_kp1._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s1_kp1._peek bit\nvoid(packed_outputs_stream_s1_kp1._.empty());\nvoid(packed_outputs_stream_s1_kp1._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s2_kp0\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s2_kp0._\n#pragma HLS aggregate variable = packed_outputs_stream_s2_kp0._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s2_kp0._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s2_kp0._peek bit\nvoid(packed_outputs_stream_s2_kp0._.empty());\nvoid(packed_outputs_stream_s2_kp0._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s2_kp1\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s2_kp1._\n#pragma HLS aggregate variable = packed_outputs_stream_s2_kp1._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s2_kp1._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s2_kp1._peek bit\nvoid(packed_outputs_stream_s2_kp1._.empty());\nvoid(packed_outputs_stream_s2_kp1._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s3_kp0\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s3_kp0._\n#pragma HLS aggregate variable = packed_outputs_stream_s3_kp0._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s3_kp0._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s3_kp0._peek bit\nvoid(packed_outputs_stream_s3_kp0._.empty());\nvoid(packed_outputs_stream_s3_kp0._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s3_kp1\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s3_kp1._\n#pragma HLS aggregate variable = packed_outputs_stream_s3_kp1._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s3_kp1._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s3_kp1._peek bit\nvoid(packed_outputs_stream_s3_kp1._.empty());\nvoid(packed_outputs_stream_s3_kp1._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s4_kp0\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s4_kp0._\n#pragma HLS aggregate variable = packed_outputs_stream_s4_kp0._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s4_kp0._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s4_kp0._peek bit\nvoid(packed_outputs_stream_s4_kp0._.empty());\nvoid(packed_outputs_stream_s4_kp0._peek.empty());\n\n#pragma HLS disaggregate variable = packed_outputs_stream_s4_kp1\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s4_kp1._\n#pragma HLS aggregate variable = packed_outputs_stream_s4_kp1._ bit\n#pragma HLS interface ap_fifo port = packed_outputs_stream_s4_kp1._peek\n#pragma HLS aggregate variable = packed_outputs_stream_s4_kp1._peek bit\nvoid(packed_outputs_stream_s4_kp1._.empty());\nvoid(packed_outputs_stream_s4_kp1._peek.empty());\n\n#pragma HLS interface m_axi port = outmmap offset = direct bundle = outmmap\n\n STORE_DTYPE to_store;\n for (int i = 0; i < PACKED_OUTPUTS_PER_STM; ++i) {\n to_store.s0_k0 = packed_outputs_stream_s0_kp0.read();\n to_store.s0_k1 = packed_outputs_stream_s0_kp1.read();\n to_store.s1_k0 = packed_outputs_stream_s1_kp0.read();\n to_store.s1_k1 = packed_outputs_stream_s1_kp1.read();\n to_store.s2_k0 = packed_outputs_stream_s2_kp0.read();\n to_store.s2_k1 = packed_outputs_stream_s2_kp1.read();\n to_store.s3_k0 = packed_outputs_stream_s3_kp0.read();\n to_store.s3_k1 = packed_outputs_stream_s3_kp1.read();\n to_store.s4_k0 = packed_outputs_stream_s4_kp0.read();\n to_store.s4_k1 = packed_outputs_stream_s4_kp1.read();\n outmmap[i] = to_store;\n }\n}\n/*************************************************************************************/\nvoid workload(\n uint64_t input_bv\n ,uint64_t key_in\n ,uint64_t out_bits\n //Add a dummy, useless variable because TAPA fast-cosim doesnt work without it.\n ,int UNUSED_DUMMY\n)\n;\n", "level": "lower", "target": "hls", "vendor": "xilinx" diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/log/tapac.INFO b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/log/tapac.INFO deleted file mode 120000 index 4ffbdb79..00000000 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/log/tapac.INFO +++ /dev/null @@ -1 +0,0 @@ -tapac.squark.ylxiao.log.INFO.20240712-150917.1339196 \ No newline at end of file diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/log/tapac.squark.ylxiao.log.INFO.20240712-150917.1339196 b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/log/tapac.squark.ylxiao.log.INFO.20240712-150917.1339196 deleted file mode 100644 index 54a292a1..00000000 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/log/tapac.squark.ylxiao.log.INFO.20240712-150917.1339196 +++ /dev/null @@ -1,4773 +0,0 @@ -I0712 15:09:17.458 tapa.util:184] logging level set to INFO -I0712 15:09:17.459 tapa.tapac:407] Executing all steps of tapac -I0712 15:09:17.459 tapa.tapac:521] running translated command: `tapa --work-dir=generated analyze --input=src/multistream_MurmurHash3.cpp --top=workload synth --part-num=xcu280-fsvh2892-2L-e --clock-period=3.33 link pack --output=generated/multistream_MurmurHash3.xo` -I0712 15:09:17.459 tapa.util:184] logging level set to INFO -I0712 15:09:17.459 tapa.util:184] logging level set to INFO -I0712 15:09:17.459 tapa.tapa:54] tapa version: 0.0.20240301.1 -I0712 15:09:17.459 tapa.tapa:54] tapa version: 0.0.20240301.1 -I0712 15:09:17.459 tapa.tapa:58] Python recursion limit set to 3000 -I0712 15:09:17.459 tapa.tapa:58] Python recursion limit set to 3000 -I0712 15:09:17.532 tapa.steps.analyze:151] added vendor include path `/tools/Xilinx/Vitis_HLS/2022.2/include` -I0712 15:09:17.532 tapa.steps.analyze:151] added vendor include path `/tools/Xilinx/Vitis_HLS/2022.2/include` -I0712 15:09:17.532 tapa.steps.analyze:248] Running tapacc command: /usr/bin/tapacc generated/flatten/flatten-bca92fa8-multistream_MurmurHash3.cpp -top workload -- -std=c++17 -I /home/ylxiao/.local/lib/python3.10/site-packages/tapa/../../../src -isystem /tools/Xilinx/Vitis_HLS/2022.2/include -stdlib=libc++ -isystem /usr/lib/llvm-17/include/c++/v1/ -isystem /usr/include/clang/17/include/ -isystem /usr/lib/clang/17/include/ -I0712 15:09:17.532 tapa.steps.analyze:248] Running tapacc command: /usr/bin/tapacc generated/flatten/flatten-bca92fa8-multistream_MurmurHash3.cpp -top workload -- -std=c++17 -I /home/ylxiao/.local/lib/python3.10/site-packages/tapa/../../../src -isystem /tools/Xilinx/Vitis_HLS/2022.2/include -stdlib=libc++ -isystem /usr/lib/llvm-17/include/c++/v1/ -isystem /usr/include/clang/17/include/ -isystem /usr/lib/clang/17/include/ -I0712 15:09:20.097 tapa.steps.common:92] writing TAPA graph to json `generated/graph.json`. -I0712 15:09:20.097 tapa.steps.common:92] writing TAPA graph to json `generated/graph.json`. -I0712 15:09:20.116 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 15:09:20.116 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 15:09:20.116 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 15:09:20.116 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 15:09:20.116 tapa.core:184] extracting HLS C++ files -I0712 15:09:20.116 tapa.core:184] extracting HLS C++ files -I0712 15:09:20.123 tapa.core:216] running HLS -I0712 15:09:20.123 tapa.core:216] running HLS -I0712 15:09:20.124 tapa.core:262] spawn 16 workers for parallel HLS synthesis of the tasks -I0712 15:09:20.124 tapa.core:262] spawn 16 workers for parallel HLS synthesis of the tasks -I0712 15:10:59.462 tapa.core:277] extracting RTL files -I0712 15:10:59.462 tapa.core:277] extracting RTL files -I0712 15:10:59.526 tapa.core:308] parsing RTL files and populating tasks -I0712 15:10:59.526 tapa.core:308] parsing RTL files and populating tasks -D0712 15:11:00.759 tapa.core:317] parsing bloom_aggregate_SPLIT -D0712 15:11:00.759 tapa.core:317] parsing bloom_aggregate_SPLIT -D0712 15:11:00.760 tapa.core:321] populating bloom_aggregate_SPLIT -D0712 15:11:00.760 tapa.core:321] populating bloom_aggregate_SPLIT -D0712 15:11:00.760 tapa.core:317] parsing bloom_arb_forwarder -D0712 15:11:00.760 tapa.core:317] parsing bloom_arb_forwarder -D0712 15:11:00.761 tapa.core:321] populating bloom_arb_forwarder -D0712 15:11:00.761 tapa.core:321] populating bloom_arb_forwarder -D0712 15:11:00.770 tapa.core:317] parsing bloom_arbiter_ratemonitor -D0712 15:11:00.770 tapa.core:317] parsing bloom_arbiter_ratemonitor -D0712 15:11:00.771 tapa.core:321] populating bloom_arbiter_ratemonitor -D0712 15:11:00.771 tapa.core:321] populating bloom_arbiter_ratemonitor -D0712 15:11:00.771 tapa.core:317] parsing bloom_hier_arbiter_atom -D0712 15:11:00.771 tapa.core:317] parsing bloom_hier_arbiter_atom -D0712 15:11:00.772 tapa.core:321] populating bloom_hier_arbiter_atom -D0712 15:11:00.772 tapa.core:321] populating bloom_hier_arbiter_atom -D0712 15:11:00.772 tapa.core:317] parsing computeHash_Computer -D0712 15:11:00.772 tapa.core:317] parsing computeHash_Computer -D0712 15:11:00.773 tapa.core:321] populating computeHash_Computer -D0712 15:11:00.773 tapa.core:321] populating computeHash_Computer -D0712 15:11:00.773 tapa.core:317] parsing computeHash_Feeder -D0712 15:11:00.773 tapa.core:317] parsing computeHash_Feeder -D0712 15:11:00.773 tapa.core:321] populating computeHash_Feeder -D0712 15:11:00.773 tapa.core:321] populating computeHash_Feeder -D0712 15:11:00.774 tapa.core:317] parsing loadBV -D0712 15:11:00.774 tapa.core:317] parsing loadBV -D0712 15:11:00.774 tapa.core:321] populating loadBV -D0712 15:11:00.774 tapa.core:321] populating loadBV -D0712 15:11:00.774 tapa.core:317] parsing loadKey -D0712 15:11:00.774 tapa.core:317] parsing loadKey -D0712 15:11:00.775 tapa.core:321] populating loadKey -D0712 15:11:00.775 tapa.core:321] populating loadKey -D0712 15:11:00.775 tapa.core:317] parsing packOutput -D0712 15:11:00.775 tapa.core:317] parsing packOutput -D0712 15:11:00.775 tapa.core:321] populating packOutput -D0712 15:11:00.775 tapa.core:321] populating packOutput -D0712 15:11:00.775 tapa.core:317] parsing queryResult_per_hash -D0712 15:11:00.775 tapa.core:317] parsing queryResult_per_hash -D0712 15:11:00.776 tapa.core:321] populating queryResult_per_hash -D0712 15:11:00.776 tapa.core:321] populating queryResult_per_hash -D0712 15:11:00.776 tapa.core:317] parsing shuffle_TtoS_per_hash -D0712 15:11:00.776 tapa.core:317] parsing shuffle_TtoS_per_hash -D0712 15:11:00.777 tapa.core:321] populating shuffle_TtoS_per_hash -D0712 15:11:00.777 tapa.core:321] populating shuffle_TtoS_per_hash -D0712 15:11:00.777 tapa.core:317] parsing shuffle_reordering_per_hash -D0712 15:11:00.777 tapa.core:317] parsing shuffle_reordering_per_hash -D0712 15:11:00.778 tapa.core:321] populating shuffle_reordering_per_hash -D0712 15:11:00.778 tapa.core:321] populating shuffle_reordering_per_hash -D0712 15:11:00.778 tapa.core:317] parsing writeOutput_synchronous -D0712 15:11:00.778 tapa.core:317] parsing writeOutput_synchronous -D0712 15:11:00.778 tapa.core:321] populating writeOutput_synchronous -D0712 15:11:00.778 tapa.core:321] populating writeOutput_synchronous -D0712 15:11:00.778 tapa.core:317] parsing workload -D0712 15:11:00.778 tapa.core:317] parsing workload -D0712 15:11:00.779 tapa.core:321] populating workload -D0712 15:11:00.779 tapa.core:321] populating workload -D0712 15:11:00.792 tapa.task:149] mmap argument 'workload.input_bv' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'loadBV_0.input_bv' -D0712 15:11:00.792 tapa.task:149] mmap argument 'workload.input_bv' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'loadBV_0.input_bv' -D0712 15:11:00.792 tapa.task:149] mmap argument 'workload.key_in' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'loadKey_0.key_in' -D0712 15:11:00.792 tapa.task:149] mmap argument 'workload.key_in' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'loadKey_0.key_in' -D0712 15:11:00.792 tapa.task:149] mmap argument 'workload.out_bits' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'writeOutput_synchronous_0.outmmap' -D0712 15:11:00.792 tapa.task:149] mmap argument 'workload.out_bits' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'writeOutput_synchronous_0.outmmap' -I0712 15:11:00.792 tapa.core:325] instrumenting upper-level RTL -I0712 15:11:00.792 tapa.core:325] instrumenting upper-level RTL -I0712 15:11:00.792 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 15:11:00.792 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 15:11:00.792 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 15:11:00.792 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 15:11:00.793 tapa.core:452] top task register level set to 0 -I0712 15:11:00.793 tapa.core:452] top task register level set to 0 -I0712 15:11:00.793 tapa.core:456] instrumenting top-level RTL -I0712 15:11:00.793 tapa.core:456] instrumenting top-level RTL -D0712 15:11:00.793 tapa.core:529] instantiating FIFOs in workload -D0712 15:11:00.793 tapa.core:529] instantiating FIFOs in workload -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp0_workload[0] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp0_workload[0] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp0_workload[1] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp0_workload[1] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp0_workload[2] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp0_workload[2] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp0_workload[3] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp0_workload[3] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp0_workload[4] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp0_workload[4] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp1_workload[0] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp1_workload[0] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp1_workload[1] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp1_workload[1] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp1_workload[2] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp1_workload[2] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp1_workload[3] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp1_workload[3] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp1_workload[4] -D0712 15:11:00.795 tapa.core:542] instantiating workload.aggregate_stream_kp1_workload[4] -D0712 15:11:00.795 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[0] -D0712 15:11:00.795 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[0] -D0712 15:11:00.795 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[10] -D0712 15:11:00.795 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[10] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[11] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[11] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[12] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[12] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[13] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[13] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[14] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[14] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[15] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[15] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[16] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[16] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[17] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[17] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[18] -D0712 15:11:00.796 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[18] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[19] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[19] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[1] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[1] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[20] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[20] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[21] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[21] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[22] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[22] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[23] -D0712 15:11:00.797 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[23] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[24] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[24] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[25] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[25] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[26] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[26] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[27] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[27] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[28] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[28] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[29] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[29] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[2] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[2] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[30] -D0712 15:11:00.798 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[30] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[31] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[31] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[32] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[32] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[33] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[33] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[34] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[34] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[35] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[35] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[36] -D0712 15:11:00.799 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[36] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[37] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[37] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[38] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[38] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[39] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[39] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[3] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[3] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[4] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[4] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[5] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[5] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[6] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[6] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[7] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[7] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[8] -D0712 15:11:00.800 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[8] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[9] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp0_workload[9] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[0] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[0] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[10] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[10] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[11] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[11] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[12] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[12] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[13] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[13] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[14] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[14] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[15] -D0712 15:11:00.801 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[15] -D0712 15:11:00.802 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[16] -D0712 15:11:00.802 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[16] -D0712 15:11:00.802 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[17] -D0712 15:11:00.802 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[17] -D0712 15:11:00.814 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[18] -D0712 15:11:00.814 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[18] -D0712 15:11:00.814 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[19] -D0712 15:11:00.814 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[19] -D0712 15:11:00.814 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[1] -D0712 15:11:00.814 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[1] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[20] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[20] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[21] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[21] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[22] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[22] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[23] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[23] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[24] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[24] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[25] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[25] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[26] -D0712 15:11:00.815 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[26] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[27] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[27] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[28] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[28] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[29] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[29] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[2] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[2] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[30] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[30] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[31] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[31] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[32] -D0712 15:11:00.816 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[32] -D0712 15:11:00.817 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[33] -D0712 15:11:00.817 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[33] -D0712 15:11:00.817 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[34] -D0712 15:11:00.817 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[34] -D0712 15:11:00.817 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[35] -D0712 15:11:00.817 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[35] -D0712 15:11:00.817 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[36] -D0712 15:11:00.817 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[36] -D0712 15:11:00.817 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[37] -D0712 15:11:00.817 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[37] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[38] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[38] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[39] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[39] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[3] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[3] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[4] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[4] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[5] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[5] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[6] -D0712 15:11:00.818 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[6] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[7] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[7] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[8] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[8] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[9] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb0_streams_kp1_workload[9] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[0] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[0] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[10] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[10] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[11] -D0712 15:11:00.819 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[11] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[12] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[12] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[13] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[13] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[14] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[14] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[15] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[15] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[16] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[16] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[17] -D0712 15:11:00.820 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[17] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[18] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[18] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[19] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[19] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[1] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[1] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[20] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[20] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[21] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[21] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[22] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[22] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[23] -D0712 15:11:00.821 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[23] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[24] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[24] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[25] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[25] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[26] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[26] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[27] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[27] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[28] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[28] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[29] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[29] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[2] -D0712 15:11:00.822 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[2] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[30] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[30] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[31] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[31] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[32] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[32] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[33] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[33] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[34] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[34] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[35] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[35] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[36] -D0712 15:11:00.823 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[36] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[37] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[37] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[38] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[38] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[39] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[39] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[3] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[3] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[4] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[4] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[5] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[5] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[6] -D0712 15:11:00.824 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[6] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[7] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[7] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[8] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[8] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[9] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp0_workload[9] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[0] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[0] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[10] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[10] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[11] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[11] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[12] -D0712 15:11:00.825 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[12] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[13] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[13] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[14] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[14] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[15] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[15] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[16] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[16] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[17] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[17] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[18] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[18] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[19] -D0712 15:11:00.826 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[19] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[1] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[1] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[20] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[20] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[21] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[21] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[22] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[22] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[23] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[23] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[24] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[24] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[25] -D0712 15:11:00.827 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[25] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[26] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[26] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[27] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[27] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[28] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[28] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[29] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[29] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[2] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[2] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[30] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[30] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[31] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[31] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[32] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[32] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[33] -D0712 15:11:00.828 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[33] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[34] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[34] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[35] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[35] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[36] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[36] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[37] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[37] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[38] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[38] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[39] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[39] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[3] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[3] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[4] -D0712 15:11:00.829 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[4] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[5] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[5] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[6] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[6] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[7] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[7] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[8] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[8] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[9] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb1_streams_kp1_workload[9] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[0] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[0] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[10] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[10] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[11] -D0712 15:11:00.830 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[11] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[12] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[12] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[13] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[13] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[14] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[14] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[15] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[15] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[16] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[16] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[17] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[17] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[18] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[18] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[19] -D0712 15:11:00.831 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[19] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[1] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[1] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[20] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[20] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[21] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[21] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[22] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[22] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[23] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[23] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[24] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[24] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[25] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[25] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[26] -D0712 15:11:00.832 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[26] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[27] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[27] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[28] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[28] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[29] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[29] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[2] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[2] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[30] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[30] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[31] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[31] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[32] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[32] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[33] -D0712 15:11:00.833 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[33] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[34] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[34] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[35] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[35] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[36] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[36] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[37] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[37] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[38] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[38] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[39] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[39] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[3] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[3] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[4] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[4] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[5] -D0712 15:11:00.834 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[5] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[6] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[6] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[7] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[7] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[8] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[8] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[9] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp0_workload[9] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[0] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[0] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[10] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[10] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[11] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[11] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[12] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[12] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[13] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[13] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[14] -D0712 15:11:00.835 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[14] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[15] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[15] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[16] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[16] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[17] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[17] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[18] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[18] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[19] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[19] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[1] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[1] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[20] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[20] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[21] -D0712 15:11:00.836 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[21] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[22] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[22] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[23] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[23] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[24] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[24] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[25] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[25] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[26] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[26] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[27] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[27] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[28] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[28] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[29] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[29] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[2] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[2] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[30] -D0712 15:11:00.837 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[30] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[31] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[31] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[32] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[32] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[33] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[33] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[34] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[34] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[35] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[35] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[36] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[36] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[37] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[37] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[38] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[38] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[39] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[39] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[3] -D0712 15:11:00.838 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[3] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[4] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[4] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[5] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[5] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[6] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[6] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[7] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[7] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[8] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[8] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[9] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb2_streams_kp1_workload[9] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.839 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.840 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.841 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.842 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.843 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.844 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage1_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_0_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.845 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_1_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_2_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.846 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_3_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_4_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_5_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.847 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_6_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arb_stage2_outputs_bloom_arbiter_tree_singlepartition_7_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[4] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[4] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[5] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[5] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[6] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[6] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[7] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_0_workload[7] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.848 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[4] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[4] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[5] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[5] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[6] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[6] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[7] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_1_workload[7] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[4] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[4] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[5] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[5] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[6] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[6] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[7] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_2_workload[7] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.849 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[4] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[4] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[5] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[5] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[6] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[6] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[7] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_3_workload[7] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[4] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[4] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[5] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[5] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[6] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[6] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[7] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_4_workload[7] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.850 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[4] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[4] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[5] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[5] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[6] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[6] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[7] -D0712 15:11:00.851 tapa.core:542] instantiating workload.arbtree_outputs_bloom_single_arbiter_5_workload[7] -D0712 15:11:00.851 tapa.core:542] instantiating workload.bv_load_stream_0_workload -D0712 15:11:00.851 tapa.core:542] instantiating workload.bv_load_stream_0_workload -D0712 15:11:00.851 tapa.core:542] instantiating workload.bv_load_stream_1_workload -D0712 15:11:00.851 tapa.core:542] instantiating workload.bv_load_stream_1_workload -D0712 15:11:00.851 tapa.core:542] instantiating workload.bv_load_stream_2_workload -D0712 15:11:00.851 tapa.core:542] instantiating workload.bv_load_stream_2_workload -D0712 15:11:00.851 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[0] -D0712 15:11:00.851 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[0] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[1] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[1] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[2] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[2] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[3] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[3] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[4] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[4] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[5] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[5] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[6] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[6] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[7] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp0_workload[7] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[0] -D0712 15:11:00.852 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[0] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[1] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[1] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[2] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[2] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[3] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[3] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[4] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[4] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[5] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[5] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[6] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[6] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[7] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h0_kp1_workload[7] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[0] -D0712 15:11:00.853 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[0] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[1] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[1] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[2] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[2] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[3] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[3] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[4] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[4] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[5] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[5] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[6] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[6] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[7] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp0_workload[7] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[0] -D0712 15:11:00.854 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[0] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[1] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[1] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[2] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[2] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[3] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[3] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[4] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[4] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[5] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[5] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[6] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[6] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[7] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h1_kp1_workload[7] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[0] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[0] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[1] -D0712 15:11:00.855 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[1] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[2] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[2] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[3] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[3] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[4] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[4] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[5] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[5] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[6] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[6] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[7] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp0_workload[7] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[0] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[0] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[1] -D0712 15:11:00.856 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[1] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[2] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[2] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[3] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[3] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[4] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[4] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[5] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[5] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[6] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[6] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[7] -D0712 15:11:00.857 tapa.core:542] instantiating workload.bv_lookup_stream_h2_kp1_workload[7] -D0712 15:11:00.857 tapa.core:542] instantiating workload.hash_stream_h0_kp0_workload[0] -D0712 15:11:00.857 tapa.core:542] instantiating workload.hash_stream_h0_kp0_workload[0] -D0712 15:11:00.857 tapa.core:542] instantiating workload.hash_stream_h0_kp0_workload[1] -D0712 15:11:00.857 tapa.core:542] instantiating workload.hash_stream_h0_kp0_workload[1] -D0712 15:11:00.857 tapa.core:542] instantiating workload.hash_stream_h0_kp0_workload[2] -D0712 15:11:00.857 tapa.core:542] instantiating workload.hash_stream_h0_kp0_workload[2] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp0_workload[3] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp0_workload[3] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp0_workload[4] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp0_workload[4] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp1_workload[0] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp1_workload[0] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp1_workload[1] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp1_workload[1] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp1_workload[2] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp1_workload[2] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp1_workload[3] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp1_workload[3] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp1_workload[4] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h0_kp1_workload[4] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp0_workload[0] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp0_workload[0] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp0_workload[1] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp0_workload[1] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp0_workload[2] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp0_workload[2] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp0_workload[3] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp0_workload[3] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp0_workload[4] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp0_workload[4] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp1_workload[0] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp1_workload[0] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp1_workload[1] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp1_workload[1] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp1_workload[2] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp1_workload[2] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp1_workload[3] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp1_workload[3] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp1_workload[4] -D0712 15:11:00.858 tapa.core:542] instantiating workload.hash_stream_h1_kp1_workload[4] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp0_workload[0] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp0_workload[0] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp0_workload[1] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp0_workload[1] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp0_workload[2] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp0_workload[2] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp0_workload[3] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp0_workload[3] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp0_workload[4] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp0_workload[4] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp1_workload[0] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp1_workload[0] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp1_workload[1] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp1_workload[1] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp1_workload[2] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp1_workload[2] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp1_workload[3] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp1_workload[3] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp1_workload[4] -D0712 15:11:00.859 tapa.core:542] instantiating workload.hash_stream_h2_kp1_workload[4] -D0712 15:11:00.859 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[0] -D0712 15:11:00.859 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[0] -D0712 15:11:00.859 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[10] -D0712 15:11:00.859 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[10] -D0712 15:11:00.859 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[11] -D0712 15:11:00.859 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[11] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[12] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[12] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[13] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[13] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[14] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[14] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[15] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[15] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[16] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[16] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[17] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[17] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[18] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[18] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[19] -D0712 15:11:00.860 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[19] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[1] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[1] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[20] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[20] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[21] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[21] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[22] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[22] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[23] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[23] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[24] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[24] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[25] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[25] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[26] -D0712 15:11:00.861 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[26] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[27] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[27] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[28] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[28] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[29] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[29] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[2] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[2] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[30] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[30] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[31] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[31] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[32] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[32] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[33] -D0712 15:11:00.862 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[33] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[34] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[34] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[35] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[35] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[36] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[36] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[37] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[37] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[38] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[38] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[39] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[39] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[3] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[3] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[4] -D0712 15:11:00.863 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[4] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[5] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[5] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[6] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[6] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[7] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[7] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[8] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[8] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[9] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp0_workload[9] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[0] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[0] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[10] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[10] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[11] -D0712 15:11:00.864 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[11] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[12] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[12] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[13] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[13] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[14] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[14] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[15] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[15] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[16] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[16] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[17] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[17] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[18] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[18] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[19] -D0712 15:11:00.865 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[19] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[1] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[1] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[20] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[20] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[21] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[21] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[22] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[22] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[23] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[23] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[24] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[24] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[25] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[25] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[26] -D0712 15:11:00.866 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[26] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[27] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[27] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[28] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[28] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[29] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[29] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[2] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[2] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[30] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[30] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[31] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[31] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[32] -D0712 15:11:00.867 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[32] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[33] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[33] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[34] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[34] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[35] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[35] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[36] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[36] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[37] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[37] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[38] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[38] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[39] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[39] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[3] -D0712 15:11:00.868 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[3] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[4] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[4] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[5] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[5] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[6] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[6] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[7] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[7] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[8] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[8] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[9] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf0_stm_kp1_workload[9] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[0] -D0712 15:11:00.869 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[0] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[10] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[10] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[11] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[11] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[12] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[12] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[13] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[13] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[14] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[14] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[15] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[15] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[16] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[16] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[17] -D0712 15:11:00.870 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[17] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[18] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[18] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[19] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[19] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[1] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[1] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[20] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[20] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[21] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[21] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[22] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[22] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[23] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[23] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[24] -D0712 15:11:00.871 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[24] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[25] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[25] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[26] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[26] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[27] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[27] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[28] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[28] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[29] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[29] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[2] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[2] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[30] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[30] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[31] -D0712 15:11:00.872 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[31] -D0712 15:11:00.873 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[32] -D0712 15:11:00.873 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[32] -D0712 15:11:00.873 tapa.core:542] instantiating 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workload.inter_shuf1_stm_kp0_workload[38] -D0712 15:11:00.874 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[39] -D0712 15:11:00.874 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[39] -D0712 15:11:00.874 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[3] -D0712 15:11:00.874 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[3] -D0712 15:11:00.874 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[4] -D0712 15:11:00.874 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[4] -D0712 15:11:00.874 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[5] -D0712 15:11:00.874 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[5] -D0712 15:11:00.874 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[6] -D0712 15:11:00.874 tapa.core:542] instantiating workload.inter_shuf1_stm_kp0_workload[6] -D0712 15:11:00.874 tapa.core:542] instantiating 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workload.inter_shuf1_stm_kp1_workload[11] -D0712 15:11:00.875 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[12] -D0712 15:11:00.875 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[12] -D0712 15:11:00.875 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[13] -D0712 15:11:00.875 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[13] -D0712 15:11:00.875 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[14] -D0712 15:11:00.875 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[14] -D0712 15:11:00.875 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[15] -D0712 15:11:00.875 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[15] -D0712 15:11:00.876 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[16] -D0712 15:11:00.876 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[16] -D0712 15:11:00.876 tapa.core:542] instantiating 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workload.inter_shuf1_stm_kp1_workload[21] -D0712 15:11:00.876 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[22] -D0712 15:11:00.876 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[22] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[23] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[23] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[24] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[24] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[25] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[25] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[26] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[26] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[27] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[27] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[28] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[28] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[29] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[29] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[2] -D0712 15:11:00.877 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[2] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[30] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[30] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[31] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[31] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[32] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[32] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[33] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[33] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[34] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[34] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[35] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[35] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[36] -D0712 15:11:00.878 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[36] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[37] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[37] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[38] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[38] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[39] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[39] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[3] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[3] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[4] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[4] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[5] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[5] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[6] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[6] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[7] -D0712 15:11:00.879 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[7] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[8] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[8] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[9] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf1_stm_kp1_workload[9] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[0] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[0] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[10] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[10] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[11] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[11] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[12] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[12] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[13] -D0712 15:11:00.880 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[13] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[14] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[14] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[15] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[15] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[16] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[16] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[17] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[17] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[18] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[18] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[19] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[19] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[1] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[1] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[20] -D0712 15:11:00.881 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[20] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[21] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[21] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[22] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[22] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[23] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[23] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[24] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[24] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[25] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[25] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[26] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[26] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[27] -D0712 15:11:00.882 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[27] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[28] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[28] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[29] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[29] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[2] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[2] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[30] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[30] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[31] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[31] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[32] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[32] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[33] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[33] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[34] -D0712 15:11:00.883 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[34] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[35] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[35] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[36] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[36] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[37] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[37] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[38] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[38] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[39] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[39] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[3] -D0712 15:11:00.884 tapa.core:542] instantiating workload.inter_shuf2_stm_kp0_workload[3] -D0712 15:11:00.884 tapa.core:542] instantiating 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workload.inter_shuf2_stm_kp0_workload[9] -D0712 15:11:00.885 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[0] -D0712 15:11:00.885 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[0] -D0712 15:11:00.885 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[10] -D0712 15:11:00.885 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[10] -D0712 15:11:00.885 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[11] -D0712 15:11:00.885 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[11] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[12] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[12] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[13] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[13] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[14] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[14] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[15] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[15] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[16] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[16] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[17] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[17] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[18] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[18] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[19] -D0712 15:11:00.886 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[19] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[1] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[1] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[20] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[20] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[21] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[21] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[22] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[22] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[23] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[23] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[24] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[24] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[25] -D0712 15:11:00.887 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[25] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[26] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[26] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[27] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[27] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[28] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[28] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[29] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[29] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[2] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[2] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[30] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[30] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[31] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[31] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[32] -D0712 15:11:00.888 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[32] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[33] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[33] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[34] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[34] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[35] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[35] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[36] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[36] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[37] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[37] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[38] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[38] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[39] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[39] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[3] -D0712 15:11:00.889 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[3] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[4] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[4] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[5] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[5] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[6] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[6] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[7] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[7] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[8] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[8] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[9] -D0712 15:11:00.890 tapa.core:542] instantiating workload.inter_shuf2_stm_kp1_workload[9] -D0712 15:11:00.890 tapa.core:542] instantiating workload.key_stream_kp0_workload[0] -D0712 15:11:00.890 tapa.core:542] instantiating workload.key_stream_kp0_workload[0] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp0_workload[1] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp0_workload[1] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp0_workload[2] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp0_workload[2] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp0_workload[3] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp0_workload[3] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp0_workload[4] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp0_workload[4] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp1_workload[0] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp1_workload[0] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp1_workload[1] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp1_workload[1] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp1_workload[2] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp1_workload[2] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp1_workload[3] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp1_workload[3] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp1_workload[4] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_stream_kp1_workload[4] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_tmp_stream_0_kp0_workload[0] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_tmp_stream_0_kp0_workload[0] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_tmp_stream_0_kp0_workload[1] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_tmp_stream_0_kp0_workload[1] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_tmp_stream_0_kp0_workload[2] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_tmp_stream_0_kp0_workload[2] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_tmp_stream_0_kp1_workload[0] -D0712 15:11:00.891 tapa.core:542] instantiating workload.key_tmp_stream_0_kp1_workload[0] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_0_kp1_workload[1] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_0_kp1_workload[1] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_0_kp1_workload[2] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_0_kp1_workload[2] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp0_workload[0] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp0_workload[0] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp0_workload[1] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp0_workload[1] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp0_workload[2] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp0_workload[2] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp1_workload[0] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp1_workload[0] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp1_workload[1] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp1_workload[1] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp1_workload[2] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_1_kp1_workload[2] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp0_workload[0] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp0_workload[0] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp0_workload[1] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp0_workload[1] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp0_workload[2] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp0_workload[2] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp1_workload[0] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp1_workload[0] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp1_workload[1] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp1_workload[1] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp1_workload[2] -D0712 15:11:00.892 tapa.core:542] instantiating workload.key_tmp_stream_2_kp1_workload[2] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp0_workload[0] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp0_workload[0] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp0_workload[1] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp0_workload[1] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp0_workload[2] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp0_workload[2] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp1_workload[0] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp1_workload[0] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp1_workload[1] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp1_workload[1] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp1_workload[2] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_3_kp1_workload[2] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp0_workload[0] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp0_workload[0] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp0_workload[1] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp0_workload[1] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp0_workload[2] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp0_workload[2] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp1_workload[0] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp1_workload[0] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp1_workload[1] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp1_workload[1] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp1_workload[2] -D0712 15:11:00.893 tapa.core:542] instantiating workload.key_tmp_stream_4_kp1_workload[2] -D0712 15:11:00.893 tapa.core:542] instantiating workload.packed_output_stm_kp0_workload[0] -D0712 15:11:00.893 tapa.core:542] instantiating workload.packed_output_stm_kp0_workload[0] -D0712 15:11:00.893 tapa.core:542] instantiating workload.packed_output_stm_kp0_workload[1] -D0712 15:11:00.893 tapa.core:542] instantiating workload.packed_output_stm_kp0_workload[1] -D0712 15:11:00.893 tapa.core:542] instantiating workload.packed_output_stm_kp0_workload[2] -D0712 15:11:00.893 tapa.core:542] instantiating workload.packed_output_stm_kp0_workload[2] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp0_workload[3] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp0_workload[3] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp0_workload[4] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp0_workload[4] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp1_workload[0] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp1_workload[0] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp1_workload[1] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp1_workload[1] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp1_workload[2] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp1_workload[2] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp1_workload[3] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp1_workload[3] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp1_workload[4] -D0712 15:11:00.894 tapa.core:542] instantiating workload.packed_output_stm_kp1_workload[4] -D0712 15:11:00.894 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[0] -D0712 15:11:00.894 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[0] -D0712 15:11:00.894 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[1] -D0712 15:11:00.894 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[1] -D0712 15:11:00.894 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[2] -D0712 15:11:00.894 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[2] -D0712 15:11:00.894 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[3] -D0712 15:11:00.894 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[3] -D0712 15:11:00.894 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[4] -D0712 15:11:00.894 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[4] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[5] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[5] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[6] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[6] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[7] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp0_workload[7] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[0] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[0] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[1] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[1] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[2] -D0712 15:11:00.895 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[2] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[3] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[3] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[4] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[4] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[5] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[5] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[6] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[6] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[7] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash0_kp1_workload[7] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[0] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[0] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[1] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[1] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[2] -D0712 15:11:00.896 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[2] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[3] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[3] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[4] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[4] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[5] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[5] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[6] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[6] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[7] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp0_workload[7] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[0] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[0] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[1] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[1] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[2] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[2] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[3] -D0712 15:11:00.897 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[3] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[4] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[4] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[5] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[5] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[6] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[6] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[7] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash1_kp1_workload[7] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[0] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[0] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[1] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[1] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[2] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[2] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[3] -D0712 15:11:00.898 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[3] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[4] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[4] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[5] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[5] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[6] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[6] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[7] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp0_workload[7] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[0] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[0] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[1] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[1] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[2] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[2] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[3] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[3] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[4] -D0712 15:11:00.899 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[4] -D0712 15:11:00.900 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[5] -D0712 15:11:00.900 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[5] -D0712 15:11:00.900 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[6] -D0712 15:11:00.900 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[6] -D0712 15:11:00.900 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[7] -D0712 15:11:00.900 tapa.core:542] instantiating workload.query_bv_packed_stream_hash2_kp1_workload[7] -D0712 15:11:00.900 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.900 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.900 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.900 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.900 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.900 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.900 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.900 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.900 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.900 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.901 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.902 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p0_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.903 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.904 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.905 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p1_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.906 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.907 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.908 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p2_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.909 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.910 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.911 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.912 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p3_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.913 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.914 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.915 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p4_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.916 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.917 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.918 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p5_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.919 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.920 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.921 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p6_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_0_workload[0] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.922 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_0_workload[1] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_0_workload[2] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_0_workload[3] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_1_workload[0] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_1_workload[1] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_1_workload[2] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_1_workload[3] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_2_workload[0] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.923 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_2_workload[1] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_2_workload[2] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_2_workload[3] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_3_workload[0] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_3_workload[1] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_3_workload[2] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_3_workload[3] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.924 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_4_workload[0] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_4_workload[1] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_4_workload[2] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_4_workload[3] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_5_workload[0] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_5_workload[1] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_5_workload[2] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.925 tapa.core:542] instantiating workload.ratemon_fdbk_streams_p7_bloom_single_arbiter_5_workload[3] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp0_workload[0] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp0_workload[0] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp0_workload[1] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp0_workload[1] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp0_workload[2] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp0_workload[2] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp1_workload[0] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp1_workload[0] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp1_workload[1] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp1_workload[1] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp1_workload[2] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm0_kp1_workload[2] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp0_workload[0] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp0_workload[0] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp0_workload[1] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp0_workload[1] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp0_workload[2] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp0_workload[2] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp1_workload[0] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp1_workload[0] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp1_workload[1] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp1_workload[1] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp1_workload[2] -D0712 15:11:00.926 tapa.core:542] instantiating workload.reconstruct_stream_stm1_kp1_workload[2] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp0_workload[0] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp0_workload[0] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp0_workload[1] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp0_workload[1] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp0_workload[2] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp0_workload[2] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp1_workload[0] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp1_workload[0] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp1_workload[1] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp1_workload[1] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp1_workload[2] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm2_kp1_workload[2] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp0_workload[0] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp0_workload[0] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp0_workload[1] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp0_workload[1] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp0_workload[2] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp0_workload[2] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp1_workload[0] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp1_workload[0] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp1_workload[1] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp1_workload[1] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp1_workload[2] -D0712 15:11:00.927 tapa.core:542] instantiating workload.reconstruct_stream_stm3_kp1_workload[2] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp0_workload[0] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp0_workload[0] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp0_workload[1] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp0_workload[1] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp0_workload[2] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp0_workload[2] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp1_workload[0] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp1_workload[0] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp1_workload[1] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp1_workload[1] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp1_workload[2] -D0712 15:11:00.928 tapa.core:542] instantiating workload.reconstruct_stream_stm4_kp1_workload[2] -D0712 15:11:00.928 tapa.core:507] connecting workload's children tasks -D0712 15:11:00.928 tapa.core:507] connecting workload's children tasks -D0712 15:11:01.392 tapa.core:598] instantiating children tasks in workload -D0712 15:11:01.392 tapa.core:598] instantiating children tasks in workload -D0712 15:11:01.394 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_0___const__64b0 -D0712 15:11:01.394 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_0___const__64b0 -D0712 15:11:01.394 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_0___const__64b0 -D0712 15:11:01.394 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_0___const__64b0 -D0712 15:11:01.395 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_1___const__64b0 -D0712 15:11:01.395 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_1___const__64b0 -D0712 15:11:01.395 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_1___const__64b1 -D0712 15:11:01.395 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_1___const__64b1 -D0712 15:11:01.395 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_2___const__64b0 -D0712 15:11:01.395 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_2___const__64b0 -D0712 15:11:01.396 tapa.core:671] pipelined signal: 64'd2 => bloom_aggregate_SPLIT_2___const__64b2 -D0712 15:11:01.396 tapa.core:671] pipelined signal: 64'd2 => bloom_aggregate_SPLIT_2___const__64b2 -D0712 15:11:01.396 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_3___const__64b0 -D0712 15:11:01.396 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_3___const__64b0 -D0712 15:11:01.397 tapa.core:671] pipelined signal: 64'd3 => bloom_aggregate_SPLIT_3___const__64b3 -D0712 15:11:01.397 tapa.core:671] pipelined signal: 64'd3 => bloom_aggregate_SPLIT_3___const__64b3 -D0712 15:11:01.397 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_4___const__64b0 -D0712 15:11:01.397 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_4___const__64b0 -D0712 15:11:01.397 tapa.core:671] pipelined signal: 64'd4 => bloom_aggregate_SPLIT_4___const__64b4 -D0712 15:11:01.397 tapa.core:671] pipelined signal: 64'd4 => bloom_aggregate_SPLIT_4___const__64b4 -D0712 15:11:01.398 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_5___const__64b0 -D0712 15:11:01.398 tapa.core:671] pipelined signal: 64'd0 => bloom_aggregate_SPLIT_5___const__64b0 -D0712 15:11:01.398 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_5___const__64b1 -D0712 15:11:01.398 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_5___const__64b1 -D0712 15:11:01.399 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_6___const__64b1 -D0712 15:11:01.399 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_6___const__64b1 -D0712 15:11:01.399 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_6___const__64b1 -D0712 15:11:01.399 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_6___const__64b1 -D0712 15:11:01.400 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_7___const__64b1 -D0712 15:11:01.400 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_7___const__64b1 -D0712 15:11:01.400 tapa.core:671] pipelined signal: 64'd2 => bloom_aggregate_SPLIT_7___const__64b2 -D0712 15:11:01.400 tapa.core:671] pipelined signal: 64'd2 => bloom_aggregate_SPLIT_7___const__64b2 -D0712 15:11:01.401 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_8___const__64b1 -D0712 15:11:01.401 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_8___const__64b1 -D0712 15:11:01.401 tapa.core:671] pipelined signal: 64'd3 => bloom_aggregate_SPLIT_8___const__64b3 -D0712 15:11:01.401 tapa.core:671] pipelined signal: 64'd3 => bloom_aggregate_SPLIT_8___const__64b3 -D0712 15:11:01.402 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_9___const__64b1 -D0712 15:11:01.402 tapa.core:671] pipelined signal: 64'd1 => bloom_aggregate_SPLIT_9___const__64b1 -D0712 15:11:01.402 tapa.core:671] pipelined signal: 64'd4 => bloom_aggregate_SPLIT_9___const__64b4 -D0712 15:11:01.402 tapa.core:671] pipelined signal: 64'd4 => bloom_aggregate_SPLIT_9___const__64b4 -D0712 15:11:01.403 tapa.core:671] pipelined signal: 64'd0 => bloom_arb_forwarder_0___const__64b0 -D0712 15:11:01.403 tapa.core:671] pipelined signal: 64'd0 => bloom_arb_forwarder_0___const__64b0 -D0712 15:11:01.403 tapa.core:671] pipelined signal: 64'd0 => bloom_arb_forwarder_0___const__64b0 -D0712 15:11:01.403 tapa.core:671] pipelined signal: 64'd0 => bloom_arb_forwarder_0___const__64b0 -D0712 15:11:01.413 tapa.core:671] pipelined signal: 64'd0 => bloom_arb_forwarder_1___const__64b0 -D0712 15:11:01.413 tapa.core:671] pipelined signal: 64'd0 => bloom_arb_forwarder_1___const__64b0 -D0712 15:11:01.413 tapa.core:671] pipelined signal: 64'd1 => bloom_arb_forwarder_1___const__64b1 -D0712 15:11:01.413 tapa.core:671] pipelined signal: 64'd1 => bloom_arb_forwarder_1___const__64b1 -D0712 15:11:01.423 tapa.core:671] pipelined signal: 64'd0 => bloom_arb_forwarder_2___const__64b0 -D0712 15:11:01.423 tapa.core:671] pipelined signal: 64'd0 => bloom_arb_forwarder_2___const__64b0 -D0712 15:11:01.423 tapa.core:671] pipelined signal: 64'd2 => bloom_arb_forwarder_2___const__64b2 -D0712 15:11:01.423 tapa.core:671] pipelined signal: 64'd2 => bloom_arb_forwarder_2___const__64b2 -D0712 15:11:01.434 tapa.core:671] pipelined signal: 64'd0 => bloom_arb_forwarder_3___const__64b0 -D0712 15:11:01.434 tapa.core:671] pipelined signal: 64'd0 => bloom_arb_forwarder_3___const__64b0 -D0712 15:11:01.434 tapa.core:671] pipelined signal: 64'd1 => bloom_arb_forwarder_3___const__64b1 -D0712 15:11:01.434 tapa.core:671] pipelined signal: 64'd1 => bloom_arb_forwarder_3___const__64b1 -D0712 15:11:01.444 tapa.core:671] pipelined signal: 64'd1 => bloom_arb_forwarder_4___const__64b1 -D0712 15:11:01.444 tapa.core:671] pipelined signal: 64'd1 => bloom_arb_forwarder_4___const__64b1 -D0712 15:11:01.445 tapa.core:671] pipelined signal: 64'd1 => bloom_arb_forwarder_4___const__64b1 -D0712 15:11:01.445 tapa.core:671] pipelined signal: 64'd1 => bloom_arb_forwarder_4___const__64b1 -D0712 15:11:01.455 tapa.core:671] pipelined signal: 64'd1 => bloom_arb_forwarder_5___const__64b1 -D0712 15:11:01.455 tapa.core:671] pipelined signal: 64'd1 => bloom_arb_forwarder_5___const__64b1 -D0712 15:11:01.455 tapa.core:671] pipelined signal: 64'd2 => bloom_arb_forwarder_5___const__64b2 -D0712 15:11:01.455 tapa.core:671] pipelined signal: 64'd2 => bloom_arb_forwarder_5___const__64b2 -D0712 15:11:01.466 tapa.core:671] pipelined signal: 64'd0 => bloom_arbiter_ratemonitor_0___const__64b0 -D0712 15:11:01.466 tapa.core:671] pipelined signal: 64'd0 => bloom_arbiter_ratemonitor_0___const__64b0 -D0712 15:11:01.466 tapa.core:671] pipelined signal: 64'd0 => bloom_arbiter_ratemonitor_0___const__64b0 -D0712 15:11:01.466 tapa.core:671] pipelined signal: 64'd0 => bloom_arbiter_ratemonitor_0___const__64b0 -D0712 15:11:01.466 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_0___const__64b97 -D0712 15:11:01.466 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_0___const__64b97 -D0712 15:11:01.479 tapa.core:671] pipelined signal: 64'd0 => bloom_arbiter_ratemonitor_1___const__64b0 -D0712 15:11:01.479 tapa.core:671] pipelined signal: 64'd0 => bloom_arbiter_ratemonitor_1___const__64b0 -D0712 15:11:01.479 tapa.core:671] pipelined signal: 64'd1 => bloom_arbiter_ratemonitor_1___const__64b1 -D0712 15:11:01.479 tapa.core:671] pipelined signal: 64'd1 => bloom_arbiter_ratemonitor_1___const__64b1 -D0712 15:11:01.479 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_1___const__64b97 -D0712 15:11:01.479 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_1___const__64b97 -D0712 15:11:01.492 tapa.core:671] pipelined signal: 64'd0 => bloom_arbiter_ratemonitor_2___const__64b0 -D0712 15:11:01.492 tapa.core:671] pipelined signal: 64'd0 => bloom_arbiter_ratemonitor_2___const__64b0 -D0712 15:11:01.492 tapa.core:671] pipelined signal: 64'd2 => bloom_arbiter_ratemonitor_2___const__64b2 -D0712 15:11:01.492 tapa.core:671] pipelined signal: 64'd2 => bloom_arbiter_ratemonitor_2___const__64b2 -D0712 15:11:01.492 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_2___const__64b97 -D0712 15:11:01.492 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_2___const__64b97 -D0712 15:11:01.505 tapa.core:671] pipelined signal: 64'd0 => bloom_arbiter_ratemonitor_3___const__64b0 -D0712 15:11:01.505 tapa.core:671] pipelined signal: 64'd0 => bloom_arbiter_ratemonitor_3___const__64b0 -D0712 15:11:01.505 tapa.core:671] pipelined signal: 64'd1 => bloom_arbiter_ratemonitor_3___const__64b1 -D0712 15:11:01.505 tapa.core:671] pipelined signal: 64'd1 => bloom_arbiter_ratemonitor_3___const__64b1 -D0712 15:11:01.505 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_3___const__64b97 -D0712 15:11:01.505 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_3___const__64b97 -D0712 15:11:01.518 tapa.core:671] pipelined signal: 64'd1 => bloom_arbiter_ratemonitor_4___const__64b1 -D0712 15:11:01.518 tapa.core:671] pipelined signal: 64'd1 => bloom_arbiter_ratemonitor_4___const__64b1 -D0712 15:11:01.518 tapa.core:671] pipelined signal: 64'd1 => bloom_arbiter_ratemonitor_4___const__64b1 -D0712 15:11:01.518 tapa.core:671] pipelined signal: 64'd1 => bloom_arbiter_ratemonitor_4___const__64b1 -D0712 15:11:01.518 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_4___const__64b97 -D0712 15:11:01.518 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_4___const__64b97 -D0712 15:11:01.530 tapa.core:671] pipelined signal: 64'd1 => bloom_arbiter_ratemonitor_5___const__64b1 -D0712 15:11:01.530 tapa.core:671] pipelined signal: 64'd1 => bloom_arbiter_ratemonitor_5___const__64b1 -D0712 15:11:01.530 tapa.core:671] pipelined signal: 64'd2 => bloom_arbiter_ratemonitor_5___const__64b2 -D0712 15:11:01.530 tapa.core:671] pipelined signal: 64'd2 => bloom_arbiter_ratemonitor_5___const__64b2 -D0712 15:11:01.531 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_5___const__64b97 -D0712 15:11:01.531 tapa.core:671] pipelined signal: 64'd97 => bloom_arbiter_ratemonitor_5___const__64b97 -D0712 15:11:01.542 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_0___const__64b0 -D0712 15:11:01.542 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_0___const__64b0 -D0712 15:11:01.542 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_0___const__64b0 -D0712 15:11:01.542 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_0___const__64b0 -D0712 15:11:01.542 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_0___const__64b0 -D0712 15:11:01.542 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_0___const__64b0 -D0712 15:11:01.542 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_0___const__64b97 -D0712 15:11:01.542 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_0___const__64b97 -D0712 15:11:01.543 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_1___const__64b0 -D0712 15:11:01.543 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_1___const__64b0 -D0712 15:11:01.543 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_1___const__64b0 -D0712 15:11:01.543 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_1___const__64b0 -D0712 15:11:01.543 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_1___const__64b0 -D0712 15:11:01.543 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_1___const__64b0 -D0712 15:11:01.543 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_1___const__64b98 -D0712 15:11:01.543 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_1___const__64b98 -D0712 15:11:01.544 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_2___const__64b0 -D0712 15:11:01.544 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_2___const__64b0 -D0712 15:11:01.544 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_2___const__64b0 -D0712 15:11:01.544 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_2___const__64b0 -D0712 15:11:01.544 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_2___const__64b0 -D0712 15:11:01.544 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_2___const__64b0 -D0712 15:11:01.544 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_2___const__64b99 -D0712 15:11:01.544 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_2___const__64b99 -D0712 15:11:01.545 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_3___const__64b0 -D0712 15:11:01.545 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_3___const__64b0 -D0712 15:11:01.545 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_3___const__64b0 -D0712 15:11:01.545 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_3___const__64b0 -D0712 15:11:01.545 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_3___const__64b0 -D0712 15:11:01.545 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_3___const__64b0 -D0712 15:11:01.545 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_3___const__64b100 -D0712 15:11:01.545 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_3___const__64b100 -D0712 15:11:01.546 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_4___const__64b0 -D0712 15:11:01.546 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_4___const__64b0 -D0712 15:11:01.546 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_4___const__64b0 -D0712 15:11:01.546 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_4___const__64b0 -D0712 15:11:01.546 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_4___const__64b1 -D0712 15:11:01.546 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_4___const__64b1 -D0712 15:11:01.546 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_4___const__64b97 -D0712 15:11:01.546 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_4___const__64b97 -D0712 15:11:01.547 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_5___const__64b0 -D0712 15:11:01.547 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_5___const__64b0 -D0712 15:11:01.547 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_5___const__64b0 -D0712 15:11:01.547 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_5___const__64b0 -D0712 15:11:01.547 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_5___const__64b1 -D0712 15:11:01.547 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_5___const__64b1 -D0712 15:11:01.547 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_5___const__64b98 -D0712 15:11:01.547 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_5___const__64b98 -D0712 15:11:01.548 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_6___const__64b0 -D0712 15:11:01.548 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_6___const__64b0 -D0712 15:11:01.548 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_6___const__64b0 -D0712 15:11:01.548 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_6___const__64b0 -D0712 15:11:01.548 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_6___const__64b1 -D0712 15:11:01.548 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_6___const__64b1 -D0712 15:11:01.548 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_6___const__64b99 -D0712 15:11:01.548 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_6___const__64b99 -D0712 15:11:01.549 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_7___const__64b0 -D0712 15:11:01.549 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_7___const__64b0 -D0712 15:11:01.549 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_7___const__64b0 -D0712 15:11:01.549 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_7___const__64b0 -D0712 15:11:01.549 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_7___const__64b1 -D0712 15:11:01.549 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_7___const__64b1 -D0712 15:11:01.549 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_7___const__64b100 -D0712 15:11:01.549 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_7___const__64b100 -D0712 15:11:01.550 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_8___const__64b0 -D0712 15:11:01.550 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_8___const__64b0 -D0712 15:11:01.550 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_8___const__64b0 -D0712 15:11:01.550 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_8___const__64b0 -D0712 15:11:01.550 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_8___const__64b2 -D0712 15:11:01.550 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_8___const__64b2 -D0712 15:11:01.550 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_8___const__64b97 -D0712 15:11:01.550 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_8___const__64b97 -D0712 15:11:01.551 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_9___const__64b0 -D0712 15:11:01.551 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_9___const__64b0 -D0712 15:11:01.551 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_9___const__64b0 -D0712 15:11:01.551 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_9___const__64b0 -D0712 15:11:01.551 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_9___const__64b2 -D0712 15:11:01.551 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_9___const__64b2 -D0712 15:11:01.551 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_9___const__64b98 -D0712 15:11:01.551 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_9___const__64b98 -D0712 15:11:01.552 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_10___const__64b0 -D0712 15:11:01.552 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_10___const__64b0 -D0712 15:11:01.552 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_10___const__64b0 -D0712 15:11:01.552 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_10___const__64b0 -D0712 15:11:01.552 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_10___const__64b2 -D0712 15:11:01.552 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_10___const__64b2 -D0712 15:11:01.552 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_10___const__64b99 -D0712 15:11:01.552 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_10___const__64b99 -D0712 15:11:01.553 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_11___const__64b0 -D0712 15:11:01.553 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_11___const__64b0 -D0712 15:11:01.553 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_11___const__64b0 -D0712 15:11:01.553 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_11___const__64b0 -D0712 15:11:01.553 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_11___const__64b100 -D0712 15:11:01.553 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_11___const__64b100 -D0712 15:11:01.553 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_11___const__64b2 -D0712 15:11:01.553 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_11___const__64b2 -D0712 15:11:01.554 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_12___const__64b0 -D0712 15:11:01.554 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_12___const__64b0 -D0712 15:11:01.554 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_12___const__64b0 -D0712 15:11:01.554 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_12___const__64b0 -D0712 15:11:01.554 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_12___const__64b3 -D0712 15:11:01.554 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_12___const__64b3 -D0712 15:11:01.554 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_12___const__64b97 -D0712 15:11:01.554 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_12___const__64b97 -D0712 15:11:01.554 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_13___const__64b0 -D0712 15:11:01.554 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_13___const__64b0 -D0712 15:11:01.555 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_13___const__64b0 -D0712 15:11:01.555 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_13___const__64b0 -D0712 15:11:01.555 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_13___const__64b3 -D0712 15:11:01.555 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_13___const__64b3 -D0712 15:11:01.555 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_13___const__64b98 -D0712 15:11:01.555 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_13___const__64b98 -D0712 15:11:01.555 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_14___const__64b0 -D0712 15:11:01.555 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_14___const__64b0 -D0712 15:11:01.556 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_14___const__64b0 -D0712 15:11:01.556 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_14___const__64b0 -D0712 15:11:01.556 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_14___const__64b3 -D0712 15:11:01.556 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_14___const__64b3 -D0712 15:11:01.556 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_14___const__64b99 -D0712 15:11:01.556 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_14___const__64b99 -D0712 15:11:01.556 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_15___const__64b0 -D0712 15:11:01.556 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_15___const__64b0 -D0712 15:11:01.557 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_15___const__64b0 -D0712 15:11:01.557 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_15___const__64b0 -D0712 15:11:01.557 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_15___const__64b100 -D0712 15:11:01.557 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_15___const__64b100 -D0712 15:11:01.557 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_15___const__64b3 -D0712 15:11:01.557 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_15___const__64b3 -D0712 15:11:01.557 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_16___const__64b0 -D0712 15:11:01.557 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_16___const__64b0 -D0712 15:11:01.557 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_16___const__64b0 -D0712 15:11:01.557 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_16___const__64b0 -D0712 15:11:01.558 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_16___const__64b4 -D0712 15:11:01.558 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_16___const__64b4 -D0712 15:11:01.558 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_16___const__64b97 -D0712 15:11:01.558 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_16___const__64b97 -D0712 15:11:01.558 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_17___const__64b0 -D0712 15:11:01.558 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_17___const__64b0 -D0712 15:11:01.558 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_17___const__64b0 -D0712 15:11:01.558 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_17___const__64b0 -D0712 15:11:01.558 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_17___const__64b4 -D0712 15:11:01.558 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_17___const__64b4 -D0712 15:11:01.559 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_17___const__64b98 -D0712 15:11:01.559 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_17___const__64b98 -D0712 15:11:01.559 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_18___const__64b0 -D0712 15:11:01.559 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_18___const__64b0 -D0712 15:11:01.559 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_18___const__64b0 -D0712 15:11:01.559 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_18___const__64b0 -D0712 15:11:01.560 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_18___const__64b4 -D0712 15:11:01.560 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_18___const__64b4 -D0712 15:11:01.560 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_18___const__64b99 -D0712 15:11:01.560 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_18___const__64b99 -D0712 15:11:01.560 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_19___const__64b0 -D0712 15:11:01.560 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_19___const__64b0 -D0712 15:11:01.560 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_19___const__64b0 -D0712 15:11:01.560 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_19___const__64b0 -D0712 15:11:01.560 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_19___const__64b100 -D0712 15:11:01.560 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_19___const__64b100 -D0712 15:11:01.561 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_19___const__64b4 -D0712 15:11:01.561 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_19___const__64b4 -D0712 15:11:01.561 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_20___const__64b0 -D0712 15:11:01.561 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_20___const__64b0 -D0712 15:11:01.561 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_20___const__64b0 -D0712 15:11:01.561 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_20___const__64b0 -D0712 15:11:01.561 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_20___const__64b5 -D0712 15:11:01.561 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_20___const__64b5 -D0712 15:11:01.561 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_20___const__64b97 -D0712 15:11:01.561 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_20___const__64b97 -D0712 15:11:01.562 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_21___const__64b0 -D0712 15:11:01.562 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_21___const__64b0 -D0712 15:11:01.562 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_21___const__64b0 -D0712 15:11:01.562 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_21___const__64b0 -D0712 15:11:01.562 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_21___const__64b5 -D0712 15:11:01.562 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_21___const__64b5 -D0712 15:11:01.562 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_21___const__64b98 -D0712 15:11:01.562 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_21___const__64b98 -D0712 15:11:01.563 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_22___const__64b0 -D0712 15:11:01.563 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_22___const__64b0 -D0712 15:11:01.563 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_22___const__64b0 -D0712 15:11:01.563 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_22___const__64b0 -D0712 15:11:01.563 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_22___const__64b5 -D0712 15:11:01.563 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_22___const__64b5 -D0712 15:11:01.563 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_22___const__64b99 -D0712 15:11:01.563 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_22___const__64b99 -D0712 15:11:01.564 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_23___const__64b0 -D0712 15:11:01.564 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_23___const__64b0 -D0712 15:11:01.564 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_23___const__64b0 -D0712 15:11:01.564 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_23___const__64b0 -D0712 15:11:01.564 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_23___const__64b100 -D0712 15:11:01.564 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_23___const__64b100 -D0712 15:11:01.564 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_23___const__64b5 -D0712 15:11:01.564 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_23___const__64b5 -D0712 15:11:01.565 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_24___const__64b0 -D0712 15:11:01.565 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_24___const__64b0 -D0712 15:11:01.565 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_24___const__64b0 -D0712 15:11:01.565 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_24___const__64b0 -D0712 15:11:01.565 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_24___const__64b6 -D0712 15:11:01.565 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_24___const__64b6 -D0712 15:11:01.565 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_24___const__64b97 -D0712 15:11:01.565 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_24___const__64b97 -D0712 15:11:01.566 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_25___const__64b0 -D0712 15:11:01.566 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_25___const__64b0 -D0712 15:11:01.566 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_25___const__64b0 -D0712 15:11:01.566 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_25___const__64b0 -D0712 15:11:01.566 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_25___const__64b6 -D0712 15:11:01.566 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_25___const__64b6 -D0712 15:11:01.566 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_25___const__64b98 -D0712 15:11:01.566 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_25___const__64b98 -D0712 15:11:01.567 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_26___const__64b0 -D0712 15:11:01.567 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_26___const__64b0 -D0712 15:11:01.567 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_26___const__64b0 -D0712 15:11:01.567 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_26___const__64b0 -D0712 15:11:01.567 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_26___const__64b6 -D0712 15:11:01.567 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_26___const__64b6 -D0712 15:11:01.567 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_26___const__64b99 -D0712 15:11:01.567 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_26___const__64b99 -D0712 15:11:01.568 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_27___const__64b0 -D0712 15:11:01.568 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_27___const__64b0 -D0712 15:11:01.568 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_27___const__64b0 -D0712 15:11:01.568 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_27___const__64b0 -D0712 15:11:01.568 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_27___const__64b100 -D0712 15:11:01.568 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_27___const__64b100 -D0712 15:11:01.568 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_27___const__64b6 -D0712 15:11:01.568 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_27___const__64b6 -D0712 15:11:01.569 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_28___const__64b0 -D0712 15:11:01.569 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_28___const__64b0 -D0712 15:11:01.569 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_28___const__64b0 -D0712 15:11:01.569 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_28___const__64b0 -D0712 15:11:01.569 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_28___const__64b7 -D0712 15:11:01.569 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_28___const__64b7 -D0712 15:11:01.569 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_28___const__64b97 -D0712 15:11:01.569 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_28___const__64b97 -D0712 15:11:01.570 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_29___const__64b0 -D0712 15:11:01.570 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_29___const__64b0 -D0712 15:11:01.570 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_29___const__64b0 -D0712 15:11:01.570 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_29___const__64b0 -D0712 15:11:01.570 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_29___const__64b7 -D0712 15:11:01.570 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_29___const__64b7 -D0712 15:11:01.570 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_29___const__64b98 -D0712 15:11:01.570 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_29___const__64b98 -D0712 15:11:01.571 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_30___const__64b0 -D0712 15:11:01.571 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_30___const__64b0 -D0712 15:11:01.571 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_30___const__64b0 -D0712 15:11:01.571 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_30___const__64b0 -D0712 15:11:01.571 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_30___const__64b7 -D0712 15:11:01.571 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_30___const__64b7 -D0712 15:11:01.571 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_30___const__64b99 -D0712 15:11:01.571 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_30___const__64b99 -D0712 15:11:01.572 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_31___const__64b0 -D0712 15:11:01.572 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_31___const__64b0 -D0712 15:11:01.572 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_31___const__64b0 -D0712 15:11:01.572 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_31___const__64b0 -D0712 15:11:01.572 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_31___const__64b100 -D0712 15:11:01.572 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_31___const__64b100 -D0712 15:11:01.572 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_31___const__64b7 -D0712 15:11:01.572 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_31___const__64b7 -D0712 15:11:01.573 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_32___const__64b0 -D0712 15:11:01.573 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_32___const__64b0 -D0712 15:11:01.573 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_32___const__64b0 -D0712 15:11:01.573 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_32___const__64b0 -D0712 15:11:01.573 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_32___const__64b1 -D0712 15:11:01.573 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_32___const__64b1 -D0712 15:11:01.573 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_32___const__64b97 -D0712 15:11:01.573 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_32___const__64b97 -D0712 15:11:01.574 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_33___const__64b0 -D0712 15:11:01.574 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_33___const__64b0 -D0712 15:11:01.574 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_33___const__64b0 -D0712 15:11:01.574 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_33___const__64b0 -D0712 15:11:01.574 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_33___const__64b1 -D0712 15:11:01.574 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_33___const__64b1 -D0712 15:11:01.574 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_33___const__64b98 -D0712 15:11:01.574 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_33___const__64b98 -D0712 15:11:01.575 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_34___const__64b0 -D0712 15:11:01.575 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_34___const__64b0 -D0712 15:11:01.575 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_34___const__64b0 -D0712 15:11:01.575 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_34___const__64b0 -D0712 15:11:01.575 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_34___const__64b1 -D0712 15:11:01.575 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_34___const__64b1 -D0712 15:11:01.575 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_34___const__64b99 -D0712 15:11:01.575 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_34___const__64b99 -D0712 15:11:01.576 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_35___const__64b0 -D0712 15:11:01.576 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_35___const__64b0 -D0712 15:11:01.576 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_35___const__64b0 -D0712 15:11:01.576 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_35___const__64b0 -D0712 15:11:01.576 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_35___const__64b1 -D0712 15:11:01.576 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_35___const__64b1 -D0712 15:11:01.576 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_35___const__64b100 -D0712 15:11:01.576 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_35___const__64b100 -D0712 15:11:01.577 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_36___const__64b0 -D0712 15:11:01.577 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_36___const__64b0 -D0712 15:11:01.577 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_36___const__64b1 -D0712 15:11:01.577 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_36___const__64b1 -D0712 15:11:01.577 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_36___const__64b1 -D0712 15:11:01.577 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_36___const__64b1 -D0712 15:11:01.577 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_36___const__64b97 -D0712 15:11:01.577 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_36___const__64b97 -D0712 15:11:01.578 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_37___const__64b0 -D0712 15:11:01.578 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_37___const__64b0 -D0712 15:11:01.578 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_37___const__64b1 -D0712 15:11:01.578 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_37___const__64b1 -D0712 15:11:01.578 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_37___const__64b1 -D0712 15:11:01.578 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_37___const__64b1 -D0712 15:11:01.578 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_37___const__64b98 -D0712 15:11:01.578 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_37___const__64b98 -D0712 15:11:01.579 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_38___const__64b0 -D0712 15:11:01.579 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_38___const__64b0 -D0712 15:11:01.579 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_38___const__64b1 -D0712 15:11:01.579 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_38___const__64b1 -D0712 15:11:01.579 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_38___const__64b1 -D0712 15:11:01.579 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_38___const__64b1 -D0712 15:11:01.579 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_38___const__64b99 -D0712 15:11:01.579 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_38___const__64b99 -D0712 15:11:01.580 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_39___const__64b0 -D0712 15:11:01.580 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_39___const__64b0 -D0712 15:11:01.580 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_39___const__64b1 -D0712 15:11:01.580 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_39___const__64b1 -D0712 15:11:01.580 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_39___const__64b1 -D0712 15:11:01.580 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_39___const__64b1 -D0712 15:11:01.580 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_39___const__64b100 -D0712 15:11:01.580 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_39___const__64b100 -D0712 15:11:01.581 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_40___const__64b0 -D0712 15:11:01.581 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_40___const__64b0 -D0712 15:11:01.581 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_40___const__64b1 -D0712 15:11:01.581 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_40___const__64b1 -D0712 15:11:01.581 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_40___const__64b2 -D0712 15:11:01.581 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_40___const__64b2 -D0712 15:11:01.581 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_40___const__64b97 -D0712 15:11:01.581 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_40___const__64b97 -D0712 15:11:01.582 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_41___const__64b0 -D0712 15:11:01.582 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_41___const__64b0 -D0712 15:11:01.582 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_41___const__64b1 -D0712 15:11:01.582 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_41___const__64b1 -D0712 15:11:01.582 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_41___const__64b2 -D0712 15:11:01.582 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_41___const__64b2 -D0712 15:11:01.582 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_41___const__64b98 -D0712 15:11:01.582 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_41___const__64b98 -D0712 15:11:01.583 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_42___const__64b0 -D0712 15:11:01.583 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_42___const__64b0 -D0712 15:11:01.583 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_42___const__64b1 -D0712 15:11:01.583 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_42___const__64b1 -D0712 15:11:01.583 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_42___const__64b2 -D0712 15:11:01.583 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_42___const__64b2 -D0712 15:11:01.583 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_42___const__64b99 -D0712 15:11:01.583 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_42___const__64b99 -D0712 15:11:01.584 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_43___const__64b0 -D0712 15:11:01.584 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_43___const__64b0 -D0712 15:11:01.584 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_43___const__64b1 -D0712 15:11:01.584 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_43___const__64b1 -D0712 15:11:01.584 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_43___const__64b100 -D0712 15:11:01.584 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_43___const__64b100 -D0712 15:11:01.584 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_43___const__64b2 -D0712 15:11:01.584 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_43___const__64b2 -D0712 15:11:01.585 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_44___const__64b0 -D0712 15:11:01.585 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_44___const__64b0 -D0712 15:11:01.585 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_44___const__64b1 -D0712 15:11:01.585 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_44___const__64b1 -D0712 15:11:01.585 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_44___const__64b3 -D0712 15:11:01.585 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_44___const__64b3 -D0712 15:11:01.585 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_44___const__64b97 -D0712 15:11:01.585 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_44___const__64b97 -D0712 15:11:01.586 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_45___const__64b0 -D0712 15:11:01.586 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_45___const__64b0 -D0712 15:11:01.586 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_45___const__64b1 -D0712 15:11:01.586 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_45___const__64b1 -D0712 15:11:01.586 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_45___const__64b3 -D0712 15:11:01.586 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_45___const__64b3 -D0712 15:11:01.586 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_45___const__64b98 -D0712 15:11:01.586 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_45___const__64b98 -D0712 15:11:01.586 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_46___const__64b0 -D0712 15:11:01.586 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_46___const__64b0 -D0712 15:11:01.587 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_46___const__64b1 -D0712 15:11:01.587 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_46___const__64b1 -D0712 15:11:01.587 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_46___const__64b3 -D0712 15:11:01.587 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_46___const__64b3 -D0712 15:11:01.587 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_46___const__64b99 -D0712 15:11:01.587 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_46___const__64b99 -D0712 15:11:01.587 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_47___const__64b0 -D0712 15:11:01.587 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_47___const__64b0 -D0712 15:11:01.588 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_47___const__64b1 -D0712 15:11:01.588 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_47___const__64b1 -D0712 15:11:01.588 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_47___const__64b100 -D0712 15:11:01.588 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_47___const__64b100 -D0712 15:11:01.588 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_47___const__64b3 -D0712 15:11:01.588 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_47___const__64b3 -D0712 15:11:01.588 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_48___const__64b0 -D0712 15:11:01.588 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_48___const__64b0 -D0712 15:11:01.589 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_48___const__64b1 -D0712 15:11:01.589 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_48___const__64b1 -D0712 15:11:01.589 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_48___const__64b4 -D0712 15:11:01.589 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_48___const__64b4 -D0712 15:11:01.589 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_48___const__64b97 -D0712 15:11:01.589 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_48___const__64b97 -D0712 15:11:01.589 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_49___const__64b0 -D0712 15:11:01.589 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_49___const__64b0 -D0712 15:11:01.590 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_49___const__64b1 -D0712 15:11:01.590 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_49___const__64b1 -D0712 15:11:01.590 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_49___const__64b4 -D0712 15:11:01.590 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_49___const__64b4 -D0712 15:11:01.590 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_49___const__64b98 -D0712 15:11:01.590 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_49___const__64b98 -D0712 15:11:01.590 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_50___const__64b0 -D0712 15:11:01.590 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_50___const__64b0 -D0712 15:11:01.590 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_50___const__64b1 -D0712 15:11:01.590 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_50___const__64b1 -D0712 15:11:01.591 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_50___const__64b4 -D0712 15:11:01.591 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_50___const__64b4 -D0712 15:11:01.591 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_50___const__64b99 -D0712 15:11:01.591 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_50___const__64b99 -D0712 15:11:01.591 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_51___const__64b0 -D0712 15:11:01.591 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_51___const__64b0 -D0712 15:11:01.592 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_51___const__64b1 -D0712 15:11:01.592 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_51___const__64b1 -D0712 15:11:01.592 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_51___const__64b100 -D0712 15:11:01.592 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_51___const__64b100 -D0712 15:11:01.592 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_51___const__64b4 -D0712 15:11:01.592 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_51___const__64b4 -D0712 15:11:01.592 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_52___const__64b0 -D0712 15:11:01.592 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_52___const__64b0 -D0712 15:11:01.592 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_52___const__64b1 -D0712 15:11:01.592 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_52___const__64b1 -D0712 15:11:01.593 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_52___const__64b5 -D0712 15:11:01.593 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_52___const__64b5 -D0712 15:11:01.593 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_52___const__64b97 -D0712 15:11:01.593 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_52___const__64b97 -D0712 15:11:01.593 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_53___const__64b0 -D0712 15:11:01.593 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_53___const__64b0 -D0712 15:11:01.593 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_53___const__64b1 -D0712 15:11:01.593 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_53___const__64b1 -D0712 15:11:01.594 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_53___const__64b5 -D0712 15:11:01.594 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_53___const__64b5 -D0712 15:11:01.594 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_53___const__64b98 -D0712 15:11:01.594 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_53___const__64b98 -D0712 15:11:01.594 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_54___const__64b0 -D0712 15:11:01.594 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_54___const__64b0 -D0712 15:11:01.594 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_54___const__64b1 -D0712 15:11:01.594 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_54___const__64b1 -D0712 15:11:01.595 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_54___const__64b5 -D0712 15:11:01.595 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_54___const__64b5 -D0712 15:11:01.595 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_54___const__64b99 -D0712 15:11:01.595 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_54___const__64b99 -D0712 15:11:01.595 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_55___const__64b0 -D0712 15:11:01.595 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_55___const__64b0 -D0712 15:11:01.595 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_55___const__64b1 -D0712 15:11:01.595 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_55___const__64b1 -D0712 15:11:01.596 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_55___const__64b100 -D0712 15:11:01.596 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_55___const__64b100 -D0712 15:11:01.596 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_55___const__64b5 -D0712 15:11:01.596 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_55___const__64b5 -D0712 15:11:01.596 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_56___const__64b0 -D0712 15:11:01.596 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_56___const__64b0 -D0712 15:11:01.596 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_56___const__64b1 -D0712 15:11:01.596 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_56___const__64b1 -D0712 15:11:01.597 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_56___const__64b6 -D0712 15:11:01.597 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_56___const__64b6 -D0712 15:11:01.597 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_56___const__64b97 -D0712 15:11:01.597 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_56___const__64b97 -D0712 15:11:01.597 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_57___const__64b0 -D0712 15:11:01.597 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_57___const__64b0 -D0712 15:11:01.597 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_57___const__64b1 -D0712 15:11:01.597 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_57___const__64b1 -D0712 15:11:01.597 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_57___const__64b6 -D0712 15:11:01.597 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_57___const__64b6 -D0712 15:11:01.598 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_57___const__64b98 -D0712 15:11:01.598 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_57___const__64b98 -D0712 15:11:01.598 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_58___const__64b0 -D0712 15:11:01.598 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_58___const__64b0 -D0712 15:11:01.598 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_58___const__64b1 -D0712 15:11:01.598 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_58___const__64b1 -D0712 15:11:01.598 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_58___const__64b6 -D0712 15:11:01.598 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_58___const__64b6 -D0712 15:11:01.599 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_58___const__64b99 -D0712 15:11:01.599 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_58___const__64b99 -D0712 15:11:01.599 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_59___const__64b0 -D0712 15:11:01.599 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_59___const__64b0 -D0712 15:11:01.599 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_59___const__64b1 -D0712 15:11:01.599 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_59___const__64b1 -D0712 15:11:01.599 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_59___const__64b100 -D0712 15:11:01.599 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_59___const__64b100 -D0712 15:11:01.600 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_59___const__64b6 -D0712 15:11:01.600 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_59___const__64b6 -D0712 15:11:01.600 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_60___const__64b0 -D0712 15:11:01.600 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_60___const__64b0 -D0712 15:11:01.600 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_60___const__64b1 -D0712 15:11:01.600 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_60___const__64b1 -D0712 15:11:01.600 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_60___const__64b7 -D0712 15:11:01.600 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_60___const__64b7 -D0712 15:11:01.601 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_60___const__64b97 -D0712 15:11:01.601 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_60___const__64b97 -D0712 15:11:01.601 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_61___const__64b0 -D0712 15:11:01.601 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_61___const__64b0 -D0712 15:11:01.601 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_61___const__64b1 -D0712 15:11:01.601 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_61___const__64b1 -D0712 15:11:01.601 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_61___const__64b7 -D0712 15:11:01.601 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_61___const__64b7 -D0712 15:11:01.601 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_61___const__64b98 -D0712 15:11:01.601 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_61___const__64b98 -D0712 15:11:01.602 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_62___const__64b0 -D0712 15:11:01.602 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_62___const__64b0 -D0712 15:11:01.602 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_62___const__64b1 -D0712 15:11:01.602 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_62___const__64b1 -D0712 15:11:01.602 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_62___const__64b7 -D0712 15:11:01.602 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_62___const__64b7 -D0712 15:11:01.603 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_62___const__64b99 -D0712 15:11:01.603 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_62___const__64b99 -D0712 15:11:01.603 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_63___const__64b0 -D0712 15:11:01.603 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_63___const__64b0 -D0712 15:11:01.603 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_63___const__64b1 -D0712 15:11:01.603 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_63___const__64b1 -D0712 15:11:01.603 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_63___const__64b100 -D0712 15:11:01.603 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_63___const__64b100 -D0712 15:11:01.604 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_63___const__64b7 -D0712 15:11:01.604 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_63___const__64b7 -D0712 15:11:01.604 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_64___const__64b0 -D0712 15:11:01.604 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_64___const__64b0 -D0712 15:11:01.604 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_64___const__64b0 -D0712 15:11:01.604 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_64___const__64b0 -D0712 15:11:01.604 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_64___const__64b2 -D0712 15:11:01.604 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_64___const__64b2 -D0712 15:11:01.604 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_64___const__64b97 -D0712 15:11:01.604 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_64___const__64b97 -D0712 15:11:01.605 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_65___const__64b0 -D0712 15:11:01.605 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_65___const__64b0 -D0712 15:11:01.605 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_65___const__64b0 -D0712 15:11:01.605 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_65___const__64b0 -D0712 15:11:01.606 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_65___const__64b2 -D0712 15:11:01.606 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_65___const__64b2 -D0712 15:11:01.606 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_65___const__64b98 -D0712 15:11:01.606 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_65___const__64b98 -D0712 15:11:01.606 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_66___const__64b0 -D0712 15:11:01.606 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_66___const__64b0 -D0712 15:11:01.607 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_66___const__64b0 -D0712 15:11:01.607 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_66___const__64b0 -D0712 15:11:01.607 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_66___const__64b2 -D0712 15:11:01.607 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_66___const__64b2 -D0712 15:11:01.607 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_66___const__64b99 -D0712 15:11:01.607 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_66___const__64b99 -D0712 15:11:01.607 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_67___const__64b0 -D0712 15:11:01.607 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_67___const__64b0 -D0712 15:11:01.607 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_67___const__64b0 -D0712 15:11:01.607 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_67___const__64b0 -D0712 15:11:01.608 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_67___const__64b100 -D0712 15:11:01.608 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_67___const__64b100 -D0712 15:11:01.608 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_67___const__64b2 -D0712 15:11:01.608 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_67___const__64b2 -D0712 15:11:01.608 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_68___const__64b0 -D0712 15:11:01.608 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_68___const__64b0 -D0712 15:11:01.609 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_68___const__64b1 -D0712 15:11:01.609 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_68___const__64b1 -D0712 15:11:01.609 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_68___const__64b2 -D0712 15:11:01.609 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_68___const__64b2 -D0712 15:11:01.609 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_68___const__64b97 -D0712 15:11:01.609 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_68___const__64b97 -D0712 15:11:01.609 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_69___const__64b0 -D0712 15:11:01.609 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_69___const__64b0 -D0712 15:11:01.609 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_69___const__64b1 -D0712 15:11:01.609 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_69___const__64b1 -D0712 15:11:01.610 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_69___const__64b2 -D0712 15:11:01.610 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_69___const__64b2 -D0712 15:11:01.610 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_69___const__64b98 -D0712 15:11:01.610 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_69___const__64b98 -D0712 15:11:01.610 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_70___const__64b0 -D0712 15:11:01.610 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_70___const__64b0 -D0712 15:11:01.610 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_70___const__64b1 -D0712 15:11:01.610 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_70___const__64b1 -D0712 15:11:01.611 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_70___const__64b2 -D0712 15:11:01.611 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_70___const__64b2 -D0712 15:11:01.611 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_70___const__64b99 -D0712 15:11:01.611 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_70___const__64b99 -D0712 15:11:01.611 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_71___const__64b0 -D0712 15:11:01.611 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_71___const__64b0 -D0712 15:11:01.611 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_71___const__64b1 -D0712 15:11:01.611 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_71___const__64b1 -D0712 15:11:01.612 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_71___const__64b100 -D0712 15:11:01.612 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_71___const__64b100 -D0712 15:11:01.612 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_71___const__64b2 -D0712 15:11:01.612 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_71___const__64b2 -D0712 15:11:01.612 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_72___const__64b0 -D0712 15:11:01.612 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_72___const__64b0 -D0712 15:11:01.612 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_72___const__64b2 -D0712 15:11:01.612 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_72___const__64b2 -D0712 15:11:01.613 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_72___const__64b2 -D0712 15:11:01.613 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_72___const__64b2 -D0712 15:11:01.613 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_72___const__64b97 -D0712 15:11:01.613 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_72___const__64b97 -D0712 15:11:01.613 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_73___const__64b0 -D0712 15:11:01.613 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_73___const__64b0 -D0712 15:11:01.613 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_73___const__64b2 -D0712 15:11:01.613 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_73___const__64b2 -D0712 15:11:01.614 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_73___const__64b2 -D0712 15:11:01.614 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_73___const__64b2 -D0712 15:11:01.614 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_73___const__64b98 -D0712 15:11:01.614 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_73___const__64b98 -D0712 15:11:01.614 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_74___const__64b0 -D0712 15:11:01.614 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_74___const__64b0 -D0712 15:11:01.614 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_74___const__64b2 -D0712 15:11:01.614 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_74___const__64b2 -D0712 15:11:01.615 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_74___const__64b2 -D0712 15:11:01.615 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_74___const__64b2 -D0712 15:11:01.615 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_74___const__64b99 -D0712 15:11:01.615 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_74___const__64b99 -D0712 15:11:01.615 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_75___const__64b0 -D0712 15:11:01.615 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_75___const__64b0 -D0712 15:11:01.615 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_75___const__64b100 -D0712 15:11:01.615 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_75___const__64b100 -D0712 15:11:01.616 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_75___const__64b2 -D0712 15:11:01.616 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_75___const__64b2 -D0712 15:11:01.616 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_75___const__64b2 -D0712 15:11:01.616 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_75___const__64b2 -D0712 15:11:01.616 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_76___const__64b0 -D0712 15:11:01.616 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_76___const__64b0 -D0712 15:11:01.616 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_76___const__64b2 -D0712 15:11:01.616 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_76___const__64b2 -D0712 15:11:01.616 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_76___const__64b3 -D0712 15:11:01.616 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_76___const__64b3 -D0712 15:11:01.617 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_76___const__64b97 -D0712 15:11:01.617 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_76___const__64b97 -D0712 15:11:01.617 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_77___const__64b0 -D0712 15:11:01.617 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_77___const__64b0 -D0712 15:11:01.617 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_77___const__64b2 -D0712 15:11:01.617 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_77___const__64b2 -D0712 15:11:01.618 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_77___const__64b3 -D0712 15:11:01.618 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_77___const__64b3 -D0712 15:11:01.618 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_77___const__64b98 -D0712 15:11:01.618 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_77___const__64b98 -D0712 15:11:01.618 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_78___const__64b0 -D0712 15:11:01.618 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_78___const__64b0 -D0712 15:11:01.618 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_78___const__64b2 -D0712 15:11:01.618 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_78___const__64b2 -D0712 15:11:01.619 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_78___const__64b3 -D0712 15:11:01.619 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_78___const__64b3 -D0712 15:11:01.619 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_78___const__64b99 -D0712 15:11:01.619 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_78___const__64b99 -D0712 15:11:01.619 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_79___const__64b0 -D0712 15:11:01.619 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_79___const__64b0 -D0712 15:11:01.619 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_79___const__64b100 -D0712 15:11:01.619 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_79___const__64b100 -D0712 15:11:01.620 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_79___const__64b2 -D0712 15:11:01.620 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_79___const__64b2 -D0712 15:11:01.620 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_79___const__64b3 -D0712 15:11:01.620 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_79___const__64b3 -D0712 15:11:01.620 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_80___const__64b0 -D0712 15:11:01.620 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_80___const__64b0 -D0712 15:11:01.620 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_80___const__64b2 -D0712 15:11:01.620 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_80___const__64b2 -D0712 15:11:01.621 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_80___const__64b4 -D0712 15:11:01.621 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_80___const__64b4 -D0712 15:11:01.621 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_80___const__64b97 -D0712 15:11:01.621 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_80___const__64b97 -D0712 15:11:01.621 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_81___const__64b0 -D0712 15:11:01.621 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_81___const__64b0 -D0712 15:11:01.621 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_81___const__64b2 -D0712 15:11:01.621 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_81___const__64b2 -D0712 15:11:01.622 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_81___const__64b4 -D0712 15:11:01.622 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_81___const__64b4 -D0712 15:11:01.622 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_81___const__64b98 -D0712 15:11:01.622 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_81___const__64b98 -D0712 15:11:01.622 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_82___const__64b0 -D0712 15:11:01.622 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_82___const__64b0 -D0712 15:11:01.622 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_82___const__64b2 -D0712 15:11:01.622 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_82___const__64b2 -D0712 15:11:01.623 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_82___const__64b4 -D0712 15:11:01.623 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_82___const__64b4 -D0712 15:11:01.623 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_82___const__64b99 -D0712 15:11:01.623 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_82___const__64b99 -D0712 15:11:01.623 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_83___const__64b0 -D0712 15:11:01.623 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_83___const__64b0 -D0712 15:11:01.623 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_83___const__64b100 -D0712 15:11:01.623 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_83___const__64b100 -D0712 15:11:01.624 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_83___const__64b2 -D0712 15:11:01.624 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_83___const__64b2 -D0712 15:11:01.624 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_83___const__64b4 -D0712 15:11:01.624 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_83___const__64b4 -D0712 15:11:01.624 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_84___const__64b0 -D0712 15:11:01.624 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_84___const__64b0 -D0712 15:11:01.624 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_84___const__64b2 -D0712 15:11:01.624 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_84___const__64b2 -D0712 15:11:01.625 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_84___const__64b5 -D0712 15:11:01.625 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_84___const__64b5 -D0712 15:11:01.625 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_84___const__64b97 -D0712 15:11:01.625 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_84___const__64b97 -D0712 15:11:01.625 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_85___const__64b0 -D0712 15:11:01.625 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_85___const__64b0 -D0712 15:11:01.625 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_85___const__64b2 -D0712 15:11:01.625 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_85___const__64b2 -D0712 15:11:01.626 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_85___const__64b5 -D0712 15:11:01.626 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_85___const__64b5 -D0712 15:11:01.626 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_85___const__64b98 -D0712 15:11:01.626 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_85___const__64b98 -D0712 15:11:01.626 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_86___const__64b0 -D0712 15:11:01.626 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_86___const__64b0 -D0712 15:11:01.626 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_86___const__64b2 -D0712 15:11:01.626 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_86___const__64b2 -D0712 15:11:01.627 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_86___const__64b5 -D0712 15:11:01.627 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_86___const__64b5 -D0712 15:11:01.627 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_86___const__64b99 -D0712 15:11:01.627 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_86___const__64b99 -D0712 15:11:01.627 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_87___const__64b0 -D0712 15:11:01.627 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_87___const__64b0 -D0712 15:11:01.627 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_87___const__64b100 -D0712 15:11:01.627 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_87___const__64b100 -D0712 15:11:01.628 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_87___const__64b2 -D0712 15:11:01.628 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_87___const__64b2 -D0712 15:11:01.628 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_87___const__64b5 -D0712 15:11:01.628 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_87___const__64b5 -D0712 15:11:01.628 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_88___const__64b0 -D0712 15:11:01.628 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_88___const__64b0 -D0712 15:11:01.628 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_88___const__64b2 -D0712 15:11:01.628 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_88___const__64b2 -D0712 15:11:01.629 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_88___const__64b6 -D0712 15:11:01.629 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_88___const__64b6 -D0712 15:11:01.629 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_88___const__64b97 -D0712 15:11:01.629 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_88___const__64b97 -D0712 15:11:01.629 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_89___const__64b0 -D0712 15:11:01.629 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_89___const__64b0 -D0712 15:11:01.629 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_89___const__64b2 -D0712 15:11:01.629 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_89___const__64b2 -D0712 15:11:01.630 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_89___const__64b6 -D0712 15:11:01.630 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_89___const__64b6 -D0712 15:11:01.630 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_89___const__64b98 -D0712 15:11:01.630 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_89___const__64b98 -D0712 15:11:01.630 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_90___const__64b0 -D0712 15:11:01.630 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_90___const__64b0 -D0712 15:11:01.630 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_90___const__64b2 -D0712 15:11:01.630 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_90___const__64b2 -D0712 15:11:01.631 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_90___const__64b6 -D0712 15:11:01.631 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_90___const__64b6 -D0712 15:11:01.631 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_90___const__64b99 -D0712 15:11:01.631 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_90___const__64b99 -D0712 15:11:01.631 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_91___const__64b0 -D0712 15:11:01.631 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_91___const__64b0 -D0712 15:11:01.631 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_91___const__64b100 -D0712 15:11:01.631 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_91___const__64b100 -D0712 15:11:01.632 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_91___const__64b2 -D0712 15:11:01.632 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_91___const__64b2 -D0712 15:11:01.632 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_91___const__64b6 -D0712 15:11:01.632 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_91___const__64b6 -D0712 15:11:01.632 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_92___const__64b0 -D0712 15:11:01.632 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_92___const__64b0 -D0712 15:11:01.633 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_92___const__64b2 -D0712 15:11:01.633 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_92___const__64b2 -D0712 15:11:01.633 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_92___const__64b7 -D0712 15:11:01.633 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_92___const__64b7 -D0712 15:11:01.633 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_92___const__64b97 -D0712 15:11:01.633 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_92___const__64b97 -D0712 15:11:01.633 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_93___const__64b0 -D0712 15:11:01.633 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_93___const__64b0 -D0712 15:11:01.634 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_93___const__64b2 -D0712 15:11:01.634 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_93___const__64b2 -D0712 15:11:01.634 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_93___const__64b7 -D0712 15:11:01.634 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_93___const__64b7 -D0712 15:11:01.634 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_93___const__64b98 -D0712 15:11:01.634 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_93___const__64b98 -D0712 15:11:01.634 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_94___const__64b0 -D0712 15:11:01.634 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_94___const__64b0 -D0712 15:11:01.634 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_94___const__64b2 -D0712 15:11:01.634 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_94___const__64b2 -D0712 15:11:01.635 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_94___const__64b7 -D0712 15:11:01.635 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_94___const__64b7 -D0712 15:11:01.635 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_94___const__64b99 -D0712 15:11:01.635 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_94___const__64b99 -D0712 15:11:01.635 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_95___const__64b0 -D0712 15:11:01.635 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_95___const__64b0 -D0712 15:11:01.636 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_95___const__64b100 -D0712 15:11:01.636 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_95___const__64b100 -D0712 15:11:01.636 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_95___const__64b2 -D0712 15:11:01.636 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_95___const__64b2 -D0712 15:11:01.636 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_95___const__64b7 -D0712 15:11:01.636 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_95___const__64b7 -D0712 15:11:01.636 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_96___const__64b0 -D0712 15:11:01.636 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_96___const__64b0 -D0712 15:11:01.637 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_96___const__64b0 -D0712 15:11:01.637 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_96___const__64b0 -D0712 15:11:01.637 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_96___const__64b1 -D0712 15:11:01.637 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_96___const__64b1 -D0712 15:11:01.637 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_96___const__64b97 -D0712 15:11:01.637 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_96___const__64b97 -D0712 15:11:01.637 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_97___const__64b0 -D0712 15:11:01.637 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_97___const__64b0 -D0712 15:11:01.638 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_97___const__64b0 -D0712 15:11:01.638 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_97___const__64b0 -D0712 15:11:01.638 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_97___const__64b1 -D0712 15:11:01.638 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_97___const__64b1 -D0712 15:11:01.638 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_97___const__64b98 -D0712 15:11:01.638 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_97___const__64b98 -D0712 15:11:01.638 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_98___const__64b0 -D0712 15:11:01.638 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_98___const__64b0 -D0712 15:11:01.639 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_98___const__64b0 -D0712 15:11:01.639 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_98___const__64b0 -D0712 15:11:01.639 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_98___const__64b1 -D0712 15:11:01.639 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_98___const__64b1 -D0712 15:11:01.639 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_98___const__64b99 -D0712 15:11:01.639 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_98___const__64b99 -D0712 15:11:01.639 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_99___const__64b0 -D0712 15:11:01.639 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_99___const__64b0 -D0712 15:11:01.640 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_99___const__64b0 -D0712 15:11:01.640 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_99___const__64b0 -D0712 15:11:01.640 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_99___const__64b1 -D0712 15:11:01.640 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_99___const__64b1 -D0712 15:11:01.640 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_99___const__64b100 -D0712 15:11:01.640 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_99___const__64b100 -D0712 15:11:01.640 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_100___const__64b0 -D0712 15:11:01.640 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_100___const__64b0 -D0712 15:11:01.641 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_100___const__64b1 -D0712 15:11:01.641 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_100___const__64b1 -D0712 15:11:01.641 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_100___const__64b1 -D0712 15:11:01.641 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_100___const__64b1 -D0712 15:11:01.641 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_100___const__64b97 -D0712 15:11:01.641 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_100___const__64b97 -D0712 15:11:01.642 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_101___const__64b0 -D0712 15:11:01.642 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_101___const__64b0 -D0712 15:11:01.642 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_101___const__64b1 -D0712 15:11:01.642 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_101___const__64b1 -D0712 15:11:01.642 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_101___const__64b1 -D0712 15:11:01.642 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_101___const__64b1 -D0712 15:11:01.642 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_101___const__64b98 -D0712 15:11:01.642 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_101___const__64b98 -D0712 15:11:01.643 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_102___const__64b0 -D0712 15:11:01.643 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_102___const__64b0 -D0712 15:11:01.643 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_102___const__64b1 -D0712 15:11:01.643 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_102___const__64b1 -D0712 15:11:01.643 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_102___const__64b1 -D0712 15:11:01.643 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_102___const__64b1 -D0712 15:11:01.643 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_102___const__64b99 -D0712 15:11:01.643 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_102___const__64b99 -D0712 15:11:01.644 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_103___const__64b0 -D0712 15:11:01.644 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_103___const__64b0 -D0712 15:11:01.644 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_103___const__64b1 -D0712 15:11:01.644 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_103___const__64b1 -D0712 15:11:01.644 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_103___const__64b1 -D0712 15:11:01.644 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_103___const__64b1 -D0712 15:11:01.644 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_103___const__64b100 -D0712 15:11:01.644 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_103___const__64b100 -D0712 15:11:01.645 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_104___const__64b0 -D0712 15:11:01.645 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_104___const__64b0 -D0712 15:11:01.645 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_104___const__64b1 -D0712 15:11:01.645 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_104___const__64b1 -D0712 15:11:01.645 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_104___const__64b2 -D0712 15:11:01.645 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_104___const__64b2 -D0712 15:11:01.645 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_104___const__64b97 -D0712 15:11:01.645 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_104___const__64b97 -D0712 15:11:01.646 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_105___const__64b0 -D0712 15:11:01.646 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_105___const__64b0 -D0712 15:11:01.646 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_105___const__64b1 -D0712 15:11:01.646 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_105___const__64b1 -D0712 15:11:01.646 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_105___const__64b2 -D0712 15:11:01.646 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_105___const__64b2 -D0712 15:11:01.646 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_105___const__64b98 -D0712 15:11:01.646 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_105___const__64b98 -D0712 15:11:01.647 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_106___const__64b0 -D0712 15:11:01.647 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_106___const__64b0 -D0712 15:11:01.647 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_106___const__64b1 -D0712 15:11:01.647 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_106___const__64b1 -D0712 15:11:01.647 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_106___const__64b2 -D0712 15:11:01.647 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_106___const__64b2 -D0712 15:11:01.647 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_106___const__64b99 -D0712 15:11:01.647 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_106___const__64b99 -D0712 15:11:01.648 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_107___const__64b0 -D0712 15:11:01.648 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_107___const__64b0 -D0712 15:11:01.648 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_107___const__64b1 -D0712 15:11:01.648 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_107___const__64b1 -D0712 15:11:01.648 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_107___const__64b100 -D0712 15:11:01.648 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_107___const__64b100 -D0712 15:11:01.648 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_107___const__64b2 -D0712 15:11:01.648 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_107___const__64b2 -D0712 15:11:01.649 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_108___const__64b0 -D0712 15:11:01.649 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_108___const__64b0 -D0712 15:11:01.649 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_108___const__64b1 -D0712 15:11:01.649 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_108___const__64b1 -D0712 15:11:01.649 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_108___const__64b3 -D0712 15:11:01.649 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_108___const__64b3 -D0712 15:11:01.649 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_108___const__64b97 -D0712 15:11:01.649 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_108___const__64b97 -D0712 15:11:01.650 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_109___const__64b0 -D0712 15:11:01.650 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_109___const__64b0 -D0712 15:11:01.650 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_109___const__64b1 -D0712 15:11:01.650 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_109___const__64b1 -D0712 15:11:01.650 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_109___const__64b3 -D0712 15:11:01.650 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_109___const__64b3 -D0712 15:11:01.650 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_109___const__64b98 -D0712 15:11:01.650 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_109___const__64b98 -D0712 15:11:01.651 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_110___const__64b0 -D0712 15:11:01.651 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_110___const__64b0 -D0712 15:11:01.651 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_110___const__64b1 -D0712 15:11:01.651 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_110___const__64b1 -D0712 15:11:01.651 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_110___const__64b3 -D0712 15:11:01.651 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_110___const__64b3 -D0712 15:11:01.651 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_110___const__64b99 -D0712 15:11:01.651 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_110___const__64b99 -D0712 15:11:01.652 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_111___const__64b0 -D0712 15:11:01.652 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_111___const__64b0 -D0712 15:11:01.652 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_111___const__64b1 -D0712 15:11:01.652 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_111___const__64b1 -D0712 15:11:01.652 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_111___const__64b100 -D0712 15:11:01.652 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_111___const__64b100 -D0712 15:11:01.652 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_111___const__64b3 -D0712 15:11:01.652 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_111___const__64b3 -D0712 15:11:01.653 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_112___const__64b0 -D0712 15:11:01.653 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_112___const__64b0 -D0712 15:11:01.653 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_112___const__64b1 -D0712 15:11:01.653 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_112___const__64b1 -D0712 15:11:01.653 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_112___const__64b4 -D0712 15:11:01.653 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_112___const__64b4 -D0712 15:11:01.653 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_112___const__64b97 -D0712 15:11:01.653 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_112___const__64b97 -D0712 15:11:01.654 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_113___const__64b0 -D0712 15:11:01.654 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_113___const__64b0 -D0712 15:11:01.654 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_113___const__64b1 -D0712 15:11:01.654 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_113___const__64b1 -D0712 15:11:01.654 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_113___const__64b4 -D0712 15:11:01.654 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_113___const__64b4 -D0712 15:11:01.655 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_113___const__64b98 -D0712 15:11:01.655 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_113___const__64b98 -D0712 15:11:01.655 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_114___const__64b0 -D0712 15:11:01.655 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_114___const__64b0 -D0712 15:11:01.655 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_114___const__64b1 -D0712 15:11:01.655 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_114___const__64b1 -D0712 15:11:01.655 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_114___const__64b4 -D0712 15:11:01.655 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_114___const__64b4 -D0712 15:11:01.656 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_114___const__64b99 -D0712 15:11:01.656 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_114___const__64b99 -D0712 15:11:01.656 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_115___const__64b0 -D0712 15:11:01.656 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_115___const__64b0 -D0712 15:11:01.656 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_115___const__64b1 -D0712 15:11:01.656 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_115___const__64b1 -D0712 15:11:01.656 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_115___const__64b100 -D0712 15:11:01.656 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_115___const__64b100 -D0712 15:11:01.657 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_115___const__64b4 -D0712 15:11:01.657 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_115___const__64b4 -D0712 15:11:01.657 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_116___const__64b0 -D0712 15:11:01.657 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_116___const__64b0 -D0712 15:11:01.657 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_116___const__64b1 -D0712 15:11:01.657 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_116___const__64b1 -D0712 15:11:01.658 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_116___const__64b5 -D0712 15:11:01.658 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_116___const__64b5 -D0712 15:11:01.658 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_116___const__64b97 -D0712 15:11:01.658 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_116___const__64b97 -D0712 15:11:01.658 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_117___const__64b0 -D0712 15:11:01.658 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_117___const__64b0 -D0712 15:11:01.658 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_117___const__64b1 -D0712 15:11:01.658 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_117___const__64b1 -D0712 15:11:01.659 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_117___const__64b5 -D0712 15:11:01.659 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_117___const__64b5 -D0712 15:11:01.659 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_117___const__64b98 -D0712 15:11:01.659 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_117___const__64b98 -D0712 15:11:01.659 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_118___const__64b0 -D0712 15:11:01.659 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_118___const__64b0 -D0712 15:11:01.659 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_118___const__64b1 -D0712 15:11:01.659 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_118___const__64b1 -D0712 15:11:01.660 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_118___const__64b5 -D0712 15:11:01.660 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_118___const__64b5 -D0712 15:11:01.660 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_118___const__64b99 -D0712 15:11:01.660 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_118___const__64b99 -D0712 15:11:01.660 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_119___const__64b0 -D0712 15:11:01.660 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_119___const__64b0 -D0712 15:11:01.660 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_119___const__64b1 -D0712 15:11:01.660 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_119___const__64b1 -D0712 15:11:01.661 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_119___const__64b100 -D0712 15:11:01.661 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_119___const__64b100 -D0712 15:11:01.661 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_119___const__64b5 -D0712 15:11:01.661 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_119___const__64b5 -D0712 15:11:01.661 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_120___const__64b0 -D0712 15:11:01.661 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_120___const__64b0 -D0712 15:11:01.661 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_120___const__64b1 -D0712 15:11:01.661 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_120___const__64b1 -D0712 15:11:01.662 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_120___const__64b6 -D0712 15:11:01.662 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_120___const__64b6 -D0712 15:11:01.662 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_120___const__64b97 -D0712 15:11:01.662 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_120___const__64b97 -D0712 15:11:01.662 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_121___const__64b0 -D0712 15:11:01.662 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_121___const__64b0 -D0712 15:11:01.662 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_121___const__64b1 -D0712 15:11:01.662 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_121___const__64b1 -D0712 15:11:01.663 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_121___const__64b6 -D0712 15:11:01.663 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_121___const__64b6 -D0712 15:11:01.663 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_121___const__64b98 -D0712 15:11:01.663 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_121___const__64b98 -D0712 15:11:01.663 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_122___const__64b0 -D0712 15:11:01.663 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_122___const__64b0 -D0712 15:11:01.664 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_122___const__64b1 -D0712 15:11:01.664 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_122___const__64b1 -D0712 15:11:01.664 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_122___const__64b6 -D0712 15:11:01.664 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_122___const__64b6 -D0712 15:11:01.664 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_122___const__64b99 -D0712 15:11:01.664 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_122___const__64b99 -D0712 15:11:01.664 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_123___const__64b0 -D0712 15:11:01.664 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_123___const__64b0 -D0712 15:11:01.665 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_123___const__64b1 -D0712 15:11:01.665 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_123___const__64b1 -D0712 15:11:01.665 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_123___const__64b100 -D0712 15:11:01.665 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_123___const__64b100 -D0712 15:11:01.665 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_123___const__64b6 -D0712 15:11:01.665 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_123___const__64b6 -D0712 15:11:01.665 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_124___const__64b0 -D0712 15:11:01.665 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_124___const__64b0 -D0712 15:11:01.666 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_124___const__64b1 -D0712 15:11:01.666 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_124___const__64b1 -D0712 15:11:01.666 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_124___const__64b7 -D0712 15:11:01.666 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_124___const__64b7 -D0712 15:11:01.666 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_124___const__64b97 -D0712 15:11:01.666 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_124___const__64b97 -D0712 15:11:01.667 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_125___const__64b0 -D0712 15:11:01.667 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_125___const__64b0 -D0712 15:11:01.667 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_125___const__64b1 -D0712 15:11:01.667 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_125___const__64b1 -D0712 15:11:01.667 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_125___const__64b7 -D0712 15:11:01.667 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_125___const__64b7 -D0712 15:11:01.667 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_125___const__64b98 -D0712 15:11:01.667 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_125___const__64b98 -D0712 15:11:01.668 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_126___const__64b0 -D0712 15:11:01.668 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_126___const__64b0 -D0712 15:11:01.668 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_126___const__64b1 -D0712 15:11:01.668 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_126___const__64b1 -D0712 15:11:01.668 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_126___const__64b7 -D0712 15:11:01.668 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_126___const__64b7 -D0712 15:11:01.668 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_126___const__64b99 -D0712 15:11:01.668 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_126___const__64b99 -D0712 15:11:01.669 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_127___const__64b0 -D0712 15:11:01.669 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_127___const__64b0 -D0712 15:11:01.669 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_127___const__64b1 -D0712 15:11:01.669 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_127___const__64b1 -D0712 15:11:01.669 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_127___const__64b100 -D0712 15:11:01.669 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_127___const__64b100 -D0712 15:11:01.669 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_127___const__64b7 -D0712 15:11:01.669 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_127___const__64b7 -D0712 15:11:01.670 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_128___const__64b0 -D0712 15:11:01.670 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_128___const__64b0 -D0712 15:11:01.670 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_128___const__64b1 -D0712 15:11:01.670 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_128___const__64b1 -D0712 15:11:01.670 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_128___const__64b1 -D0712 15:11:01.670 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_128___const__64b1 -D0712 15:11:01.670 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_128___const__64b97 -D0712 15:11:01.670 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_128___const__64b97 -D0712 15:11:01.671 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_129___const__64b0 -D0712 15:11:01.671 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_129___const__64b0 -D0712 15:11:01.671 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_129___const__64b1 -D0712 15:11:01.671 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_129___const__64b1 -D0712 15:11:01.671 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_129___const__64b1 -D0712 15:11:01.671 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_129___const__64b1 -D0712 15:11:01.671 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_129___const__64b98 -D0712 15:11:01.671 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_129___const__64b98 -D0712 15:11:01.672 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_130___const__64b0 -D0712 15:11:01.672 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_130___const__64b0 -D0712 15:11:01.672 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_130___const__64b1 -D0712 15:11:01.672 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_130___const__64b1 -D0712 15:11:01.672 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_130___const__64b1 -D0712 15:11:01.672 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_130___const__64b1 -D0712 15:11:01.672 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_130___const__64b99 -D0712 15:11:01.672 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_130___const__64b99 -D0712 15:11:01.673 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_131___const__64b0 -D0712 15:11:01.673 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_131___const__64b0 -D0712 15:11:01.673 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_131___const__64b1 -D0712 15:11:01.673 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_131___const__64b1 -D0712 15:11:01.673 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_131___const__64b1 -D0712 15:11:01.673 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_131___const__64b1 -D0712 15:11:01.673 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_131___const__64b100 -D0712 15:11:01.673 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_131___const__64b100 -D0712 15:11:01.674 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_132___const__64b1 -D0712 15:11:01.674 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_132___const__64b1 -D0712 15:11:01.674 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_132___const__64b1 -D0712 15:11:01.674 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_132___const__64b1 -D0712 15:11:01.674 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_132___const__64b1 -D0712 15:11:01.674 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_132___const__64b1 -D0712 15:11:01.674 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_132___const__64b97 -D0712 15:11:01.674 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_132___const__64b97 -D0712 15:11:01.675 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_133___const__64b1 -D0712 15:11:01.675 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_133___const__64b1 -D0712 15:11:01.675 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_133___const__64b1 -D0712 15:11:01.675 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_133___const__64b1 -D0712 15:11:01.675 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_133___const__64b1 -D0712 15:11:01.675 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_133___const__64b1 -D0712 15:11:01.675 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_133___const__64b98 -D0712 15:11:01.675 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_133___const__64b98 -D0712 15:11:01.676 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_134___const__64b1 -D0712 15:11:01.676 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_134___const__64b1 -D0712 15:11:01.676 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_134___const__64b1 -D0712 15:11:01.676 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_134___const__64b1 -D0712 15:11:01.676 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_134___const__64b1 -D0712 15:11:01.676 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_134___const__64b1 -D0712 15:11:01.676 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_134___const__64b99 -D0712 15:11:01.676 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_134___const__64b99 -D0712 15:11:01.677 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_135___const__64b1 -D0712 15:11:01.677 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_135___const__64b1 -D0712 15:11:01.677 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_135___const__64b1 -D0712 15:11:01.677 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_135___const__64b1 -D0712 15:11:01.677 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_135___const__64b1 -D0712 15:11:01.677 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_135___const__64b1 -D0712 15:11:01.677 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_135___const__64b100 -D0712 15:11:01.677 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_135___const__64b100 -D0712 15:11:01.678 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_136___const__64b1 -D0712 15:11:01.678 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_136___const__64b1 -D0712 15:11:01.679 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_136___const__64b1 -D0712 15:11:01.679 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_136___const__64b1 -D0712 15:11:01.679 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_136___const__64b2 -D0712 15:11:01.679 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_136___const__64b2 -D0712 15:11:01.679 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_136___const__64b97 -D0712 15:11:01.679 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_136___const__64b97 -D0712 15:11:01.679 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_137___const__64b1 -D0712 15:11:01.679 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_137___const__64b1 -D0712 15:11:01.680 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_137___const__64b1 -D0712 15:11:01.680 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_137___const__64b1 -D0712 15:11:01.680 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_137___const__64b2 -D0712 15:11:01.680 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_137___const__64b2 -D0712 15:11:01.680 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_137___const__64b98 -D0712 15:11:01.680 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_137___const__64b98 -D0712 15:11:01.680 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_138___const__64b1 -D0712 15:11:01.680 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_138___const__64b1 -D0712 15:11:01.681 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_138___const__64b1 -D0712 15:11:01.681 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_138___const__64b1 -D0712 15:11:01.681 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_138___const__64b2 -D0712 15:11:01.681 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_138___const__64b2 -D0712 15:11:01.681 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_138___const__64b99 -D0712 15:11:01.681 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_138___const__64b99 -D0712 15:11:01.682 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_139___const__64b1 -D0712 15:11:01.682 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_139___const__64b1 -D0712 15:11:01.682 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_139___const__64b1 -D0712 15:11:01.682 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_139___const__64b1 -D0712 15:11:01.682 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_139___const__64b100 -D0712 15:11:01.682 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_139___const__64b100 -D0712 15:11:01.682 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_139___const__64b2 -D0712 15:11:01.682 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_139___const__64b2 -D0712 15:11:01.683 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_140___const__64b1 -D0712 15:11:01.683 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_140___const__64b1 -D0712 15:11:01.683 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_140___const__64b1 -D0712 15:11:01.683 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_140___const__64b1 -D0712 15:11:01.683 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_140___const__64b3 -D0712 15:11:01.683 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_140___const__64b3 -D0712 15:11:01.683 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_140___const__64b97 -D0712 15:11:01.683 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_140___const__64b97 -D0712 15:11:01.684 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_141___const__64b1 -D0712 15:11:01.684 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_141___const__64b1 -D0712 15:11:01.684 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_141___const__64b1 -D0712 15:11:01.684 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_141___const__64b1 -D0712 15:11:01.684 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_141___const__64b3 -D0712 15:11:01.684 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_141___const__64b3 -D0712 15:11:01.684 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_141___const__64b98 -D0712 15:11:01.684 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_141___const__64b98 -D0712 15:11:01.685 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_142___const__64b1 -D0712 15:11:01.685 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_142___const__64b1 -D0712 15:11:01.685 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_142___const__64b1 -D0712 15:11:01.685 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_142___const__64b1 -D0712 15:11:01.685 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_142___const__64b3 -D0712 15:11:01.685 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_142___const__64b3 -D0712 15:11:01.685 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_142___const__64b99 -D0712 15:11:01.685 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_142___const__64b99 -D0712 15:11:01.686 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_143___const__64b1 -D0712 15:11:01.686 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_143___const__64b1 -D0712 15:11:01.686 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_143___const__64b1 -D0712 15:11:01.686 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_143___const__64b1 -D0712 15:11:01.686 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_143___const__64b100 -D0712 15:11:01.686 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_143___const__64b100 -D0712 15:11:01.686 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_143___const__64b3 -D0712 15:11:01.686 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_143___const__64b3 -D0712 15:11:01.687 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_144___const__64b1 -D0712 15:11:01.687 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_144___const__64b1 -D0712 15:11:01.687 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_144___const__64b1 -D0712 15:11:01.687 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_144___const__64b1 -D0712 15:11:01.687 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_144___const__64b4 -D0712 15:11:01.687 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_144___const__64b4 -D0712 15:11:01.687 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_144___const__64b97 -D0712 15:11:01.687 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_144___const__64b97 -D0712 15:11:01.688 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_145___const__64b1 -D0712 15:11:01.688 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_145___const__64b1 -D0712 15:11:01.688 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_145___const__64b1 -D0712 15:11:01.688 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_145___const__64b1 -D0712 15:11:01.688 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_145___const__64b4 -D0712 15:11:01.688 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_145___const__64b4 -D0712 15:11:01.688 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_145___const__64b98 -D0712 15:11:01.688 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_145___const__64b98 -D0712 15:11:01.689 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_146___const__64b1 -D0712 15:11:01.689 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_146___const__64b1 -D0712 15:11:01.689 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_146___const__64b1 -D0712 15:11:01.689 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_146___const__64b1 -D0712 15:11:01.689 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_146___const__64b4 -D0712 15:11:01.689 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_146___const__64b4 -D0712 15:11:01.689 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_146___const__64b99 -D0712 15:11:01.689 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_146___const__64b99 -D0712 15:11:01.690 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_147___const__64b1 -D0712 15:11:01.690 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_147___const__64b1 -D0712 15:11:01.690 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_147___const__64b1 -D0712 15:11:01.690 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_147___const__64b1 -D0712 15:11:01.690 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_147___const__64b100 -D0712 15:11:01.690 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_147___const__64b100 -D0712 15:11:01.690 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_147___const__64b4 -D0712 15:11:01.690 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_147___const__64b4 -D0712 15:11:01.691 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_148___const__64b1 -D0712 15:11:01.691 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_148___const__64b1 -D0712 15:11:01.691 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_148___const__64b1 -D0712 15:11:01.691 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_148___const__64b1 -D0712 15:11:01.691 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_148___const__64b5 -D0712 15:11:01.691 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_148___const__64b5 -D0712 15:11:01.691 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_148___const__64b97 -D0712 15:11:01.691 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_148___const__64b97 -D0712 15:11:01.692 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_149___const__64b1 -D0712 15:11:01.692 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_149___const__64b1 -D0712 15:11:01.692 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_149___const__64b1 -D0712 15:11:01.692 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_149___const__64b1 -D0712 15:11:01.692 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_149___const__64b5 -D0712 15:11:01.692 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_149___const__64b5 -D0712 15:11:01.693 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_149___const__64b98 -D0712 15:11:01.693 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_149___const__64b98 -D0712 15:11:01.693 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_150___const__64b1 -D0712 15:11:01.693 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_150___const__64b1 -D0712 15:11:01.693 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_150___const__64b1 -D0712 15:11:01.693 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_150___const__64b1 -D0712 15:11:01.693 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_150___const__64b5 -D0712 15:11:01.693 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_150___const__64b5 -D0712 15:11:01.694 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_150___const__64b99 -D0712 15:11:01.694 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_150___const__64b99 -D0712 15:11:01.694 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_151___const__64b1 -D0712 15:11:01.694 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_151___const__64b1 -D0712 15:11:01.694 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_151___const__64b1 -D0712 15:11:01.694 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_151___const__64b1 -D0712 15:11:01.695 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_151___const__64b100 -D0712 15:11:01.695 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_151___const__64b100 -D0712 15:11:01.695 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_151___const__64b5 -D0712 15:11:01.695 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_151___const__64b5 -D0712 15:11:01.695 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_152___const__64b1 -D0712 15:11:01.695 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_152___const__64b1 -D0712 15:11:01.695 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_152___const__64b1 -D0712 15:11:01.695 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_152___const__64b1 -D0712 15:11:01.696 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_152___const__64b6 -D0712 15:11:01.696 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_152___const__64b6 -D0712 15:11:01.696 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_152___const__64b97 -D0712 15:11:01.696 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_152___const__64b97 -D0712 15:11:01.696 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_153___const__64b1 -D0712 15:11:01.696 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_153___const__64b1 -D0712 15:11:01.696 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_153___const__64b1 -D0712 15:11:01.696 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_153___const__64b1 -D0712 15:11:01.697 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_153___const__64b6 -D0712 15:11:01.697 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_153___const__64b6 -D0712 15:11:01.697 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_153___const__64b98 -D0712 15:11:01.697 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_153___const__64b98 -D0712 15:11:01.697 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_154___const__64b1 -D0712 15:11:01.697 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_154___const__64b1 -D0712 15:11:01.698 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_154___const__64b1 -D0712 15:11:01.698 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_154___const__64b1 -D0712 15:11:01.698 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_154___const__64b6 -D0712 15:11:01.698 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_154___const__64b6 -D0712 15:11:01.698 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_154___const__64b99 -D0712 15:11:01.698 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_154___const__64b99 -D0712 15:11:01.698 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_155___const__64b1 -D0712 15:11:01.698 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_155___const__64b1 -D0712 15:11:01.699 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_155___const__64b1 -D0712 15:11:01.699 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_155___const__64b1 -D0712 15:11:01.699 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_155___const__64b100 -D0712 15:11:01.699 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_155___const__64b100 -D0712 15:11:01.699 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_155___const__64b6 -D0712 15:11:01.699 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_155___const__64b6 -D0712 15:11:01.700 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_156___const__64b1 -D0712 15:11:01.700 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_156___const__64b1 -D0712 15:11:01.700 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_156___const__64b1 -D0712 15:11:01.700 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_156___const__64b1 -D0712 15:11:01.700 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_156___const__64b7 -D0712 15:11:01.700 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_156___const__64b7 -D0712 15:11:01.700 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_156___const__64b97 -D0712 15:11:01.700 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_156___const__64b97 -D0712 15:11:01.701 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_157___const__64b1 -D0712 15:11:01.701 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_157___const__64b1 -D0712 15:11:01.701 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_157___const__64b1 -D0712 15:11:01.701 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_157___const__64b1 -D0712 15:11:01.701 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_157___const__64b7 -D0712 15:11:01.701 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_157___const__64b7 -D0712 15:11:01.701 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_157___const__64b98 -D0712 15:11:01.701 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_157___const__64b98 -D0712 15:11:01.702 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_158___const__64b1 -D0712 15:11:01.702 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_158___const__64b1 -D0712 15:11:01.702 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_158___const__64b1 -D0712 15:11:01.702 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_158___const__64b1 -D0712 15:11:01.702 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_158___const__64b7 -D0712 15:11:01.702 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_158___const__64b7 -D0712 15:11:01.702 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_158___const__64b99 -D0712 15:11:01.702 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_158___const__64b99 -D0712 15:11:01.703 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_159___const__64b1 -D0712 15:11:01.703 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_159___const__64b1 -D0712 15:11:01.703 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_159___const__64b1 -D0712 15:11:01.703 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_159___const__64b1 -D0712 15:11:01.703 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_159___const__64b100 -D0712 15:11:01.703 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_159___const__64b100 -D0712 15:11:01.703 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_159___const__64b7 -D0712 15:11:01.703 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_159___const__64b7 -D0712 15:11:01.704 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_160___const__64b0 -D0712 15:11:01.704 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_160___const__64b0 -D0712 15:11:01.704 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_160___const__64b1 -D0712 15:11:01.704 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_160___const__64b1 -D0712 15:11:01.704 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_160___const__64b2 -D0712 15:11:01.704 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_160___const__64b2 -D0712 15:11:01.704 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_160___const__64b97 -D0712 15:11:01.704 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_160___const__64b97 -D0712 15:11:01.705 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_161___const__64b0 -D0712 15:11:01.705 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_161___const__64b0 -D0712 15:11:01.705 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_161___const__64b1 -D0712 15:11:01.705 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_161___const__64b1 -D0712 15:11:01.705 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_161___const__64b2 -D0712 15:11:01.705 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_161___const__64b2 -D0712 15:11:01.705 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_161___const__64b98 -D0712 15:11:01.705 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_161___const__64b98 -D0712 15:11:01.706 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_162___const__64b0 -D0712 15:11:01.706 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_162___const__64b0 -D0712 15:11:01.706 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_162___const__64b1 -D0712 15:11:01.706 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_162___const__64b1 -D0712 15:11:01.706 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_162___const__64b2 -D0712 15:11:01.706 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_162___const__64b2 -D0712 15:11:01.707 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_162___const__64b99 -D0712 15:11:01.707 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_162___const__64b99 -D0712 15:11:01.707 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_163___const__64b0 -D0712 15:11:01.707 tapa.core:671] pipelined signal: 64'd0 => bloom_hier_arbiter_atom_163___const__64b0 -D0712 15:11:01.707 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_163___const__64b1 -D0712 15:11:01.707 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_163___const__64b1 -D0712 15:11:01.708 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_163___const__64b100 -D0712 15:11:01.708 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_163___const__64b100 -D0712 15:11:01.708 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_163___const__64b2 -D0712 15:11:01.708 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_163___const__64b2 -D0712 15:11:01.708 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_164___const__64b1 -D0712 15:11:01.708 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_164___const__64b1 -D0712 15:11:01.709 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_164___const__64b1 -D0712 15:11:01.709 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_164___const__64b1 -D0712 15:11:01.709 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_164___const__64b2 -D0712 15:11:01.709 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_164___const__64b2 -D0712 15:11:01.709 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_164___const__64b97 -D0712 15:11:01.709 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_164___const__64b97 -D0712 15:11:01.709 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_165___const__64b1 -D0712 15:11:01.709 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_165___const__64b1 -D0712 15:11:01.710 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_165___const__64b1 -D0712 15:11:01.710 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_165___const__64b1 -D0712 15:11:01.710 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_165___const__64b2 -D0712 15:11:01.710 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_165___const__64b2 -D0712 15:11:01.710 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_165___const__64b98 -D0712 15:11:01.710 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_165___const__64b98 -D0712 15:11:01.711 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_166___const__64b1 -D0712 15:11:01.711 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_166___const__64b1 -D0712 15:11:01.711 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_166___const__64b1 -D0712 15:11:01.711 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_166___const__64b1 -D0712 15:11:01.711 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_166___const__64b2 -D0712 15:11:01.711 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_166___const__64b2 -D0712 15:11:01.711 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_166___const__64b99 -D0712 15:11:01.711 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_166___const__64b99 -D0712 15:11:01.712 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_167___const__64b1 -D0712 15:11:01.712 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_167___const__64b1 -D0712 15:11:01.712 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_167___const__64b1 -D0712 15:11:01.712 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_167___const__64b1 -D0712 15:11:01.712 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_167___const__64b100 -D0712 15:11:01.712 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_167___const__64b100 -D0712 15:11:01.712 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_167___const__64b2 -D0712 15:11:01.712 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_167___const__64b2 -D0712 15:11:01.713 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_168___const__64b1 -D0712 15:11:01.713 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_168___const__64b1 -D0712 15:11:01.713 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_168___const__64b2 -D0712 15:11:01.713 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_168___const__64b2 -D0712 15:11:01.713 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_168___const__64b2 -D0712 15:11:01.713 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_168___const__64b2 -D0712 15:11:01.713 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_168___const__64b97 -D0712 15:11:01.713 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_168___const__64b97 -D0712 15:11:01.714 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_169___const__64b1 -D0712 15:11:01.714 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_169___const__64b1 -D0712 15:11:01.714 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_169___const__64b2 -D0712 15:11:01.714 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_169___const__64b2 -D0712 15:11:01.714 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_169___const__64b2 -D0712 15:11:01.714 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_169___const__64b2 -D0712 15:11:01.714 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_169___const__64b98 -D0712 15:11:01.714 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_169___const__64b98 -D0712 15:11:01.715 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_170___const__64b1 -D0712 15:11:01.715 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_170___const__64b1 -D0712 15:11:01.715 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_170___const__64b2 -D0712 15:11:01.715 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_170___const__64b2 -D0712 15:11:01.715 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_170___const__64b2 -D0712 15:11:01.715 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_170___const__64b2 -D0712 15:11:01.715 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_170___const__64b99 -D0712 15:11:01.715 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_170___const__64b99 -D0712 15:11:01.716 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_171___const__64b1 -D0712 15:11:01.716 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_171___const__64b1 -D0712 15:11:01.716 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_171___const__64b100 -D0712 15:11:01.716 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_171___const__64b100 -D0712 15:11:01.716 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_171___const__64b2 -D0712 15:11:01.716 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_171___const__64b2 -D0712 15:11:01.716 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_171___const__64b2 -D0712 15:11:01.716 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_171___const__64b2 -D0712 15:11:01.717 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_172___const__64b1 -D0712 15:11:01.717 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_172___const__64b1 -D0712 15:11:01.717 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_172___const__64b2 -D0712 15:11:01.717 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_172___const__64b2 -D0712 15:11:01.718 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_172___const__64b3 -D0712 15:11:01.718 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_172___const__64b3 -D0712 15:11:01.718 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_172___const__64b97 -D0712 15:11:01.718 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_172___const__64b97 -D0712 15:11:01.718 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_173___const__64b1 -D0712 15:11:01.718 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_173___const__64b1 -D0712 15:11:01.719 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_173___const__64b2 -D0712 15:11:01.719 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_173___const__64b2 -D0712 15:11:01.719 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_173___const__64b3 -D0712 15:11:01.719 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_173___const__64b3 -D0712 15:11:01.719 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_173___const__64b98 -D0712 15:11:01.719 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_173___const__64b98 -D0712 15:11:01.719 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_174___const__64b1 -D0712 15:11:01.719 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_174___const__64b1 -D0712 15:11:01.720 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_174___const__64b2 -D0712 15:11:01.720 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_174___const__64b2 -D0712 15:11:01.720 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_174___const__64b3 -D0712 15:11:01.720 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_174___const__64b3 -D0712 15:11:01.720 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_174___const__64b99 -D0712 15:11:01.720 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_174___const__64b99 -D0712 15:11:01.739 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_175___const__64b1 -D0712 15:11:01.739 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_175___const__64b1 -D0712 15:11:01.739 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_175___const__64b100 -D0712 15:11:01.739 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_175___const__64b100 -D0712 15:11:01.739 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_175___const__64b2 -D0712 15:11:01.739 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_175___const__64b2 -D0712 15:11:01.740 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_175___const__64b3 -D0712 15:11:01.740 tapa.core:671] pipelined signal: 64'd3 => bloom_hier_arbiter_atom_175___const__64b3 -D0712 15:11:01.740 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_176___const__64b1 -D0712 15:11:01.740 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_176___const__64b1 -D0712 15:11:01.740 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_176___const__64b2 -D0712 15:11:01.740 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_176___const__64b2 -D0712 15:11:01.741 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_176___const__64b4 -D0712 15:11:01.741 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_176___const__64b4 -D0712 15:11:01.741 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_176___const__64b97 -D0712 15:11:01.741 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_176___const__64b97 -D0712 15:11:01.741 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_177___const__64b1 -D0712 15:11:01.741 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_177___const__64b1 -D0712 15:11:01.742 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_177___const__64b2 -D0712 15:11:01.742 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_177___const__64b2 -D0712 15:11:01.742 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_177___const__64b4 -D0712 15:11:01.742 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_177___const__64b4 -D0712 15:11:01.742 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_177___const__64b98 -D0712 15:11:01.742 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_177___const__64b98 -D0712 15:11:01.742 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_178___const__64b1 -D0712 15:11:01.742 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_178___const__64b1 -D0712 15:11:01.743 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_178___const__64b2 -D0712 15:11:01.743 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_178___const__64b2 -D0712 15:11:01.743 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_178___const__64b4 -D0712 15:11:01.743 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_178___const__64b4 -D0712 15:11:01.743 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_178___const__64b99 -D0712 15:11:01.743 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_178___const__64b99 -D0712 15:11:01.744 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_179___const__64b1 -D0712 15:11:01.744 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_179___const__64b1 -D0712 15:11:01.744 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_179___const__64b100 -D0712 15:11:01.744 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_179___const__64b100 -D0712 15:11:01.744 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_179___const__64b2 -D0712 15:11:01.744 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_179___const__64b2 -D0712 15:11:01.744 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_179___const__64b4 -D0712 15:11:01.744 tapa.core:671] pipelined signal: 64'd4 => bloom_hier_arbiter_atom_179___const__64b4 -D0712 15:11:01.745 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_180___const__64b1 -D0712 15:11:01.745 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_180___const__64b1 -D0712 15:11:01.745 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_180___const__64b2 -D0712 15:11:01.745 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_180___const__64b2 -D0712 15:11:01.745 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_180___const__64b5 -D0712 15:11:01.745 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_180___const__64b5 -D0712 15:11:01.745 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_180___const__64b97 -D0712 15:11:01.745 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_180___const__64b97 -D0712 15:11:01.746 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_181___const__64b1 -D0712 15:11:01.746 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_181___const__64b1 -D0712 15:11:01.746 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_181___const__64b2 -D0712 15:11:01.746 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_181___const__64b2 -D0712 15:11:01.746 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_181___const__64b5 -D0712 15:11:01.746 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_181___const__64b5 -D0712 15:11:01.746 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_181___const__64b98 -D0712 15:11:01.746 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_181___const__64b98 -D0712 15:11:01.747 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_182___const__64b1 -D0712 15:11:01.747 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_182___const__64b1 -D0712 15:11:01.747 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_182___const__64b2 -D0712 15:11:01.747 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_182___const__64b2 -D0712 15:11:01.747 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_182___const__64b5 -D0712 15:11:01.747 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_182___const__64b5 -D0712 15:11:01.747 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_182___const__64b99 -D0712 15:11:01.747 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_182___const__64b99 -D0712 15:11:01.748 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_183___const__64b1 -D0712 15:11:01.748 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_183___const__64b1 -D0712 15:11:01.748 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_183___const__64b100 -D0712 15:11:01.748 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_183___const__64b100 -D0712 15:11:01.748 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_183___const__64b2 -D0712 15:11:01.748 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_183___const__64b2 -D0712 15:11:01.748 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_183___const__64b5 -D0712 15:11:01.748 tapa.core:671] pipelined signal: 64'd5 => bloom_hier_arbiter_atom_183___const__64b5 -D0712 15:11:01.749 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_184___const__64b1 -D0712 15:11:01.749 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_184___const__64b1 -D0712 15:11:01.749 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_184___const__64b2 -D0712 15:11:01.749 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_184___const__64b2 -D0712 15:11:01.749 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_184___const__64b6 -D0712 15:11:01.749 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_184___const__64b6 -D0712 15:11:01.749 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_184___const__64b97 -D0712 15:11:01.749 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_184___const__64b97 -D0712 15:11:01.750 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_185___const__64b1 -D0712 15:11:01.750 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_185___const__64b1 -D0712 15:11:01.750 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_185___const__64b2 -D0712 15:11:01.750 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_185___const__64b2 -D0712 15:11:01.750 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_185___const__64b6 -D0712 15:11:01.750 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_185___const__64b6 -D0712 15:11:01.750 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_185___const__64b98 -D0712 15:11:01.750 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_185___const__64b98 -D0712 15:11:01.751 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_186___const__64b1 -D0712 15:11:01.751 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_186___const__64b1 -D0712 15:11:01.751 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_186___const__64b2 -D0712 15:11:01.751 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_186___const__64b2 -D0712 15:11:01.751 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_186___const__64b6 -D0712 15:11:01.751 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_186___const__64b6 -D0712 15:11:01.752 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_186___const__64b99 -D0712 15:11:01.752 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_186___const__64b99 -D0712 15:11:01.752 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_187___const__64b1 -D0712 15:11:01.752 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_187___const__64b1 -D0712 15:11:01.752 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_187___const__64b100 -D0712 15:11:01.752 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_187___const__64b100 -D0712 15:11:01.753 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_187___const__64b2 -D0712 15:11:01.753 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_187___const__64b2 -D0712 15:11:01.753 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_187___const__64b6 -D0712 15:11:01.753 tapa.core:671] pipelined signal: 64'd6 => bloom_hier_arbiter_atom_187___const__64b6 -D0712 15:11:01.753 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_188___const__64b1 -D0712 15:11:01.753 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_188___const__64b1 -D0712 15:11:01.753 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_188___const__64b2 -D0712 15:11:01.753 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_188___const__64b2 -D0712 15:11:01.754 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_188___const__64b7 -D0712 15:11:01.754 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_188___const__64b7 -D0712 15:11:01.754 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_188___const__64b97 -D0712 15:11:01.754 tapa.core:671] pipelined signal: 64'd97 => bloom_hier_arbiter_atom_188___const__64b97 -D0712 15:11:01.754 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_189___const__64b1 -D0712 15:11:01.754 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_189___const__64b1 -D0712 15:11:01.755 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_189___const__64b2 -D0712 15:11:01.755 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_189___const__64b2 -D0712 15:11:01.755 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_189___const__64b7 -D0712 15:11:01.755 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_189___const__64b7 -D0712 15:11:01.755 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_189___const__64b98 -D0712 15:11:01.755 tapa.core:671] pipelined signal: 64'd98 => bloom_hier_arbiter_atom_189___const__64b98 -D0712 15:11:01.756 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_190___const__64b1 -D0712 15:11:01.756 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_190___const__64b1 -D0712 15:11:01.756 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_190___const__64b2 -D0712 15:11:01.756 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_190___const__64b2 -D0712 15:11:01.756 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_190___const__64b7 -D0712 15:11:01.756 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_190___const__64b7 -D0712 15:11:01.756 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_190___const__64b99 -D0712 15:11:01.756 tapa.core:671] pipelined signal: 64'd99 => bloom_hier_arbiter_atom_190___const__64b99 -D0712 15:11:01.757 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_191___const__64b1 -D0712 15:11:01.757 tapa.core:671] pipelined signal: 64'd1 => bloom_hier_arbiter_atom_191___const__64b1 -D0712 15:11:01.757 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_191___const__64b100 -D0712 15:11:01.757 tapa.core:671] pipelined signal: 64'd100 => bloom_hier_arbiter_atom_191___const__64b100 -D0712 15:11:01.757 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_191___const__64b2 -D0712 15:11:01.757 tapa.core:671] pipelined signal: 64'd2 => bloom_hier_arbiter_atom_191___const__64b2 -D0712 15:11:01.757 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_191___const__64b7 -D0712 15:11:01.757 tapa.core:671] pipelined signal: 64'd7 => bloom_hier_arbiter_atom_191___const__64b7 -D0712 15:11:01.758 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_0___const__64b0 -D0712 15:11:01.758 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_0___const__64b0 -D0712 15:11:01.758 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_0___const__64b0 -D0712 15:11:01.758 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_0___const__64b0 -D0712 15:11:01.758 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_0___const__64b0 -D0712 15:11:01.758 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_0___const__64b0 -D0712 15:11:01.759 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_1___const__64b0 -D0712 15:11:01.759 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_1___const__64b0 -D0712 15:11:01.759 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_1___const__64b0 -D0712 15:11:01.759 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_1___const__64b0 -D0712 15:11:01.759 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_1___const__64b1 -D0712 15:11:01.759 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_1___const__64b1 -D0712 15:11:01.760 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_2___const__64b0 -D0712 15:11:01.760 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_2___const__64b0 -D0712 15:11:01.760 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_2___const__64b0 -D0712 15:11:01.760 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_2___const__64b0 -D0712 15:11:01.760 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_2___const__64b2 -D0712 15:11:01.760 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_2___const__64b2 -D0712 15:11:01.761 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_3___const__64b0 -D0712 15:11:01.761 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_3___const__64b0 -D0712 15:11:01.761 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_3___const__64b0 -D0712 15:11:01.761 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_3___const__64b0 -D0712 15:11:01.761 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_3___const__64b1 -D0712 15:11:01.761 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_3___const__64b1 -D0712 15:11:01.761 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_4___const__64b0 -D0712 15:11:01.761 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_4___const__64b0 -D0712 15:11:01.762 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_4___const__64b1 -D0712 15:11:01.762 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_4___const__64b1 -D0712 15:11:01.762 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_4___const__64b1 -D0712 15:11:01.762 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_4___const__64b1 -D0712 15:11:01.762 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_5___const__64b0 -D0712 15:11:01.762 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_5___const__64b0 -D0712 15:11:01.762 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_5___const__64b1 -D0712 15:11:01.762 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_5___const__64b1 -D0712 15:11:01.763 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_5___const__64b2 -D0712 15:11:01.763 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_5___const__64b2 -D0712 15:11:01.763 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_6___const__64b0 -D0712 15:11:01.763 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_6___const__64b0 -D0712 15:11:01.763 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_6___const__64b0 -D0712 15:11:01.763 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_6___const__64b0 -D0712 15:11:01.763 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_6___const__64b2 -D0712 15:11:01.763 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_6___const__64b2 -D0712 15:11:01.764 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_7___const__64b0 -D0712 15:11:01.764 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_7___const__64b0 -D0712 15:11:01.764 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_7___const__64b1 -D0712 15:11:01.764 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_7___const__64b1 -D0712 15:11:01.764 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_7___const__64b2 -D0712 15:11:01.764 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_7___const__64b2 -D0712 15:11:01.765 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_8___const__64b0 -D0712 15:11:01.765 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_8___const__64b0 -D0712 15:11:01.765 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_8___const__64b2 -D0712 15:11:01.765 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_8___const__64b2 -D0712 15:11:01.765 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_8___const__64b2 -D0712 15:11:01.765 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_8___const__64b2 -D0712 15:11:01.766 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_9___const__64b0 -D0712 15:11:01.766 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_9___const__64b0 -D0712 15:11:01.766 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_9___const__64b0 -D0712 15:11:01.766 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_9___const__64b0 -D0712 15:11:01.766 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_9___const__64b3 -D0712 15:11:01.766 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_9___const__64b3 -D0712 15:11:01.767 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_10___const__64b0 -D0712 15:11:01.767 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_10___const__64b0 -D0712 15:11:01.767 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_10___const__64b1 -D0712 15:11:01.767 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_10___const__64b1 -D0712 15:11:01.767 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_10___const__64b3 -D0712 15:11:01.767 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_10___const__64b3 -D0712 15:11:01.768 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_11___const__64b0 -D0712 15:11:01.768 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_11___const__64b0 -D0712 15:11:01.768 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_11___const__64b2 -D0712 15:11:01.768 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_11___const__64b2 -D0712 15:11:01.768 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_11___const__64b3 -D0712 15:11:01.768 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_11___const__64b3 -D0712 15:11:01.769 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_12___const__64b0 -D0712 15:11:01.769 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_12___const__64b0 -D0712 15:11:01.769 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_12___const__64b0 -D0712 15:11:01.769 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_12___const__64b0 -D0712 15:11:01.769 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_12___const__64b4 -D0712 15:11:01.769 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_12___const__64b4 -D0712 15:11:01.770 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_13___const__64b0 -D0712 15:11:01.770 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_13___const__64b0 -D0712 15:11:01.770 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_13___const__64b1 -D0712 15:11:01.770 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_13___const__64b1 -D0712 15:11:01.770 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_13___const__64b4 -D0712 15:11:01.770 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_13___const__64b4 -D0712 15:11:01.771 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_14___const__64b0 -D0712 15:11:01.771 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_14___const__64b0 -D0712 15:11:01.771 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_14___const__64b2 -D0712 15:11:01.771 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_14___const__64b2 -D0712 15:11:01.771 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_14___const__64b4 -D0712 15:11:01.771 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_14___const__64b4 -D0712 15:11:01.772 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_15___const__64b0 -D0712 15:11:01.772 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_15___const__64b0 -D0712 15:11:01.772 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_15___const__64b0 -D0712 15:11:01.772 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_15___const__64b0 -D0712 15:11:01.772 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_15___const__64b1 -D0712 15:11:01.772 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_15___const__64b1 -D0712 15:11:01.772 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_16___const__64b0 -D0712 15:11:01.772 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_16___const__64b0 -D0712 15:11:01.773 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_16___const__64b1 -D0712 15:11:01.773 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_16___const__64b1 -D0712 15:11:01.773 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_16___const__64b1 -D0712 15:11:01.773 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_16___const__64b1 -D0712 15:11:01.773 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_17___const__64b0 -D0712 15:11:01.773 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_17___const__64b0 -D0712 15:11:01.774 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_17___const__64b1 -D0712 15:11:01.774 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_17___const__64b1 -D0712 15:11:01.774 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_17___const__64b2 -D0712 15:11:01.774 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_17___const__64b2 -D0712 15:11:01.774 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_18___const__64b0 -D0712 15:11:01.774 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_18___const__64b0 -D0712 15:11:01.774 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_18___const__64b1 -D0712 15:11:01.774 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_18___const__64b1 -D0712 15:11:01.775 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_18___const__64b1 -D0712 15:11:01.775 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_18___const__64b1 -D0712 15:11:01.775 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_19___const__64b1 -D0712 15:11:01.775 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_19___const__64b1 -D0712 15:11:01.775 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_19___const__64b1 -D0712 15:11:01.775 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_19___const__64b1 -D0712 15:11:01.776 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_19___const__64b1 -D0712 15:11:01.776 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_19___const__64b1 -D0712 15:11:01.776 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_20___const__64b1 -D0712 15:11:01.776 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_20___const__64b1 -D0712 15:11:01.776 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_20___const__64b1 -D0712 15:11:01.776 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_20___const__64b1 -D0712 15:11:01.776 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_20___const__64b2 -D0712 15:11:01.776 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_20___const__64b2 -D0712 15:11:01.777 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_21___const__64b0 -D0712 15:11:01.777 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_21___const__64b0 -D0712 15:11:01.777 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_21___const__64b1 -D0712 15:11:01.777 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_21___const__64b1 -D0712 15:11:01.777 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_21___const__64b2 -D0712 15:11:01.777 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_21___const__64b2 -D0712 15:11:01.778 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_22___const__64b1 -D0712 15:11:01.778 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_22___const__64b1 -D0712 15:11:01.778 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_22___const__64b1 -D0712 15:11:01.778 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_22___const__64b1 -D0712 15:11:01.778 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_22___const__64b2 -D0712 15:11:01.778 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_22___const__64b2 -D0712 15:11:01.779 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_23___const__64b1 -D0712 15:11:01.779 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_23___const__64b1 -D0712 15:11:01.779 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_23___const__64b2 -D0712 15:11:01.779 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_23___const__64b2 -D0712 15:11:01.779 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_23___const__64b2 -D0712 15:11:01.779 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_23___const__64b2 -D0712 15:11:01.780 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_24___const__64b0 -D0712 15:11:01.780 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_24___const__64b0 -D0712 15:11:01.780 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_24___const__64b1 -D0712 15:11:01.780 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_24___const__64b1 -D0712 15:11:01.780 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_24___const__64b3 -D0712 15:11:01.780 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_24___const__64b3 -D0712 15:11:01.781 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_25___const__64b1 -D0712 15:11:01.781 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_25___const__64b1 -D0712 15:11:01.781 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_25___const__64b1 -D0712 15:11:01.781 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_25___const__64b1 -D0712 15:11:01.781 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_25___const__64b3 -D0712 15:11:01.781 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_25___const__64b3 -D0712 15:11:01.782 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_26___const__64b1 -D0712 15:11:01.782 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_26___const__64b1 -D0712 15:11:01.782 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_26___const__64b2 -D0712 15:11:01.782 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_26___const__64b2 -D0712 15:11:01.782 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_26___const__64b3 -D0712 15:11:01.782 tapa.core:671] pipelined signal: 64'd3 => computeHash_Computer_26___const__64b3 -D0712 15:11:01.783 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_27___const__64b0 -D0712 15:11:01.783 tapa.core:671] pipelined signal: 64'd0 => computeHash_Computer_27___const__64b0 -D0712 15:11:01.783 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_27___const__64b1 -D0712 15:11:01.783 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_27___const__64b1 -D0712 15:11:01.783 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_27___const__64b4 -D0712 15:11:01.783 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_27___const__64b4 -D0712 15:11:01.783 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_28___const__64b1 -D0712 15:11:01.783 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_28___const__64b1 -D0712 15:11:01.784 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_28___const__64b1 -D0712 15:11:01.784 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_28___const__64b1 -D0712 15:11:01.784 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_28___const__64b4 -D0712 15:11:01.784 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_28___const__64b4 -D0712 15:11:01.784 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_29___const__64b1 -D0712 15:11:01.784 tapa.core:671] pipelined signal: 64'd1 => computeHash_Computer_29___const__64b1 -D0712 15:11:01.785 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_29___const__64b2 -D0712 15:11:01.785 tapa.core:671] pipelined signal: 64'd2 => computeHash_Computer_29___const__64b2 -D0712 15:11:01.785 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_29___const__64b4 -D0712 15:11:01.785 tapa.core:671] pipelined signal: 64'd4 => computeHash_Computer_29___const__64b4 -D0712 15:11:01.785 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_0___const__64b0 -D0712 15:11:01.785 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_0___const__64b0 -D0712 15:11:01.785 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_0___const__64b0 -D0712 15:11:01.785 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_0___const__64b0 -D0712 15:11:01.786 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_1___const__64b0 -D0712 15:11:01.786 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_1___const__64b0 -D0712 15:11:01.786 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_1___const__64b1 -D0712 15:11:01.786 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_1___const__64b1 -D0712 15:11:01.787 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_2___const__64b0 -D0712 15:11:01.787 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_2___const__64b0 -D0712 15:11:01.787 tapa.core:671] pipelined signal: 64'd2 => computeHash_Feeder_2___const__64b2 -D0712 15:11:01.787 tapa.core:671] pipelined signal: 64'd2 => computeHash_Feeder_2___const__64b2 -D0712 15:11:01.788 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_3___const__64b0 -D0712 15:11:01.788 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_3___const__64b0 -D0712 15:11:01.788 tapa.core:671] pipelined signal: 64'd3 => computeHash_Feeder_3___const__64b3 -D0712 15:11:01.788 tapa.core:671] pipelined signal: 64'd3 => computeHash_Feeder_3___const__64b3 -D0712 15:11:01.789 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_4___const__64b0 -D0712 15:11:01.789 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_4___const__64b0 -D0712 15:11:01.789 tapa.core:671] pipelined signal: 64'd4 => computeHash_Feeder_4___const__64b4 -D0712 15:11:01.789 tapa.core:671] pipelined signal: 64'd4 => computeHash_Feeder_4___const__64b4 -D0712 15:11:01.790 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_5___const__64b0 -D0712 15:11:01.790 tapa.core:671] pipelined signal: 64'd0 => computeHash_Feeder_5___const__64b0 -D0712 15:11:01.790 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_5___const__64b1 -D0712 15:11:01.790 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_5___const__64b1 -D0712 15:11:01.791 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_6___const__64b1 -D0712 15:11:01.791 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_6___const__64b1 -D0712 15:11:01.791 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_6___const__64b1 -D0712 15:11:01.791 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_6___const__64b1 -D0712 15:11:01.792 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_7___const__64b1 -D0712 15:11:01.792 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_7___const__64b1 -D0712 15:11:01.792 tapa.core:671] pipelined signal: 64'd2 => computeHash_Feeder_7___const__64b2 -D0712 15:11:01.792 tapa.core:671] pipelined signal: 64'd2 => computeHash_Feeder_7___const__64b2 -D0712 15:11:01.793 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_8___const__64b1 -D0712 15:11:01.793 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_8___const__64b1 -D0712 15:11:01.793 tapa.core:671] pipelined signal: 64'd3 => computeHash_Feeder_8___const__64b3 -D0712 15:11:01.793 tapa.core:671] pipelined signal: 64'd3 => computeHash_Feeder_8___const__64b3 -D0712 15:11:01.794 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_9___const__64b1 -D0712 15:11:01.794 tapa.core:671] pipelined signal: 64'd1 => computeHash_Feeder_9___const__64b1 -D0712 15:11:01.794 tapa.core:671] pipelined signal: 64'd4 => computeHash_Feeder_9___const__64b4 -D0712 15:11:01.794 tapa.core:671] pipelined signal: 64'd4 => computeHash_Feeder_9___const__64b4 -D0712 15:11:01.795 tapa.core:671] pipelined signal: input_bv => loadBV_0___input_bv -D0712 15:11:01.795 tapa.core:671] pipelined signal: input_bv => loadBV_0___input_bv -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_din` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_din` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_full_n` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_full_n` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_write` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_write` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_dout` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_dout` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_read_data_peek_dout` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_read_data_peek_dout` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_empty_n` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_empty_n` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_read_data_peek_empty_n` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_read_data_peek_empty_n` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_read` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_read` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_din` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_din` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_full_n` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_full_n` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_write` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_write` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_din` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_din` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_full_n` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_full_n` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_write` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_write` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_dout` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_dout` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_write_resp_peek_dout` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_write_resp_peek_dout` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_empty_n` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_empty_n` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_write_resp_peek_empty_n` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.795 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_write_resp_peek_empty_n` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.796 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_read` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.796 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_read` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_din` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_din` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_full_n` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_full_n` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_write` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_addr_write` is connected to async_mmap port `input_bv.read_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_dout` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_dout` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_read_data_peek_dout` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_read_data_peek_dout` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_empty_n` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_empty_n` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_read_data_peek_empty_n` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_read_data_peek_empty_n` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_read` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_read_data_s_read` is connected to async_mmap port `input_bv.read_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_din` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_din` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_full_n` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_full_n` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_write` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_addr_write` is connected to async_mmap port `input_bv.write_addr` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_din` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_din` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_full_n` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_full_n` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_write` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_data_write` is connected to async_mmap port `input_bv.write_data` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_dout` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_dout` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_write_resp_peek_dout` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_write_resp_peek_dout` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_empty_n` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_empty_n` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_write_resp_peek_empty_n` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:81] `loadBV_0.input_bv_write_resp_peek_empty_n` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_read` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.797 tapa.verilog.xilinx.async_mmap:71] `loadBV_0.input_bv_write_resp_s_read` is connected to async_mmap port `input_bv.write_resp` -D0712 15:11:01.798 tapa.core:671] pipelined signal: key_in => loadKey_0___key_in -D0712 15:11:01.798 tapa.core:671] pipelined signal: key_in => loadKey_0___key_in -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_din` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_din` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_full_n` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_full_n` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_write` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_write` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_dout` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_dout` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_read_data_peek_dout` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_read_data_peek_dout` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_empty_n` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_empty_n` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_read_data_peek_empty_n` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_read_data_peek_empty_n` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_read` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_read` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_din` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_din` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_full_n` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_full_n` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_write` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_write` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_din` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_din` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_full_n` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_full_n` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_write` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_write` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_dout` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_dout` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_write_resp_peek_dout` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_write_resp_peek_dout` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_empty_n` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.798 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_empty_n` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.799 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_write_resp_peek_empty_n` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.799 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_write_resp_peek_empty_n` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.799 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_read` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.799 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_read` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.799 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_din` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.799 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_din` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_full_n` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_full_n` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_write` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_addr_write` is connected to async_mmap port `key_in.read_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_dout` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_dout` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_read_data_peek_dout` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_read_data_peek_dout` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_empty_n` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_empty_n` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_read_data_peek_empty_n` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_read_data_peek_empty_n` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_read` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_read_data_s_read` is connected to async_mmap port `key_in.read_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_din` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_din` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_full_n` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_full_n` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_write` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_addr_write` is connected to async_mmap port `key_in.write_addr` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_din` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_din` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_full_n` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_full_n` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_write` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_data_write` is connected to async_mmap port `key_in.write_data` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_dout` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_dout` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_write_resp_peek_dout` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_write_resp_peek_dout` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_empty_n` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_empty_n` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_write_resp_peek_empty_n` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:81] `loadKey_0.key_in_write_resp_peek_empty_n` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_read` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.800 tapa.verilog.xilinx.async_mmap:71] `loadKey_0.key_in_write_resp_s_read` is connected to async_mmap port `key_in.write_resp` -D0712 15:11:01.801 tapa.core:671] pipelined signal: 64'd0 => packOutput_0___const__64b0 -D0712 15:11:01.801 tapa.core:671] pipelined signal: 64'd0 => packOutput_0___const__64b0 -D0712 15:11:01.801 tapa.core:671] pipelined signal: 64'd0 => packOutput_0___const__64b0 -D0712 15:11:01.801 tapa.core:671] pipelined signal: 64'd0 => packOutput_0___const__64b0 -D0712 15:11:01.802 tapa.core:671] pipelined signal: 64'd0 => packOutput_1___const__64b0 -D0712 15:11:01.802 tapa.core:671] pipelined signal: 64'd0 => packOutput_1___const__64b0 -D0712 15:11:01.802 tapa.core:671] pipelined signal: 64'd1 => packOutput_1___const__64b1 -D0712 15:11:01.802 tapa.core:671] pipelined signal: 64'd1 => packOutput_1___const__64b1 -D0712 15:11:01.803 tapa.core:671] pipelined signal: 64'd0 => packOutput_2___const__64b0 -D0712 15:11:01.803 tapa.core:671] pipelined signal: 64'd0 => packOutput_2___const__64b0 -D0712 15:11:01.803 tapa.core:671] pipelined signal: 64'd2 => packOutput_2___const__64b2 -D0712 15:11:01.803 tapa.core:671] pipelined signal: 64'd2 => packOutput_2___const__64b2 -D0712 15:11:01.804 tapa.core:671] pipelined signal: 64'd0 => packOutput_3___const__64b0 -D0712 15:11:01.804 tapa.core:671] pipelined signal: 64'd0 => packOutput_3___const__64b0 -D0712 15:11:01.804 tapa.core:671] pipelined signal: 64'd3 => packOutput_3___const__64b3 -D0712 15:11:01.804 tapa.core:671] pipelined signal: 64'd3 => packOutput_3___const__64b3 -D0712 15:11:01.805 tapa.core:671] pipelined signal: 64'd0 => packOutput_4___const__64b0 -D0712 15:11:01.805 tapa.core:671] pipelined signal: 64'd0 => packOutput_4___const__64b0 -D0712 15:11:01.805 tapa.core:671] pipelined signal: 64'd4 => packOutput_4___const__64b4 -D0712 15:11:01.805 tapa.core:671] pipelined signal: 64'd4 => packOutput_4___const__64b4 -D0712 15:11:01.805 tapa.core:671] pipelined signal: 64'd0 => packOutput_5___const__64b0 -D0712 15:11:01.805 tapa.core:671] pipelined signal: 64'd0 => packOutput_5___const__64b0 -D0712 15:11:01.806 tapa.core:671] pipelined signal: 64'd1 => packOutput_5___const__64b1 -D0712 15:11:01.806 tapa.core:671] pipelined signal: 64'd1 => packOutput_5___const__64b1 -D0712 15:11:01.806 tapa.core:671] pipelined signal: 64'd1 => packOutput_6___const__64b1 -D0712 15:11:01.806 tapa.core:671] pipelined signal: 64'd1 => packOutput_6___const__64b1 -D0712 15:11:01.806 tapa.core:671] pipelined signal: 64'd1 => packOutput_6___const__64b1 -D0712 15:11:01.806 tapa.core:671] pipelined signal: 64'd1 => packOutput_6___const__64b1 -D0712 15:11:01.807 tapa.core:671] pipelined signal: 64'd1 => packOutput_7___const__64b1 -D0712 15:11:01.807 tapa.core:671] pipelined signal: 64'd1 => packOutput_7___const__64b1 -D0712 15:11:01.807 tapa.core:671] pipelined signal: 64'd2 => packOutput_7___const__64b2 -D0712 15:11:01.807 tapa.core:671] pipelined signal: 64'd2 => packOutput_7___const__64b2 -D0712 15:11:01.808 tapa.core:671] pipelined signal: 64'd1 => packOutput_8___const__64b1 -D0712 15:11:01.808 tapa.core:671] pipelined signal: 64'd1 => packOutput_8___const__64b1 -D0712 15:11:01.808 tapa.core:671] pipelined signal: 64'd3 => packOutput_8___const__64b3 -D0712 15:11:01.808 tapa.core:671] pipelined signal: 64'd3 => packOutput_8___const__64b3 -D0712 15:11:01.809 tapa.core:671] pipelined signal: 64'd1 => packOutput_9___const__64b1 -D0712 15:11:01.809 tapa.core:671] pipelined signal: 64'd1 => packOutput_9___const__64b1 -D0712 15:11:01.809 tapa.core:671] pipelined signal: 64'd4 => packOutput_9___const__64b4 -D0712 15:11:01.809 tapa.core:671] pipelined signal: 64'd4 => packOutput_9___const__64b4 -D0712 15:11:01.810 tapa.core:671] pipelined signal: 64'd0 => queryResult_per_hash_0___const__64b0 -D0712 15:11:01.810 tapa.core:671] pipelined signal: 64'd0 => queryResult_per_hash_0___const__64b0 -D0712 15:11:01.819 tapa.core:671] pipelined signal: 64'd1 => queryResult_per_hash_1___const__64b1 -D0712 15:11:01.819 tapa.core:671] pipelined signal: 64'd1 => queryResult_per_hash_1___const__64b1 -D0712 15:11:01.828 tapa.core:671] pipelined signal: 64'd2 => queryResult_per_hash_2___const__64b2 -D0712 15:11:01.828 tapa.core:671] pipelined signal: 64'd2 => queryResult_per_hash_2___const__64b2 -D0712 15:11:01.838 tapa.core:671] pipelined signal: 64'd0 => shuffle_TtoS_per_hash_0___const__64b0 -D0712 15:11:01.838 tapa.core:671] pipelined signal: 64'd0 => shuffle_TtoS_per_hash_0___const__64b0 -D0712 15:11:01.838 tapa.core:671] pipelined signal: 64'd0 => shuffle_TtoS_per_hash_0___const__64b0 -D0712 15:11:01.838 tapa.core:671] pipelined signal: 64'd0 => shuffle_TtoS_per_hash_0___const__64b0 -D0712 15:11:01.851 tapa.core:671] pipelined signal: 64'd0 => shuffle_TtoS_per_hash_1___const__64b0 -D0712 15:11:01.851 tapa.core:671] pipelined signal: 64'd0 => shuffle_TtoS_per_hash_1___const__64b0 -D0712 15:11:01.851 tapa.core:671] pipelined signal: 64'd1 => shuffle_TtoS_per_hash_1___const__64b1 -D0712 15:11:01.851 tapa.core:671] pipelined signal: 64'd1 => shuffle_TtoS_per_hash_1___const__64b1 -D0712 15:11:01.864 tapa.core:671] pipelined signal: 64'd0 => shuffle_TtoS_per_hash_2___const__64b0 -D0712 15:11:01.864 tapa.core:671] pipelined signal: 64'd0 => shuffle_TtoS_per_hash_2___const__64b0 -D0712 15:11:01.864 tapa.core:671] pipelined signal: 64'd2 => shuffle_TtoS_per_hash_2___const__64b2 -D0712 15:11:01.864 tapa.core:671] pipelined signal: 64'd2 => shuffle_TtoS_per_hash_2___const__64b2 -D0712 15:11:01.877 tapa.core:671] pipelined signal: 64'd0 => shuffle_TtoS_per_hash_3___const__64b0 -D0712 15:11:01.877 tapa.core:671] pipelined signal: 64'd0 => shuffle_TtoS_per_hash_3___const__64b0 -D0712 15:11:01.877 tapa.core:671] pipelined signal: 64'd1 => shuffle_TtoS_per_hash_3___const__64b1 -D0712 15:11:01.877 tapa.core:671] pipelined signal: 64'd1 => shuffle_TtoS_per_hash_3___const__64b1 -D0712 15:11:01.889 tapa.core:671] pipelined signal: 64'd1 => shuffle_TtoS_per_hash_4___const__64b1 -D0712 15:11:01.889 tapa.core:671] pipelined signal: 64'd1 => shuffle_TtoS_per_hash_4___const__64b1 -D0712 15:11:01.890 tapa.core:671] pipelined signal: 64'd1 => shuffle_TtoS_per_hash_4___const__64b1 -D0712 15:11:01.890 tapa.core:671] pipelined signal: 64'd1 => shuffle_TtoS_per_hash_4___const__64b1 -D0712 15:11:01.902 tapa.core:671] pipelined signal: 64'd1 => shuffle_TtoS_per_hash_5___const__64b1 -D0712 15:11:01.902 tapa.core:671] pipelined signal: 64'd1 => shuffle_TtoS_per_hash_5___const__64b1 -D0712 15:11:01.902 tapa.core:671] pipelined signal: 64'd2 => shuffle_TtoS_per_hash_5___const__64b2 -D0712 15:11:01.902 tapa.core:671] pipelined signal: 64'd2 => shuffle_TtoS_per_hash_5___const__64b2 -D0712 15:11:01.915 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_0___const__64b0 -D0712 15:11:01.915 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_0___const__64b0 -D0712 15:11:01.915 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_0___const__64b0 -D0712 15:11:01.915 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_0___const__64b0 -D0712 15:11:01.915 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_0___const__64b0 -D0712 15:11:01.915 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_0___const__64b0 -D0712 15:11:01.917 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_1___const__64b0 -D0712 15:11:01.917 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_1___const__64b0 -D0712 15:11:01.917 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_1___const__64b0 -D0712 15:11:01.917 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_1___const__64b0 -D0712 15:11:01.917 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_1___const__64b1 -D0712 15:11:01.917 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_1___const__64b1 -D0712 15:11:01.919 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_2___const__64b0 -D0712 15:11:01.919 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_2___const__64b0 -D0712 15:11:01.919 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_2___const__64b0 -D0712 15:11:01.919 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_2___const__64b0 -D0712 15:11:01.919 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_2___const__64b2 -D0712 15:11:01.919 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_2___const__64b2 -D0712 15:11:01.921 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_3___const__64b0 -D0712 15:11:01.921 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_3___const__64b0 -D0712 15:11:01.921 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_3___const__64b0 -D0712 15:11:01.921 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_3___const__64b0 -D0712 15:11:01.922 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_3___const__64b3 -D0712 15:11:01.922 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_3___const__64b3 -D0712 15:11:01.923 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_4___const__64b0 -D0712 15:11:01.923 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_4___const__64b0 -D0712 15:11:01.923 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_4___const__64b0 -D0712 15:11:01.923 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_4___const__64b0 -D0712 15:11:01.924 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_4___const__64b4 -D0712 15:11:01.924 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_4___const__64b4 -D0712 15:11:01.925 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_5___const__64b0 -D0712 15:11:01.925 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_5___const__64b0 -D0712 15:11:01.926 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_5___const__64b0 -D0712 15:11:01.926 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_5___const__64b0 -D0712 15:11:01.926 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_5___const__64b1 -D0712 15:11:01.926 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_5___const__64b1 -D0712 15:11:01.928 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_6___const__64b0 -D0712 15:11:01.928 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_6___const__64b0 -D0712 15:11:01.928 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_6___const__64b1 -D0712 15:11:01.928 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_6___const__64b1 -D0712 15:11:01.928 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_6___const__64b1 -D0712 15:11:01.928 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_6___const__64b1 -D0712 15:11:01.930 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_7___const__64b0 -D0712 15:11:01.930 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_7___const__64b0 -D0712 15:11:01.930 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_7___const__64b1 -D0712 15:11:01.930 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_7___const__64b1 -D0712 15:11:01.930 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_7___const__64b2 -D0712 15:11:01.930 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_7___const__64b2 -D0712 15:11:01.932 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_8___const__64b0 -D0712 15:11:01.932 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_8___const__64b0 -D0712 15:11:01.932 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_8___const__64b1 -D0712 15:11:01.932 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_8___const__64b1 -D0712 15:11:01.932 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_8___const__64b3 -D0712 15:11:01.932 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_8___const__64b3 -D0712 15:11:01.934 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_9___const__64b0 -D0712 15:11:01.934 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_9___const__64b0 -D0712 15:11:01.934 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_9___const__64b1 -D0712 15:11:01.934 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_9___const__64b1 -D0712 15:11:01.934 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_9___const__64b4 -D0712 15:11:01.934 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_9___const__64b4 -D0712 15:11:01.936 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_10___const__64b0 -D0712 15:11:01.936 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_10___const__64b0 -D0712 15:11:01.936 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_10___const__64b0 -D0712 15:11:01.936 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_10___const__64b0 -D0712 15:11:01.936 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_10___const__64b2 -D0712 15:11:01.936 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_10___const__64b2 -D0712 15:11:01.938 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_11___const__64b0 -D0712 15:11:01.938 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_11___const__64b0 -D0712 15:11:01.938 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_11___const__64b1 -D0712 15:11:01.938 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_11___const__64b1 -D0712 15:11:01.939 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_11___const__64b2 -D0712 15:11:01.939 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_11___const__64b2 -D0712 15:11:01.940 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_12___const__64b0 -D0712 15:11:01.940 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_12___const__64b0 -D0712 15:11:01.940 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_12___const__64b2 -D0712 15:11:01.940 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_12___const__64b2 -D0712 15:11:01.941 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_12___const__64b2 -D0712 15:11:01.941 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_12___const__64b2 -D0712 15:11:01.942 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_13___const__64b0 -D0712 15:11:01.942 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_13___const__64b0 -D0712 15:11:01.943 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_13___const__64b2 -D0712 15:11:01.943 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_13___const__64b2 -D0712 15:11:01.943 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_13___const__64b3 -D0712 15:11:01.943 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_13___const__64b3 -D0712 15:11:01.945 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_14___const__64b0 -D0712 15:11:01.945 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_14___const__64b0 -D0712 15:11:01.945 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_14___const__64b2 -D0712 15:11:01.945 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_14___const__64b2 -D0712 15:11:01.945 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_14___const__64b4 -D0712 15:11:01.945 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_14___const__64b4 -D0712 15:11:01.947 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_15___const__64b0 -D0712 15:11:01.947 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_15___const__64b0 -D0712 15:11:01.947 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_15___const__64b0 -D0712 15:11:01.947 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_15___const__64b0 -D0712 15:11:01.947 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_15___const__64b1 -D0712 15:11:01.947 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_15___const__64b1 -D0712 15:11:01.949 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_16___const__64b0 -D0712 15:11:01.949 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_16___const__64b0 -D0712 15:11:01.949 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_16___const__64b1 -D0712 15:11:01.949 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_16___const__64b1 -D0712 15:11:01.949 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_16___const__64b1 -D0712 15:11:01.949 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_16___const__64b1 -D0712 15:11:01.951 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_17___const__64b0 -D0712 15:11:01.951 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_17___const__64b0 -D0712 15:11:01.951 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_17___const__64b1 -D0712 15:11:01.951 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_17___const__64b1 -D0712 15:11:01.951 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_17___const__64b2 -D0712 15:11:01.951 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_17___const__64b2 -D0712 15:11:01.953 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_18___const__64b0 -D0712 15:11:01.953 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_18___const__64b0 -D0712 15:11:01.953 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_18___const__64b1 -D0712 15:11:01.953 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_18___const__64b1 -D0712 15:11:01.953 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_18___const__64b3 -D0712 15:11:01.953 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_18___const__64b3 -D0712 15:11:01.955 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_19___const__64b0 -D0712 15:11:01.955 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_19___const__64b0 -D0712 15:11:01.955 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_19___const__64b1 -D0712 15:11:01.955 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_19___const__64b1 -D0712 15:11:01.955 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_19___const__64b4 -D0712 15:11:01.955 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_19___const__64b4 -D0712 15:11:01.957 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_20___const__64b0 -D0712 15:11:01.957 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_20___const__64b0 -D0712 15:11:01.957 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_20___const__64b1 -D0712 15:11:01.957 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_20___const__64b1 -D0712 15:11:01.957 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_20___const__64b1 -D0712 15:11:01.957 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_20___const__64b1 -D0712 15:11:01.959 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_21___const__64b1 -D0712 15:11:01.959 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_21___const__64b1 -D0712 15:11:01.959 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_21___const__64b1 -D0712 15:11:01.959 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_21___const__64b1 -D0712 15:11:01.959 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_21___const__64b1 -D0712 15:11:01.959 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_21___const__64b1 -D0712 15:11:01.961 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_22___const__64b1 -D0712 15:11:01.961 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_22___const__64b1 -D0712 15:11:01.961 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_22___const__64b1 -D0712 15:11:01.961 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_22___const__64b1 -D0712 15:11:01.961 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_22___const__64b2 -D0712 15:11:01.961 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_22___const__64b2 -D0712 15:11:01.963 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_23___const__64b1 -D0712 15:11:01.963 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_23___const__64b1 -D0712 15:11:01.963 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_23___const__64b1 -D0712 15:11:01.963 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_23___const__64b1 -D0712 15:11:01.964 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_23___const__64b3 -D0712 15:11:01.964 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_23___const__64b3 -D0712 15:11:01.965 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_24___const__64b1 -D0712 15:11:01.965 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_24___const__64b1 -D0712 15:11:01.965 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_24___const__64b1 -D0712 15:11:01.965 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_24___const__64b1 -D0712 15:11:01.966 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_24___const__64b4 -D0712 15:11:01.966 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_24___const__64b4 -D0712 15:11:01.967 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_25___const__64b0 -D0712 15:11:01.967 tapa.core:671] pipelined signal: 64'd0 => shuffle_reordering_per_hash_25___const__64b0 -D0712 15:11:01.968 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_25___const__64b1 -D0712 15:11:01.968 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_25___const__64b1 -D0712 15:11:01.968 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_25___const__64b2 -D0712 15:11:01.968 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_25___const__64b2 -D0712 15:11:01.969 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_26___const__64b1 -D0712 15:11:01.969 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_26___const__64b1 -D0712 15:11:01.970 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_26___const__64b1 -D0712 15:11:01.970 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_26___const__64b1 -D0712 15:11:01.970 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_26___const__64b2 -D0712 15:11:01.970 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_26___const__64b2 -D0712 15:11:01.972 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_27___const__64b1 -D0712 15:11:01.972 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_27___const__64b1 -D0712 15:11:01.972 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_27___const__64b2 -D0712 15:11:01.972 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_27___const__64b2 -D0712 15:11:01.972 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_27___const__64b2 -D0712 15:11:01.972 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_27___const__64b2 -D0712 15:11:01.974 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_28___const__64b1 -D0712 15:11:01.974 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_28___const__64b1 -D0712 15:11:01.974 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_28___const__64b2 -D0712 15:11:01.974 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_28___const__64b2 -D0712 15:11:01.974 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_28___const__64b3 -D0712 15:11:01.974 tapa.core:671] pipelined signal: 64'd3 => shuffle_reordering_per_hash_28___const__64b3 -D0712 15:11:01.976 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_29___const__64b1 -D0712 15:11:01.976 tapa.core:671] pipelined signal: 64'd1 => shuffle_reordering_per_hash_29___const__64b1 -D0712 15:11:01.976 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_29___const__64b2 -D0712 15:11:01.976 tapa.core:671] pipelined signal: 64'd2 => shuffle_reordering_per_hash_29___const__64b2 -D0712 15:11:01.976 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_29___const__64b4 -D0712 15:11:01.976 tapa.core:671] pipelined signal: 64'd4 => shuffle_reordering_per_hash_29___const__64b4 -D0712 15:11:01.978 tapa.core:671] pipelined signal: out_bits => writeOutput_synchronous_0___out_bits -D0712 15:11:01.978 tapa.core:671] pipelined signal: out_bits => writeOutput_synchronous_0___out_bits -D0712 15:11:01.981 tapa.core:852] Set the address width of async_mmap to 64 -D0712 15:11:01.981 tapa.core:852] Set the address width of async_mmap to 64 -I0712 15:11:02.722 tapa.core:465] generating report -I0712 15:11:02.722 tapa.core:465] generating report -I0712 15:11:02.731 tapa.core:473] writing generated auxiliary RTL files -I0712 15:11:02.731 tapa.core:473] writing generated auxiliary RTL files -I0712 15:11:02.731 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 15:11:02.731 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 15:11:02.731 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 15:11:02.731 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 15:11:02.731 tapa.core:481] packaging RTL code -I0712 15:11:02.731 tapa.core:481] packaging RTL code -D0712 15:11:02.731 tapa.verilog.xilinx:70] RTL ports of workload: -D0712 15:11:02.731 tapa.verilog.xilinx:70] RTL ports of workload: -D0712 15:11:02.731 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: input_bv, ctype: BV_LOAD_DTYPE*, width: 128, chan_count: None, chan_size: None -D0712 15:11:02.731 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: input_bv, ctype: BV_LOAD_DTYPE*, width: 128, chan_count: None, chan_size: None -D0712 15:11:02.731 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: key_in, ctype: LOAD_DTYPE*, width: 512, chan_count: None, chan_size: None -D0712 15:11:02.731 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: key_in, ctype: LOAD_DTYPE*, width: 512, chan_count: None, chan_size: None -D0712 15:11:02.731 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_bits, ctype: STORE_DTYPE*, width: 512, chan_count: None, chan_size: None -D0712 15:11:02.731 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_bits, ctype: STORE_DTYPE*, width: 512, chan_count: None, chan_size: None -D0712 15:11:02.731 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: UNUSED_DUMMY, ctype: int, width: 32, chan_count: None, chan_size: None -D0712 15:11:02.731 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: UNUSED_DUMMY, ctype: int, width: 32, chan_count: None, chan_size: None -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_arb_forwarder_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_arb_forwarder_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: queryResult_per_hash_bv_buf_URAMS_V_RAM_T2P_URAM_1R1W.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: queryResult_per_hash_bv_buf_URAMS_V_RAM_T2P_URAM_1R1W.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_3.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_3.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Computer_mul_32s_30ns_32_2_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Computer_mul_32s_30ns_32_2_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: queryResult_per_hash_queryResult_per_hash_Pipeline_PROCESS_QUERIES.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: queryResult_per_hash_queryResult_per_hash_Pipeline_PROCESS_QUERIES.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash_mux_83_1_1_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash_mux_83_1_1_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Feeder_computeHash_Feeder_Pipeline_VITIS_LOOP_222_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Feeder_computeHash_Feeder_Pipeline_VITIS_LOOP_222_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Feeder_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Feeder_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_aggregate_SPLIT_bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_aggregate_SPLIT_bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: axi_crossbar_wr.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: axi_crossbar_wr.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: axi_crossbar.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: axi_crossbar.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: packOutput_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: packOutput_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: loadBV.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: loadBV.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Computer.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Computer.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_arb_forwarder_bloom_arb_forwarder_Pipeline_INIT_LOOP.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_arb_forwarder_bloom_arb_forwarder_Pipeline_INIT_LOOP.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: queryResult_per_hash_bv_buf_BRAMS_V_RAM_T2P_BRAM_1R1W.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: queryResult_per_hash_bv_buf_BRAMS_V_RAM_T2P_BRAM_1R1W.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: axi_register_rd.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: axi_register_rd.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: writeOutput_synchronous.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: writeOutput_synchronous.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: workload_fsm.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: workload_fsm.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_arbiter_ratemonitor_bloom_arbiter_ratemonitor_Pipeline_INIT_LOOP_2.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_arbiter_ratemonitor_bloom_arbiter_ratemonitor_Pipeline_INIT_LOOP_2.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_4.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_4.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_TtoS_per_hash.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_TtoS_per_hash.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_arbiter_ratemonitor.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_arbiter_ratemonitor.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: loadKey.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: loadKey.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: writeOutput_synchronous_outmmap_m_axi.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: writeOutput_synchronous_outmmap_m_axi.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Computer_mul_32s_31s_32_2_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Computer_mul_32s_31s_32_2_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: fifo_srl.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: fifo_srl.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: axi_crossbar_rd.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: axi_crossbar_rd.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_hier_arbiter_atom_bloom_hier_arbiter_atom_Pipeline_MAIN_LOOP.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_hier_arbiter_atom_bloom_hier_arbiter_atom_Pipeline_MAIN_LOOP.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: queryResult_per_hash_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: queryResult_per_hash_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash_shuffle_reordering_per_hash_Pipeline_PEEK_EMULATOR_INIT_VITIS_LOOP_368_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash_shuffle_reordering_per_hash_Pipeline_PEEK_EMULATOR_INIT_VITIS_LOOP_368_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: queryResult_per_hash.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: queryResult_per_hash.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Computer_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Computer_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: relay_station.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: relay_station.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Computer_mul_32s_32s_32_2_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: computeHash_Computer_mul_32s_32s_32_2_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: detect_burst.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: detect_burst.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_hier_arbiter_atom.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_hier_arbiter_atom.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: fifo.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: fifo.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash_mux_83_24_1_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash_mux_83_24_1_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: packOutput_packOutput_Pipeline_VITIS_LOOP_317_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: packOutput_packOutput_Pipeline_VITIS_LOOP_317_1.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: async_mmap.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: async_mmap.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: axi_crossbar_addr.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: axi_crossbar_addr.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_aggregate_SPLIT.v -D0712 15:11:02.732 haoda.backend.xilinx:163] packing: bloom_aggregate_SPLIT.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: loadBV_loadBV_Pipeline_VITIS_LOOP_181_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: loadBV_loadBV_Pipeline_VITIS_LOOP_181_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: loadBV_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: loadBV_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_arb_forwarder.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_arb_forwarder.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: computeHash_Computer_computeHash_Computer_Pipeline_MAIN_LOOP.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: computeHash_Computer_computeHash_Computer_Pipeline_MAIN_LOOP.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash_shuffle_reordering_per_hash_Pipeline_MAIN_LOOP.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: shuffle_reordering_per_hash_shuffle_reordering_per_hash_Pipeline_MAIN_LOOP.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_arbiter_ratemonitor_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_arbiter_ratemonitor_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_arbiter_ratemonitor_bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_arbiter_ratemonitor_bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: fifo_fwd.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: fifo_fwd.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_arbiter_ratemonitor_mux_83_1_1_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_arbiter_ratemonitor_mux_83_1_1_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: shuffle_TtoS_per_hash_mux_53_1_1_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: shuffle_TtoS_per_hash_mux_53_1_1_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: computeHash_Feeder.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: computeHash_Feeder.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: writeOutput_synchronous_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: writeOutput_synchronous_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: queryResult_per_hash_queryResult_per_hash_Pipeline_LOAD_BV_VALUES.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: queryResult_per_hash_queryResult_per_hash_Pipeline_LOAD_BV_VALUES.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: computeHash_Computer_mul_25s_25ns_25_2_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: computeHash_Computer_mul_25s_25ns_25_2_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: axi_pipeline.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: axi_pipeline.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: workload.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: workload.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: fifo_bram.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: fifo_bram.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: writeOutput_synchronous_writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: writeOutput_synchronous_writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_aggregate_SPLIT_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_aggregate_SPLIT_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: generate_last.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: generate_last.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: workload_control_s_axi.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: workload_control_s_axi.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: arbiter.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: arbiter.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: priority_encoder.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: priority_encoder.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: shuffle_TtoS_per_hash_shuffle_TtoS_per_hash_Pipeline_VITIS_LOOP_473_2.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: shuffle_TtoS_per_hash_shuffle_TtoS_per_hash_Pipeline_VITIS_LOOP_473_2.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: packOutput.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: packOutput.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: axi_register_wr.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: axi_register_wr.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_arb_forwarder_bloom_arb_forwarder_Pipeline_MAIN_LOOP.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: bloom_arb_forwarder_bloom_arb_forwarder_Pipeline_MAIN_LOOP.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: loadKey_loadKey_Pipeline_VITIS_LOOP_194_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: loadKey_loadKey_Pipeline_VITIS_LOOP_194_1.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: loadKey_flow_control_loop_pipe_sequential_init.v -D0712 15:11:02.733 haoda.backend.xilinx:163] packing: loadKey_flow_control_loop_pipe_sequential_init.v -I0712 15:11:21.474 tapa.core:489] packaging HLS report -I0712 15:11:21.474 tapa.core:489] packaging HLS report -D0712 15:11:21.475 tapa.core:494] packing report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES_csynth.xml -D0712 15:11:21.475 tapa.core:494] packing report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES_csynth.xml -D0712 15:11:21.476 tapa.core:494] packing report/shuffle_reordering_per_hash_Pipeline_MAIN_LOOP_csynth.xml -D0712 15:11:21.476 tapa.core:494] packing report/shuffle_reordering_per_hash_Pipeline_MAIN_LOOP_csynth.xml -D0712 15:11:21.476 tapa.core:494] packing report/bloom_hier_arbiter_atom_Pipeline_MAIN_LOOP_csynth.xml -D0712 15:11:21.476 tapa.core:494] packing report/bloom_hier_arbiter_atom_Pipeline_MAIN_LOOP_csynth.xml -D0712 15:11:21.476 tapa.core:494] packing report/bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP_csynth.xml -D0712 15:11:21.476 tapa.core:494] packing report/bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP_csynth.xml -D0712 15:11:21.476 tapa.core:494] packing report/queryResult_per_hash_csynth.xml -D0712 15:11:21.476 tapa.core:494] packing report/queryResult_per_hash_csynth.xml -D0712 15:11:21.477 tapa.core:494] packing report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1_csynth.xml -D0712 15:11:21.477 tapa.core:494] packing report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1_csynth.xml -D0712 15:11:21.477 tapa.core:494] packing report/bloom_arbiter_ratemonitor_Pipeline_INIT_LOOP_2_csynth.xml -D0712 15:11:21.477 tapa.core:494] packing report/bloom_arbiter_ratemonitor_Pipeline_INIT_LOOP_2_csynth.xml -D0712 15:11:21.477 tapa.core:494] packing report/loadKey_Pipeline_VITIS_LOOP_194_1_csynth.xml -D0712 15:11:21.477 tapa.core:494] packing report/loadKey_Pipeline_VITIS_LOOP_194_1_csynth.xml -D0712 15:11:21.477 tapa.core:494] packing report/shuffle_reordering_per_hash_Pipeline_PEEK_EMULATOR_INIT_VITIS_LOOP_368_1_csynth.xml -D0712 15:11:21.477 tapa.core:494] packing report/shuffle_reordering_per_hash_Pipeline_PEEK_EMULATOR_INIT_VITIS_LOOP_368_1_csynth.xml -D0712 15:11:21.478 tapa.core:494] packing report/packOutput_Pipeline_VITIS_LOOP_317_1_csynth.xml -D0712 15:11:21.478 tapa.core:494] packing report/packOutput_Pipeline_VITIS_LOOP_317_1_csynth.xml -D0712 15:11:21.478 tapa.core:494] packing report/computeHash_Feeder_csynth.xml -D0712 15:11:21.478 tapa.core:494] packing report/computeHash_Feeder_csynth.xml -D0712 15:11:21.478 tapa.core:494] packing report/packOutput_csynth.xml -D0712 15:11:21.478 tapa.core:494] packing report/packOutput_csynth.xml -D0712 15:11:21.478 tapa.core:494] packing report/bloom_arbiter_ratemonitor_csynth.xml -D0712 15:11:21.478 tapa.core:494] packing report/bloom_arbiter_ratemonitor_csynth.xml -D0712 15:11:21.479 tapa.core:494] packing report/bloom_arb_forwarder_csynth.xml -D0712 15:11:21.479 tapa.core:494] packing report/bloom_arb_forwarder_csynth.xml -D0712 15:11:21.479 tapa.core:494] packing report/shuffle_reordering_per_hash_csynth.xml -D0712 15:11:21.479 tapa.core:494] packing report/shuffle_reordering_per_hash_csynth.xml -D0712 15:11:21.479 tapa.core:494] packing report/bloom_arb_forwarder_Pipeline_MAIN_LOOP_csynth.xml -D0712 15:11:21.479 tapa.core:494] packing report/bloom_arb_forwarder_Pipeline_MAIN_LOOP_csynth.xml -D0712 15:11:21.480 tapa.core:494] packing report/bloom_hier_arbiter_atom_csynth.xml -D0712 15:11:21.480 tapa.core:494] packing report/bloom_hier_arbiter_atom_csynth.xml -D0712 15:11:21.480 tapa.core:494] packing report/bloom_arb_forwarder_Pipeline_INIT_LOOP_csynth.xml -D0712 15:11:21.480 tapa.core:494] packing report/bloom_arb_forwarder_Pipeline_INIT_LOOP_csynth.xml -D0712 15:11:21.480 tapa.core:494] packing report/queryResult_per_hash_Pipeline_PROCESS_QUERIES_csynth.xml -D0712 15:11:21.480 tapa.core:494] packing report/queryResult_per_hash_Pipeline_PROCESS_QUERIES_csynth.xml -D0712 15:11:21.480 tapa.core:494] packing report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1_csynth.xml -D0712 15:11:21.480 tapa.core:494] packing report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1_csynth.xml -D0712 15:11:21.481 tapa.core:494] packing report/writeOutput_synchronous_csynth.xml -D0712 15:11:21.481 tapa.core:494] packing report/writeOutput_synchronous_csynth.xml -D0712 15:11:21.481 tapa.core:494] packing report/workload_csynth.xml -D0712 15:11:21.481 tapa.core:494] packing report/workload_csynth.xml -D0712 15:11:21.481 tapa.core:494] packing report/loadBV_Pipeline_VITIS_LOOP_181_1_csynth.xml -D0712 15:11:21.481 tapa.core:494] packing report/loadBV_Pipeline_VITIS_LOOP_181_1_csynth.xml -D0712 15:11:21.481 tapa.core:494] packing report/bloom_aggregate_SPLIT_csynth.xml -D0712 15:11:21.481 tapa.core:494] packing report/bloom_aggregate_SPLIT_csynth.xml -D0712 15:11:21.482 tapa.core:494] packing report/computeHash_Computer_Pipeline_MAIN_LOOP_csynth.xml -D0712 15:11:21.482 tapa.core:494] packing report/computeHash_Computer_Pipeline_MAIN_LOOP_csynth.xml -D0712 15:11:21.482 tapa.core:494] packing report/computeHash_Computer_csynth.xml -D0712 15:11:21.482 tapa.core:494] packing report/computeHash_Computer_csynth.xml -D0712 15:11:21.482 tapa.core:494] packing report/shuffle_TtoS_per_hash_Pipeline_VITIS_LOOP_473_2_csynth.xml -D0712 15:11:21.482 tapa.core:494] packing report/shuffle_TtoS_per_hash_Pipeline_VITIS_LOOP_473_2_csynth.xml -D0712 15:11:21.482 tapa.core:494] packing report/loadBV_csynth.xml -D0712 15:11:21.482 tapa.core:494] packing report/loadBV_csynth.xml -D0712 15:11:21.483 tapa.core:494] packing report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1_csynth.xml -D0712 15:11:21.483 tapa.core:494] packing report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1_csynth.xml -D0712 15:11:21.483 tapa.core:494] packing report/loadKey_csynth.xml -D0712 15:11:21.483 tapa.core:494] packing report/loadKey_csynth.xml -D0712 15:11:21.483 tapa.core:494] packing report/shuffle_TtoS_per_hash_csynth.xml -D0712 15:11:21.483 tapa.core:494] packing report/shuffle_TtoS_per_hash_csynth.xml -I0712 15:11:21.484 tapa.core:497] generated the v++ xo file at generated/multistream_MurmurHash3.xo -I0712 15:11:21.484 tapa.core:497] generated the v++ xo file at generated/multistream_MurmurHash3.xo diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/multistream_MurmurHash3.xo b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/multistream_MurmurHash3.xo index d334d6c5..2a3c28f1 100644 Binary files a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/multistream_MurmurHash3.xo and b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/multistream_MurmurHash3.xo differ diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/multistream_MurmurHash3_generate_bitstream.sh b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/multistream_MurmurHash3_generate_bitstream.sh new file mode 100755 index 00000000..7096d86f --- /dev/null +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/multistream_MurmurHash3_generate_bitstream.sh @@ -0,0 +1,35 @@ +#!/bin/bash +TARGET=hw +# TARGET=hw_emu +# DEBUG=-g + +TOP=workload +XO='/home/ylxiao/workspace/rapidstream-cookbook/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/multistream_MurmurHash3.xo' +>&2 echo "Using the default clock target of the platform." +PLATFORM="" +if [ -z $PLATFORM ]; then echo Please edit this file and set a valid PLATFORM= on line "${LINENO}"; exit; fi + +OUTPUT_DIR="$(pwd)/vitis_run_${TARGET}" + +MAX_SYNTH_JOBS=8 +STRATEGY="Explore" +PLACEMENT_STRATEGY="EarlyBlockPlacement" + +v++ ${DEBUG} \ + --link \ + --output "${OUTPUT_DIR}/${TOP}_${PLATFORM}.xclbin" \ + --kernel ${TOP} \ + --platform ${PLATFORM} \ + --target ${TARGET} \ + --report_level 2 \ + --temp_dir "${OUTPUT_DIR}/${TOP}_${PLATFORM}.temp" \ + --optimize 3 \ + --connectivity.nk ${TOP}:1:${TOP} \ + --save-temps \ + "${XO}" \ + --vivado.synth.jobs ${MAX_SYNTH_JOBS} \ + --vivado.prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=1 \ + --vivado.prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=$STRATEGY \ + --vivado.prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=$PLACEMENT_STRATEGY \ + --vivado.prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=$STRATEGY \ + --vivado.prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=$STRATEGY \ diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report.json b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report.json index 4d40a0f7..e33fa203 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report.json +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report.json @@ -8,7 +8,7 @@ "BRAM_18K": 0, "DSP": 0, "FF": 41, - "LUT": 209, + "LUT": 204, "URAM": 0 } }, @@ -20,8 +20,8 @@ "total": { "BRAM_18K": 0, "DSP": 0, - "FF": 935, - "LUT": 5078, + "FF": 1065, + "LUT": 4853, "URAM": 0 } }, @@ -58,9 +58,9 @@ "source": "hls", "total": { "BRAM_18K": 0, - "DSP": 14, - "FF": 1034, - "LUT": 515, + "DSP": 15, + "FF": 1126, + "LUT": 601, "URAM": 0 } }, @@ -73,7 +73,7 @@ "BRAM_18K": 0, "DSP": 0, "FF": 138, - "LUT": 635, + "LUT": 625, "URAM": 0 } }, @@ -86,7 +86,7 @@ "BRAM_18K": 0, "DSP": 0, "FF": 170, - "LUT": 297, + "LUT": 285, "URAM": 0 } }, @@ -99,7 +99,7 @@ "BRAM_18K": 0, "DSP": 0, "FF": 394, - "LUT": 419, + "LUT": 409, "URAM": 0 } }, @@ -111,8 +111,8 @@ "total": { "BRAM_18K": 0, "DSP": 0, - "FF": 55, - "LUT": 146, + "FF": 68, + "LUT": 164, "URAM": 0 } }, @@ -122,11 +122,11 @@ "area": { "source": "hls", "total": { - "BRAM_18K": 4, + "BRAM_18K": 64, "DSP": 0, - "FF": 784, - "LUT": 3449, - "URAM": 4 + "FF": 828, + "LUT": 3778, + "URAM": 16 } }, "count": 3 @@ -163,8 +163,8 @@ "total": { "BRAM_18K": 0, "DSP": 0, - "FF": 6011, - "LUT": 11050, + "FF": 6037, + "LUT": 11067, "URAM": 0 } }, @@ -173,11 +173,11 @@ }, "source": "hls", "total": { - "BRAM_18K": 12, - "DSP": 420, - "FF": 189355, - "LUT": 533801, - "URAM": 12 + "BRAM_18K": 192, + "DSP": 450, + "FF": 193183, + "LUT": 536043, + "URAM": 48 } }, "name": "workload", diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report.yaml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report.yaml index d21fb2a1..a43629b6 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report.yaml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report.yaml @@ -10,11 +10,11 @@ performance: area: source: hls total: - BRAM_18K: 12 - DSP: 420 - FF: 189355 - LUT: 533801 - URAM: 12 + BRAM_18K: 192 + DSP: 450 + FF: 193183 + LUT: 536043 + URAM: 48 breakdown: bloom_aggregate_SPLIT: count: 10 @@ -24,7 +24,7 @@ area: BRAM_18K: 0 DSP: 0 FF: 41 - LUT: 209 + LUT: 204 URAM: 0 bloom_arb_forwarder: count: 6 @@ -33,8 +33,8 @@ area: total: BRAM_18K: 0 DSP: 0 - FF: 935 - LUT: 5078 + FF: 1065 + LUT: 4853 URAM: 0 bloom_arbiter_ratemonitor: count: 6 @@ -62,9 +62,9 @@ area: source: hls total: BRAM_18K: 0 - DSP: 14 - FF: 1034 - LUT: 515 + DSP: 15 + FF: 1126 + LUT: 601 URAM: 0 computeHash_Feeder: count: 10 @@ -74,7 +74,7 @@ area: BRAM_18K: 0 DSP: 0 FF: 138 - LUT: 635 + LUT: 625 URAM: 0 loadBV: count: 1 @@ -84,7 +84,7 @@ area: BRAM_18K: 0 DSP: 0 FF: 170 - LUT: 297 + LUT: 285 URAM: 0 loadKey: count: 1 @@ -94,7 +94,7 @@ area: BRAM_18K: 0 DSP: 0 FF: 394 - LUT: 419 + LUT: 409 URAM: 0 packOutput: count: 10 @@ -103,19 +103,19 @@ area: total: BRAM_18K: 0 DSP: 0 - FF: 55 - LUT: 146 + FF: 68 + LUT: 164 URAM: 0 queryResult_per_hash: count: 3 area: source: hls total: - BRAM_18K: 4 + BRAM_18K: 64 DSP: 0 - FF: 784 - LUT: 3449 - URAM: 4 + FF: 828 + LUT: 3778 + URAM: 16 shuffle_TtoS_per_hash: count: 6 area: @@ -143,6 +143,6 @@ area: total: BRAM_18K: 0 DSP: 0 - FF: 6011 - LUT: 11050 + FF: 6037 + LUT: 11067 URAM: 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT.verbose.sched.rpt.xml index 9bbdf624..c8f63d42 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:47 2024 +Mon Jul 22 13:45:05 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -15,7 +15,7 @@
Clock, Target, Estimated, Uncertainty -3.33 ns, 1.972 ns, 0.90 ns +3.33 ns, 1.820 ns, 0.90 ns
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1.sched.adb.xml index 0954d88e..07476f54 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1.sched.adb.xml @@ -158,9 +158,9 @@ while.cond:1 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4 - + @@ -173,9 +173,9 @@ while.cond:2 %tmp = partselect i23 @_ssdm_op_PartSelect.i23.i32.i32.i32, i32 %nu - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1.verbose.sched.rpt.xml index 7e30d8a9..23224075 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:47 2024 +Mon Jul 22 13:45:05 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -15,7 +15,7 @@
Clock, Target, Estimated, Uncertainty -3.33 ns, 1.972 ns, 0.90 ns +3.33 ns, 1.820 ns, 0.90 ns
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1_csynth.xml index 78ef81ae..4652883f 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_Pipeline_VITIS_LOOP_324_1_csynth.xml @@ -18,7 +18,7 @@ no ns -1.972 +1.820 clock cycles @@ -48,7 +48,7 @@ 37 -153 +148 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_csynth.xml index 86bdf916..874187b0 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_aggregate_SPLIT_csynth.xml @@ -18,7 +18,7 @@ no ns -1.972 +1.820 clock cycles @@ -36,7 +36,7 @@ 41 -209 +204 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder.sched.adb.xml index 257bc3c9..97429308 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder.sched.adb.xml @@ -803,9 +803,9 @@ entry:169 %call_ln0 = call void @bloom_arb_forwarder_Pipeline_INIT_LOOP, i24 %bl - + @@ -833,9 +833,9 @@ entry:156 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_HASH_ - + @@ -878,9 +878,9 @@ entry:159 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_HASH_ - + @@ -923,9 +923,9 @@ entry:162 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_HASH_ - + @@ -968,9 +968,9 @@ entry:165 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_HASH_ - + @@ -1046,9 +1046,9 @@ entry:170 %empty_106 = wait i32 @_ssdm_op_Wait - + @@ -2639,9 +2639,9 @@ entry:104 %specbitsmap_ln0 = specbitsmap void @_ssdm_op_SpecBitsMap, i65 %arb_st - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder.verbose.sched.rpt.xml index 652dae3f..9b35a6de 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:54 2024 +Mon Jul 22 13:45:12 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_INIT_LOOP.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_INIT_LOOP.verbose.sched.rpt.xml index 8fe034a6..922c550f 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_INIT_LOOP.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_INIT_LOOP.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:50 2024 +Mon Jul 22 13:45:07 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP.sched.adb.xml index f50d5fbe..3b9a7b54 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP.sched.adb.xml @@ -353,9 +353,9 @@ newFuncRoot:21 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -398,9 +398,9 @@ newFuncRoot:24 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -443,9 +443,9 @@ newFuncRoot:27 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -488,9 +488,9 @@ newFuncRoot:30 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -518,9 +518,9 @@ newFuncRoot:32 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -548,9 +548,9 @@ newFuncRoot:34 %zext_ln392_cast = zext i3 %zext_ln392_read - + @@ -578,9 +578,9 @@ newFuncRoot:36 %zext_ln146_6_cast = zext i2 %zext_ln146_6_read - + @@ -608,9 +608,9 @@ newFuncRoot:38 %zext_ln146_4_cast = zext i2 %zext_ln146_4_read - + @@ -638,9 +638,9 @@ newFuncRoot:40 %zext_ln146_2_cast = zext i1 %zext_ln146_2_read - + @@ -653,9 +653,9 @@ newFuncRoot:41 %zext_ln146_1_cast = zext i6 %zext_ln146_1_read - + @@ -1753,7 +1753,7 @@ while.cond:5 %p_load = load i32 %empty_16 @@ -1766,9 +1766,9 @@ while.cond:6 %icmp_ln399 = icmp_slt i32 %total_num_reads_11, i32 2560 - + @@ -1781,9 +1781,9 @@ while.cond:7 %tmp_6 = partselect i23 @_ssdm_op_PartSelect.i23.i32.i32.i32, i32 % - + @@ -1796,9 +1796,9 @@ while.cond:8 %icmp_ln400 = icmp_slt i23 %tmp_6, i23 1 - + @@ -1811,9 +1811,9 @@ while.cond:9 %tmp_8 = partselect i23 @_ssdm_op_PartSelect.i23.i32.i32.i32, i32 % - + @@ -1826,9 +1826,9 @@ while.cond:10 %icmp_ln401 = icmp_slt i23 %tmp_8, i23 1 - + @@ -1841,9 +1841,9 @@ while.cond:11 %tmp_10 = partselect i23 @_ssdm_op_PartSelect.i23.i32.i32.i32, i32 - + @@ -1856,9 +1856,9 @@ while.cond:12 %icmp_ln402 = icmp_slt i23 %tmp_10, i23 1 - + @@ -1871,9 +1871,9 @@ while.cond:13 %tmp_12 = partselect i23 @_ssdm_op_PartSelect.i23.i32.i32.i32, i32 - + @@ -1886,9 +1886,9 @@ while.cond:14 %icmp_ln403 = icmp_slt i23 %tmp_12, i23 1 - + @@ -1901,9 +1901,9 @@ while.cond:15 %tmp_16 = partselect i23 @_ssdm_op_PartSelect.i23.i32.i32.i32, i32 - + @@ -2125,7 +2125,7 @@ if.then189:0 %hash_stream_0_read = read i33 @_ssdm_op_Read.ap_fifo.volatile.i33P - + - + @@ -2161,9 +2161,9 @@ if.then189:2 %zext_ln1514 = zext i6 %ret_V - + @@ -2269,9 +2269,9 @@ if.then189:8 %store_ln433 = store i1 1, i1 %bloom_arb_forwarder_int_int_istream_ - + @@ -2305,9 +2305,9 @@ if.then189:10 %store_ln434 = store i24 %cur_metadata_iidx_V, i24 %bloom_arb_forw - + @@ -2509,7 +2509,7 @@ if.then189.1:0 %hash_stream_1_read = read i33 @_ssdm_op_Read.ap_fifo.volatile.i3 - + - + @@ -2545,9 +2545,9 @@ if.then189.1:2 %zext_ln1514_1 = zext i6 %ret_V_1 - + @@ -2653,9 +2653,9 @@ if.then189.1:8 %store_ln433 = store i1 1, i1 %bloom_arb_forwarder_int_int_istrea - + @@ -2707,9 +2707,9 @@ if.then189.1:11 %store_ln434 = store i1 1, i1 %bloom_arb_forwarder_int_int_istre - + @@ -2945,7 +2945,7 @@ if.then189.2:0 %hash_stream_2_read = read i33 @_ssdm_op_Read.ap_fifo.volatile.i3 - + - + @@ -2981,9 +2981,9 @@ if.then189.2:2 %zext_ln1514_2 = zext i6 %ret_V_2 - + @@ -3089,9 +3089,9 @@ if.then189.2:8 %store_ln433 = store i1 1, i1 %bloom_arb_forwarder_int_int_istrea - + @@ -3143,9 +3143,9 @@ if.then189.2:11 %store_ln434 = store i2 2, i2 %bloom_arb_forwarder_int_int_istre - + @@ -3381,7 +3381,7 @@ if.then189.3:0 %hash_stream_3_read = read i33 @_ssdm_op_Read.ap_fifo.volatile.i3 - + - + @@ -3417,9 +3417,9 @@ if.then189.3:2 %zext_ln1514_3 = zext i6 %ret_V_3 - + @@ -3525,9 +3525,9 @@ if.then189.3:8 %store_ln433 = store i1 1, i1 %bloom_arb_forwarder_int_int_istrea - + @@ -3579,9 +3579,9 @@ if.then189.3:11 %store_ln434 = store i2 3, i2 %bloom_arb_forwarder_int_int_istre - + @@ -3817,7 +3817,7 @@ if.then189.4:0 %hash_stream_4_read = read i33 @_ssdm_op_Read.ap_fifo.volatile.i3 - + - + @@ -3853,9 +3853,9 @@ if.then189.4:2 %zext_ln1514_4 = zext i6 %ret_V_4 - + @@ -3961,9 +3961,9 @@ if.then189.4:8 %store_ln433 = store i1 1, i1 %bloom_arb_forwarder_int_int_istrea - + @@ -4015,9 +4015,9 @@ if.then189.4:11 %store_ln434 = store i3 4, i3 %bloom_arb_forwarder_int_int_istre - + @@ -4183,9 +4183,9 @@ for.body221:4 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_H - + @@ -4199,9 +4199,9 @@ for.body221:5 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_H - + @@ -4401,9 +4401,9 @@ for.inc247:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_HA - + @@ -4417,9 +4417,9 @@ for.inc247:2 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_HA - + @@ -4602,9 +4602,9 @@ for.inc247.122:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -4618,9 +4618,9 @@ for.inc247.122:2 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -4803,9 +4803,9 @@ for.inc247.239:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -4819,9 +4819,9 @@ for.inc247.239:2 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -5004,9 +5004,9 @@ for.inc247.356:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -5020,9 +5020,9 @@ for.inc247.356:2 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -5205,9 +5205,9 @@ for.body221.1:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED - + @@ -5407,9 +5407,9 @@ for.inc247.1:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -5592,9 +5592,9 @@ for.inc247.1.1:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -5777,9 +5777,9 @@ for.inc247.1.2:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -5962,9 +5962,9 @@ for.inc247.1.3:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -6147,9 +6147,9 @@ for.body221.2:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED - + @@ -6349,9 +6349,9 @@ for.inc247.2:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -6534,9 +6534,9 @@ for.inc247.2.1:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -6719,9 +6719,9 @@ for.inc247.2.2:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -6904,9 +6904,9 @@ for.inc247.2.3:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -7089,9 +7089,9 @@ for.body221.3:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED - + @@ -7291,9 +7291,9 @@ for.inc247.3:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -7476,9 +7476,9 @@ for.inc247.3.1:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -7661,9 +7661,9 @@ for.inc247.3.2:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -7846,9 +7846,9 @@ for.inc247.3.3:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -8031,9 +8031,9 @@ for.body221.4:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED - + @@ -8233,9 +8233,9 @@ for.inc247.4:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -8418,9 +8418,9 @@ for.inc247.4.1:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -8603,9 +8603,9 @@ for.inc247.4.2:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -8788,9 +8788,9 @@ for.inc247.4.3:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -8973,9 +8973,9 @@ for.body221.5:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED - + @@ -9175,9 +9175,9 @@ for.inc247.5:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -9360,9 +9360,9 @@ for.inc247.5.1:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -9545,9 +9545,9 @@ for.inc247.5.2:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -9730,9 +9730,9 @@ for.inc247.5.3:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -9915,9 +9915,9 @@ for.body221.6:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED - + @@ -10117,9 +10117,9 @@ for.inc247.6:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -10302,9 +10302,9 @@ for.inc247.6.1:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -10487,9 +10487,9 @@ for.inc247.6.2:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -10672,9 +10672,9 @@ for.inc247.6.3:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -10857,9 +10857,9 @@ for.body221.7:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED - + @@ -11059,9 +11059,9 @@ for.inc247.7:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKED_ - + @@ -11244,9 +11244,9 @@ for.inc247.7.1:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -11429,9 +11429,9 @@ for.inc247.7.2:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + @@ -11614,9 +11614,9 @@ for.inc247.7.3:1 %bloom_arb_forwarder_int_int_istream_ap_uint_32_5_ostream_PACKE - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml index d8c19cbf..207ac791 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:54 2024 +Mon Jul 22 13:45:11 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP_csynth.xml index 0b7d3622..583dc4f8 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_Pipeline_MAIN_LOOP_csynth.xml @@ -48,7 +48,7 @@ 483 -4512 +4287 0 0 0 @@ -302,7 +302,7 @@ ap_none in -6 +19 data @@ -324,7 +324,7 @@ ap_none in -6 +19 data @@ -357,7 +357,7 @@ ap_none in -6 +19 data @@ -390,7 +390,7 @@ ap_none in -6 +19 data @@ -423,7 +423,7 @@ ap_none in -6 +19 data @@ -1974,7 +1974,7 @@ ap_vld out -6 +19 data @@ -2051,7 +2051,7 @@ ap_vld out -6 +19 data @@ -2150,7 +2150,7 @@ ap_vld out -6 +19 data @@ -2249,7 +2249,7 @@ ap_vld out -6 +19 data @@ -2348,7 +2348,7 @@ ap_vld out -6 +19 data diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_csynth.xml index cfc80ea6..376732bc 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arb_forwarder_csynth.xml @@ -35,8 +35,8 @@ -935 -5078 +1065 +4853 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor.verbose.sched.rpt.xml index a3e9af66..7fabdabb 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:10:42 2024 +Mon Jul 22 13:46:09 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_INIT_LOOP_2.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_INIT_LOOP_2.verbose.sched.rpt.xml index 70699ca9..aee33577 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_INIT_LOOP_2.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_INIT_LOOP_2.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:52 2024 +Mon Jul 22 13:45:10 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP.sched.adb.xml index 63b64d32..ef8e3eea 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP.sched.adb.xml @@ -3064,7 +3064,7 @@ while.cond:62 %add_ln475 = add i32 %add_ln475_3, i32 %inc61630_lcssa54_load diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml index 9cb2c52b..2754cfbd 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_arbiter_ratemonitor_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:10:38 2024 +Mon Jul 22 13:46:05 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_hier_arbiter_atom.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_hier_arbiter_atom.verbose.sched.rpt.xml index eefc4466..38ec094b 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_hier_arbiter_atom.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_hier_arbiter_atom.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:49 2024 +Mon Jul 22 13:45:06 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_hier_arbiter_atom_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_hier_arbiter_atom_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml index a1afc735..d466cec1 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_hier_arbiter_atom_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/bloom_hier_arbiter_atom_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:49 2024 +Mon Jul 22 13:45:05 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer.sched.adb.xml index f590973b..1f9393cd 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer.sched.adb.xml @@ -61,10 +61,10 @@ entry:14 %empty = nbreadreq i1 @_ssdm_op_NbReadReq.ap_fifo.i33P0A, i33 %key_stre - + @@ -76,10 +76,10 @@ entry:15 %empty_12 = nbreadreq i1 @_ssdm_op_NbReadReq.ap_fifo.i33P0A, i33 %key_s - + @@ -94,10 +94,10 @@ entry:16 %empty_13 = nbwritereq i1 @_ssdm_op_NbWriteReq.ap_fifo.i33P0A, i33 %has - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer.verbose.sched.rpt.xml index 8a68c0af..23abdf06 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:46 2024 +Mon Jul 22 13:45:05 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -24,7 +24,7 @@
, min, max, min, max, min, max, Type -527, 527, 1.755 us, 1.755 us, 528, 528, no +4194319, 4194319, 13.967 ms, 13.967 ms, 4194320, 4194320, no
 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP.sched.adb.xml index 5b22476b..551951f8 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP.sched.adb.xml @@ -89,7 +89,7 @@ - + - + @@ -179,9 +179,9 @@ newFuncRoot:5 %br_ln0 = br void %for.body.i - + @@ -194,9 +194,9 @@ for.body.i:0 %total_num_writes_1 = load i10 %total_num_writes - + @@ -211,7 +211,7 @@ for.body.i:1 %icmp_ln216 = icmp_eq i10 %total_num_writes_1, i10 512 @@ -224,9 +224,9 @@ for.body.i:2 %empty = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 512 - + @@ -255,9 +255,9 @@ for.body.i:4 %br_ln216 = br i1 %icmp_ln216, void %for.body.i.split, void %while. - + @@ -669,57 +669,42 @@ for.body.i.split:22 %h1_5 = mul i32 %h1_4, i32 2246822507 - + - - - - -NULL - - - - - - - - + - + NULL - + - + LogicGate - + @@ -728,16 +713,16 @@ for.body.i.split:26 %h1_6 = xor i25 %zext_ln174, i25 %trunc_ln146 - + Multiplier - + @@ -746,49 +731,49 @@ for.body.i.split:27 %h1_7 = mul i25 %h1_6, i25 11710005 - + Multiplier - + - + NULL - + - + - + NULL - + - + @@ -810,7 +795,7 @@ while.end.exitStub:0 %ret_ln0 = ret - + NULL @@ -825,7 +810,7 @@ for.body.i.split:0 %specpipeline_ln217 = specpipeline void @_ssdm_op_SpecPipelin - + NULL @@ -840,6 +825,21 @@ for.body.i.split:1 %specloopname_ln213 = specloopname void @_ssdm_op_SpecLoopNam + +NULL + + + + + + + + + + LogicGate @@ -847,12 +847,12 @@ for.body.i.split:1 %specloopname_ln213 = specloopname void @_ssdm_op_SpecLoopNam - + - + @@ -862,9 +862,9 @@ for.body.i.split:30 %h1_9 = xor i9 %trunc_ln2, i9 %trunc_ln146_1 - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml index 92cf3c7e..4acbf3f8 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:46 2024 +Mon Jul 22 13:45:05 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -24,7 +24,7 @@
, min, max, min, max, min, max, Type -525, 525, 1.748 us, 1.748 us, 525, 525, no +4194317, 4194317, 13.967 ms, 13.967 ms, 4194317, 4194317, no
 @@ -35,7 +35,7 @@ Loop Name, min, max, Latency, achieved, target, Count, Pipelined -523, 523, 13, 1, 1, 512, yes +4194315, 4194315, 13, 1, 1, 4194304, yes
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP_csynth.xml index 04a55afe..35a96070 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_Pipeline_MAIN_LOOP_csynth.xml @@ -22,21 +22,21 @@ clock cycles -525 -525 -525 -1.748 us -1.748 us -1.748 us -525 -525 +4194317 +4194317 +4194317 +13.967 ms +13.967 ms +13.967 ms +4194317 +4194317 2.43 -512 -523 -1741 +4194304 +4194315 +13967068 1 13 @@ -47,9 +47,9 @@ -14 -1030 -477 +15 +1122 +563 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_csynth.xml index b91620f4..8b33fa26 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Computer_csynth.xml @@ -22,22 +22,22 @@ clock cycles -527 -527 -527 -1.755 us -1.755 us -1.755 us -528 -528 +4194319 +4194319 +4194319 +13.967 ms +13.967 ms +13.967 ms +4194320 +4194320 -14 -1034 -515 +15 +1126 +601 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder.verbose.sched.rpt.xml index ab1bbea9..cf7d8ab2 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:45 2024 +Mon Jul 22 13:45:06 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1.sched.adb.xml index 29d1c3f5..b13b0169 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1.sched.adb.xml @@ -296,9 +296,9 @@ while.cond:5 %total_num_writes_4 = load i32 %total_num_writes - + @@ -311,9 +311,9 @@ while.cond:6 %tmp = partselect i23 @_ssdm_op_PartSelect.i23.i32.i32.i32, i32 %to - + @@ -328,7 +328,7 @@ while.cond:7 %icmp_ln222 = icmp_slt i23 %tmp, i23 1 @@ -404,9 +404,9 @@ for.body16:1 %specloopname_ln226 = specloopname void @_ssdm_op_SpecLoopName, voi - + @@ -420,9 +420,9 @@ for.body16:2 %tmp_1 = partselect i23 @_ssdm_op_PartSelect.i23.i32.i32.i32, i32 % - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1.verbose.sched.rpt.xml index 1a771320..9a33f5b6 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:45 2024 +Mon Jul 22 13:45:06 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1_csynth.xml index 38d6d665..a0915479 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_Pipeline_VITIS_LOOP_222_1_csynth.xml @@ -48,7 +48,7 @@ 134 -579 +569 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_csynth.xml index fb241a96..2c19c65f 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/computeHash_Feeder_csynth.xml @@ -36,7 +36,7 @@ 138 -635 +625 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/csynth.xml index 393d1772..0c5a9301 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/csynth.xml @@ -540,12 +540,12 @@
- - - - - - - + + + + + + + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV.verbose.sched.rpt.xml index f633b798..c4dc6934 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:49 2024 +Mon Jul 22 13:45:06 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -15,7 +15,7 @@
Clock, Target, Estimated, Uncertainty -3.33 ns, 2.029 ns, 0.90 ns +3.33 ns, 1.880 ns, 0.90 ns
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1.sched.adb.xml index d1deadb7..c81cf785 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1.sched.adb.xml @@ -188,9 +188,9 @@ for.cond:0 %i_resp_1 = load i32 %i_resp - + @@ -203,9 +203,9 @@ for.cond:2 %tmp = partselect i28 @_ssdm_op_PartSelect.i28.i32.i32.i32, i32 %i_re - + @@ -451,9 +451,9 @@ for.body:1 %specloopname_ln185 = specloopname void @_ssdm_op_SpecLoopName, void - + @@ -467,9 +467,9 @@ for.body:2 %tmp_1 = partselect i28 @_ssdm_op_PartSelect.i28.i32.i32.i32, i32 %i_ - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1.verbose.sched.rpt.xml index 9661eff3..5e9240d6 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:49 2024 +Mon Jul 22 13:45:06 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -15,7 +15,7 @@
Clock, Target, Estimated, Uncertainty -3.33 ns, 2.029 ns, 0.90 ns +3.33 ns, 1.880 ns, 0.90 ns
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1_csynth.xml index b363bb46..c1dd0a90 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_Pipeline_VITIS_LOOP_181_1_csynth.xml @@ -18,7 +18,7 @@ no ns -2.029 +1.880 clock cycles @@ -48,7 +48,7 @@ 166 -232 +220 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_csynth.xml index 482d13c5..87df15f4 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadBV_csynth.xml @@ -18,7 +18,7 @@ no ns -2.029 +1.880 clock cycles @@ -36,7 +36,7 @@ 170 -297 +285 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey.verbose.sched.rpt.xml index ba8fdfdf..df895a0c 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:48 2024 +Mon Jul 22 13:45:06 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -15,7 +15,7 @@
Clock, Target, Estimated, Uncertainty -3.33 ns, 1.972 ns, 0.90 ns +3.33 ns, 1.829 ns, 0.90 ns
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1.sched.adb.xml index 9b261d4c..8e9c0c05 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1.sched.adb.xml @@ -293,9 +293,9 @@ for.cond:0 %i_resp_1 = load i32 %i_resp - + @@ -308,9 +308,9 @@ for.cond:2 %tmp = partselect i23 @_ssdm_op_PartSelect.i23.i32.i32.i32, i32 %i_re - + @@ -675,9 +675,9 @@ for.body:1 %specloopname_ln198 = specloopname void @_ssdm_op_SpecLoopName, void - + @@ -691,9 +691,9 @@ for.body:2 %tmp_1 = partselect i23 @_ssdm_op_PartSelect.i23.i32.i32.i32, i32 %i_ - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1.verbose.sched.rpt.xml index a6e38872..fe174781 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:48 2024 +Mon Jul 22 13:45:06 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -15,7 +15,7 @@
Clock, Target, Estimated, Uncertainty -3.33 ns, 1.972 ns, 0.90 ns +3.33 ns, 1.829 ns, 0.90 ns
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1_csynth.xml index 61df12cc..e8ef48e2 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_Pipeline_VITIS_LOOP_194_1_csynth.xml @@ -18,7 +18,7 @@ no ns -1.972 +1.829 clock cycles @@ -48,7 +48,7 @@ 390 -291 +281 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_csynth.xml index ac0ccc0f..8cd985b5 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/loadKey_csynth.xml @@ -18,7 +18,7 @@ no ns -1.972 +1.829 clock cycles @@ -36,7 +36,7 @@ 394 -419 +409 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput.verbose.sched.rpt.xml index 2ad846fc..11120793 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:48 2024 +Mon Jul 22 13:45:30 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -24,7 +24,7 @@
, min, max, min, max, min, max, Type -516, 516, 1.718 us, 1.718 us, 517, 517, no +4194308, 4194308, 13.967 ms, 13.967 ms, 4194309, 4194309, no
 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1.sched.adb.xml index 68d3d80e..c3b49c78 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1.sched.adb.xml @@ -38,7 +38,7 @@ newFuncRoot:0 %p_Val2_s = alloca i32 1 - + - + @@ -113,9 +113,9 @@ newFuncRoot:5 %br_ln0 = br void %for.body - + @@ -143,9 +143,9 @@ for.body:1 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 429 - + @@ -160,7 +160,7 @@ for.body:2 %icmp_ln317 = icmp_eq i10 %i_1, i10 512 @@ -173,9 +173,9 @@ for.body:3 %empty = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 512, - + @@ -204,9 +204,9 @@ for.body:5 %br_ln317 = br i1 %icmp_ln317, void %for.body.split, void %for.end.ex - + @@ -252,9 +252,9 @@ for.body.split:8 %br_ln321 = br i1 %icmp_ln321, void %for.body.split.for.inc_cri - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1.verbose.sched.rpt.xml index 0a74d843..13e6db03 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:48 2024 +Mon Jul 22 13:45:30 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -24,7 +24,7 @@
, min, max, min, max, min, max, Type -514, 514, 1.712 us, 1.712 us, 514, 514, no +4194306, 4194306, 13.967 ms, 13.967 ms, 4194306, 4194306, no
 @@ -35,7 +35,7 @@ Loop Name, min, max, Latency, achieved, target, Count, Pipelined -512, 512, 2, 1, 1, 512, yes +4194304, 4194304, 2, 1, 1, 4194304, yes
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1_csynth.xml index 6a5ffe9d..428eb239 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_Pipeline_VITIS_LOOP_317_1_csynth.xml @@ -22,21 +22,21 @@ clock cycles -514 -514 -514 -1.712 us -1.712 us -1.712 us -514 -514 +4194306 +4194306 +4194306 +13.967 ms +13.967 ms +13.967 ms +4194306 +4194306 2.43 -512 -512 -1704 +4194304 +4194304 +13967032 1 2 @@ -47,8 +47,8 @@ -51 -108 +64 +126 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_csynth.xml index b6575653..6dd842e7 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/packOutput_csynth.xml @@ -22,21 +22,21 @@ clock cycles -516 -516 -516 -1.718 us -1.718 us -1.718 us -517 -517 +4194308 +4194308 +4194308 +13.967 ms +13.967 ms +13.967 ms +4194309 +4194309 -55 -146 +68 +164 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash.verbose.sched.rpt.xml index 225c0b5a..6ca6322e 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:52 2024 +Mon Jul 22 13:45:36 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES.sched.adb.xml index f0d4097b..4b5ea095 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES.sched.adb.xml @@ -3,13 +3,13 @@ - + - + @@ -29,7 +29,7 @@ - + - + @@ -209,9 +209,9 @@ newFuncRoot:11 %br_ln0 = br void %for.body220 - + @@ -224,9 +224,9 @@ for.body220:0 %i_1 = load i5 %i - + @@ -241,7 +241,7 @@ for.body220:1 %icmp_ln460 = icmp_eq i5 %i_1, i5 16 @@ -254,9 +254,9 @@ for.body220:2 %empty = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 16 - + @@ -285,9 +285,9 @@ for.body220:4 %br_ln460 = br i1 %icmp_ln460, void %for.body220.split, void %whil - + @@ -301,9 +301,9 @@ for.body220.split:0 %element_idx = trunc i5 %i_1 - + @@ -333,9 +333,9 @@ for.body220.split:6 %icmp_ln465 = icmp_eq i2 %tmp, i2 0 - + @@ -433,9 +433,9 @@ arrayidx226102.exit:0 %br_ln467 = br void %for.inc231 - + @@ -461,18 +461,18 @@ for.inc231:1 %br_ln460 = br void %for.body220 -NULL +FIFO - + - + @@ -482,60 +482,79 @@ for.body220.split:1 %specpipeline_ln461 = specpipeline void @_ssdm_op_SpecPipeli - + - + - -FIFO + +NULL + + + + + + + + + + + + + + + +NULL - + - + - + NULL - + - + - + NULL - + - + NULL @@ -543,7 +562,7 @@ for.body220.split:7 %zext_ln469 = zext i1 %element_idx - + - + NULL @@ -559,7 +578,7 @@ if.else:0 %bv_buf_URAMS_V_addr = getelementptr i32 %bv_buf_URAMS_V, i64 0, i64 % - + - + NULL @@ -575,7 +594,7 @@ if.else:1 %bv_buf_URAMS_V_1_addr = getelementptr i32 %bv_buf_URAMS_V_1, i64 0, i - + - + NULL @@ -591,7 +610,7 @@ if.else:2 %bv_buf_URAMS_V_2_addr = getelementptr i32 %bv_buf_URAMS_V_2, i64 0, i - + - -NULL + +RAM_T2P_URAM - + + - + - + - + NULL - + + - + - + - -NULL + +RAM_T2P_URAM - + + - + - + - + NULL - + + - + - + - -RAM_T2P_BRAM + +RAM_T2P_URAM - - + + - + - + - + NULL - - + + - + - + - -RAM_T2P_BRAM + +RAM_T2P_URAM - - + + - + - + - + NULL - - - - - - - - - - - -RAM_T2P_BRAM - - - - + + - + - + - + NULL - - + - + - -RAM_T2P_BRAM + +NULL - - + - + - + NULL - - + - + - + NULL - + - + - + - - - -RAM_T2P_URAM +RAM_T2P_BRAM - + - + - + NULL - + - + - + -RAM_T2P_URAM +RAM_T2P_BRAM - + - + - + NULL - + - + - + -RAM_T2P_URAM +RAM_T2P_BRAM - + - + - + NULL - + - + - + -RAM_T2P_URAM +RAM_T2P_BRAM - + - + - + NULL - + - + - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES.verbose.sched.rpt.xml index 7f937f5c..30756b8c 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:50 2024 +Mon Jul 22 13:45:35 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -15,7 +15,7 @@
Clock, Target, Estimated, Uncertainty -3.33 ns, 2.411 ns, 0.90 ns +3.33 ns, 1.792 ns, 0.90 ns
@@ -24,7 +24,7 @@
, min, max, min, max, min, max, Type -19, 19, 63.270 ns, 63.270 ns, 19, 19, no +131075, 131075, 0.436 ms, 0.436 ms, 131075, 131075, no
 @@ -35,7 +35,7 @@ Loop Name, min, max, Latency, achieved, target, Count, Pipelined -17, 17, 3, 1, 1, 16, yes +131073, 131073, 3, 1, 1, 131072, yes
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES_csynth.xml index b1f95c2e..1498dc81 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_LOAD_BV_VALUES_csynth.xml @@ -18,25 +18,25 @@ no ns -2.411 +1.792 clock cycles -19 -19 -19 -63.270 ns -63.270 ns -63.270 ns -19 -19 +131075 +131075 +131075 +0.436 ms +0.436 ms +0.436 ms +131075 +131075 2.43 -16 -17 -56 +131072 +131073 +436473 1 3 @@ -47,8 +47,8 @@ -53 -79 +89 +96 0 0 0 @@ -170,7 +170,7 @@ ap_memory out -1 +14 address @@ -214,7 +214,7 @@ ap_memory out -1 +14 address @@ -258,7 +258,7 @@ ap_memory out -1 +14 address @@ -302,7 +302,7 @@ ap_memory out -1 +14 address @@ -346,7 +346,7 @@ ap_memory out -1 +14 address @@ -390,7 +390,7 @@ ap_memory out -1 +14 address @@ -434,7 +434,7 @@ ap_memory out -1 +14 address @@ -478,7 +478,7 @@ ap_memory out -1 +14 address diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES.sched.adb.xml index 94098dac..8caa4536 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES.sched.adb.xml @@ -1645,7 +1645,7 @@ while.cond:16 %num_writes_17 = load i32 %num_writes @@ -1839,12 +1839,12 @@ if.then247:3 %packed_hash_md_sidx_V = partselect i8 @_ssdm_op_PartSelect.i8.i65. - + - + @@ -1856,9 +1856,9 @@ if.then247:4 %tmp_4 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_looku - + @@ -1873,7 +1873,7 @@ if.then247:6 %zext_ln541 = zext i1 %tmp_4 - + - + @@ -2074,12 +2074,12 @@ if.then280:3 %packed_hash_md_sidx_V_1 = partselect i8 @_ssdm_op_PartSelect.i8.i6 - + - + @@ -2091,9 +2091,9 @@ if.then280:4 %tmp_8 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_looku - + @@ -2108,7 +2108,7 @@ if.then280:6 %zext_ln541_1 = zext i1 %tmp_8 - + - + @@ -2309,12 +2309,12 @@ if.then247.1:3 %packed_hash_md_sidx_V_2 = partselect i8 @_ssdm_op_PartSelect.i8. - + - + @@ -2326,9 +2326,9 @@ if.then247.1:4 %tmp_15 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -2343,7 +2343,7 @@ if.then247.1:6 %zext_ln541_2 = zext i1 %tmp_15 - + - + @@ -2544,12 +2544,12 @@ if.then280.1:3 %packed_hash_md_sidx_V_3 = partselect i8 @_ssdm_op_PartSelect.i8. - + - + @@ -2561,9 +2561,9 @@ if.then280.1:4 %tmp_21 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -2578,7 +2578,7 @@ if.then280.1:6 %zext_ln541_3 = zext i1 %tmp_21 - + - + @@ -2664,10 +2664,10 @@ if.then280.1:13 %br_ln531 = br void %if.end314.1 - + @@ -2696,7 +2696,7 @@ for.inc358.1:3 %xor_ln901_4 = xor i1 %empty_23, i1 1 @@ -2779,12 +2779,12 @@ if.then247.2:3 %packed_hash_md_sidx_V_4 = partselect i8 @_ssdm_op_PartSelect.i8. - + - + @@ -2796,9 +2796,9 @@ if.then247.2:4 %tmp_27 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -2813,7 +2813,7 @@ if.then247.2:6 %zext_ln541_4 = zext i1 %tmp_27 - + - + @@ -2899,10 +2899,10 @@ if.then247.2:13 %br_ln505 = br void %if.end270.2 - + @@ -2931,7 +2931,7 @@ if.end270.2:5 %xor_ln901_5 = xor i1 %empty_22, i1 1 @@ -3014,12 +3014,12 @@ if.then280.2:3 %packed_hash_md_sidx_V_5 = partselect i8 @_ssdm_op_PartSelect.i8. - + - + @@ -3031,9 +3031,9 @@ if.then280.2:4 %tmp_33 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -3048,7 +3048,7 @@ if.then280.2:6 %zext_ln541_5 = zext i1 %tmp_33 - + - + @@ -3134,10 +3134,10 @@ if.then280.2:13 %br_ln531 = br void %if.end314.2 - + @@ -3166,7 +3166,7 @@ for.inc358.2:3 %xor_ln901_6 = xor i1 %empty_21, i1 1 @@ -3249,12 +3249,12 @@ if.then247.3:3 %packed_hash_md_sidx_V_6 = partselect i8 @_ssdm_op_PartSelect.i8. - + - + @@ -3266,9 +3266,9 @@ if.then247.3:4 %tmp_39 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -3283,7 +3283,7 @@ if.then247.3:6 %zext_ln541_6 = zext i1 %tmp_39 - + - + @@ -3369,10 +3369,10 @@ if.then247.3:13 %br_ln505 = br void %if.end270.3 - + @@ -3401,7 +3401,7 @@ if.end270.3:5 %xor_ln901_7 = xor i1 %empty_20, i1 1 @@ -3484,12 +3484,12 @@ if.then280.3:3 %packed_hash_md_sidx_V_7 = partselect i8 @_ssdm_op_PartSelect.i8. - + - + @@ -3501,9 +3501,9 @@ if.then280.3:4 %tmp_45 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -3518,7 +3518,7 @@ if.then280.3:6 %zext_ln541_7 = zext i1 %tmp_45 - + - + @@ -3604,10 +3604,10 @@ if.then280.3:13 %br_ln531 = br void %if.end314.3 - + @@ -3636,7 +3636,7 @@ for.body364:3 %xor_ln901_8 = xor i1 %empty_19, i1 1 @@ -3719,12 +3719,12 @@ if.then374:3 %packed_hash_md_sidx_V_8 = partselect i8 @_ssdm_op_PartSelect.i8.i6 - + - + @@ -3736,9 +3736,9 @@ if.then374:4 %tmp_48 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_look - + @@ -3753,7 +3753,7 @@ if.then374:6 %zext_ln541_8 = zext i1 %tmp_48 - + - + @@ -3839,10 +3839,10 @@ if.then374:13 %br_ln583 = br void %if.end409 - + @@ -3871,7 +3871,7 @@ if.end409:5 %xor_ln901_9 = xor i1 %empty_18, i1 1 @@ -3954,12 +3954,12 @@ if.then420:3 %packed_hash_md_sidx_V_9 = partselect i8 @_ssdm_op_PartSelect.i8.i6 - + - + @@ -3971,9 +3971,9 @@ if.then420:4 %tmp_50 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_look - + @@ -3988,7 +3988,7 @@ if.then420:6 %zext_ln541_9 = zext i1 %tmp_50 - + - + @@ -4074,10 +4074,10 @@ if.then420:13 %br_ln609 = br void %if.end455 - + @@ -4106,7 +4106,7 @@ for.inc502:3 %xor_ln901_10 = xor i1 %empty_17, i1 1 @@ -4189,12 +4189,12 @@ if.then374.1:3 %packed_hash_md_sidx_V_10 = partselect i8 @_ssdm_op_PartSelect.i8 - + - + @@ -4206,9 +4206,9 @@ if.then374.1:4 %tmp_52 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -4223,7 +4223,7 @@ if.then374.1:6 %zext_ln541_10 = zext i1 %tmp_52 - + - + @@ -4309,10 +4309,10 @@ if.then374.1:13 %br_ln583 = br void %if.end409.1 - + @@ -4341,7 +4341,7 @@ if.end409.1:5 %xor_ln901_11 = xor i1 %empty_16, i1 1 @@ -4424,12 +4424,12 @@ if.then420.1:3 %packed_hash_md_sidx_V_11 = partselect i8 @_ssdm_op_PartSelect.i8 - + - + @@ -4441,9 +4441,9 @@ if.then420.1:4 %tmp_54 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -4458,7 +4458,7 @@ if.then420.1:6 %zext_ln541_11 = zext i1 %tmp_54 - + - + @@ -4544,10 +4544,10 @@ if.then420.1:13 %br_ln609 = br void %if.end455.1 - + @@ -4576,7 +4576,7 @@ for.inc502.1:3 %xor_ln901_12 = xor i1 %empty_15, i1 1 @@ -4659,12 +4659,12 @@ if.then374.2:3 %packed_hash_md_sidx_V_12 = partselect i8 @_ssdm_op_PartSelect.i8 - + - + @@ -4676,9 +4676,9 @@ if.then374.2:4 %tmp_56 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -4693,7 +4693,7 @@ if.then374.2:6 %zext_ln541_12 = zext i1 %tmp_56 - + - + @@ -4779,10 +4779,10 @@ if.then374.2:13 %br_ln583 = br void %if.end409.2 - + @@ -4811,7 +4811,7 @@ if.end409.2:5 %xor_ln901_13 = xor i1 %empty_14, i1 1 @@ -4894,12 +4894,12 @@ if.then420.2:3 %packed_hash_md_sidx_V_13 = partselect i8 @_ssdm_op_PartSelect.i8 - + - + @@ -4911,9 +4911,9 @@ if.then420.2:4 %tmp_58 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -4928,7 +4928,7 @@ if.then420.2:6 %zext_ln541_13 = zext i1 %tmp_58 - + - + @@ -5014,10 +5014,10 @@ if.then420.2:13 %br_ln609 = br void %if.end455.2 - + @@ -5046,7 +5046,7 @@ for.inc502.2:3 %xor_ln901_14 = xor i1 %empty_13, i1 1 @@ -5129,12 +5129,12 @@ if.then374.3:3 %packed_hash_md_sidx_V_14 = partselect i8 @_ssdm_op_PartSelect.i8 - + - + @@ -5146,9 +5146,9 @@ if.then374.3:4 %tmp_60 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -5163,7 +5163,7 @@ if.then374.3:6 %zext_ln541_14 = zext i1 %tmp_60 - + - + @@ -5249,10 +5249,10 @@ if.then374.3:13 %br_ln583 = br void %if.end409.3 - + @@ -5281,7 +5281,7 @@ if.end409.3:5 %xor_ln901_15 = xor i1 %empty, i1 1 @@ -5364,12 +5364,12 @@ if.then420.3:3 %packed_hash_md_sidx_V_15 = partselect i8 @_ssdm_op_PartSelect.i8 - + - + @@ -5381,9 +5381,9 @@ if.then420.3:4 %tmp_62 = bitselect i1 @_ssdm_op_BitSelect.i1.i65.i32, i65 %bv_lo - + @@ -5398,7 +5398,7 @@ if.then420.3:6 %zext_ln541_15 = zext i1 %tmp_62 - + - + @@ -5519,9 +5519,9 @@ if.then247:5 %zext_ln1514 = zext i5 %ret_V - + @@ -5667,9 +5667,9 @@ if.then280:5 %zext_ln1514_1 = zext i5 %ret_V_1 - + @@ -6115,9 +6115,9 @@ if.then247.1:5 %zext_ln1514_2 = zext i5 %ret_V_2 - + @@ -6263,9 +6263,9 @@ if.then280.1:5 %zext_ln1514_3 = zext i5 %ret_V_3 - + @@ -6711,9 +6711,9 @@ if.then247.2:5 %zext_ln1514_4 = zext i5 %ret_V_4 - + @@ -6859,9 +6859,9 @@ if.then280.2:5 %zext_ln1514_5 = zext i5 %ret_V_5 - + @@ -7009,10 +7009,10 @@ land.lhs.true320.2:0 %p_4 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1.i - + @@ -7043,7 +7043,7 @@ land.lhs.true320.2:2 %add_ln540_2 = add i32 %num_writes_4, i32 1 @@ -7060,7 +7060,7 @@ land.lhs.true320.2:3 %xor_ln535_2 = xor i1 %tmp_11, i1 1 @@ -7159,10 +7159,10 @@ land.lhs.true342.2:0 %p_5 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1.i - + @@ -7193,7 +7193,7 @@ land.lhs.true342.2:2 %add_ln549_2 = add i32 %num_writes_7, i32 1 @@ -7210,7 +7210,7 @@ land.lhs.true342.2:3 %xor_ln544_2 = xor i1 %tmp_12, i1 1 @@ -7307,9 +7307,9 @@ if.then247.3:5 %zext_ln1514_6 = zext i5 %ret_V_6 - + @@ -7455,9 +7455,9 @@ if.then280.3:5 %zext_ln1514_7 = zext i5 %ret_V_7 - + @@ -7605,10 +7605,10 @@ land.lhs.true320.3:0 %p_6 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1.i - + @@ -7639,7 +7639,7 @@ land.lhs.true320.3:2 %add_ln540_3 = add i32 %num_writes_8, i32 1 @@ -7656,7 +7656,7 @@ land.lhs.true320.3:3 %xor_ln535_3 = xor i1 %tmp_16, i1 1 @@ -7755,10 +7755,10 @@ land.lhs.true342.3:0 %p_7 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1.i - + @@ -7789,7 +7789,7 @@ land.lhs.true342.3:2 %add_ln549_3 = add i32 %num_writes_9, i32 1 @@ -7806,7 +7806,7 @@ land.lhs.true342.3:3 %xor_ln544_3 = xor i1 %tmp_17, i1 1 @@ -7903,9 +7903,9 @@ if.then374:5 %zext_ln1514_8 = zext i5 %ret_V_8 - + @@ -8051,9 +8051,9 @@ if.then420:5 %zext_ln1514_9 = zext i5 %ret_V_9 - + @@ -8201,10 +8201,10 @@ land.lhs.true462:0 %p_8 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1.i8. - + @@ -8235,7 +8235,7 @@ land.lhs.true462:2 %add_ln618 = add i32 %num_writes_10, i32 1 @@ -8252,7 +8252,7 @@ land.lhs.true462:3 %xor_ln613 = xor i1 %tmp_20, i1 1 @@ -8351,10 +8351,10 @@ land.lhs.true485:0 %p_9 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1.i8. - + @@ -8385,7 +8385,7 @@ land.lhs.true485:2 %add_ln627 = add i32 %num_writes_5, i32 1 @@ -8402,7 +8402,7 @@ land.lhs.true485:3 %xor_ln622 = xor i1 %tmp_22, i1 1 @@ -8499,9 +8499,9 @@ if.then374.1:5 %zext_ln1514_10 = zext i5 %ret_V_10 - + @@ -8647,9 +8647,9 @@ if.then420.1:5 %zext_ln1514_11 = zext i5 %ret_V_11 - + @@ -8797,10 +8797,10 @@ land.lhs.true462.1:0 %p_10 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1. - + @@ -8831,7 +8831,7 @@ land.lhs.true462.1:2 %add_ln618_1 = add i32 %num_writes_6, i32 1 @@ -8848,7 +8848,7 @@ land.lhs.true462.1:3 %xor_ln613_1 = xor i1 %tmp_25, i1 1 @@ -8947,10 +8947,10 @@ land.lhs.true485.1:0 %p_11 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1. - + @@ -8981,7 +8981,7 @@ land.lhs.true485.1:2 %add_ln627_1 = add i32 %num_writes_11, i32 1 @@ -8998,7 +8998,7 @@ land.lhs.true485.1:3 %xor_ln622_1 = xor i1 %tmp_26, i1 1 @@ -9095,9 +9095,9 @@ if.then374.2:5 %zext_ln1514_12 = zext i5 %ret_V_12 - + @@ -9243,9 +9243,9 @@ if.then420.2:5 %zext_ln1514_13 = zext i5 %ret_V_13 - + @@ -9393,10 +9393,10 @@ land.lhs.true462.2:0 %p_12 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1. - + @@ -9427,7 +9427,7 @@ land.lhs.true462.2:2 %add_ln618_2 = add i32 %num_writes_12, i32 1 @@ -9444,7 +9444,7 @@ land.lhs.true462.2:3 %xor_ln613_2 = xor i1 %tmp_30, i1 1 @@ -9543,10 +9543,10 @@ land.lhs.true485.2:0 %p_13 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1. - + @@ -9577,7 +9577,7 @@ land.lhs.true485.2:2 %add_ln627_2 = add i32 %num_writes_13, i32 1 @@ -9594,7 +9594,7 @@ land.lhs.true485.2:3 %xor_ln622_2 = xor i1 %tmp_31, i1 1 @@ -9691,9 +9691,9 @@ if.then374.3:5 %zext_ln1514_14 = zext i5 %ret_V_14 - + @@ -9839,9 +9839,9 @@ if.then420.3:5 %zext_ln1514_15 = zext i5 %ret_V_15 - + @@ -9989,10 +9989,10 @@ land.lhs.true462.3:0 %p_14 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1. - + @@ -10023,7 +10023,7 @@ land.lhs.true462.3:2 %add_ln618_3 = add i32 %num_writes_14, i32 1 @@ -10040,7 +10040,7 @@ land.lhs.true462.3:3 %xor_ln613_3 = xor i1 %tmp_35, i1 1 @@ -10139,10 +10139,10 @@ land.lhs.true485.3:0 %p_0 = bitconcatenate i34 @_ssdm_op_BitConcatenate.i34.i1.i - + @@ -10173,7 +10173,7 @@ land.lhs.true485.3:2 %add_ln627_3 = add i32 %num_writes_15, i32 1 @@ -10190,7 +10190,7 @@ land.lhs.true485.3:3 %xor_ln622_3 = xor i1 %tmp_36, i1 1 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES.verbose.sched.rpt.xml index f305b561..0e501ee9 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:51 2024 +Mon Jul 22 13:45:35 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES_csynth.xml index d0e94f0f..ea52a93d 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_Pipeline_PROCESS_QUERIES_csynth.xml @@ -665,7 +665,7 @@ ap_memory out -1 +14 address @@ -698,7 +698,7 @@ ap_memory out -1 +14 address @@ -797,7 +797,7 @@ ap_memory out -1 +14 address @@ -830,7 +830,7 @@ ap_memory out -1 +14 address @@ -929,7 +929,7 @@ ap_memory out -1 +14 address @@ -962,7 +962,7 @@ ap_memory out -1 +14 address @@ -1061,7 +1061,7 @@ ap_memory out -1 +14 address @@ -1094,7 +1094,7 @@ ap_memory out -1 +14 address @@ -1193,7 +1193,7 @@ ap_memory out -1 +14 address @@ -1226,7 +1226,7 @@ ap_memory out -1 +14 address @@ -1325,7 +1325,7 @@ ap_memory out -1 +14 address @@ -1358,7 +1358,7 @@ ap_memory out -1 +14 address @@ -1457,7 +1457,7 @@ ap_memory out -1 +14 address @@ -1490,7 +1490,7 @@ ap_memory out -1 +14 address @@ -1589,7 +1589,7 @@ ap_memory out -1 +14 address @@ -1622,7 +1622,7 @@ ap_memory out -1 +14 address diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_csynth.xml index 3a361f41..9f27557f 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/queryResult_per_hash_csynth.xml @@ -35,10 +35,10 @@ -4 -784 -3449 -4 +64 +828 +3778 +16 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_TtoS_per_hash.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_TtoS_per_hash.verbose.sched.rpt.xml index 6bda06d8..87eb8fc2 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_TtoS_per_hash.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_TtoS_per_hash.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:52 2024 +Mon Jul 22 13:45:33 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_TtoS_per_hash_Pipeline_VITIS_LOOP_473_2.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_TtoS_per_hash_Pipeline_VITIS_LOOP_473_2.verbose.sched.rpt.xml index 7fc44f45..444abe2d 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_TtoS_per_hash_Pipeline_VITIS_LOOP_473_2.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_TtoS_per_hash_Pipeline_VITIS_LOOP_473_2.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:51 2024 +Mon Jul 22 13:45:33 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash.verbose.sched.rpt.xml index f713558e..c0650da5 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:10:07 2024 +Mon Jul 22 13:45:49 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_MAIN_LOOP.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_MAIN_LOOP.sched.adb.xml index 5318cb43..6e409938 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_MAIN_LOOP.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_MAIN_LOOP.sched.adb.xml @@ -51132,7 +51132,7 @@ valid3214.exit:63 %shufbuf_valid_191 = phi i1 %shufbuf_valid_127, void %valid321 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml index da1b9115..a62de4da 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_MAIN_LOOP.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:10:06 2024 +Mon Jul 22 13:45:48 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_PEEK_EMULATOR_INIT_VITIS_LOOP_368_1.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_PEEK_EMULATOR_INIT_VITIS_LOOP_368_1.verbose.sched.rpt.xml index 8a28a14d..a50e2dd5 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_PEEK_EMULATOR_INIT_VITIS_LOOP_368_1.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/shuffle_reordering_per_hash_Pipeline_PEEK_EMULATOR_INIT_VITIS_LOOP_368_1.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:52 2024 +Mon Jul 22 13:45:33 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/workload.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/workload.verbose.sched.rpt.xml index 43b348c6..c9175253 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/workload.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/workload.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:47 2024 +Mon Jul 22 13:45:31 2024 2022.2 (Build 3670227 on Oct 13 2022) project diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous.verbose.sched.rpt.xml index f8f57c21..302fd5d8 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:49 2024 +Mon Jul 22 13:45:31 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -24,7 +24,7 @@
, min, max, min, max, min, max, Type -43, 43, 0.143 us, 0.143 us, 44, 44, no +262155, 262155, 0.873 ms, 0.873 ms, 262156, 262156, no
 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1.sched.adb.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1.sched.adb.xml index 5640ac3b..11cc32c6 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1.sched.adb.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1.sched.adb.xml @@ -71,7 +71,7 @@ - + - + @@ -416,9 +416,9 @@ newFuncRoot:22 %br_ln0 = br void %for.inc - + @@ -431,9 +431,9 @@ for.inc:0 %i_1 = load i5 %i - + @@ -512,7 +512,7 @@ for.inc:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294 @@ -525,9 +525,9 @@ for.inc:4 %empty = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 16, i6 - + @@ -861,9 +861,9 @@ for.inc.split:20 %to_store_s4_k1_V = trunc i33 %packed_outputs_stream_s4_kp1_s_r - + @@ -877,9 +877,9 @@ for.inc.split:21 %trunc_ln406 = trunc i5 %i_1 - + @@ -893,9 +893,9 @@ for.inc.split:22 %shl_ln406_2 = bitconcatenate i10 @_ssdm_op_BitConcatenate.i10. - + @@ -941,9 +941,9 @@ for.inc.split:28 %trunc_ln406_3 = partselect i58 @_ssdm_op_PartSelect.i58.i64.i3 - + diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1.verbose.sched.rpt.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1.verbose.sched.rpt.xml index 06f0f4f1..5affa344 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1.verbose.sched.rpt.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Jul 12 15:09:49 2024 +Mon Jul 22 13:45:31 2024 2022.2 (Build 3670227 on Oct 13 2022) project @@ -24,7 +24,7 @@
, min, max, min, max, min, max, Type -41, 41, 0.137 us, 0.137 us, 41, 41, no +262153, 262153, 0.873 ms, 0.873 ms, 262153, 262153, no
 @@ -35,7 +35,7 @@ Loop Name, min, max, Latency, achieved, target, Count, Pipelined -39, 39, 10, 2, 1, 16, yes +262151, 262151, 10, 2, 1, 131072, yes
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1_csynth.xml index a75a60ed..e4963528 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_Pipeline_VITIS_LOOP_395_1_csynth.xml @@ -22,21 +22,21 @@ clock cycles -41 -41 -41 -0.137 us -0.137 us -0.137 us -41 -41 +262153 +262153 +262153 +0.873 ms +0.873 ms +0.873 ms +262153 +262153 2.43 -16 -39 -129 +131072 +262151 +872962 2 10 @@ -47,8 +47,8 @@ -1298 -2480 +1324 +2497 0 0 0 diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_csynth.xml b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_csynth.xml index 664152f7..f534f863 100644 --- a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_csynth.xml +++ b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/design/generated/report/writeOutput_synchronous_csynth.xml @@ -22,22 +22,22 @@ clock cycles -43 -43 -43 -0.143 us -0.143 us -0.143 us -44 -44 +262155 +262155 +262155 +0.873 ms +0.873 ms +0.873 ms +262156 +262156 0 -6011 -11050 +6037 +11067 0 0 diff --git a/benchmarks/tapa_flow/sextans/Makefile b/benchmarks/tapa_flow/sextans/Makefile index 3933f8b5..78ead83a 100644 --- a/benchmarks/tapa_flow/sextans/Makefile +++ b/benchmarks/tapa_flow/sextans/Makefile @@ -20,15 +20,6 @@ show_groups: rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \ -o $(TEMP_DIR)/module_types.csv - - - -show_groups: - rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \ - -o $(TEMP_DIR)/module_types.csv - - - clean: rm -rf $(TEMP_DIR) *.log rm -rf .Xil .run diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/Makefile b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/Makefile deleted file mode 100644 index 5f299d36..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. -# The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. - -ROOT_DIR := $(shell git rev-parse --show-toplevel) -GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py -TEMP_DIR := $(CURDIR)/build -RS_TARGET := $(CURDIR)/$(TEMP_DIR)/dse/candidate_0/exported/impl/vitis_run_hw -TAPA_XO := $(CURDIR)/design/generated/unikernel.xo -PLATFORM := xilinx_u280_gen3x16_xdma_1_202211_1 -PART := xcu280-fsvh2892-2L-e -RUN_FILE := $(CURDIR)/run.py - -all: $(RS_TARGET) - -$(RS_TARGET):$(TAPA_XO) - rapidstream $(RUN_FILE) - - -show_groups: - rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \ - -o $(TEMP_DIR)/module_types.csv - - - -clean: - rm -rf $(TEMP_DIR) *.log - rm -rf .Xil .run - rm -rf *.exe - rm -rf .ipcache diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/README.md b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/README.md deleted file mode 100644 index 83b44056..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/README.md +++ /dev/null @@ -1,184 +0,0 @@ - - -RapidStream Logo - -# TAPA Flow: K Nearest Neighbour - -## Introduction - - -In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include: - -- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA. -- Optimize the .xo file with RapidStream to obtain an optimized .xo file. -- Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment. - -## Tutorial - -### Step 1 (Done): Generate the Xilinx Object File (`.xo`) - - -We utilize TAPA to generate the `.xo` file. If you have not installed TAPA, we've already compiled the C++ source to `.xo` using TAPA. The original C++ source files are located in [design/src](design/src). The generated `.xo` file can be found at [design/generated/unikernel.xo](design/generated/unikernel.xo). To compile C++ to `.xo` using TAPA, we use the script [design/run_tapa.sh](design/run_tapa.sh), with the detailed commands shown below. For your convenience, we have also backed up all the generated metadata by TAPA in the [design/generated](design/generated/) directory. - -```bash -WORK_DIR=generated -tapac \ - --work-dir ${WORK_DIR} \ - --top unikernel \ - --part-num xcu280-fsvh2892-2L-e \ - --clock-period 3.33 \ - -o ${WORK_DIR}/unikernel.xo \ - --connectivity config/link_config.ini \ - src/unikernel.cpp \ - 2>&1 | tee tapa.log - -``` - -### Step 2: Use Rapidstream to Optimize `.xo` Design - -The RapidStream flow conducts design space exploration and generates solutions by taking all TAPA-generated `.xo` file as the input. -The RapidStream flow for TAPA requires the following key inputs: - -- **Platform**: The Vitis platform (e.g., `xilinx_u280_gen3x16_xdma_1_202211_1`). -- **Device**: virtual device define by calling rapidstream APIs based on platform (e.g., `get_u280_vitis_device_factory`). -- **.xo file**: The `.xo` file generated by TAPA -- **Connectivity** (.ini): Include the configuration file for `v++` ([link_config.ini](design/config/link_config.ini)). -- **top_module_name**: Top module name for the kernel. -- **Clock**: All the clock and frequencies. -- **Flatten Module**: Within a design, not all modules need to be optimized. The flatten module name is the target module rapidstream will optimize. - -The Python snippet below shows how we initiate rapidstream instance to set up the rapidstream environment. - -```Python -from rapidstream import get_u280_vitis_device_factory, RapidStreamTAPA -import os - -CURR_DIR = os.path.dirname(os.path.abspath(__file__)) -INI_PATH = f"{CURR_DIR}/design/config/link_config.ini" -VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1" -XO_PATH = f"{CURR_DIR}/design/generated/unikernel.xo" -kernel_name = "unikernel" -factory = get_u280_vitis_device_factory(VITIS_PLATFORM) -rs = RapidStreamTAPA(f"{CURR_DIR}/build") -rs.set_virtual_device(factory.generate_virtual_device()) -rs.add_xo_file(XO_PATH) -rs.set_vitis_platform(VITIS_PLATFORM) -rs.set_vitis_connectivity_config(INI_PATH) -rs.set_top_module_name(kernel_name) -rs.add_clock("ap_clk", 3.33) -rs.add_flatten_targets([kernel_name]) -``` - -The HBM AXI port connection is described in [design/config/link_config.ini](design/config/link_config.ini). - -```bash -[connectivity] -sp=unikernel.in_0:HBM[0] -sp=unikernel.out_0:HBM[1] -sp=unikernel.in_1:HBM[2] -sp=unikernel.out_1:HBM[3] -sp=unikernel.in_2:HBM[4] -sp=unikernel.out_2:HBM[5] -sp=unikernel.in_3:HBM[6] -sp=unikernel.out_3:HBM[7] -sp=unikernel.in_4:HBM[8] -sp=unikernel.out_4:HBM[9] -sp=unikernel.in_5:HBM[10] -sp=unikernel.out_5:HBM[11] -sp=unikernel.in_6:HBM[12] -sp=unikernel.out_6:HBM[13] -sp=unikernel.in_7:HBM[14] -sp=unikernel.out_7:HBM[15] -sp=unikernel.in_8:HBM[17] -sp=unikernel.out_8:HBM[18] -sp=unikernel.in_9:HBM[19] -sp=unikernel.out_9:HBM[20] -sp=unikernel.in_10:HBM[21] -sp=unikernel.out_10:HBM[22] -sp=unikernel.in_11:HBM[23] -sp=unikernel.out_11:HBM[24] -``` - -As a result, it is necessary to assign the kernel ports to the appropriate slots. The Python code below demonstrates this process. For comprehensive linking details, please refer to the [design/config/link_config.ini](design/config/link_config.ini) file. - - ```Python -right_slot = "SLOT_X1Y0:SLOT_X1Y0" -left_slot = "SLOT_X0Y0:SLOT_X0Y0" -left_args = [ - "in_0", - "out_0", - "in_1", - "out_1", - "in_2", - "out_2", - "in_3", - "out_3", - "in_4", - "out_4", - "in_5", - "out_5", - "in_6", - "out_6", - "in_7", - "out_7", -] -for arg in left_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", left_slot) -right_args = [ - "in_8", - "out_8", - "in_9", - "out_9", - "in_10", - "out_10", - "in_11", - "out_11", -] -for arg in right_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", right_slot) -rs.assign_port_to_region("s_axi_control_.*", left_slot) -rs.assign_port_to_region("ap_clk", left_slot) -rs.assign_port_to_region("ap_rst_n", left_slot) -rs.assign_port_to_region("interrupt", left_slot) -``` - -For the complete detail, please refore to [./run.py](./run.py) file. Call the rapidstream by launching the command below or `make all`. - -```bash -rapidstream run.py -``` - -If everything is successful, you should at least get one optimized `.xclbin` file. - - - -### Step 3: Check the Group Module Report - - -RapidStream mandates a clear distinction between communication and computation within user designs. - -- In `Group modules`, users are tasked solely with defining inter-submodule communication. For those familiar with Vivado IP Integrator flow, crafting a Group module mirrors the process of connecting IPs in IPI. RapidStream subsequently integrates appropriate pipeline registers into these Group modules. - -- In `Leaf modules`, users retain the flexibility to implement diverse computational patterns, as RapidStream leaves these Leaf modules unchanged. - -For further details, please consult the [code style](https://docs.rapidstream-da.com/required-coding-style/) section in our Documentation. - -To generate a report on group types, execute the commands below or `run make show_groups`: - -```bash -rapidstream ../../../../common/util/get_group.py \ - -i build/passes/0-imported.json \ - -o build/module_types.csv -``` - -The module types for your design can be found in `build/module_types.csv`. Below, we list the four Group modules. In this design, `unikernel` serves as a Group module, while the other three modules are added by RapidStream. - -| Module Name | Group Type | -|:--------------------------------:|:--------------:| -| unikernel | grouped_module | -|__rs_ap_ctrl_start_ready_pipeline | grouped_module | -|__rs_ff_pipeline | grouped_module | -|__rs_hs_pipeline | grouped_module | diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/config/link_config.ini b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/config/link_config.ini deleted file mode 100644 index 5ea6616e..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/config/link_config.ini +++ /dev/null @@ -1,25 +0,0 @@ -[connectivity] -sp=unikernel.in_0:HBM[0] -sp=unikernel.out_0:HBM[1] -sp=unikernel.in_1:HBM[2] -sp=unikernel.out_1:HBM[3] -sp=unikernel.in_2:HBM[4] -sp=unikernel.out_2:HBM[5] -sp=unikernel.in_3:HBM[6] -sp=unikernel.out_3:HBM[7] -sp=unikernel.in_4:HBM[8] -sp=unikernel.out_4:HBM[9] -sp=unikernel.in_5:HBM[10] -sp=unikernel.out_5:HBM[11] -sp=unikernel.in_6:HBM[12] -sp=unikernel.out_6:HBM[13] -sp=unikernel.in_7:HBM[14] -sp=unikernel.out_7:HBM[15] -sp=unikernel.in_8:HBM[17] -sp=unikernel.out_8:HBM[18] -sp=unikernel.in_9:HBM[19] -sp=unikernel.out_9:HBM[20] -sp=unikernel.in_10:HBM[21] -sp=unikernel.out_10:HBM[22] -sp=unikernel.in_11:HBM[23] -sp=unikernel.out_11:HBM[24] diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/cpp/HEAT3D.cpp b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/cpp/HEAT3D.cpp deleted file mode 100644 index 5f6ea038..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/cpp/HEAT3D.cpp +++ /dev/null @@ -1,171 +0,0 @@ - - - #include - -#include "math.h" - - - - #include "ap_int.h" - -#include - - const int WIDTH_FACTOR = 512/32; - - - #include - -template -T HLS_REG(T in){ -#pragma HLS pipeline -#pragma HLS inline off -#pragma HLS interface port=return register - return in; -} -float HEAT3D_stencil_kernel(float in_1_0_0, float in_0_0_1, - float in_0_0_m1, float in_0_0_0, float in_0_m1_0, float in_m1_0_0, - float in_0_1_0) -{ - /* - (cal1 + cal2 + cal3 + in(0, 0, 0)) - */ - const float cal1 = ((in_1_0_0 - ((float)2 * in_0_0_0) + in_m1_0_0) / (float)8); - const float cal2 = ((in_0_1_0 - ((float)2 * in_0_0_0) + in_0_m1_0) / (float)8); - const float cal3 = ((in_0_0_1 - ((float)2 * in_0_0_0) + in_0_0_m1) / (float)8); - return (cal1 + cal2 + cal3 + in_0_0_0); -} // stencil kernel definition -void HEAT3D(tapa::istream >&in, tapa::ostream >&out, //int useless, - int iters) -{ -#pragma HLS disaggregate variable = in -#pragma HLS interface ap_fifo port = in._ -#pragma HLS aggregate variable = in._ bit -#pragma HLS interface ap_fifo port = in._peek -#pragma HLS aggregate variable = in._peek bit -void(in._.empty()); -void(in._peek.empty()); - -#pragma HLS disaggregate variable = out -#pragma HLS interface ap_fifo port = out._ -#pragma HLS aggregate variable = out._ bit -void(out._.full()); - - - ap_uint<512> in_block_m16; - hls::stream, 15> in_stream_m15_to_m2; - ap_uint<512> in_block_m1; - ap_uint<512> in_block_0; - ap_uint<512> in_block_1; - hls::stream, 15> in_stream_2_to_15; - ap_uint<512> in_block_16; - in_block_m16 = in.read(); - for (int i = 16 + -15; i < 16 + -1; i++) { - in_stream_m15_to_m2 << in.read(); - } - in_block_m1 = in.read(); - in_block_0 = in.read(); - in_block_1 = in.read(); - for (int i = 16 + 2; i < 16 + 16; i++) { - in_stream_2_to_15 << in.read(); - } - in_block_16 = in.read(); - MAJOR_LOOP: - for (int i = 0; i < 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1); i++) { -#pragma HLS pipeline II=1 - ap_uint<512> out_temp; - COMPUTE_LOOP: - for (int k = 0; k < 16; k++) { -#pragma HLS unroll - float in_1_0_0[16], in_0_0_1[16], in_0_0_m1[16], in_0_0_0[16], in_0_m1_0[16], in_m1_0_0[16], in_0_1_0[16]; -#pragma HLS array_partition variable=in_1_0_0 complete dim=0 -#pragma HLS array_partition variable=in_0_0_1 complete dim=0 -#pragma HLS array_partition variable=in_0_0_m1 complete dim=0 -#pragma HLS array_partition variable=in_0_0_0 complete dim=0 -#pragma HLS array_partition variable=in_0_m1_0 complete dim=0 -#pragma HLS array_partition variable=in_m1_0_0 complete dim=0 -#pragma HLS array_partition variable=in_0_1_0 complete dim=0 - unsigned int idx_k = k << 5; - uint32_t temp_in_1_0_0 = in_block_16.range(idx_k+31, idx_k); - in_1_0_0[k] = *((float*)(&temp_in_1_0_0)); - uint32_t temp_in_0_0_1 = (k<15)?in_block_0.range(idx_k + 63, idx_k + 32) : in_block_1.range(idx_k + -449, idx_k + -480); - in_0_0_1[k] = *((float*)(&temp_in_0_0_1)); - uint32_t temp_in_0_0_m1 = (k<1)?in_block_m1.range(idx_k + 511, idx_k + 480) : in_block_0.range(idx_k + -1, idx_k + -32); - in_0_0_m1[k] = *((float*)(&temp_in_0_0_m1)); - uint32_t temp_in_0_0_0 = in_block_0.range(idx_k+31, idx_k); - in_0_0_0[k] = *((float*)(&temp_in_0_0_0)); - uint32_t temp_in_0_m1_0 = in_block_m1.range(idx_k+31, idx_k); - in_0_m1_0[k] = *((float*)(&temp_in_0_m1_0)); - uint32_t temp_in_m1_0_0 = in_block_m16.range(idx_k+31, idx_k); - in_m1_0_0[k] = *((float*)(&temp_in_m1_0_0)); - uint32_t temp_in_0_1_0 = in_block_1.range(idx_k+31, idx_k); - in_0_1_0[k] = *((float*)(&temp_in_0_1_0)); - float result = HEAT3D_stencil_kernel(in_1_0_0[k], in_0_0_1[k], in_0_0_m1[k], in_0_0_0[k], in_0_m1_0[k], in_m1_0_0[k], in_0_1_0[k]); - out_temp.range(idx_k+31, idx_k) = *((uint32_t *)(&result)); - } - out.write(out_temp); - in_block_m16 = in_stream_m15_to_m2.read(); - in_stream_m15_to_m2 << HLS_REG(in_block_m1); - in_block_m1 = HLS_REG(in_block_0); - in_block_0 = HLS_REG(in_block_1); - in_block_1 = in_stream_2_to_15.read(); - in_stream_2_to_15 << HLS_REG(in_block_16); - unsigned int idx_in = 16 + (i + 17); - in_block_16 = HLS_REG(in.read()); - } - ap_uint<512> popout_in_stream_m15_to_m2; - for (int i = 0; i < 14; i++) { -#pragma HLS pipeline II=1 - in_stream_m15_to_m2 >> popout_in_stream_m15_to_m2; - } - ap_uint<512> popout_in_stream_2_to_15; - for (int i = 0; i < 14; i++) { -#pragma HLS pipeline II=1 - in_stream_2_to_15 >> popout_in_stream_2_to_15; - } - return; -} // stencil kernel definition -void load(tapa::async_mmap >& a, tapa::async_mmap >& b, - tapa::ostream > &stream_out, tapa::istream > &stream_in, - uint32_t iters) { -#pragma HLS inline off - unsigned int loop_bound = 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1) + 17 + 16; - for(int k_wr_req = (17 + 16), k_wr_resp = (17 + 16), k_rd_req = 0, k_rd_resp = 0; k_rd_resp < loop_bound || k_wr_resp < loop_bound; ) { - // read from a - if (k_rd_req < loop_bound && a.read_addr.try_write(k_rd_req)) { - k_rd_req++; - } - if (k_rd_resp < loop_bound && !a.read_data.empty() && !stream_out.full()) { - ap_uint<512> temp = a.read_data.read(nullptr); - stream_out.write(temp); - k_rd_resp++; - } - // write to b - if (k_wr_req < loop_bound && !b.write_addr.full() && !b.write_data.full() && !stream_in.empty()) { - b.write_addr.write(k_wr_req); - b.write_data.write(stream_in.read()); - k_wr_req++; - } - if (!b.write_resp.empty()) { - k_wr_resp += (unsigned int)(b.write_resp.read()) + 1; - } - } -} -void inter_kernel(uint64_t a, uint64_t b, - tapa::ostream > &stream_out, tapa::istream > &stream_in, - uint32_t iters); -void unikernel(uint64_t in_0, uint64_t out_0, //HBM 0 1 - uint64_t in_1, uint64_t out_1, - uint64_t in_2, uint64_t out_2, - uint64_t in_3, uint64_t out_3, - uint64_t in_4, uint64_t out_4, - uint64_t in_5, uint64_t out_5, - uint64_t in_6, uint64_t out_6, - uint64_t in_7, uint64_t out_7, - uint64_t in_8, uint64_t out_8, - uint64_t in_9, uint64_t out_9, - uint64_t in_10, uint64_t out_10, - uint64_t in_11, uint64_t out_11, - // tapa::mmap in_12, tapa::mmap out_12, - // tapa::mmap in_13, tapa::mmap out_13, - // tapa::mmap in_14, tapa::mmap out_14, - uint32_t iters); diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/cpp/inter_kernel.cpp b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/cpp/inter_kernel.cpp deleted file mode 100644 index 10749e91..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/cpp/inter_kernel.cpp +++ /dev/null @@ -1,157 +0,0 @@ - - - #include - -#include "math.h" - - - - #include "ap_int.h" - -#include - - const int WIDTH_FACTOR = 512/32; - - - #include - -template -T HLS_REG(T in){ -#pragma HLS pipeline -#pragma HLS inline off -#pragma HLS interface port=return register - return in; -} -float HEAT3D_stencil_kernel(float in_1_0_0, float in_0_0_1, - float in_0_0_m1, float in_0_0_0, float in_0_m1_0, float in_m1_0_0, - float in_0_1_0) -{ - /* - (cal1 + cal2 + cal3 + in(0, 0, 0)) - */ - const float cal1 = ((in_1_0_0 - ((float)2 * in_0_0_0) + in_m1_0_0) / (float)8); - const float cal2 = ((in_0_1_0 - ((float)2 * in_0_0_0) + in_0_m1_0) / (float)8); - const float cal3 = ((in_0_0_1 - ((float)2 * in_0_0_0) + in_0_0_m1) / (float)8); - return (cal1 + cal2 + cal3 + in_0_0_0); -} // stencil kernel definition -void HEAT3D(tapa::istream >&in, tapa::ostream >&out, //int useless, - int iters) -; // stencil kernel definition -void load(tapa::async_mmap >& a, tapa::async_mmap >& b, - tapa::ostream > &stream_out, tapa::istream > &stream_in, - uint32_t iters) { -#pragma HLS inline off - unsigned int loop_bound = 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1) + 17 + 16; - for(int k_wr_req = (17 + 16), k_wr_resp = (17 + 16), k_rd_req = 0, k_rd_resp = 0; k_rd_resp < loop_bound || k_wr_resp < loop_bound; ) { - // read from a - if (k_rd_req < loop_bound && a.read_addr.try_write(k_rd_req)) { - k_rd_req++; - } - if (k_rd_resp < loop_bound && !a.read_data.empty() && !stream_out.full()) { - ap_uint<512> temp = a.read_data.read(nullptr); - stream_out.write(temp); - k_rd_resp++; - } - // write to b - if (k_wr_req < loop_bound && !b.write_addr.full() && !b.write_data.full() && !stream_in.empty()) { - b.write_addr.write(k_wr_req); - b.write_data.write(stream_in.read()); - k_wr_req++; - } - if (!b.write_resp.empty()) { - k_wr_resp += (unsigned int)(b.write_resp.read()) + 1; - } - } -} -void inter_kernel(tapa::async_mmap >& a, tapa::async_mmap >& b, - tapa::ostream > &stream_out, tapa::istream > &stream_in, - uint32_t iters){ -#pragma HLS disaggregate variable = a -#pragma HLS interface ap_fifo port = a.read_addr._ -#pragma HLS aggregate variable = a.read_addr._ bit -#pragma HLS interface ap_fifo port = a.read_data._ -#pragma HLS aggregate variable = a.read_data._ bit -#pragma HLS interface ap_fifo port = a.write_addr._ -#pragma HLS aggregate variable = a.write_addr._ bit -#pragma HLS interface ap_fifo port = a.write_data._ -#pragma HLS aggregate variable = a.write_data._ bit -#pragma HLS interface ap_fifo port = a.write_resp._ -#pragma HLS aggregate variable = a.write_resp._ bit -#pragma HLS disaggregate variable = a .read_data -#pragma HLS interface ap_fifo port = a.read_data._peek -#pragma HLS aggregate variable = a.read_data._peek bit -#pragma HLS disaggregate variable = a .write_resp -#pragma HLS interface ap_fifo port = a.write_resp._peek -#pragma HLS aggregate variable = a.write_resp._peek bit -void(a.read_addr._.full()); -void(a.read_data._.empty()); -void(a.read_data._peek.empty()); -void(a.write_addr._.full()); -void(a.write_data._.full()); -void(a.write_resp._.empty()); -void(a.write_resp._peek.empty()); - -#pragma HLS disaggregate variable = b -#pragma HLS interface ap_fifo port = b.read_addr._ -#pragma HLS aggregate variable = b.read_addr._ bit -#pragma HLS interface ap_fifo port = b.read_data._ -#pragma HLS aggregate variable = b.read_data._ bit -#pragma HLS interface ap_fifo port = b.write_addr._ -#pragma HLS aggregate variable = b.write_addr._ bit -#pragma HLS interface ap_fifo port = b.write_data._ -#pragma HLS aggregate variable = b.write_data._ bit -#pragma HLS interface ap_fifo port = b.write_resp._ -#pragma HLS aggregate variable = b.write_resp._ bit -#pragma HLS disaggregate variable = b .read_data -#pragma HLS interface ap_fifo port = b.read_data._peek -#pragma HLS aggregate variable = b.read_data._peek bit -#pragma HLS disaggregate variable = b .write_resp -#pragma HLS interface ap_fifo port = b.write_resp._peek -#pragma HLS aggregate variable = b.write_resp._peek bit -void(b.read_addr._.full()); -void(b.read_data._.empty()); -void(b.read_data._peek.empty()); -void(b.write_addr._.full()); -void(b.write_data._.full()); -void(b.write_resp._.empty()); -void(b.write_resp._peek.empty()); - -#pragma HLS disaggregate variable = stream_out -#pragma HLS interface ap_fifo port = stream_out._ -#pragma HLS aggregate variable = stream_out._ bit -void(stream_out._.full()); - -#pragma HLS disaggregate variable = stream_in -#pragma HLS interface ap_fifo port = stream_in._ -#pragma HLS aggregate variable = stream_in._ bit -#pragma HLS interface ap_fifo port = stream_in._peek -#pragma HLS aggregate variable = stream_in._peek bit -void(stream_in._.empty()); -void(stream_in._peek.empty()); - - - for(int i = 0; i < iters; i+=1){ - if(i%(2*1)==0){ - load(a, b, stream_out, stream_in, iters); - } - else{ - load(b, a, stream_out, stream_in, iters); - } - } -} -void unikernel(uint64_t in_0, uint64_t out_0, //HBM 0 1 - uint64_t in_1, uint64_t out_1, - uint64_t in_2, uint64_t out_2, - uint64_t in_3, uint64_t out_3, - uint64_t in_4, uint64_t out_4, - uint64_t in_5, uint64_t out_5, - uint64_t in_6, uint64_t out_6, - uint64_t in_7, uint64_t out_7, - uint64_t in_8, uint64_t out_8, - uint64_t in_9, uint64_t out_9, - uint64_t in_10, uint64_t out_10, - uint64_t in_11, uint64_t out_11, - // tapa::mmap in_12, tapa::mmap out_12, - // tapa::mmap in_13, tapa::mmap out_13, - // tapa::mmap in_14, tapa::mmap out_14, - uint32_t iters); diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/cpp/unikernel.cpp b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/cpp/unikernel.cpp deleted file mode 100644 index 9e2fbe10..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/cpp/unikernel.cpp +++ /dev/null @@ -1,192 +0,0 @@ - - - #include - -#include "math.h" - - - - #include "ap_int.h" - -#include - - const int WIDTH_FACTOR = 512/32; - - - #include - -template -T HLS_REG(T in){ -#pragma HLS pipeline -#pragma HLS inline off -#pragma HLS interface port=return register - return in; -} -float HEAT3D_stencil_kernel(float in_1_0_0, float in_0_0_1, - float in_0_0_m1, float in_0_0_0, float in_0_m1_0, float in_m1_0_0, - float in_0_1_0) -{ - /* - (cal1 + cal2 + cal3 + in(0, 0, 0)) - */ - const float cal1 = ((in_1_0_0 - ((float)2 * in_0_0_0) + in_m1_0_0) / (float)8); - const float cal2 = ((in_0_1_0 - ((float)2 * in_0_0_0) + in_0_m1_0) / (float)8); - const float cal3 = ((in_0_0_1 - ((float)2 * in_0_0_0) + in_0_0_m1) / (float)8); - return (cal1 + cal2 + cal3 + in_0_0_0); -} // stencil kernel definition -void HEAT3D(tapa::istream >&in, tapa::ostream >&out, //int useless, - int iters) -; // stencil kernel definition -void load(tapa::async_mmap >& a, tapa::async_mmap >& b, - tapa::ostream > &stream_out, tapa::istream > &stream_in, - uint32_t iters) { -#pragma HLS inline off - unsigned int loop_bound = 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1) + 17 + 16; - for(int k_wr_req = (17 + 16), k_wr_resp = (17 + 16), k_rd_req = 0, k_rd_resp = 0; k_rd_resp < loop_bound || k_wr_resp < loop_bound; ) { - // read from a - if (k_rd_req < loop_bound && a.read_addr.try_write(k_rd_req)) { - k_rd_req++; - } - if (k_rd_resp < loop_bound && !a.read_data.empty() && !stream_out.full()) { - ap_uint<512> temp = a.read_data.read(nullptr); - stream_out.write(temp); - k_rd_resp++; - } - // write to b - if (k_wr_req < loop_bound && !b.write_addr.full() && !b.write_data.full() && !stream_in.empty()) { - b.write_addr.write(k_wr_req); - b.write_data.write(stream_in.read()); - k_wr_req++; - } - if (!b.write_resp.empty()) { - k_wr_resp += (unsigned int)(b.write_resp.read()) + 1; - } - } -} -void inter_kernel(uint64_t a, uint64_t b, - tapa::ostream > &stream_out, tapa::istream > &stream_in, - uint32_t iters); -extern "C" { - -void unikernel(uint64_t in_0, uint64_t out_0, //HBM 0 1 - uint64_t in_1, uint64_t out_1, - uint64_t in_2, uint64_t out_2, - uint64_t in_3, uint64_t out_3, - uint64_t in_4, uint64_t out_4, - uint64_t in_5, uint64_t out_5, - uint64_t in_6, uint64_t out_6, - uint64_t in_7, uint64_t out_7, - uint64_t in_8, uint64_t out_8, - uint64_t in_9, uint64_t out_9, - uint64_t in_10, uint64_t out_10, - uint64_t in_11, uint64_t out_11, - // tapa::mmap in_12, tapa::mmap out_12, - // tapa::mmap in_13, tapa::mmap out_13, - // tapa::mmap in_14, tapa::mmap out_14, - uint32_t iters){ - -#pragma HLS interface s_axilite port = in_0 bundle = control -{ auto val = reinterpret_cast(in_0); } -{ auto val = reinterpret_cast(in_0); } - -#pragma HLS interface s_axilite port = out_0 bundle = control -{ auto val = reinterpret_cast(out_0); } -{ auto val = reinterpret_cast(out_0); } - -#pragma HLS interface s_axilite port = in_1 bundle = control -{ auto val = reinterpret_cast(in_1); } -{ auto val = reinterpret_cast(in_1); } - -#pragma HLS interface s_axilite port = out_1 bundle = control -{ auto val = reinterpret_cast(out_1); } -{ auto val = reinterpret_cast(out_1); } - -#pragma HLS interface s_axilite port = in_2 bundle = control -{ auto val = reinterpret_cast(in_2); } -{ auto val = reinterpret_cast(in_2); } - -#pragma HLS interface s_axilite port = out_2 bundle = control -{ auto val = reinterpret_cast(out_2); } -{ auto val = reinterpret_cast(out_2); } - -#pragma HLS interface s_axilite port = in_3 bundle = control -{ auto val = reinterpret_cast(in_3); } -{ auto val = reinterpret_cast(in_3); } - -#pragma HLS interface s_axilite port = out_3 bundle = control -{ auto val = reinterpret_cast(out_3); } -{ auto val = reinterpret_cast(out_3); } - -#pragma HLS interface s_axilite port = in_4 bundle = control -{ auto val = reinterpret_cast(in_4); } -{ auto val = reinterpret_cast(in_4); } - -#pragma HLS interface s_axilite port = out_4 bundle = control -{ auto val = reinterpret_cast(out_4); } -{ auto val = reinterpret_cast(out_4); } - -#pragma HLS interface s_axilite port = in_5 bundle = control -{ auto val = reinterpret_cast(in_5); } -{ auto val = reinterpret_cast(in_5); } - -#pragma HLS interface s_axilite port = out_5 bundle = control -{ auto val = reinterpret_cast(out_5); } -{ auto val = reinterpret_cast(out_5); } - -#pragma HLS interface s_axilite port = in_6 bundle = control -{ auto val = reinterpret_cast(in_6); } -{ auto val = reinterpret_cast(in_6); } - -#pragma HLS interface s_axilite port = out_6 bundle = control -{ auto val = reinterpret_cast(out_6); } -{ auto val = reinterpret_cast(out_6); } - -#pragma HLS interface s_axilite port = in_7 bundle = control -{ auto val = reinterpret_cast(in_7); } -{ auto val = reinterpret_cast(in_7); } - -#pragma HLS interface s_axilite port = out_7 bundle = control -{ auto val = reinterpret_cast(out_7); } -{ auto val = reinterpret_cast(out_7); } - -#pragma HLS interface s_axilite port = in_8 bundle = control -{ auto val = reinterpret_cast(in_8); } -{ auto val = reinterpret_cast(in_8); } - -#pragma HLS interface s_axilite port = out_8 bundle = control -{ auto val = reinterpret_cast(out_8); } -{ auto val = reinterpret_cast(out_8); } - -#pragma HLS interface s_axilite port = in_9 bundle = control -{ auto val = reinterpret_cast(in_9); } -{ auto val = reinterpret_cast(in_9); } - -#pragma HLS interface s_axilite port = out_9 bundle = control -{ auto val = reinterpret_cast(out_9); } -{ auto val = reinterpret_cast(out_9); } - -#pragma HLS interface s_axilite port = in_10 bundle = control -{ auto val = reinterpret_cast(in_10); } -{ auto val = reinterpret_cast(in_10); } - -#pragma HLS interface s_axilite port = out_10 bundle = control -{ auto val = reinterpret_cast(out_10); } -{ auto val = reinterpret_cast(out_10); } - -#pragma HLS interface s_axilite port = in_11 bundle = control -{ auto val = reinterpret_cast(in_11); } -{ auto val = reinterpret_cast(in_11); } - -#pragma HLS interface s_axilite port = out_11 bundle = control -{ auto val = reinterpret_cast(out_11); } -{ auto val = reinterpret_cast(out_11); } - -#pragma HLS interface s_axilite port = iters bundle = control -{ auto val = reinterpret_cast(iters); } - - -#pragma HLS interface s_axilite port = return bundle = control -} - - -} // extern "C" diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/flatten/flatten-e756cccc-unikernel.cpp b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/flatten/flatten-e756cccc-unikernel.cpp deleted file mode 100644 index 5bb83bd5..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/flatten/flatten-e756cccc-unikernel.cpp +++ /dev/null @@ -1,201 +0,0 @@ - - - #include - -#include "math.h" - - - - #include "ap_int.h" - -#include - - const int WIDTH_FACTOR = 512/32; - - - #include - -template -T HLS_REG(T in){ -#pragma HLS pipeline -#pragma HLS inline off -#pragma HLS interface port=return register - return in; -} -float HEAT3D_stencil_kernel(float in_1_0_0, float in_0_0_1, - float in_0_0_m1, float in_0_0_0, float in_0_m1_0, float in_m1_0_0, - float in_0_1_0) -{ - /* - (cal1 + cal2 + cal3 + in(0, 0, 0)) - */ - const float cal1 = ((in_1_0_0 - ((float)2 * in_0_0_0) + in_m1_0_0) / (float)8); - const float cal2 = ((in_0_1_0 - ((float)2 * in_0_0_0) + in_0_m1_0) / (float)8); - const float cal3 = ((in_0_0_1 - ((float)2 * in_0_0_0) + in_0_0_m1) / (float)8); - return (cal1 + cal2 + cal3 + in_0_0_0); -} // stencil kernel definition -void HEAT3D(tapa::istream >&in, tapa::ostream >&out, //int useless, - int iters) -{ - ap_uint<512> in_block_m16; - hls::stream, 15> in_stream_m15_to_m2; - ap_uint<512> in_block_m1; - ap_uint<512> in_block_0; - ap_uint<512> in_block_1; - hls::stream, 15> in_stream_2_to_15; - ap_uint<512> in_block_16; - in_block_m16 = in.read(); - for (int i = 16 + -15; i < 16 + -1; i++) { - in_stream_m15_to_m2 << in.read(); - } - in_block_m1 = in.read(); - in_block_0 = in.read(); - in_block_1 = in.read(); - for (int i = 16 + 2; i < 16 + 16; i++) { - in_stream_2_to_15 << in.read(); - } - in_block_16 = in.read(); - MAJOR_LOOP: - for (int i = 0; i < 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1); i++) { -#pragma HLS pipeline II=1 - ap_uint<512> out_temp; - COMPUTE_LOOP: - for (int k = 0; k < 16; k++) { -#pragma HLS unroll - float in_1_0_0[16], in_0_0_1[16], in_0_0_m1[16], in_0_0_0[16], in_0_m1_0[16], in_m1_0_0[16], in_0_1_0[16]; -#pragma HLS array_partition variable=in_1_0_0 complete dim=0 -#pragma HLS array_partition variable=in_0_0_1 complete dim=0 -#pragma HLS array_partition variable=in_0_0_m1 complete dim=0 -#pragma HLS array_partition variable=in_0_0_0 complete dim=0 -#pragma HLS array_partition variable=in_0_m1_0 complete dim=0 -#pragma HLS array_partition variable=in_m1_0_0 complete dim=0 -#pragma HLS array_partition variable=in_0_1_0 complete dim=0 - unsigned int idx_k = k << 5; - uint32_t temp_in_1_0_0 = in_block_16.range(idx_k+31, idx_k); - in_1_0_0[k] = *((float*)(&temp_in_1_0_0)); - uint32_t temp_in_0_0_1 = (k<15)?in_block_0.range(idx_k + 63, idx_k + 32) : in_block_1.range(idx_k + -449, idx_k + -480); - in_0_0_1[k] = *((float*)(&temp_in_0_0_1)); - uint32_t temp_in_0_0_m1 = (k<1)?in_block_m1.range(idx_k + 511, idx_k + 480) : in_block_0.range(idx_k + -1, idx_k + -32); - in_0_0_m1[k] = *((float*)(&temp_in_0_0_m1)); - uint32_t temp_in_0_0_0 = in_block_0.range(idx_k+31, idx_k); - in_0_0_0[k] = *((float*)(&temp_in_0_0_0)); - uint32_t temp_in_0_m1_0 = in_block_m1.range(idx_k+31, idx_k); - in_0_m1_0[k] = *((float*)(&temp_in_0_m1_0)); - uint32_t temp_in_m1_0_0 = in_block_m16.range(idx_k+31, idx_k); - in_m1_0_0[k] = *((float*)(&temp_in_m1_0_0)); - uint32_t temp_in_0_1_0 = in_block_1.range(idx_k+31, idx_k); - in_0_1_0[k] = *((float*)(&temp_in_0_1_0)); - float result = HEAT3D_stencil_kernel(in_1_0_0[k], in_0_0_1[k], in_0_0_m1[k], in_0_0_0[k], in_0_m1_0[k], in_m1_0_0[k], in_0_1_0[k]); - out_temp.range(idx_k+31, idx_k) = *((uint32_t *)(&result)); - } - out.write(out_temp); - in_block_m16 = in_stream_m15_to_m2.read(); - in_stream_m15_to_m2 << HLS_REG(in_block_m1); - in_block_m1 = HLS_REG(in_block_0); - in_block_0 = HLS_REG(in_block_1); - in_block_1 = in_stream_2_to_15.read(); - in_stream_2_to_15 << HLS_REG(in_block_16); - unsigned int idx_in = 16 + (i + 17); - in_block_16 = HLS_REG(in.read()); - } - ap_uint<512> popout_in_stream_m15_to_m2; - for (int i = 0; i < 14; i++) { -#pragma HLS pipeline II=1 - in_stream_m15_to_m2 >> popout_in_stream_m15_to_m2; - } - ap_uint<512> popout_in_stream_2_to_15; - for (int i = 0; i < 14; i++) { -#pragma HLS pipeline II=1 - in_stream_2_to_15 >> popout_in_stream_2_to_15; - } - return; -} // stencil kernel definition -void load(tapa::async_mmap >& a, tapa::async_mmap >& b, - tapa::ostream > &stream_out, tapa::istream > &stream_in, - uint32_t iters) { -#pragma HLS inline off - unsigned int loop_bound = 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1) + 17 + 16; - for(int k_wr_req = (17 + 16), k_wr_resp = (17 + 16), k_rd_req = 0, k_rd_resp = 0; k_rd_resp < loop_bound || k_wr_resp < loop_bound; ) { - // read from a - if (k_rd_req < loop_bound && a.read_addr.try_write(k_rd_req)) { - k_rd_req++; - } - if (k_rd_resp < loop_bound && !a.read_data.empty() && !stream_out.full()) { - ap_uint<512> temp = a.read_data.read(nullptr); - stream_out.write(temp); - k_rd_resp++; - } - // write to b - if (k_wr_req < loop_bound && !b.write_addr.full() && !b.write_data.full() && !stream_in.empty()) { - b.write_addr.write(k_wr_req); - b.write_data.write(stream_in.read()); - k_wr_req++; - } - if (!b.write_resp.empty()) { - k_wr_resp += (unsigned int)(b.write_resp.read()) + 1; - } - } -} -void inter_kernel(tapa::async_mmap >& a, tapa::async_mmap >& b, - tapa::ostream > &stream_out, tapa::istream > &stream_in, - uint32_t iters){ - for(int i = 0; i < iters; i+=1){ - if(i%(2*1)==0){ - load(a, b, stream_out, stream_in, iters); - } - else{ - load(b, a, stream_out, stream_in, iters); - } - } -} -void unikernel(tapa::mmap > in_0, tapa::mmap > out_0, //HBM 0 1 - tapa::mmap > in_1, tapa::mmap > out_1, - tapa::mmap > in_2, tapa::mmap > out_2, - tapa::mmap > in_3, tapa::mmap > out_3, - tapa::mmap > in_4, tapa::mmap > out_4, - tapa::mmap > in_5, tapa::mmap > out_5, - tapa::mmap > in_6, tapa::mmap > out_6, - tapa::mmap > in_7, tapa::mmap > out_7, - tapa::mmap > in_8, tapa::mmap > out_8, - tapa::mmap > in_9, tapa::mmap > out_9, - tapa::mmap > in_10, tapa::mmap > out_10, - tapa::mmap > in_11, tapa::mmap > out_11, - // tapa::mmap in_12, tapa::mmap out_12, - // tapa::mmap in_13, tapa::mmap out_13, - // tapa::mmap in_14, tapa::mmap out_14, - uint32_t iters){ - tapa::streams, 15, 3> k_wr; - tapa::streams, 15, 3> k_rd; - tapa::task() - .invoke(inter_kernel, in_0, out_0, k_rd[0], k_wr[0], iters) - .invoke(HEAT3D, k_rd[0], k_wr[0], iters) - .invoke(inter_kernel, in_1, out_1, k_rd[1], k_wr[1], iters) - .invoke(HEAT3D, k_rd[1], k_wr[1], iters) - .invoke(inter_kernel, in_2, out_2, k_rd[2], k_wr[2], iters) - .invoke(HEAT3D, k_rd[2], k_wr[2], iters) - .invoke(inter_kernel, in_3, out_3, k_rd[3], k_wr[3], iters) - .invoke(HEAT3D, k_rd[3], k_wr[3], iters) - .invoke(inter_kernel, in_4, out_4, k_rd[4], k_wr[4], iters) - .invoke(HEAT3D, k_rd[4], k_wr[4], iters) - .invoke(inter_kernel, in_5, out_5, k_rd[5], k_wr[5], iters) - .invoke(HEAT3D, k_rd[5], k_wr[5], iters) - .invoke(inter_kernel, in_6, out_6, k_rd[6], k_wr[6], iters) - .invoke(HEAT3D, k_rd[6], k_wr[6], iters) - .invoke(inter_kernel, in_7, out_7, k_rd[7], k_wr[7], iters) - .invoke(HEAT3D, k_rd[7], k_wr[7], iters) - .invoke(inter_kernel, in_8, out_8, k_rd[8], k_wr[8], iters) - .invoke(HEAT3D, k_rd[8], k_wr[8], iters) - .invoke(inter_kernel, in_9, out_9, k_rd[9], k_wr[9], iters) - .invoke(HEAT3D, k_rd[9], k_wr[9], iters) - .invoke(inter_kernel, in_10, out_10, k_rd[10], k_wr[10], iters) - .invoke(HEAT3D, k_rd[10], k_wr[10], iters) - .invoke(inter_kernel, in_11, out_11, k_rd[11], k_wr[11], iters) - .invoke(HEAT3D, k_rd[11], k_wr[11], iters) - // .invoke(inter_kernel, in_12, out_12, k_rd[12], k_wr[12], iters) - // .invoke(HEAT3D, k_rd[12], k_wr[12], iters) - // .invoke(inter_kernel, in_13, out_13, k_rd[13], k_wr[13], iters) - // .invoke(HEAT3D, k_rd[13], k_wr[13], iters) - // .invoke(inter_kernel, in_14, out_14, k_rd[14], k_wr[14], iters) - // .invoke(HEAT3D, k_rd[14], k_wr[14], iters) - ; -} diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/graph.json b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/graph.json deleted file mode 100644 index 5a19a36b..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/graph.json +++ /dev/null @@ -1,959 +0,0 @@ -{ - "cflags": [ - "-std=c++17", - "-I", - "/home/ylxiao/.local/lib/python3.8/site-packages/tapa/../../../src", - "-isystem", - "/tools/Xilinx/Vitis_HLS/2022.2/include" - ], - "tasks": { - "HEAT3D": { - "code": "\n\n #include \n\n#include \"math.h\"\n\n\n\n #include \"ap_int.h\"\n\n#include \n\n const int WIDTH_FACTOR = 512/32;\n\n\n #include \n\ntemplate\nT HLS_REG(T in){\n#pragma HLS pipeline\n#pragma HLS inline off\n#pragma HLS interface port=return register\n return in;\n}\nfloat HEAT3D_stencil_kernel(float in_1_0_0, float in_0_0_1,\n float in_0_0_m1, float in_0_0_0, float in_0_m1_0, float in_m1_0_0,\n float in_0_1_0)\n{\n /*\n (cal1 + cal2 + cal3 + in(0, 0, 0))\n */\n const float cal1 = ((in_1_0_0 - ((float)2 * in_0_0_0) + in_m1_0_0) / (float)8);\n const float cal2 = ((in_0_1_0 - ((float)2 * in_0_0_0) + in_0_m1_0) / (float)8);\n const float cal3 = ((in_0_0_1 - ((float)2 * in_0_0_0) + in_0_0_m1) / (float)8);\n return (cal1 + cal2 + cal3 + in_0_0_0);\n} // stencil kernel definition\nvoid HEAT3D(tapa::istream >&in, tapa::ostream >&out, //int useless, \n int iters)\n{\n#pragma HLS disaggregate variable = in\n#pragma HLS interface ap_fifo port = in._\n#pragma HLS aggregate variable = in._ bit\n#pragma HLS interface ap_fifo port = in._peek\n#pragma HLS aggregate variable = in._peek bit\nvoid(in._.empty());\nvoid(in._peek.empty());\n\n#pragma HLS disaggregate variable = out\n#pragma HLS interface ap_fifo port = out._\n#pragma HLS aggregate variable = out._ bit\nvoid(out._.full());\n\n\n ap_uint<512> in_block_m16;\n hls::stream, 15> in_stream_m15_to_m2;\n ap_uint<512> in_block_m1;\n ap_uint<512> in_block_0;\n ap_uint<512> in_block_1;\n hls::stream, 15> in_stream_2_to_15;\n ap_uint<512> in_block_16;\n in_block_m16 = in.read();\n for (int i = 16 + -15; i < 16 + -1; i++) {\n in_stream_m15_to_m2 << in.read();\n }\n in_block_m1 = in.read();\n in_block_0 = in.read();\n in_block_1 = in.read();\n for (int i = 16 + 2; i < 16 + 16; i++) {\n in_stream_2_to_15 << in.read();\n }\n in_block_16 = in.read();\n MAJOR_LOOP:\n for (int i = 0; i < 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1); i++) {\n#pragma HLS pipeline II=1\n ap_uint<512> out_temp;\n COMPUTE_LOOP:\n for (int k = 0; k < 16; k++) {\n#pragma HLS unroll\n float in_1_0_0[16], in_0_0_1[16], in_0_0_m1[16], in_0_0_0[16], in_0_m1_0[16], in_m1_0_0[16], in_0_1_0[16];\n#pragma HLS array_partition variable=in_1_0_0 complete dim=0\n#pragma HLS array_partition variable=in_0_0_1 complete dim=0\n#pragma HLS array_partition variable=in_0_0_m1 complete dim=0\n#pragma HLS array_partition variable=in_0_0_0 complete dim=0\n#pragma HLS array_partition variable=in_0_m1_0 complete dim=0\n#pragma HLS array_partition variable=in_m1_0_0 complete dim=0\n#pragma HLS array_partition variable=in_0_1_0 complete dim=0\n unsigned int idx_k = k << 5;\n uint32_t temp_in_1_0_0 = in_block_16.range(idx_k+31, idx_k);\n in_1_0_0[k] = *((float*)(&temp_in_1_0_0));\n uint32_t temp_in_0_0_1 = (k<15)?in_block_0.range(idx_k + 63, idx_k + 32) : in_block_1.range(idx_k + -449, idx_k + -480);\n in_0_0_1[k] = *((float*)(&temp_in_0_0_1));\n uint32_t temp_in_0_0_m1 = (k<1)?in_block_m1.range(idx_k + 511, idx_k + 480) : in_block_0.range(idx_k + -1, idx_k + -32);\n in_0_0_m1[k] = *((float*)(&temp_in_0_0_m1));\n uint32_t temp_in_0_0_0 = in_block_0.range(idx_k+31, idx_k);\n in_0_0_0[k] = *((float*)(&temp_in_0_0_0));\n uint32_t temp_in_0_m1_0 = in_block_m1.range(idx_k+31, idx_k);\n in_0_m1_0[k] = *((float*)(&temp_in_0_m1_0));\n uint32_t temp_in_m1_0_0 = in_block_m16.range(idx_k+31, idx_k);\n in_m1_0_0[k] = *((float*)(&temp_in_m1_0_0));\n uint32_t temp_in_0_1_0 = in_block_1.range(idx_k+31, idx_k);\n in_0_1_0[k] = *((float*)(&temp_in_0_1_0));\n float result = HEAT3D_stencil_kernel(in_1_0_0[k], in_0_0_1[k], in_0_0_m1[k], in_0_0_0[k], in_0_m1_0[k], in_m1_0_0[k], in_0_1_0[k]);\n out_temp.range(idx_k+31, idx_k) = *((uint32_t *)(&result));\n }\n out.write(out_temp);\n in_block_m16 = in_stream_m15_to_m2.read();\n in_stream_m15_to_m2 << HLS_REG(in_block_m1);\n in_block_m1 = HLS_REG(in_block_0);\n in_block_0 = HLS_REG(in_block_1);\n in_block_1 = in_stream_2_to_15.read();\n in_stream_2_to_15 << HLS_REG(in_block_16);\n unsigned int idx_in = 16 + (i + 17);\n in_block_16 = HLS_REG(in.read());\n }\n ap_uint<512> popout_in_stream_m15_to_m2;\n for (int i = 0; i < 14; i++) {\n#pragma HLS pipeline II=1\n in_stream_m15_to_m2 >> popout_in_stream_m15_to_m2;\n }\n ap_uint<512> popout_in_stream_2_to_15;\n for (int i = 0; i < 14; i++) {\n#pragma HLS pipeline II=1\n in_stream_2_to_15 >> popout_in_stream_2_to_15;\n }\n return;\n} // stencil kernel definition\nvoid load(tapa::async_mmap >& a, tapa::async_mmap >& b,\n tapa::ostream > &stream_out, tapa::istream > &stream_in,\n uint32_t iters) {\n#pragma HLS inline off\n unsigned int loop_bound = 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1) + 17 + 16;\n for(int k_wr_req = (17 + 16), k_wr_resp = (17 + 16), k_rd_req = 0, k_rd_resp = 0; k_rd_resp < loop_bound || k_wr_resp < loop_bound; ) {\n // read from a\n if (k_rd_req < loop_bound && a.read_addr.try_write(k_rd_req)) {\n k_rd_req++;\n }\n if (k_rd_resp < loop_bound && !a.read_data.empty() && !stream_out.full()) {\n ap_uint<512> temp = a.read_data.read(nullptr);\n stream_out.write(temp);\n k_rd_resp++;\n }\n // write to b\n if (k_wr_req < loop_bound && !b.write_addr.full() && !b.write_data.full() && !stream_in.empty()) {\n b.write_addr.write(k_wr_req);\n b.write_data.write(stream_in.read());\n k_wr_req++;\n }\n if (!b.write_resp.empty()) {\n k_wr_resp += (unsigned int)(b.write_resp.read()) + 1;\n }\n }\n}\nvoid inter_kernel(uint64_t a, uint64_t b,\n tapa::ostream > &stream_out, tapa::istream > &stream_in,\n uint32_t iters);\nvoid unikernel(uint64_t in_0, uint64_t out_0, //HBM 0 1\n uint64_t in_1, uint64_t out_1,\n uint64_t in_2, uint64_t out_2,\n uint64_t in_3, uint64_t out_3,\n uint64_t in_4, uint64_t out_4,\n uint64_t in_5, uint64_t out_5,\n uint64_t in_6, uint64_t out_6,\n uint64_t in_7, uint64_t out_7,\n uint64_t in_8, uint64_t out_8,\n uint64_t in_9, uint64_t out_9,\n uint64_t in_10, uint64_t out_10,\n uint64_t in_11, uint64_t out_11,\n // tapa::mmap in_12, tapa::mmap out_12,\n // tapa::mmap in_13, tapa::mmap out_13,\n // tapa::mmap in_14, tapa::mmap out_14,\n uint32_t iters);\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "inter_kernel": { - "code": "\n\n #include \n\n#include \"math.h\"\n\n\n\n #include \"ap_int.h\"\n\n#include \n\n const int WIDTH_FACTOR = 512/32;\n\n\n #include \n\ntemplate\nT HLS_REG(T in){\n#pragma HLS pipeline\n#pragma HLS inline off\n#pragma HLS interface port=return register\n return in;\n}\nfloat HEAT3D_stencil_kernel(float in_1_0_0, float in_0_0_1,\n float in_0_0_m1, float in_0_0_0, float in_0_m1_0, float in_m1_0_0,\n float in_0_1_0)\n{\n /*\n (cal1 + cal2 + cal3 + in(0, 0, 0))\n */\n const float cal1 = ((in_1_0_0 - ((float)2 * in_0_0_0) + in_m1_0_0) / (float)8);\n const float cal2 = ((in_0_1_0 - ((float)2 * in_0_0_0) + in_0_m1_0) / (float)8);\n const float cal3 = ((in_0_0_1 - ((float)2 * in_0_0_0) + in_0_0_m1) / (float)8);\n return (cal1 + cal2 + cal3 + in_0_0_0);\n} // stencil kernel definition\nvoid HEAT3D(tapa::istream >&in, tapa::ostream >&out, //int useless, \n int iters)\n; // stencil kernel definition\nvoid load(tapa::async_mmap >& a, tapa::async_mmap >& b,\n tapa::ostream > &stream_out, tapa::istream > &stream_in,\n uint32_t iters) {\n#pragma HLS inline off\n unsigned int loop_bound = 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1) + 17 + 16;\n for(int k_wr_req = (17 + 16), k_wr_resp = (17 + 16), k_rd_req = 0, k_rd_resp = 0; k_rd_resp < loop_bound || k_wr_resp < loop_bound; ) {\n // read from a\n if (k_rd_req < loop_bound && a.read_addr.try_write(k_rd_req)) {\n k_rd_req++;\n }\n if (k_rd_resp < loop_bound && !a.read_data.empty() && !stream_out.full()) {\n ap_uint<512> temp = a.read_data.read(nullptr);\n stream_out.write(temp);\n k_rd_resp++;\n }\n // write to b\n if (k_wr_req < loop_bound && !b.write_addr.full() && !b.write_data.full() && !stream_in.empty()) {\n b.write_addr.write(k_wr_req);\n b.write_data.write(stream_in.read());\n k_wr_req++;\n }\n if (!b.write_resp.empty()) {\n k_wr_resp += (unsigned int)(b.write_resp.read()) + 1;\n }\n }\n}\nvoid inter_kernel(tapa::async_mmap >& a, tapa::async_mmap >& b,\n tapa::ostream > &stream_out, tapa::istream > &stream_in,\n uint32_t iters){\n#pragma HLS disaggregate variable = a\n#pragma HLS interface ap_fifo port = a.read_addr._\n#pragma HLS aggregate variable = a.read_addr._ bit\n#pragma HLS interface ap_fifo port = a.read_data._\n#pragma HLS aggregate variable = a.read_data._ bit\n#pragma HLS interface ap_fifo port = a.write_addr._\n#pragma HLS aggregate variable = a.write_addr._ bit\n#pragma HLS interface ap_fifo port = a.write_data._\n#pragma HLS aggregate variable = a.write_data._ bit\n#pragma HLS interface ap_fifo port = a.write_resp._\n#pragma HLS aggregate variable = a.write_resp._ bit\n#pragma HLS disaggregate variable = a .read_data\n#pragma HLS interface ap_fifo port = a.read_data._peek\n#pragma HLS aggregate variable = a.read_data._peek bit\n#pragma HLS disaggregate variable = a .write_resp\n#pragma HLS interface ap_fifo port = a.write_resp._peek\n#pragma HLS aggregate variable = a.write_resp._peek bit\nvoid(a.read_addr._.full());\nvoid(a.read_data._.empty());\nvoid(a.read_data._peek.empty());\nvoid(a.write_addr._.full());\nvoid(a.write_data._.full());\nvoid(a.write_resp._.empty());\nvoid(a.write_resp._peek.empty());\n\n#pragma HLS disaggregate variable = b\n#pragma HLS interface ap_fifo port = b.read_addr._\n#pragma HLS aggregate variable = b.read_addr._ bit\n#pragma HLS interface ap_fifo port = b.read_data._\n#pragma HLS aggregate variable = b.read_data._ bit\n#pragma HLS interface ap_fifo port = b.write_addr._\n#pragma HLS aggregate variable = b.write_addr._ bit\n#pragma HLS interface ap_fifo port = b.write_data._\n#pragma HLS aggregate variable = b.write_data._ bit\n#pragma HLS interface ap_fifo port = b.write_resp._\n#pragma HLS aggregate variable = b.write_resp._ bit\n#pragma HLS disaggregate variable = b .read_data\n#pragma HLS interface ap_fifo port = b.read_data._peek\n#pragma HLS aggregate variable = b.read_data._peek bit\n#pragma HLS disaggregate variable = b .write_resp\n#pragma HLS interface ap_fifo port = b.write_resp._peek\n#pragma HLS aggregate variable = b.write_resp._peek bit\nvoid(b.read_addr._.full());\nvoid(b.read_data._.empty());\nvoid(b.read_data._peek.empty());\nvoid(b.write_addr._.full());\nvoid(b.write_data._.full());\nvoid(b.write_resp._.empty());\nvoid(b.write_resp._peek.empty());\n\n#pragma HLS disaggregate variable = stream_out\n#pragma HLS interface ap_fifo port = stream_out._\n#pragma HLS aggregate variable = stream_out._ bit\nvoid(stream_out._.full());\n\n#pragma HLS disaggregate variable = stream_in\n#pragma HLS interface ap_fifo port = stream_in._\n#pragma HLS aggregate variable = stream_in._ bit\n#pragma HLS interface ap_fifo port = stream_in._peek\n#pragma HLS aggregate variable = stream_in._peek bit\nvoid(stream_in._.empty());\nvoid(stream_in._peek.empty());\n\n\n for(int i = 0; i < iters; i+=1){\n if(i%(2*1)==0){\n load(a, b, stream_out, stream_in, iters);\n }\n else{\n load(b, a, stream_out, stream_in, iters);\n }\n }\n}\nvoid unikernel(uint64_t in_0, uint64_t out_0, //HBM 0 1\n uint64_t in_1, uint64_t out_1,\n uint64_t in_2, uint64_t out_2,\n uint64_t in_3, uint64_t out_3,\n uint64_t in_4, uint64_t out_4,\n uint64_t in_5, uint64_t out_5,\n uint64_t in_6, uint64_t out_6,\n uint64_t in_7, uint64_t out_7,\n uint64_t in_8, uint64_t out_8,\n uint64_t in_9, uint64_t out_9,\n uint64_t in_10, uint64_t out_10,\n uint64_t in_11, uint64_t out_11,\n // tapa::mmap in_12, tapa::mmap out_12,\n // tapa::mmap in_13, tapa::mmap out_13,\n // tapa::mmap in_14, tapa::mmap out_14,\n uint32_t iters);\n", - "level": "lower", - "target": "hls", - "vendor": "xilinx" - }, - "unikernel": { - "code": "\n\n #include \n\n#include \"math.h\"\n\n\n\n #include \"ap_int.h\"\n\n#include \n\n const int WIDTH_FACTOR = 512/32;\n\n\n #include \n\ntemplate\nT HLS_REG(T in){\n#pragma HLS pipeline\n#pragma HLS inline off\n#pragma HLS interface port=return register\n return in;\n}\nfloat HEAT3D_stencil_kernel(float in_1_0_0, float in_0_0_1,\n float in_0_0_m1, float in_0_0_0, float in_0_m1_0, float in_m1_0_0,\n float in_0_1_0)\n{\n /*\n (cal1 + cal2 + cal3 + in(0, 0, 0))\n */\n const float cal1 = ((in_1_0_0 - ((float)2 * in_0_0_0) + in_m1_0_0) / (float)8);\n const float cal2 = ((in_0_1_0 - ((float)2 * in_0_0_0) + in_0_m1_0) / (float)8);\n const float cal3 = ((in_0_0_1 - ((float)2 * in_0_0_0) + in_0_0_m1) / (float)8);\n return (cal1 + cal2 + cal3 + in_0_0_0);\n} // stencil kernel definition\nvoid HEAT3D(tapa::istream >&in, tapa::ostream >&out, //int useless, \n int iters)\n; // stencil kernel definition\nvoid load(tapa::async_mmap >& a, tapa::async_mmap >& b,\n tapa::ostream > &stream_out, tapa::istream > &stream_in,\n uint32_t iters) {\n#pragma HLS inline off\n unsigned int loop_bound = 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1) + 17 + 16;\n for(int k_wr_req = (17 + 16), k_wr_resp = (17 + 16), k_rd_req = 0, k_rd_resp = 0; k_rd_resp < loop_bound || k_wr_resp < loop_bound; ) {\n // read from a\n if (k_rd_req < loop_bound && a.read_addr.try_write(k_rd_req)) {\n k_rd_req++;\n }\n if (k_rd_resp < loop_bound && !a.read_data.empty() && !stream_out.full()) {\n ap_uint<512> temp = a.read_data.read(nullptr);\n stream_out.write(temp);\n k_rd_resp++;\n }\n // write to b\n if (k_wr_req < loop_bound && !b.write_addr.full() && !b.write_data.full() && !stream_in.empty()) {\n b.write_addr.write(k_wr_req);\n b.write_data.write(stream_in.read());\n k_wr_req++;\n }\n if (!b.write_resp.empty()) {\n k_wr_resp += (unsigned int)(b.write_resp.read()) + 1;\n }\n }\n}\nvoid inter_kernel(uint64_t a, uint64_t b,\n tapa::ostream > &stream_out, tapa::istream > &stream_in,\n uint32_t iters);\nextern \"C\" {\n\nvoid unikernel(uint64_t in_0, uint64_t out_0, //HBM 0 1\n uint64_t in_1, uint64_t out_1,\n uint64_t in_2, uint64_t out_2,\n uint64_t in_3, uint64_t out_3,\n uint64_t in_4, uint64_t out_4,\n uint64_t in_5, uint64_t out_5,\n uint64_t in_6, uint64_t out_6,\n uint64_t in_7, uint64_t out_7,\n uint64_t in_8, uint64_t out_8,\n uint64_t in_9, uint64_t out_9,\n uint64_t in_10, uint64_t out_10,\n uint64_t in_11, uint64_t out_11,\n // tapa::mmap in_12, tapa::mmap out_12,\n // tapa::mmap in_13, tapa::mmap out_13,\n // tapa::mmap in_14, tapa::mmap out_14,\n uint32_t iters){\n\n#pragma HLS interface s_axilite port = in_0 bundle = control\n{ auto val = reinterpret_cast(in_0); }\n{ auto val = reinterpret_cast(in_0); }\n\n#pragma HLS interface s_axilite port = out_0 bundle = control\n{ auto val = reinterpret_cast(out_0); }\n{ auto val = reinterpret_cast(out_0); }\n\n#pragma HLS interface s_axilite port = in_1 bundle = control\n{ auto val = reinterpret_cast(in_1); }\n{ auto val = reinterpret_cast(in_1); }\n\n#pragma HLS interface s_axilite port = out_1 bundle = control\n{ auto val = reinterpret_cast(out_1); }\n{ auto val = reinterpret_cast(out_1); }\n\n#pragma HLS interface s_axilite port = in_2 bundle = control\n{ auto val = reinterpret_cast(in_2); }\n{ auto val = reinterpret_cast(in_2); }\n\n#pragma HLS interface s_axilite port = out_2 bundle = control\n{ auto val = reinterpret_cast(out_2); }\n{ auto val = reinterpret_cast(out_2); }\n\n#pragma HLS interface s_axilite port = in_3 bundle = control\n{ auto val = reinterpret_cast(in_3); }\n{ auto val = reinterpret_cast(in_3); }\n\n#pragma HLS interface s_axilite port = out_3 bundle = control\n{ auto val = reinterpret_cast(out_3); }\n{ auto val = reinterpret_cast(out_3); }\n\n#pragma HLS interface s_axilite port = in_4 bundle = control\n{ auto val = reinterpret_cast(in_4); }\n{ auto val = reinterpret_cast(in_4); }\n\n#pragma HLS interface s_axilite port = out_4 bundle = control\n{ auto val = reinterpret_cast(out_4); }\n{ auto val = reinterpret_cast(out_4); }\n\n#pragma HLS interface s_axilite port = in_5 bundle = control\n{ auto val = reinterpret_cast(in_5); }\n{ auto val = reinterpret_cast(in_5); }\n\n#pragma HLS interface s_axilite port = out_5 bundle = control\n{ auto val = reinterpret_cast(out_5); }\n{ auto val = reinterpret_cast(out_5); }\n\n#pragma HLS interface s_axilite port = in_6 bundle = control\n{ auto val = reinterpret_cast(in_6); }\n{ auto val = reinterpret_cast(in_6); }\n\n#pragma HLS interface s_axilite port = out_6 bundle = control\n{ auto val = reinterpret_cast(out_6); }\n{ auto val = reinterpret_cast(out_6); }\n\n#pragma HLS interface s_axilite port = in_7 bundle = control\n{ auto val = reinterpret_cast(in_7); }\n{ auto val = reinterpret_cast(in_7); }\n\n#pragma HLS interface s_axilite port = out_7 bundle = control\n{ auto val = reinterpret_cast(out_7); }\n{ auto val = reinterpret_cast(out_7); }\n\n#pragma HLS interface s_axilite port = in_8 bundle = control\n{ auto val = reinterpret_cast(in_8); }\n{ auto val = reinterpret_cast(in_8); }\n\n#pragma HLS interface s_axilite port = out_8 bundle = control\n{ auto val = reinterpret_cast(out_8); }\n{ auto val = reinterpret_cast(out_8); }\n\n#pragma HLS interface s_axilite port = in_9 bundle = control\n{ auto val = reinterpret_cast(in_9); }\n{ auto val = reinterpret_cast(in_9); }\n\n#pragma HLS interface s_axilite port = out_9 bundle = control\n{ auto val = reinterpret_cast(out_9); }\n{ auto val = reinterpret_cast(out_9); }\n\n#pragma HLS interface s_axilite port = in_10 bundle = control\n{ auto val = reinterpret_cast(in_10); }\n{ auto val = reinterpret_cast(in_10); }\n\n#pragma HLS interface s_axilite port = out_10 bundle = control\n{ auto val = reinterpret_cast(out_10); }\n{ auto val = reinterpret_cast(out_10); }\n\n#pragma HLS interface s_axilite port = in_11 bundle = control\n{ auto val = reinterpret_cast(in_11); }\n{ auto val = reinterpret_cast(in_11); }\n\n#pragma HLS interface s_axilite port = out_11 bundle = control\n{ auto val = reinterpret_cast(out_11); }\n{ auto val = reinterpret_cast(out_11); }\n\n#pragma HLS interface s_axilite port = iters bundle = control\n{ auto val = reinterpret_cast(iters); }\n\n\n#pragma HLS interface s_axilite port = return bundle = control\n}\n\n\n} // extern \"C\"\n\n", - "fifos": { - "k_rd_unikernel[0]": { - "consumed_by": [ - "HEAT3D", - 0 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 0 - ] - }, - "k_rd_unikernel[10]": { - "consumed_by": [ - "HEAT3D", - 10 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 10 - ] - }, - "k_rd_unikernel[11]": { - "consumed_by": [ - "HEAT3D", - 11 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 11 - ] - }, - "k_rd_unikernel[1]": { - "consumed_by": [ - "HEAT3D", - 1 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 1 - ] - }, - "k_rd_unikernel[2]": { - "consumed_by": [ - "HEAT3D", - 2 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 2 - ] - }, - "k_rd_unikernel[3]": { - "consumed_by": [ - "HEAT3D", - 3 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 3 - ] - }, - "k_rd_unikernel[4]": { - "consumed_by": [ - "HEAT3D", - 4 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 4 - ] - }, - "k_rd_unikernel[5]": { - "consumed_by": [ - "HEAT3D", - 5 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 5 - ] - }, - "k_rd_unikernel[6]": { - "consumed_by": [ - "HEAT3D", - 6 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 6 - ] - }, - "k_rd_unikernel[7]": { - "consumed_by": [ - "HEAT3D", - 7 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 7 - ] - }, - "k_rd_unikernel[8]": { - "consumed_by": [ - "HEAT3D", - 8 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 8 - ] - }, - "k_rd_unikernel[9]": { - "consumed_by": [ - "HEAT3D", - 9 - ], - "depth": 3, - "produced_by": [ - "inter_kernel", - 9 - ] - }, - "k_wr_unikernel[0]": { - "consumed_by": [ - "inter_kernel", - 0 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 0 - ] - }, - "k_wr_unikernel[10]": { - "consumed_by": [ - "inter_kernel", - 10 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 10 - ] - }, - "k_wr_unikernel[11]": { - "consumed_by": [ - "inter_kernel", - 11 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 11 - ] - }, - "k_wr_unikernel[1]": { - "consumed_by": [ - "inter_kernel", - 1 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 1 - ] - }, - "k_wr_unikernel[2]": { - "consumed_by": [ - "inter_kernel", - 2 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 2 - ] - }, - "k_wr_unikernel[3]": { - "consumed_by": [ - "inter_kernel", - 3 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 3 - ] - }, - "k_wr_unikernel[4]": { - "consumed_by": [ - "inter_kernel", - 4 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 4 - ] - }, - "k_wr_unikernel[5]": { - "consumed_by": [ - "inter_kernel", - 5 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 5 - ] - }, - "k_wr_unikernel[6]": { - "consumed_by": [ - "inter_kernel", - 6 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 6 - ] - }, - "k_wr_unikernel[7]": { - "consumed_by": [ - "inter_kernel", - 7 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 7 - ] - }, - "k_wr_unikernel[8]": { - "consumed_by": [ - "inter_kernel", - 8 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 8 - ] - }, - "k_wr_unikernel[9]": { - "consumed_by": [ - "inter_kernel", - 9 - ], - "depth": 3, - "produced_by": [ - "HEAT3D", - 9 - ] - } - }, - "frt_interface": "#include \n#include \n#include \n\n\n\n #include \n\n#include \"math.h\"\n\n\n\n #include \"ap_int.h\"\n\n#include \n\n const int WIDTH_FACTOR = 512/32;\n\n\n #include \n\ntemplate\nT HLS_REG(T in){\n#pragma HLS pipeline\n#pragma HLS inline off\n#pragma HLS interface port=return register\n return in;\n}\nfloat HEAT3D_stencil_kernel(float in_1_0_0, float in_0_0_1,\n float in_0_0_m1, float in_0_0_0, float in_0_m1_0, float in_m1_0_0,\n float in_0_1_0)\n{\n /*\n (cal1 + cal2 + cal3 + in(0, 0, 0))\n */\n const float cal1 = ((in_1_0_0 - ((float)2 * in_0_0_0) + in_m1_0_0) / (float)8);\n const float cal2 = ((in_0_1_0 - ((float)2 * in_0_0_0) + in_0_m1_0) / (float)8);\n const float cal3 = ((in_0_0_1 - ((float)2 * in_0_0_0) + in_0_0_m1) / (float)8);\n return (cal1 + cal2 + cal3 + in_0_0_0);\n} // stencil kernel definition\nvoid HEAT3D(tapa::istream >&in, tapa::ostream >&out, //int useless, \n int iters)\n; // stencil kernel definition\nvoid load(tapa::async_mmap >& a, tapa::async_mmap >& b,\n tapa::ostream > &stream_out, tapa::istream > &stream_in,\n uint32_t iters) {\n#pragma HLS inline off\n unsigned int loop_bound = 256/WIDTH_FACTOR*256 / 12 + (16 +17)*(iters-1) + 17 + 16;\n for(int k_wr_req = (17 + 16), k_wr_resp = (17 + 16), k_rd_req = 0, k_rd_resp = 0; k_rd_resp < loop_bound || k_wr_resp < loop_bound; ) {\n // read from a\n if (k_rd_req < loop_bound && a.read_addr.try_write(k_rd_req)) {\n k_rd_req++;\n }\n if (k_rd_resp < loop_bound && !a.read_data.empty() && !stream_out.full()) {\n ap_uint<512> temp = a.read_data.read(nullptr);\n stream_out.write(temp);\n k_rd_resp++;\n }\n // write to b\n if (k_wr_req < loop_bound && !b.write_addr.full() && !b.write_data.full() && !stream_in.empty()) {\n b.write_addr.write(k_wr_req);\n b.write_data.write(stream_in.read());\n k_wr_req++;\n }\n if (!b.write_resp.empty()) {\n k_wr_resp += (unsigned int)(b.write_resp.read()) + 1;\n }\n }\n}\nvoid inter_kernel(uint64_t a, uint64_t b,\n tapa::ostream > &stream_out, tapa::istream > &stream_in,\n uint32_t iters);\nvoid unikernel(tapa::mmap > in_0, tapa::mmap > out_0, //HBM 0 1\n tapa::mmap > in_1, tapa::mmap > out_1,\n tapa::mmap > in_2, tapa::mmap > out_2,\n tapa::mmap > in_3, tapa::mmap > out_3,\n tapa::mmap > in_4, tapa::mmap > out_4,\n tapa::mmap > in_5, tapa::mmap > out_5,\n tapa::mmap > in_6, tapa::mmap > out_6,\n tapa::mmap > in_7, tapa::mmap > out_7,\n tapa::mmap > in_8, tapa::mmap > out_8,\n tapa::mmap > in_9, tapa::mmap > out_9,\n tapa::mmap > in_10, tapa::mmap > out_10,\n tapa::mmap > in_11, tapa::mmap > out_11,\n // tapa::mmap in_12, tapa::mmap out_12,\n // tapa::mmap in_13, tapa::mmap out_13,\n // tapa::mmap in_14, tapa::mmap out_14,\n uint32_t iters){\n#define TAPAB_APP \"TAPAB_unikernel\"\n#define TAPAB \"TAPAB\"\n const char* _tapa_bitstream = nullptr;\n if ((_tapa_bitstream = getenv(TAPAB_APP)) ||\n (_tapa_bitstream = getenv(TAPAB))) {\n fpga::Instance _tapa_instance(_tapa_bitstream);\n int _tapa_arg_index = 0;\n for (const auto& _tapa_arg_info : _tapa_instance.GetArgsInfo()) {\n if (false) {\n } else if (_tapa_arg_info.name == \"in_0\") {\n auto _tapa_arg = fpga::ReadWrite(in_0.get(), in_0.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_0\") {\n auto _tapa_arg = fpga::ReadWrite(out_0.get(), out_0.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_1\") {\n auto _tapa_arg = fpga::ReadWrite(in_1.get(), in_1.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_1\") {\n auto _tapa_arg = fpga::ReadWrite(out_1.get(), out_1.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_2\") {\n auto _tapa_arg = fpga::ReadWrite(in_2.get(), in_2.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_2\") {\n auto _tapa_arg = fpga::ReadWrite(out_2.get(), out_2.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_3\") {\n auto _tapa_arg = fpga::ReadWrite(in_3.get(), in_3.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_3\") {\n auto _tapa_arg = fpga::ReadWrite(out_3.get(), out_3.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_4\") {\n auto _tapa_arg = fpga::ReadWrite(in_4.get(), in_4.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_4\") {\n auto _tapa_arg = fpga::ReadWrite(out_4.get(), out_4.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_5\") {\n auto _tapa_arg = fpga::ReadWrite(in_5.get(), in_5.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_5\") {\n auto _tapa_arg = fpga::ReadWrite(out_5.get(), out_5.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_6\") {\n auto _tapa_arg = fpga::ReadWrite(in_6.get(), in_6.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_6\") {\n auto _tapa_arg = fpga::ReadWrite(out_6.get(), out_6.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_7\") {\n auto _tapa_arg = fpga::ReadWrite(in_7.get(), in_7.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_7\") {\n auto _tapa_arg = fpga::ReadWrite(out_7.get(), out_7.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_8\") {\n auto _tapa_arg = fpga::ReadWrite(in_8.get(), in_8.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_8\") {\n auto _tapa_arg = fpga::ReadWrite(out_8.get(), out_8.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_9\") {\n auto _tapa_arg = fpga::ReadWrite(in_9.get(), in_9.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_9\") {\n auto _tapa_arg = fpga::ReadWrite(out_9.get(), out_9.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_10\") {\n auto _tapa_arg = fpga::ReadWrite(in_10.get(), in_10.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_10\") {\n auto _tapa_arg = fpga::ReadWrite(out_10.get(), out_10.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"in_11\") {\n auto _tapa_arg = fpga::ReadWrite(in_11.get(), in_11.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"out_11\") {\n auto _tapa_arg = fpga::ReadWrite(out_11.get(), out_11.size());\n _tapa_instance.SetArg(_tapa_arg_index, _tapa_arg);\n } else if (_tapa_arg_info.name == \"iters\") {\n _tapa_instance.SetArg(_tapa_arg_index, iters);\n } else {\n std::stringstream ss;\n ss << \"unknown argument: \" << _tapa_arg_info;\n throw std::runtime_error(ss.str());\n }\n ++_tapa_arg_index;\n }\n _tapa_instance.WriteToDevice();\n _tapa_instance.Exec();\n _tapa_instance.ReadFromDevice();\n _tapa_instance.Finish();\n } else {\n throw std::runtime_error(\"no bitstream found; please set `\" TAPAB_APP\n \"` or `\" TAPAB \"`\");\n }\n}\n", - "level": "upper", - "ports": [ - { - "cat": "mmap", - "name": "in_0", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_0", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_1", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_1", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_2", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_2", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_3", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_3", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_4", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_4", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_5", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_5", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_6", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_6", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_7", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_7", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_8", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_8", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_9", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_9", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_10", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_10", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "in_11", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "mmap", - "name": "out_11", - "type": "ap_uint<512>*", - "width": 512 - }, - { - "cat": "scalar", - "name": "iters", - "type": "uint32_t", - "width": 32 - } - ], - "target": "hls", - "tasks": { - "HEAT3D": [ - { - "args": { - "in": { - "arg": "k_rd_unikernel[0]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[0]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[1]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[1]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[2]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[2]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[3]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[3]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[4]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[4]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[5]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[5]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[6]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[6]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[7]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[7]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[8]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[8]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[9]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[9]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[10]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[10]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "in": { - "arg": "k_rd_unikernel[11]", - "cat": "istream" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "out": { - "arg": "k_wr_unikernel[11]", - "cat": "ostream" - } - }, - "step": 0 - } - ], - "inter_kernel": [ - { - "args": { - "a": { - "arg": "in_0", - "cat": "async_mmap" - }, - "b": { - "arg": "out_0", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[0]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[0]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_1", - "cat": "async_mmap" - }, - "b": { - "arg": "out_1", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[1]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[1]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_2", - "cat": "async_mmap" - }, - "b": { - "arg": "out_2", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[2]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[2]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_3", - "cat": "async_mmap" - }, - "b": { - "arg": "out_3", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[3]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[3]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_4", - "cat": "async_mmap" - }, - "b": { - "arg": "out_4", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[4]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[4]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_5", - "cat": "async_mmap" - }, - "b": { - "arg": "out_5", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[5]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[5]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_6", - "cat": "async_mmap" - }, - "b": { - "arg": "out_6", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[6]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[6]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_7", - "cat": "async_mmap" - }, - "b": { - "arg": "out_7", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[7]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[7]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_8", - "cat": "async_mmap" - }, - "b": { - "arg": "out_8", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[8]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[8]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_9", - "cat": "async_mmap" - }, - "b": { - "arg": "out_9", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[9]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[9]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_10", - "cat": "async_mmap" - }, - "b": { - "arg": "out_10", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[10]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[10]", - "cat": "ostream" - } - }, - "step": 0 - }, - { - "args": { - "a": { - "arg": "in_11", - "cat": "async_mmap" - }, - "b": { - "arg": "out_11", - "cat": "async_mmap" - }, - "iters": { - "arg": "iters", - "cat": "scalar" - }, - "stream_in": { - "arg": "k_wr_unikernel[11]", - "cat": "istream" - }, - "stream_out": { - "arg": "k_rd_unikernel[11]", - "cat": "ostream" - } - }, - "step": 0 - } - ] - }, - "vendor": "xilinx" - } - }, - "top": "unikernel" -} diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D.v deleted file mode 100644 index c75336fa..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D.v +++ /dev/null @@ -1,781 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="HEAT3D_HEAT3D,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=85918,HLS_SYN_LUT=40261,HLS_VERSION=2022_2}" *) - -module HEAT3D ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - in_s_dout, - in_s_empty_n, - in_s_read, - in_peek_dout, - in_peek_empty_n, - in_peek_read, - out_r_din, - out_r_full_n, - out_r_write, - iters -); - -parameter ap_ST_fsm_state1 = 17'd1; -parameter ap_ST_fsm_state2 = 17'd2; -parameter ap_ST_fsm_state3 = 17'd4; -parameter ap_ST_fsm_state4 = 17'd8; -parameter ap_ST_fsm_state5 = 17'd16; -parameter ap_ST_fsm_state6 = 17'd32; -parameter ap_ST_fsm_state7 = 17'd64; -parameter ap_ST_fsm_state8 = 17'd128; -parameter ap_ST_fsm_state9 = 17'd256; -parameter ap_ST_fsm_state10 = 17'd512; -parameter ap_ST_fsm_state11 = 17'd1024; -parameter ap_ST_fsm_state12 = 17'd2048; -parameter ap_ST_fsm_state13 = 17'd4096; -parameter ap_ST_fsm_state14 = 17'd8192; -parameter ap_ST_fsm_state15 = 17'd16384; -parameter ap_ST_fsm_state16 = 17'd32768; -parameter ap_ST_fsm_state17 = 17'd65536; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [512:0] in_s_dout; -input in_s_empty_n; -output in_s_read; -input [512:0] in_peek_dout; -input in_peek_empty_n; -output in_peek_read; -output [512:0] out_r_din; -input out_r_full_n; -output out_r_write; -input [31:0] iters; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg in_s_read; -reg out_r_write; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [16:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -reg in_s_blk_n; -wire ap_CS_fsm_state4; -wire ap_CS_fsm_state5; -wire ap_CS_fsm_state6; -wire ap_CS_fsm_state9; -wire [511:0] in_block_m16_V_fu_148_p1; -reg [511:0] in_block_m16_V_reg_205; -wire [511:0] in_block_m1_fu_152_p1; -reg [511:0] in_block_m1_reg_210; -wire [511:0] in_block_0_fu_156_p1; -reg [511:0] in_block_0_reg_215; -wire [511:0] in_block_1_fu_160_p1; -reg [511:0] in_block_1_reg_220; -wire [511:0] in_block_16_V_fu_164_p1; -reg [511:0] in_block_16_V_reg_225; -wire [31:0] add_ln73_fu_178_p2; -reg [31:0] add_ln73_reg_230; -wire ap_CS_fsm_state10; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_start; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_done; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_idle; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_ready; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_in_s_read; -wire [511:0] grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_in_stream_m15_to_m2_din; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_in_stream_m15_to_m2_write; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_start; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_done; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_idle; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_ready; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_in_s_read; -wire [511:0] grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_in_stream_2_to_15_din; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_in_stream_2_to_15_write; -wire grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_start; -wire grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_done; -wire grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_idle; -wire grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_ready; -wire grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_m15_to_m2_read; -wire [511:0] grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_m15_to_m2_din; -wire grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_m15_to_m2_write; -wire grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_2_to_15_read; -wire [511:0] grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_2_to_15_din; -wire grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_2_to_15_write; -wire grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_s_read; -wire [512:0] grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_out_r_din; -wire grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_out_r_write; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_start; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_done; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_idle; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_ready; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_in_stream_m15_to_m2_read; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_start; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_done; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_idle; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_ready; -wire grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_in_stream_2_to_15_read; -reg grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_start_reg; -wire ap_CS_fsm_state2; -wire ap_CS_fsm_state3; -reg [511:0] in_stream_m15_to_m2_din; -wire in_stream_m15_to_m2_full_n; -reg in_stream_m15_to_m2_write; -reg grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_start_reg; -wire ap_CS_fsm_state7; -wire ap_CS_fsm_state8; -reg [511:0] in_stream_2_to_15_din; -wire in_stream_2_to_15_full_n; -reg in_stream_2_to_15_write; -reg grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_start_reg; -wire ap_CS_fsm_state11; -wire [511:0] in_stream_m15_to_m2_dout; -wire in_stream_m15_to_m2_empty_n; -reg in_stream_m15_to_m2_read; -wire [511:0] in_stream_2_to_15_dout; -wire in_stream_2_to_15_empty_n; -reg in_stream_2_to_15_read; -reg grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_start_reg; -wire ap_CS_fsm_state13; -wire ap_CS_fsm_state14; -reg grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_start_reg; -wire ap_CS_fsm_state16; -wire ap_CS_fsm_state17; -reg ap_block_state1; -wire [31:0] add_ln73_1_fu_173_p2; -wire [31:0] shl_ln73_fu_168_p2; -reg [16:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -reg ap_ST_fsm_state4_blk; -reg ap_ST_fsm_state5_blk; -reg ap_ST_fsm_state6_blk; -wire ap_ST_fsm_state7_blk; -reg ap_ST_fsm_state8_blk; -reg ap_ST_fsm_state9_blk; -wire ap_ST_fsm_state10_blk; -reg ap_ST_fsm_state11_blk; -wire ap_ST_fsm_state12_blk; -wire ap_ST_fsm_state13_blk; -reg ap_ST_fsm_state14_blk; -wire ap_ST_fsm_state15_blk; -wire ap_ST_fsm_state16_blk; -reg ap_ST_fsm_state17_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 17'd1; -#0 grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_start_reg = 1'b0; -#0 grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_start_reg = 1'b0; -#0 grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_start_reg = 1'b0; -#0 grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_start_reg = 1'b0; -#0 grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_start_reg = 1'b0; -end - -HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_62_1 grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_start), - .ap_done(grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_done), - .ap_idle(grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_idle), - .ap_ready(grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_ready), - .in_s_dout(in_s_dout), - .in_s_empty_n(in_s_empty_n), - .in_s_read(grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_in_s_read), - .in_stream_m15_to_m2_din(grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_in_stream_m15_to_m2_din), - .in_stream_m15_to_m2_full_n(in_stream_m15_to_m2_full_n), - .in_stream_m15_to_m2_write(grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_in_stream_m15_to_m2_write) -); - -HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_68_2 grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_start), - .ap_done(grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_done), - .ap_idle(grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_idle), - .ap_ready(grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_ready), - .in_s_dout(in_s_dout), - .in_s_empty_n(in_s_empty_n), - .in_s_read(grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_in_s_read), - .in_stream_2_to_15_din(grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_in_stream_2_to_15_din), - .in_stream_2_to_15_full_n(in_stream_2_to_15_full_n), - .in_stream_2_to_15_write(grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_in_stream_2_to_15_write) -); - -HEAT3D_HEAT3D_Pipeline_MAJOR_LOOP grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_start), - .ap_done(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_done), - .ap_idle(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_idle), - .ap_ready(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_ready), - .in_stream_m15_to_m2_dout(in_stream_m15_to_m2_dout), - .in_stream_m15_to_m2_empty_n(in_stream_m15_to_m2_empty_n), - .in_stream_m15_to_m2_read(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_m15_to_m2_read), - .in_stream_m15_to_m2_din(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_m15_to_m2_din), - .in_stream_m15_to_m2_full_n(in_stream_m15_to_m2_full_n), - .in_stream_m15_to_m2_write(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_m15_to_m2_write), - .in_stream_2_to_15_dout(in_stream_2_to_15_dout), - .in_stream_2_to_15_empty_n(in_stream_2_to_15_empty_n), - .in_stream_2_to_15_read(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_2_to_15_read), - .in_stream_2_to_15_din(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_2_to_15_din), - .in_stream_2_to_15_full_n(in_stream_2_to_15_full_n), - .in_stream_2_to_15_write(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_2_to_15_write), - .in_s_dout(in_s_dout), - .in_s_empty_n(in_s_empty_n), - .in_s_read(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_s_read), - .out_r_din(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_out_r_din), - .out_r_full_n(out_r_full_n), - .out_r_write(grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_out_r_write), - .in_block_1(in_block_1_reg_220), - .in_block_m1(in_block_m1_reg_210), - .in_block_0(in_block_0_reg_215), - .in_block_16_V(in_block_16_V_reg_225), - .in_block_m16_V(in_block_m16_V_reg_205), - .add_ln73(add_ln73_reg_230) -); - -HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_116_3 grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_start), - .ap_done(grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_done), - .ap_idle(grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_idle), - .ap_ready(grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_ready), - .in_stream_m15_to_m2_dout(in_stream_m15_to_m2_dout), - .in_stream_m15_to_m2_empty_n(in_stream_m15_to_m2_empty_n), - .in_stream_m15_to_m2_read(grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_in_stream_m15_to_m2_read) -); - -HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_121_4 grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_start), - .ap_done(grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_done), - .ap_idle(grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_idle), - .ap_ready(grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_ready), - .in_stream_2_to_15_dout(in_stream_2_to_15_dout), - .in_stream_2_to_15_empty_n(in_stream_2_to_15_empty_n), - .in_stream_2_to_15_read(grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_in_stream_2_to_15_read) -); - -HEAT3D_fifo_w512_d15_A in_stream_m15_to_m2_fifo_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .if_read_ce(1'b1), - .if_write_ce(1'b1), - .if_din(in_stream_m15_to_m2_din), - .if_full_n(in_stream_m15_to_m2_full_n), - .if_write(in_stream_m15_to_m2_write), - .if_dout(in_stream_m15_to_m2_dout), - .if_empty_n(in_stream_m15_to_m2_empty_n), - .if_read(in_stream_m15_to_m2_read) -); - -HEAT3D_fifo_w512_d15_A in_stream_2_to_15_fifo_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .if_read_ce(1'b1), - .if_write_ce(1'b1), - .if_din(in_stream_2_to_15_din), - .if_full_n(in_stream_2_to_15_full_n), - .if_write(in_stream_2_to_15_write), - .if_dout(in_stream_2_to_15_dout), - .if_empty_n(in_stream_2_to_15_empty_n), - .if_read(in_stream_2_to_15_read) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state10)) begin - grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_start_reg <= 1'b1; - end else if ((grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_ready == 1'b1)) begin - grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state13)) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_start_reg <= 1'b1; - end else if ((grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_ready == 1'b1)) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state16)) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_start_reg <= 1'b1; - end else if ((grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_ready == 1'b1)) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state2)) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_start_reg <= 1'b1; - end else if ((grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_ready == 1'b1)) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state7)) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_start_reg <= 1'b1; - end else if ((grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_ready == 1'b1)) begin - grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state10)) begin - add_ln73_reg_230 <= add_ln73_fu_178_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state5)) begin - in_block_0_reg_215 <= in_block_0_fu_156_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state9)) begin - in_block_16_V_reg_225 <= in_block_16_V_fu_164_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state6)) begin - in_block_1_reg_220 <= in_block_1_fu_160_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state1)) begin - in_block_m16_V_reg_205 <= in_block_m16_V_fu_148_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state4)) begin - in_block_m1_reg_210 <= in_block_m1_fu_152_p1; - end -end - -assign ap_ST_fsm_state10_blk = 1'b0; - -always @ (*) begin - if ((grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_done == 1'b0)) begin - ap_ST_fsm_state11_blk = 1'b1; - end else begin - ap_ST_fsm_state11_blk = 1'b0; - end -end - -assign ap_ST_fsm_state12_blk = 1'b0; - -assign ap_ST_fsm_state13_blk = 1'b0; - -always @ (*) begin - if ((grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_done == 1'b0)) begin - ap_ST_fsm_state14_blk = 1'b1; - end else begin - ap_ST_fsm_state14_blk = 1'b0; - end -end - -assign ap_ST_fsm_state15_blk = 1'b0; - -assign ap_ST_fsm_state16_blk = 1'b0; - -always @ (*) begin - if ((grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_done == 1'b0)) begin - ap_ST_fsm_state17_blk = 1'b1; - end else begin - ap_ST_fsm_state17_blk = 1'b0; - end -end - -always @ (*) begin - if (((in_s_empty_n == 1'b0) | (ap_start == 1'b0))) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if ((grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_done == 1'b0)) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -always @ (*) begin - if ((in_s_empty_n == 1'b0)) begin - ap_ST_fsm_state4_blk = 1'b1; - end else begin - ap_ST_fsm_state4_blk = 1'b0; - end -end - -always @ (*) begin - if ((in_s_empty_n == 1'b0)) begin - ap_ST_fsm_state5_blk = 1'b1; - end else begin - ap_ST_fsm_state5_blk = 1'b0; - end -end - -always @ (*) begin - if ((in_s_empty_n == 1'b0)) begin - ap_ST_fsm_state6_blk = 1'b1; - end else begin - ap_ST_fsm_state6_blk = 1'b0; - end -end - -assign ap_ST_fsm_state7_blk = 1'b0; - -always @ (*) begin - if ((grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_done == 1'b0)) begin - ap_ST_fsm_state8_blk = 1'b1; - end else begin - ap_ST_fsm_state8_blk = 1'b0; - end -end - -always @ (*) begin - if ((in_s_empty_n == 1'b0)) begin - ap_ST_fsm_state9_blk = 1'b1; - end else begin - ap_ST_fsm_state9_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state17) & (grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_done == 1'b1))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state17) & (grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_done == 1'b1))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state9) | (1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state5) | (1'b1 == ap_CS_fsm_state4) | ((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1)))) begin - in_s_blk_n = in_s_empty_n; - end else begin - in_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if ((((in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state9)) | ((in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state6)) | ((in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state5)) | ((in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state4)) | (~((in_s_empty_n == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin - in_s_read = 1'b1; - end else if ((1'b1 == ap_CS_fsm_state11)) begin - in_s_read = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_s_read; - end else if ((1'b1 == ap_CS_fsm_state8)) begin - in_s_read = grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_in_s_read; - end else if ((1'b1 == ap_CS_fsm_state3)) begin - in_s_read = grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_in_s_read; - end else begin - in_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state11)) begin - in_stream_2_to_15_din = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_2_to_15_din; - end else if ((1'b1 == ap_CS_fsm_state8)) begin - in_stream_2_to_15_din = grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_in_stream_2_to_15_din; - end else begin - in_stream_2_to_15_din = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_2_to_15_din; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state17)) begin - in_stream_2_to_15_read = grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_in_stream_2_to_15_read; - end else if ((1'b1 == ap_CS_fsm_state11)) begin - in_stream_2_to_15_read = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_2_to_15_read; - end else begin - in_stream_2_to_15_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state11)) begin - in_stream_2_to_15_write = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_2_to_15_write; - end else if ((1'b1 == ap_CS_fsm_state8)) begin - in_stream_2_to_15_write = grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_in_stream_2_to_15_write; - end else begin - in_stream_2_to_15_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state11)) begin - in_stream_m15_to_m2_din = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_m15_to_m2_din; - end else if ((1'b1 == ap_CS_fsm_state3)) begin - in_stream_m15_to_m2_din = grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_in_stream_m15_to_m2_din; - end else begin - in_stream_m15_to_m2_din = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_m15_to_m2_din; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state14)) begin - in_stream_m15_to_m2_read = grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_in_stream_m15_to_m2_read; - end else if ((1'b1 == ap_CS_fsm_state11)) begin - in_stream_m15_to_m2_read = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_m15_to_m2_read; - end else begin - in_stream_m15_to_m2_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state11)) begin - in_stream_m15_to_m2_write = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_in_stream_m15_to_m2_write; - end else if ((1'b1 == ap_CS_fsm_state3)) begin - in_stream_m15_to_m2_write = grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_in_stream_m15_to_m2_write; - end else begin - in_stream_m15_to_m2_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state11)) begin - out_r_write = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_out_r_write; - end else begin - out_r_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if ((~((in_s_empty_n == 1'b0) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state3; - end - ap_ST_fsm_state3 : begin - if (((1'b1 == ap_CS_fsm_state3) & (grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_done == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state4; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - ap_ST_fsm_state4 : begin - if (((in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state4))) begin - ap_NS_fsm = ap_ST_fsm_state5; - end else begin - ap_NS_fsm = ap_ST_fsm_state4; - end - end - ap_ST_fsm_state5 : begin - if (((in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state5))) begin - ap_NS_fsm = ap_ST_fsm_state6; - end else begin - ap_NS_fsm = ap_ST_fsm_state5; - end - end - ap_ST_fsm_state6 : begin - if (((in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state6))) begin - ap_NS_fsm = ap_ST_fsm_state7; - end else begin - ap_NS_fsm = ap_ST_fsm_state6; - end - end - ap_ST_fsm_state7 : begin - ap_NS_fsm = ap_ST_fsm_state8; - end - ap_ST_fsm_state8 : begin - if (((1'b1 == ap_CS_fsm_state8) & (grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_done == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state9; - end else begin - ap_NS_fsm = ap_ST_fsm_state8; - end - end - ap_ST_fsm_state9 : begin - if (((in_s_empty_n == 1'b1) & (1'b1 == ap_CS_fsm_state9))) begin - ap_NS_fsm = ap_ST_fsm_state10; - end else begin - ap_NS_fsm = ap_ST_fsm_state9; - end - end - ap_ST_fsm_state10 : begin - ap_NS_fsm = ap_ST_fsm_state11; - end - ap_ST_fsm_state11 : begin - if (((1'b1 == ap_CS_fsm_state11) & (grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_done == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state12; - end else begin - ap_NS_fsm = ap_ST_fsm_state11; - end - end - ap_ST_fsm_state12 : begin - ap_NS_fsm = ap_ST_fsm_state13; - end - ap_ST_fsm_state13 : begin - ap_NS_fsm = ap_ST_fsm_state14; - end - ap_ST_fsm_state14 : begin - if (((1'b1 == ap_CS_fsm_state14) & (grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_done == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state15; - end else begin - ap_NS_fsm = ap_ST_fsm_state14; - end - end - ap_ST_fsm_state15 : begin - ap_NS_fsm = ap_ST_fsm_state16; - end - ap_ST_fsm_state16 : begin - ap_NS_fsm = ap_ST_fsm_state17; - end - ap_ST_fsm_state17 : begin - if (((1'b1 == ap_CS_fsm_state17) & (grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_done == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state17; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign add_ln73_1_fu_173_p2 = (iters + 32'd308); - -assign add_ln73_fu_178_p2 = (add_ln73_1_fu_173_p2 + shl_ln73_fu_168_p2); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; - -assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; - -assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; - -assign ap_CS_fsm_state14 = ap_CS_fsm[32'd13]; - -assign ap_CS_fsm_state16 = ap_CS_fsm[32'd15]; - -assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; - -assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; - -assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; - -assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; - -assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; - -assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; - -always @ (*) begin - ap_block_state1 = ((in_s_empty_n == 1'b0) | (ap_start == 1'b0)); -end - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_start = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_ap_start_reg; - -assign grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_start = grp_HEAT3D_Pipeline_VITIS_LOOP_116_3_fu_138_ap_start_reg; - -assign grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_start = grp_HEAT3D_Pipeline_VITIS_LOOP_121_4_fu_143_ap_start_reg; - -assign grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_start = grp_HEAT3D_Pipeline_VITIS_LOOP_62_1_fu_108_ap_start_reg; - -assign grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_start = grp_HEAT3D_Pipeline_VITIS_LOOP_68_2_fu_115_ap_start_reg; - -assign in_block_0_fu_156_p1 = in_s_dout[511:0]; - -assign in_block_16_V_fu_164_p1 = in_s_dout[511:0]; - -assign in_block_1_fu_160_p1 = in_s_dout[511:0]; - -assign in_block_m16_V_fu_148_p1 = in_s_dout[511:0]; - -assign in_block_m1_fu_152_p1 = in_s_dout[511:0]; - -assign in_peek_read = 1'b0; - -assign out_r_din = grp_HEAT3D_Pipeline_MAJOR_LOOP_fu_122_out_r_din; - -assign shl_ln73_fu_168_p2 = iters << 32'd5; - -endmodule //HEAT3D diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_MAJOR_LOOP.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_MAJOR_LOOP.v deleted file mode 100644 index 30808d5e..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_MAJOR_LOOP.v +++ /dev/null @@ -1,4531 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module HEAT3D_HEAT3D_Pipeline_MAJOR_LOOP ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - in_stream_m15_to_m2_dout, - in_stream_m15_to_m2_empty_n, - in_stream_m15_to_m2_read, - in_stream_m15_to_m2_din, - in_stream_m15_to_m2_full_n, - in_stream_m15_to_m2_write, - in_stream_2_to_15_dout, - in_stream_2_to_15_empty_n, - in_stream_2_to_15_read, - in_stream_2_to_15_din, - in_stream_2_to_15_full_n, - in_stream_2_to_15_write, - in_s_dout, - in_s_empty_n, - in_s_read, - out_r_din, - out_r_full_n, - out_r_write, - in_block_1, - in_block_m1, - in_block_0, - in_block_16_V, - in_block_m16_V, - add_ln73 -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [511:0] in_stream_m15_to_m2_dout; -input in_stream_m15_to_m2_empty_n; -output in_stream_m15_to_m2_read; -output [511:0] in_stream_m15_to_m2_din; -input in_stream_m15_to_m2_full_n; -output in_stream_m15_to_m2_write; -input [511:0] in_stream_2_to_15_dout; -input in_stream_2_to_15_empty_n; -output in_stream_2_to_15_read; -output [511:0] in_stream_2_to_15_din; -input in_stream_2_to_15_full_n; -output in_stream_2_to_15_write; -input [512:0] in_s_dout; -input in_s_empty_n; -output in_s_read; -output [512:0] out_r_din; -input out_r_full_n; -output out_r_write; -input [511:0] in_block_1; -input [511:0] in_block_m1; -input [511:0] in_block_0; -input [511:0] in_block_16_V; -input [511:0] in_block_m16_V; -input [31:0] add_ln73; - -reg ap_idle; -reg in_stream_m15_to_m2_read; -reg in_stream_m15_to_m2_write; -reg in_stream_2_to_15_read; -reg in_stream_2_to_15_write; -reg in_s_read; -reg out_r_write; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_enable_reg_pp0_iter2; -reg ap_enable_reg_pp0_iter3; -reg ap_enable_reg_pp0_iter4; -reg ap_enable_reg_pp0_iter5; -reg ap_enable_reg_pp0_iter6; -reg ap_enable_reg_pp0_iter7; -reg ap_enable_reg_pp0_iter8; -reg ap_enable_reg_pp0_iter9; -reg ap_enable_reg_pp0_iter10; -reg ap_enable_reg_pp0_iter11; -reg ap_enable_reg_pp0_iter12; -reg ap_enable_reg_pp0_iter13; -reg ap_enable_reg_pp0_iter14; -reg ap_enable_reg_pp0_iter15; -reg ap_enable_reg_pp0_iter16; -reg ap_enable_reg_pp0_iter17; -reg ap_enable_reg_pp0_iter18; -reg ap_enable_reg_pp0_iter19; -reg ap_enable_reg_pp0_iter20; -reg ap_enable_reg_pp0_iter21; -reg ap_enable_reg_pp0_iter22; -reg ap_enable_reg_pp0_iter23; -reg ap_enable_reg_pp0_iter24; -reg ap_enable_reg_pp0_iter25; -reg ap_enable_reg_pp0_iter26; -reg ap_enable_reg_pp0_iter27; -reg ap_enable_reg_pp0_iter28; -reg ap_enable_reg_pp0_iter29; -reg ap_enable_reg_pp0_iter30; -reg ap_enable_reg_pp0_iter31; -reg ap_enable_reg_pp0_iter32; -reg ap_enable_reg_pp0_iter33; -reg ap_enable_reg_pp0_iter34; -reg ap_enable_reg_pp0_iter35; -reg ap_enable_reg_pp0_iter36; -reg ap_enable_reg_pp0_iter37; -reg ap_enable_reg_pp0_iter38; -reg ap_enable_reg_pp0_iter39; -reg ap_enable_reg_pp0_iter40; -reg ap_enable_reg_pp0_iter41; -reg ap_enable_reg_pp0_iter42; -reg ap_enable_reg_pp0_iter43; -reg ap_enable_reg_pp0_iter44; -reg ap_enable_reg_pp0_iter45; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -reg ap_block_state2_pp0_stage0_iter1; -wire ap_block_state3_pp0_stage0_iter2; -wire ap_block_state4_pp0_stage0_iter3; -wire ap_block_state5_pp0_stage0_iter4; -wire ap_block_state6_pp0_stage0_iter5; -wire ap_block_state7_pp0_stage0_iter6; -wire ap_block_state8_pp0_stage0_iter7; -wire ap_block_state9_pp0_stage0_iter8; -wire ap_block_state10_pp0_stage0_iter9; -wire ap_block_state11_pp0_stage0_iter10; -wire ap_block_state12_pp0_stage0_iter11; -wire ap_block_state13_pp0_stage0_iter12; -wire ap_block_state14_pp0_stage0_iter13; -wire ap_block_state15_pp0_stage0_iter14; -wire ap_block_state16_pp0_stage0_iter15; -wire ap_block_state17_pp0_stage0_iter16; -wire ap_block_state18_pp0_stage0_iter17; -wire ap_block_state19_pp0_stage0_iter18; -wire ap_block_state20_pp0_stage0_iter19; -wire ap_block_state21_pp0_stage0_iter20; -wire ap_block_state22_pp0_stage0_iter21; -wire ap_block_state23_pp0_stage0_iter22; -wire ap_block_state24_pp0_stage0_iter23; -wire ap_block_state25_pp0_stage0_iter24; -wire ap_block_state26_pp0_stage0_iter25; -wire ap_block_state27_pp0_stage0_iter26; -wire ap_block_state28_pp0_stage0_iter27; -wire ap_block_state29_pp0_stage0_iter28; -wire ap_block_state30_pp0_stage0_iter29; -wire ap_block_state31_pp0_stage0_iter30; -wire ap_block_state32_pp0_stage0_iter31; -wire ap_block_state33_pp0_stage0_iter32; -wire ap_block_state34_pp0_stage0_iter33; -wire ap_block_state35_pp0_stage0_iter34; -wire ap_block_state36_pp0_stage0_iter35; -wire ap_block_state37_pp0_stage0_iter36; -wire ap_block_state38_pp0_stage0_iter37; -wire ap_block_state39_pp0_stage0_iter38; -wire ap_block_state40_pp0_stage0_iter39; -wire ap_block_state41_pp0_stage0_iter40; -wire ap_block_state42_pp0_stage0_iter41; -wire ap_block_state43_pp0_stage0_iter42; -wire ap_block_state44_pp0_stage0_iter43; -wire ap_block_state45_pp0_stage0_iter44; -reg ap_block_state46_pp0_stage0_iter45; -reg ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln73_fu_463_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -reg out_r_blk_n; -wire ap_block_pp0_stage0; -reg in_stream_m15_to_m2_i_blk_n; -reg in_stream_m15_to_m2_o_blk_n; -reg in_stream_2_to_15_i_blk_n; -reg in_stream_2_to_15_o_blk_n; -reg in_s_blk_n; -reg ap_block_pp0_stage0_11001; -wire [31:0] bitcast_ln91_fu_518_p1; -wire [31:0] bitcast_ln93_fu_535_p1; -wire [31:0] bitcast_ln95_fu_545_p1; -wire [31:0] bitcast_ln101_fu_573_p1; -wire [31:0] bitcast_ln91_1_fu_604_p1; -wire [31:0] bitcast_ln91_2_fu_681_p1; -wire [31:0] bitcast_ln91_3_fu_758_p1; -wire [31:0] bitcast_ln91_4_fu_835_p1; -wire [31:0] bitcast_ln91_5_fu_912_p1; -wire [31:0] bitcast_ln91_6_fu_989_p1; -wire [31:0] bitcast_ln91_7_fu_1066_p1; -wire [31:0] bitcast_ln91_8_fu_1143_p1; -wire [31:0] bitcast_ln91_9_fu_1220_p1; -wire [31:0] bitcast_ln91_10_fu_1297_p1; -wire [31:0] bitcast_ln91_11_fu_1374_p1; -wire [31:0] bitcast_ln91_12_fu_1451_p1; -wire [31:0] bitcast_ln91_13_fu_1528_p1; -wire [31:0] bitcast_ln91_14_fu_1605_p1; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_223_ap_return; -reg [31:0] result_reg_2296; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_234_ap_return; -reg [31:0] result_1_reg_2301; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_245_ap_return; -reg [31:0] result_2_reg_2306; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_256_ap_return; -reg [31:0] result_3_reg_2311; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_267_ap_return; -reg [31:0] result_4_reg_2316; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_278_ap_return; -reg [31:0] result_5_reg_2321; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_289_ap_return; -reg [31:0] result_6_reg_2326; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_300_ap_return; -reg [31:0] result_7_reg_2331; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_311_ap_return; -reg [31:0] result_8_reg_2336; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_322_ap_return; -reg [31:0] result_9_reg_2341; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_333_ap_return; -reg [31:0] result_10_reg_2346; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_344_ap_return; -reg [31:0] result_11_reg_2351; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_355_ap_return; -reg [31:0] result_12_reg_2356; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_366_ap_return; -reg [31:0] result_13_reg_2361; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_377_ap_return; -reg [31:0] result_14_reg_2366; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_388_ap_return; -reg [31:0] result_15_reg_2371; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_223_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_223_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_223_in_m1_0_0; -reg grp_HEAT3D_stencil_kernel_fu_223_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call21; -reg ap_block_state2_pp0_stage0_iter1_ignore_call21; -wire ap_block_state3_pp0_stage0_iter2_ignore_call21; -wire ap_block_state4_pp0_stage0_iter3_ignore_call21; -wire ap_block_state5_pp0_stage0_iter4_ignore_call21; -wire ap_block_state6_pp0_stage0_iter5_ignore_call21; -wire ap_block_state7_pp0_stage0_iter6_ignore_call21; -wire ap_block_state8_pp0_stage0_iter7_ignore_call21; -wire ap_block_state9_pp0_stage0_iter8_ignore_call21; -wire ap_block_state10_pp0_stage0_iter9_ignore_call21; -wire ap_block_state11_pp0_stage0_iter10_ignore_call21; -wire ap_block_state12_pp0_stage0_iter11_ignore_call21; -wire ap_block_state13_pp0_stage0_iter12_ignore_call21; -wire ap_block_state14_pp0_stage0_iter13_ignore_call21; -wire ap_block_state15_pp0_stage0_iter14_ignore_call21; -wire ap_block_state16_pp0_stage0_iter15_ignore_call21; -wire ap_block_state17_pp0_stage0_iter16_ignore_call21; -wire ap_block_state18_pp0_stage0_iter17_ignore_call21; -wire ap_block_state19_pp0_stage0_iter18_ignore_call21; -wire ap_block_state20_pp0_stage0_iter19_ignore_call21; -wire ap_block_state21_pp0_stage0_iter20_ignore_call21; -wire ap_block_state22_pp0_stage0_iter21_ignore_call21; -wire ap_block_state23_pp0_stage0_iter22_ignore_call21; -wire ap_block_state24_pp0_stage0_iter23_ignore_call21; -wire ap_block_state25_pp0_stage0_iter24_ignore_call21; -wire ap_block_state26_pp0_stage0_iter25_ignore_call21; -wire ap_block_state27_pp0_stage0_iter26_ignore_call21; -wire ap_block_state28_pp0_stage0_iter27_ignore_call21; -wire ap_block_state29_pp0_stage0_iter28_ignore_call21; -wire ap_block_state30_pp0_stage0_iter29_ignore_call21; -wire ap_block_state31_pp0_stage0_iter30_ignore_call21; -wire ap_block_state32_pp0_stage0_iter31_ignore_call21; -wire ap_block_state33_pp0_stage0_iter32_ignore_call21; -wire ap_block_state34_pp0_stage0_iter33_ignore_call21; -wire ap_block_state35_pp0_stage0_iter34_ignore_call21; -wire ap_block_state36_pp0_stage0_iter35_ignore_call21; -wire ap_block_state37_pp0_stage0_iter36_ignore_call21; -wire ap_block_state38_pp0_stage0_iter37_ignore_call21; -wire ap_block_state39_pp0_stage0_iter38_ignore_call21; -wire ap_block_state40_pp0_stage0_iter39_ignore_call21; -wire ap_block_state41_pp0_stage0_iter40_ignore_call21; -wire ap_block_state42_pp0_stage0_iter41_ignore_call21; -wire ap_block_state43_pp0_stage0_iter42_ignore_call21; -wire ap_block_state44_pp0_stage0_iter43_ignore_call21; -wire ap_block_state45_pp0_stage0_iter44_ignore_call21; -reg ap_block_state46_pp0_stage0_iter45_ignore_call21; -reg ap_block_pp0_stage0_11001_ignoreCallOp97; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_234_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_234_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_234_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_234_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_234_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call33; -reg ap_block_state2_pp0_stage0_iter1_ignore_call33; -wire ap_block_state3_pp0_stage0_iter2_ignore_call33; -wire ap_block_state4_pp0_stage0_iter3_ignore_call33; -wire ap_block_state5_pp0_stage0_iter4_ignore_call33; -wire ap_block_state6_pp0_stage0_iter5_ignore_call33; -wire ap_block_state7_pp0_stage0_iter6_ignore_call33; -wire ap_block_state8_pp0_stage0_iter7_ignore_call33; -wire ap_block_state9_pp0_stage0_iter8_ignore_call33; -wire ap_block_state10_pp0_stage0_iter9_ignore_call33; -wire ap_block_state11_pp0_stage0_iter10_ignore_call33; -wire ap_block_state12_pp0_stage0_iter11_ignore_call33; -wire ap_block_state13_pp0_stage0_iter12_ignore_call33; -wire ap_block_state14_pp0_stage0_iter13_ignore_call33; -wire ap_block_state15_pp0_stage0_iter14_ignore_call33; -wire ap_block_state16_pp0_stage0_iter15_ignore_call33; -wire ap_block_state17_pp0_stage0_iter16_ignore_call33; -wire ap_block_state18_pp0_stage0_iter17_ignore_call33; -wire ap_block_state19_pp0_stage0_iter18_ignore_call33; -wire ap_block_state20_pp0_stage0_iter19_ignore_call33; -wire ap_block_state21_pp0_stage0_iter20_ignore_call33; -wire ap_block_state22_pp0_stage0_iter21_ignore_call33; -wire ap_block_state23_pp0_stage0_iter22_ignore_call33; -wire ap_block_state24_pp0_stage0_iter23_ignore_call33; -wire ap_block_state25_pp0_stage0_iter24_ignore_call33; -wire ap_block_state26_pp0_stage0_iter25_ignore_call33; -wire ap_block_state27_pp0_stage0_iter26_ignore_call33; -wire ap_block_state28_pp0_stage0_iter27_ignore_call33; -wire ap_block_state29_pp0_stage0_iter28_ignore_call33; -wire ap_block_state30_pp0_stage0_iter29_ignore_call33; -wire ap_block_state31_pp0_stage0_iter30_ignore_call33; -wire ap_block_state32_pp0_stage0_iter31_ignore_call33; -wire ap_block_state33_pp0_stage0_iter32_ignore_call33; -wire ap_block_state34_pp0_stage0_iter33_ignore_call33; -wire ap_block_state35_pp0_stage0_iter34_ignore_call33; -wire ap_block_state36_pp0_stage0_iter35_ignore_call33; -wire ap_block_state37_pp0_stage0_iter36_ignore_call33; -wire ap_block_state38_pp0_stage0_iter37_ignore_call33; -wire ap_block_state39_pp0_stage0_iter38_ignore_call33; -wire ap_block_state40_pp0_stage0_iter39_ignore_call33; -wire ap_block_state41_pp0_stage0_iter40_ignore_call33; -wire ap_block_state42_pp0_stage0_iter41_ignore_call33; -wire ap_block_state43_pp0_stage0_iter42_ignore_call33; -wire ap_block_state44_pp0_stage0_iter43_ignore_call33; -wire ap_block_state45_pp0_stage0_iter44_ignore_call33; -reg ap_block_state46_pp0_stage0_iter45_ignore_call33; -reg ap_block_pp0_stage0_11001_ignoreCallOp108; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_245_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_245_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_245_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_245_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_245_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call45; -reg ap_block_state2_pp0_stage0_iter1_ignore_call45; -wire ap_block_state3_pp0_stage0_iter2_ignore_call45; -wire ap_block_state4_pp0_stage0_iter3_ignore_call45; -wire ap_block_state5_pp0_stage0_iter4_ignore_call45; -wire ap_block_state6_pp0_stage0_iter5_ignore_call45; -wire ap_block_state7_pp0_stage0_iter6_ignore_call45; -wire ap_block_state8_pp0_stage0_iter7_ignore_call45; -wire ap_block_state9_pp0_stage0_iter8_ignore_call45; -wire ap_block_state10_pp0_stage0_iter9_ignore_call45; -wire ap_block_state11_pp0_stage0_iter10_ignore_call45; -wire ap_block_state12_pp0_stage0_iter11_ignore_call45; -wire ap_block_state13_pp0_stage0_iter12_ignore_call45; -wire ap_block_state14_pp0_stage0_iter13_ignore_call45; -wire ap_block_state15_pp0_stage0_iter14_ignore_call45; -wire ap_block_state16_pp0_stage0_iter15_ignore_call45; -wire ap_block_state17_pp0_stage0_iter16_ignore_call45; -wire ap_block_state18_pp0_stage0_iter17_ignore_call45; -wire ap_block_state19_pp0_stage0_iter18_ignore_call45; -wire ap_block_state20_pp0_stage0_iter19_ignore_call45; -wire ap_block_state21_pp0_stage0_iter20_ignore_call45; -wire ap_block_state22_pp0_stage0_iter21_ignore_call45; -wire ap_block_state23_pp0_stage0_iter22_ignore_call45; -wire ap_block_state24_pp0_stage0_iter23_ignore_call45; -wire ap_block_state25_pp0_stage0_iter24_ignore_call45; -wire ap_block_state26_pp0_stage0_iter25_ignore_call45; -wire ap_block_state27_pp0_stage0_iter26_ignore_call45; -wire ap_block_state28_pp0_stage0_iter27_ignore_call45; -wire ap_block_state29_pp0_stage0_iter28_ignore_call45; -wire ap_block_state30_pp0_stage0_iter29_ignore_call45; -wire ap_block_state31_pp0_stage0_iter30_ignore_call45; -wire ap_block_state32_pp0_stage0_iter31_ignore_call45; -wire ap_block_state33_pp0_stage0_iter32_ignore_call45; -wire ap_block_state34_pp0_stage0_iter33_ignore_call45; -wire ap_block_state35_pp0_stage0_iter34_ignore_call45; -wire ap_block_state36_pp0_stage0_iter35_ignore_call45; -wire ap_block_state37_pp0_stage0_iter36_ignore_call45; -wire ap_block_state38_pp0_stage0_iter37_ignore_call45; -wire ap_block_state39_pp0_stage0_iter38_ignore_call45; -wire ap_block_state40_pp0_stage0_iter39_ignore_call45; -wire ap_block_state41_pp0_stage0_iter40_ignore_call45; -wire ap_block_state42_pp0_stage0_iter41_ignore_call45; -wire ap_block_state43_pp0_stage0_iter42_ignore_call45; -wire ap_block_state44_pp0_stage0_iter43_ignore_call45; -wire ap_block_state45_pp0_stage0_iter44_ignore_call45; -reg ap_block_state46_pp0_stage0_iter45_ignore_call45; -reg ap_block_pp0_stage0_11001_ignoreCallOp119; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_256_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_256_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_256_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_256_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_256_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call57; -reg ap_block_state2_pp0_stage0_iter1_ignore_call57; -wire ap_block_state3_pp0_stage0_iter2_ignore_call57; -wire ap_block_state4_pp0_stage0_iter3_ignore_call57; -wire ap_block_state5_pp0_stage0_iter4_ignore_call57; -wire ap_block_state6_pp0_stage0_iter5_ignore_call57; -wire ap_block_state7_pp0_stage0_iter6_ignore_call57; -wire ap_block_state8_pp0_stage0_iter7_ignore_call57; -wire ap_block_state9_pp0_stage0_iter8_ignore_call57; -wire ap_block_state10_pp0_stage0_iter9_ignore_call57; -wire ap_block_state11_pp0_stage0_iter10_ignore_call57; -wire ap_block_state12_pp0_stage0_iter11_ignore_call57; -wire ap_block_state13_pp0_stage0_iter12_ignore_call57; -wire ap_block_state14_pp0_stage0_iter13_ignore_call57; -wire ap_block_state15_pp0_stage0_iter14_ignore_call57; -wire ap_block_state16_pp0_stage0_iter15_ignore_call57; -wire ap_block_state17_pp0_stage0_iter16_ignore_call57; -wire ap_block_state18_pp0_stage0_iter17_ignore_call57; -wire ap_block_state19_pp0_stage0_iter18_ignore_call57; -wire ap_block_state20_pp0_stage0_iter19_ignore_call57; -wire ap_block_state21_pp0_stage0_iter20_ignore_call57; -wire ap_block_state22_pp0_stage0_iter21_ignore_call57; -wire ap_block_state23_pp0_stage0_iter22_ignore_call57; -wire ap_block_state24_pp0_stage0_iter23_ignore_call57; -wire ap_block_state25_pp0_stage0_iter24_ignore_call57; -wire ap_block_state26_pp0_stage0_iter25_ignore_call57; -wire ap_block_state27_pp0_stage0_iter26_ignore_call57; -wire ap_block_state28_pp0_stage0_iter27_ignore_call57; -wire ap_block_state29_pp0_stage0_iter28_ignore_call57; -wire ap_block_state30_pp0_stage0_iter29_ignore_call57; -wire ap_block_state31_pp0_stage0_iter30_ignore_call57; -wire ap_block_state32_pp0_stage0_iter31_ignore_call57; -wire ap_block_state33_pp0_stage0_iter32_ignore_call57; -wire ap_block_state34_pp0_stage0_iter33_ignore_call57; -wire ap_block_state35_pp0_stage0_iter34_ignore_call57; -wire ap_block_state36_pp0_stage0_iter35_ignore_call57; -wire ap_block_state37_pp0_stage0_iter36_ignore_call57; -wire ap_block_state38_pp0_stage0_iter37_ignore_call57; -wire ap_block_state39_pp0_stage0_iter38_ignore_call57; -wire ap_block_state40_pp0_stage0_iter39_ignore_call57; -wire ap_block_state41_pp0_stage0_iter40_ignore_call57; -wire ap_block_state42_pp0_stage0_iter41_ignore_call57; -wire ap_block_state43_pp0_stage0_iter42_ignore_call57; -wire ap_block_state44_pp0_stage0_iter43_ignore_call57; -wire ap_block_state45_pp0_stage0_iter44_ignore_call57; -reg ap_block_state46_pp0_stage0_iter45_ignore_call57; -reg ap_block_pp0_stage0_11001_ignoreCallOp130; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_267_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_267_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_267_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_267_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_267_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call69; -reg ap_block_state2_pp0_stage0_iter1_ignore_call69; -wire ap_block_state3_pp0_stage0_iter2_ignore_call69; -wire ap_block_state4_pp0_stage0_iter3_ignore_call69; -wire ap_block_state5_pp0_stage0_iter4_ignore_call69; -wire ap_block_state6_pp0_stage0_iter5_ignore_call69; -wire ap_block_state7_pp0_stage0_iter6_ignore_call69; -wire ap_block_state8_pp0_stage0_iter7_ignore_call69; -wire ap_block_state9_pp0_stage0_iter8_ignore_call69; -wire ap_block_state10_pp0_stage0_iter9_ignore_call69; -wire ap_block_state11_pp0_stage0_iter10_ignore_call69; -wire ap_block_state12_pp0_stage0_iter11_ignore_call69; -wire ap_block_state13_pp0_stage0_iter12_ignore_call69; -wire ap_block_state14_pp0_stage0_iter13_ignore_call69; -wire ap_block_state15_pp0_stage0_iter14_ignore_call69; -wire ap_block_state16_pp0_stage0_iter15_ignore_call69; -wire ap_block_state17_pp0_stage0_iter16_ignore_call69; -wire ap_block_state18_pp0_stage0_iter17_ignore_call69; -wire ap_block_state19_pp0_stage0_iter18_ignore_call69; -wire ap_block_state20_pp0_stage0_iter19_ignore_call69; -wire ap_block_state21_pp0_stage0_iter20_ignore_call69; -wire ap_block_state22_pp0_stage0_iter21_ignore_call69; -wire ap_block_state23_pp0_stage0_iter22_ignore_call69; -wire ap_block_state24_pp0_stage0_iter23_ignore_call69; -wire ap_block_state25_pp0_stage0_iter24_ignore_call69; -wire ap_block_state26_pp0_stage0_iter25_ignore_call69; -wire ap_block_state27_pp0_stage0_iter26_ignore_call69; -wire ap_block_state28_pp0_stage0_iter27_ignore_call69; -wire ap_block_state29_pp0_stage0_iter28_ignore_call69; -wire ap_block_state30_pp0_stage0_iter29_ignore_call69; -wire ap_block_state31_pp0_stage0_iter30_ignore_call69; -wire ap_block_state32_pp0_stage0_iter31_ignore_call69; -wire ap_block_state33_pp0_stage0_iter32_ignore_call69; -wire ap_block_state34_pp0_stage0_iter33_ignore_call69; -wire ap_block_state35_pp0_stage0_iter34_ignore_call69; -wire ap_block_state36_pp0_stage0_iter35_ignore_call69; -wire ap_block_state37_pp0_stage0_iter36_ignore_call69; -wire ap_block_state38_pp0_stage0_iter37_ignore_call69; -wire ap_block_state39_pp0_stage0_iter38_ignore_call69; -wire ap_block_state40_pp0_stage0_iter39_ignore_call69; -wire ap_block_state41_pp0_stage0_iter40_ignore_call69; -wire ap_block_state42_pp0_stage0_iter41_ignore_call69; -wire ap_block_state43_pp0_stage0_iter42_ignore_call69; -wire ap_block_state44_pp0_stage0_iter43_ignore_call69; -wire ap_block_state45_pp0_stage0_iter44_ignore_call69; -reg ap_block_state46_pp0_stage0_iter45_ignore_call69; -reg ap_block_pp0_stage0_11001_ignoreCallOp141; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_278_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_278_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_278_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_278_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_278_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call81; -reg ap_block_state2_pp0_stage0_iter1_ignore_call81; -wire ap_block_state3_pp0_stage0_iter2_ignore_call81; -wire ap_block_state4_pp0_stage0_iter3_ignore_call81; -wire ap_block_state5_pp0_stage0_iter4_ignore_call81; -wire ap_block_state6_pp0_stage0_iter5_ignore_call81; -wire ap_block_state7_pp0_stage0_iter6_ignore_call81; -wire ap_block_state8_pp0_stage0_iter7_ignore_call81; -wire ap_block_state9_pp0_stage0_iter8_ignore_call81; -wire ap_block_state10_pp0_stage0_iter9_ignore_call81; -wire ap_block_state11_pp0_stage0_iter10_ignore_call81; -wire ap_block_state12_pp0_stage0_iter11_ignore_call81; -wire ap_block_state13_pp0_stage0_iter12_ignore_call81; -wire ap_block_state14_pp0_stage0_iter13_ignore_call81; -wire ap_block_state15_pp0_stage0_iter14_ignore_call81; -wire ap_block_state16_pp0_stage0_iter15_ignore_call81; -wire ap_block_state17_pp0_stage0_iter16_ignore_call81; -wire ap_block_state18_pp0_stage0_iter17_ignore_call81; -wire ap_block_state19_pp0_stage0_iter18_ignore_call81; -wire ap_block_state20_pp0_stage0_iter19_ignore_call81; -wire ap_block_state21_pp0_stage0_iter20_ignore_call81; -wire ap_block_state22_pp0_stage0_iter21_ignore_call81; -wire ap_block_state23_pp0_stage0_iter22_ignore_call81; -wire ap_block_state24_pp0_stage0_iter23_ignore_call81; -wire ap_block_state25_pp0_stage0_iter24_ignore_call81; -wire ap_block_state26_pp0_stage0_iter25_ignore_call81; -wire ap_block_state27_pp0_stage0_iter26_ignore_call81; -wire ap_block_state28_pp0_stage0_iter27_ignore_call81; -wire ap_block_state29_pp0_stage0_iter28_ignore_call81; -wire ap_block_state30_pp0_stage0_iter29_ignore_call81; -wire ap_block_state31_pp0_stage0_iter30_ignore_call81; -wire ap_block_state32_pp0_stage0_iter31_ignore_call81; -wire ap_block_state33_pp0_stage0_iter32_ignore_call81; -wire ap_block_state34_pp0_stage0_iter33_ignore_call81; -wire ap_block_state35_pp0_stage0_iter34_ignore_call81; -wire ap_block_state36_pp0_stage0_iter35_ignore_call81; -wire ap_block_state37_pp0_stage0_iter36_ignore_call81; -wire ap_block_state38_pp0_stage0_iter37_ignore_call81; -wire ap_block_state39_pp0_stage0_iter38_ignore_call81; -wire ap_block_state40_pp0_stage0_iter39_ignore_call81; -wire ap_block_state41_pp0_stage0_iter40_ignore_call81; -wire ap_block_state42_pp0_stage0_iter41_ignore_call81; -wire ap_block_state43_pp0_stage0_iter42_ignore_call81; -wire ap_block_state44_pp0_stage0_iter43_ignore_call81; -wire ap_block_state45_pp0_stage0_iter44_ignore_call81; -reg ap_block_state46_pp0_stage0_iter45_ignore_call81; -reg ap_block_pp0_stage0_11001_ignoreCallOp152; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_289_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_289_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_289_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_289_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_289_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call93; -reg ap_block_state2_pp0_stage0_iter1_ignore_call93; -wire ap_block_state3_pp0_stage0_iter2_ignore_call93; -wire ap_block_state4_pp0_stage0_iter3_ignore_call93; -wire ap_block_state5_pp0_stage0_iter4_ignore_call93; -wire ap_block_state6_pp0_stage0_iter5_ignore_call93; -wire ap_block_state7_pp0_stage0_iter6_ignore_call93; -wire ap_block_state8_pp0_stage0_iter7_ignore_call93; -wire ap_block_state9_pp0_stage0_iter8_ignore_call93; -wire ap_block_state10_pp0_stage0_iter9_ignore_call93; -wire ap_block_state11_pp0_stage0_iter10_ignore_call93; -wire ap_block_state12_pp0_stage0_iter11_ignore_call93; -wire ap_block_state13_pp0_stage0_iter12_ignore_call93; -wire ap_block_state14_pp0_stage0_iter13_ignore_call93; -wire ap_block_state15_pp0_stage0_iter14_ignore_call93; -wire ap_block_state16_pp0_stage0_iter15_ignore_call93; -wire ap_block_state17_pp0_stage0_iter16_ignore_call93; -wire ap_block_state18_pp0_stage0_iter17_ignore_call93; -wire ap_block_state19_pp0_stage0_iter18_ignore_call93; -wire ap_block_state20_pp0_stage0_iter19_ignore_call93; -wire ap_block_state21_pp0_stage0_iter20_ignore_call93; -wire ap_block_state22_pp0_stage0_iter21_ignore_call93; -wire ap_block_state23_pp0_stage0_iter22_ignore_call93; -wire ap_block_state24_pp0_stage0_iter23_ignore_call93; -wire ap_block_state25_pp0_stage0_iter24_ignore_call93; -wire ap_block_state26_pp0_stage0_iter25_ignore_call93; -wire ap_block_state27_pp0_stage0_iter26_ignore_call93; -wire ap_block_state28_pp0_stage0_iter27_ignore_call93; -wire ap_block_state29_pp0_stage0_iter28_ignore_call93; -wire ap_block_state30_pp0_stage0_iter29_ignore_call93; -wire ap_block_state31_pp0_stage0_iter30_ignore_call93; -wire ap_block_state32_pp0_stage0_iter31_ignore_call93; -wire ap_block_state33_pp0_stage0_iter32_ignore_call93; -wire ap_block_state34_pp0_stage0_iter33_ignore_call93; -wire ap_block_state35_pp0_stage0_iter34_ignore_call93; -wire ap_block_state36_pp0_stage0_iter35_ignore_call93; -wire ap_block_state37_pp0_stage0_iter36_ignore_call93; -wire ap_block_state38_pp0_stage0_iter37_ignore_call93; -wire ap_block_state39_pp0_stage0_iter38_ignore_call93; -wire ap_block_state40_pp0_stage0_iter39_ignore_call93; -wire ap_block_state41_pp0_stage0_iter40_ignore_call93; -wire ap_block_state42_pp0_stage0_iter41_ignore_call93; -wire ap_block_state43_pp0_stage0_iter42_ignore_call93; -wire ap_block_state44_pp0_stage0_iter43_ignore_call93; -wire ap_block_state45_pp0_stage0_iter44_ignore_call93; -reg ap_block_state46_pp0_stage0_iter45_ignore_call93; -reg ap_block_pp0_stage0_11001_ignoreCallOp163; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_300_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_300_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_300_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_300_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_300_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call105; -reg ap_block_state2_pp0_stage0_iter1_ignore_call105; -wire ap_block_state3_pp0_stage0_iter2_ignore_call105; -wire ap_block_state4_pp0_stage0_iter3_ignore_call105; -wire ap_block_state5_pp0_stage0_iter4_ignore_call105; -wire ap_block_state6_pp0_stage0_iter5_ignore_call105; -wire ap_block_state7_pp0_stage0_iter6_ignore_call105; -wire ap_block_state8_pp0_stage0_iter7_ignore_call105; -wire ap_block_state9_pp0_stage0_iter8_ignore_call105; -wire ap_block_state10_pp0_stage0_iter9_ignore_call105; -wire ap_block_state11_pp0_stage0_iter10_ignore_call105; -wire ap_block_state12_pp0_stage0_iter11_ignore_call105; -wire ap_block_state13_pp0_stage0_iter12_ignore_call105; -wire ap_block_state14_pp0_stage0_iter13_ignore_call105; -wire ap_block_state15_pp0_stage0_iter14_ignore_call105; -wire ap_block_state16_pp0_stage0_iter15_ignore_call105; -wire ap_block_state17_pp0_stage0_iter16_ignore_call105; -wire ap_block_state18_pp0_stage0_iter17_ignore_call105; -wire ap_block_state19_pp0_stage0_iter18_ignore_call105; -wire ap_block_state20_pp0_stage0_iter19_ignore_call105; -wire ap_block_state21_pp0_stage0_iter20_ignore_call105; -wire ap_block_state22_pp0_stage0_iter21_ignore_call105; -wire ap_block_state23_pp0_stage0_iter22_ignore_call105; -wire ap_block_state24_pp0_stage0_iter23_ignore_call105; -wire ap_block_state25_pp0_stage0_iter24_ignore_call105; -wire ap_block_state26_pp0_stage0_iter25_ignore_call105; -wire ap_block_state27_pp0_stage0_iter26_ignore_call105; -wire ap_block_state28_pp0_stage0_iter27_ignore_call105; -wire ap_block_state29_pp0_stage0_iter28_ignore_call105; -wire ap_block_state30_pp0_stage0_iter29_ignore_call105; -wire ap_block_state31_pp0_stage0_iter30_ignore_call105; -wire ap_block_state32_pp0_stage0_iter31_ignore_call105; -wire ap_block_state33_pp0_stage0_iter32_ignore_call105; -wire ap_block_state34_pp0_stage0_iter33_ignore_call105; -wire ap_block_state35_pp0_stage0_iter34_ignore_call105; -wire ap_block_state36_pp0_stage0_iter35_ignore_call105; -wire ap_block_state37_pp0_stage0_iter36_ignore_call105; -wire ap_block_state38_pp0_stage0_iter37_ignore_call105; -wire ap_block_state39_pp0_stage0_iter38_ignore_call105; -wire ap_block_state40_pp0_stage0_iter39_ignore_call105; -wire ap_block_state41_pp0_stage0_iter40_ignore_call105; -wire ap_block_state42_pp0_stage0_iter41_ignore_call105; -wire ap_block_state43_pp0_stage0_iter42_ignore_call105; -wire ap_block_state44_pp0_stage0_iter43_ignore_call105; -wire ap_block_state45_pp0_stage0_iter44_ignore_call105; -reg ap_block_state46_pp0_stage0_iter45_ignore_call105; -reg ap_block_pp0_stage0_11001_ignoreCallOp174; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_311_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_311_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_311_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_311_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_311_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call117; -reg ap_block_state2_pp0_stage0_iter1_ignore_call117; -wire ap_block_state3_pp0_stage0_iter2_ignore_call117; -wire ap_block_state4_pp0_stage0_iter3_ignore_call117; -wire ap_block_state5_pp0_stage0_iter4_ignore_call117; -wire ap_block_state6_pp0_stage0_iter5_ignore_call117; -wire ap_block_state7_pp0_stage0_iter6_ignore_call117; -wire ap_block_state8_pp0_stage0_iter7_ignore_call117; -wire ap_block_state9_pp0_stage0_iter8_ignore_call117; -wire ap_block_state10_pp0_stage0_iter9_ignore_call117; -wire ap_block_state11_pp0_stage0_iter10_ignore_call117; -wire ap_block_state12_pp0_stage0_iter11_ignore_call117; -wire ap_block_state13_pp0_stage0_iter12_ignore_call117; -wire ap_block_state14_pp0_stage0_iter13_ignore_call117; -wire ap_block_state15_pp0_stage0_iter14_ignore_call117; -wire ap_block_state16_pp0_stage0_iter15_ignore_call117; -wire ap_block_state17_pp0_stage0_iter16_ignore_call117; -wire ap_block_state18_pp0_stage0_iter17_ignore_call117; -wire ap_block_state19_pp0_stage0_iter18_ignore_call117; -wire ap_block_state20_pp0_stage0_iter19_ignore_call117; -wire ap_block_state21_pp0_stage0_iter20_ignore_call117; -wire ap_block_state22_pp0_stage0_iter21_ignore_call117; -wire ap_block_state23_pp0_stage0_iter22_ignore_call117; -wire ap_block_state24_pp0_stage0_iter23_ignore_call117; -wire ap_block_state25_pp0_stage0_iter24_ignore_call117; -wire ap_block_state26_pp0_stage0_iter25_ignore_call117; -wire ap_block_state27_pp0_stage0_iter26_ignore_call117; -wire ap_block_state28_pp0_stage0_iter27_ignore_call117; -wire ap_block_state29_pp0_stage0_iter28_ignore_call117; -wire ap_block_state30_pp0_stage0_iter29_ignore_call117; -wire ap_block_state31_pp0_stage0_iter30_ignore_call117; -wire ap_block_state32_pp0_stage0_iter31_ignore_call117; -wire ap_block_state33_pp0_stage0_iter32_ignore_call117; -wire ap_block_state34_pp0_stage0_iter33_ignore_call117; -wire ap_block_state35_pp0_stage0_iter34_ignore_call117; -wire ap_block_state36_pp0_stage0_iter35_ignore_call117; -wire ap_block_state37_pp0_stage0_iter36_ignore_call117; -wire ap_block_state38_pp0_stage0_iter37_ignore_call117; -wire ap_block_state39_pp0_stage0_iter38_ignore_call117; -wire ap_block_state40_pp0_stage0_iter39_ignore_call117; -wire ap_block_state41_pp0_stage0_iter40_ignore_call117; -wire ap_block_state42_pp0_stage0_iter41_ignore_call117; -wire ap_block_state43_pp0_stage0_iter42_ignore_call117; -wire ap_block_state44_pp0_stage0_iter43_ignore_call117; -wire ap_block_state45_pp0_stage0_iter44_ignore_call117; -reg ap_block_state46_pp0_stage0_iter45_ignore_call117; -reg ap_block_pp0_stage0_11001_ignoreCallOp185; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_322_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_322_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_322_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_322_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_322_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call129; -reg ap_block_state2_pp0_stage0_iter1_ignore_call129; -wire ap_block_state3_pp0_stage0_iter2_ignore_call129; -wire ap_block_state4_pp0_stage0_iter3_ignore_call129; -wire ap_block_state5_pp0_stage0_iter4_ignore_call129; -wire ap_block_state6_pp0_stage0_iter5_ignore_call129; -wire ap_block_state7_pp0_stage0_iter6_ignore_call129; -wire ap_block_state8_pp0_stage0_iter7_ignore_call129; -wire ap_block_state9_pp0_stage0_iter8_ignore_call129; -wire ap_block_state10_pp0_stage0_iter9_ignore_call129; -wire ap_block_state11_pp0_stage0_iter10_ignore_call129; -wire ap_block_state12_pp0_stage0_iter11_ignore_call129; -wire ap_block_state13_pp0_stage0_iter12_ignore_call129; -wire ap_block_state14_pp0_stage0_iter13_ignore_call129; -wire ap_block_state15_pp0_stage0_iter14_ignore_call129; -wire ap_block_state16_pp0_stage0_iter15_ignore_call129; -wire ap_block_state17_pp0_stage0_iter16_ignore_call129; -wire ap_block_state18_pp0_stage0_iter17_ignore_call129; -wire ap_block_state19_pp0_stage0_iter18_ignore_call129; -wire ap_block_state20_pp0_stage0_iter19_ignore_call129; -wire ap_block_state21_pp0_stage0_iter20_ignore_call129; -wire ap_block_state22_pp0_stage0_iter21_ignore_call129; -wire ap_block_state23_pp0_stage0_iter22_ignore_call129; -wire ap_block_state24_pp0_stage0_iter23_ignore_call129; -wire ap_block_state25_pp0_stage0_iter24_ignore_call129; -wire ap_block_state26_pp0_stage0_iter25_ignore_call129; -wire ap_block_state27_pp0_stage0_iter26_ignore_call129; -wire ap_block_state28_pp0_stage0_iter27_ignore_call129; -wire ap_block_state29_pp0_stage0_iter28_ignore_call129; -wire ap_block_state30_pp0_stage0_iter29_ignore_call129; -wire ap_block_state31_pp0_stage0_iter30_ignore_call129; -wire ap_block_state32_pp0_stage0_iter31_ignore_call129; -wire ap_block_state33_pp0_stage0_iter32_ignore_call129; -wire ap_block_state34_pp0_stage0_iter33_ignore_call129; -wire ap_block_state35_pp0_stage0_iter34_ignore_call129; -wire ap_block_state36_pp0_stage0_iter35_ignore_call129; -wire ap_block_state37_pp0_stage0_iter36_ignore_call129; -wire ap_block_state38_pp0_stage0_iter37_ignore_call129; -wire ap_block_state39_pp0_stage0_iter38_ignore_call129; -wire ap_block_state40_pp0_stage0_iter39_ignore_call129; -wire ap_block_state41_pp0_stage0_iter40_ignore_call129; -wire ap_block_state42_pp0_stage0_iter41_ignore_call129; -wire ap_block_state43_pp0_stage0_iter42_ignore_call129; -wire ap_block_state44_pp0_stage0_iter43_ignore_call129; -wire ap_block_state45_pp0_stage0_iter44_ignore_call129; -reg ap_block_state46_pp0_stage0_iter45_ignore_call129; -reg ap_block_pp0_stage0_11001_ignoreCallOp196; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_333_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_333_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_333_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_333_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_333_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call141; -reg ap_block_state2_pp0_stage0_iter1_ignore_call141; -wire ap_block_state3_pp0_stage0_iter2_ignore_call141; -wire ap_block_state4_pp0_stage0_iter3_ignore_call141; -wire ap_block_state5_pp0_stage0_iter4_ignore_call141; -wire ap_block_state6_pp0_stage0_iter5_ignore_call141; -wire ap_block_state7_pp0_stage0_iter6_ignore_call141; -wire ap_block_state8_pp0_stage0_iter7_ignore_call141; -wire ap_block_state9_pp0_stage0_iter8_ignore_call141; -wire ap_block_state10_pp0_stage0_iter9_ignore_call141; -wire ap_block_state11_pp0_stage0_iter10_ignore_call141; -wire ap_block_state12_pp0_stage0_iter11_ignore_call141; -wire ap_block_state13_pp0_stage0_iter12_ignore_call141; -wire ap_block_state14_pp0_stage0_iter13_ignore_call141; -wire ap_block_state15_pp0_stage0_iter14_ignore_call141; -wire ap_block_state16_pp0_stage0_iter15_ignore_call141; -wire ap_block_state17_pp0_stage0_iter16_ignore_call141; -wire ap_block_state18_pp0_stage0_iter17_ignore_call141; -wire ap_block_state19_pp0_stage0_iter18_ignore_call141; -wire ap_block_state20_pp0_stage0_iter19_ignore_call141; -wire ap_block_state21_pp0_stage0_iter20_ignore_call141; -wire ap_block_state22_pp0_stage0_iter21_ignore_call141; -wire ap_block_state23_pp0_stage0_iter22_ignore_call141; -wire ap_block_state24_pp0_stage0_iter23_ignore_call141; -wire ap_block_state25_pp0_stage0_iter24_ignore_call141; -wire ap_block_state26_pp0_stage0_iter25_ignore_call141; -wire ap_block_state27_pp0_stage0_iter26_ignore_call141; -wire ap_block_state28_pp0_stage0_iter27_ignore_call141; -wire ap_block_state29_pp0_stage0_iter28_ignore_call141; -wire ap_block_state30_pp0_stage0_iter29_ignore_call141; -wire ap_block_state31_pp0_stage0_iter30_ignore_call141; -wire ap_block_state32_pp0_stage0_iter31_ignore_call141; -wire ap_block_state33_pp0_stage0_iter32_ignore_call141; -wire ap_block_state34_pp0_stage0_iter33_ignore_call141; -wire ap_block_state35_pp0_stage0_iter34_ignore_call141; -wire ap_block_state36_pp0_stage0_iter35_ignore_call141; -wire ap_block_state37_pp0_stage0_iter36_ignore_call141; -wire ap_block_state38_pp0_stage0_iter37_ignore_call141; -wire ap_block_state39_pp0_stage0_iter38_ignore_call141; -wire ap_block_state40_pp0_stage0_iter39_ignore_call141; -wire ap_block_state41_pp0_stage0_iter40_ignore_call141; -wire ap_block_state42_pp0_stage0_iter41_ignore_call141; -wire ap_block_state43_pp0_stage0_iter42_ignore_call141; -wire ap_block_state44_pp0_stage0_iter43_ignore_call141; -wire ap_block_state45_pp0_stage0_iter44_ignore_call141; -reg ap_block_state46_pp0_stage0_iter45_ignore_call141; -reg ap_block_pp0_stage0_11001_ignoreCallOp207; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_344_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_344_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_344_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_344_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_344_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call153; -reg ap_block_state2_pp0_stage0_iter1_ignore_call153; -wire ap_block_state3_pp0_stage0_iter2_ignore_call153; -wire ap_block_state4_pp0_stage0_iter3_ignore_call153; -wire ap_block_state5_pp0_stage0_iter4_ignore_call153; -wire ap_block_state6_pp0_stage0_iter5_ignore_call153; -wire ap_block_state7_pp0_stage0_iter6_ignore_call153; -wire ap_block_state8_pp0_stage0_iter7_ignore_call153; -wire ap_block_state9_pp0_stage0_iter8_ignore_call153; -wire ap_block_state10_pp0_stage0_iter9_ignore_call153; -wire ap_block_state11_pp0_stage0_iter10_ignore_call153; -wire ap_block_state12_pp0_stage0_iter11_ignore_call153; -wire ap_block_state13_pp0_stage0_iter12_ignore_call153; -wire ap_block_state14_pp0_stage0_iter13_ignore_call153; -wire ap_block_state15_pp0_stage0_iter14_ignore_call153; -wire ap_block_state16_pp0_stage0_iter15_ignore_call153; -wire ap_block_state17_pp0_stage0_iter16_ignore_call153; -wire ap_block_state18_pp0_stage0_iter17_ignore_call153; -wire ap_block_state19_pp0_stage0_iter18_ignore_call153; -wire ap_block_state20_pp0_stage0_iter19_ignore_call153; -wire ap_block_state21_pp0_stage0_iter20_ignore_call153; -wire ap_block_state22_pp0_stage0_iter21_ignore_call153; -wire ap_block_state23_pp0_stage0_iter22_ignore_call153; -wire ap_block_state24_pp0_stage0_iter23_ignore_call153; -wire ap_block_state25_pp0_stage0_iter24_ignore_call153; -wire ap_block_state26_pp0_stage0_iter25_ignore_call153; -wire ap_block_state27_pp0_stage0_iter26_ignore_call153; -wire ap_block_state28_pp0_stage0_iter27_ignore_call153; -wire ap_block_state29_pp0_stage0_iter28_ignore_call153; -wire ap_block_state30_pp0_stage0_iter29_ignore_call153; -wire ap_block_state31_pp0_stage0_iter30_ignore_call153; -wire ap_block_state32_pp0_stage0_iter31_ignore_call153; -wire ap_block_state33_pp0_stage0_iter32_ignore_call153; -wire ap_block_state34_pp0_stage0_iter33_ignore_call153; -wire ap_block_state35_pp0_stage0_iter34_ignore_call153; -wire ap_block_state36_pp0_stage0_iter35_ignore_call153; -wire ap_block_state37_pp0_stage0_iter36_ignore_call153; -wire ap_block_state38_pp0_stage0_iter37_ignore_call153; -wire ap_block_state39_pp0_stage0_iter38_ignore_call153; -wire ap_block_state40_pp0_stage0_iter39_ignore_call153; -wire ap_block_state41_pp0_stage0_iter40_ignore_call153; -wire ap_block_state42_pp0_stage0_iter41_ignore_call153; -wire ap_block_state43_pp0_stage0_iter42_ignore_call153; -wire ap_block_state44_pp0_stage0_iter43_ignore_call153; -wire ap_block_state45_pp0_stage0_iter44_ignore_call153; -reg ap_block_state46_pp0_stage0_iter45_ignore_call153; -reg ap_block_pp0_stage0_11001_ignoreCallOp218; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_355_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_355_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_355_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_355_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_355_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call165; -reg ap_block_state2_pp0_stage0_iter1_ignore_call165; -wire ap_block_state3_pp0_stage0_iter2_ignore_call165; -wire ap_block_state4_pp0_stage0_iter3_ignore_call165; -wire ap_block_state5_pp0_stage0_iter4_ignore_call165; -wire ap_block_state6_pp0_stage0_iter5_ignore_call165; -wire ap_block_state7_pp0_stage0_iter6_ignore_call165; -wire ap_block_state8_pp0_stage0_iter7_ignore_call165; -wire ap_block_state9_pp0_stage0_iter8_ignore_call165; -wire ap_block_state10_pp0_stage0_iter9_ignore_call165; -wire ap_block_state11_pp0_stage0_iter10_ignore_call165; -wire ap_block_state12_pp0_stage0_iter11_ignore_call165; -wire ap_block_state13_pp0_stage0_iter12_ignore_call165; -wire ap_block_state14_pp0_stage0_iter13_ignore_call165; -wire ap_block_state15_pp0_stage0_iter14_ignore_call165; -wire ap_block_state16_pp0_stage0_iter15_ignore_call165; -wire ap_block_state17_pp0_stage0_iter16_ignore_call165; -wire ap_block_state18_pp0_stage0_iter17_ignore_call165; -wire ap_block_state19_pp0_stage0_iter18_ignore_call165; -wire ap_block_state20_pp0_stage0_iter19_ignore_call165; -wire ap_block_state21_pp0_stage0_iter20_ignore_call165; -wire ap_block_state22_pp0_stage0_iter21_ignore_call165; -wire ap_block_state23_pp0_stage0_iter22_ignore_call165; -wire ap_block_state24_pp0_stage0_iter23_ignore_call165; -wire ap_block_state25_pp0_stage0_iter24_ignore_call165; -wire ap_block_state26_pp0_stage0_iter25_ignore_call165; -wire ap_block_state27_pp0_stage0_iter26_ignore_call165; -wire ap_block_state28_pp0_stage0_iter27_ignore_call165; -wire ap_block_state29_pp0_stage0_iter28_ignore_call165; -wire ap_block_state30_pp0_stage0_iter29_ignore_call165; -wire ap_block_state31_pp0_stage0_iter30_ignore_call165; -wire ap_block_state32_pp0_stage0_iter31_ignore_call165; -wire ap_block_state33_pp0_stage0_iter32_ignore_call165; -wire ap_block_state34_pp0_stage0_iter33_ignore_call165; -wire ap_block_state35_pp0_stage0_iter34_ignore_call165; -wire ap_block_state36_pp0_stage0_iter35_ignore_call165; -wire ap_block_state37_pp0_stage0_iter36_ignore_call165; -wire ap_block_state38_pp0_stage0_iter37_ignore_call165; -wire ap_block_state39_pp0_stage0_iter38_ignore_call165; -wire ap_block_state40_pp0_stage0_iter39_ignore_call165; -wire ap_block_state41_pp0_stage0_iter40_ignore_call165; -wire ap_block_state42_pp0_stage0_iter41_ignore_call165; -wire ap_block_state43_pp0_stage0_iter42_ignore_call165; -wire ap_block_state44_pp0_stage0_iter43_ignore_call165; -wire ap_block_state45_pp0_stage0_iter44_ignore_call165; -reg ap_block_state46_pp0_stage0_iter45_ignore_call165; -reg ap_block_pp0_stage0_11001_ignoreCallOp229; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_366_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_366_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_366_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_366_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_366_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call177; -reg ap_block_state2_pp0_stage0_iter1_ignore_call177; -wire ap_block_state3_pp0_stage0_iter2_ignore_call177; -wire ap_block_state4_pp0_stage0_iter3_ignore_call177; -wire ap_block_state5_pp0_stage0_iter4_ignore_call177; -wire ap_block_state6_pp0_stage0_iter5_ignore_call177; -wire ap_block_state7_pp0_stage0_iter6_ignore_call177; -wire ap_block_state8_pp0_stage0_iter7_ignore_call177; -wire ap_block_state9_pp0_stage0_iter8_ignore_call177; -wire ap_block_state10_pp0_stage0_iter9_ignore_call177; -wire ap_block_state11_pp0_stage0_iter10_ignore_call177; -wire ap_block_state12_pp0_stage0_iter11_ignore_call177; -wire ap_block_state13_pp0_stage0_iter12_ignore_call177; -wire ap_block_state14_pp0_stage0_iter13_ignore_call177; -wire ap_block_state15_pp0_stage0_iter14_ignore_call177; -wire ap_block_state16_pp0_stage0_iter15_ignore_call177; -wire ap_block_state17_pp0_stage0_iter16_ignore_call177; -wire ap_block_state18_pp0_stage0_iter17_ignore_call177; -wire ap_block_state19_pp0_stage0_iter18_ignore_call177; -wire ap_block_state20_pp0_stage0_iter19_ignore_call177; -wire ap_block_state21_pp0_stage0_iter20_ignore_call177; -wire ap_block_state22_pp0_stage0_iter21_ignore_call177; -wire ap_block_state23_pp0_stage0_iter22_ignore_call177; -wire ap_block_state24_pp0_stage0_iter23_ignore_call177; -wire ap_block_state25_pp0_stage0_iter24_ignore_call177; -wire ap_block_state26_pp0_stage0_iter25_ignore_call177; -wire ap_block_state27_pp0_stage0_iter26_ignore_call177; -wire ap_block_state28_pp0_stage0_iter27_ignore_call177; -wire ap_block_state29_pp0_stage0_iter28_ignore_call177; -wire ap_block_state30_pp0_stage0_iter29_ignore_call177; -wire ap_block_state31_pp0_stage0_iter30_ignore_call177; -wire ap_block_state32_pp0_stage0_iter31_ignore_call177; -wire ap_block_state33_pp0_stage0_iter32_ignore_call177; -wire ap_block_state34_pp0_stage0_iter33_ignore_call177; -wire ap_block_state35_pp0_stage0_iter34_ignore_call177; -wire ap_block_state36_pp0_stage0_iter35_ignore_call177; -wire ap_block_state37_pp0_stage0_iter36_ignore_call177; -wire ap_block_state38_pp0_stage0_iter37_ignore_call177; -wire ap_block_state39_pp0_stage0_iter38_ignore_call177; -wire ap_block_state40_pp0_stage0_iter39_ignore_call177; -wire ap_block_state41_pp0_stage0_iter40_ignore_call177; -wire ap_block_state42_pp0_stage0_iter41_ignore_call177; -wire ap_block_state43_pp0_stage0_iter42_ignore_call177; -wire ap_block_state44_pp0_stage0_iter43_ignore_call177; -wire ap_block_state45_pp0_stage0_iter44_ignore_call177; -reg ap_block_state46_pp0_stage0_iter45_ignore_call177; -reg ap_block_pp0_stage0_11001_ignoreCallOp240; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_377_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_377_in_0_m1_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_377_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_377_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_377_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call189; -reg ap_block_state2_pp0_stage0_iter1_ignore_call189; -wire ap_block_state3_pp0_stage0_iter2_ignore_call189; -wire ap_block_state4_pp0_stage0_iter3_ignore_call189; -wire ap_block_state5_pp0_stage0_iter4_ignore_call189; -wire ap_block_state6_pp0_stage0_iter5_ignore_call189; -wire ap_block_state7_pp0_stage0_iter6_ignore_call189; -wire ap_block_state8_pp0_stage0_iter7_ignore_call189; -wire ap_block_state9_pp0_stage0_iter8_ignore_call189; -wire ap_block_state10_pp0_stage0_iter9_ignore_call189; -wire ap_block_state11_pp0_stage0_iter10_ignore_call189; -wire ap_block_state12_pp0_stage0_iter11_ignore_call189; -wire ap_block_state13_pp0_stage0_iter12_ignore_call189; -wire ap_block_state14_pp0_stage0_iter13_ignore_call189; -wire ap_block_state15_pp0_stage0_iter14_ignore_call189; -wire ap_block_state16_pp0_stage0_iter15_ignore_call189; -wire ap_block_state17_pp0_stage0_iter16_ignore_call189; -wire ap_block_state18_pp0_stage0_iter17_ignore_call189; -wire ap_block_state19_pp0_stage0_iter18_ignore_call189; -wire ap_block_state20_pp0_stage0_iter19_ignore_call189; -wire ap_block_state21_pp0_stage0_iter20_ignore_call189; -wire ap_block_state22_pp0_stage0_iter21_ignore_call189; -wire ap_block_state23_pp0_stage0_iter22_ignore_call189; -wire ap_block_state24_pp0_stage0_iter23_ignore_call189; -wire ap_block_state25_pp0_stage0_iter24_ignore_call189; -wire ap_block_state26_pp0_stage0_iter25_ignore_call189; -wire ap_block_state27_pp0_stage0_iter26_ignore_call189; -wire ap_block_state28_pp0_stage0_iter27_ignore_call189; -wire ap_block_state29_pp0_stage0_iter28_ignore_call189; -wire ap_block_state30_pp0_stage0_iter29_ignore_call189; -wire ap_block_state31_pp0_stage0_iter30_ignore_call189; -wire ap_block_state32_pp0_stage0_iter31_ignore_call189; -wire ap_block_state33_pp0_stage0_iter32_ignore_call189; -wire ap_block_state34_pp0_stage0_iter33_ignore_call189; -wire ap_block_state35_pp0_stage0_iter34_ignore_call189; -wire ap_block_state36_pp0_stage0_iter35_ignore_call189; -wire ap_block_state37_pp0_stage0_iter36_ignore_call189; -wire ap_block_state38_pp0_stage0_iter37_ignore_call189; -wire ap_block_state39_pp0_stage0_iter38_ignore_call189; -wire ap_block_state40_pp0_stage0_iter39_ignore_call189; -wire ap_block_state41_pp0_stage0_iter40_ignore_call189; -wire ap_block_state42_pp0_stage0_iter41_ignore_call189; -wire ap_block_state43_pp0_stage0_iter42_ignore_call189; -wire ap_block_state44_pp0_stage0_iter43_ignore_call189; -wire ap_block_state45_pp0_stage0_iter44_ignore_call189; -reg ap_block_state46_pp0_stage0_iter45_ignore_call189; -reg ap_block_pp0_stage0_11001_ignoreCallOp251; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_388_in_1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_388_in_m1_0_0; -wire [31:0] grp_HEAT3D_stencil_kernel_fu_388_in_0_1_0; -reg grp_HEAT3D_stencil_kernel_fu_388_ap_ce; -wire ap_block_state1_pp0_stage0_iter0_ignore_call197; -reg ap_block_state2_pp0_stage0_iter1_ignore_call197; -wire ap_block_state3_pp0_stage0_iter2_ignore_call197; -wire ap_block_state4_pp0_stage0_iter3_ignore_call197; -wire ap_block_state5_pp0_stage0_iter4_ignore_call197; -wire ap_block_state6_pp0_stage0_iter5_ignore_call197; -wire ap_block_state7_pp0_stage0_iter6_ignore_call197; -wire ap_block_state8_pp0_stage0_iter7_ignore_call197; -wire ap_block_state9_pp0_stage0_iter8_ignore_call197; -wire ap_block_state10_pp0_stage0_iter9_ignore_call197; -wire ap_block_state11_pp0_stage0_iter10_ignore_call197; -wire ap_block_state12_pp0_stage0_iter11_ignore_call197; -wire ap_block_state13_pp0_stage0_iter12_ignore_call197; -wire ap_block_state14_pp0_stage0_iter13_ignore_call197; -wire ap_block_state15_pp0_stage0_iter14_ignore_call197; -wire ap_block_state16_pp0_stage0_iter15_ignore_call197; -wire ap_block_state17_pp0_stage0_iter16_ignore_call197; -wire ap_block_state18_pp0_stage0_iter17_ignore_call197; -wire ap_block_state19_pp0_stage0_iter18_ignore_call197; -wire ap_block_state20_pp0_stage0_iter19_ignore_call197; -wire ap_block_state21_pp0_stage0_iter20_ignore_call197; -wire ap_block_state22_pp0_stage0_iter21_ignore_call197; -wire ap_block_state23_pp0_stage0_iter22_ignore_call197; -wire ap_block_state24_pp0_stage0_iter23_ignore_call197; -wire ap_block_state25_pp0_stage0_iter24_ignore_call197; -wire ap_block_state26_pp0_stage0_iter25_ignore_call197; -wire ap_block_state27_pp0_stage0_iter26_ignore_call197; -wire ap_block_state28_pp0_stage0_iter27_ignore_call197; -wire ap_block_state29_pp0_stage0_iter28_ignore_call197; -wire ap_block_state30_pp0_stage0_iter29_ignore_call197; -wire ap_block_state31_pp0_stage0_iter30_ignore_call197; -wire ap_block_state32_pp0_stage0_iter31_ignore_call197; -wire ap_block_state33_pp0_stage0_iter32_ignore_call197; -wire ap_block_state34_pp0_stage0_iter33_ignore_call197; -wire ap_block_state35_pp0_stage0_iter34_ignore_call197; -wire ap_block_state36_pp0_stage0_iter35_ignore_call197; -wire ap_block_state37_pp0_stage0_iter36_ignore_call197; -wire ap_block_state38_pp0_stage0_iter37_ignore_call197; -wire ap_block_state39_pp0_stage0_iter38_ignore_call197; -wire ap_block_state40_pp0_stage0_iter39_ignore_call197; -wire ap_block_state41_pp0_stage0_iter40_ignore_call197; -wire ap_block_state42_pp0_stage0_iter41_ignore_call197; -wire ap_block_state43_pp0_stage0_iter42_ignore_call197; -wire ap_block_state44_pp0_stage0_iter43_ignore_call197; -wire ap_block_state45_pp0_stage0_iter44_ignore_call197; -reg ap_block_state46_pp0_stage0_iter45_ignore_call197; -reg ap_block_pp0_stage0_11001_ignoreCallOp258; -wire p_1_HLS_REG_ap_uint_512_s_fu_399_ap_ready; -wire [511:0] p_1_HLS_REG_ap_uint_512_s_fu_399_ap_return; -wire ref_tmp1_HLS_REG_ap_uint_512_s_fu_405_ap_ready; -wire [511:0] ref_tmp1_HLS_REG_ap_uint_512_s_fu_405_ap_return; -wire ref_tmp2_HLS_REG_ap_uint_512_s_fu_410_ap_ready; -wire [511:0] ref_tmp2_HLS_REG_ap_uint_512_s_fu_410_ap_return; -wire p_0_HLS_REG_ap_uint_512_s_fu_415_ap_ready; -wire [511:0] p_0_HLS_REG_ap_uint_512_s_fu_415_ap_return; -wire in_block_16_V_1_HLS_REG_ap_uint_512_s_fu_421_ap_ready; -wire [511:0] in_block_16_V_1_HLS_REG_ap_uint_512_s_fu_421_in_r; -wire [511:0] in_block_16_V_1_HLS_REG_ap_uint_512_s_fu_421_ap_return; -reg [511:0] p_Val2_s_fu_124; -wire ap_loop_init; -reg [511:0] p_Val2_1_fu_128; -reg [30:0] i_4_fu_132; -wire [30:0] add_ln73_1_fu_469_p2; -reg [30:0] ap_sig_allocacmp_i_4_load; -reg [511:0] p_Val2_2_fu_136; -reg [511:0] p_Val2_3_fu_140; -reg [511:0] p_Val2_4_fu_144; -reg ap_block_pp0_stage0_01001; -wire [31:0] zext_ln73_fu_459_p1; -wire [31:0] temp_in_1_0_0_fu_499_p1; -wire [31:0] temp_in_0_0_1_fu_508_p4; -wire [31:0] temp_in_0_0_m1_fu_525_p4; -wire [31:0] temp_in_0_0_0_1_fu_541_p1; -wire [31:0] temp_in_0_m1_0_fu_551_p1; -wire [31:0] temp_in_m1_0_0_fu_560_p1; -wire [31:0] temp_in_0_1_0_15_fu_569_p1; -wire [31:0] temp_in_1_0_0_1_fu_579_p4; -wire [31:0] temp_in_0_0_1_9_fu_594_p4; -wire [31:0] temp_in_0_m1_0_1_fu_611_p4; -wire [31:0] temp_in_m1_0_0_1_fu_626_p4; -wire [31:0] temp_in_0_1_0_1_fu_641_p4; -wire [31:0] temp_in_1_0_0_2_fu_656_p4; -wire [31:0] temp_in_0_0_1_10_fu_671_p4; -wire [31:0] temp_in_0_m1_0_2_fu_688_p4; -wire [31:0] temp_in_m1_0_0_2_fu_703_p4; -wire [31:0] temp_in_0_1_0_2_fu_718_p4; -wire [31:0] temp_in_1_0_0_3_fu_733_p4; -wire [31:0] temp_in_0_0_1_11_fu_748_p4; -wire [31:0] temp_in_0_m1_0_3_fu_765_p4; -wire [31:0] temp_in_m1_0_0_3_fu_780_p4; -wire [31:0] temp_in_0_1_0_3_fu_795_p4; -wire [31:0] temp_in_1_0_0_4_fu_810_p4; -wire [31:0] temp_in_0_0_1_12_fu_825_p4; -wire [31:0] temp_in_0_m1_0_4_fu_842_p4; -wire [31:0] temp_in_m1_0_0_4_fu_857_p4; -wire [31:0] temp_in_0_1_0_4_fu_872_p4; -wire [31:0] temp_in_1_0_0_5_fu_887_p4; -wire [31:0] temp_in_0_0_1_13_fu_902_p4; -wire [31:0] temp_in_0_m1_0_5_fu_919_p4; -wire [31:0] temp_in_m1_0_0_5_fu_934_p4; -wire [31:0] temp_in_0_1_0_5_fu_949_p4; -wire [31:0] temp_in_1_0_0_6_fu_964_p4; -wire [31:0] temp_in_0_0_1_14_fu_979_p4; -wire [31:0] temp_in_0_m1_0_6_fu_996_p4; -wire [31:0] temp_in_m1_0_0_6_fu_1011_p4; -wire [31:0] temp_in_0_1_0_6_fu_1026_p4; -wire [31:0] temp_in_1_0_0_7_fu_1041_p4; -wire [31:0] temp_in_0_0_1_15_fu_1056_p4; -wire [31:0] temp_in_0_m1_0_7_fu_1073_p4; -wire [31:0] temp_in_m1_0_0_7_fu_1088_p4; -wire [31:0] temp_in_0_1_0_7_fu_1103_p4; -wire [31:0] temp_in_1_0_0_8_fu_1118_p4; -wire [31:0] temp_in_0_0_1_16_fu_1133_p4; -wire [31:0] temp_in_0_m1_0_8_fu_1150_p4; -wire [31:0] temp_in_m1_0_0_8_fu_1165_p4; -wire [31:0] temp_in_0_1_0_8_fu_1180_p4; -wire [31:0] temp_in_1_0_0_9_fu_1195_p4; -wire [31:0] temp_in_0_0_1_17_fu_1210_p4; -wire [31:0] temp_in_0_m1_0_9_fu_1227_p4; -wire [31:0] temp_in_m1_0_0_9_fu_1242_p4; -wire [31:0] temp_in_0_1_0_9_fu_1257_p4; -wire [31:0] temp_in_1_0_0_10_fu_1272_p4; -wire [31:0] temp_in_0_0_1_18_fu_1287_p4; -wire [31:0] temp_in_0_m1_0_10_fu_1304_p4; -wire [31:0] temp_in_m1_0_0_10_fu_1319_p4; -wire [31:0] temp_in_0_1_0_10_fu_1334_p4; -wire [31:0] temp_in_1_0_0_11_fu_1349_p4; -wire [31:0] temp_in_0_0_1_19_fu_1364_p4; -wire [31:0] temp_in_0_m1_0_11_fu_1381_p4; -wire [31:0] temp_in_m1_0_0_11_fu_1396_p4; -wire [31:0] temp_in_0_1_0_11_fu_1411_p4; -wire [31:0] temp_in_1_0_0_12_fu_1426_p4; -wire [31:0] temp_in_0_0_1_20_fu_1441_p4; -wire [31:0] temp_in_0_m1_0_12_fu_1458_p4; -wire [31:0] temp_in_m1_0_0_12_fu_1473_p4; -wire [31:0] temp_in_0_1_0_12_fu_1488_p4; -wire [31:0] temp_in_1_0_0_13_fu_1503_p4; -wire [31:0] temp_in_0_0_1_21_fu_1518_p4; -wire [31:0] temp_in_0_m1_0_13_fu_1535_p4; -wire [31:0] temp_in_m1_0_0_13_fu_1550_p4; -wire [31:0] temp_in_0_1_0_13_fu_1565_p4; -wire [31:0] temp_in_1_0_0_14_fu_1580_p4; -wire [31:0] temp_in_0_0_1_22_fu_1595_p4; -wire [31:0] temp_in_0_m1_0_14_fu_1611_p4; -wire [31:0] temp_in_m1_0_0_14_fu_1626_p4; -wire [31:0] temp_in_0_1_0_14_fu_1641_p4; -wire [31:0] temp_in_1_0_0_15_fu_1656_p4; -wire [31:0] temp_in_m1_0_0_15_fu_1671_p4; -wire [31:0] temp_in_0_1_0_fu_1686_p4; -wire [31:0] bitcast_ln103_15_fu_1776_p1; -wire [31:0] bitcast_ln103_14_fu_1773_p1; -wire [31:0] bitcast_ln103_13_fu_1770_p1; -wire [31:0] bitcast_ln103_12_fu_1767_p1; -wire [31:0] bitcast_ln103_11_fu_1764_p1; -wire [31:0] bitcast_ln103_10_fu_1761_p1; -wire [31:0] bitcast_ln103_9_fu_1758_p1; -wire [31:0] bitcast_ln103_8_fu_1755_p1; -wire [31:0] bitcast_ln103_7_fu_1752_p1; -wire [31:0] bitcast_ln103_6_fu_1749_p1; -wire [31:0] bitcast_ln103_5_fu_1746_p1; -wire [31:0] bitcast_ln103_4_fu_1743_p1; -wire [31:0] bitcast_ln103_3_fu_1740_p1; -wire [31:0] bitcast_ln103_2_fu_1737_p1; -wire [31:0] bitcast_ln103_1_fu_1734_p1; -wire [31:0] bitcast_ln103_fu_1731_p1; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg ap_loop_exit_ready_pp0_iter1_reg; -reg ap_loop_exit_ready_pp0_iter2_reg; -reg ap_loop_exit_ready_pp0_iter3_reg; -reg ap_loop_exit_ready_pp0_iter4_reg; -reg ap_loop_exit_ready_pp0_iter5_reg; -reg ap_loop_exit_ready_pp0_iter6_reg; -reg ap_loop_exit_ready_pp0_iter7_reg; -reg ap_loop_exit_ready_pp0_iter8_reg; -reg ap_loop_exit_ready_pp0_iter9_reg; -reg ap_loop_exit_ready_pp0_iter10_reg; -reg ap_loop_exit_ready_pp0_iter11_reg; -reg ap_loop_exit_ready_pp0_iter12_reg; -reg ap_loop_exit_ready_pp0_iter13_reg; -reg ap_loop_exit_ready_pp0_iter14_reg; -reg ap_loop_exit_ready_pp0_iter15_reg; -reg ap_loop_exit_ready_pp0_iter16_reg; -reg ap_loop_exit_ready_pp0_iter17_reg; -reg ap_loop_exit_ready_pp0_iter18_reg; -reg ap_loop_exit_ready_pp0_iter19_reg; -reg ap_loop_exit_ready_pp0_iter20_reg; -reg ap_loop_exit_ready_pp0_iter21_reg; -reg ap_loop_exit_ready_pp0_iter22_reg; -reg ap_loop_exit_ready_pp0_iter23_reg; -reg ap_loop_exit_ready_pp0_iter24_reg; -reg ap_loop_exit_ready_pp0_iter25_reg; -reg ap_loop_exit_ready_pp0_iter26_reg; -reg ap_loop_exit_ready_pp0_iter27_reg; -reg ap_loop_exit_ready_pp0_iter28_reg; -reg ap_loop_exit_ready_pp0_iter29_reg; -reg ap_loop_exit_ready_pp0_iter30_reg; -reg ap_loop_exit_ready_pp0_iter31_reg; -reg ap_loop_exit_ready_pp0_iter32_reg; -reg ap_loop_exit_ready_pp0_iter33_reg; -reg ap_loop_exit_ready_pp0_iter34_reg; -reg ap_loop_exit_ready_pp0_iter35_reg; -reg ap_loop_exit_ready_pp0_iter36_reg; -reg ap_loop_exit_ready_pp0_iter37_reg; -reg ap_loop_exit_ready_pp0_iter38_reg; -reg ap_loop_exit_ready_pp0_iter39_reg; -reg ap_loop_exit_ready_pp0_iter40_reg; -reg ap_loop_exit_ready_pp0_iter41_reg; -reg ap_loop_exit_ready_pp0_iter42_reg; -reg ap_loop_exit_ready_pp0_iter43_reg; -reg ap_loop_exit_ready_pp0_iter44_reg; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_enable_reg_pp0_iter2 = 1'b0; -#0 ap_enable_reg_pp0_iter3 = 1'b0; -#0 ap_enable_reg_pp0_iter4 = 1'b0; -#0 ap_enable_reg_pp0_iter5 = 1'b0; -#0 ap_enable_reg_pp0_iter6 = 1'b0; -#0 ap_enable_reg_pp0_iter7 = 1'b0; -#0 ap_enable_reg_pp0_iter8 = 1'b0; -#0 ap_enable_reg_pp0_iter9 = 1'b0; -#0 ap_enable_reg_pp0_iter10 = 1'b0; -#0 ap_enable_reg_pp0_iter11 = 1'b0; -#0 ap_enable_reg_pp0_iter12 = 1'b0; -#0 ap_enable_reg_pp0_iter13 = 1'b0; -#0 ap_enable_reg_pp0_iter14 = 1'b0; -#0 ap_enable_reg_pp0_iter15 = 1'b0; -#0 ap_enable_reg_pp0_iter16 = 1'b0; -#0 ap_enable_reg_pp0_iter17 = 1'b0; -#0 ap_enable_reg_pp0_iter18 = 1'b0; -#0 ap_enable_reg_pp0_iter19 = 1'b0; -#0 ap_enable_reg_pp0_iter20 = 1'b0; -#0 ap_enable_reg_pp0_iter21 = 1'b0; -#0 ap_enable_reg_pp0_iter22 = 1'b0; -#0 ap_enable_reg_pp0_iter23 = 1'b0; -#0 ap_enable_reg_pp0_iter24 = 1'b0; -#0 ap_enable_reg_pp0_iter25 = 1'b0; -#0 ap_enable_reg_pp0_iter26 = 1'b0; -#0 ap_enable_reg_pp0_iter27 = 1'b0; -#0 ap_enable_reg_pp0_iter28 = 1'b0; -#0 ap_enable_reg_pp0_iter29 = 1'b0; -#0 ap_enable_reg_pp0_iter30 = 1'b0; -#0 ap_enable_reg_pp0_iter31 = 1'b0; -#0 ap_enable_reg_pp0_iter32 = 1'b0; -#0 ap_enable_reg_pp0_iter33 = 1'b0; -#0 ap_enable_reg_pp0_iter34 = 1'b0; -#0 ap_enable_reg_pp0_iter35 = 1'b0; -#0 ap_enable_reg_pp0_iter36 = 1'b0; -#0 ap_enable_reg_pp0_iter37 = 1'b0; -#0 ap_enable_reg_pp0_iter38 = 1'b0; -#0 ap_enable_reg_pp0_iter39 = 1'b0; -#0 ap_enable_reg_pp0_iter40 = 1'b0; -#0 ap_enable_reg_pp0_iter41 = 1'b0; -#0 ap_enable_reg_pp0_iter42 = 1'b0; -#0 ap_enable_reg_pp0_iter43 = 1'b0; -#0 ap_enable_reg_pp0_iter44 = 1'b0; -#0 ap_enable_reg_pp0_iter45 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_223( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_223_in_1_0_0), - .in_0_0_1(bitcast_ln91_fu_518_p1), - .in_0_0_m1(bitcast_ln93_fu_535_p1), - .in_0_0_0(bitcast_ln95_fu_545_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_223_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_223_in_m1_0_0), - .in_0_1_0(bitcast_ln101_fu_573_p1), - .ap_return(grp_HEAT3D_stencil_kernel_fu_223_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_223_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_234( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_234_in_1_0_0), - .in_0_0_1(bitcast_ln91_1_fu_604_p1), - .in_0_0_m1(bitcast_ln95_fu_545_p1), - .in_0_0_0(bitcast_ln91_fu_518_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_234_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_234_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_234_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_234_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_234_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_245( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_245_in_1_0_0), - .in_0_0_1(bitcast_ln91_2_fu_681_p1), - .in_0_0_m1(bitcast_ln91_fu_518_p1), - .in_0_0_0(bitcast_ln91_1_fu_604_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_245_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_245_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_245_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_245_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_245_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_256( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_256_in_1_0_0), - .in_0_0_1(bitcast_ln91_3_fu_758_p1), - .in_0_0_m1(bitcast_ln91_1_fu_604_p1), - .in_0_0_0(bitcast_ln91_2_fu_681_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_256_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_256_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_256_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_256_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_256_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_267( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_267_in_1_0_0), - .in_0_0_1(bitcast_ln91_4_fu_835_p1), - .in_0_0_m1(bitcast_ln91_2_fu_681_p1), - .in_0_0_0(bitcast_ln91_3_fu_758_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_267_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_267_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_267_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_267_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_267_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_278( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_278_in_1_0_0), - .in_0_0_1(bitcast_ln91_5_fu_912_p1), - .in_0_0_m1(bitcast_ln91_3_fu_758_p1), - .in_0_0_0(bitcast_ln91_4_fu_835_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_278_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_278_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_278_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_278_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_278_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_289( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_289_in_1_0_0), - .in_0_0_1(bitcast_ln91_6_fu_989_p1), - .in_0_0_m1(bitcast_ln91_4_fu_835_p1), - .in_0_0_0(bitcast_ln91_5_fu_912_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_289_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_289_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_289_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_289_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_289_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_300( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_300_in_1_0_0), - .in_0_0_1(bitcast_ln91_7_fu_1066_p1), - .in_0_0_m1(bitcast_ln91_5_fu_912_p1), - .in_0_0_0(bitcast_ln91_6_fu_989_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_300_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_300_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_300_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_300_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_300_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_311( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_311_in_1_0_0), - .in_0_0_1(bitcast_ln91_8_fu_1143_p1), - .in_0_0_m1(bitcast_ln91_6_fu_989_p1), - .in_0_0_0(bitcast_ln91_7_fu_1066_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_311_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_311_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_311_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_311_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_311_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_322( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_322_in_1_0_0), - .in_0_0_1(bitcast_ln91_9_fu_1220_p1), - .in_0_0_m1(bitcast_ln91_7_fu_1066_p1), - .in_0_0_0(bitcast_ln91_8_fu_1143_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_322_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_322_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_322_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_322_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_322_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_333( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_333_in_1_0_0), - .in_0_0_1(bitcast_ln91_10_fu_1297_p1), - .in_0_0_m1(bitcast_ln91_8_fu_1143_p1), - .in_0_0_0(bitcast_ln91_9_fu_1220_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_333_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_333_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_333_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_333_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_333_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_344( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_344_in_1_0_0), - .in_0_0_1(bitcast_ln91_11_fu_1374_p1), - .in_0_0_m1(bitcast_ln91_9_fu_1220_p1), - .in_0_0_0(bitcast_ln91_10_fu_1297_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_344_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_344_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_344_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_344_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_344_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_355( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_355_in_1_0_0), - .in_0_0_1(bitcast_ln91_12_fu_1451_p1), - .in_0_0_m1(bitcast_ln91_10_fu_1297_p1), - .in_0_0_0(bitcast_ln91_11_fu_1374_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_355_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_355_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_355_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_355_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_355_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_366( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_366_in_1_0_0), - .in_0_0_1(bitcast_ln91_13_fu_1528_p1), - .in_0_0_m1(bitcast_ln91_11_fu_1374_p1), - .in_0_0_0(bitcast_ln91_12_fu_1451_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_366_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_366_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_366_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_366_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_366_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_377( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_377_in_1_0_0), - .in_0_0_1(bitcast_ln91_14_fu_1605_p1), - .in_0_0_m1(bitcast_ln91_12_fu_1451_p1), - .in_0_0_0(bitcast_ln91_13_fu_1528_p1), - .in_0_m1_0(grp_HEAT3D_stencil_kernel_fu_377_in_0_m1_0), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_377_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_377_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_377_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_377_ap_ce) -); - -HEAT3D_HEAT3D_stencil_kernel grp_HEAT3D_stencil_kernel_fu_388( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .in_1_0_0(grp_HEAT3D_stencil_kernel_fu_388_in_1_0_0), - .in_0_0_1(bitcast_ln101_fu_573_p1), - .in_0_0_m1(bitcast_ln91_13_fu_1528_p1), - .in_0_0_0(bitcast_ln91_14_fu_1605_p1), - .in_0_m1_0(bitcast_ln93_fu_535_p1), - .in_m1_0_0(grp_HEAT3D_stencil_kernel_fu_388_in_m1_0_0), - .in_0_1_0(grp_HEAT3D_stencil_kernel_fu_388_in_0_1_0), - .ap_return(grp_HEAT3D_stencil_kernel_fu_388_ap_return), - .ap_ce(grp_HEAT3D_stencil_kernel_fu_388_ap_ce) -); - -HEAT3D_HLS_REG_ap_uint_512_s p_1_HLS_REG_ap_uint_512_s_fu_399( - .ap_ready(p_1_HLS_REG_ap_uint_512_s_fu_399_ap_ready), - .in_r(p_Val2_3_fu_140), - .ap_return(p_1_HLS_REG_ap_uint_512_s_fu_399_ap_return) -); - -HEAT3D_HLS_REG_ap_uint_512_s ref_tmp1_HLS_REG_ap_uint_512_s_fu_405( - .ap_ready(ref_tmp1_HLS_REG_ap_uint_512_s_fu_405_ap_ready), - .in_r(p_Val2_2_fu_136), - .ap_return(ref_tmp1_HLS_REG_ap_uint_512_s_fu_405_ap_return) -); - -HEAT3D_HLS_REG_ap_uint_512_s ref_tmp2_HLS_REG_ap_uint_512_s_fu_410( - .ap_ready(ref_tmp2_HLS_REG_ap_uint_512_s_fu_410_ap_ready), - .in_r(p_Val2_4_fu_144), - .ap_return(ref_tmp2_HLS_REG_ap_uint_512_s_fu_410_ap_return) -); - -HEAT3D_HLS_REG_ap_uint_512_s p_0_HLS_REG_ap_uint_512_s_fu_415( - .ap_ready(p_0_HLS_REG_ap_uint_512_s_fu_415_ap_ready), - .in_r(p_Val2_1_fu_128), - .ap_return(p_0_HLS_REG_ap_uint_512_s_fu_415_ap_return) -); - -HEAT3D_HLS_REG_ap_uint_512_s in_block_16_V_1_HLS_REG_ap_uint_512_s_fu_421( - .ap_ready(in_block_16_V_1_HLS_REG_ap_uint_512_s_fu_421_ap_ready), - .in_r(in_block_16_V_1_HLS_REG_ap_uint_512_s_fu_421_in_r), - .ap_return(in_block_16_V_1_HLS_REG_ap_uint_512_s_fu_421_ap_return) -); - -HEAT3D_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready_pp0_iter44_reg == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter10 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter11 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter12 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter13 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter14 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter15 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter16 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter17 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter18 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter19 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter2 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter20 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter21 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter22 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter23 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter24 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter25 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter25 <= ap_enable_reg_pp0_iter24; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter26 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter26 <= ap_enable_reg_pp0_iter25; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter27 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter27 <= ap_enable_reg_pp0_iter26; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter28 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter28 <= ap_enable_reg_pp0_iter27; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter29 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter29 <= ap_enable_reg_pp0_iter28; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter3 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter30 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter30 <= ap_enable_reg_pp0_iter29; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter31 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter31 <= ap_enable_reg_pp0_iter30; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter32 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter32 <= ap_enable_reg_pp0_iter31; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter33 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter33 <= ap_enable_reg_pp0_iter32; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter34 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter34 <= ap_enable_reg_pp0_iter33; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter35 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter35 <= ap_enable_reg_pp0_iter34; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter36 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter36 <= ap_enable_reg_pp0_iter35; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter37 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter37 <= ap_enable_reg_pp0_iter36; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter38 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter38 <= ap_enable_reg_pp0_iter37; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter39 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter39 <= ap_enable_reg_pp0_iter38; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter4 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter40 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter40 <= ap_enable_reg_pp0_iter39; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter41 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter41 <= ap_enable_reg_pp0_iter40; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter42 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter42 <= ap_enable_reg_pp0_iter41; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter43 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter43 <= ap_enable_reg_pp0_iter42; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter44 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter44 <= ap_enable_reg_pp0_iter43; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter45 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter45 <= ap_enable_reg_pp0_iter44; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter5 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter6 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter7 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter8 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter9 <= 1'b0; - end else begin - if ((1'b0 == ap_block_pp0_stage0_subdone)) begin - ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if (((icmp_ln73_fu_463_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin - i_4_fu_132 <= add_ln73_1_fu_469_p2; - end else if ((ap_loop_init == 1'b1)) begin - i_4_fu_132 <= 31'd0; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - p_Val2_1_fu_128 <= in_block_16_V; - end else if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin - p_Val2_1_fu_128 <= in_block_16_V_1_HLS_REG_ap_uint_512_s_fu_421_ap_return; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - p_Val2_2_fu_136 <= in_block_0; - end else if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin - p_Val2_2_fu_136 <= ref_tmp2_HLS_REG_ap_uint_512_s_fu_410_ap_return; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - p_Val2_3_fu_140 <= in_block_m1; - end else if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin - p_Val2_3_fu_140 <= ref_tmp1_HLS_REG_ap_uint_512_s_fu_405_ap_return; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - p_Val2_4_fu_144 <= in_block_1; - end else if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin - p_Val2_4_fu_144 <= in_stream_2_to_15_dout; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - p_Val2_s_fu_124 <= in_block_m16_V; - end else if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin - p_Val2_s_fu_124 <= in_stream_m15_to_m2_dout; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b0 == ap_block_pp0_stage0_11001)) begin - ap_loop_exit_ready_pp0_iter10_reg <= ap_loop_exit_ready_pp0_iter9_reg; - ap_loop_exit_ready_pp0_iter11_reg <= ap_loop_exit_ready_pp0_iter10_reg; - ap_loop_exit_ready_pp0_iter12_reg <= ap_loop_exit_ready_pp0_iter11_reg; - ap_loop_exit_ready_pp0_iter13_reg <= ap_loop_exit_ready_pp0_iter12_reg; - ap_loop_exit_ready_pp0_iter14_reg <= ap_loop_exit_ready_pp0_iter13_reg; - ap_loop_exit_ready_pp0_iter15_reg <= ap_loop_exit_ready_pp0_iter14_reg; - ap_loop_exit_ready_pp0_iter16_reg <= ap_loop_exit_ready_pp0_iter15_reg; - ap_loop_exit_ready_pp0_iter17_reg <= ap_loop_exit_ready_pp0_iter16_reg; - ap_loop_exit_ready_pp0_iter18_reg <= ap_loop_exit_ready_pp0_iter17_reg; - ap_loop_exit_ready_pp0_iter19_reg <= ap_loop_exit_ready_pp0_iter18_reg; - ap_loop_exit_ready_pp0_iter20_reg <= ap_loop_exit_ready_pp0_iter19_reg; - ap_loop_exit_ready_pp0_iter21_reg <= ap_loop_exit_ready_pp0_iter20_reg; - ap_loop_exit_ready_pp0_iter22_reg <= ap_loop_exit_ready_pp0_iter21_reg; - ap_loop_exit_ready_pp0_iter23_reg <= ap_loop_exit_ready_pp0_iter22_reg; - ap_loop_exit_ready_pp0_iter24_reg <= ap_loop_exit_ready_pp0_iter23_reg; - ap_loop_exit_ready_pp0_iter25_reg <= ap_loop_exit_ready_pp0_iter24_reg; - ap_loop_exit_ready_pp0_iter26_reg <= ap_loop_exit_ready_pp0_iter25_reg; - ap_loop_exit_ready_pp0_iter27_reg <= ap_loop_exit_ready_pp0_iter26_reg; - ap_loop_exit_ready_pp0_iter28_reg <= ap_loop_exit_ready_pp0_iter27_reg; - ap_loop_exit_ready_pp0_iter29_reg <= ap_loop_exit_ready_pp0_iter28_reg; - ap_loop_exit_ready_pp0_iter30_reg <= ap_loop_exit_ready_pp0_iter29_reg; - ap_loop_exit_ready_pp0_iter31_reg <= ap_loop_exit_ready_pp0_iter30_reg; - ap_loop_exit_ready_pp0_iter32_reg <= ap_loop_exit_ready_pp0_iter31_reg; - ap_loop_exit_ready_pp0_iter33_reg <= ap_loop_exit_ready_pp0_iter32_reg; - ap_loop_exit_ready_pp0_iter34_reg <= ap_loop_exit_ready_pp0_iter33_reg; - ap_loop_exit_ready_pp0_iter35_reg <= ap_loop_exit_ready_pp0_iter34_reg; - ap_loop_exit_ready_pp0_iter36_reg <= ap_loop_exit_ready_pp0_iter35_reg; - ap_loop_exit_ready_pp0_iter37_reg <= ap_loop_exit_ready_pp0_iter36_reg; - ap_loop_exit_ready_pp0_iter38_reg <= ap_loop_exit_ready_pp0_iter37_reg; - ap_loop_exit_ready_pp0_iter39_reg <= ap_loop_exit_ready_pp0_iter38_reg; - ap_loop_exit_ready_pp0_iter3_reg <= ap_loop_exit_ready_pp0_iter2_reg; - ap_loop_exit_ready_pp0_iter40_reg <= ap_loop_exit_ready_pp0_iter39_reg; - ap_loop_exit_ready_pp0_iter41_reg <= ap_loop_exit_ready_pp0_iter40_reg; - ap_loop_exit_ready_pp0_iter42_reg <= ap_loop_exit_ready_pp0_iter41_reg; - ap_loop_exit_ready_pp0_iter43_reg <= ap_loop_exit_ready_pp0_iter42_reg; - ap_loop_exit_ready_pp0_iter44_reg <= ap_loop_exit_ready_pp0_iter43_reg; - ap_loop_exit_ready_pp0_iter4_reg <= ap_loop_exit_ready_pp0_iter3_reg; - ap_loop_exit_ready_pp0_iter5_reg <= ap_loop_exit_ready_pp0_iter4_reg; - ap_loop_exit_ready_pp0_iter6_reg <= ap_loop_exit_ready_pp0_iter5_reg; - ap_loop_exit_ready_pp0_iter7_reg <= ap_loop_exit_ready_pp0_iter6_reg; - ap_loop_exit_ready_pp0_iter8_reg <= ap_loop_exit_ready_pp0_iter7_reg; - ap_loop_exit_ready_pp0_iter9_reg <= ap_loop_exit_ready_pp0_iter8_reg; - result_10_reg_2346 <= grp_HEAT3D_stencil_kernel_fu_333_ap_return; - result_11_reg_2351 <= grp_HEAT3D_stencil_kernel_fu_344_ap_return; - result_12_reg_2356 <= grp_HEAT3D_stencil_kernel_fu_355_ap_return; - result_13_reg_2361 <= grp_HEAT3D_stencil_kernel_fu_366_ap_return; - result_14_reg_2366 <= grp_HEAT3D_stencil_kernel_fu_377_ap_return; - result_15_reg_2371 <= grp_HEAT3D_stencil_kernel_fu_388_ap_return; - result_1_reg_2301 <= grp_HEAT3D_stencil_kernel_fu_234_ap_return; - result_2_reg_2306 <= grp_HEAT3D_stencil_kernel_fu_245_ap_return; - result_3_reg_2311 <= grp_HEAT3D_stencil_kernel_fu_256_ap_return; - result_4_reg_2316 <= grp_HEAT3D_stencil_kernel_fu_267_ap_return; - result_5_reg_2321 <= grp_HEAT3D_stencil_kernel_fu_278_ap_return; - result_6_reg_2326 <= grp_HEAT3D_stencil_kernel_fu_289_ap_return; - result_7_reg_2331 <= grp_HEAT3D_stencil_kernel_fu_300_ap_return; - result_8_reg_2336 <= grp_HEAT3D_stencil_kernel_fu_311_ap_return; - result_9_reg_2341 <= grp_HEAT3D_stencil_kernel_fu_322_ap_return; - result_reg_2296 <= grp_HEAT3D_stencil_kernel_fu_223_ap_return; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_loop_exit_ready_pp0_iter1_reg <= ap_loop_exit_ready; - ap_loop_exit_ready_pp0_iter2_reg <= ap_loop_exit_ready_pp0_iter1_reg; - end -end - -always @ (*) begin - if (((icmp_ln73_fu_463_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready_pp0_iter44_reg == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_start_int == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_idle_pp0 == 1'b1))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter26 == 1'b0) & (ap_enable_reg_pp0_iter25 == 1'b0) & (ap_enable_reg_pp0_iter24 == 1'b0) & (ap_enable_reg_pp0_iter23 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b0) & (ap_enable_reg_pp0_iter44 == 1'b0) & (ap_enable_reg_pp0_iter43 == 1'b0) & (ap_enable_reg_pp0_iter42 == 1'b0) & (ap_enable_reg_pp0_iter41 == 1'b0) & (ap_enable_reg_pp0_iter40 == 1'b0) & (ap_enable_reg_pp0_iter39 == 1'b0) & (ap_enable_reg_pp0_iter38 == 1'b0) & (ap_enable_reg_pp0_iter37 == 1'b0) & (ap_enable_reg_pp0_iter36 == 1'b0) & (ap_enable_reg_pp0_iter35 == 1'b0) & (ap_enable_reg_pp0_iter34 == 1'b0) & (ap_enable_reg_pp0_iter33 == 1'b0) & (ap_enable_reg_pp0_iter32 == 1'b0) & (ap_enable_reg_pp0_iter31 == 1'b0) & (ap_enable_reg_pp0_iter30 == 1'b0) & (ap_enable_reg_pp0_iter29 == 1'b0) & (ap_enable_reg_pp0_iter28 == 1'b0) & (ap_enable_reg_pp0_iter27 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_init == 1'b1) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_sig_allocacmp_i_4_load = 31'd0; - end else begin - ap_sig_allocacmp_i_4_load = i_4_fu_132; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp97) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_223_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_223_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp108) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_234_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_234_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp119) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_245_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_245_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp130) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_256_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_256_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp141) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_267_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_267_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp152) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_278_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_278_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp163) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_289_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_289_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp174) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_300_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_300_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp185) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_311_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_311_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp196) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_322_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_322_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp207) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_333_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_333_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp218) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_344_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_344_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp229) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_355_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_355_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp240) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_366_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_366_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp251) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_377_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_377_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp258) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - grp_HEAT3D_stencil_kernel_fu_388_ap_ce = 1'b1; - end else begin - grp_HEAT3D_stencil_kernel_fu_388_ap_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_s_blk_n = in_s_empty_n; - end else begin - in_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_s_read = 1'b1; - end else begin - in_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_2_to_15_i_blk_n = in_stream_2_to_15_empty_n; - end else begin - in_stream_2_to_15_i_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_2_to_15_o_blk_n = in_stream_2_to_15_full_n; - end else begin - in_stream_2_to_15_o_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_2_to_15_read = 1'b1; - end else begin - in_stream_2_to_15_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_2_to_15_write = 1'b1; - end else begin - in_stream_2_to_15_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_m15_to_m2_i_blk_n = in_stream_m15_to_m2_empty_n; - end else begin - in_stream_m15_to_m2_i_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_m15_to_m2_o_blk_n = in_stream_m15_to_m2_full_n; - end else begin - in_stream_m15_to_m2_o_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_m15_to_m2_read = 1'b1; - end else begin - in_stream_m15_to_m2_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_m15_to_m2_write = 1'b1; - end else begin - in_stream_m15_to_m2_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter45 == 1'b1))) begin - out_r_blk_n = out_r_full_n; - end else begin - out_r_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter45 == 1'b1))) begin - out_r_write = 1'b1; - end else begin - out_r_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign add_ln73_1_fu_469_p2 = (ap_sig_allocacmp_i_4_load + 31'd1); - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage0_01001 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp108 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp119 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp130 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp141 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp152 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp163 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp174 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp185 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp196 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp207 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp218 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp229 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp240 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp251 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp258 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001_ignoreCallOp97 = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -always @ (*) begin - ap_block_pp0_stage0_subdone = (((out_r_full_n == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)))); -end - -assign ap_block_state10_pp0_stage0_iter9 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28_ignore_call93 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call105 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call117 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call129 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call141 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call153 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call165 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call177 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call189 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call197 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call21 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call33 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call45 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call57 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call69 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call81 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1_ignore_call93 = ((in_s_empty_n == 1'b0) | (in_stream_2_to_15_full_n == 1'b0) | (in_stream_2_to_15_empty_n == 1'b0) | (in_stream_m15_to_m2_full_n == 1'b0) | (in_stream_m15_to_m2_empty_n == 1'b0)); -end - -assign ap_block_state30_pp0_stage0_iter29 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state44_pp0_stage0_iter43_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state45_pp0_stage0_iter44_ignore_call93 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call105 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call117 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call129 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call141 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call153 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call165 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call177 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call189 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call197 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call21 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call33 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call45 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call57 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call69 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call81 = (out_r_full_n == 1'b0); -end - -always @ (*) begin - ap_block_state46_pp0_stage0_iter45_ignore_call93 = (out_r_full_n == 1'b0); -end - -assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call105 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call117 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call129 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call141 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call153 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call165 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call177 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call189 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call197 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call21 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call33 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call45 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call57 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call69 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call81 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8_ignore_call93 = ~(1'b1 == 1'b1); - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -assign bitcast_ln101_fu_573_p1 = temp_in_0_1_0_15_fu_569_p1; - -assign bitcast_ln103_10_fu_1761_p1 = result_10_reg_2346; - -assign bitcast_ln103_11_fu_1764_p1 = result_11_reg_2351; - -assign bitcast_ln103_12_fu_1767_p1 = result_12_reg_2356; - -assign bitcast_ln103_13_fu_1770_p1 = result_13_reg_2361; - -assign bitcast_ln103_14_fu_1773_p1 = result_14_reg_2366; - -assign bitcast_ln103_15_fu_1776_p1 = result_15_reg_2371; - -assign bitcast_ln103_1_fu_1734_p1 = result_1_reg_2301; - -assign bitcast_ln103_2_fu_1737_p1 = result_2_reg_2306; - -assign bitcast_ln103_3_fu_1740_p1 = result_3_reg_2311; - -assign bitcast_ln103_4_fu_1743_p1 = result_4_reg_2316; - -assign bitcast_ln103_5_fu_1746_p1 = result_5_reg_2321; - -assign bitcast_ln103_6_fu_1749_p1 = result_6_reg_2326; - -assign bitcast_ln103_7_fu_1752_p1 = result_7_reg_2331; - -assign bitcast_ln103_8_fu_1755_p1 = result_8_reg_2336; - -assign bitcast_ln103_9_fu_1758_p1 = result_9_reg_2341; - -assign bitcast_ln103_fu_1731_p1 = result_reg_2296; - -assign bitcast_ln91_10_fu_1297_p1 = temp_in_0_0_1_18_fu_1287_p4; - -assign bitcast_ln91_11_fu_1374_p1 = temp_in_0_0_1_19_fu_1364_p4; - -assign bitcast_ln91_12_fu_1451_p1 = temp_in_0_0_1_20_fu_1441_p4; - -assign bitcast_ln91_13_fu_1528_p1 = temp_in_0_0_1_21_fu_1518_p4; - -assign bitcast_ln91_14_fu_1605_p1 = temp_in_0_0_1_22_fu_1595_p4; - -assign bitcast_ln91_1_fu_604_p1 = temp_in_0_0_1_9_fu_594_p4; - -assign bitcast_ln91_2_fu_681_p1 = temp_in_0_0_1_10_fu_671_p4; - -assign bitcast_ln91_3_fu_758_p1 = temp_in_0_0_1_11_fu_748_p4; - -assign bitcast_ln91_4_fu_835_p1 = temp_in_0_0_1_12_fu_825_p4; - -assign bitcast_ln91_5_fu_912_p1 = temp_in_0_0_1_13_fu_902_p4; - -assign bitcast_ln91_6_fu_989_p1 = temp_in_0_0_1_14_fu_979_p4; - -assign bitcast_ln91_7_fu_1066_p1 = temp_in_0_0_1_15_fu_1056_p4; - -assign bitcast_ln91_8_fu_1143_p1 = temp_in_0_0_1_16_fu_1133_p4; - -assign bitcast_ln91_9_fu_1220_p1 = temp_in_0_0_1_17_fu_1210_p4; - -assign bitcast_ln91_fu_518_p1 = temp_in_0_0_1_fu_508_p4; - -assign bitcast_ln93_fu_535_p1 = temp_in_0_0_m1_fu_525_p4; - -assign bitcast_ln95_fu_545_p1 = temp_in_0_0_0_1_fu_541_p1; - -assign grp_HEAT3D_stencil_kernel_fu_223_in_0_m1_0 = temp_in_0_m1_0_fu_551_p1; - -assign grp_HEAT3D_stencil_kernel_fu_223_in_1_0_0 = temp_in_1_0_0_fu_499_p1; - -assign grp_HEAT3D_stencil_kernel_fu_223_in_m1_0_0 = temp_in_m1_0_0_fu_560_p1; - -assign grp_HEAT3D_stencil_kernel_fu_234_in_0_1_0 = temp_in_0_1_0_1_fu_641_p4; - -assign grp_HEAT3D_stencil_kernel_fu_234_in_0_m1_0 = temp_in_0_m1_0_1_fu_611_p4; - -assign grp_HEAT3D_stencil_kernel_fu_234_in_1_0_0 = temp_in_1_0_0_1_fu_579_p4; - -assign grp_HEAT3D_stencil_kernel_fu_234_in_m1_0_0 = temp_in_m1_0_0_1_fu_626_p4; - -assign grp_HEAT3D_stencil_kernel_fu_245_in_0_1_0 = temp_in_0_1_0_2_fu_718_p4; - -assign grp_HEAT3D_stencil_kernel_fu_245_in_0_m1_0 = temp_in_0_m1_0_2_fu_688_p4; - -assign grp_HEAT3D_stencil_kernel_fu_245_in_1_0_0 = temp_in_1_0_0_2_fu_656_p4; - -assign grp_HEAT3D_stencil_kernel_fu_245_in_m1_0_0 = temp_in_m1_0_0_2_fu_703_p4; - -assign grp_HEAT3D_stencil_kernel_fu_256_in_0_1_0 = temp_in_0_1_0_3_fu_795_p4; - -assign grp_HEAT3D_stencil_kernel_fu_256_in_0_m1_0 = temp_in_0_m1_0_3_fu_765_p4; - -assign grp_HEAT3D_stencil_kernel_fu_256_in_1_0_0 = temp_in_1_0_0_3_fu_733_p4; - -assign grp_HEAT3D_stencil_kernel_fu_256_in_m1_0_0 = temp_in_m1_0_0_3_fu_780_p4; - -assign grp_HEAT3D_stencil_kernel_fu_267_in_0_1_0 = temp_in_0_1_0_4_fu_872_p4; - -assign grp_HEAT3D_stencil_kernel_fu_267_in_0_m1_0 = temp_in_0_m1_0_4_fu_842_p4; - -assign grp_HEAT3D_stencil_kernel_fu_267_in_1_0_0 = temp_in_1_0_0_4_fu_810_p4; - -assign grp_HEAT3D_stencil_kernel_fu_267_in_m1_0_0 = temp_in_m1_0_0_4_fu_857_p4; - -assign grp_HEAT3D_stencil_kernel_fu_278_in_0_1_0 = temp_in_0_1_0_5_fu_949_p4; - -assign grp_HEAT3D_stencil_kernel_fu_278_in_0_m1_0 = temp_in_0_m1_0_5_fu_919_p4; - -assign grp_HEAT3D_stencil_kernel_fu_278_in_1_0_0 = temp_in_1_0_0_5_fu_887_p4; - -assign grp_HEAT3D_stencil_kernel_fu_278_in_m1_0_0 = temp_in_m1_0_0_5_fu_934_p4; - -assign grp_HEAT3D_stencil_kernel_fu_289_in_0_1_0 = temp_in_0_1_0_6_fu_1026_p4; - -assign grp_HEAT3D_stencil_kernel_fu_289_in_0_m1_0 = temp_in_0_m1_0_6_fu_996_p4; - -assign grp_HEAT3D_stencil_kernel_fu_289_in_1_0_0 = temp_in_1_0_0_6_fu_964_p4; - -assign grp_HEAT3D_stencil_kernel_fu_289_in_m1_0_0 = temp_in_m1_0_0_6_fu_1011_p4; - -assign grp_HEAT3D_stencil_kernel_fu_300_in_0_1_0 = temp_in_0_1_0_7_fu_1103_p4; - -assign grp_HEAT3D_stencil_kernel_fu_300_in_0_m1_0 = temp_in_0_m1_0_7_fu_1073_p4; - -assign grp_HEAT3D_stencil_kernel_fu_300_in_1_0_0 = temp_in_1_0_0_7_fu_1041_p4; - -assign grp_HEAT3D_stencil_kernel_fu_300_in_m1_0_0 = temp_in_m1_0_0_7_fu_1088_p4; - -assign grp_HEAT3D_stencil_kernel_fu_311_in_0_1_0 = temp_in_0_1_0_8_fu_1180_p4; - -assign grp_HEAT3D_stencil_kernel_fu_311_in_0_m1_0 = temp_in_0_m1_0_8_fu_1150_p4; - -assign grp_HEAT3D_stencil_kernel_fu_311_in_1_0_0 = temp_in_1_0_0_8_fu_1118_p4; - -assign grp_HEAT3D_stencil_kernel_fu_311_in_m1_0_0 = temp_in_m1_0_0_8_fu_1165_p4; - -assign grp_HEAT3D_stencil_kernel_fu_322_in_0_1_0 = temp_in_0_1_0_9_fu_1257_p4; - -assign grp_HEAT3D_stencil_kernel_fu_322_in_0_m1_0 = temp_in_0_m1_0_9_fu_1227_p4; - -assign grp_HEAT3D_stencil_kernel_fu_322_in_1_0_0 = temp_in_1_0_0_9_fu_1195_p4; - -assign grp_HEAT3D_stencil_kernel_fu_322_in_m1_0_0 = temp_in_m1_0_0_9_fu_1242_p4; - -assign grp_HEAT3D_stencil_kernel_fu_333_in_0_1_0 = temp_in_0_1_0_10_fu_1334_p4; - -assign grp_HEAT3D_stencil_kernel_fu_333_in_0_m1_0 = temp_in_0_m1_0_10_fu_1304_p4; - -assign grp_HEAT3D_stencil_kernel_fu_333_in_1_0_0 = temp_in_1_0_0_10_fu_1272_p4; - -assign grp_HEAT3D_stencil_kernel_fu_333_in_m1_0_0 = temp_in_m1_0_0_10_fu_1319_p4; - -assign grp_HEAT3D_stencil_kernel_fu_344_in_0_1_0 = temp_in_0_1_0_11_fu_1411_p4; - -assign grp_HEAT3D_stencil_kernel_fu_344_in_0_m1_0 = temp_in_0_m1_0_11_fu_1381_p4; - -assign grp_HEAT3D_stencil_kernel_fu_344_in_1_0_0 = temp_in_1_0_0_11_fu_1349_p4; - -assign grp_HEAT3D_stencil_kernel_fu_344_in_m1_0_0 = temp_in_m1_0_0_11_fu_1396_p4; - -assign grp_HEAT3D_stencil_kernel_fu_355_in_0_1_0 = temp_in_0_1_0_12_fu_1488_p4; - -assign grp_HEAT3D_stencil_kernel_fu_355_in_0_m1_0 = temp_in_0_m1_0_12_fu_1458_p4; - -assign grp_HEAT3D_stencil_kernel_fu_355_in_1_0_0 = temp_in_1_0_0_12_fu_1426_p4; - -assign grp_HEAT3D_stencil_kernel_fu_355_in_m1_0_0 = temp_in_m1_0_0_12_fu_1473_p4; - -assign grp_HEAT3D_stencil_kernel_fu_366_in_0_1_0 = temp_in_0_1_0_13_fu_1565_p4; - -assign grp_HEAT3D_stencil_kernel_fu_366_in_0_m1_0 = temp_in_0_m1_0_13_fu_1535_p4; - -assign grp_HEAT3D_stencil_kernel_fu_366_in_1_0_0 = temp_in_1_0_0_13_fu_1503_p4; - -assign grp_HEAT3D_stencil_kernel_fu_366_in_m1_0_0 = temp_in_m1_0_0_13_fu_1550_p4; - -assign grp_HEAT3D_stencil_kernel_fu_377_in_0_1_0 = temp_in_0_1_0_14_fu_1641_p4; - -assign grp_HEAT3D_stencil_kernel_fu_377_in_0_m1_0 = temp_in_0_m1_0_14_fu_1611_p4; - -assign grp_HEAT3D_stencil_kernel_fu_377_in_1_0_0 = temp_in_1_0_0_14_fu_1580_p4; - -assign grp_HEAT3D_stencil_kernel_fu_377_in_m1_0_0 = temp_in_m1_0_0_14_fu_1626_p4; - -assign grp_HEAT3D_stencil_kernel_fu_388_in_0_1_0 = temp_in_0_1_0_fu_1686_p4; - -assign grp_HEAT3D_stencil_kernel_fu_388_in_1_0_0 = temp_in_1_0_0_15_fu_1656_p4; - -assign grp_HEAT3D_stencil_kernel_fu_388_in_m1_0_0 = temp_in_m1_0_0_15_fu_1671_p4; - -assign icmp_ln73_fu_463_p2 = (($signed(zext_ln73_fu_459_p1) < $signed(add_ln73)) ? 1'b1 : 1'b0); - -assign in_block_16_V_1_HLS_REG_ap_uint_512_s_fu_421_in_r = in_s_dout[511:0]; - -assign in_stream_2_to_15_din = p_0_HLS_REG_ap_uint_512_s_fu_415_ap_return; - -assign in_stream_m15_to_m2_din = p_1_HLS_REG_ap_uint_512_s_fu_399_ap_return; - -assign out_r_din = {{{{{{{{{{{{{{{{{{{{{{{{{{{{{{{{1'd0}, {bitcast_ln103_15_fu_1776_p1}}}, {bitcast_ln103_14_fu_1773_p1}}}, {bitcast_ln103_13_fu_1770_p1}}}, {bitcast_ln103_12_fu_1767_p1}}}, {bitcast_ln103_11_fu_1764_p1}}}, {bitcast_ln103_10_fu_1761_p1}}}, {bitcast_ln103_9_fu_1758_p1}}}, {bitcast_ln103_8_fu_1755_p1}}}, {bitcast_ln103_7_fu_1752_p1}}}, {bitcast_ln103_6_fu_1749_p1}}}, {bitcast_ln103_5_fu_1746_p1}}}, {bitcast_ln103_4_fu_1743_p1}}}, {bitcast_ln103_3_fu_1740_p1}}}, {bitcast_ln103_2_fu_1737_p1}}}, {bitcast_ln103_1_fu_1734_p1}}}, {bitcast_ln103_fu_1731_p1}}; - -assign temp_in_0_0_0_1_fu_541_p1 = p_Val2_2_fu_136[31:0]; - -assign temp_in_0_0_1_10_fu_671_p4 = {{p_Val2_2_fu_136[127:96]}}; - -assign temp_in_0_0_1_11_fu_748_p4 = {{p_Val2_2_fu_136[159:128]}}; - -assign temp_in_0_0_1_12_fu_825_p4 = {{p_Val2_2_fu_136[191:160]}}; - -assign temp_in_0_0_1_13_fu_902_p4 = {{p_Val2_2_fu_136[223:192]}}; - -assign temp_in_0_0_1_14_fu_979_p4 = {{p_Val2_2_fu_136[255:224]}}; - -assign temp_in_0_0_1_15_fu_1056_p4 = {{p_Val2_2_fu_136[287:256]}}; - -assign temp_in_0_0_1_16_fu_1133_p4 = {{p_Val2_2_fu_136[319:288]}}; - -assign temp_in_0_0_1_17_fu_1210_p4 = {{p_Val2_2_fu_136[351:320]}}; - -assign temp_in_0_0_1_18_fu_1287_p4 = {{p_Val2_2_fu_136[383:352]}}; - -assign temp_in_0_0_1_19_fu_1364_p4 = {{p_Val2_2_fu_136[415:384]}}; - -assign temp_in_0_0_1_20_fu_1441_p4 = {{p_Val2_2_fu_136[447:416]}}; - -assign temp_in_0_0_1_21_fu_1518_p4 = {{p_Val2_2_fu_136[479:448]}}; - -assign temp_in_0_0_1_22_fu_1595_p4 = {{p_Val2_2_fu_136[511:480]}}; - -assign temp_in_0_0_1_9_fu_594_p4 = {{p_Val2_2_fu_136[95:64]}}; - -assign temp_in_0_0_1_fu_508_p4 = {{p_Val2_2_fu_136[63:32]}}; - -assign temp_in_0_0_m1_fu_525_p4 = {{p_Val2_3_fu_140[511:480]}}; - -assign temp_in_0_1_0_10_fu_1334_p4 = {{p_Val2_4_fu_144[351:320]}}; - -assign temp_in_0_1_0_11_fu_1411_p4 = {{p_Val2_4_fu_144[383:352]}}; - -assign temp_in_0_1_0_12_fu_1488_p4 = {{p_Val2_4_fu_144[415:384]}}; - -assign temp_in_0_1_0_13_fu_1565_p4 = {{p_Val2_4_fu_144[447:416]}}; - -assign temp_in_0_1_0_14_fu_1641_p4 = {{p_Val2_4_fu_144[479:448]}}; - -assign temp_in_0_1_0_15_fu_569_p1 = p_Val2_4_fu_144[31:0]; - -assign temp_in_0_1_0_1_fu_641_p4 = {{p_Val2_4_fu_144[63:32]}}; - -assign temp_in_0_1_0_2_fu_718_p4 = {{p_Val2_4_fu_144[95:64]}}; - -assign temp_in_0_1_0_3_fu_795_p4 = {{p_Val2_4_fu_144[127:96]}}; - -assign temp_in_0_1_0_4_fu_872_p4 = {{p_Val2_4_fu_144[159:128]}}; - -assign temp_in_0_1_0_5_fu_949_p4 = {{p_Val2_4_fu_144[191:160]}}; - -assign temp_in_0_1_0_6_fu_1026_p4 = {{p_Val2_4_fu_144[223:192]}}; - -assign temp_in_0_1_0_7_fu_1103_p4 = {{p_Val2_4_fu_144[255:224]}}; - -assign temp_in_0_1_0_8_fu_1180_p4 = {{p_Val2_4_fu_144[287:256]}}; - -assign temp_in_0_1_0_9_fu_1257_p4 = {{p_Val2_4_fu_144[319:288]}}; - -assign temp_in_0_1_0_fu_1686_p4 = {{p_Val2_4_fu_144[511:480]}}; - -assign temp_in_0_m1_0_10_fu_1304_p4 = {{p_Val2_3_fu_140[351:320]}}; - -assign temp_in_0_m1_0_11_fu_1381_p4 = {{p_Val2_3_fu_140[383:352]}}; - -assign temp_in_0_m1_0_12_fu_1458_p4 = {{p_Val2_3_fu_140[415:384]}}; - -assign temp_in_0_m1_0_13_fu_1535_p4 = {{p_Val2_3_fu_140[447:416]}}; - -assign temp_in_0_m1_0_14_fu_1611_p4 = {{p_Val2_3_fu_140[479:448]}}; - -assign temp_in_0_m1_0_1_fu_611_p4 = {{p_Val2_3_fu_140[63:32]}}; - -assign temp_in_0_m1_0_2_fu_688_p4 = {{p_Val2_3_fu_140[95:64]}}; - -assign temp_in_0_m1_0_3_fu_765_p4 = {{p_Val2_3_fu_140[127:96]}}; - -assign temp_in_0_m1_0_4_fu_842_p4 = {{p_Val2_3_fu_140[159:128]}}; - -assign temp_in_0_m1_0_5_fu_919_p4 = {{p_Val2_3_fu_140[191:160]}}; - -assign temp_in_0_m1_0_6_fu_996_p4 = {{p_Val2_3_fu_140[223:192]}}; - -assign temp_in_0_m1_0_7_fu_1073_p4 = {{p_Val2_3_fu_140[255:224]}}; - -assign temp_in_0_m1_0_8_fu_1150_p4 = {{p_Val2_3_fu_140[287:256]}}; - -assign temp_in_0_m1_0_9_fu_1227_p4 = {{p_Val2_3_fu_140[319:288]}}; - -assign temp_in_0_m1_0_fu_551_p1 = p_Val2_3_fu_140[31:0]; - -assign temp_in_1_0_0_10_fu_1272_p4 = {{p_Val2_1_fu_128[351:320]}}; - -assign temp_in_1_0_0_11_fu_1349_p4 = {{p_Val2_1_fu_128[383:352]}}; - -assign temp_in_1_0_0_12_fu_1426_p4 = {{p_Val2_1_fu_128[415:384]}}; - -assign temp_in_1_0_0_13_fu_1503_p4 = {{p_Val2_1_fu_128[447:416]}}; - -assign temp_in_1_0_0_14_fu_1580_p4 = {{p_Val2_1_fu_128[479:448]}}; - -assign temp_in_1_0_0_15_fu_1656_p4 = {{p_Val2_1_fu_128[511:480]}}; - -assign temp_in_1_0_0_1_fu_579_p4 = {{p_Val2_1_fu_128[63:32]}}; - -assign temp_in_1_0_0_2_fu_656_p4 = {{p_Val2_1_fu_128[95:64]}}; - -assign temp_in_1_0_0_3_fu_733_p4 = {{p_Val2_1_fu_128[127:96]}}; - -assign temp_in_1_0_0_4_fu_810_p4 = {{p_Val2_1_fu_128[159:128]}}; - -assign temp_in_1_0_0_5_fu_887_p4 = {{p_Val2_1_fu_128[191:160]}}; - -assign temp_in_1_0_0_6_fu_964_p4 = {{p_Val2_1_fu_128[223:192]}}; - -assign temp_in_1_0_0_7_fu_1041_p4 = {{p_Val2_1_fu_128[255:224]}}; - -assign temp_in_1_0_0_8_fu_1118_p4 = {{p_Val2_1_fu_128[287:256]}}; - -assign temp_in_1_0_0_9_fu_1195_p4 = {{p_Val2_1_fu_128[319:288]}}; - -assign temp_in_1_0_0_fu_499_p1 = p_Val2_1_fu_128[31:0]; - -assign temp_in_m1_0_0_10_fu_1319_p4 = {{p_Val2_s_fu_124[351:320]}}; - -assign temp_in_m1_0_0_11_fu_1396_p4 = {{p_Val2_s_fu_124[383:352]}}; - -assign temp_in_m1_0_0_12_fu_1473_p4 = {{p_Val2_s_fu_124[415:384]}}; - -assign temp_in_m1_0_0_13_fu_1550_p4 = {{p_Val2_s_fu_124[447:416]}}; - -assign temp_in_m1_0_0_14_fu_1626_p4 = {{p_Val2_s_fu_124[479:448]}}; - -assign temp_in_m1_0_0_15_fu_1671_p4 = {{p_Val2_s_fu_124[511:480]}}; - -assign temp_in_m1_0_0_1_fu_626_p4 = {{p_Val2_s_fu_124[63:32]}}; - -assign temp_in_m1_0_0_2_fu_703_p4 = {{p_Val2_s_fu_124[95:64]}}; - -assign temp_in_m1_0_0_3_fu_780_p4 = {{p_Val2_s_fu_124[127:96]}}; - -assign temp_in_m1_0_0_4_fu_857_p4 = {{p_Val2_s_fu_124[159:128]}}; - -assign temp_in_m1_0_0_5_fu_934_p4 = {{p_Val2_s_fu_124[191:160]}}; - -assign temp_in_m1_0_0_6_fu_1011_p4 = {{p_Val2_s_fu_124[223:192]}}; - -assign temp_in_m1_0_0_7_fu_1088_p4 = {{p_Val2_s_fu_124[255:224]}}; - -assign temp_in_m1_0_0_8_fu_1165_p4 = {{p_Val2_s_fu_124[287:256]}}; - -assign temp_in_m1_0_0_9_fu_1242_p4 = {{p_Val2_s_fu_124[319:288]}}; - -assign temp_in_m1_0_0_fu_560_p1 = p_Val2_s_fu_124[31:0]; - -assign zext_ln73_fu_459_p1 = ap_sig_allocacmp_i_4_load; - -endmodule //HEAT3D_HEAT3D_Pipeline_MAJOR_LOOP diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_116_3.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_116_3.v deleted file mode 100644 index 30e9826e..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_116_3.v +++ /dev/null @@ -1,231 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_116_3 ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - in_stream_m15_to_m2_dout, - in_stream_m15_to_m2_empty_n, - in_stream_m15_to_m2_read -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [511:0] in_stream_m15_to_m2_dout; -input in_stream_m15_to_m2_empty_n; -output in_stream_m15_to_m2_read; - -reg ap_idle; -reg in_stream_m15_to_m2_read; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -reg ap_block_state2_pp0_stage0_iter1; -reg ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln116_fu_50_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -reg in_stream_m15_to_m2_blk_n; -wire ap_block_pp0_stage0; -reg [3:0] i_5_fu_32; -wire [3:0] i_7_fu_56_p2; -wire ap_loop_init; -reg ap_block_pp0_stage0_11001; -reg [3:0] ap_sig_allocacmp_i; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -HEAT3D_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if (((icmp_ln116_fu_50_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin - i_5_fu_32 <= i_7_fu_56_p2; - end else if ((ap_loop_init == 1'b1)) begin - i_5_fu_32 <= 4'd0; - end - end -end - -always @ (*) begin - if (((icmp_ln116_fu_50_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_start_int == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_init == 1'b1) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_sig_allocacmp_i = 4'd0; - end else begin - ap_sig_allocacmp_i = i_5_fu_32; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_m15_to_m2_blk_n = in_stream_m15_to_m2_empty_n; - end else begin - in_stream_m15_to_m2_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_m15_to_m2_read = 1'b1; - end else begin - in_stream_m15_to_m2_read = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage0_11001 = ((in_stream_m15_to_m2_empty_n == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -always @ (*) begin - ap_block_pp0_stage0_subdone = ((in_stream_m15_to_m2_empty_n == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1 = (in_stream_m15_to_m2_empty_n == 1'b0); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -assign i_7_fu_56_p2 = (ap_sig_allocacmp_i + 4'd1); - -assign icmp_ln116_fu_50_p2 = ((ap_sig_allocacmp_i == 4'd14) ? 1'b1 : 1'b0); - -endmodule //HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_116_3 diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_121_4.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_121_4.v deleted file mode 100644 index 2fdfd046..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_121_4.v +++ /dev/null @@ -1,231 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_121_4 ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - in_stream_2_to_15_dout, - in_stream_2_to_15_empty_n, - in_stream_2_to_15_read -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [511:0] in_stream_2_to_15_dout; -input in_stream_2_to_15_empty_n; -output in_stream_2_to_15_read; - -reg ap_idle; -reg in_stream_2_to_15_read; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -reg ap_block_state2_pp0_stage0_iter1; -reg ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln121_fu_50_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -reg in_stream_2_to_15_blk_n; -wire ap_block_pp0_stage0; -reg [3:0] i_fu_32; -wire [3:0] i_6_fu_56_p2; -wire ap_loop_init; -reg ap_block_pp0_stage0_11001; -reg [3:0] ap_sig_allocacmp_i_5; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -HEAT3D_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if (((icmp_ln121_fu_50_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin - i_fu_32 <= i_6_fu_56_p2; - end else if ((ap_loop_init == 1'b1)) begin - i_fu_32 <= 4'd0; - end - end -end - -always @ (*) begin - if (((icmp_ln121_fu_50_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_start_int == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_init == 1'b1) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_sig_allocacmp_i_5 = 4'd0; - end else begin - ap_sig_allocacmp_i_5 = i_fu_32; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_2_to_15_blk_n = in_stream_2_to_15_empty_n; - end else begin - in_stream_2_to_15_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_2_to_15_read = 1'b1; - end else begin - in_stream_2_to_15_read = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage0_11001 = ((in_stream_2_to_15_empty_n == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -always @ (*) begin - ap_block_pp0_stage0_subdone = ((in_stream_2_to_15_empty_n == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)); -end - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1 = (in_stream_2_to_15_empty_n == 1'b0); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -assign i_6_fu_56_p2 = (ap_sig_allocacmp_i_5 + 4'd1); - -assign icmp_ln121_fu_50_p2 = ((ap_sig_allocacmp_i_5 == 4'd14) ? 1'b1 : 1'b0); - -endmodule //HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_121_4 diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_62_1.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_62_1.v deleted file mode 100644 index f4008adf..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_62_1.v +++ /dev/null @@ -1,262 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_62_1 ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - in_s_dout, - in_s_empty_n, - in_s_read, - in_stream_m15_to_m2_din, - in_stream_m15_to_m2_full_n, - in_stream_m15_to_m2_write -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [512:0] in_s_dout; -input in_s_empty_n; -output in_s_read; -output [511:0] in_stream_m15_to_m2_din; -input in_stream_m15_to_m2_full_n; -output in_stream_m15_to_m2_write; - -reg ap_idle; -reg in_s_read; -reg in_stream_m15_to_m2_write; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -reg ap_block_state2_pp0_stage0_iter1; -reg ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln62_fu_61_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -reg in_s_blk_n; -wire ap_block_pp0_stage0; -reg in_stream_m15_to_m2_blk_n; -reg [3:0] i_fu_36; -wire [3:0] i_4_fu_67_p2; -wire ap_loop_init; -reg ap_block_pp0_stage0_11001; -reg [3:0] ap_sig_allocacmp_i_3; -reg ap_block_pp0_stage0_01001; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -HEAT3D_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if (((icmp_ln62_fu_61_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin - i_fu_36 <= i_4_fu_67_p2; - end else if ((ap_loop_init == 1'b1)) begin - i_fu_36 <= 4'd1; - end - end -end - -always @ (*) begin - if (((icmp_ln62_fu_61_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_start_int == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_init == 1'b1) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_sig_allocacmp_i_3 = 4'd1; - end else begin - ap_sig_allocacmp_i_3 = i_fu_36; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_s_blk_n = in_s_empty_n; - end else begin - in_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_s_read = 1'b1; - end else begin - in_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_m15_to_m2_blk_n = in_stream_m15_to_m2_full_n; - end else begin - in_stream_m15_to_m2_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_m15_to_m2_write = 1'b1; - end else begin - in_stream_m15_to_m2_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage0_01001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_stream_m15_to_m2_full_n == 1'b0) | (in_s_empty_n == 1'b0))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_stream_m15_to_m2_full_n == 1'b0) | (in_s_empty_n == 1'b0))); -end - -always @ (*) begin - ap_block_pp0_stage0_subdone = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_stream_m15_to_m2_full_n == 1'b0) | (in_s_empty_n == 1'b0))); -end - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1 = ((in_stream_m15_to_m2_full_n == 1'b0) | (in_s_empty_n == 1'b0)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -assign i_4_fu_67_p2 = (ap_sig_allocacmp_i_3 + 4'd1); - -assign icmp_ln62_fu_61_p2 = ((ap_sig_allocacmp_i_3 == 4'd15) ? 1'b1 : 1'b0); - -assign in_stream_m15_to_m2_din = in_s_dout[511:0]; - -endmodule //HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_62_1 diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_68_2.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_68_2.v deleted file mode 100644 index 456fe6dc..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_68_2.v +++ /dev/null @@ -1,262 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_68_2 ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - in_s_dout, - in_s_empty_n, - in_s_read, - in_stream_2_to_15_din, - in_stream_2_to_15_full_n, - in_stream_2_to_15_write -); - -parameter ap_ST_fsm_pp0_stage0 = 1'd1; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [512:0] in_s_dout; -input in_s_empty_n; -output in_s_read; -output [511:0] in_stream_2_to_15_din; -input in_stream_2_to_15_full_n; -output in_stream_2_to_15_write; - -reg ap_idle; -reg in_s_read; -reg in_stream_2_to_15_write; - -(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -wire ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_block_state1_pp0_stage0_iter0; -reg ap_block_state2_pp0_stage0_iter1; -reg ap_block_pp0_stage0_subdone; -wire [0:0] icmp_ln68_fu_63_p2; -reg ap_condition_exit_pp0_iter0_stage0; -wire ap_loop_exit_ready; -reg ap_ready_int; -reg in_s_blk_n; -wire ap_block_pp0_stage0; -reg in_stream_2_to_15_blk_n; -reg [5:0] i_fu_38; -wire [5:0] i_2_fu_69_p2; -wire ap_loop_init; -reg ap_block_pp0_stage0_11001; -reg [5:0] ap_sig_allocacmp_i_1; -reg ap_block_pp0_stage0_01001; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [0:0] ap_NS_fsm; -wire ap_enable_pp0; -wire ap_start_int; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 1'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_done_reg = 1'b0; -end - -HEAT3D_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_enable_reg_pp0_iter1 <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if (((icmp_ln68_fu_63_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin - i_fu_38 <= i_2_fu_69_p2; - end else if ((ap_loop_init == 1'b1)) begin - i_fu_38 <= 6'd18; - end - end -end - -always @ (*) begin - if (((icmp_ln68_fu_63_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_condition_exit_pp0_iter0_stage0 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage0 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if (((ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_start_int == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_init == 1'b1) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_sig_allocacmp_i_1 = 6'd18; - end else begin - ap_sig_allocacmp_i_1 = i_fu_38; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_s_blk_n = in_s_empty_n; - end else begin - in_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_s_read = 1'b1; - end else begin - in_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_2_to_15_blk_n = in_stream_2_to_15_full_n; - end else begin - in_stream_2_to_15_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - in_stream_2_to_15_write = 1'b1; - end else begin - in_stream_2_to_15_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage0_01001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_stream_2_to_15_full_n == 1'b0) | (in_s_empty_n == 1'b0))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_stream_2_to_15_full_n == 1'b0) | (in_s_empty_n == 1'b0))); -end - -always @ (*) begin - ap_block_pp0_stage0_subdone = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((in_stream_2_to_15_full_n == 1'b0) | (in_s_empty_n == 1'b0))); -end - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_state2_pp0_stage0_iter1 = ((in_stream_2_to_15_full_n == 1'b0) | (in_s_empty_n == 1'b0)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_enable_reg_pp0_iter0 = ap_start_int; - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0; - -assign i_2_fu_69_p2 = (ap_sig_allocacmp_i_1 + 6'd1); - -assign icmp_ln68_fu_63_p2 = ((ap_sig_allocacmp_i_1 == 6'd32) ? 1'b1 : 1'b0); - -assign in_stream_2_to_15_din = in_s_dout[511:0]; - -endmodule //HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_68_2 diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_stencil_kernel.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_stencil_kernel.v deleted file mode 100644 index e96d479d..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HEAT3D_stencil_kernel.v +++ /dev/null @@ -1,746 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module HEAT3D_HEAT3D_stencil_kernel ( - ap_clk, - ap_rst, - in_1_0_0, - in_0_0_1, - in_0_0_m1, - in_0_0_0, - in_0_m1_0, - in_m1_0_0, - in_0_1_0, - ap_return, - ap_ce -); - - -input ap_clk; -input ap_rst; -input [31:0] in_1_0_0; -input [31:0] in_0_0_1; -input [31:0] in_0_0_m1; -input [31:0] in_0_0_0; -input [31:0] in_0_m1_0; -input [31:0] in_m1_0_0; -input [31:0] in_0_1_0; -output [31:0] ap_return; -input ap_ce; - -reg[31:0] ap_return; - -reg [31:0] in_0_1_0_read_reg_119; -wire ap_block_state1_pp0_stage0_iter0; -wire ap_block_state2_pp0_stage0_iter1; -wire ap_block_state3_pp0_stage0_iter2; -wire ap_block_state4_pp0_stage0_iter3; -wire ap_block_state5_pp0_stage0_iter4; -wire ap_block_state6_pp0_stage0_iter5; -wire ap_block_state7_pp0_stage0_iter6; -wire ap_block_state8_pp0_stage0_iter7; -wire ap_block_state9_pp0_stage0_iter8; -wire ap_block_state10_pp0_stage0_iter9; -wire ap_block_state11_pp0_stage0_iter10; -wire ap_block_state12_pp0_stage0_iter11; -wire ap_block_state13_pp0_stage0_iter12; -wire ap_block_state14_pp0_stage0_iter13; -wire ap_block_state15_pp0_stage0_iter14; -wire ap_block_state16_pp0_stage0_iter15; -wire ap_block_state17_pp0_stage0_iter16; -wire ap_block_state18_pp0_stage0_iter17; -wire ap_block_state19_pp0_stage0_iter18; -wire ap_block_state20_pp0_stage0_iter19; -wire ap_block_state21_pp0_stage0_iter20; -wire ap_block_state22_pp0_stage0_iter21; -wire ap_block_state23_pp0_stage0_iter22; -wire ap_block_state24_pp0_stage0_iter23; -wire ap_block_state25_pp0_stage0_iter24; -wire ap_block_state26_pp0_stage0_iter25; -wire ap_block_state27_pp0_stage0_iter26; -wire ap_block_state28_pp0_stage0_iter27; -wire ap_block_state29_pp0_stage0_iter28; -wire ap_block_state30_pp0_stage0_iter29; -wire ap_block_state31_pp0_stage0_iter30; -wire ap_block_state32_pp0_stage0_iter31; -wire ap_block_state33_pp0_stage0_iter32; -wire ap_block_state34_pp0_stage0_iter33; -wire ap_block_state35_pp0_stage0_iter34; -wire ap_block_state36_pp0_stage0_iter35; -wire ap_block_state37_pp0_stage0_iter36; -wire ap_block_state38_pp0_stage0_iter37; -wire ap_block_state39_pp0_stage0_iter38; -wire ap_block_state40_pp0_stage0_iter39; -wire ap_block_state41_pp0_stage0_iter40; -wire ap_block_state42_pp0_stage0_iter41; -wire ap_block_state43_pp0_stage0_iter42; -wire ap_block_pp0_stage0_11001; -reg [31:0] in_0_1_0_read_reg_119_pp0_iter1_reg; -reg [31:0] in_0_1_0_read_reg_119_pp0_iter2_reg; -reg [31:0] in_0_1_0_read_reg_119_pp0_iter3_reg; -reg [31:0] in_m1_0_0_read_reg_124; -reg [31:0] in_m1_0_0_read_reg_124_pp0_iter1_reg; -reg [31:0] in_m1_0_0_read_reg_124_pp0_iter2_reg; -reg [31:0] in_m1_0_0_read_reg_124_pp0_iter3_reg; -reg [31:0] in_m1_0_0_read_reg_124_pp0_iter4_reg; -reg [31:0] in_m1_0_0_read_reg_124_pp0_iter5_reg; -reg [31:0] in_m1_0_0_read_reg_124_pp0_iter6_reg; -reg [31:0] in_m1_0_0_read_reg_124_pp0_iter7_reg; -reg [31:0] in_m1_0_0_read_reg_124_pp0_iter8_reg; -reg [31:0] in_m1_0_0_read_reg_124_pp0_iter9_reg; -reg [31:0] in_m1_0_0_read_reg_124_pp0_iter10_reg; -reg [31:0] in_0_m1_0_read_reg_129; -reg [31:0] in_0_m1_0_read_reg_129_pp0_iter1_reg; -reg [31:0] in_0_m1_0_read_reg_129_pp0_iter2_reg; -reg [31:0] in_0_m1_0_read_reg_129_pp0_iter3_reg; -reg [31:0] in_0_m1_0_read_reg_129_pp0_iter4_reg; -reg [31:0] in_0_m1_0_read_reg_129_pp0_iter5_reg; -reg [31:0] in_0_m1_0_read_reg_129_pp0_iter6_reg; -reg [31:0] in_0_m1_0_read_reg_129_pp0_iter7_reg; -reg [31:0] in_0_m1_0_read_reg_129_pp0_iter8_reg; -reg [31:0] in_0_m1_0_read_reg_129_pp0_iter9_reg; -reg [31:0] in_0_m1_0_read_reg_129_pp0_iter10_reg; -reg [31:0] in_0_0_0_read_reg_134; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter1_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter2_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter3_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter4_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter5_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter6_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter7_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter8_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter9_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter10_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter11_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter12_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter13_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter14_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter15_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter16_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter17_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter18_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter19_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter20_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter21_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter22_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter23_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter24_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter25_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter26_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter27_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter28_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter29_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter30_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter31_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter32_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter33_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter34_reg; -reg [31:0] in_0_0_0_read_reg_134_pp0_iter35_reg; -reg [31:0] in_0_0_m1_read_reg_140; -reg [31:0] in_0_0_m1_read_reg_140_pp0_iter1_reg; -reg [31:0] in_0_0_m1_read_reg_140_pp0_iter2_reg; -reg [31:0] in_0_0_m1_read_reg_140_pp0_iter3_reg; -reg [31:0] in_0_0_m1_read_reg_140_pp0_iter4_reg; -reg [31:0] in_0_0_m1_read_reg_140_pp0_iter5_reg; -reg [31:0] in_0_0_m1_read_reg_140_pp0_iter6_reg; -reg [31:0] in_0_0_m1_read_reg_140_pp0_iter7_reg; -reg [31:0] in_0_0_m1_read_reg_140_pp0_iter8_reg; -reg [31:0] in_0_0_m1_read_reg_140_pp0_iter9_reg; -reg [31:0] in_0_0_m1_read_reg_140_pp0_iter10_reg; -reg [31:0] in_0_0_1_read_reg_145; -reg [31:0] in_0_0_1_read_reg_145_pp0_iter1_reg; -reg [31:0] in_0_0_1_read_reg_145_pp0_iter2_reg; -reg [31:0] in_0_0_1_read_reg_145_pp0_iter3_reg; -reg [31:0] in_1_0_0_read_reg_150; -reg [31:0] in_1_0_0_read_reg_150_pp0_iter1_reg; -reg [31:0] in_1_0_0_read_reg_150_pp0_iter2_reg; -reg [31:0] in_1_0_0_read_reg_150_pp0_iter3_reg; -wire [31:0] grp_fu_98_p2; -reg [31:0] mul_reg_155; -wire [31:0] grp_fu_62_p2; -reg [31:0] sub_reg_162; -wire [31:0] grp_fu_66_p2; -reg [31:0] sub2_reg_167; -wire [31:0] grp_fu_70_p2; -reg [31:0] sub6_reg_172; -wire [31:0] grp_fu_74_p2; -reg [31:0] add_reg_177; -wire [31:0] grp_fu_78_p2; -reg [31:0] add3_reg_182; -wire [31:0] grp_fu_82_p2; -reg [31:0] add7_reg_187; -reg [31:0] add7_reg_187_pp0_iter18_reg; -reg [31:0] add7_reg_187_pp0_iter19_reg; -reg [31:0] add7_reg_187_pp0_iter20_reg; -reg [31:0] add7_reg_187_pp0_iter21_reg; -reg [31:0] add7_reg_187_pp0_iter22_reg; -reg [31:0] add7_reg_187_pp0_iter23_reg; -reg [31:0] add7_reg_187_pp0_iter24_reg; -wire [31:0] grp_fu_104_p2; -reg [31:0] cal1_reg_192; -wire [31:0] grp_fu_109_p2; -reg [31:0] cal2_reg_197; -wire [31:0] grp_fu_114_p2; -reg [31:0] cal3_reg_202; -wire [31:0] grp_fu_86_p2; -reg [31:0] add9_reg_207; -wire [31:0] grp_fu_90_p2; -reg [31:0] add1_reg_212; -wire ap_block_pp0_stage0; -reg grp_fu_62_ce; -reg grp_fu_66_ce; -reg grp_fu_70_ce; -reg grp_fu_74_ce; -reg grp_fu_78_ce; -reg grp_fu_82_ce; -reg grp_fu_86_ce; -reg grp_fu_90_ce; -wire [31:0] grp_fu_94_p2; -reg grp_fu_94_ce; -reg grp_fu_98_ce; -reg grp_fu_104_ce; -reg grp_fu_109_ce; -reg grp_fu_114_ce; -reg ap_ce_reg; -reg [31:0] in_1_0_0_int_reg; -reg [31:0] in_0_0_1_int_reg; -reg [31:0] in_0_0_m1_int_reg; -reg [31:0] in_0_0_0_int_reg; -reg [31:0] in_0_m1_0_int_reg; -reg [31:0] in_m1_0_0_int_reg; -reg [31:0] in_0_1_0_int_reg; -reg [31:0] ap_return_int_reg; - -HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fsub_32ns_32ns_32_7_full_dsp_0_U5( - .clk(ap_clk), - .reset(ap_rst), - .din0(in_1_0_0_read_reg_150_pp0_iter3_reg), - .din1(mul_reg_155), - .ce(grp_fu_62_ce), - .dout(grp_fu_62_p2) -); - -HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fsub_32ns_32ns_32_7_full_dsp_0_U6( - .clk(ap_clk), - .reset(ap_rst), - .din0(in_0_1_0_read_reg_119_pp0_iter3_reg), - .din1(mul_reg_155), - .ce(grp_fu_66_ce), - .dout(grp_fu_66_p2) -); - -HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fsub_32ns_32ns_32_7_full_dsp_0_U7( - .clk(ap_clk), - .reset(ap_rst), - .din0(in_0_0_1_read_reg_145_pp0_iter3_reg), - .din1(mul_reg_155), - .ce(grp_fu_70_ce), - .dout(grp_fu_70_p2) -); - -HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_0_U8( - .clk(ap_clk), - .reset(ap_rst), - .din0(sub_reg_162), - .din1(in_m1_0_0_read_reg_124_pp0_iter10_reg), - .ce(grp_fu_74_ce), - .dout(grp_fu_74_p2) -); - -HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_0_U9( - .clk(ap_clk), - .reset(ap_rst), - .din0(sub2_reg_167), - .din1(in_0_m1_0_read_reg_129_pp0_iter10_reg), - .ce(grp_fu_78_ce), - .dout(grp_fu_78_p2) -); - -HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_0_U10( - .clk(ap_clk), - .reset(ap_rst), - .din0(sub6_reg_172), - .din1(in_0_0_m1_read_reg_140_pp0_iter10_reg), - .ce(grp_fu_82_ce), - .dout(grp_fu_82_p2) -); - -HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_0_U11( - .clk(ap_clk), - .reset(ap_rst), - .din0(cal1_reg_192), - .din1(cal2_reg_197), - .ce(grp_fu_86_ce), - .dout(grp_fu_86_p2) -); - -HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_0_U12( - .clk(ap_clk), - .reset(ap_rst), - .din0(add9_reg_207), - .din1(cal3_reg_202), - .ce(grp_fu_90_ce), - .dout(grp_fu_90_p2) -); - -HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 7 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fadd_32ns_32ns_32_7_full_dsp_0_U13( - .clk(ap_clk), - .reset(ap_rst), - .din0(add1_reg_212), - .din1(in_0_0_0_read_reg_134_pp0_iter35_reg), - .ce(grp_fu_94_ce), - .dout(grp_fu_94_p2) -); - -HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_0_U14( - .clk(ap_clk), - .reset(ap_rst), - .din0(in_0_0_0_int_reg), - .din1(32'd1073741824), - .ce(grp_fu_98_ce), - .dout(grp_fu_98_p2) -); - -HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_0_U15( - .clk(ap_clk), - .reset(ap_rst), - .din0(add_reg_177), - .din1(32'd1040187392), - .ce(grp_fu_104_ce), - .dout(grp_fu_104_p2) -); - -HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_0_U16( - .clk(ap_clk), - .reset(ap_rst), - .din0(add3_reg_182), - .din1(32'd1040187392), - .ce(grp_fu_109_ce), - .dout(grp_fu_109_p2) -); - -HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0 #( - .ID( 1 ), - .NUM_STAGE( 4 ), - .din0_WIDTH( 32 ), - .din1_WIDTH( 32 ), - .dout_WIDTH( 32 )) -fmul_32ns_32ns_32_4_max_dsp_0_U17( - .clk(ap_clk), - .reset(ap_rst), - .din0(add7_reg_187_pp0_iter24_reg), - .din1(32'd1040187392), - .ce(grp_fu_114_ce), - .dout(grp_fu_114_p2) -); - -always @ (posedge ap_clk) begin - ap_ce_reg <= ap_ce; -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - add1_reg_212 <= grp_fu_90_p2; - add3_reg_182 <= grp_fu_78_p2; - add7_reg_187 <= grp_fu_82_p2; - add7_reg_187_pp0_iter18_reg <= add7_reg_187; - add7_reg_187_pp0_iter19_reg <= add7_reg_187_pp0_iter18_reg; - add7_reg_187_pp0_iter20_reg <= add7_reg_187_pp0_iter19_reg; - add7_reg_187_pp0_iter21_reg <= add7_reg_187_pp0_iter20_reg; - add7_reg_187_pp0_iter22_reg <= add7_reg_187_pp0_iter21_reg; - add7_reg_187_pp0_iter23_reg <= add7_reg_187_pp0_iter22_reg; - add7_reg_187_pp0_iter24_reg <= add7_reg_187_pp0_iter23_reg; - add9_reg_207 <= grp_fu_86_p2; - add_reg_177 <= grp_fu_74_p2; - cal1_reg_192 <= grp_fu_104_p2; - cal2_reg_197 <= grp_fu_109_p2; - cal3_reg_202 <= grp_fu_114_p2; - in_0_0_0_read_reg_134 <= in_0_0_0_int_reg; - in_0_0_0_read_reg_134_pp0_iter10_reg <= in_0_0_0_read_reg_134_pp0_iter9_reg; - in_0_0_0_read_reg_134_pp0_iter11_reg <= in_0_0_0_read_reg_134_pp0_iter10_reg; - in_0_0_0_read_reg_134_pp0_iter12_reg <= in_0_0_0_read_reg_134_pp0_iter11_reg; - in_0_0_0_read_reg_134_pp0_iter13_reg <= in_0_0_0_read_reg_134_pp0_iter12_reg; - in_0_0_0_read_reg_134_pp0_iter14_reg <= in_0_0_0_read_reg_134_pp0_iter13_reg; - in_0_0_0_read_reg_134_pp0_iter15_reg <= in_0_0_0_read_reg_134_pp0_iter14_reg; - in_0_0_0_read_reg_134_pp0_iter16_reg <= in_0_0_0_read_reg_134_pp0_iter15_reg; - in_0_0_0_read_reg_134_pp0_iter17_reg <= in_0_0_0_read_reg_134_pp0_iter16_reg; - in_0_0_0_read_reg_134_pp0_iter18_reg <= in_0_0_0_read_reg_134_pp0_iter17_reg; - in_0_0_0_read_reg_134_pp0_iter19_reg <= in_0_0_0_read_reg_134_pp0_iter18_reg; - in_0_0_0_read_reg_134_pp0_iter1_reg <= in_0_0_0_read_reg_134; - in_0_0_0_read_reg_134_pp0_iter20_reg <= in_0_0_0_read_reg_134_pp0_iter19_reg; - in_0_0_0_read_reg_134_pp0_iter21_reg <= in_0_0_0_read_reg_134_pp0_iter20_reg; - in_0_0_0_read_reg_134_pp0_iter22_reg <= in_0_0_0_read_reg_134_pp0_iter21_reg; - in_0_0_0_read_reg_134_pp0_iter23_reg <= in_0_0_0_read_reg_134_pp0_iter22_reg; - in_0_0_0_read_reg_134_pp0_iter24_reg <= in_0_0_0_read_reg_134_pp0_iter23_reg; - in_0_0_0_read_reg_134_pp0_iter25_reg <= in_0_0_0_read_reg_134_pp0_iter24_reg; - in_0_0_0_read_reg_134_pp0_iter26_reg <= in_0_0_0_read_reg_134_pp0_iter25_reg; - in_0_0_0_read_reg_134_pp0_iter27_reg <= in_0_0_0_read_reg_134_pp0_iter26_reg; - in_0_0_0_read_reg_134_pp0_iter28_reg <= in_0_0_0_read_reg_134_pp0_iter27_reg; - in_0_0_0_read_reg_134_pp0_iter29_reg <= in_0_0_0_read_reg_134_pp0_iter28_reg; - in_0_0_0_read_reg_134_pp0_iter2_reg <= in_0_0_0_read_reg_134_pp0_iter1_reg; - in_0_0_0_read_reg_134_pp0_iter30_reg <= in_0_0_0_read_reg_134_pp0_iter29_reg; - in_0_0_0_read_reg_134_pp0_iter31_reg <= in_0_0_0_read_reg_134_pp0_iter30_reg; - in_0_0_0_read_reg_134_pp0_iter32_reg <= in_0_0_0_read_reg_134_pp0_iter31_reg; - in_0_0_0_read_reg_134_pp0_iter33_reg <= in_0_0_0_read_reg_134_pp0_iter32_reg; - in_0_0_0_read_reg_134_pp0_iter34_reg <= in_0_0_0_read_reg_134_pp0_iter33_reg; - in_0_0_0_read_reg_134_pp0_iter35_reg <= in_0_0_0_read_reg_134_pp0_iter34_reg; - in_0_0_0_read_reg_134_pp0_iter3_reg <= in_0_0_0_read_reg_134_pp0_iter2_reg; - in_0_0_0_read_reg_134_pp0_iter4_reg <= in_0_0_0_read_reg_134_pp0_iter3_reg; - in_0_0_0_read_reg_134_pp0_iter5_reg <= in_0_0_0_read_reg_134_pp0_iter4_reg; - in_0_0_0_read_reg_134_pp0_iter6_reg <= in_0_0_0_read_reg_134_pp0_iter5_reg; - in_0_0_0_read_reg_134_pp0_iter7_reg <= in_0_0_0_read_reg_134_pp0_iter6_reg; - in_0_0_0_read_reg_134_pp0_iter8_reg <= in_0_0_0_read_reg_134_pp0_iter7_reg; - in_0_0_0_read_reg_134_pp0_iter9_reg <= in_0_0_0_read_reg_134_pp0_iter8_reg; - in_0_0_1_read_reg_145 <= in_0_0_1_int_reg; - in_0_0_1_read_reg_145_pp0_iter1_reg <= in_0_0_1_read_reg_145; - in_0_0_1_read_reg_145_pp0_iter2_reg <= in_0_0_1_read_reg_145_pp0_iter1_reg; - in_0_0_1_read_reg_145_pp0_iter3_reg <= in_0_0_1_read_reg_145_pp0_iter2_reg; - in_0_0_m1_read_reg_140 <= in_0_0_m1_int_reg; - in_0_0_m1_read_reg_140_pp0_iter10_reg <= in_0_0_m1_read_reg_140_pp0_iter9_reg; - in_0_0_m1_read_reg_140_pp0_iter1_reg <= in_0_0_m1_read_reg_140; - in_0_0_m1_read_reg_140_pp0_iter2_reg <= in_0_0_m1_read_reg_140_pp0_iter1_reg; - in_0_0_m1_read_reg_140_pp0_iter3_reg <= in_0_0_m1_read_reg_140_pp0_iter2_reg; - in_0_0_m1_read_reg_140_pp0_iter4_reg <= in_0_0_m1_read_reg_140_pp0_iter3_reg; - in_0_0_m1_read_reg_140_pp0_iter5_reg <= in_0_0_m1_read_reg_140_pp0_iter4_reg; - in_0_0_m1_read_reg_140_pp0_iter6_reg <= in_0_0_m1_read_reg_140_pp0_iter5_reg; - in_0_0_m1_read_reg_140_pp0_iter7_reg <= in_0_0_m1_read_reg_140_pp0_iter6_reg; - in_0_0_m1_read_reg_140_pp0_iter8_reg <= in_0_0_m1_read_reg_140_pp0_iter7_reg; - in_0_0_m1_read_reg_140_pp0_iter9_reg <= in_0_0_m1_read_reg_140_pp0_iter8_reg; - in_0_1_0_read_reg_119 <= in_0_1_0_int_reg; - in_0_1_0_read_reg_119_pp0_iter1_reg <= in_0_1_0_read_reg_119; - in_0_1_0_read_reg_119_pp0_iter2_reg <= in_0_1_0_read_reg_119_pp0_iter1_reg; - in_0_1_0_read_reg_119_pp0_iter3_reg <= in_0_1_0_read_reg_119_pp0_iter2_reg; - in_0_m1_0_read_reg_129 <= in_0_m1_0_int_reg; - in_0_m1_0_read_reg_129_pp0_iter10_reg <= in_0_m1_0_read_reg_129_pp0_iter9_reg; - in_0_m1_0_read_reg_129_pp0_iter1_reg <= in_0_m1_0_read_reg_129; - in_0_m1_0_read_reg_129_pp0_iter2_reg <= in_0_m1_0_read_reg_129_pp0_iter1_reg; - in_0_m1_0_read_reg_129_pp0_iter3_reg <= in_0_m1_0_read_reg_129_pp0_iter2_reg; - in_0_m1_0_read_reg_129_pp0_iter4_reg <= in_0_m1_0_read_reg_129_pp0_iter3_reg; - in_0_m1_0_read_reg_129_pp0_iter5_reg <= in_0_m1_0_read_reg_129_pp0_iter4_reg; - in_0_m1_0_read_reg_129_pp0_iter6_reg <= in_0_m1_0_read_reg_129_pp0_iter5_reg; - in_0_m1_0_read_reg_129_pp0_iter7_reg <= in_0_m1_0_read_reg_129_pp0_iter6_reg; - in_0_m1_0_read_reg_129_pp0_iter8_reg <= in_0_m1_0_read_reg_129_pp0_iter7_reg; - in_0_m1_0_read_reg_129_pp0_iter9_reg <= in_0_m1_0_read_reg_129_pp0_iter8_reg; - in_1_0_0_read_reg_150 <= in_1_0_0_int_reg; - in_1_0_0_read_reg_150_pp0_iter1_reg <= in_1_0_0_read_reg_150; - in_1_0_0_read_reg_150_pp0_iter2_reg <= in_1_0_0_read_reg_150_pp0_iter1_reg; - in_1_0_0_read_reg_150_pp0_iter3_reg <= in_1_0_0_read_reg_150_pp0_iter2_reg; - in_m1_0_0_read_reg_124 <= in_m1_0_0_int_reg; - in_m1_0_0_read_reg_124_pp0_iter10_reg <= in_m1_0_0_read_reg_124_pp0_iter9_reg; - in_m1_0_0_read_reg_124_pp0_iter1_reg <= in_m1_0_0_read_reg_124; - in_m1_0_0_read_reg_124_pp0_iter2_reg <= in_m1_0_0_read_reg_124_pp0_iter1_reg; - in_m1_0_0_read_reg_124_pp0_iter3_reg <= in_m1_0_0_read_reg_124_pp0_iter2_reg; - in_m1_0_0_read_reg_124_pp0_iter4_reg <= in_m1_0_0_read_reg_124_pp0_iter3_reg; - in_m1_0_0_read_reg_124_pp0_iter5_reg <= in_m1_0_0_read_reg_124_pp0_iter4_reg; - in_m1_0_0_read_reg_124_pp0_iter6_reg <= in_m1_0_0_read_reg_124_pp0_iter5_reg; - in_m1_0_0_read_reg_124_pp0_iter7_reg <= in_m1_0_0_read_reg_124_pp0_iter6_reg; - in_m1_0_0_read_reg_124_pp0_iter8_reg <= in_m1_0_0_read_reg_124_pp0_iter7_reg; - in_m1_0_0_read_reg_124_pp0_iter9_reg <= in_m1_0_0_read_reg_124_pp0_iter8_reg; - mul_reg_155 <= grp_fu_98_p2; - sub2_reg_167 <= grp_fu_66_p2; - sub6_reg_172 <= grp_fu_70_p2; - sub_reg_162 <= grp_fu_62_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_ce_reg)) begin - ap_return_int_reg <= grp_fu_94_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_ce)) begin - in_0_0_0_int_reg <= in_0_0_0; - in_0_0_1_int_reg <= in_0_0_1; - in_0_0_m1_int_reg <= in_0_0_m1; - in_0_1_0_int_reg <= in_0_1_0; - in_0_m1_0_int_reg <= in_0_m1_0; - in_1_0_0_int_reg <= in_1_0_0; - in_m1_0_0_int_reg <= in_m1_0_0; - end -end - -always @ (*) begin - if ((1'b0 == ap_ce_reg)) begin - ap_return = ap_return_int_reg; - end else if ((1'b1 == ap_ce_reg)) begin - ap_return = grp_fu_94_p2; - end else begin - ap_return = 'bx; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_104_ce = 1'b1; - end else begin - grp_fu_104_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_109_ce = 1'b1; - end else begin - grp_fu_109_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_114_ce = 1'b1; - end else begin - grp_fu_114_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_62_ce = 1'b1; - end else begin - grp_fu_62_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_66_ce = 1'b1; - end else begin - grp_fu_66_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_70_ce = 1'b1; - end else begin - grp_fu_70_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_74_ce = 1'b1; - end else begin - grp_fu_74_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_78_ce = 1'b1; - end else begin - grp_fu_78_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_82_ce = 1'b1; - end else begin - grp_fu_82_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_86_ce = 1'b1; - end else begin - grp_fu_86_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_90_ce = 1'b1; - end else begin - grp_fu_90_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_94_ce = 1'b1; - end else begin - grp_fu_94_ce = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin - grp_fu_98_ce = 1'b1; - end else begin - grp_fu_98_ce = 1'b0; - end -end - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); - -assign ap_block_state10_pp0_stage0_iter9 = ~(1'b1 == 1'b1); - -assign ap_block_state11_pp0_stage0_iter10 = ~(1'b1 == 1'b1); - -assign ap_block_state12_pp0_stage0_iter11 = ~(1'b1 == 1'b1); - -assign ap_block_state13_pp0_stage0_iter12 = ~(1'b1 == 1'b1); - -assign ap_block_state14_pp0_stage0_iter13 = ~(1'b1 == 1'b1); - -assign ap_block_state15_pp0_stage0_iter14 = ~(1'b1 == 1'b1); - -assign ap_block_state16_pp0_stage0_iter15 = ~(1'b1 == 1'b1); - -assign ap_block_state17_pp0_stage0_iter16 = ~(1'b1 == 1'b1); - -assign ap_block_state18_pp0_stage0_iter17 = ~(1'b1 == 1'b1); - -assign ap_block_state19_pp0_stage0_iter18 = ~(1'b1 == 1'b1); - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -assign ap_block_state20_pp0_stage0_iter19 = ~(1'b1 == 1'b1); - -assign ap_block_state21_pp0_stage0_iter20 = ~(1'b1 == 1'b1); - -assign ap_block_state22_pp0_stage0_iter21 = ~(1'b1 == 1'b1); - -assign ap_block_state23_pp0_stage0_iter22 = ~(1'b1 == 1'b1); - -assign ap_block_state24_pp0_stage0_iter23 = ~(1'b1 == 1'b1); - -assign ap_block_state25_pp0_stage0_iter24 = ~(1'b1 == 1'b1); - -assign ap_block_state26_pp0_stage0_iter25 = ~(1'b1 == 1'b1); - -assign ap_block_state27_pp0_stage0_iter26 = ~(1'b1 == 1'b1); - -assign ap_block_state28_pp0_stage0_iter27 = ~(1'b1 == 1'b1); - -assign ap_block_state29_pp0_stage0_iter28 = ~(1'b1 == 1'b1); - -assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); - -assign ap_block_state30_pp0_stage0_iter29 = ~(1'b1 == 1'b1); - -assign ap_block_state31_pp0_stage0_iter30 = ~(1'b1 == 1'b1); - -assign ap_block_state32_pp0_stage0_iter31 = ~(1'b1 == 1'b1); - -assign ap_block_state33_pp0_stage0_iter32 = ~(1'b1 == 1'b1); - -assign ap_block_state34_pp0_stage0_iter33 = ~(1'b1 == 1'b1); - -assign ap_block_state35_pp0_stage0_iter34 = ~(1'b1 == 1'b1); - -assign ap_block_state36_pp0_stage0_iter35 = ~(1'b1 == 1'b1); - -assign ap_block_state37_pp0_stage0_iter36 = ~(1'b1 == 1'b1); - -assign ap_block_state38_pp0_stage0_iter37 = ~(1'b1 == 1'b1); - -assign ap_block_state39_pp0_stage0_iter38 = ~(1'b1 == 1'b1); - -assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); - -assign ap_block_state40_pp0_stage0_iter39 = ~(1'b1 == 1'b1); - -assign ap_block_state41_pp0_stage0_iter40 = ~(1'b1 == 1'b1); - -assign ap_block_state42_pp0_stage0_iter41 = ~(1'b1 == 1'b1); - -assign ap_block_state43_pp0_stage0_iter42 = ~(1'b1 == 1'b1); - -assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1); - -assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1); - -assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1); - -assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1); - -assign ap_block_state8_pp0_stage0_iter7 = ~(1'b1 == 1'b1); - -assign ap_block_state9_pp0_stage0_iter8 = ~(1'b1 == 1'b1); - -endmodule //HEAT3D_HEAT3D_stencil_kernel diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HLS_REG_ap_uint_512_s.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HLS_REG_ap_uint_512_s.v deleted file mode 100644 index 3642685b..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_HLS_REG_ap_uint_512_s.v +++ /dev/null @@ -1,25 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module HEAT3D_HLS_REG_ap_uint_512_s ( - ap_ready, - in_r, - ap_return -); - - -output ap_ready; -input [511:0] in_r; -output [511:0] ap_return; - -assign ap_ready = 1'b1; - -assign ap_return = in_r; - -endmodule //HEAT3D_HLS_REG_ap_uint_512_s diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0.v deleted file mode 100644 index c192cb50..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0.v +++ /dev/null @@ -1,76 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1ns/1ps - -module HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0 -#(parameter - ID = 1, - NUM_STAGE = 3, - din0_WIDTH = 32, - din1_WIDTH = 32, - dout_WIDTH = 32 -)( - input wire clk, - input wire reset, - input wire ce, - input wire [din0_WIDTH-1:0] din0, - input wire [din1_WIDTH-1:0] din1, - output wire [dout_WIDTH-1:0] dout -); -//------------------------Local signal------------------- -wire aclk; -wire aclken; -wire a_tvalid; -wire [31:0] a_tdata; -wire b_tvalid; -wire [31:0] b_tdata; -wire r_tvalid; -wire [31:0] r_tdata; -reg [din0_WIDTH-1:0] din0_buf1; -reg [din1_WIDTH-1:0] din1_buf1; -reg ce_r; -wire [dout_WIDTH-1:0] dout_i; -reg [dout_WIDTH-1:0] dout_r; -//------------------------Instantiation------------------ -HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip_u ( - .aclk ( aclk ), - .aclken ( aclken ), - .s_axis_a_tvalid ( a_tvalid ), - .s_axis_a_tdata ( a_tdata ), - .s_axis_b_tvalid ( b_tvalid ), - .s_axis_b_tdata ( b_tdata ), - .m_axis_result_tvalid ( r_tvalid ), - .m_axis_result_tdata ( r_tdata ) -); -//------------------------Body--------------------------- -assign aclk = clk; -assign aclken = ce_r; -assign a_tvalid = 1'b1; -assign a_tdata = din0_buf1; -assign b_tvalid = 1'b1; -assign b_tdata = din1_buf1; -assign dout_i = r_tdata; - -always @(posedge clk) begin - if (ce) begin - din0_buf1 <= din0; - din1_buf1 <= din1; - end -end - -always @ (posedge clk) begin - ce_r <= ce; -end - -always @ (posedge clk) begin - if (ce_r) begin - dout_r <= dout_i; - end -end - -assign dout = ce_r?dout_i:dout_r; -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip.tcl b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip.tcl deleted file mode 100644 index ed99e679..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip.tcl +++ /dev/null @@ -1,45 +0,0 @@ -# BEGIN Vivado Commands -set vivado_ver [version -short] -set fpo_ver 7.1 -if {[regexp -nocase {2015\.1.*} $vivado_ver match]} { - set fpo_ver 7.0 -} -create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip -# BEGIN Vivado Commands -# BEGIN Vivado Parameters -set_property -dict [list CONFIG.a_precision_type Single \ - CONFIG.a_tuser_width 1 \ - CONFIG.add_sub_value Add \ - CONFIG.b_tuser_width 1 \ - CONFIG.c_a_exponent_width 8 \ - CONFIG.c_a_fraction_width 24 \ - CONFIG.c_compare_operation Programmable \ - CONFIG.c_has_divide_by_zero false \ - CONFIG.c_has_invalid_op false \ - CONFIG.c_has_overflow false \ - CONFIG.c_has_underflow false \ - CONFIG.c_latency 5 \ - CONFIG.c_mult_usage Full_Usage \ - CONFIG.c_optimization Speed_Optimized \ - CONFIG.c_rate 1 \ - CONFIG.c_result_exponent_width 8 \ - CONFIG.c_result_fraction_width 24 \ - CONFIG.component_name HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip \ - CONFIG.flow_control NonBlocking \ - CONFIG.has_a_tlast false \ - CONFIG.has_a_tuser false \ - CONFIG.has_aclken true \ - CONFIG.has_aresetn false \ - CONFIG.has_b_tlast false \ - CONFIG.has_b_tuser false \ - CONFIG.has_operation_tlast false \ - CONFIG.has_operation_tuser false \ - CONFIG.has_result_tready false \ - CONFIG.maximum_latency false \ - CONFIG.operation_tuser_width 1 \ - CONFIG.operation_type Add_Subtract \ - CONFIG.result_precision_type Single \ - CONFIG.result_tlast_behv Null] -objects [get_ips HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip] -quiet -# END Vivado Parameters -set_property generate_synth_checkpoint false [get_files HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip.xci] -generate_target {synthesis simulation} [get_files HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip.xci] diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fifo_w512_d15_A.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fifo_w512_d15_A.v deleted file mode 100644 index 4bc05680..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fifo_w512_d15_A.v +++ /dev/null @@ -1,189 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== -// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 - -`timescale 1ns/1ps - -module HEAT3D_fifo_w512_d15_A -#(parameter - MEM_STYLE = "auto", - DATA_WIDTH = 512, - ADDR_WIDTH = 4, - DEPTH = 14) -( - // system signal - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); -//------------------------Parameter---------------------- - -//------------------------Local signal------------------- - reg [ADDR_WIDTH-1:0] waddr = 1'b0; - reg [ADDR_WIDTH-1:0] raddr = 1'b0; - wire [ADDR_WIDTH-1:0] wnext; - wire [ADDR_WIDTH-1:0] rnext; - wire push; - wire pop; - reg [ADDR_WIDTH:0] mOutPtr = 1'b0; - reg empty_n = 1'b0; - reg full_n = 1'b1; - // has almost full? no - // has output register? - reg dout_vld = 1'b0;//yes - -//------------------------Instantiation------------------ - HEAT3D_fifo_w512_d15_A_ram - #( .MEM_STYLE (MEM_STYLE), - .DATA_WIDTH (DATA_WIDTH), - .ADDR_WIDTH (ADDR_WIDTH), - .DEPTH (DEPTH) - ) U_HEAT3D_fifo_w512_d15_A_ram ( - .clk (clk), - .reset (reset), - .we (push), - .waddr (waddr), - .din (if_din), - .raddr (rnext), - .rden (pop), - .dout (if_dout) - ); - -//------------------------Task and function-------------- - -//------------------------Body--------------------------- - // has num_data_valid ? no - - // has almost full ? - assign if_full_n = full_n; //no - - // has output register? - assign if_empty_n = dout_vld; // yes - assign pop = empty_n & if_read_ce & (if_read | ~dout_vld); // yes - assign push = full_n & if_write_ce & if_write; - assign wnext = !push ? waddr : - (waddr == DEPTH - 1) ? 1'b0 : - waddr + 1'b1; - assign rnext = !pop ? raddr : - (raddr == DEPTH - 1) ? 1'b0 : - raddr + 1'b1; - - // waddr - always @(posedge clk ) begin - if (reset == 1'b1) - waddr <= 1'b0; - else - waddr <= wnext; - end - - // raddr - always @(posedge clk ) begin - if (reset == 1'b1) - raddr <= 1'b0; - else - raddr <= rnext; - end - - // mOutPtr - always @(posedge clk ) begin - if (reset == 1'b1) - mOutPtr <= 1'b0; - else if (push & ~pop) - mOutPtr <= mOutPtr + 1'b1; - else if (~push & pop) - mOutPtr <= mOutPtr - 1'b1; - end - - // full_n - always @(posedge clk ) begin - if (reset == 1'b1) - full_n <= 1'b1; - else if (push & ~pop) - full_n <= (mOutPtr != DEPTH - 1); - else if (~push & pop) - full_n <= 1'b1; - end - - // almost_full_n - - // empty_n - always @(posedge clk ) begin - if (reset == 1'b1) - empty_n <= 1'b0; - else if (push & ~pop) - empty_n <= 1'b1; - else if (~push & pop) - empty_n <= (mOutPtr != 1'b1); - end - - // if_num_data_valid - - // dout_vld - always @(posedge clk ) begin - if (reset == 1'b1) - dout_vld <= 1'b0; - else if (pop) - dout_vld <= 1'b1; - else if (if_read_ce & if_read) - dout_vld <= 1'b0; - end // - -endmodule - - -module HEAT3D_fifo_w512_d15_A_ram -#(parameter - MEM_STYLE = "auto", - DATA_WIDTH = 512, - ADDR_WIDTH = 4, - DEPTH = 14) -( - input wire clk, - input wire reset, - input wire we, - input wire [ADDR_WIDTH-1:0] waddr, - input wire [DATA_WIDTH-1:0] din, - input wire [ADDR_WIDTH-1:0] raddr, - //output register? - input wire rden, - output reg [DATA_WIDTH-1:0] dout //yes -); - - (* ram_style = MEM_STYLE, rw_addr_collision = "yes" *) - reg [DATA_WIDTH-1:0] mem[0:DEPTH-1]; - reg [ADDR_WIDTH-1:0] raddr_reg; - - //write to ram - always @(posedge clk) begin - if (we) - mem[waddr] <= din; - end - - //buffer the raddr - always @(posedge clk) begin - raddr_reg <= raddr; - end - - //read from ram, output register? - always @(posedge clk ) begin - if (reset) - dout <= 0; - else if (rden) - dout <= mem[raddr_reg]; - end// yes - -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_flow_control_loop_pipe_sequential_init.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_flow_control_loop_pipe_sequential_init.v deleted file mode 100644 index fc33e2d8..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_flow_control_loop_pipe_sequential_init.v +++ /dev/null @@ -1,104 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module HEAT3D_flow_control_loop_pipe_sequential_init( - ap_clk, - ap_rst, - ap_start, - ap_ready, - ap_done, - ap_start_int, - ap_ready_int, - ap_done_int, - ap_continue_int, - ap_loop_init, - ap_loop_exit_ready, - ap_loop_exit_done -); - -input ap_clk; -input ap_rst; - -//Block level handshake with outside loop -input ap_start; -output ap_ready; -output ap_done; - -//Block level handshake with loop body -output ap_start_int; -input ap_ready_int; -input ap_done_int; -output ap_continue_int; - -//Init live in variables -output ap_loop_init; -wire ap_loop_init; -reg ap_loop_init_int; -reg ap_done; -reg ap_done_cache; - -//Exit signal from loop body -input ap_loop_exit_ready; -input ap_loop_exit_done; - -// power-on initialization -initial begin -#0 ap_loop_init_int = 1'b1; -#0 ap_done_cache = 1'b0; -end - -assign ap_start_int = ap_start; - -assign ap_continue_int = 1'b1; - -assign ap_ready = ap_loop_exit_ready; - -//ap_loop_init is valid for the first II -//of the first loop run so as to enable -//the init block ops which are pushed into -//the first state of the pipeline region -always @ (posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_loop_exit_done == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_ready_int == 1'b1) begin - ap_loop_init_int <= 1'b0; - end -end - -assign ap_loop_init = ap_loop_init_int & ap_start; - -// if no ap_continue port and current module is not top module, -// ap_done handshakes with ap_start. Internally, flow control sends out -// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle. -// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int -// is asserted, so DUT can start the next run -always @(posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_done_cache <= 1'b0; - end else if (ap_done_int == 1'b1) begin - ap_done_cache <= 1'b1; - end else if (ap_start_int == 1'b1) begin - ap_done_cache <= 1'b0; - end -end - -// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start -always @(*) -begin - if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0.v deleted file mode 100644 index b9238a38..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0.v +++ /dev/null @@ -1,76 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1ns/1ps - -module HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0 -#(parameter - ID = 1, - NUM_STAGE = 3, - din0_WIDTH = 32, - din1_WIDTH = 32, - dout_WIDTH = 32 -)( - input wire clk, - input wire reset, - input wire ce, - input wire [din0_WIDTH-1:0] din0, - input wire [din1_WIDTH-1:0] din1, - output wire [dout_WIDTH-1:0] dout -); -//------------------------Local signal------------------- -wire aclk; -wire aclken; -wire a_tvalid; -wire [31:0] a_tdata; -wire b_tvalid; -wire [31:0] b_tdata; -wire r_tvalid; -wire [31:0] r_tdata; -reg [din0_WIDTH-1:0] din0_buf1; -reg [din1_WIDTH-1:0] din1_buf1; -reg ce_r; -wire [dout_WIDTH-1:0] dout_i; -reg [dout_WIDTH-1:0] dout_r; -//------------------------Instantiation------------------ -HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip_u ( - .aclk ( aclk ), - .aclken ( aclken ), - .s_axis_a_tvalid ( a_tvalid ), - .s_axis_a_tdata ( a_tdata ), - .s_axis_b_tvalid ( b_tvalid ), - .s_axis_b_tdata ( b_tdata ), - .m_axis_result_tvalid ( r_tvalid ), - .m_axis_result_tdata ( r_tdata ) -); -//------------------------Body--------------------------- -assign aclk = clk; -assign aclken = ce_r; -assign a_tvalid = 1'b1; -assign a_tdata = din0_buf1; -assign b_tvalid = 1'b1; -assign b_tdata = din1_buf1; -assign dout_i = r_tdata; - -always @(posedge clk) begin - if (ce) begin - din0_buf1 <= din0; - din1_buf1 <= din1; - end -end - -always @ (posedge clk) begin - ce_r <= ce; -end - -always @ (posedge clk) begin - if (ce_r) begin - dout_r <= dout_i; - end -end - -assign dout = ce_r?dout_i:dout_r; -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip.tcl b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip.tcl deleted file mode 100644 index b6e101b2..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip.tcl +++ /dev/null @@ -1,45 +0,0 @@ -# BEGIN Vivado Commands -set vivado_ver [version -short] -set fpo_ver 7.1 -if {[regexp -nocase {2015\.1.*} $vivado_ver match]} { - set fpo_ver 7.0 -} -create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip -# BEGIN Vivado Commands -# BEGIN Vivado Parameters -set_property -dict [list CONFIG.a_precision_type Single \ - CONFIG.a_tuser_width 1 \ - CONFIG.add_sub_value Both \ - CONFIG.b_tuser_width 1 \ - CONFIG.c_a_exponent_width 8 \ - CONFIG.c_a_fraction_width 24 \ - CONFIG.c_compare_operation Programmable \ - CONFIG.c_has_divide_by_zero false \ - CONFIG.c_has_invalid_op false \ - CONFIG.c_has_overflow false \ - CONFIG.c_has_underflow false \ - CONFIG.c_latency 2 \ - CONFIG.c_mult_usage Max_Usage \ - CONFIG.c_optimization Speed_Optimized \ - CONFIG.c_rate 1 \ - CONFIG.c_result_exponent_width 8 \ - CONFIG.c_result_fraction_width 24 \ - CONFIG.component_name HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip \ - CONFIG.flow_control NonBlocking \ - CONFIG.has_a_tlast false \ - CONFIG.has_a_tuser false \ - CONFIG.has_aclken true \ - CONFIG.has_aresetn false \ - CONFIG.has_b_tlast false \ - CONFIG.has_b_tuser false \ - CONFIG.has_operation_tlast false \ - CONFIG.has_operation_tuser false \ - CONFIG.has_result_tready false \ - CONFIG.maximum_latency false \ - CONFIG.operation_tuser_width 1 \ - CONFIG.operation_type Multiply \ - CONFIG.result_precision_type Single \ - CONFIG.result_tlast_behv Null] -objects [get_ips HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip] -quiet -# END Vivado Parameters -set_property generate_synth_checkpoint false [get_files HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip.xci] -generate_target {synthesis simulation} [get_files HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip.xci] diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0.v deleted file mode 100644 index da8b9134..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0.v +++ /dev/null @@ -1,76 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1ns/1ps - -module HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0 -#(parameter - ID = 1, - NUM_STAGE = 3, - din0_WIDTH = 32, - din1_WIDTH = 32, - dout_WIDTH = 32 -)( - input wire clk, - input wire reset, - input wire ce, - input wire [din0_WIDTH-1:0] din0, - input wire [din1_WIDTH-1:0] din1, - output wire [dout_WIDTH-1:0] dout -); -//------------------------Local signal------------------- -wire aclk; -wire aclken; -wire a_tvalid; -wire [31:0] a_tdata; -wire b_tvalid; -wire [31:0] b_tdata; -wire r_tvalid; -wire [31:0] r_tdata; -reg [din0_WIDTH-1:0] din0_buf1; -reg [din1_WIDTH-1:0] din1_buf1; -reg ce_r; -wire [dout_WIDTH-1:0] dout_i; -reg [dout_WIDTH-1:0] dout_r; -//------------------------Instantiation------------------ -HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip_u ( - .aclk ( aclk ), - .aclken ( aclken ), - .s_axis_a_tvalid ( a_tvalid ), - .s_axis_a_tdata ( a_tdata ), - .s_axis_b_tvalid ( b_tvalid ), - .s_axis_b_tdata ( b_tdata ), - .m_axis_result_tvalid ( r_tvalid ), - .m_axis_result_tdata ( r_tdata ) -); -//------------------------Body--------------------------- -assign aclk = clk; -assign aclken = ce_r; -assign a_tvalid = 1'b1; -assign a_tdata = din0_buf1; -assign b_tvalid = 1'b1; -assign b_tdata = din1_buf1; -assign dout_i = r_tdata; - -always @(posedge clk) begin - if (ce) begin - din0_buf1 <= din0; - din1_buf1 <= din1; - end -end - -always @ (posedge clk) begin - ce_r <= ce; -end - -always @ (posedge clk) begin - if (ce_r) begin - dout_r <= dout_i; - end -end - -assign dout = ce_r?dout_i:dout_r; -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip.tcl b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip.tcl deleted file mode 100644 index 5783d463..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip.tcl +++ /dev/null @@ -1,45 +0,0 @@ -# BEGIN Vivado Commands -set vivado_ver [version -short] -set fpo_ver 7.1 -if {[regexp -nocase {2015\.1.*} $vivado_ver match]} { - set fpo_ver 7.0 -} -create_ip -name floating_point -version $fpo_ver -vendor xilinx.com -library ip -module_name HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip -# BEGIN Vivado Commands -# BEGIN Vivado Parameters -set_property -dict [list CONFIG.a_precision_type Single \ - CONFIG.a_tuser_width 1 \ - CONFIG.add_sub_value Subtract \ - CONFIG.b_tuser_width 1 \ - CONFIG.c_a_exponent_width 8 \ - CONFIG.c_a_fraction_width 24 \ - CONFIG.c_compare_operation Programmable \ - CONFIG.c_has_divide_by_zero false \ - CONFIG.c_has_invalid_op false \ - CONFIG.c_has_overflow false \ - CONFIG.c_has_underflow false \ - CONFIG.c_latency 5 \ - CONFIG.c_mult_usage Full_Usage \ - CONFIG.c_optimization Speed_Optimized \ - CONFIG.c_rate 1 \ - CONFIG.c_result_exponent_width 8 \ - CONFIG.c_result_fraction_width 24 \ - CONFIG.component_name HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip \ - CONFIG.flow_control NonBlocking \ - CONFIG.has_a_tlast false \ - CONFIG.has_a_tuser false \ - CONFIG.has_aclken true \ - CONFIG.has_aresetn false \ - CONFIG.has_b_tlast false \ - CONFIG.has_b_tuser false \ - CONFIG.has_operation_tlast false \ - CONFIG.has_operation_tuser false \ - CONFIG.has_result_tready false \ - CONFIG.maximum_latency false \ - CONFIG.operation_tuser_width 1 \ - CONFIG.operation_type Add_Subtract \ - CONFIG.result_precision_type Single \ - CONFIG.result_tlast_behv Null] -objects [get_ips HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip] -quiet -# END Vivado Parameters -set_property generate_synth_checkpoint false [get_files HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip.xci] -generate_target {synthesis simulation} [get_files HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip.xci] diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/a_axi_write_broadcastor_1_to_3.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/a_axi_write_broadcastor_1_to_3.v deleted file mode 100644 index d84fe57e..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/a_axi_write_broadcastor_1_to_3.v +++ /dev/null @@ -1,269 +0,0 @@ - -module a_axi_write_broadcastor_1_to_3 ( - ap_clk, - - s_axi_control_AWVALID_slr_0, - s_axi_control_AWREADY_slr_0, - s_axi_control_AWADDR_slr_0, - s_axi_control_WVALID_slr_0, - s_axi_control_WREADY_slr_0, - s_axi_control_WDATA_slr_0, - s_axi_control_WSTRB_slr_0, - s_axi_control_AWVALID_slr_1, - s_axi_control_AWREADY_slr_1, - s_axi_control_AWADDR_slr_1, - s_axi_control_WVALID_slr_1, - s_axi_control_WREADY_slr_1, - s_axi_control_WDATA_slr_1, - s_axi_control_WSTRB_slr_1, - s_axi_control_AWVALID_slr_2, - s_axi_control_AWREADY_slr_2, - s_axi_control_AWADDR_slr_2, - s_axi_control_WVALID_slr_2, - s_axi_control_WREADY_slr_2, - s_axi_control_WDATA_slr_2, - s_axi_control_WSTRB_slr_2, - s_axi_control_AWVALID, - s_axi_control_AWREADY, - s_axi_control_AWADDR, - s_axi_control_WVALID, - s_axi_control_WREADY, - s_axi_control_WDATA, - s_axi_control_WSTRB -); - parameter C_S_AXI_CONTROL_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_ADDR_WIDTH = 9; - parameter C_S_AXI_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_WSTRB_WIDTH = 32 / 8; - parameter C_S_AXI_WSTRB_WIDTH = 32 / 8; - - input ap_clk; - - input s_axi_control_AWVALID; - output s_axi_control_AWREADY; - input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR; - input s_axi_control_WVALID; - output s_axi_control_WREADY; - input [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA; - input [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB; - - output s_axi_control_AWVALID_slr_0; - input s_axi_control_AWREADY_slr_0; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0; - output s_axi_control_WVALID_slr_0; - input s_axi_control_WREADY_slr_0; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0; - - output s_axi_control_AWVALID_slr_1; - input s_axi_control_AWREADY_slr_1; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1; - output s_axi_control_WVALID_slr_1; - input s_axi_control_WREADY_slr_1; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1; - - output s_axi_control_AWVALID_slr_2; - input s_axi_control_AWREADY_slr_2; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2; - output s_axi_control_WVALID_slr_2; - input s_axi_control_WREADY_slr_2; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2; - - wire s_axi_control_AWVALID_slr_0_inner; - wire s_axi_control_AWREADY_slr_0_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0_inner; - wire s_axi_control_WVALID_slr_0_inner; - wire s_axi_control_WREADY_slr_0_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0_inner; - - wire s_axi_control_AWVALID_slr_1_inner; - wire s_axi_control_AWREADY_slr_1_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1_inner; - wire s_axi_control_WVALID_slr_1_inner; - wire s_axi_control_WREADY_slr_1_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1_inner; - - wire s_axi_control_AWVALID_slr_2_inner; - wire s_axi_control_AWREADY_slr_2_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2_inner; - wire s_axi_control_WVALID_slr_2_inner; - wire s_axi_control_WREADY_slr_2_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2_inner; - - // broadcast the AW channel - assign s_axi_control_AWADDR_slr_0_inner = s_axi_control_AWADDR; - assign s_axi_control_AWADDR_slr_1_inner = s_axi_control_AWADDR; - assign s_axi_control_AWADDR_slr_2_inner = s_axi_control_AWADDR; - - assign s_axi_control_AWVALID_slr_0_inner = s_axi_control_AWVALID; - assign s_axi_control_AWVALID_slr_1_inner = s_axi_control_AWVALID; - assign s_axi_control_AWVALID_slr_2_inner = s_axi_control_AWVALID; - - assign s_axi_control_AWREADY = s_axi_control_AWREADY_slr_0_inner & - s_axi_control_AWREADY_slr_1_inner & - s_axi_control_AWREADY_slr_2_inner; - - // broadcast the W channel - assign s_axi_control_WDATA_slr_0_inner = s_axi_control_WDATA; - assign s_axi_control_WDATA_slr_1_inner = s_axi_control_WDATA; - assign s_axi_control_WDATA_slr_2_inner = s_axi_control_WDATA; - - assign s_axi_control_WSTRB_slr_0_inner = s_axi_control_WSTRB; - assign s_axi_control_WSTRB_slr_1_inner = s_axi_control_WSTRB; - assign s_axi_control_WSTRB_slr_2_inner = s_axi_control_WSTRB; - - assign s_axi_control_WVALID_slr_0_inner = s_axi_control_WVALID; - assign s_axi_control_WVALID_slr_1_inner = s_axi_control_WVALID; - assign s_axi_control_WVALID_slr_2_inner = s_axi_control_WVALID; - - assign s_axi_control_WREADY = s_axi_control_WREADY_slr_0_inner & - s_axi_control_WREADY_slr_1_inner & - s_axi_control_WREADY_slr_2_inner; - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_0 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_0_inner), - .if_full_n (s_axi_control_AWREADY_slr_0_inner), - .if_write (s_axi_control_AWVALID_slr_0_inner), - - .if_dout (s_axi_control_AWADDR_slr_0), - .if_empty_n (s_axi_control_AWVALID_slr_0), - .if_read (s_axi_control_AWREADY_slr_0) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_0 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_0_inner, s_axi_control_WSTRB_slr_0_inner}), - .if_full_n (s_axi_control_WREADY_slr_0_inner), - .if_write (s_axi_control_WVALID_slr_0_inner), - - .if_dout ({s_axi_control_WDATA_slr_0, s_axi_control_WSTRB_slr_0}), - .if_empty_n (s_axi_control_WVALID_slr_0), - .if_read (s_axi_control_WREADY_slr_0) - ); - - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_1 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_1_inner), - .if_full_n (s_axi_control_AWREADY_slr_1_inner), - .if_write (s_axi_control_AWVALID_slr_1_inner), - - .if_dout (s_axi_control_AWADDR_slr_1), - .if_empty_n (s_axi_control_AWVALID_slr_1), - .if_read (s_axi_control_AWREADY_slr_1) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_1 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_1_inner, s_axi_control_WSTRB_slr_1_inner}), - .if_full_n (s_axi_control_WREADY_slr_1_inner), - .if_write (s_axi_control_WVALID_slr_1_inner), - - .if_dout ({s_axi_control_WDATA_slr_1, s_axi_control_WSTRB_slr_1}), - .if_empty_n (s_axi_control_WVALID_slr_1), - .if_read (s_axi_control_WREADY_slr_1) - ); - - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_2 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_2_inner), - .if_full_n (s_axi_control_AWREADY_slr_2_inner), - .if_write (s_axi_control_AWVALID_slr_2_inner), - - .if_dout (s_axi_control_AWADDR_slr_2), - .if_empty_n (s_axi_control_AWVALID_slr_2), - .if_read (s_axi_control_AWREADY_slr_2) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_2 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_2_inner, s_axi_control_WSTRB_slr_2_inner}), - .if_full_n (s_axi_control_WREADY_slr_2_inner), - .if_write (s_axi_control_WVALID_slr_2_inner), - - .if_dout ({s_axi_control_WDATA_slr_2, s_axi_control_WSTRB_slr_2}), - .if_empty_n (s_axi_control_WVALID_slr_2), - .if_read (s_axi_control_WREADY_slr_2) - ); - - -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/a_axi_write_broadcastor_1_to_4.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/a_axi_write_broadcastor_1_to_4.v deleted file mode 100644 index 055ed0bd..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/a_axi_write_broadcastor_1_to_4.v +++ /dev/null @@ -1,346 +0,0 @@ - -module a_axi_write_broadcastor_1_to_4 ( - ap_clk, - - s_axi_control_AWVALID_slr_0, - s_axi_control_AWREADY_slr_0, - s_axi_control_AWADDR_slr_0, - s_axi_control_WVALID_slr_0, - s_axi_control_WREADY_slr_0, - s_axi_control_WDATA_slr_0, - s_axi_control_WSTRB_slr_0, - s_axi_control_AWVALID_slr_1, - s_axi_control_AWREADY_slr_1, - s_axi_control_AWADDR_slr_1, - s_axi_control_WVALID_slr_1, - s_axi_control_WREADY_slr_1, - s_axi_control_WDATA_slr_1, - s_axi_control_WSTRB_slr_1, - s_axi_control_AWVALID_slr_2, - s_axi_control_AWREADY_slr_2, - s_axi_control_AWADDR_slr_2, - s_axi_control_WVALID_slr_2, - s_axi_control_WREADY_slr_2, - s_axi_control_WDATA_slr_2, - s_axi_control_WSTRB_slr_2, - s_axi_control_AWVALID_slr_3, - s_axi_control_AWREADY_slr_3, - s_axi_control_AWADDR_slr_3, - s_axi_control_WVALID_slr_3, - s_axi_control_WREADY_slr_3, - s_axi_control_WDATA_slr_3, - s_axi_control_WSTRB_slr_3, - s_axi_control_AWVALID, - s_axi_control_AWREADY, - s_axi_control_AWADDR, - s_axi_control_WVALID, - s_axi_control_WREADY, - s_axi_control_WDATA, - s_axi_control_WSTRB -); - parameter C_S_AXI_CONTROL_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_ADDR_WIDTH = 9; - parameter C_S_AXI_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_WSTRB_WIDTH = 32 / 8; - parameter C_S_AXI_WSTRB_WIDTH = 32 / 8; - - input ap_clk; - input s_axi_control_AWVALID; - output s_axi_control_AWREADY; - input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR; - input s_axi_control_WVALID; - output s_axi_control_WREADY; - input [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA; - input [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB; - - output s_axi_control_AWVALID_slr_0; - input s_axi_control_AWREADY_slr_0; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0; - output s_axi_control_WVALID_slr_0; - input s_axi_control_WREADY_slr_0; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0; - - output s_axi_control_AWVALID_slr_1; - input s_axi_control_AWREADY_slr_1; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1; - output s_axi_control_WVALID_slr_1; - input s_axi_control_WREADY_slr_1; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1; - - output s_axi_control_AWVALID_slr_2; - input s_axi_control_AWREADY_slr_2; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2; - output s_axi_control_WVALID_slr_2; - input s_axi_control_WREADY_slr_2; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2; - - output s_axi_control_AWVALID_slr_3; - input s_axi_control_AWREADY_slr_3; - output [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_3; - output s_axi_control_WVALID_slr_3; - input s_axi_control_WREADY_slr_3; - output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_3; - output [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_3; - - wire s_axi_control_AWVALID_slr_0_inner; - wire s_axi_control_AWREADY_slr_0_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_0_inner; - wire s_axi_control_WVALID_slr_0_inner; - wire s_axi_control_WREADY_slr_0_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_0_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_0_inner; - - wire s_axi_control_AWVALID_slr_1_inner; - wire s_axi_control_AWREADY_slr_1_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_1_inner; - wire s_axi_control_WVALID_slr_1_inner; - wire s_axi_control_WREADY_slr_1_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_1_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_1_inner; - - wire s_axi_control_AWVALID_slr_2_inner; - wire s_axi_control_AWREADY_slr_2_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_2_inner; - wire s_axi_control_WVALID_slr_2_inner; - wire s_axi_control_WREADY_slr_2_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_2_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_2_inner; - - wire s_axi_control_AWVALID_slr_3_inner; - wire s_axi_control_AWREADY_slr_3_inner; - wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR_slr_3_inner; - wire s_axi_control_WVALID_slr_3_inner; - wire s_axi_control_WREADY_slr_3_inner; - wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA_slr_3_inner; - wire [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB_slr_3_inner; - - // broadcast the AW channel - assign s_axi_control_AWADDR_slr_0_inner = s_axi_control_AWADDR; - assign s_axi_control_AWADDR_slr_1_inner = s_axi_control_AWADDR; - assign s_axi_control_AWADDR_slr_2_inner = s_axi_control_AWADDR; - assign s_axi_control_AWADDR_slr_3_inner = s_axi_control_AWADDR; - - assign s_axi_control_AWVALID_slr_0_inner = s_axi_control_AWVALID; - assign s_axi_control_AWVALID_slr_1_inner = s_axi_control_AWVALID; - assign s_axi_control_AWVALID_slr_2_inner = s_axi_control_AWVALID; - assign s_axi_control_AWVALID_slr_3_inner = s_axi_control_AWVALID; - - assign s_axi_control_AWREADY = s_axi_control_AWREADY_slr_0_inner & - s_axi_control_AWREADY_slr_1_inner & - s_axi_control_AWREADY_slr_2_inner & - s_axi_control_AWREADY_slr_3_inner; - - // broadcast the W channel - assign s_axi_control_WDATA_slr_0_inner = s_axi_control_WDATA; - assign s_axi_control_WDATA_slr_1_inner = s_axi_control_WDATA; - assign s_axi_control_WDATA_slr_2_inner = s_axi_control_WDATA; - assign s_axi_control_WDATA_slr_3_inner = s_axi_control_WDATA; - - assign s_axi_control_WSTRB_slr_0_inner = s_axi_control_WSTRB; - assign s_axi_control_WSTRB_slr_1_inner = s_axi_control_WSTRB; - assign s_axi_control_WSTRB_slr_2_inner = s_axi_control_WSTRB; - assign s_axi_control_WSTRB_slr_3_inner = s_axi_control_WSTRB; - - assign s_axi_control_WVALID_slr_0_inner = s_axi_control_WVALID; - assign s_axi_control_WVALID_slr_1_inner = s_axi_control_WVALID; - assign s_axi_control_WVALID_slr_2_inner = s_axi_control_WVALID; - assign s_axi_control_WVALID_slr_3_inner = s_axi_control_WVALID; - - assign s_axi_control_WREADY = s_axi_control_WREADY_slr_0_inner & - s_axi_control_WREADY_slr_1_inner & - s_axi_control_WREADY_slr_2_inner & - s_axi_control_WREADY_slr_3_inner; - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_0 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_0_inner), - .if_full_n (s_axi_control_AWREADY_slr_0_inner), - .if_write (s_axi_control_AWVALID_slr_0_inner), - - .if_dout (s_axi_control_AWADDR_slr_0), - .if_empty_n (s_axi_control_AWVALID_slr_0), - .if_read (s_axi_control_AWREADY_slr_0) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_0 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_0_inner, s_axi_control_WSTRB_slr_0_inner}), - .if_full_n (s_axi_control_WREADY_slr_0_inner), - .if_write (s_axi_control_WVALID_slr_0_inner), - - .if_dout ({s_axi_control_WDATA_slr_0, s_axi_control_WSTRB_slr_0}), - .if_empty_n (s_axi_control_WVALID_slr_0), - .if_read (s_axi_control_WREADY_slr_0) - ); - - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_1 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_1_inner), - .if_full_n (s_axi_control_AWREADY_slr_1_inner), - .if_write (s_axi_control_AWVALID_slr_1_inner), - - .if_dout (s_axi_control_AWADDR_slr_1), - .if_empty_n (s_axi_control_AWVALID_slr_1), - .if_read (s_axi_control_AWREADY_slr_1) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_1 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_1_inner, s_axi_control_WSTRB_slr_1_inner}), - .if_full_n (s_axi_control_WREADY_slr_1_inner), - .if_write (s_axi_control_WVALID_slr_1_inner), - - .if_dout ({s_axi_control_WDATA_slr_1, s_axi_control_WSTRB_slr_1}), - .if_empty_n (s_axi_control_WVALID_slr_1), - .if_read (s_axi_control_WREADY_slr_1) - ); - - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_2 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_2_inner), - .if_full_n (s_axi_control_AWREADY_slr_2_inner), - .if_write (s_axi_control_AWVALID_slr_2_inner), - - .if_dout (s_axi_control_AWADDR_slr_2), - .if_empty_n (s_axi_control_AWVALID_slr_2), - .if_read (s_axi_control_AWREADY_slr_2) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_2 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_2_inner, s_axi_control_WSTRB_slr_2_inner}), - .if_full_n (s_axi_control_WREADY_slr_2_inner), - .if_write (s_axi_control_WVALID_slr_2_inner), - - .if_dout ({s_axi_control_WDATA_slr_2, s_axi_control_WSTRB_slr_2}), - .if_empty_n (s_axi_control_WVALID_slr_2), - .if_read (s_axi_control_WREADY_slr_2) - ); - - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - AW_pipeline_slr_3 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din (s_axi_control_AWADDR_slr_3_inner), - .if_full_n (s_axi_control_AWREADY_slr_3_inner), - .if_write (s_axi_control_AWVALID_slr_3_inner), - - .if_dout (s_axi_control_AWADDR_slr_3), - .if_empty_n (s_axi_control_AWVALID_slr_3), - .if_read (s_axi_control_AWREADY_slr_3) - ); - - relay_station - #( - .DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH + C_S_AXI_CONTROL_WSTRB_WIDTH), - .DEPTH(24), - .ADDR_WIDTH(1), - .LEVEL( 3 ) - ) - W_pipeline_slr_3 - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({s_axi_control_WDATA_slr_3_inner, s_axi_control_WSTRB_slr_3_inner}), - .if_full_n (s_axi_control_WREADY_slr_3_inner), - .if_write (s_axi_control_WVALID_slr_3_inner), - - .if_dout ({s_axi_control_WDATA_slr_3, s_axi_control_WSTRB_slr_3}), - .if_empty_n (s_axi_control_WVALID_slr_3), - .if_read (s_axi_control_WREADY_slr_3) - ); - - - -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/arbiter.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/arbiter.v deleted file mode 100644 index cfac70d1..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/arbiter.v +++ /dev/null @@ -1,159 +0,0 @@ -/* - -Copyright (c) 2014-2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Arbiter module - */ -module arbiter # -( - parameter PORTS = 4, - // select round robin arbitration - parameter ARB_TYPE_ROUND_ROBIN = 0, - // blocking arbiter enable - parameter ARB_BLOCK = 0, - // block on acknowledge assert when nonzero, request deassert when 0 - parameter ARB_BLOCK_ACK = 1, - // LSB priority selection - parameter ARB_LSB_HIGH_PRIORITY = 0 -) -( - input wire clk, - input wire rst, - - input wire [PORTS-1:0] request, - input wire [PORTS-1:0] acknowledge, - - output wire [PORTS-1:0] grant, - output wire grant_valid, - output wire [$clog2(PORTS)-1:0] grant_encoded -); - -reg [PORTS-1:0] grant_reg = 0, grant_next; -reg grant_valid_reg = 0, grant_valid_next; -reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next; - -assign grant_valid = grant_valid_reg; -assign grant = grant_reg; -assign grant_encoded = grant_encoded_reg; - -wire request_valid; -wire [$clog2(PORTS)-1:0] request_index; -wire [PORTS-1:0] request_mask; - -priority_encoder #( - .WIDTH(PORTS), - .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY) -) -priority_encoder_inst ( - .input_unencoded(request), - .output_valid(request_valid), - .output_encoded(request_index), - .output_unencoded(request_mask) -); - -reg [PORTS-1:0] mask_reg = 0, mask_next; - -wire masked_request_valid; -wire [$clog2(PORTS)-1:0] masked_request_index; -wire [PORTS-1:0] masked_request_mask; - -priority_encoder #( - .WIDTH(PORTS), - .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY) -) -priority_encoder_masked ( - .input_unencoded(request & mask_reg), - .output_valid(masked_request_valid), - .output_encoded(masked_request_index), - .output_unencoded(masked_request_mask) -); - -always @* begin - grant_next = 0; - grant_valid_next = 0; - grant_encoded_next = 0; - mask_next = mask_reg; - - if (ARB_BLOCK && !ARB_BLOCK_ACK && grant_reg & request) begin - // granted request still asserted; hold it - grant_valid_next = grant_valid_reg; - grant_next = grant_reg; - grant_encoded_next = grant_encoded_reg; - end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && !(grant_reg & acknowledge)) begin - // granted request not yet acknowledged; hold it - grant_valid_next = grant_valid_reg; - grant_next = grant_reg; - grant_encoded_next = grant_encoded_reg; - end else if (request_valid) begin - if (ARB_TYPE_ROUND_ROBIN) begin - if (masked_request_valid) begin - grant_valid_next = 1; - grant_next = masked_request_mask; - grant_encoded_next = masked_request_index; - if (ARB_LSB_HIGH_PRIORITY) begin - mask_next = {PORTS{1'b1}} << (masked_request_index + 1); - end else begin - mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index); - end - end else begin - grant_valid_next = 1; - grant_next = request_mask; - grant_encoded_next = request_index; - if (ARB_LSB_HIGH_PRIORITY) begin - mask_next = {PORTS{1'b1}} << (request_index + 1); - end else begin - mask_next = {PORTS{1'b1}} >> (PORTS - request_index); - end - end - end else begin - grant_valid_next = 1; - grant_next = request_mask; - grant_encoded_next = request_index; - end - end -end - -always @(posedge clk) begin - if (rst) begin - grant_reg <= 0; - grant_valid_reg <= 0; - grant_encoded_reg <= 0; - mask_reg <= 0; - end else begin - grant_reg <= grant_next; - grant_valid_reg <= grant_valid_next; - grant_encoded_reg <= grant_encoded_next; - mask_reg <= mask_next; - end -end - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/async_mmap.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/async_mmap.v deleted file mode 100644 index 2dd27717..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/async_mmap.v +++ /dev/null @@ -1,524 +0,0 @@ -`default_nettype none - -module async_mmap #( - parameter BufferSize = 32, - parameter BufferSizeLog = 5, - parameter AddrWidth = 64, - parameter AxiSideAddrWidth = 64, - parameter DataWidth = 512, - parameter DataWidthBytesLog = 6, // must equal log2(DataWidth/8) - parameter WaitTimeWidth = 4, - parameter BurstLenWidth = 8, - // implement the FIFOs for the read channel - // if set to 0: disconnect the data link - parameter EnableReadChannel = 1, - parameter EnableWriteChannel= 1, - // for burst inference - parameter MaxWaitTime = 3, - parameter MaxBurstLen = 15 -) ( - (* RS_CLK *) input wire clk, - (* RS_RST *) input wire rst, // active high - - // base address for the memory region - (* RS_FF = "offset" *) input wire [63:0] offset, - - // axi write addr channel - (* RS_HS = "aw.valid" *) output wire m_axi_AWVALID, - (* RS_HS = "aw.ready" *) input wire m_axi_AWREADY, - (* RS_HS = "aw.data" *) output wire [AxiSideAddrWidth-1:0] m_axi_AWADDR, - (* RS_HS = "aw.data" *) output wire [0:0] m_axi_AWID, - (* RS_HS = "aw.data" *) output wire [7:0] m_axi_AWLEN, - (* RS_HS = "aw.data" *) output wire [2:0] m_axi_AWSIZE, - (* RS_HS = "aw.data" *) output wire [1:0] m_axi_AWBURST, - (* RS_HS = "aw.data" *) output wire [0:0] m_axi_AWLOCK, - (* RS_HS = "aw.data" *) output wire [3:0] m_axi_AWCACHE, - (* RS_HS = "aw.data" *) output wire [2:0] m_axi_AWPROT, - (* RS_HS = "aw.data" *) output wire [3:0] m_axi_AWQOS, - - // axi write data channel - (* RS_HS = "w.valid" *) output wire m_axi_WVALID, - (* RS_HS = "w.ready" *) input wire m_axi_WREADY, - (* RS_HS = "w.data" *) output wire [DataWidth-1:0] m_axi_WDATA, - (* RS_HS = "w.data" *) output wire [DataWidth/8-1:0] m_axi_WSTRB, - (* RS_HS = "w.data" *) output wire m_axi_WLAST, - - // axi write acknowledge channel - (* RS_HS = "b.valid" *) input wire m_axi_BVALID, - (* RS_HS = "b.ready" *) output wire m_axi_BREADY, - (* RS_HS = "b.data" *) input wire [1:0] m_axi_BRESP, - (* RS_HS = "b.data" *) input wire [0:0] m_axi_BID, - - // axi read addr channel - (* RS_HS = "ar.valid" *) output wire m_axi_ARVALID, - (* RS_HS = "ar.ready" *) input wire m_axi_ARREADY, - (* RS_HS = "ar.data" *) output wire [AxiSideAddrWidth-1:0] m_axi_ARADDR, - (* RS_HS = "ar.data" *) output wire [0:0] m_axi_ARID, - (* RS_HS = "ar.data" *) output wire [7:0] m_axi_ARLEN, - (* RS_HS = "ar.data" *) output wire [2:0] m_axi_ARSIZE, - (* RS_HS = "ar.data" *) output wire [1:0] m_axi_ARBURST, - (* RS_HS = "ar.data" *) output wire [0:0] m_axi_ARLOCK, - (* RS_HS = "ar.data" *) output wire [3:0] m_axi_ARCACHE, - (* RS_HS = "ar.data" *) output wire [2:0] m_axi_ARPROT, - (* RS_HS = "ar.data" *) output wire [3:0] m_axi_ARQOS, - - // axi read response channel - (* RS_HS = "r.valid" *) input wire m_axi_RVALID, - (* RS_HS = "r.ready" *) output wire m_axi_RREADY, - (* RS_HS = "r.data" *) input wire [DataWidth-1:0] m_axi_RDATA, - (* RS_HS = "r.data" *) input wire m_axi_RLAST, - (* RS_HS = "r.data" *) input wire [0:0] m_axi_RID, - (* RS_HS = "r.data" *) input wire [1:0] m_axi_RRESP, - - - // push read addr here - (* RS_HS = "read_addr.data" *) input wire [AddrWidth-1:0] read_addr_din, - (* RS_HS = "read_addr.valid" *) input wire read_addr_write, - (* RS_HS = "read_addr.ready" *) output wire read_addr_full_n, - - // pop read resp here - (* RS_HS = "read_data.data" *) output wire [DataWidth-1:0] read_data_dout, - (* RS_HS = "read_data.ready" *) input wire read_data_read, - (* RS_HS = "read_data.valid" *) output wire read_data_empty_n, - - // push write addr and data here - (* RS_HS = "write_addr.data" *) input wire [AddrWidth-1:0] write_addr_din, - (* RS_HS = "write_addr.valid" *) input wire write_addr_write, - (* RS_HS = "write_addr.ready" *) output wire write_addr_full_n, - (* RS_HS = "write_data.data" *) input wire [DataWidth-1:0] write_data_din, - (* RS_HS = "write_data.valid" *) input wire write_data_write, - (* RS_HS = "write_data.ready" *) output wire write_data_full_n, - - // pop write resp here - (* RS_HS = "write_resp.data" *) output wire [7:0] write_resp_dout, - (* RS_HS = "write_resp.ready" *) input wire write_resp_read, - (* RS_HS = "write_resp.valid" *) output wire write_resp_empty_n -); - - // write addr buffer, from user to burst detector - wire [AddrWidth-1:0] write_addr_dout; - wire write_addr_empty_n; - wire write_addr_read; - - relay_station #( - .DATA_WIDTH(AddrWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) write_addr ( - .clk (clk), - .reset(rst), - - // from user - .if_full_n (write_addr_full_n), - .if_write_ce(1'b1), - .if_write (write_addr_write), - .if_din (offset + (write_addr_din << $clog2(DataWidth/8))), - - // to burst detector - .if_empty_n(write_addr_empty_n), - .if_read_ce(1'b1), - .if_read (write_addr_read), - .if_dout (write_addr_dout) - ); - - // burst write addr buffer, from burst detector to axi - wire [BurstLenWidth+AddrWidth-1:0] burst_write_addr_din; - wire burst_write_addr_full_n; - wire burst_write_addr_write; - wire [AddrWidth-1:0] burst_write_addr_dout_addr; - wire [BurstLenWidth-1:0] burst_write_addr_dout_burst_len; - wire burst_write_addr_empty_n; - wire burst_write_addr_read; - - wire [BurstLenWidth-1:0] burst_write_len_din; - wire burst_write_len_full_n; - wire burst_write_len_write; - wire [BurstLenWidth-1:0] burst_write_len_dout; - wire burst_write_len_empty_n; - wire burst_write_len_read; - - wire [BurstLenWidth-1:0] write_req_din; - wire write_req_write; - wire write_req_full_n; - wire [BurstLenWidth-1:0] write_req_dout; - wire write_req_read; - wire write_req_empty_n; - - wire burst_write_last_din; - wire burst_write_last_full_n; - wire burst_write_last_write; - wire burst_write_last_dout; - wire burst_write_last_empty_n; - - detect_burst #( - .AddrWidth (AddrWidth), - .DataWidthBytesLog(DataWidthBytesLog), - .WaitTimeWidth (WaitTimeWidth), - .BurstLenWidth (BurstLenWidth) - ) detect_burst_write ( - .clk(clk), - .rst(rst), - - .max_wait_time(MaxWaitTime[WaitTimeWidth-1:0]), - .max_burst_len(MaxBurstLen[BurstLenWidth-1:0]), - - // input: individual addresses - .addr_dout (write_addr_dout), - .addr_empty_n(write_addr_empty_n), - .addr_read (write_addr_read), - - // output: inferred burst addresses - .addr_din (burst_write_addr_din), - .addr_full_n(burst_write_addr_full_n), - .addr_write (burst_write_addr_write), - - // output: used to generate the "last" signals - .burst_len_0_din (burst_write_len_din), - .burst_len_0_full_n(burst_write_len_full_n), - .burst_len_0_write (burst_write_len_write), - - // output: used to generate write responses - .burst_len_1_din (write_req_din), - .burst_len_1_full_n(write_req_full_n), - .burst_len_1_write (write_req_write) - ); - - relay_station #( - .DATA_WIDTH(BurstLenWidth + AddrWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) burst_write_addr ( - .clk (clk), - .reset(rst), - - // from burst detector - .if_full_n (burst_write_addr_full_n), - .if_write_ce(1'b1), - .if_write (burst_write_addr_write), - .if_din (burst_write_addr_din), - - // to axi - .if_empty_n(burst_write_addr_empty_n), - .if_read_ce(1'b1), - .if_read (burst_write_addr_read), - .if_dout ({burst_write_addr_dout_burst_len, burst_write_addr_dout_addr}) - ); - - relay_station #( - .DATA_WIDTH(BurstLenWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) burst_write_len ( - .clk (clk), - .reset(rst), - - // from burst detector - .if_full_n (burst_write_len_full_n), - .if_write_ce(1'b1), - .if_write (burst_write_len_write), - .if_din (burst_write_len_din), - - // to last generator - .if_empty_n(burst_write_len_empty_n), - .if_read_ce(1'b1), - .if_read (burst_write_len_read), - .if_dout (burst_write_len_dout) - ); - - // generate last signal for W channel - generate_last #( - .BurstLenWidth(BurstLenWidth) - ) generate_last_unit( - .clk(clk), - .rst(rst), - - .burst_len_dout (burst_write_len_dout), - .burst_len_empty_n(burst_write_len_empty_n), - .burst_len_read (burst_write_len_read), - - .last_din (burst_write_last_din), - .last_full_n(burst_write_last_full_n), - .last_write (burst_write_last_write) - ); - - // write req buffer that remembers the burst length of each write transaction - relay_station #( - .DATA_WIDTH(BurstLenWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) write_req ( - .clk (clk), - .reset(rst), - - // from burst detector - .if_full_n (write_req_full_n), - .if_write_ce(1'b1), - .if_write (write_req_write), - .if_din (write_req_din), - - // to write resp buffer - .if_empty_n(write_req_empty_n), - .if_read_ce(1'b1), - .if_read (write_req_read), - .if_dout (write_req_dout) - ); - - // write data buffer - wire [DataWidth-1:0] write_data_dout; - wire write_data_empty_n; - relay_station #( - .DATA_WIDTH(DataWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) write_data ( - .clk (clk), - .reset(rst), - - // from user - .if_full_n (write_data_full_n), - .if_write_ce(1'b1), - .if_write (write_data_write), - .if_din (write_data_din), - - // to axi - .if_empty_n(write_data_empty_n), - .if_read_ce(1'b1), - // deal with when data-relay_station is non empty but last-relay_station is empty - .if_read (m_axi_WREADY && burst_write_last_empty_n), - .if_dout (write_data_dout) - ); - - // this relay_station should be synchronized with the wr_data relay_station - relay_station #( - .DATA_WIDTH(1), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) burst_write_last ( - .clk (clk), - .reset(rst), - - // from burst detector - .if_full_n (burst_write_last_full_n), - .if_write_ce(1'b1), - .if_write (burst_write_last_write), - .if_din (burst_write_last_din), - - // to axi - .if_empty_n(burst_write_last_empty_n), - .if_read_ce(1'b1), - // deal with when last-relay_station is non-empty while data-relay_station is empty - .if_read (m_axi_WREADY && write_data_empty_n), - .if_dout (burst_write_last_dout) - ); - - // write resp buffer - wire [BurstLenWidth-1:0] write_resp_din = write_req_dout; - wire write_resp_write = m_axi_BVALID && write_req_empty_n; - wire write_resp_full_n; - relay_station #( - .DATA_WIDTH(BurstLenWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableWriteChannel) - ) write_resp ( - .clk (clk), - .reset(rst), - - // from write req buffer and axi - .if_full_n (write_resp_full_n), - .if_write_ce(1'b1), - .if_write (write_resp_write), - .if_din (write_resp_din), - - // to user - .if_empty_n(write_resp_empty_n), - .if_read_ce(1'b1), - .if_read (write_resp_read), - .if_dout (write_resp_dout) - ); - - // AW channel - assign burst_write_addr_read = m_axi_AWREADY; - assign m_axi_AWVALID = burst_write_addr_empty_n; - assign m_axi_AWADDR = {{(AxiSideAddrWidth - AddrWidth){1'b0}}, burst_write_addr_dout_addr}; - assign m_axi_AWID = 0; - assign m_axi_AWLEN = burst_write_addr_dout_burst_len; - assign m_axi_AWSIZE = DataWidthBytesLog; - assign m_axi_AWBURST = 1; // INCR mode - assign m_axi_AWLOCK = 0; // Xilinx only supports 0 - assign m_axi_AWCACHE = 4'b0011; // Xilinx only supports 4'b0011 - assign m_axi_AWPROT = 0; - assign m_axi_AWQOS = 0; - - // W channel - assign m_axi_WVALID = write_data_empty_n && burst_write_last_empty_n; - assign m_axi_WDATA = write_data_dout; - assign m_axi_WSTRB = {(DataWidth/8){1'b1}}; // assume every bit is valid - assign m_axi_WLAST = burst_write_last_dout; - - // B channel - assign m_axi_BREADY = write_resp_full_n && write_req_empty_n; - assign write_req_read = write_resp_full_n && m_axi_BVALID; - - // read addr buffer, from user to burst detector - wire [AddrWidth-1:0] read_addr_dout; - wire read_addr_empty_n; - wire read_addr_read; - - relay_station #( - .DATA_WIDTH(AddrWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableReadChannel) - ) read_addr ( - .clk (clk), - .reset(rst), - - // from user - .if_full_n (read_addr_full_n), - .if_write_ce(1'b1), - .if_write (read_addr_write), - .if_din (offset + (read_addr_din << $clog2(DataWidth/8))), - - // to axi - .if_empty_n(read_addr_empty_n), - .if_read_ce(1'b1), - .if_read (read_addr_read), - .if_dout (read_addr_dout) - ); - - wire [BurstLenWidth+AddrWidth-1:0] burst_read_addr_din; - wire burst_read_addr_full_n; - wire burst_read_addr_write; - wire [AddrWidth-1:0] burst_read_addr_dout_addr; - wire [BurstLenWidth-1:0] burst_read_addr_dout_burst_len; - wire burst_read_addr_empty_n; - wire burst_read_addr_read; - - relay_station #( - .DATA_WIDTH(BurstLenWidth + AddrWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableReadChannel) - ) burst_read_addr ( - .clk (clk), - .reset(rst), - - // from burst detector - .if_full_n (burst_read_addr_full_n), - .if_write_ce(1'b1), - .if_write (burst_read_addr_write), - .if_din (burst_read_addr_din), - - // to axi - .if_empty_n(burst_read_addr_empty_n), - .if_read_ce(1'b1), - .if_read (burst_read_addr_read), - .if_dout ({burst_read_addr_dout_burst_len, burst_read_addr_dout_addr}) - ); - - detect_burst #( - .AddrWidth (AddrWidth), - .DataWidthBytesLog(DataWidthBytesLog), - .WaitTimeWidth (WaitTimeWidth), - .BurstLenWidth (BurstLenWidth) - ) detect_burst_read ( - .clk(clk), - .rst(rst), - - .max_wait_time(MaxWaitTime[WaitTimeWidth-1:0]), - .max_burst_len(MaxBurstLen[BurstLenWidth-1:0]), - - // input: individual addresses - .addr_dout (read_addr_dout), - .addr_empty_n(read_addr_empty_n), - .addr_read (read_addr_read), - - // output: inferred burst addresses - .addr_din (burst_read_addr_din), - .addr_full_n(burst_read_addr_full_n), - .addr_write (burst_read_addr_write), - - // output: used to generate the "last" signals, unused - .burst_len_0_din (), - .burst_len_0_full_n(1'b1), - .burst_len_0_write (), - - // output: used to generate write responses, unused - .burst_len_1_din (), - .burst_len_1_full_n(1'b1), - .burst_len_1_write () - ); - - // read resp buffer - wire [DataWidth-1:0] read_data_din; - wire read_data_write; - wire read_data_full_n; - relay_station #( - .DATA_WIDTH(DataWidth), - .ADDR_WIDTH(BufferSizeLog), - .DEPTH (BufferSize), - .LEVEL (1), - .CONNECT (EnableReadChannel) - ) read_data ( - .clk (clk), - .reset(rst), - - // from axi - .if_full_n (read_data_full_n), - .if_write_ce(1'b1), - .if_write (read_data_write), - .if_din (read_data_din), - - // to user - .if_empty_n(read_data_empty_n), - .if_read_ce(1'b1), - .if_read (read_data_read), - .if_dout (read_data_dout) - ); - - // AR channel - assign burst_read_addr_read = m_axi_ARREADY; - assign m_axi_ARVALID = burst_read_addr_empty_n; - assign m_axi_ARADDR = {{(AxiSideAddrWidth - AddrWidth){1'b0}}, burst_read_addr_dout_addr}; - assign m_axi_ARID = 0; - assign m_axi_ARLEN = burst_read_addr_dout_burst_len; - assign m_axi_ARSIZE = DataWidthBytesLog; - assign m_axi_ARBURST = 1; // INCR mode - assign m_axi_ARLOCK = 0; // Xilinx only supports 0 - assign m_axi_ARCACHE = 4'b0011; // Xilinx only supports 4'b0011 - assign m_axi_ARPROT = 0; - assign m_axi_ARQOS = 0; - - // R channel - assign m_axi_RREADY = read_data_full_n; - assign read_data_write = m_axi_RVALID; - assign read_data_din = m_axi_RDATA; - - // unused input signals - wire _unused = &{1'b0, - m_axi_BRESP, - m_axi_BID, - m_axi_RLAST, - m_axi_RID, - m_axi_RRESP, - 1'b0}; - -endmodule // async_mmap - -`default_nettype wire diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar.v deleted file mode 100644 index 991d4540..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar.v +++ /dev/null @@ -1,391 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 crossbar - */ -module axi_crossbar # -( - // Number of AXI inputs (slave interfaces) - parameter S_COUNT = 4, - // Number of AXI outputs (master interfaces) - parameter M_COUNT = 4, - // Width of data bus in bits - parameter DATA_WIDTH = 32, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // Width of wstrb (width of data bus in words) - parameter STRB_WIDTH = (DATA_WIDTH/8), - // Input ID field width (from AXI masters) - parameter S_ID_WIDTH = 8, - // Output ID field width (towards AXI slaves) - // Additional bits required for response routing - parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), - // Propagate awuser signal - parameter AWUSER_ENABLE = 0, - // Width of awuser signal - parameter AWUSER_WIDTH = 1, - // Propagate wuser signal - parameter WUSER_ENABLE = 0, - // Width of wuser signal - parameter WUSER_WIDTH = 1, - // Propagate buser signal - parameter BUSER_ENABLE = 0, - // Width of buser signal - parameter BUSER_WIDTH = 1, - // Propagate aruser signal - parameter ARUSER_ENABLE = 0, - // Width of aruser signal - parameter ARUSER_WIDTH = 1, - // Propagate ruser signal - parameter RUSER_ENABLE = 0, - // Width of ruser signal - parameter RUSER_WIDTH = 1, - // Number of concurrent unique IDs for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_THREADS = {S_COUNT{32'd2}}, - // Number of concurrent operations for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_ACCEPT = {S_COUNT{32'd16}}, - // Number of regions per master interface - parameter M_REGIONS = 1, - // Master interface base addresses - // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits - // set to zero for default addressing based on M_ADDR_WIDTH - parameter M_BASE_ADDR = 0, - // Master interface address widths - // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits - parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}}, - // Read connections between interfaces - // M_COUNT concatenated fields of S_COUNT bits - parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}}, - // Write connections between interfaces - // M_COUNT concatenated fields of S_COUNT bits - parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}}, - // Number of concurrent operations for each master interface - // M_COUNT concatenated fields of 32 bits - parameter M_ISSUE = {M_COUNT{32'd4}}, - // Secure master (fail operations based on awprot/arprot) - // M_COUNT bits - parameter M_SECURE = {M_COUNT{1'b0}}, - // Slave interface AW channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_AW_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface W channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_W_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface B channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_B_REG_TYPE = {S_COUNT{2'd1}}, - // Slave interface AR channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_AR_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface R channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_R_REG_TYPE = {S_COUNT{2'd2}}, - // Master interface AW channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, - // Master interface W channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, - // Master interface B channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_B_REG_TYPE = {M_COUNT{2'd0}}, - // Master interface AR channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, - // Master interface R channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_R_REG_TYPE = {M_COUNT{2'd0}} -) -( - input wire clk, - input wire rst, - - /* - * AXI slave interfaces - */ - input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_awid, - input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr, - input wire [S_COUNT*8-1:0] s_axi_awlen, - input wire [S_COUNT*3-1:0] s_axi_awsize, - input wire [S_COUNT*2-1:0] s_axi_awburst, - input wire [S_COUNT-1:0] s_axi_awlock, - input wire [S_COUNT*4-1:0] s_axi_awcache, - input wire [S_COUNT*3-1:0] s_axi_awprot, - input wire [S_COUNT*4-1:0] s_axi_awqos, - input wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser, - input wire [S_COUNT-1:0] s_axi_awvalid, - output wire [S_COUNT-1:0] s_axi_awready, - input wire [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata, - input wire [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb, - input wire [S_COUNT-1:0] s_axi_wlast, - input wire [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser, - input wire [S_COUNT-1:0] s_axi_wvalid, - output wire [S_COUNT-1:0] s_axi_wready, - output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_bid, - output wire [S_COUNT*2-1:0] s_axi_bresp, - output wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser, - output wire [S_COUNT-1:0] s_axi_bvalid, - input wire [S_COUNT-1:0] s_axi_bready, - input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_arid, - input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr, - input wire [S_COUNT*8-1:0] s_axi_arlen, - input wire [S_COUNT*3-1:0] s_axi_arsize, - input wire [S_COUNT*2-1:0] s_axi_arburst, - input wire [S_COUNT-1:0] s_axi_arlock, - input wire [S_COUNT*4-1:0] s_axi_arcache, - input wire [S_COUNT*3-1:0] s_axi_arprot, - input wire [S_COUNT*4-1:0] s_axi_arqos, - input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser, - input wire [S_COUNT-1:0] s_axi_arvalid, - output wire [S_COUNT-1:0] s_axi_arready, - output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_rid, - output wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata, - output wire [S_COUNT*2-1:0] s_axi_rresp, - output wire [S_COUNT-1:0] s_axi_rlast, - output wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser, - output wire [S_COUNT-1:0] s_axi_rvalid, - input wire [S_COUNT-1:0] s_axi_rready, - - /* - * AXI master interfaces - */ - output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_awid, - output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [M_COUNT*8-1:0] m_axi_awlen, - output wire [M_COUNT*3-1:0] m_axi_awsize, - output wire [M_COUNT*2-1:0] m_axi_awburst, - output wire [M_COUNT-1:0] m_axi_awlock, - output wire [M_COUNT*4-1:0] m_axi_awcache, - output wire [M_COUNT*3-1:0] m_axi_awprot, - output wire [M_COUNT*4-1:0] m_axi_awqos, - output wire [M_COUNT*4-1:0] m_axi_awregion, - output wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser, - output wire [M_COUNT-1:0] m_axi_awvalid, - input wire [M_COUNT-1:0] m_axi_awready, - output wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata, - output wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb, - output wire [M_COUNT-1:0] m_axi_wlast, - output wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser, - output wire [M_COUNT-1:0] m_axi_wvalid, - input wire [M_COUNT-1:0] m_axi_wready, - input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_bid, - input wire [M_COUNT*2-1:0] m_axi_bresp, - input wire [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser, - input wire [M_COUNT-1:0] m_axi_bvalid, - output wire [M_COUNT-1:0] m_axi_bready, - output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_arid, - output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr, - output wire [M_COUNT*8-1:0] m_axi_arlen, - output wire [M_COUNT*3-1:0] m_axi_arsize, - output wire [M_COUNT*2-1:0] m_axi_arburst, - output wire [M_COUNT-1:0] m_axi_arlock, - output wire [M_COUNT*4-1:0] m_axi_arcache, - output wire [M_COUNT*3-1:0] m_axi_arprot, - output wire [M_COUNT*4-1:0] m_axi_arqos, - output wire [M_COUNT*4-1:0] m_axi_arregion, - output wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser, - output wire [M_COUNT-1:0] m_axi_arvalid, - input wire [M_COUNT-1:0] m_axi_arready, - input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_rid, - input wire [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata, - input wire [M_COUNT*2-1:0] m_axi_rresp, - input wire [M_COUNT-1:0] m_axi_rlast, - input wire [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser, - input wire [M_COUNT-1:0] m_axi_rvalid, - output wire [M_COUNT-1:0] m_axi_rready -); - -axi_crossbar_wr #( - .S_COUNT(S_COUNT), - .M_COUNT(M_COUNT), - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .S_ID_WIDTH(S_ID_WIDTH), - .M_ID_WIDTH(M_ID_WIDTH), - .AWUSER_ENABLE(AWUSER_ENABLE), - .AWUSER_WIDTH(AWUSER_WIDTH), - .WUSER_ENABLE(WUSER_ENABLE), - .WUSER_WIDTH(WUSER_WIDTH), - .BUSER_ENABLE(BUSER_ENABLE), - .BUSER_WIDTH(BUSER_WIDTH), - .S_THREADS(S_THREADS), - .S_ACCEPT(S_ACCEPT), - .M_REGIONS(M_REGIONS), - .M_BASE_ADDR(M_BASE_ADDR), - .M_ADDR_WIDTH(M_ADDR_WIDTH), - .M_CONNECT(M_CONNECT_WRITE), - .M_ISSUE(M_ISSUE), - .M_SECURE(M_SECURE), - .S_AW_REG_TYPE(S_AW_REG_TYPE), - .S_W_REG_TYPE (S_W_REG_TYPE), - .S_B_REG_TYPE (S_B_REG_TYPE) -) -axi_crossbar_wr_inst ( - .clk(clk), - .rst(rst), - - /* - * AXI slave interfaces - */ - .s_axi_awid(s_axi_awid), - .s_axi_awaddr(s_axi_awaddr), - .s_axi_awlen(s_axi_awlen), - .s_axi_awsize(s_axi_awsize), - .s_axi_awburst(s_axi_awburst), - .s_axi_awlock(s_axi_awlock), - .s_axi_awcache(s_axi_awcache), - .s_axi_awprot(s_axi_awprot), - .s_axi_awqos(s_axi_awqos), - .s_axi_awuser(s_axi_awuser), - .s_axi_awvalid(s_axi_awvalid), - .s_axi_awready(s_axi_awready), - .s_axi_wdata(s_axi_wdata), - .s_axi_wstrb(s_axi_wstrb), - .s_axi_wlast(s_axi_wlast), - .s_axi_wuser(s_axi_wuser), - .s_axi_wvalid(s_axi_wvalid), - .s_axi_wready(s_axi_wready), - .s_axi_bid(s_axi_bid), - .s_axi_bresp(s_axi_bresp), - .s_axi_buser(s_axi_buser), - .s_axi_bvalid(s_axi_bvalid), - .s_axi_bready(s_axi_bready), - - /* - * AXI master interfaces - */ - .m_axi_awid(m_axi_awid), - .m_axi_awaddr(m_axi_awaddr), - .m_axi_awlen(m_axi_awlen), - .m_axi_awsize(m_axi_awsize), - .m_axi_awburst(m_axi_awburst), - .m_axi_awlock(m_axi_awlock), - .m_axi_awcache(m_axi_awcache), - .m_axi_awprot(m_axi_awprot), - .m_axi_awqos(m_axi_awqos), - .m_axi_awregion(m_axi_awregion), - .m_axi_awuser(m_axi_awuser), - .m_axi_awvalid(m_axi_awvalid), - .m_axi_awready(m_axi_awready), - .m_axi_wdata(m_axi_wdata), - .m_axi_wstrb(m_axi_wstrb), - .m_axi_wlast(m_axi_wlast), - .m_axi_wuser(m_axi_wuser), - .m_axi_wvalid(m_axi_wvalid), - .m_axi_wready(m_axi_wready), - .m_axi_bid(m_axi_bid), - .m_axi_bresp(m_axi_bresp), - .m_axi_buser(m_axi_buser), - .m_axi_bvalid(m_axi_bvalid), - .m_axi_bready(m_axi_bready) -); - -axi_crossbar_rd #( - .S_COUNT(S_COUNT), - .M_COUNT(M_COUNT), - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .S_ID_WIDTH(S_ID_WIDTH), - .M_ID_WIDTH(M_ID_WIDTH), - .ARUSER_ENABLE(ARUSER_ENABLE), - .ARUSER_WIDTH(ARUSER_WIDTH), - .RUSER_ENABLE(RUSER_ENABLE), - .RUSER_WIDTH(RUSER_WIDTH), - .S_THREADS(S_THREADS), - .S_ACCEPT(S_ACCEPT), - .M_REGIONS(M_REGIONS), - .M_BASE_ADDR(M_BASE_ADDR), - .M_ADDR_WIDTH(M_ADDR_WIDTH), - .M_CONNECT(M_CONNECT_READ), - .M_ISSUE(M_ISSUE), - .M_SECURE(M_SECURE), - .S_AR_REG_TYPE(S_AR_REG_TYPE), - .S_R_REG_TYPE (S_R_REG_TYPE) -) -axi_crossbar_rd_inst ( - .clk(clk), - .rst(rst), - - /* - * AXI slave interfaces - */ - .s_axi_arid(s_axi_arid), - .s_axi_araddr(s_axi_araddr), - .s_axi_arlen(s_axi_arlen), - .s_axi_arsize(s_axi_arsize), - .s_axi_arburst(s_axi_arburst), - .s_axi_arlock(s_axi_arlock), - .s_axi_arcache(s_axi_arcache), - .s_axi_arprot(s_axi_arprot), - .s_axi_arqos(s_axi_arqos), - .s_axi_aruser(s_axi_aruser), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_arready(s_axi_arready), - .s_axi_rid(s_axi_rid), - .s_axi_rdata(s_axi_rdata), - .s_axi_rresp(s_axi_rresp), - .s_axi_rlast(s_axi_rlast), - .s_axi_ruser(s_axi_ruser), - .s_axi_rvalid(s_axi_rvalid), - .s_axi_rready(s_axi_rready), - - /* - * AXI master interfaces - */ - .m_axi_arid(m_axi_arid), - .m_axi_araddr(m_axi_araddr), - .m_axi_arlen(m_axi_arlen), - .m_axi_arsize(m_axi_arsize), - .m_axi_arburst(m_axi_arburst), - .m_axi_arlock(m_axi_arlock), - .m_axi_arcache(m_axi_arcache), - .m_axi_arprot(m_axi_arprot), - .m_axi_arqos(m_axi_arqos), - .m_axi_arregion(m_axi_arregion), - .m_axi_aruser(m_axi_aruser), - .m_axi_arvalid(m_axi_arvalid), - .m_axi_arready(m_axi_arready), - .m_axi_rid(m_axi_rid), - .m_axi_rdata(m_axi_rdata), - .m_axi_rresp(m_axi_rresp), - .m_axi_rlast(m_axi_rlast), - .m_axi_ruser(m_axi_ruser), - .m_axi_rvalid(m_axi_rvalid), - .m_axi_rready(m_axi_rready) -); - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar_addr.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar_addr.v deleted file mode 100644 index 7b784652..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar_addr.v +++ /dev/null @@ -1,418 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 crossbar address decode and admission control - */ -module axi_crossbar_addr # -( - // Slave interface index - parameter S = 0, - // Number of AXI inputs (slave interfaces) - parameter S_COUNT = 4, - // Number of AXI outputs (master interfaces) - parameter M_COUNT = 4, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // ID field width - parameter ID_WIDTH = 8, - // Number of concurrent unique IDs - parameter S_THREADS = 32'd2, - // Number of concurrent operations - parameter S_ACCEPT = 32'd16, - // Number of regions per master interface - parameter M_REGIONS = 1, - // Master interface base addresses - // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits - // set to zero for default addressing based on M_ADDR_WIDTH - parameter M_BASE_ADDR = 0, - // Master interface address widths - // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits - parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}}, - // Connections between interfaces - // M_COUNT concatenated fields of S_COUNT bits - parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, - // Secure master (fail operations based on awprot/arprot) - // M_COUNT bits - parameter M_SECURE = {M_COUNT{1'b0}}, - // Enable write command output - parameter WC_OUTPUT = 0 -) -( - input wire clk, - input wire rst, - - /* - * Address input - */ - input wire [ID_WIDTH-1:0] s_axi_aid, - input wire [ADDR_WIDTH-1:0] s_axi_aaddr, - input wire [2:0] s_axi_aprot, - input wire [3:0] s_axi_aqos, - input wire s_axi_avalid, - output wire s_axi_aready, - - /* - * Address output - */ - output wire [3:0] m_axi_aregion, - output wire [$clog2(M_COUNT)-1:0] m_select, - output wire m_axi_avalid, - input wire m_axi_aready, - - /* - * Write command output - */ - output wire [$clog2(M_COUNT)-1:0] m_wc_select, - output wire m_wc_decerr, - output wire m_wc_valid, - input wire m_wc_ready, - - /* - * Reply command output - */ - output wire m_rc_decerr, - output wire m_rc_valid, - input wire m_rc_ready, - - /* - * Completion input - */ - input wire [ID_WIDTH-1:0] s_cpl_id, - input wire s_cpl_valid -); - -parameter CL_S_COUNT = $clog2(S_COUNT); -parameter CL_M_COUNT = $clog2(M_COUNT); - -parameter S_INT_THREADS = S_THREADS > S_ACCEPT ? S_ACCEPT : S_THREADS; -parameter CL_S_INT_THREADS = $clog2(S_INT_THREADS); -parameter CL_S_ACCEPT = $clog2(S_ACCEPT); - -// default address computation -function [M_COUNT*M_REGIONS*ADDR_WIDTH-1:0] calcBaseAddrs(input [31:0] dummy); - integer i; - reg [ADDR_WIDTH-1:0] base; - reg [ADDR_WIDTH-1:0] width; - reg [ADDR_WIDTH-1:0] size; - reg [ADDR_WIDTH-1:0] mask; - begin - calcBaseAddrs = {M_COUNT*M_REGIONS*ADDR_WIDTH{1'b0}}; - base = 0; - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - width = M_ADDR_WIDTH[i*32 +: 32]; - mask = {ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - width); - size = mask + 1; - if (width > 0) begin - if ((base & mask) != 0) begin - base = base + size - (base & mask); // align - end - calcBaseAddrs[i * ADDR_WIDTH +: ADDR_WIDTH] = base; - base = base + size; // increment - end - end - end -endfunction - -parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); - -integer i, j; - -// check configuration -initial begin - if (S_ACCEPT < 1) begin - $error("Error: need at least 1 accept (instance %m)"); - $finish; - end - - if (S_THREADS < 1) begin - $error("Error: need at least 1 thread (instance %m)"); - $finish; - end - - if (S_THREADS > S_ACCEPT) begin - $warning("Warning: requested thread count larger than accept count; limiting thread count to accept count (instance %m)"); - end - - if (M_REGIONS < 1) begin - $error("Error: need at least 1 region (instance %m)"); - $finish; - end - - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin - $error("Error: address width out of range (instance %m)"); - $finish; - end - end - - $display("Addressing configuration for axi_crossbar_addr instance %m"); - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32]) begin - $display("%2d (%2d): %x / %02d -- %x-%x", - i/M_REGIONS, i%M_REGIONS, - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH], - M_ADDR_WIDTH[i*32 +: 32], - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])) - ); - end - end - - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if ((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & (2**M_ADDR_WIDTH[i*32 +: 32]-1)) != 0) begin - $display("Region not aligned:"); - $display("%2d (%2d): %x / %2d -- %x-%x", - i/M_REGIONS, i%M_REGIONS, - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH], - M_ADDR_WIDTH[i*32 +: 32], - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])) - ); - $error("Error: address range not aligned (instance %m)"); - $finish; - end - end - - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - for (j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[j*32 +: 32]) begin - if (((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])))) - && ((M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32])) <= (M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))))) begin - $display("Overlapping regions:"); - $display("%2d (%2d): %x / %2d -- %x-%x", - i/M_REGIONS, i%M_REGIONS, - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH], - M_ADDR_WIDTH[i*32 +: 32], - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), - M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])) - ); - $display("%2d (%2d): %x / %2d -- %x-%x", - j/M_REGIONS, j%M_REGIONS, - M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH], - M_ADDR_WIDTH[j*32 +: 32], - M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]), - M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])) - ); - $error("Error: address ranges overlap (instance %m)"); - $finish; - end - end - end - end -end - -localparam [2:0] - STATE_IDLE = 3'd0, - STATE_DECODE = 3'd1; - -reg [2:0] state_reg = STATE_IDLE, state_next; - -reg s_axi_aready_reg = 0, s_axi_aready_next; - -reg [3:0] m_axi_aregion_reg = 4'd0, m_axi_aregion_next; -reg [CL_M_COUNT-1:0] m_select_reg = 0, m_select_next; -reg m_axi_avalid_reg = 1'b0, m_axi_avalid_next; -reg m_decerr_reg = 1'b0, m_decerr_next; -reg m_wc_valid_reg = 1'b0, m_wc_valid_next; -reg m_rc_valid_reg = 1'b0, m_rc_valid_next; - -assign s_axi_aready = s_axi_aready_reg; - -assign m_axi_aregion = m_axi_aregion_reg; -assign m_select = m_select_reg; -assign m_axi_avalid = m_axi_avalid_reg; - -assign m_wc_select = m_select_reg; -assign m_wc_decerr = m_decerr_reg; -assign m_wc_valid = m_wc_valid_reg; - -assign m_rc_decerr = m_decerr_reg; -assign m_rc_valid = m_rc_valid_reg; - -reg match; -reg trans_start; -reg trans_complete; - -reg [$clog2(S_ACCEPT+1)-1:0] trans_count_reg = 0; -wire trans_limit = trans_count_reg >= S_ACCEPT && !trans_complete; - -// transfer ID thread tracking -reg [ID_WIDTH-1:0] thread_id_reg[S_INT_THREADS-1:0]; -reg [CL_M_COUNT-1:0] thread_m_reg[S_INT_THREADS-1:0]; -reg [3:0] thread_region_reg[S_INT_THREADS-1:0]; -reg [$clog2(S_ACCEPT+1)-1:0] thread_count_reg[S_INT_THREADS-1:0]; - -wire [S_INT_THREADS-1:0] thread_active; -wire [S_INT_THREADS-1:0] thread_match; -wire [S_INT_THREADS-1:0] thread_match_dest; -wire [S_INT_THREADS-1:0] thread_cpl_match; -wire [S_INT_THREADS-1:0] thread_trans_start; -wire [S_INT_THREADS-1:0] thread_trans_complete; - -generate - genvar n; - - for (n = 0; n < S_INT_THREADS; n = n + 1) begin - initial begin - thread_count_reg[n] <= 0; - end - - assign thread_active[n] = thread_count_reg[n] != 0; - assign thread_match[n] = thread_active[n] && thread_id_reg[n] == s_axi_aid; - assign thread_match_dest[n] = thread_match[n] && thread_m_reg[n] == m_select_next && (M_REGIONS < 2 || thread_region_reg[n] == m_axi_aregion_next); - assign thread_cpl_match[n] = thread_active[n] && thread_id_reg[n] == s_cpl_id; - assign thread_trans_start[n] = (thread_match[n] || (!thread_active[n] && !thread_match && !(thread_trans_start & ({S_INT_THREADS{1'b1}} >> (S_INT_THREADS-n))))) && trans_start; - assign thread_trans_complete[n] = thread_cpl_match[n] && trans_complete; - - always @(posedge clk) begin - if (rst) begin - thread_count_reg[n] <= 0; - end else begin - if (thread_trans_start[n] && !thread_trans_complete[n]) begin - thread_count_reg[n] <= thread_count_reg[n] + 1; - end else if (!thread_trans_start[n] && thread_trans_complete[n]) begin - thread_count_reg[n] <= thread_count_reg[n] - 1; - end - end - - if (thread_trans_start[n]) begin - thread_id_reg[n] <= s_axi_aid; - thread_m_reg[n] <= m_select_next; - thread_region_reg[n] <= m_axi_aregion_next; - end - end - end -endgenerate - -always @* begin - state_next = STATE_IDLE; - - match = 1'b0; - trans_start = 1'b0; - trans_complete = 1'b0; - - s_axi_aready_next = 1'b0; - - m_axi_aregion_next = m_axi_aregion_reg; - m_select_next = m_select_reg; - m_axi_avalid_next = m_axi_avalid_reg && !m_axi_aready; - m_decerr_next = m_decerr_reg; - m_wc_valid_next = m_wc_valid_reg && !m_wc_ready; - m_rc_valid_next = m_rc_valid_reg && !m_rc_ready; - - case (state_reg) - STATE_IDLE: begin - // idle state, store values - s_axi_aready_next = 1'b0; - - if (s_axi_avalid && !s_axi_aready) begin - match = 1'b0; - for (i = 0; i < M_COUNT; i = i + 1) begin - for (j = 0; j < M_REGIONS; j = j + 1) begin - if (M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32] && (!M_SECURE[i] || !s_axi_aprot[1]) && (M_CONNECT & (1 << (S+i*S_COUNT))) && (s_axi_aaddr >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32]) == (M_BASE_ADDR_INT[(i*M_REGIONS+j)*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32])) begin - m_select_next = i; - m_axi_aregion_next = j; - match = 1'b1; - end - end - end - - if (match) begin - // address decode successful - if (!trans_limit && (thread_match_dest || (!(&thread_active) && !thread_match))) begin - // transaction limit not reached - m_axi_avalid_next = 1'b1; - m_decerr_next = 1'b0; - m_wc_valid_next = WC_OUTPUT; - m_rc_valid_next = 1'b0; - trans_start = 1'b1; - state_next = STATE_DECODE; - end else begin - // transaction limit reached; block in idle - state_next = STATE_IDLE; - end - end else begin - // decode error - m_axi_avalid_next = 1'b0; - m_decerr_next = 1'b1; - m_wc_valid_next = WC_OUTPUT; - m_rc_valid_next = 1'b1; - state_next = STATE_DECODE; - end - end else begin - state_next = STATE_IDLE; - end - end - STATE_DECODE: begin - if (!m_axi_avalid_next && (!m_wc_valid_next || !WC_OUTPUT) && !m_rc_valid_next) begin - s_axi_aready_next = 1'b1; - state_next = STATE_IDLE; - end else begin - state_next = STATE_DECODE; - end - end - endcase - - // manage completions - trans_complete = s_cpl_valid; -end - -always @(posedge clk) begin - if (rst) begin - state_reg <= STATE_IDLE; - s_axi_aready_reg <= 1'b0; - m_axi_avalid_reg <= 1'b0; - m_wc_valid_reg <= 1'b0; - m_rc_valid_reg <= 1'b0; - - trans_count_reg <= 0; - end else begin - state_reg <= state_next; - s_axi_aready_reg <= s_axi_aready_next; - m_axi_avalid_reg <= m_axi_avalid_next; - m_wc_valid_reg <= m_wc_valid_next; - m_rc_valid_reg <= m_rc_valid_next; - - if (trans_start && !trans_complete) begin - trans_count_reg <= trans_count_reg + 1; - end else if (!trans_start && trans_complete) begin - trans_count_reg <= trans_count_reg - 1; - end - end - - m_axi_aregion_reg <= m_axi_aregion_next; - m_select_reg <= m_select_next; - m_decerr_reg <= m_decerr_next; -end - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar_rd.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar_rd.v deleted file mode 100644 index 2b1410ac..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar_rd.v +++ /dev/null @@ -1,569 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 crossbar (read) - */ -module axi_crossbar_rd # -( - // Number of AXI inputs (slave interfaces) - parameter S_COUNT = 4, - // Number of AXI outputs (master interfaces) - parameter M_COUNT = 4, - // Width of data bus in bits - parameter DATA_WIDTH = 32, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // Width of wstrb (width of data bus in words) - parameter STRB_WIDTH = (DATA_WIDTH/8), - // Input ID field width (from AXI masters) - parameter S_ID_WIDTH = 8, - // Output ID field width (towards AXI slaves) - // Additional bits required for response routing - parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), - // Propagate aruser signal - parameter ARUSER_ENABLE = 0, - // Width of aruser signal - parameter ARUSER_WIDTH = 1, - // Propagate ruser signal - parameter RUSER_ENABLE = 0, - // Width of ruser signal - parameter RUSER_WIDTH = 1, - // Number of concurrent unique IDs for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_THREADS = {S_COUNT{32'd2}}, - // Number of concurrent operations for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_ACCEPT = {S_COUNT{32'd16}}, - // Number of regions per master interface - parameter M_REGIONS = 1, - // Master interface base addresses - // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits - // set to zero for default addressing based on M_ADDR_WIDTH - parameter M_BASE_ADDR = 0, - // Master interface address widths - // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits - parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}}, - // Read connections between interfaces - // M_COUNT concatenated fields of S_COUNT bits - parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, - // Number of concurrent operations for each master interface - // M_COUNT concatenated fields of 32 bits - parameter M_ISSUE = {M_COUNT{32'd4}}, - // Secure master (fail operations based on awprot/arprot) - // M_COUNT bits - parameter M_SECURE = {M_COUNT{1'b0}}, - // Slave interface AR channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_AR_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface R channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_R_REG_TYPE = {S_COUNT{2'd2}}, - // Master interface AR channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, - // Master interface R channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_R_REG_TYPE = {M_COUNT{2'd0}} -) -( - input wire clk, - input wire rst, - - /* - * AXI slave interfaces - */ - input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_arid, - input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr, - input wire [S_COUNT*8-1:0] s_axi_arlen, - input wire [S_COUNT*3-1:0] s_axi_arsize, - input wire [S_COUNT*2-1:0] s_axi_arburst, - input wire [S_COUNT-1:0] s_axi_arlock, - input wire [S_COUNT*4-1:0] s_axi_arcache, - input wire [S_COUNT*3-1:0] s_axi_arprot, - input wire [S_COUNT*4-1:0] s_axi_arqos, - input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser, - input wire [S_COUNT-1:0] s_axi_arvalid, - output wire [S_COUNT-1:0] s_axi_arready, - output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_rid, - output wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata, - output wire [S_COUNT*2-1:0] s_axi_rresp, - output wire [S_COUNT-1:0] s_axi_rlast, - output wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser, - output wire [S_COUNT-1:0] s_axi_rvalid, - input wire [S_COUNT-1:0] s_axi_rready, - - /* - * AXI master interfaces - */ - output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_arid, - output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr, - output wire [M_COUNT*8-1:0] m_axi_arlen, - output wire [M_COUNT*3-1:0] m_axi_arsize, - output wire [M_COUNT*2-1:0] m_axi_arburst, - output wire [M_COUNT-1:0] m_axi_arlock, - output wire [M_COUNT*4-1:0] m_axi_arcache, - output wire [M_COUNT*3-1:0] m_axi_arprot, - output wire [M_COUNT*4-1:0] m_axi_arqos, - output wire [M_COUNT*4-1:0] m_axi_arregion, - output wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser, - output wire [M_COUNT-1:0] m_axi_arvalid, - input wire [M_COUNT-1:0] m_axi_arready, - input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_rid, - input wire [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata, - input wire [M_COUNT*2-1:0] m_axi_rresp, - input wire [M_COUNT-1:0] m_axi_rlast, - input wire [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser, - input wire [M_COUNT-1:0] m_axi_rvalid, - output wire [M_COUNT-1:0] m_axi_rready -); - -parameter CL_S_COUNT = $clog2(S_COUNT); -parameter CL_M_COUNT = $clog2(M_COUNT); -parameter M_COUNT_P1 = M_COUNT+1; -parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1); - -integer i; - -// check configuration -initial begin - if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin - $error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)"); - $finish; - end - - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin - $error("Error: value out of range (instance %m)"); - $finish; - end - end -end - -wire [S_COUNT*S_ID_WIDTH-1:0] int_s_axi_arid; -wire [S_COUNT*ADDR_WIDTH-1:0] int_s_axi_araddr; -wire [S_COUNT*8-1:0] int_s_axi_arlen; -wire [S_COUNT*3-1:0] int_s_axi_arsize; -wire [S_COUNT*2-1:0] int_s_axi_arburst; -wire [S_COUNT-1:0] int_s_axi_arlock; -wire [S_COUNT*4-1:0] int_s_axi_arcache; -wire [S_COUNT*3-1:0] int_s_axi_arprot; -wire [S_COUNT*4-1:0] int_s_axi_arqos; -wire [S_COUNT*4-1:0] int_s_axi_arregion; -wire [S_COUNT*ARUSER_WIDTH-1:0] int_s_axi_aruser; -wire [S_COUNT-1:0] int_s_axi_arvalid; -wire [S_COUNT-1:0] int_s_axi_arready; - -wire [S_COUNT*M_COUNT-1:0] int_axi_arvalid; -wire [M_COUNT*S_COUNT-1:0] int_axi_arready; - -wire [M_COUNT*M_ID_WIDTH-1:0] int_m_axi_rid; -wire [M_COUNT*DATA_WIDTH-1:0] int_m_axi_rdata; -wire [M_COUNT*2-1:0] int_m_axi_rresp; -wire [M_COUNT-1:0] int_m_axi_rlast; -wire [M_COUNT*RUSER_WIDTH-1:0] int_m_axi_ruser; -wire [M_COUNT-1:0] int_m_axi_rvalid; -wire [M_COUNT-1:0] int_m_axi_rready; - -wire [M_COUNT*S_COUNT-1:0] int_axi_rvalid; -wire [S_COUNT*M_COUNT-1:0] int_axi_rready; - -generate - - genvar m, n; - - for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces - // address decode and admission control - wire [CL_M_COUNT-1:0] a_select; - - wire m_axi_avalid; - wire m_axi_aready; - - wire m_rc_decerr; - wire m_rc_valid; - wire m_rc_ready; - - wire [S_ID_WIDTH-1:0] s_cpl_id; - wire s_cpl_valid; - - axi_crossbar_addr #( - .S(m), - .S_COUNT(S_COUNT), - .M_COUNT(M_COUNT), - .ADDR_WIDTH(ADDR_WIDTH), - .ID_WIDTH(S_ID_WIDTH), - .S_THREADS(S_THREADS[m*32 +: 32]), - .S_ACCEPT(S_ACCEPT[m*32 +: 32]), - .M_REGIONS(M_REGIONS), - .M_BASE_ADDR(M_BASE_ADDR), - .M_ADDR_WIDTH(M_ADDR_WIDTH), - .M_CONNECT(M_CONNECT), - .M_SECURE(M_SECURE), - .WC_OUTPUT(0) - ) - addr_inst ( - .clk(clk), - .rst(rst), - - /* - * Address input - */ - .s_axi_aid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_aaddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .s_axi_aprot(int_s_axi_arprot[m*3 +: 3]), - .s_axi_aqos(int_s_axi_arqos[m*4 +: 4]), - .s_axi_avalid(int_s_axi_arvalid[m]), - .s_axi_aready(int_s_axi_arready[m]), - - /* - * Address output - */ - .m_axi_aregion(int_s_axi_arregion[m*4 +: 4]), - .m_select(a_select), - .m_axi_avalid(m_axi_avalid), - .m_axi_aready(m_axi_aready), - - /* - * Write command output - */ - .m_wc_select(), - .m_wc_decerr(), - .m_wc_valid(), - .m_wc_ready(1'b1), - - /* - * Response command output - */ - .m_rc_decerr(m_rc_decerr), - .m_rc_valid(m_rc_valid), - .m_rc_ready(m_rc_ready), - - /* - * Completion input - */ - .s_cpl_id(s_cpl_id), - .s_cpl_valid(s_cpl_valid) - ); - - assign int_axi_arvalid[m*M_COUNT +: M_COUNT] = m_axi_avalid << a_select; - assign m_axi_aready = int_axi_arready[a_select*S_COUNT+m]; - - // decode error handling - reg [S_ID_WIDTH-1:0] decerr_m_axi_rid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_rid_next; - reg decerr_m_axi_rlast_reg = 1'b0, decerr_m_axi_rlast_next; - reg decerr_m_axi_rvalid_reg = 1'b0, decerr_m_axi_rvalid_next; - wire decerr_m_axi_rready; - - reg [7:0] decerr_len_reg = 8'd0, decerr_len_next; - - assign m_rc_ready = !decerr_m_axi_rvalid_reg; - - always @* begin - decerr_len_next = decerr_len_reg; - decerr_m_axi_rid_next = decerr_m_axi_rid_reg; - decerr_m_axi_rlast_next = decerr_m_axi_rlast_reg; - decerr_m_axi_rvalid_next = decerr_m_axi_rvalid_reg; - - if (decerr_m_axi_rvalid_reg) begin - if (decerr_m_axi_rready) begin - if (decerr_len_reg > 0) begin - decerr_len_next = decerr_len_reg-1; - decerr_m_axi_rlast_next = (decerr_len_next == 0); - decerr_m_axi_rvalid_next = 1'b1; - end else begin - decerr_m_axi_rvalid_next = 1'b0; - end - end - end else if (m_rc_valid && m_rc_ready) begin - decerr_len_next = int_s_axi_arlen[m*8 +: 8]; - decerr_m_axi_rid_next = int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]; - decerr_m_axi_rlast_next = (decerr_len_next == 0); - decerr_m_axi_rvalid_next = 1'b1; - end - end - - always @(posedge clk) begin - if (rst) begin - decerr_m_axi_rvalid_reg <= 1'b0; - end else begin - decerr_m_axi_rvalid_reg <= decerr_m_axi_rvalid_next; - end - - decerr_m_axi_rid_reg <= decerr_m_axi_rid_next; - decerr_m_axi_rlast_reg <= decerr_m_axi_rlast_next; - decerr_len_reg <= decerr_len_next; - end - - // read response arbitration - wire [M_COUNT_P1-1:0] r_request; - wire [M_COUNT_P1-1:0] r_acknowledge; - wire [M_COUNT_P1-1:0] r_grant; - wire r_grant_valid; - wire [CL_M_COUNT_P1-1:0] r_grant_encoded; - - arbiter #( - .PORTS(M_COUNT_P1), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_BLOCK(1), - .ARB_BLOCK_ACK(1), - .ARB_LSB_HIGH_PRIORITY(1) - ) - r_arb_inst ( - .clk(clk), - .rst(rst), - .request(r_request), - .acknowledge(r_acknowledge), - .grant(r_grant), - .grant_valid(r_grant_valid), - .grant_encoded(r_grant_encoded) - ); - - // read response mux - wire [S_ID_WIDTH-1:0] m_axi_rid_mux = {decerr_m_axi_rid_reg, int_m_axi_rid} >> r_grant_encoded*M_ID_WIDTH; - wire [DATA_WIDTH-1:0] m_axi_rdata_mux = {{DATA_WIDTH{1'b0}}, int_m_axi_rdata} >> r_grant_encoded*DATA_WIDTH; - wire [1:0] m_axi_rresp_mux = {2'b11, int_m_axi_rresp} >> r_grant_encoded*2; - wire m_axi_rlast_mux = {decerr_m_axi_rlast_reg, int_m_axi_rlast} >> r_grant_encoded; - wire [RUSER_WIDTH-1:0] m_axi_ruser_mux = {{RUSER_WIDTH{1'b0}}, int_m_axi_ruser} >> r_grant_encoded*RUSER_WIDTH; - wire m_axi_rvalid_mux = ({decerr_m_axi_rvalid_reg, int_m_axi_rvalid} >> r_grant_encoded) & r_grant_valid; - wire m_axi_rready_mux; - - assign int_axi_rready[m*M_COUNT +: M_COUNT] = (r_grant_valid && m_axi_rready_mux) << r_grant_encoded; - assign decerr_m_axi_rready = (r_grant_valid && m_axi_rready_mux) && (r_grant_encoded == M_COUNT_P1-1); - - for (n = 0; n < M_COUNT; n = n + 1) begin - assign r_request[n] = int_axi_rvalid[n*S_COUNT+m] && !r_grant[n]; - assign r_acknowledge[n] = r_grant[n] && int_axi_rvalid[n*S_COUNT+m] && m_axi_rlast_mux && m_axi_rready_mux; - end - - assign r_request[M_COUNT_P1-1] = decerr_m_axi_rvalid_reg && !r_grant[M_COUNT_P1-1]; - assign r_acknowledge[M_COUNT_P1-1] = r_grant[M_COUNT_P1-1] && decerr_m_axi_rvalid_reg && decerr_m_axi_rlast_reg && m_axi_rready_mux; - - assign s_cpl_id = m_axi_rid_mux; - assign s_cpl_valid = m_axi_rvalid_mux && m_axi_rready_mux && m_axi_rlast_mux; - - // S side register - axi_register_rd #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .ID_WIDTH(S_ID_WIDTH), - .ARUSER_ENABLE(ARUSER_ENABLE), - .ARUSER_WIDTH(ARUSER_WIDTH), - .RUSER_ENABLE(RUSER_ENABLE), - .RUSER_WIDTH(RUSER_WIDTH), - .AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]), - .R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2]) - ) - reg_inst ( - .clk(clk), - .rst(rst), - .s_axi_arid(s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_araddr(s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .s_axi_arlen(s_axi_arlen[m*8 +: 8]), - .s_axi_arsize(s_axi_arsize[m*3 +: 3]), - .s_axi_arburst(s_axi_arburst[m*2 +: 2]), - .s_axi_arlock(s_axi_arlock[m]), - .s_axi_arcache(s_axi_arcache[m*4 +: 4]), - .s_axi_arprot(s_axi_arprot[m*3 +: 3]), - .s_axi_arqos(s_axi_arqos[m*4 +: 4]), - .s_axi_arregion(4'd0), - .s_axi_aruser(s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]), - .s_axi_arvalid(s_axi_arvalid[m]), - .s_axi_arready(s_axi_arready[m]), - .s_axi_rid(s_axi_rid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_rdata(s_axi_rdata[m*DATA_WIDTH +: DATA_WIDTH]), - .s_axi_rresp(s_axi_rresp[m*2 +: 2]), - .s_axi_rlast(s_axi_rlast[m]), - .s_axi_ruser(s_axi_ruser[m*RUSER_WIDTH +: RUSER_WIDTH]), - .s_axi_rvalid(s_axi_rvalid[m]), - .s_axi_rready(s_axi_rready[m]), - .m_axi_arid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .m_axi_araddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .m_axi_arlen(int_s_axi_arlen[m*8 +: 8]), - .m_axi_arsize(int_s_axi_arsize[m*3 +: 3]), - .m_axi_arburst(int_s_axi_arburst[m*2 +: 2]), - .m_axi_arlock(int_s_axi_arlock[m]), - .m_axi_arcache(int_s_axi_arcache[m*4 +: 4]), - .m_axi_arprot(int_s_axi_arprot[m*3 +: 3]), - .m_axi_arqos(int_s_axi_arqos[m*4 +: 4]), - .m_axi_arregion(), - .m_axi_aruser(int_s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]), - .m_axi_arvalid(int_s_axi_arvalid[m]), - .m_axi_arready(int_s_axi_arready[m]), - .m_axi_rid(m_axi_rid_mux), - .m_axi_rdata(m_axi_rdata_mux), - .m_axi_rresp(m_axi_rresp_mux), - .m_axi_rlast(m_axi_rlast_mux), - .m_axi_ruser(m_axi_ruser_mux), - .m_axi_rvalid(m_axi_rvalid_mux), - .m_axi_rready(m_axi_rready_mux) - ); - end // s_ifaces - - for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces - // in-flight transaction count - wire trans_start; - wire trans_complete; - reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0; - - wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete; - - always @(posedge clk) begin - if (rst) begin - trans_count_reg <= 0; - end else begin - if (trans_start && !trans_complete) begin - trans_count_reg <= trans_count_reg + 1; - end else if (!trans_start && trans_complete) begin - trans_count_reg <= trans_count_reg - 1; - end - end - end - - // address arbitration - wire [S_COUNT-1:0] a_request; - wire [S_COUNT-1:0] a_acknowledge; - wire [S_COUNT-1:0] a_grant; - wire a_grant_valid; - wire [CL_S_COUNT-1:0] a_grant_encoded; - - arbiter #( - .PORTS(S_COUNT), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_BLOCK(1), - .ARB_BLOCK_ACK(1), - .ARB_LSB_HIGH_PRIORITY(1) - ) - a_arb_inst ( - .clk(clk), - .rst(rst), - .request(a_request), - .acknowledge(a_acknowledge), - .grant(a_grant), - .grant_valid(a_grant_valid), - .grant_encoded(a_grant_encoded) - ); - - // address mux - wire [M_ID_WIDTH-1:0] s_axi_arid_mux = int_s_axi_arid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH); - wire [ADDR_WIDTH-1:0] s_axi_araddr_mux = int_s_axi_araddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH]; - wire [7:0] s_axi_arlen_mux = int_s_axi_arlen[a_grant_encoded*8 +: 8]; - wire [2:0] s_axi_arsize_mux = int_s_axi_arsize[a_grant_encoded*3 +: 3]; - wire [1:0] s_axi_arburst_mux = int_s_axi_arburst[a_grant_encoded*2 +: 2]; - wire s_axi_arlock_mux = int_s_axi_arlock[a_grant_encoded]; - wire [3:0] s_axi_arcache_mux = int_s_axi_arcache[a_grant_encoded*4 +: 4]; - wire [2:0] s_axi_arprot_mux = int_s_axi_arprot[a_grant_encoded*3 +: 3]; - wire [3:0] s_axi_arqos_mux = int_s_axi_arqos[a_grant_encoded*4 +: 4]; - wire [3:0] s_axi_arregion_mux = int_s_axi_arregion[a_grant_encoded*4 +: 4]; - wire [ARUSER_WIDTH-1:0] s_axi_aruser_mux = int_s_axi_aruser[a_grant_encoded*ARUSER_WIDTH +: ARUSER_WIDTH]; - wire s_axi_arvalid_mux = int_axi_arvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid; - wire s_axi_arready_mux; - - assign int_axi_arready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_arready_mux) << a_grant_encoded; - - for (m = 0; m < S_COUNT; m = m + 1) begin - assign a_request[m] = int_axi_arvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit; - assign a_acknowledge[m] = a_grant[m] && int_axi_arvalid[m*M_COUNT+n] && s_axi_arready_mux; - end - - assign trans_start = s_axi_arvalid_mux && s_axi_arready_mux && a_grant_valid; - - // read response forwarding - wire [CL_S_COUNT-1:0] r_select = m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH; - - assign int_axi_rvalid[n*S_COUNT +: S_COUNT] = int_m_axi_rvalid[n] << r_select; - assign int_m_axi_rready[n] = int_axi_rready[r_select*M_COUNT+n]; - - assign trans_complete = int_m_axi_rvalid[n] && int_m_axi_rready[n] && int_m_axi_rlast[n]; - - // M side register - axi_register_rd #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .ID_WIDTH(M_ID_WIDTH), - .ARUSER_ENABLE(ARUSER_ENABLE), - .ARUSER_WIDTH(ARUSER_WIDTH), - .RUSER_ENABLE(RUSER_ENABLE), - .RUSER_WIDTH(RUSER_WIDTH), - .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]), - .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2]) - ) - reg_inst ( - .clk(clk), - .rst(rst), - .s_axi_arid(s_axi_arid_mux), - .s_axi_araddr(s_axi_araddr_mux), - .s_axi_arlen(s_axi_arlen_mux), - .s_axi_arsize(s_axi_arsize_mux), - .s_axi_arburst(s_axi_arburst_mux), - .s_axi_arlock(s_axi_arlock_mux), - .s_axi_arcache(s_axi_arcache_mux), - .s_axi_arprot(s_axi_arprot_mux), - .s_axi_arqos(s_axi_arqos_mux), - .s_axi_arregion(s_axi_arregion_mux), - .s_axi_aruser(s_axi_aruser_mux), - .s_axi_arvalid(s_axi_arvalid_mux), - .s_axi_arready(s_axi_arready_mux), - .s_axi_rid(int_m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .s_axi_rdata(int_m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]), - .s_axi_rresp(int_m_axi_rresp[n*2 +: 2]), - .s_axi_rlast(int_m_axi_rlast[n]), - .s_axi_ruser(int_m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]), - .s_axi_rvalid(int_m_axi_rvalid[n]), - .s_axi_rready(int_m_axi_rready[n]), - .m_axi_arid(m_axi_arid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .m_axi_araddr(m_axi_araddr[n*ADDR_WIDTH +: ADDR_WIDTH]), - .m_axi_arlen(m_axi_arlen[n*8 +: 8]), - .m_axi_arsize(m_axi_arsize[n*3 +: 3]), - .m_axi_arburst(m_axi_arburst[n*2 +: 2]), - .m_axi_arlock(m_axi_arlock[n]), - .m_axi_arcache(m_axi_arcache[n*4 +: 4]), - .m_axi_arprot(m_axi_arprot[n*3 +: 3]), - .m_axi_arqos(m_axi_arqos[n*4 +: 4]), - .m_axi_arregion(m_axi_arregion[n*4 +: 4]), - .m_axi_aruser(m_axi_aruser[n*ARUSER_WIDTH +: ARUSER_WIDTH]), - .m_axi_arvalid(m_axi_arvalid[n]), - .m_axi_arready(m_axi_arready[n]), - .m_axi_rid(m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .m_axi_rdata(m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]), - .m_axi_rresp(m_axi_rresp[n*2 +: 2]), - .m_axi_rlast(m_axi_rlast[n]), - .m_axi_ruser(m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]), - .m_axi_rvalid(m_axi_rvalid[n]), - .m_axi_rready(m_axi_rready[n]) - ); - end // m_ifaces - -endgenerate - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar_wr.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar_wr.v deleted file mode 100644 index 5f556653..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_crossbar_wr.v +++ /dev/null @@ -1,678 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 crossbar (write) - */ -module axi_crossbar_wr # -( - // Number of AXI inputs (slave interfaces) - parameter S_COUNT = 4, - // Number of AXI outputs (master interfaces) - parameter M_COUNT = 4, - // Width of data bus in bits - parameter DATA_WIDTH = 32, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // Width of wstrb (width of data bus in words) - parameter STRB_WIDTH = (DATA_WIDTH/8), - // Input ID field width (from AXI masters) - parameter S_ID_WIDTH = 8, - // Output ID field width (towards AXI slaves) - // Additional bits required for response routing - parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), - // Propagate awuser signal - parameter AWUSER_ENABLE = 0, - // Width of awuser signal - parameter AWUSER_WIDTH = 1, - // Propagate wuser signal - parameter WUSER_ENABLE = 0, - // Width of wuser signal - parameter WUSER_WIDTH = 1, - // Propagate buser signal - parameter BUSER_ENABLE = 0, - // Width of buser signal - parameter BUSER_WIDTH = 1, - // Number of concurrent unique IDs for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_THREADS = {S_COUNT{32'd2}}, - // Number of concurrent operations for each slave interface - // S_COUNT concatenated fields of 32 bits - parameter S_ACCEPT = {S_COUNT{32'd16}}, - // Number of regions per master interface - parameter M_REGIONS = 1, - // Master interface base addresses - // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits - // set to zero for default addressing based on M_ADDR_WIDTH - parameter M_BASE_ADDR = 0, - // Master interface address widths - // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits - parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}}, - // Write connections between interfaces - // M_COUNT concatenated fields of S_COUNT bits - parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, - // Number of concurrent operations for each master interface - // M_COUNT concatenated fields of 32 bits - parameter M_ISSUE = {M_COUNT{32'd4}}, - // Secure master (fail operations based on awprot/arprot) - // M_COUNT bits - parameter M_SECURE = {M_COUNT{1'b0}}, - // Slave interface AW channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_AW_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface W channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_W_REG_TYPE = {S_COUNT{2'd0}}, - // Slave interface B channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter S_B_REG_TYPE = {S_COUNT{2'd1}}, - // Master interface AW channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, - // Master interface W channel register type (output) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, - // Master interface B channel register type (input) - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter M_B_REG_TYPE = {M_COUNT{2'd0}} -) -( - input wire clk, - input wire rst, - - /* - * AXI slave interfaces - */ - input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_awid, - input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr, - input wire [S_COUNT*8-1:0] s_axi_awlen, - input wire [S_COUNT*3-1:0] s_axi_awsize, - input wire [S_COUNT*2-1:0] s_axi_awburst, - input wire [S_COUNT-1:0] s_axi_awlock, - input wire [S_COUNT*4-1:0] s_axi_awcache, - input wire [S_COUNT*3-1:0] s_axi_awprot, - input wire [S_COUNT*4-1:0] s_axi_awqos, - input wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser, - input wire [S_COUNT-1:0] s_axi_awvalid, - output wire [S_COUNT-1:0] s_axi_awready, - input wire [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata, - input wire [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb, - input wire [S_COUNT-1:0] s_axi_wlast, - input wire [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser, - input wire [S_COUNT-1:0] s_axi_wvalid, - output wire [S_COUNT-1:0] s_axi_wready, - output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_bid, - output wire [S_COUNT*2-1:0] s_axi_bresp, - output wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser, - output wire [S_COUNT-1:0] s_axi_bvalid, - input wire [S_COUNT-1:0] s_axi_bready, - - /* - * AXI master interfaces - */ - output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_awid, - output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [M_COUNT*8-1:0] m_axi_awlen, - output wire [M_COUNT*3-1:0] m_axi_awsize, - output wire [M_COUNT*2-1:0] m_axi_awburst, - output wire [M_COUNT-1:0] m_axi_awlock, - output wire [M_COUNT*4-1:0] m_axi_awcache, - output wire [M_COUNT*3-1:0] m_axi_awprot, - output wire [M_COUNT*4-1:0] m_axi_awqos, - output wire [M_COUNT*4-1:0] m_axi_awregion, - output wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser, - output wire [M_COUNT-1:0] m_axi_awvalid, - input wire [M_COUNT-1:0] m_axi_awready, - output wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata, - output wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb, - output wire [M_COUNT-1:0] m_axi_wlast, - output wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser, - output wire [M_COUNT-1:0] m_axi_wvalid, - input wire [M_COUNT-1:0] m_axi_wready, - input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_bid, - input wire [M_COUNT*2-1:0] m_axi_bresp, - input wire [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser, - input wire [M_COUNT-1:0] m_axi_bvalid, - output wire [M_COUNT-1:0] m_axi_bready -); - -parameter CL_S_COUNT = $clog2(S_COUNT); -parameter CL_M_COUNT = $clog2(M_COUNT); -parameter M_COUNT_P1 = M_COUNT+1; -parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1); - -integer i; - -// check configuration -initial begin - if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin - $error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)"); - $finish; - end - - for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin - if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin - $error("Error: value out of range (instance %m)"); - $finish; - end - end -end - -wire [S_COUNT*S_ID_WIDTH-1:0] int_s_axi_awid; -wire [S_COUNT*ADDR_WIDTH-1:0] int_s_axi_awaddr; -wire [S_COUNT*8-1:0] int_s_axi_awlen; -wire [S_COUNT*3-1:0] int_s_axi_awsize; -wire [S_COUNT*2-1:0] int_s_axi_awburst; -wire [S_COUNT-1:0] int_s_axi_awlock; -wire [S_COUNT*4-1:0] int_s_axi_awcache; -wire [S_COUNT*3-1:0] int_s_axi_awprot; -wire [S_COUNT*4-1:0] int_s_axi_awqos; -wire [S_COUNT*4-1:0] int_s_axi_awregion; -wire [S_COUNT*AWUSER_WIDTH-1:0] int_s_axi_awuser; -wire [S_COUNT-1:0] int_s_axi_awvalid; -wire [S_COUNT-1:0] int_s_axi_awready; - -wire [S_COUNT*M_COUNT-1:0] int_axi_awvalid; -wire [M_COUNT*S_COUNT-1:0] int_axi_awready; - -wire [S_COUNT*DATA_WIDTH-1:0] int_s_axi_wdata; -wire [S_COUNT*STRB_WIDTH-1:0] int_s_axi_wstrb; -wire [S_COUNT-1:0] int_s_axi_wlast; -wire [S_COUNT*WUSER_WIDTH-1:0] int_s_axi_wuser; -wire [S_COUNT-1:0] int_s_axi_wvalid; -wire [S_COUNT-1:0] int_s_axi_wready; - -wire [S_COUNT*M_COUNT-1:0] int_axi_wvalid; -wire [M_COUNT*S_COUNT-1:0] int_axi_wready; - -wire [M_COUNT*M_ID_WIDTH-1:0] int_m_axi_bid; -wire [M_COUNT*2-1:0] int_m_axi_bresp; -wire [M_COUNT*BUSER_WIDTH-1:0] int_m_axi_buser; -wire [M_COUNT-1:0] int_m_axi_bvalid; -wire [M_COUNT-1:0] int_m_axi_bready; - -wire [M_COUNT*S_COUNT-1:0] int_axi_bvalid; -wire [S_COUNT*M_COUNT-1:0] int_axi_bready; - -generate - - genvar m, n; - - for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces - // address decode and admission control - wire [CL_M_COUNT-1:0] a_select; - - wire m_axi_avalid; - wire m_axi_aready; - - wire [CL_M_COUNT-1:0] m_wc_select; - wire m_wc_decerr; - wire m_wc_valid; - wire m_wc_ready; - - wire m_rc_decerr; - wire m_rc_valid; - wire m_rc_ready; - - wire [S_ID_WIDTH-1:0] s_cpl_id; - wire s_cpl_valid; - - axi_crossbar_addr #( - .S(m), - .S_COUNT(S_COUNT), - .M_COUNT(M_COUNT), - .ADDR_WIDTH(ADDR_WIDTH), - .ID_WIDTH(S_ID_WIDTH), - .S_THREADS(S_THREADS[m*32 +: 32]), - .S_ACCEPT(S_ACCEPT[m*32 +: 32]), - .M_REGIONS(M_REGIONS), - .M_BASE_ADDR(M_BASE_ADDR), - .M_ADDR_WIDTH(M_ADDR_WIDTH), - .M_CONNECT(M_CONNECT), - .M_SECURE(M_SECURE), - .WC_OUTPUT(1) - ) - addr_inst ( - .clk(clk), - .rst(rst), - - /* - * Address input - */ - .s_axi_aid(int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_aaddr(int_s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .s_axi_aprot(int_s_axi_awprot[m*3 +: 3]), - .s_axi_aqos(int_s_axi_awqos[m*4 +: 4]), - .s_axi_avalid(int_s_axi_awvalid[m]), - .s_axi_aready(int_s_axi_awready[m]), - - /* - * Address output - */ - .m_axi_aregion(int_s_axi_awregion[m*4 +: 4]), - .m_select(a_select), - .m_axi_avalid(m_axi_avalid), - .m_axi_aready(m_axi_aready), - - /* - * Write command output - */ - .m_wc_select(m_wc_select), - .m_wc_decerr(m_wc_decerr), - .m_wc_valid(m_wc_valid), - .m_wc_ready(m_wc_ready), - - /* - * Response command output - */ - .m_rc_decerr(m_rc_decerr), - .m_rc_valid(m_rc_valid), - .m_rc_ready(m_rc_ready), - - /* - * Completion input - */ - .s_cpl_id(s_cpl_id), - .s_cpl_valid(s_cpl_valid) - ); - - assign int_axi_awvalid[m*M_COUNT +: M_COUNT] = m_axi_avalid << a_select; - assign m_axi_aready = int_axi_awready[a_select*S_COUNT+m]; - - // write command handling - reg [CL_M_COUNT-1:0] w_select_reg = 0, w_select_next; - reg w_drop_reg = 1'b0, w_drop_next; - reg w_select_valid_reg = 1'b0, w_select_valid_next; - - assign m_wc_ready = !w_select_valid_reg; - - always @* begin - w_select_next = w_select_reg; - w_drop_next = w_drop_reg && !(int_s_axi_wvalid[m] && int_s_axi_wready[m] && int_s_axi_wlast[m]); - w_select_valid_next = w_select_valid_reg && !(int_s_axi_wvalid[m] && int_s_axi_wready[m] && int_s_axi_wlast[m]); - - if (m_wc_valid && !w_select_valid_reg) begin - w_select_next = m_wc_select; - w_drop_next = m_wc_decerr; - w_select_valid_next = m_wc_valid; - end - end - - always @(posedge clk) begin - if (rst) begin - w_select_valid_reg <= 1'b0; - end else begin - w_select_valid_reg <= w_select_valid_next; - end - - w_select_reg <= w_select_next; - w_drop_reg <= w_drop_next; - end - - // write data forwarding - assign int_axi_wvalid[m*M_COUNT +: M_COUNT] = (int_s_axi_wvalid[m] && w_select_valid_reg && !w_drop_reg) << w_select_reg; - assign int_s_axi_wready[m] = int_axi_wready[w_select_reg*S_COUNT+m] || w_drop_reg; - - // decode error handling - reg [S_ID_WIDTH-1:0] decerr_m_axi_bid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_bid_next; - reg decerr_m_axi_bvalid_reg = 1'b0, decerr_m_axi_bvalid_next; - wire decerr_m_axi_bready; - - assign m_rc_ready = !decerr_m_axi_bvalid_reg; - - always @* begin - decerr_m_axi_bid_next = decerr_m_axi_bid_reg; - decerr_m_axi_bvalid_next = decerr_m_axi_bvalid_reg; - - if (decerr_m_axi_bvalid_reg) begin - if (decerr_m_axi_bready) begin - decerr_m_axi_bvalid_next = 1'b0; - end - end else if (m_rc_valid && m_rc_ready) begin - decerr_m_axi_bid_next = int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]; - decerr_m_axi_bvalid_next = 1'b1; - end - end - - always @(posedge clk) begin - if (rst) begin - decerr_m_axi_bvalid_reg <= 1'b0; - end else begin - decerr_m_axi_bvalid_reg <= decerr_m_axi_bvalid_next; - end - - decerr_m_axi_bid_reg <= decerr_m_axi_bid_next; - end - - // write response arbitration - wire [M_COUNT_P1-1:0] b_request; - wire [M_COUNT_P1-1:0] b_acknowledge; - wire [M_COUNT_P1-1:0] b_grant; - wire b_grant_valid; - wire [CL_M_COUNT_P1-1:0] b_grant_encoded; - - arbiter #( - .PORTS(M_COUNT_P1), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_BLOCK(1), - .ARB_BLOCK_ACK(1), - .ARB_LSB_HIGH_PRIORITY(1) - ) - b_arb_inst ( - .clk(clk), - .rst(rst), - .request(b_request), - .acknowledge(b_acknowledge), - .grant(b_grant), - .grant_valid(b_grant_valid), - .grant_encoded(b_grant_encoded) - ); - - // write response mux - wire [S_ID_WIDTH-1:0] m_axi_bid_mux = {decerr_m_axi_bid_reg, int_m_axi_bid} >> b_grant_encoded*M_ID_WIDTH; - wire [1:0] m_axi_bresp_mux = {2'b11, int_m_axi_bresp} >> b_grant_encoded*2; - wire [BUSER_WIDTH-1:0] m_axi_buser_mux = {{BUSER_WIDTH{1'b0}}, int_m_axi_buser} >> b_grant_encoded*BUSER_WIDTH; - wire m_axi_bvalid_mux = ({decerr_m_axi_bvalid_reg, int_m_axi_bvalid} >> b_grant_encoded) & b_grant_valid; - wire m_axi_bready_mux; - - assign int_axi_bready[m*M_COUNT +: M_COUNT] = (b_grant_valid && m_axi_bready_mux) << b_grant_encoded; - assign decerr_m_axi_bready = (b_grant_valid && m_axi_bready_mux) && (b_grant_encoded == M_COUNT_P1-1); - - for (n = 0; n < M_COUNT; n = n + 1) begin - assign b_request[n] = int_axi_bvalid[n*S_COUNT+m] && !b_grant[n]; - assign b_acknowledge[n] = b_grant[n] && int_axi_bvalid[n*S_COUNT+m] && m_axi_bready_mux; - end - - assign b_request[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1]; - assign b_acknowledge[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && m_axi_bready_mux; - - assign s_cpl_id = m_axi_bid_mux; - assign s_cpl_valid = m_axi_bvalid_mux && m_axi_bready_mux; - - // S side register - axi_register_wr #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .ID_WIDTH(S_ID_WIDTH), - .AWUSER_ENABLE(AWUSER_ENABLE), - .AWUSER_WIDTH(AWUSER_WIDTH), - .WUSER_ENABLE(WUSER_ENABLE), - .WUSER_WIDTH(WUSER_WIDTH), - .BUSER_ENABLE(BUSER_ENABLE), - .BUSER_WIDTH(BUSER_WIDTH), - .AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]), - .W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]), - .B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2]) - ) - reg_inst ( - .clk(clk), - .rst(rst), - .s_axi_awid(s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_awaddr(s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .s_axi_awlen(s_axi_awlen[m*8 +: 8]), - .s_axi_awsize(s_axi_awsize[m*3 +: 3]), - .s_axi_awburst(s_axi_awburst[m*2 +: 2]), - .s_axi_awlock(s_axi_awlock[m]), - .s_axi_awcache(s_axi_awcache[m*4 +: 4]), - .s_axi_awprot(s_axi_awprot[m*3 +: 3]), - .s_axi_awqos(s_axi_awqos[m*4 +: 4]), - .s_axi_awregion(4'd0), - .s_axi_awuser(s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]), - .s_axi_awvalid(s_axi_awvalid[m]), - .s_axi_awready(s_axi_awready[m]), - .s_axi_wdata(s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]), - .s_axi_wstrb(s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]), - .s_axi_wlast(s_axi_wlast[m]), - .s_axi_wuser(s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]), - .s_axi_wvalid(s_axi_wvalid[m]), - .s_axi_wready(s_axi_wready[m]), - .s_axi_bid(s_axi_bid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .s_axi_bresp(s_axi_bresp[m*2 +: 2]), - .s_axi_buser(s_axi_buser[m*BUSER_WIDTH +: BUSER_WIDTH]), - .s_axi_bvalid(s_axi_bvalid[m]), - .s_axi_bready(s_axi_bready[m]), - .m_axi_awid(int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]), - .m_axi_awaddr(int_s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]), - .m_axi_awlen(int_s_axi_awlen[m*8 +: 8]), - .m_axi_awsize(int_s_axi_awsize[m*3 +: 3]), - .m_axi_awburst(int_s_axi_awburst[m*2 +: 2]), - .m_axi_awlock(int_s_axi_awlock[m]), - .m_axi_awcache(int_s_axi_awcache[m*4 +: 4]), - .m_axi_awprot(int_s_axi_awprot[m*3 +: 3]), - .m_axi_awqos(int_s_axi_awqos[m*4 +: 4]), - .m_axi_awregion(), - .m_axi_awuser(int_s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]), - .m_axi_awvalid(int_s_axi_awvalid[m]), - .m_axi_awready(int_s_axi_awready[m]), - .m_axi_wdata(int_s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]), - .m_axi_wstrb(int_s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]), - .m_axi_wlast(int_s_axi_wlast[m]), - .m_axi_wuser(int_s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]), - .m_axi_wvalid(int_s_axi_wvalid[m]), - .m_axi_wready(int_s_axi_wready[m]), - .m_axi_bid(m_axi_bid_mux), - .m_axi_bresp(m_axi_bresp_mux), - .m_axi_buser(m_axi_buser_mux), - .m_axi_bvalid(m_axi_bvalid_mux), - .m_axi_bready(m_axi_bready_mux) - ); - end // s_ifaces - - for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces - // in-flight transaction count - wire trans_start; - wire trans_complete; - reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0; - - wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete; - - always @(posedge clk) begin - if (rst) begin - trans_count_reg <= 0; - end else begin - if (trans_start && !trans_complete) begin - trans_count_reg <= trans_count_reg + 1; - end else if (!trans_start && trans_complete) begin - trans_count_reg <= trans_count_reg - 1; - end - end - end - - // address arbitration - reg [CL_S_COUNT-1:0] w_select_reg = 0, w_select_next; - reg w_select_valid_reg = 1'b0, w_select_valid_next; - reg w_select_new_reg = 1'b0, w_select_new_next; - - wire [S_COUNT-1:0] a_request; - wire [S_COUNT-1:0] a_acknowledge; - wire [S_COUNT-1:0] a_grant; - wire a_grant_valid; - wire [CL_S_COUNT-1:0] a_grant_encoded; - - arbiter #( - .PORTS(S_COUNT), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_BLOCK(1), - .ARB_BLOCK_ACK(1), - .ARB_LSB_HIGH_PRIORITY(1) - ) - a_arb_inst ( - .clk(clk), - .rst(rst), - .request(a_request), - .acknowledge(a_acknowledge), - .grant(a_grant), - .grant_valid(a_grant_valid), - .grant_encoded(a_grant_encoded) - ); - - // address mux - wire [M_ID_WIDTH-1:0] s_axi_awid_mux = int_s_axi_awid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH); - wire [ADDR_WIDTH-1:0] s_axi_awaddr_mux = int_s_axi_awaddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH]; - wire [7:0] s_axi_awlen_mux = int_s_axi_awlen[a_grant_encoded*8 +: 8]; - wire [2:0] s_axi_awsize_mux = int_s_axi_awsize[a_grant_encoded*3 +: 3]; - wire [1:0] s_axi_awburst_mux = int_s_axi_awburst[a_grant_encoded*2 +: 2]; - wire s_axi_awlock_mux = int_s_axi_awlock[a_grant_encoded]; - wire [3:0] s_axi_awcache_mux = int_s_axi_awcache[a_grant_encoded*4 +: 4]; - wire [2:0] s_axi_awprot_mux = int_s_axi_awprot[a_grant_encoded*3 +: 3]; - wire [3:0] s_axi_awqos_mux = int_s_axi_awqos[a_grant_encoded*4 +: 4]; - wire [3:0] s_axi_awregion_mux = int_s_axi_awregion[a_grant_encoded*4 +: 4]; - wire [AWUSER_WIDTH-1:0] s_axi_awuser_mux = int_s_axi_awuser[a_grant_encoded*AWUSER_WIDTH +: AWUSER_WIDTH]; - wire s_axi_awvalid_mux = int_axi_awvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid; - wire s_axi_awready_mux; - - assign int_axi_awready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_awready_mux) << a_grant_encoded; - - for (m = 0; m < S_COUNT; m = m + 1) begin - assign a_request[m] = int_axi_awvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit && !w_select_valid_next; - assign a_acknowledge[m] = a_grant[m] && int_axi_awvalid[m*M_COUNT+n] && s_axi_awready_mux; - end - - assign trans_start = s_axi_awvalid_mux && s_axi_awready_mux && a_grant_valid; - - // write data mux - wire [DATA_WIDTH-1:0] s_axi_wdata_mux = int_s_axi_wdata[w_select_reg*DATA_WIDTH +: DATA_WIDTH]; - wire [STRB_WIDTH-1:0] s_axi_wstrb_mux = int_s_axi_wstrb[w_select_reg*STRB_WIDTH +: STRB_WIDTH]; - wire s_axi_wlast_mux = int_s_axi_wlast[w_select_reg]; - wire [WUSER_WIDTH-1:0] s_axi_wuser_mux = int_s_axi_wuser[w_select_reg*WUSER_WIDTH +: WUSER_WIDTH]; - wire s_axi_wvalid_mux = int_axi_wvalid[w_select_reg*M_COUNT+n] && w_select_valid_reg; - wire s_axi_wready_mux; - - assign int_axi_wready[n*S_COUNT +: S_COUNT] = (w_select_valid_reg && s_axi_wready_mux) << w_select_reg; - - // write data routing - always @* begin - w_select_next = w_select_reg; - w_select_valid_next = w_select_valid_reg && !(s_axi_wvalid_mux && s_axi_wready_mux && s_axi_wlast_mux); - w_select_new_next = w_select_new_reg || !a_grant_valid || a_acknowledge; - - if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin - w_select_next = a_grant_encoded; - w_select_valid_next = a_grant_valid; - w_select_new_next = 1'b0; - end - end - - always @(posedge clk) begin - if (rst) begin - w_select_valid_reg <= 1'b0; - w_select_new_reg <= 1'b1; - end else begin - w_select_valid_reg <= w_select_valid_next; - w_select_new_reg <= w_select_new_next; - end - - w_select_reg <= w_select_next; - end - - // write response forwarding - wire [CL_S_COUNT-1:0] b_select = m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH; - - assign int_axi_bvalid[n*S_COUNT +: S_COUNT] = int_m_axi_bvalid[n] << b_select; - assign int_m_axi_bready[n] = int_axi_bready[b_select*M_COUNT+n]; - - assign trans_complete = int_m_axi_bvalid[n] && int_m_axi_bready[n]; - - // M side register - axi_register_wr #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .STRB_WIDTH(STRB_WIDTH), - .ID_WIDTH(M_ID_WIDTH), - .AWUSER_ENABLE(AWUSER_ENABLE), - .AWUSER_WIDTH(AWUSER_WIDTH), - .WUSER_ENABLE(WUSER_ENABLE), - .WUSER_WIDTH(WUSER_WIDTH), - .BUSER_ENABLE(BUSER_ENABLE), - .BUSER_WIDTH(BUSER_WIDTH), - .AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]), - .W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]), - .B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2]) - ) - reg_inst ( - .clk(clk), - .rst(rst), - .s_axi_awid(s_axi_awid_mux), - .s_axi_awaddr(s_axi_awaddr_mux), - .s_axi_awlen(s_axi_awlen_mux), - .s_axi_awsize(s_axi_awsize_mux), - .s_axi_awburst(s_axi_awburst_mux), - .s_axi_awlock(s_axi_awlock_mux), - .s_axi_awcache(s_axi_awcache_mux), - .s_axi_awprot(s_axi_awprot_mux), - .s_axi_awqos(s_axi_awqos_mux), - .s_axi_awregion(s_axi_awregion_mux), - .s_axi_awuser(s_axi_awuser_mux), - .s_axi_awvalid(s_axi_awvalid_mux), - .s_axi_awready(s_axi_awready_mux), - .s_axi_wdata(s_axi_wdata_mux), - .s_axi_wstrb(s_axi_wstrb_mux), - .s_axi_wlast(s_axi_wlast_mux), - .s_axi_wuser(s_axi_wuser_mux), - .s_axi_wvalid(s_axi_wvalid_mux), - .s_axi_wready(s_axi_wready_mux), - .s_axi_bid(int_m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .s_axi_bresp(int_m_axi_bresp[n*2 +: 2]), - .s_axi_buser(int_m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]), - .s_axi_bvalid(int_m_axi_bvalid[n]), - .s_axi_bready(int_m_axi_bready[n]), - .m_axi_awid(m_axi_awid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .m_axi_awaddr(m_axi_awaddr[n*ADDR_WIDTH +: ADDR_WIDTH]), - .m_axi_awlen(m_axi_awlen[n*8 +: 8]), - .m_axi_awsize(m_axi_awsize[n*3 +: 3]), - .m_axi_awburst(m_axi_awburst[n*2 +: 2]), - .m_axi_awlock(m_axi_awlock[n]), - .m_axi_awcache(m_axi_awcache[n*4 +: 4]), - .m_axi_awprot(m_axi_awprot[n*3 +: 3]), - .m_axi_awqos(m_axi_awqos[n*4 +: 4]), - .m_axi_awregion(m_axi_awregion[n*4 +: 4]), - .m_axi_awuser(m_axi_awuser[n*AWUSER_WIDTH +: AWUSER_WIDTH]), - .m_axi_awvalid(m_axi_awvalid[n]), - .m_axi_awready(m_axi_awready[n]), - .m_axi_wdata(m_axi_wdata[n*DATA_WIDTH +: DATA_WIDTH]), - .m_axi_wstrb(m_axi_wstrb[n*STRB_WIDTH +: STRB_WIDTH]), - .m_axi_wlast(m_axi_wlast[n]), - .m_axi_wuser(m_axi_wuser[n*WUSER_WIDTH +: WUSER_WIDTH]), - .m_axi_wvalid(m_axi_wvalid[n]), - .m_axi_wready(m_axi_wready[n]), - .m_axi_bid(m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]), - .m_axi_bresp(m_axi_bresp[n*2 +: 2]), - .m_axi_buser(m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]), - .m_axi_bvalid(m_axi_bvalid[n]), - .m_axi_bready(m_axi_bready[n]) - ); - end // m_ifaces - -endgenerate - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_pipeline.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_pipeline.v deleted file mode 100644 index 7f3d08fe..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_pipeline.v +++ /dev/null @@ -1,214 +0,0 @@ -module axi_pipeline #( - parameter - C_M_AXI_ID_WIDTH = 8, - C_M_AXI_ADDR_WIDTH = 32, - C_M_AXI_DATA_WIDTH = 512, - C_M_AXI_WSTRB_WIDTH = (512 / 8), - - PIPELINE_LEVEL = 3, - EnableReadChannel = 1, - EnableWriteChannel = 1 -) -( - input ap_clk, - - // pipeline in - input in_AWVALID, - output in_AWREADY, - input [C_M_AXI_ADDR_WIDTH - 1:0] in_AWADDR, - input [1:0] in_AWBURST, - input [7:0] in_AWLEN, - input [2:0] in_AWSIZE, - input [C_M_AXI_ID_WIDTH - 1:0] in_AWID, - - input in_WVALID, - output in_WREADY, - input [C_M_AXI_DATA_WIDTH - 1:0] in_WDATA, - input [C_M_AXI_WSTRB_WIDTH - 1:0] in_WSTRB, - input in_WLAST, - - output in_BVALID, - input in_BREADY, - output [1:0] in_BRESP, - output [C_M_AXI_ID_WIDTH - 1:0] in_BID, - - input in_ARVALID, - output in_ARREADY, - input [C_M_AXI_ADDR_WIDTH - 1:0] in_ARADDR, - input [1:0] in_ARBURST, - input [7:0] in_ARLEN, - input [2:0] in_ARSIZE, - input [C_M_AXI_ID_WIDTH - 1:0] in_ARID, - - output in_RVALID, - input in_RREADY, - output [C_M_AXI_DATA_WIDTH - 1:0] in_RDATA, - output in_RLAST, - output [C_M_AXI_ID_WIDTH - 1:0] in_RID, - output [1:0] in_RRESP, - - // pipeline out - output out_AWVALID, - input out_AWREADY, - output [C_M_AXI_ADDR_WIDTH - 1:0] out_AWADDR, - output [1:0] out_AWBURST, - output [7:0] out_AWLEN, - output [2:0] out_AWSIZE, - output [C_M_AXI_ID_WIDTH - 1:0] out_AWID, - - output out_WVALID, - input out_WREADY, - output [C_M_AXI_DATA_WIDTH - 1:0] out_WDATA, - output [C_M_AXI_WSTRB_WIDTH - 1:0] out_WSTRB, - output out_WLAST, - - input out_BVALID, - output out_BREADY, - input [1:0] out_BRESP, - input [C_M_AXI_ID_WIDTH - 1:0] out_BID, - - output out_ARVALID, - input out_ARREADY, - output [C_M_AXI_ADDR_WIDTH - 1:0] out_ARADDR, - output [1:0] out_ARBURST, - output [7:0] out_ARLEN, - output [2:0] out_ARSIZE, - output [C_M_AXI_ID_WIDTH - 1:0] out_ARID, - - input out_RVALID, - output out_RREADY, - input [C_M_AXI_DATA_WIDTH - 1:0] out_RDATA, - input out_RLAST, - input [C_M_AXI_ID_WIDTH - 1:0] out_RID, - input [1:0] out_RRESP -); - - relay_station - #( - .DATA_WIDTH ( C_M_AXI_ADDR_WIDTH + C_M_AXI_ID_WIDTH + 8 + 3 + 2 ), - .DEPTH ( 2 ), - .ADDR_WIDTH ( 1 ), - .LEVEL ( PIPELINE_LEVEL ), - .CONNECT ( EnableWriteChannel ) - ) - AW_pipeline - ( - .clk ( ap_clk ), - .reset ( 1'b0 ), - .if_read_ce ( 1'b1 ), - .if_write_ce ( 1'b1 ), - - .if_din ( {in_AWADDR, in_AWID, in_AWLEN, in_AWSIZE, in_AWBURST} ), - .if_full_n ( in_AWREADY ), - .if_write ( in_AWVALID ), - - .if_dout ( {out_AWADDR, out_AWID, out_AWLEN, out_AWSIZE, out_AWBURST} ), - .if_empty_n ( out_AWVALID ), - .if_read ( out_AWREADY ) - ); - - relay_station - #( - .DATA_WIDTH( - C_M_AXI_DATA_WIDTH + C_M_AXI_WSTRB_WIDTH + 1 - ), - .DEPTH(2), - .ADDR_WIDTH(1), - .LEVEL( PIPELINE_LEVEL ), - .CONNECT ( EnableWriteChannel ) - ) - W_pipeline - ( - .clk (ap_clk), - .reset ( 1'b0 ), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({in_WDATA, in_WSTRB, in_WLAST}), - .if_full_n ( in_WREADY), - .if_write ( in_WVALID), - - .if_dout ({out_WDATA, out_WSTRB, out_WLAST}), - .if_empty_n (out_WVALID), - .if_read (out_WREADY) - ); - - relay_station - #( - .DATA_WIDTH( - C_M_AXI_ADDR_WIDTH + C_M_AXI_ID_WIDTH + 8 + 3 + 2 - ), - .DEPTH(2), - .ADDR_WIDTH(1), - .LEVEL( PIPELINE_LEVEL ), - .CONNECT( EnableReadChannel ) - ) - AR_pipeline - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({ in_ARADDR, in_ARID, in_ARLEN, in_ARSIZE, in_ARBURST}), - .if_full_n ( in_ARREADY), - .if_write ( in_ARVALID), - - .if_dout ({out_ARADDR, out_ARID, out_ARLEN, out_ARSIZE, out_ARBURST}), - .if_empty_n (out_ARVALID), - .if_read (out_ARREADY) - ); - - relay_station - #( - .DATA_WIDTH( - C_M_AXI_DATA_WIDTH + 1 + C_M_AXI_ID_WIDTH + 2 - ), - .DEPTH(2), - .ADDR_WIDTH(1), - .LEVEL( PIPELINE_LEVEL ), - .CONNECT( EnableReadChannel ) - ) - R_pipeline - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({out_RDATA, out_RLAST, out_RID, out_RRESP}), - .if_full_n ( out_RREADY), - .if_write ( out_RVALID), - - .if_dout ({in_RDATA, in_RLAST, in_RID, in_RRESP}), - .if_empty_n (in_RVALID), - .if_read (in_RREADY) - ); - - relay_station - #( - .DATA_WIDTH( - 2 + C_M_AXI_ID_WIDTH - ), - .DEPTH(2), - .ADDR_WIDTH(1), - .LEVEL( PIPELINE_LEVEL ), - .CONNECT( EnableWriteChannel ) - ) - B_pipeline - ( - .clk (ap_clk), - .reset (1'b0), - .if_read_ce (1'b1), - .if_write_ce(1'b1), - - .if_din ({out_BRESP, out_BID}), - .if_full_n (out_BREADY), - .if_write (out_BVALID), - - .if_dout ({ in_BRESP, in_BID}), - .if_empty_n (in_BVALID), - .if_read (in_BREADY) - ); - -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_register_rd.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_register_rd.v deleted file mode 100644 index c0df03a0..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_register_rd.v +++ /dev/null @@ -1,530 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 register (read) - */ -module axi_register_rd # -( - // Width of data bus in bits - parameter DATA_WIDTH = 32, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // Width of wstrb (width of data bus in words) - parameter STRB_WIDTH = (DATA_WIDTH/8), - // Width of ID signal - parameter ID_WIDTH = 8, - // Propagate aruser signal - parameter ARUSER_ENABLE = 0, - // Width of aruser signal - parameter ARUSER_WIDTH = 1, - // Propagate ruser signal - parameter RUSER_ENABLE = 0, - // Width of ruser signal - parameter RUSER_WIDTH = 1, - // AR channel register type - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter AR_REG_TYPE = 1, - // R channel register type - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter R_REG_TYPE = 2 -) -( - input wire clk, - input wire rst, - - /* - * AXI slave interface - */ - input wire [ID_WIDTH-1:0] s_axi_arid, - input wire [ADDR_WIDTH-1:0] s_axi_araddr, - input wire [7:0] s_axi_arlen, - input wire [2:0] s_axi_arsize, - input wire [1:0] s_axi_arburst, - input wire s_axi_arlock, - input wire [3:0] s_axi_arcache, - input wire [2:0] s_axi_arprot, - input wire [3:0] s_axi_arqos, - input wire [3:0] s_axi_arregion, - input wire [ARUSER_WIDTH-1:0] s_axi_aruser, - input wire s_axi_arvalid, - output wire s_axi_arready, - output wire [ID_WIDTH-1:0] s_axi_rid, - output wire [DATA_WIDTH-1:0] s_axi_rdata, - output wire [1:0] s_axi_rresp, - output wire s_axi_rlast, - output wire [RUSER_WIDTH-1:0] s_axi_ruser, - output wire s_axi_rvalid, - input wire s_axi_rready, - - /* - * AXI master interface - */ - output wire [ID_WIDTH-1:0] m_axi_arid, - output wire [ADDR_WIDTH-1:0] m_axi_araddr, - output wire [7:0] m_axi_arlen, - output wire [2:0] m_axi_arsize, - output wire [1:0] m_axi_arburst, - output wire m_axi_arlock, - output wire [3:0] m_axi_arcache, - output wire [2:0] m_axi_arprot, - output wire [3:0] m_axi_arqos, - output wire [3:0] m_axi_arregion, - output wire [ARUSER_WIDTH-1:0] m_axi_aruser, - output wire m_axi_arvalid, - input wire m_axi_arready, - input wire [ID_WIDTH-1:0] m_axi_rid, - input wire [DATA_WIDTH-1:0] m_axi_rdata, - input wire [1:0] m_axi_rresp, - input wire m_axi_rlast, - input wire [RUSER_WIDTH-1:0] m_axi_ruser, - input wire m_axi_rvalid, - output wire m_axi_rready -); - -generate - -// AR channel - -if (AR_REG_TYPE > 1) begin -// skid buffer, no bubble cycles - -// datapath registers -reg s_axi_arready_reg = 1'b0; - -reg [ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] m_axi_arlen_reg = 8'd0; -reg [2:0] m_axi_arsize_reg = 3'd0; -reg [1:0] m_axi_arburst_reg = 2'd0; -reg m_axi_arlock_reg = 1'b0; -reg [3:0] m_axi_arcache_reg = 4'd0; -reg [2:0] m_axi_arprot_reg = 3'd0; -reg [3:0] m_axi_arqos_reg = 4'd0; -reg [3:0] m_axi_arregion_reg = 4'd0; -reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}}; -reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next; - -reg [ID_WIDTH-1:0] temp_m_axi_arid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] temp_m_axi_araddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] temp_m_axi_arlen_reg = 8'd0; -reg [2:0] temp_m_axi_arsize_reg = 3'd0; -reg [1:0] temp_m_axi_arburst_reg = 2'd0; -reg temp_m_axi_arlock_reg = 1'b0; -reg [3:0] temp_m_axi_arcache_reg = 4'd0; -reg [2:0] temp_m_axi_arprot_reg = 3'd0; -reg [3:0] temp_m_axi_arqos_reg = 4'd0; -reg [3:0] temp_m_axi_arregion_reg = 4'd0; -reg [ARUSER_WIDTH-1:0] temp_m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}}; -reg temp_m_axi_arvalid_reg = 1'b0, temp_m_axi_arvalid_next; - -// datapath control -reg store_axi_ar_input_to_output; -reg store_axi_ar_input_to_temp; -reg store_axi_ar_temp_to_output; - -assign s_axi_arready = s_axi_arready_reg; - -assign m_axi_arid = m_axi_arid_reg; -assign m_axi_araddr = m_axi_araddr_reg; -assign m_axi_arlen = m_axi_arlen_reg; -assign m_axi_arsize = m_axi_arsize_reg; -assign m_axi_arburst = m_axi_arburst_reg; -assign m_axi_arlock = m_axi_arlock_reg; -assign m_axi_arcache = m_axi_arcache_reg; -assign m_axi_arprot = m_axi_arprot_reg; -assign m_axi_arqos = m_axi_arqos_reg; -assign m_axi_arregion = m_axi_arregion_reg; -assign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}}; -assign m_axi_arvalid = m_axi_arvalid_reg; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -wire s_axi_arready_early = m_axi_arready | (~temp_m_axi_arvalid_reg & (~m_axi_arvalid_reg | ~s_axi_arvalid)); - -always @* begin - // transfer sink ready state to source - m_axi_arvalid_next = m_axi_arvalid_reg; - temp_m_axi_arvalid_next = temp_m_axi_arvalid_reg; - - store_axi_ar_input_to_output = 1'b0; - store_axi_ar_input_to_temp = 1'b0; - store_axi_ar_temp_to_output = 1'b0; - - if (s_axi_arready_reg) begin - // input is ready - if (m_axi_arready | ~m_axi_arvalid_reg) begin - // output is ready or currently not valid, transfer data to output - m_axi_arvalid_next = s_axi_arvalid; - store_axi_ar_input_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_m_axi_arvalid_next = s_axi_arvalid; - store_axi_ar_input_to_temp = 1'b1; - end - end else if (m_axi_arready) begin - // input is not ready, but output is ready - m_axi_arvalid_next = temp_m_axi_arvalid_reg; - temp_m_axi_arvalid_next = 1'b0; - store_axi_ar_temp_to_output = 1'b1; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_arready_reg <= 1'b0; - m_axi_arvalid_reg <= 1'b0; - temp_m_axi_arvalid_reg <= 1'b0; - end else begin - s_axi_arready_reg <= s_axi_arready_early; - m_axi_arvalid_reg <= m_axi_arvalid_next; - temp_m_axi_arvalid_reg <= temp_m_axi_arvalid_next; - end - - // datapath - if (store_axi_ar_input_to_output) begin - m_axi_arid_reg <= s_axi_arid; - m_axi_araddr_reg <= s_axi_araddr; - m_axi_arlen_reg <= s_axi_arlen; - m_axi_arsize_reg <= s_axi_arsize; - m_axi_arburst_reg <= s_axi_arburst; - m_axi_arlock_reg <= s_axi_arlock; - m_axi_arcache_reg <= s_axi_arcache; - m_axi_arprot_reg <= s_axi_arprot; - m_axi_arqos_reg <= s_axi_arqos; - m_axi_arregion_reg <= s_axi_arregion; - m_axi_aruser_reg <= s_axi_aruser; - end else if (store_axi_ar_temp_to_output) begin - m_axi_arid_reg <= temp_m_axi_arid_reg; - m_axi_araddr_reg <= temp_m_axi_araddr_reg; - m_axi_arlen_reg <= temp_m_axi_arlen_reg; - m_axi_arsize_reg <= temp_m_axi_arsize_reg; - m_axi_arburst_reg <= temp_m_axi_arburst_reg; - m_axi_arlock_reg <= temp_m_axi_arlock_reg; - m_axi_arcache_reg <= temp_m_axi_arcache_reg; - m_axi_arprot_reg <= temp_m_axi_arprot_reg; - m_axi_arqos_reg <= temp_m_axi_arqos_reg; - m_axi_arregion_reg <= temp_m_axi_arregion_reg; - m_axi_aruser_reg <= temp_m_axi_aruser_reg; - end - - if (store_axi_ar_input_to_temp) begin - temp_m_axi_arid_reg <= s_axi_arid; - temp_m_axi_araddr_reg <= s_axi_araddr; - temp_m_axi_arlen_reg <= s_axi_arlen; - temp_m_axi_arsize_reg <= s_axi_arsize; - temp_m_axi_arburst_reg <= s_axi_arburst; - temp_m_axi_arlock_reg <= s_axi_arlock; - temp_m_axi_arcache_reg <= s_axi_arcache; - temp_m_axi_arprot_reg <= s_axi_arprot; - temp_m_axi_arqos_reg <= s_axi_arqos; - temp_m_axi_arregion_reg <= s_axi_arregion; - temp_m_axi_aruser_reg <= s_axi_aruser; - end -end - -end else if (AR_REG_TYPE == 1) begin -// simple register, inserts bubble cycles - -// datapath registers -reg s_axi_arready_reg = 1'b0; - -reg [ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] m_axi_arlen_reg = 8'd0; -reg [2:0] m_axi_arsize_reg = 3'd0; -reg [1:0] m_axi_arburst_reg = 2'd0; -reg m_axi_arlock_reg = 1'b0; -reg [3:0] m_axi_arcache_reg = 4'd0; -reg [2:0] m_axi_arprot_reg = 3'd0; -reg [3:0] m_axi_arqos_reg = 4'd0; -reg [3:0] m_axi_arregion_reg = 4'd0; -reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}}; -reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next; - -// datapath control -reg store_axi_ar_input_to_output; - -assign s_axi_arready = s_axi_arready_reg; - -assign m_axi_arid = m_axi_arid_reg; -assign m_axi_araddr = m_axi_araddr_reg; -assign m_axi_arlen = m_axi_arlen_reg; -assign m_axi_arsize = m_axi_arsize_reg; -assign m_axi_arburst = m_axi_arburst_reg; -assign m_axi_arlock = m_axi_arlock_reg; -assign m_axi_arcache = m_axi_arcache_reg; -assign m_axi_arprot = m_axi_arprot_reg; -assign m_axi_arqos = m_axi_arqos_reg; -assign m_axi_arregion = m_axi_arregion_reg; -assign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}}; -assign m_axi_arvalid = m_axi_arvalid_reg; - -// enable ready input next cycle if output buffer will be empty -wire s_axi_arready_early = !m_axi_arvalid_next; - -always @* begin - // transfer sink ready state to source - m_axi_arvalid_next = m_axi_arvalid_reg; - - store_axi_ar_input_to_output = 1'b0; - - if (s_axi_arready_reg) begin - m_axi_arvalid_next = s_axi_arvalid; - store_axi_ar_input_to_output = 1'b1; - end else if (m_axi_arready) begin - m_axi_arvalid_next = 1'b0; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_arready_reg <= 1'b0; - m_axi_arvalid_reg <= 1'b0; - end else begin - s_axi_arready_reg <= s_axi_arready_early; - m_axi_arvalid_reg <= m_axi_arvalid_next; - end - - // datapath - if (store_axi_ar_input_to_output) begin - m_axi_arid_reg <= s_axi_arid; - m_axi_araddr_reg <= s_axi_araddr; - m_axi_arlen_reg <= s_axi_arlen; - m_axi_arsize_reg <= s_axi_arsize; - m_axi_arburst_reg <= s_axi_arburst; - m_axi_arlock_reg <= s_axi_arlock; - m_axi_arcache_reg <= s_axi_arcache; - m_axi_arprot_reg <= s_axi_arprot; - m_axi_arqos_reg <= s_axi_arqos; - m_axi_arregion_reg <= s_axi_arregion; - m_axi_aruser_reg <= s_axi_aruser; - end -end - -end else begin - - // bypass AR channel - assign m_axi_arid = s_axi_arid; - assign m_axi_araddr = s_axi_araddr; - assign m_axi_arlen = s_axi_arlen; - assign m_axi_arsize = s_axi_arsize; - assign m_axi_arburst = s_axi_arburst; - assign m_axi_arlock = s_axi_arlock; - assign m_axi_arcache = s_axi_arcache; - assign m_axi_arprot = s_axi_arprot; - assign m_axi_arqos = s_axi_arqos; - assign m_axi_arregion = s_axi_arregion; - assign m_axi_aruser = ARUSER_ENABLE ? s_axi_aruser : {ARUSER_WIDTH{1'b0}}; - assign m_axi_arvalid = s_axi_arvalid; - assign s_axi_arready = m_axi_arready; - -end - -// R channel - -if (R_REG_TYPE > 1) begin -// skid buffer, no bubble cycles - -// datapath registers -reg m_axi_rready_reg = 1'b0; - -reg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}}; -reg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}}; -reg [1:0] s_axi_rresp_reg = 2'b0; -reg s_axi_rlast_reg = 1'b0; -reg [RUSER_WIDTH-1:0] s_axi_ruser_reg = {RUSER_WIDTH{1'b0}}; -reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next; - -reg [ID_WIDTH-1:0] temp_s_axi_rid_reg = {ID_WIDTH{1'b0}}; -reg [DATA_WIDTH-1:0] temp_s_axi_rdata_reg = {DATA_WIDTH{1'b0}}; -reg [1:0] temp_s_axi_rresp_reg = 2'b0; -reg temp_s_axi_rlast_reg = 1'b0; -reg [RUSER_WIDTH-1:0] temp_s_axi_ruser_reg = {RUSER_WIDTH{1'b0}}; -reg temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next; - -// datapath control -reg store_axi_r_input_to_output; -reg store_axi_r_input_to_temp; -reg store_axi_r_temp_to_output; - -assign m_axi_rready = m_axi_rready_reg; - -assign s_axi_rid = s_axi_rid_reg; -assign s_axi_rdata = s_axi_rdata_reg; -assign s_axi_rresp = s_axi_rresp_reg; -assign s_axi_rlast = s_axi_rlast_reg; -assign s_axi_ruser = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}}; -assign s_axi_rvalid = s_axi_rvalid_reg; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -wire m_axi_rready_early = s_axi_rready | (~temp_s_axi_rvalid_reg & (~s_axi_rvalid_reg | ~m_axi_rvalid)); - -always @* begin - // transfer sink ready state to source - s_axi_rvalid_next = s_axi_rvalid_reg; - temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg; - - store_axi_r_input_to_output = 1'b0; - store_axi_r_input_to_temp = 1'b0; - store_axi_r_temp_to_output = 1'b0; - - if (m_axi_rready_reg) begin - // input is ready - if (s_axi_rready | ~s_axi_rvalid_reg) begin - // output is ready or currently not valid, transfer data to output - s_axi_rvalid_next = m_axi_rvalid; - store_axi_r_input_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_s_axi_rvalid_next = m_axi_rvalid; - store_axi_r_input_to_temp = 1'b1; - end - end else if (s_axi_rready) begin - // input is not ready, but output is ready - s_axi_rvalid_next = temp_s_axi_rvalid_reg; - temp_s_axi_rvalid_next = 1'b0; - store_axi_r_temp_to_output = 1'b1; - end -end - -always @(posedge clk) begin - if (rst) begin - m_axi_rready_reg <= 1'b0; - s_axi_rvalid_reg <= 1'b0; - temp_s_axi_rvalid_reg <= 1'b0; - end else begin - m_axi_rready_reg <= m_axi_rready_early; - s_axi_rvalid_reg <= s_axi_rvalid_next; - temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next; - end - - // datapath - if (store_axi_r_input_to_output) begin - s_axi_rid_reg <= m_axi_rid; - s_axi_rdata_reg <= m_axi_rdata; - s_axi_rresp_reg <= m_axi_rresp; - s_axi_rlast_reg <= m_axi_rlast; - s_axi_ruser_reg <= m_axi_ruser; - end else if (store_axi_r_temp_to_output) begin - s_axi_rid_reg <= temp_s_axi_rid_reg; - s_axi_rdata_reg <= temp_s_axi_rdata_reg; - s_axi_rresp_reg <= temp_s_axi_rresp_reg; - s_axi_rlast_reg <= temp_s_axi_rlast_reg; - s_axi_ruser_reg <= temp_s_axi_ruser_reg; - end - - if (store_axi_r_input_to_temp) begin - temp_s_axi_rid_reg <= m_axi_rid; - temp_s_axi_rdata_reg <= m_axi_rdata; - temp_s_axi_rresp_reg <= m_axi_rresp; - temp_s_axi_rlast_reg <= m_axi_rlast; - temp_s_axi_ruser_reg <= m_axi_ruser; - end -end - -end else if (R_REG_TYPE == 1) begin -// simple register, inserts bubble cycles - -// datapath registers -reg m_axi_rready_reg = 1'b0; - -reg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}}; -reg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}}; -reg [1:0] s_axi_rresp_reg = 2'b0; -reg s_axi_rlast_reg = 1'b0; -reg [RUSER_WIDTH-1:0] s_axi_ruser_reg = {RUSER_WIDTH{1'b0}}; -reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next; - -// datapath control -reg store_axi_r_input_to_output; - -assign m_axi_rready = m_axi_rready_reg; - -assign s_axi_rid = s_axi_rid_reg; -assign s_axi_rdata = s_axi_rdata_reg; -assign s_axi_rresp = s_axi_rresp_reg; -assign s_axi_rlast = s_axi_rlast_reg; -assign s_axi_ruser = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}}; -assign s_axi_rvalid = s_axi_rvalid_reg; - -// enable ready input next cycle if output buffer will be empty -wire m_axi_rready_early = !s_axi_rvalid_next; - -always @* begin - // transfer sink ready state to source - s_axi_rvalid_next = s_axi_rvalid_reg; - - store_axi_r_input_to_output = 1'b0; - - if (m_axi_rready_reg) begin - s_axi_rvalid_next = m_axi_rvalid; - store_axi_r_input_to_output = 1'b1; - end else if (s_axi_rready) begin - s_axi_rvalid_next = 1'b0; - end -end - -always @(posedge clk) begin - if (rst) begin - m_axi_rready_reg <= 1'b0; - s_axi_rvalid_reg <= 1'b0; - end else begin - m_axi_rready_reg <= m_axi_rready_early; - s_axi_rvalid_reg <= s_axi_rvalid_next; - end - - // datapath - if (store_axi_r_input_to_output) begin - s_axi_rid_reg <= m_axi_rid; - s_axi_rdata_reg <= m_axi_rdata; - s_axi_rresp_reg <= m_axi_rresp; - s_axi_rlast_reg <= m_axi_rlast; - s_axi_ruser_reg <= m_axi_ruser; - end -end - -end else begin - - // bypass R channel - assign s_axi_rid = m_axi_rid; - assign s_axi_rdata = m_axi_rdata; - assign s_axi_rresp = m_axi_rresp; - assign s_axi_rlast = m_axi_rlast; - assign s_axi_ruser = RUSER_ENABLE ? m_axi_ruser : {RUSER_WIDTH{1'b0}}; - assign s_axi_rvalid = m_axi_rvalid; - assign m_axi_rready = s_axi_rready; - -end - -endgenerate - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_register_wr.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_register_wr.v deleted file mode 100644 index 9176d6ba..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/axi_register_wr.v +++ /dev/null @@ -1,691 +0,0 @@ -/* - -Copyright (c) 2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4 register (write) - */ -module axi_register_wr # -( - // Width of data bus in bits - parameter DATA_WIDTH = 32, - // Width of address bus in bits - parameter ADDR_WIDTH = 32, - // Width of wstrb (width of data bus in words) - parameter STRB_WIDTH = (DATA_WIDTH/8), - // Width of ID signal - parameter ID_WIDTH = 8, - // Propagate awuser signal - parameter AWUSER_ENABLE = 0, - // Width of awuser signal - parameter AWUSER_WIDTH = 1, - // Propagate wuser signal - parameter WUSER_ENABLE = 0, - // Width of wuser signal - parameter WUSER_WIDTH = 1, - // Propagate buser signal - parameter BUSER_ENABLE = 0, - // Width of buser signal - parameter BUSER_WIDTH = 1, - // AW channel register type - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter AW_REG_TYPE = 1, - // W channel register type - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter W_REG_TYPE = 2, - // B channel register type - // 0 to bypass, 1 for simple buffer, 2 for skid buffer - parameter B_REG_TYPE = 1 -) -( - input wire clk, - input wire rst, - - /* - * AXI slave interface - */ - input wire [ID_WIDTH-1:0] s_axi_awid, - input wire [ADDR_WIDTH-1:0] s_axi_awaddr, - input wire [7:0] s_axi_awlen, - input wire [2:0] s_axi_awsize, - input wire [1:0] s_axi_awburst, - input wire s_axi_awlock, - input wire [3:0] s_axi_awcache, - input wire [2:0] s_axi_awprot, - input wire [3:0] s_axi_awqos, - input wire [3:0] s_axi_awregion, - input wire [AWUSER_WIDTH-1:0] s_axi_awuser, - input wire s_axi_awvalid, - output wire s_axi_awready, - input wire [DATA_WIDTH-1:0] s_axi_wdata, - input wire [STRB_WIDTH-1:0] s_axi_wstrb, - input wire s_axi_wlast, - input wire [WUSER_WIDTH-1:0] s_axi_wuser, - input wire s_axi_wvalid, - output wire s_axi_wready, - output wire [ID_WIDTH-1:0] s_axi_bid, - output wire [1:0] s_axi_bresp, - output wire [BUSER_WIDTH-1:0] s_axi_buser, - output wire s_axi_bvalid, - input wire s_axi_bready, - - /* - * AXI master interface - */ - output wire [ID_WIDTH-1:0] m_axi_awid, - output wire [ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [7:0] m_axi_awlen, - output wire [2:0] m_axi_awsize, - output wire [1:0] m_axi_awburst, - output wire m_axi_awlock, - output wire [3:0] m_axi_awcache, - output wire [2:0] m_axi_awprot, - output wire [3:0] m_axi_awqos, - output wire [3:0] m_axi_awregion, - output wire [AWUSER_WIDTH-1:0] m_axi_awuser, - output wire m_axi_awvalid, - input wire m_axi_awready, - output wire [DATA_WIDTH-1:0] m_axi_wdata, - output wire [STRB_WIDTH-1:0] m_axi_wstrb, - output wire m_axi_wlast, - output wire [WUSER_WIDTH-1:0] m_axi_wuser, - output wire m_axi_wvalid, - input wire m_axi_wready, - input wire [ID_WIDTH-1:0] m_axi_bid, - input wire [1:0] m_axi_bresp, - input wire [BUSER_WIDTH-1:0] m_axi_buser, - input wire m_axi_bvalid, - output wire m_axi_bready -); - -generate - -// AW channel - -if (AW_REG_TYPE > 1) begin -// skid buffer, no bubble cycles - -// datapath registers -reg s_axi_awready_reg = 1'b0; - -reg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] m_axi_awlen_reg = 8'd0; -reg [2:0] m_axi_awsize_reg = 3'd0; -reg [1:0] m_axi_awburst_reg = 2'd0; -reg m_axi_awlock_reg = 1'b0; -reg [3:0] m_axi_awcache_reg = 4'd0; -reg [2:0] m_axi_awprot_reg = 3'd0; -reg [3:0] m_axi_awqos_reg = 4'd0; -reg [3:0] m_axi_awregion_reg = 4'd0; -reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}}; -reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next; - -reg [ID_WIDTH-1:0] temp_m_axi_awid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] temp_m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] temp_m_axi_awlen_reg = 8'd0; -reg [2:0] temp_m_axi_awsize_reg = 3'd0; -reg [1:0] temp_m_axi_awburst_reg = 2'd0; -reg temp_m_axi_awlock_reg = 1'b0; -reg [3:0] temp_m_axi_awcache_reg = 4'd0; -reg [2:0] temp_m_axi_awprot_reg = 3'd0; -reg [3:0] temp_m_axi_awqos_reg = 4'd0; -reg [3:0] temp_m_axi_awregion_reg = 4'd0; -reg [AWUSER_WIDTH-1:0] temp_m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}}; -reg temp_m_axi_awvalid_reg = 1'b0, temp_m_axi_awvalid_next; - -// datapath control -reg store_axi_aw_input_to_output; -reg store_axi_aw_input_to_temp; -reg store_axi_aw_temp_to_output; - -assign s_axi_awready = s_axi_awready_reg; - -assign m_axi_awid = m_axi_awid_reg; -assign m_axi_awaddr = m_axi_awaddr_reg; -assign m_axi_awlen = m_axi_awlen_reg; -assign m_axi_awsize = m_axi_awsize_reg; -assign m_axi_awburst = m_axi_awburst_reg; -assign m_axi_awlock = m_axi_awlock_reg; -assign m_axi_awcache = m_axi_awcache_reg; -assign m_axi_awprot = m_axi_awprot_reg; -assign m_axi_awqos = m_axi_awqos_reg; -assign m_axi_awregion = m_axi_awregion_reg; -assign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}}; -assign m_axi_awvalid = m_axi_awvalid_reg; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -wire s_axi_awready_early = m_axi_awready | (~temp_m_axi_awvalid_reg & (~m_axi_awvalid_reg | ~s_axi_awvalid)); - -always @* begin - // transfer sink ready state to source - m_axi_awvalid_next = m_axi_awvalid_reg; - temp_m_axi_awvalid_next = temp_m_axi_awvalid_reg; - - store_axi_aw_input_to_output = 1'b0; - store_axi_aw_input_to_temp = 1'b0; - store_axi_aw_temp_to_output = 1'b0; - - if (s_axi_awready_reg) begin - // input is ready - if (m_axi_awready | ~m_axi_awvalid_reg) begin - // output is ready or currently not valid, transfer data to output - m_axi_awvalid_next = s_axi_awvalid; - store_axi_aw_input_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_m_axi_awvalid_next = s_axi_awvalid; - store_axi_aw_input_to_temp = 1'b1; - end - end else if (m_axi_awready) begin - // input is not ready, but output is ready - m_axi_awvalid_next = temp_m_axi_awvalid_reg; - temp_m_axi_awvalid_next = 1'b0; - store_axi_aw_temp_to_output = 1'b1; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_awready_reg <= 1'b0; - m_axi_awvalid_reg <= 1'b0; - temp_m_axi_awvalid_reg <= 1'b0; - end else begin - s_axi_awready_reg <= s_axi_awready_early; - m_axi_awvalid_reg <= m_axi_awvalid_next; - temp_m_axi_awvalid_reg <= temp_m_axi_awvalid_next; - end - - // datapath - if (store_axi_aw_input_to_output) begin - m_axi_awid_reg <= s_axi_awid; - m_axi_awaddr_reg <= s_axi_awaddr; - m_axi_awlen_reg <= s_axi_awlen; - m_axi_awsize_reg <= s_axi_awsize; - m_axi_awburst_reg <= s_axi_awburst; - m_axi_awlock_reg <= s_axi_awlock; - m_axi_awcache_reg <= s_axi_awcache; - m_axi_awprot_reg <= s_axi_awprot; - m_axi_awqos_reg <= s_axi_awqos; - m_axi_awregion_reg <= s_axi_awregion; - m_axi_awuser_reg <= s_axi_awuser; - end else if (store_axi_aw_temp_to_output) begin - m_axi_awid_reg <= temp_m_axi_awid_reg; - m_axi_awaddr_reg <= temp_m_axi_awaddr_reg; - m_axi_awlen_reg <= temp_m_axi_awlen_reg; - m_axi_awsize_reg <= temp_m_axi_awsize_reg; - m_axi_awburst_reg <= temp_m_axi_awburst_reg; - m_axi_awlock_reg <= temp_m_axi_awlock_reg; - m_axi_awcache_reg <= temp_m_axi_awcache_reg; - m_axi_awprot_reg <= temp_m_axi_awprot_reg; - m_axi_awqos_reg <= temp_m_axi_awqos_reg; - m_axi_awregion_reg <= temp_m_axi_awregion_reg; - m_axi_awuser_reg <= temp_m_axi_awuser_reg; - end - - if (store_axi_aw_input_to_temp) begin - temp_m_axi_awid_reg <= s_axi_awid; - temp_m_axi_awaddr_reg <= s_axi_awaddr; - temp_m_axi_awlen_reg <= s_axi_awlen; - temp_m_axi_awsize_reg <= s_axi_awsize; - temp_m_axi_awburst_reg <= s_axi_awburst; - temp_m_axi_awlock_reg <= s_axi_awlock; - temp_m_axi_awcache_reg <= s_axi_awcache; - temp_m_axi_awprot_reg <= s_axi_awprot; - temp_m_axi_awqos_reg <= s_axi_awqos; - temp_m_axi_awregion_reg <= s_axi_awregion; - temp_m_axi_awuser_reg <= s_axi_awuser; - end -end - -end else if (AW_REG_TYPE == 1) begin -// simple register, inserts bubble cycles - -// datapath registers -reg s_axi_awready_reg = 1'b0; - -reg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}}; -reg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}}; -reg [7:0] m_axi_awlen_reg = 8'd0; -reg [2:0] m_axi_awsize_reg = 3'd0; -reg [1:0] m_axi_awburst_reg = 2'd0; -reg m_axi_awlock_reg = 1'b0; -reg [3:0] m_axi_awcache_reg = 4'd0; -reg [2:0] m_axi_awprot_reg = 3'd0; -reg [3:0] m_axi_awqos_reg = 4'd0; -reg [3:0] m_axi_awregion_reg = 4'd0; -reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}}; -reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next; - -// datapath control -reg store_axi_aw_input_to_output; - -assign s_axi_awready = s_axi_awready_reg; - -assign m_axi_awid = m_axi_awid_reg; -assign m_axi_awaddr = m_axi_awaddr_reg; -assign m_axi_awlen = m_axi_awlen_reg; -assign m_axi_awsize = m_axi_awsize_reg; -assign m_axi_awburst = m_axi_awburst_reg; -assign m_axi_awlock = m_axi_awlock_reg; -assign m_axi_awcache = m_axi_awcache_reg; -assign m_axi_awprot = m_axi_awprot_reg; -assign m_axi_awqos = m_axi_awqos_reg; -assign m_axi_awregion = m_axi_awregion_reg; -assign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}}; -assign m_axi_awvalid = m_axi_awvalid_reg; - -// enable ready input next cycle if output buffer will be empty -wire s_axi_awready_eawly = !m_axi_awvalid_next; - -always @* begin - // transfer sink ready state to source - m_axi_awvalid_next = m_axi_awvalid_reg; - - store_axi_aw_input_to_output = 1'b0; - - if (s_axi_awready_reg) begin - m_axi_awvalid_next = s_axi_awvalid; - store_axi_aw_input_to_output = 1'b1; - end else if (m_axi_awready) begin - m_axi_awvalid_next = 1'b0; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_awready_reg <= 1'b0; - m_axi_awvalid_reg <= 1'b0; - end else begin - s_axi_awready_reg <= s_axi_awready_eawly; - m_axi_awvalid_reg <= m_axi_awvalid_next; - end - - // datapath - if (store_axi_aw_input_to_output) begin - m_axi_awid_reg <= s_axi_awid; - m_axi_awaddr_reg <= s_axi_awaddr; - m_axi_awlen_reg <= s_axi_awlen; - m_axi_awsize_reg <= s_axi_awsize; - m_axi_awburst_reg <= s_axi_awburst; - m_axi_awlock_reg <= s_axi_awlock; - m_axi_awcache_reg <= s_axi_awcache; - m_axi_awprot_reg <= s_axi_awprot; - m_axi_awqos_reg <= s_axi_awqos; - m_axi_awregion_reg <= s_axi_awregion; - m_axi_awuser_reg <= s_axi_awuser; - end -end - -end else begin - - // bypass AW channel - assign m_axi_awid = s_axi_awid; - assign m_axi_awaddr = s_axi_awaddr; - assign m_axi_awlen = s_axi_awlen; - assign m_axi_awsize = s_axi_awsize; - assign m_axi_awburst = s_axi_awburst; - assign m_axi_awlock = s_axi_awlock; - assign m_axi_awcache = s_axi_awcache; - assign m_axi_awprot = s_axi_awprot; - assign m_axi_awqos = s_axi_awqos; - assign m_axi_awregion = s_axi_awregion; - assign m_axi_awuser = AWUSER_ENABLE ? s_axi_awuser : {AWUSER_WIDTH{1'b0}}; - assign m_axi_awvalid = s_axi_awvalid; - assign s_axi_awready = m_axi_awready; - -end - -// W channel - -if (W_REG_TYPE > 1) begin -// skid buffer, no bubble cycles - -// datapath registers -reg s_axi_wready_reg = 1'b0; - -reg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}}; -reg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}}; -reg m_axi_wlast_reg = 1'b0; -reg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}}; -reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next; - -reg [DATA_WIDTH-1:0] temp_m_axi_wdata_reg = {DATA_WIDTH{1'b0}}; -reg [STRB_WIDTH-1:0] temp_m_axi_wstrb_reg = {STRB_WIDTH{1'b0}}; -reg temp_m_axi_wlast_reg = 1'b0; -reg [WUSER_WIDTH-1:0] temp_m_axi_wuser_reg = {WUSER_WIDTH{1'b0}}; -reg temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next; - -// datapath control -reg store_axi_w_input_to_output; -reg store_axi_w_input_to_temp; -reg store_axi_w_temp_to_output; - -assign s_axi_wready = s_axi_wready_reg; - -assign m_axi_wdata = m_axi_wdata_reg; -assign m_axi_wstrb = m_axi_wstrb_reg; -assign m_axi_wlast = m_axi_wlast_reg; -assign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}}; -assign m_axi_wvalid = m_axi_wvalid_reg; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -wire s_axi_wready_early = m_axi_wready | (~temp_m_axi_wvalid_reg & (~m_axi_wvalid_reg | ~s_axi_wvalid)); - -always @* begin - // transfer sink ready state to source - m_axi_wvalid_next = m_axi_wvalid_reg; - temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg; - - store_axi_w_input_to_output = 1'b0; - store_axi_w_input_to_temp = 1'b0; - store_axi_w_temp_to_output = 1'b0; - - if (s_axi_wready_reg) begin - // input is ready - if (m_axi_wready | ~m_axi_wvalid_reg) begin - // output is ready or currently not valid, transfer data to output - m_axi_wvalid_next = s_axi_wvalid; - store_axi_w_input_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_m_axi_wvalid_next = s_axi_wvalid; - store_axi_w_input_to_temp = 1'b1; - end - end else if (m_axi_wready) begin - // input is not ready, but output is ready - m_axi_wvalid_next = temp_m_axi_wvalid_reg; - temp_m_axi_wvalid_next = 1'b0; - store_axi_w_temp_to_output = 1'b1; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_wready_reg <= 1'b0; - m_axi_wvalid_reg <= 1'b0; - temp_m_axi_wvalid_reg <= 1'b0; - end else begin - s_axi_wready_reg <= s_axi_wready_early; - m_axi_wvalid_reg <= m_axi_wvalid_next; - temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next; - end - - // datapath - if (store_axi_w_input_to_output) begin - m_axi_wdata_reg <= s_axi_wdata; - m_axi_wstrb_reg <= s_axi_wstrb; - m_axi_wlast_reg <= s_axi_wlast; - m_axi_wuser_reg <= s_axi_wuser; - end else if (store_axi_w_temp_to_output) begin - m_axi_wdata_reg <= temp_m_axi_wdata_reg; - m_axi_wstrb_reg <= temp_m_axi_wstrb_reg; - m_axi_wlast_reg <= temp_m_axi_wlast_reg; - m_axi_wuser_reg <= temp_m_axi_wuser_reg; - end - - if (store_axi_w_input_to_temp) begin - temp_m_axi_wdata_reg <= s_axi_wdata; - temp_m_axi_wstrb_reg <= s_axi_wstrb; - temp_m_axi_wlast_reg <= s_axi_wlast; - temp_m_axi_wuser_reg <= s_axi_wuser; - end -end - -end else if (W_REG_TYPE == 1) begin -// simple register, inserts bubble cycles - -// datapath registers -reg s_axi_wready_reg = 1'b0; - -reg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}}; -reg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}}; -reg m_axi_wlast_reg = 1'b0; -reg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}}; -reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next; - -// datapath control -reg store_axi_w_input_to_output; - -assign s_axi_wready = s_axi_wready_reg; - -assign m_axi_wdata = m_axi_wdata_reg; -assign m_axi_wstrb = m_axi_wstrb_reg; -assign m_axi_wlast = m_axi_wlast_reg; -assign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}}; -assign m_axi_wvalid = m_axi_wvalid_reg; - -// enable ready input next cycle if output buffer will be empty -wire s_axi_wready_ewly = !m_axi_wvalid_next; - -always @* begin - // transfer sink ready state to source - m_axi_wvalid_next = m_axi_wvalid_reg; - - store_axi_w_input_to_output = 1'b0; - - if (s_axi_wready_reg) begin - m_axi_wvalid_next = s_axi_wvalid; - store_axi_w_input_to_output = 1'b1; - end else if (m_axi_wready) begin - m_axi_wvalid_next = 1'b0; - end -end - -always @(posedge clk) begin - if (rst) begin - s_axi_wready_reg <= 1'b0; - m_axi_wvalid_reg <= 1'b0; - end else begin - s_axi_wready_reg <= s_axi_wready_ewly; - m_axi_wvalid_reg <= m_axi_wvalid_next; - end - - // datapath - if (store_axi_w_input_to_output) begin - m_axi_wdata_reg <= s_axi_wdata; - m_axi_wstrb_reg <= s_axi_wstrb; - m_axi_wlast_reg <= s_axi_wlast; - m_axi_wuser_reg <= s_axi_wuser; - end -end - -end else begin - - // bypass W channel - assign m_axi_wdata = s_axi_wdata; - assign m_axi_wstrb = s_axi_wstrb; - assign m_axi_wlast = s_axi_wlast; - assign m_axi_wuser = WUSER_ENABLE ? s_axi_wuser : {WUSER_WIDTH{1'b0}}; - assign m_axi_wvalid = s_axi_wvalid; - assign s_axi_wready = m_axi_wready; - -end - -// B channel - -if (B_REG_TYPE > 1) begin -// skid buffer, no bubble cycles - -// datapath registers -reg m_axi_bready_reg = 1'b0; - -reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}; -reg [1:0] s_axi_bresp_reg = 2'b0; -reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}}; -reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next; - -reg [ID_WIDTH-1:0] temp_s_axi_bid_reg = {ID_WIDTH{1'b0}}; -reg [1:0] temp_s_axi_bresp_reg = 2'b0; -reg [BUSER_WIDTH-1:0] temp_s_axi_buser_reg = {BUSER_WIDTH{1'b0}}; -reg temp_s_axi_bvalid_reg = 1'b0, temp_s_axi_bvalid_next; - -// datapath control -reg store_axi_b_input_to_output; -reg store_axi_b_input_to_temp; -reg store_axi_b_temp_to_output; - -assign m_axi_bready = m_axi_bready_reg; - -assign s_axi_bid = s_axi_bid_reg; -assign s_axi_bresp = s_axi_bresp_reg; -assign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}}; -assign s_axi_bvalid = s_axi_bvalid_reg; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -wire m_axi_bready_early = s_axi_bready | (~temp_s_axi_bvalid_reg & (~s_axi_bvalid_reg | ~m_axi_bvalid)); - -always @* begin - // transfer sink ready state to source - s_axi_bvalid_next = s_axi_bvalid_reg; - temp_s_axi_bvalid_next = temp_s_axi_bvalid_reg; - - store_axi_b_input_to_output = 1'b0; - store_axi_b_input_to_temp = 1'b0; - store_axi_b_temp_to_output = 1'b0; - - if (m_axi_bready_reg) begin - // input is ready - if (s_axi_bready | ~s_axi_bvalid_reg) begin - // output is ready or currently not valid, transfer data to output - s_axi_bvalid_next = m_axi_bvalid; - store_axi_b_input_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_s_axi_bvalid_next = m_axi_bvalid; - store_axi_b_input_to_temp = 1'b1; - end - end else if (s_axi_bready) begin - // input is not ready, but output is ready - s_axi_bvalid_next = temp_s_axi_bvalid_reg; - temp_s_axi_bvalid_next = 1'b0; - store_axi_b_temp_to_output = 1'b1; - end -end - -always @(posedge clk) begin - if (rst) begin - m_axi_bready_reg <= 1'b0; - s_axi_bvalid_reg <= 1'b0; - temp_s_axi_bvalid_reg <= 1'b0; - end else begin - m_axi_bready_reg <= m_axi_bready_early; - s_axi_bvalid_reg <= s_axi_bvalid_next; - temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next; - end - - // datapath - if (store_axi_b_input_to_output) begin - s_axi_bid_reg <= m_axi_bid; - s_axi_bresp_reg <= m_axi_bresp; - s_axi_buser_reg <= m_axi_buser; - end else if (store_axi_b_temp_to_output) begin - s_axi_bid_reg <= temp_s_axi_bid_reg; - s_axi_bresp_reg <= temp_s_axi_bresp_reg; - s_axi_buser_reg <= temp_s_axi_buser_reg; - end - - if (store_axi_b_input_to_temp) begin - temp_s_axi_bid_reg <= m_axi_bid; - temp_s_axi_bresp_reg <= m_axi_bresp; - temp_s_axi_buser_reg <= m_axi_buser; - end -end - -end else if (B_REG_TYPE == 1) begin -// simple register, inserts bubble cycles - -// datapath registers -reg m_axi_bready_reg = 1'b0; - -reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}; -reg [1:0] s_axi_bresp_reg = 2'b0; -reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}}; -reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next; - -// datapath control -reg store_axi_b_input_to_output; - -assign m_axi_bready = m_axi_bready_reg; - -assign s_axi_bid = s_axi_bid_reg; -assign s_axi_bresp = s_axi_bresp_reg; -assign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}}; -assign s_axi_bvalid = s_axi_bvalid_reg; - -// enable ready input next cycle if output buffer will be empty -wire m_axi_bready_early = !s_axi_bvalid_next; - -always @* begin - // transfer sink ready state to source - s_axi_bvalid_next = s_axi_bvalid_reg; - - store_axi_b_input_to_output = 1'b0; - - if (m_axi_bready_reg) begin - s_axi_bvalid_next = m_axi_bvalid; - store_axi_b_input_to_output = 1'b1; - end else if (s_axi_bready) begin - s_axi_bvalid_next = 1'b0; - end -end - -always @(posedge clk) begin - if (rst) begin - m_axi_bready_reg <= 1'b0; - s_axi_bvalid_reg <= 1'b0; - end else begin - m_axi_bready_reg <= m_axi_bready_early; - s_axi_bvalid_reg <= s_axi_bvalid_next; - end - - // datapath - if (store_axi_b_input_to_output) begin - s_axi_bid_reg <= m_axi_bid; - s_axi_bresp_reg <= m_axi_bresp; - s_axi_buser_reg <= m_axi_buser; - end -end - -end else begin - - // bypass B channel - assign s_axi_bid = m_axi_bid; - assign s_axi_bresp = m_axi_bresp; - assign s_axi_buser = BUSER_ENABLE ? m_axi_buser : {BUSER_WIDTH{1'b0}}; - assign s_axi_bvalid = m_axi_bvalid; - assign m_axi_bready = s_axi_bready; - -end - -endgenerate - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/detect_burst.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/detect_burst.v deleted file mode 100644 index 8abeaa66..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/detect_burst.v +++ /dev/null @@ -1,156 +0,0 @@ -`default_nettype none - -// Detect burst from address stream. -module detect_burst #( - parameter AddrWidth = 64, - parameter DataWidthBytesLog = 6, - parameter WaitTimeWidth = 4, - parameter BurstLenWidth = 8 -) ( - input wire clk, - input wire rst, - - input wire [WaitTimeWidth-1:0] max_wait_time, - input wire [BurstLenWidth-1:0] max_burst_len, // 0 disables detection - - input wire [AddrWidth-1:0] addr_dout, - input wire addr_empty_n, - output reg addr_read, - - output wire [BurstLenWidth+AddrWidth-1:0] addr_din, - input wire addr_full_n, - output wire addr_write, - - output wire [BurstLenWidth-1:0] burst_len_0_din, - input wire burst_len_0_full_n, - output wire burst_len_0_write, - - output wire [BurstLenWidth-1:0] burst_len_1_din, - input wire burst_len_1_full_n, - output wire burst_len_1_write -); - // parameter - localparam NextAddrWidth = AddrWidth - DataWidthBytesLog; - - // state - reg [AddrWidth-1:0] base_addr; - reg base_valid; - reg [BurstLenWidth-1:0] burst_len; - reg [WaitTimeWidth-1:0] wait_time; - reg [NextAddrWidth-1:0] next_addr; - - // logic - reg write_enable; - reg [AddrWidth-1:0] base_addr_next; - reg base_valid_next; - reg [BurstLenWidth-1:0] burst_len_next; - reg [WaitTimeWidth-1:0] wait_time_next; - - wire [NextAddrWidth-1:0] next_addr_next = - base_addr_next[AddrWidth-1:DataWidthBytesLog] + - {{(NextAddrWidth-BurstLenWidth){1'b0}}, burst_len_next} + - {{(NextAddrWidth-1){1'b0}}, 1'b1}; - - assign addr_write = write_enable; - assign burst_len_0_write = write_enable; - assign burst_len_1_write = write_enable; - assign addr_din = {burst_len, base_addr}; - assign burst_len_0_din = burst_len; - assign burst_len_1_din = burst_len; - - // register the input for timing closure - reg addr_empty_n_q; - reg [AddrWidth-1:0] addr_dout_q; - always @(posedge clk) begin - if (addr_full_n && burst_len_0_full_n && burst_len_1_full_n) begin - addr_empty_n_q <= addr_empty_n; - addr_dout_q <= addr_dout; - end - end - wire [AddrWidth-1:0] curr_addr = addr_dout_q; - - always @* begin - // defaults - addr_read = 1'b0; - if (!addr_full_n || !burst_len_0_full_n || !burst_len_1_full_n) begin - addr_read = 1'b0; - end else if (addr_empty_n) begin - // read new item if non-empty - addr_read = 1'b1; - end else if (base_valid) begin - addr_read = 1'b0; - end - end - - always @* begin - // defaults - write_enable = 1'b0; - base_addr_next = base_addr; - base_valid_next = base_valid; - wait_time_next = wait_time; - burst_len_next = burst_len; - if (!addr_full_n || !burst_len_0_full_n || !burst_len_1_full_n) begin - // output FIFO full, do nothing - end else if (addr_empty_n_q) begin - wait_time_next = 0; - if (!base_valid) begin - base_addr_next = curr_addr; - base_valid_next = 1'b1; - - write_enable = 1'b0; - burst_len_next = burst_len; - end else begin - if (next_addr == curr_addr[AddrWidth-1:DataWidthBytesLog] && - burst_len < max_burst_len) begin - burst_len_next = burst_len + 1; - - write_enable = 1'b0; - base_addr_next = base_addr; - base_valid_next = base_valid; - end else begin - // no more burst detected - write_enable = 1'b1; - burst_len_next = 0; - base_addr_next = curr_addr; - - base_valid_next = base_valid; - end - end - end else if (base_valid) begin - if (wait_time < max_wait_time) begin - wait_time_next = wait_time + 1; - - write_enable = 1'b0; - base_addr_next = base_addr; - base_valid_next = base_valid; - burst_len_next = burst_len; - end else begin - write_enable = 1'b1; - wait_time_next = 0; - base_valid_next = 1'b0; - burst_len_next = 0; - - base_addr_next = base_addr; - end - end - end - - always @(posedge clk) begin - if (rst) begin - base_addr <= {AddrWidth{1'b0}}; - base_valid <= 1'd0; - burst_len <= {BurstLenWidth{1'b0}}; - wait_time <= {WaitTimeWidth{1'b0}}; - next_addr <= {{(NextAddrWidth-1){1'b0}}, 1'b1}; - end else begin - base_addr <= base_addr_next; - base_valid <= base_valid_next; - burst_len <= burst_len_next; - wait_time <= wait_time_next; - next_addr <= next_addr_next; - end - end - -endmodule // detect_burst - -`default_nettype wire diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo.v deleted file mode 100644 index d2559d97..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo.v +++ /dev/null @@ -1,107 +0,0 @@ -`default_nettype none - -// first-word fall-through (FWFT) FIFO -module fifo #( - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 5, - parameter DEPTH = 32 -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - -generate - if (DEPTH == 1) begin : d1 - fifo_fwd #( - .DATA_WIDTH(DATA_WIDTH) - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end else if (DATA_WIDTH >= 36 && DEPTH >= 4096) begin : uram - fifo_bram #( - .MEM_STYLE ("ultra"), - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .DEPTH (DEPTH) - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end else if (DEPTH >=128) begin : bram - fifo_bram #( - .MEM_STYLE ("block"), - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .DEPTH (DEPTH) - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end else begin : srl - fifo_srl #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .DEPTH (DEPTH) - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end -endgenerate - -endmodule // fifo - -`default_nettype wire diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo_bram.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo_bram.v deleted file mode 100644 index 8b5aea64..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo_bram.v +++ /dev/null @@ -1,151 +0,0 @@ -`default_nettype none - -// first-word fall-through (FWFT) FIFO using block RAM -// based on HLS generated code -module fifo_bram #( - parameter MEM_STYLE = "auto", - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 5, - parameter DEPTH = 32 -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - -(* ram_style = MEM_STYLE *) -reg [DATA_WIDTH-1:0] mem[0:DEPTH-1]; -reg [DATA_WIDTH-1:0] q_buf; -reg [ADDR_WIDTH-1:0] waddr; -reg [ADDR_WIDTH-1:0] raddr; -wire [ADDR_WIDTH-1:0] wnext; -wire [ADDR_WIDTH-1:0] rnext; -wire push; -wire pop; -reg [ADDR_WIDTH-1:0] used; -reg full_n; -reg empty_n; -reg [DATA_WIDTH-1:0] q_tmp; -reg show_ahead; -reg [DATA_WIDTH-1:0] dout_buf; -reg dout_valid; - -localparam DepthM1 = DEPTH[ADDR_WIDTH-1:0] - 1'd1; - -assign if_full_n = full_n; -assign if_empty_n = dout_valid; -assign if_dout = dout_buf; -assign push = full_n & if_write_ce & if_write; -assign pop = empty_n & if_read_ce & (~dout_valid | if_read); -assign wnext = !push ? waddr : - (waddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : waddr + 1'd1; -assign rnext = !pop ? raddr : - (raddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : raddr + 1'd1; - -// waddr -always @(posedge clk) begin - if (reset) - waddr <= {ADDR_WIDTH{1'b0}}; - else - waddr <= wnext; -end - -// raddr -always @(posedge clk) begin - if (reset) - raddr <= {ADDR_WIDTH{1'b0}}; - else - raddr <= rnext; -end - -// used -always @(posedge clk) begin - if (reset) - used <= {ADDR_WIDTH{1'b0}}; - else if (push && !pop) - used <= used + 1'b1; - else if (!push && pop) - used <= used - 1'b1; -end - -// full_n -always @(posedge clk) begin - if (reset) - full_n <= 1'b1; - else if (push && !pop) - full_n <= (used != DepthM1); - else if (!push && pop) - full_n <= 1'b1; -end - -// empty_n -always @(posedge clk) begin - if (reset) - empty_n <= 1'b0; - else if (push && !pop) - empty_n <= 1'b1; - else if (!push && pop) - empty_n <= (used != {{(ADDR_WIDTH-1){1'b0}},1'b1}); -end - -// mem -always @(posedge clk) begin - if (push) - mem[waddr] <= if_din; -end - -// q_buf -always @(posedge clk) begin - q_buf <= mem[rnext]; -end - -// q_tmp -always @(posedge clk) begin - if (reset) - q_tmp <= {DATA_WIDTH{1'b0}}; - else if (push) - q_tmp <= if_din; -end - -// show_ahead -always @(posedge clk) begin - if (reset) - show_ahead <= 1'b0; - else if (push && used == {{(ADDR_WIDTH-1){1'b0}},pop}) - show_ahead <= 1'b1; - else - show_ahead <= 1'b0; -end - -// dout_buf -always @(posedge clk) begin - if (reset) - dout_buf <= {DATA_WIDTH{1'b0}}; - else if (pop) - dout_buf <= show_ahead? q_tmp : q_buf; -end - -// dout_valid -always @(posedge clk) begin - if (reset) - dout_valid <= 1'b0; - else if (pop) - dout_valid <= 1'b1; - else if (if_read_ce & if_read) - dout_valid <= 1'b0; -end - -endmodule // fifo_bram - -`default_nettype wire diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo_fwd.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo_fwd.v deleted file mode 100644 index 870695ea..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo_fwd.v +++ /dev/null @@ -1,58 +0,0 @@ -`default_nettype none - -// first-word fall-through (FWFT) FIFO with latency=0 and depth=1 -module fifo_fwd #( - parameter MEM_STYLE = "", // ignored - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 0, // ignored - parameter DEPTH = 1 // ignored -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - reg [DATA_WIDTH-1:0] mem; - reg is_mem_valid; - - // If mem is valid, the FIFO is not empty and is full; if read, mem becomes - // invalid. If mem is not valid, the FIFO is not empty if and only if written - // and is not full; if written but not read, mem becomes valid. - - assign if_empty_n = is_mem_valid || (if_write && if_write_ce); - assign if_full_n = !is_mem_valid; - assign if_dout = is_mem_valid ? mem : if_din; - - always @(posedge clk) begin - if (reset) begin - is_mem_valid <= 1'b0; - end else begin - if (is_mem_valid) begin - if (if_read && if_read_ce) begin - is_mem_valid <= 1'b0; - end - end else begin - if (if_write && if_write_ce && !(if_read && if_read_ce)) begin - is_mem_valid <= 1'b1; - end - end - - if (if_write && if_write_ce) begin - mem <= if_din; - end - end - end - -endmodule // fifo_fwd - -`default_nettype wire diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo_srl.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo_srl.v deleted file mode 100644 index 8ed7a247..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/fifo_srl.v +++ /dev/null @@ -1,84 +0,0 @@ -`default_nettype none - -// first-word fall-through (FWFT) FIFO using shift register LUT -// based on HLS generated code -module fifo_srl #( - parameter MEM_STYLE = "shiftreg", - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 5, - parameter DEPTH = 32 -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - parameter REAL_DEPTH = DEPTH < 4 ? 4 : DEPTH; - parameter REAL_ADDR_WIDTH = $clog2(REAL_DEPTH)+1; - - wire [REAL_ADDR_WIDTH - 1:0] shift_reg_addr; - wire [DATA_WIDTH - 1:0] shift_reg_data; - wire [DATA_WIDTH - 1:0] shift_reg_q; - wire shift_reg_ce; - reg [REAL_ADDR_WIDTH:0] out_ptr; - reg internal_empty_n; - reg internal_full_n; - - (* shreg_extract = "yes" *) reg [DATA_WIDTH-1:0] mem [0:REAL_DEPTH-1]; - - assign if_empty_n = internal_empty_n; - assign if_full_n = internal_full_n; - assign shift_reg_data = if_din; - assign if_dout = shift_reg_q; - - assign shift_reg_addr = out_ptr[REAL_ADDR_WIDTH] == 1'b0 ? out_ptr[REAL_ADDR_WIDTH-1:0] : {REAL_ADDR_WIDTH{1'b0}}; - assign shift_reg_ce = (if_write & if_write_ce) & internal_full_n; - - assign shift_reg_q = mem[shift_reg_addr]; - - always @(posedge clk) begin - if (reset) begin - out_ptr <= ~{REAL_ADDR_WIDTH+1{1'b0}}; - internal_empty_n <= 1'b0; - internal_full_n <= 1'b1; - end else begin - if (((if_read && if_read_ce) && internal_empty_n) && - (!(if_write && if_write_ce) || !internal_full_n)) begin - out_ptr <= out_ptr - 1'b1; - if (out_ptr == {(REAL_ADDR_WIDTH+1){1'b0}}) - internal_empty_n <= 1'b0; - internal_full_n <= 1'b1; - end - else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && - ((if_write & if_write_ce) == 1 & internal_full_n == 1)) - begin - out_ptr <= out_ptr + 1'b1; - internal_empty_n <= 1'b1; - if (out_ptr == REAL_DEPTH - {{(REAL_ADDR_WIDTH-1){1'b0}}, 2'd2}) - internal_full_n <= 1'b0; - end - end - end - - integer i; - always @(posedge clk) begin - if (shift_reg_ce) begin - for (i = 0; i < REAL_DEPTH - 1; i = i + 1) - mem[i + 1] <= mem[i]; - mem[0] <= shift_reg_data; - end - end - -endmodule // fifo_srl - -`default_nettype wire diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/generate_last.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/generate_last.v deleted file mode 100644 index f592117d..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/generate_last.v +++ /dev/null @@ -1,71 +0,0 @@ -`default_nettype none - -module generate_last #( - parameter BurstLenWidth = 8 -) ( - input wire clk, - input wire rst, - - input wire [BurstLenWidth-1:0] burst_len_dout, - input wire burst_len_empty_n, - output reg burst_len_read, - - output reg last_din, - input wire last_full_n, - output reg last_write -); - - // state - reg busy; - reg [BurstLenWidth-1:0] count; - - // logic - reg busy_next; - reg [BurstLenWidth-1:0] count_next; - - always @* begin - busy_next = busy; - count_next = count; - burst_len_read = 1'b0; - last_write = 1'b0; - - if (last_full_n) begin - if (busy == 1'b0) begin - if (burst_len_empty_n) begin - // read from burst_len - burst_len_read = 1'b1; - count_next = burst_len_dout; - - // write to last - last_write = 1'b1; - last_din = ~|count_next; - - // change busy - if (|count_next) busy_next = 1'b1; - end - end else begin - count_next = count - 1'b1; - - // write to last - last_write = 1'b1; - last_din = ~|count_next; - - // change busy - if (~|count_next) busy_next = 1'b0; - end - end - end - - always @(posedge clk) begin - if (rst) begin - busy <= 1'b0; - count <= {BurstLenWidth{1'b0}}; - end else begin - busy <= busy_next; - count <= count_next; - end - end - -endmodule // generate_last - -`default_nettype wire diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel.v deleted file mode 100644 index 526eac43..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel.v +++ /dev/null @@ -1,576 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="inter_kernel_inter_kernel,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.430900,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=384,HLS_SYN_LUT=846,HLS_VERSION=2022_2}" *) - -module inter_kernel ( - ap_clk, - ap_rst_n, - ap_start, - ap_done, - ap_idle, - ap_ready, - a_read_addr_din, - a_read_addr_full_n, - a_read_addr_write, - a_read_data_s_dout, - a_read_data_s_empty_n, - a_read_data_s_read, - a_read_data_peek_dout, - a_read_data_peek_empty_n, - a_read_data_peek_read, - a_write_addr_din, - a_write_addr_full_n, - a_write_addr_write, - a_write_data_din, - a_write_data_full_n, - a_write_data_write, - a_write_resp_s_dout, - a_write_resp_s_empty_n, - a_write_resp_s_read, - a_write_resp_peek_dout, - a_write_resp_peek_empty_n, - a_write_resp_peek_read, - b_read_addr_din, - b_read_addr_full_n, - b_read_addr_write, - b_read_data_s_dout, - b_read_data_s_empty_n, - b_read_data_s_read, - b_read_data_peek_dout, - b_read_data_peek_empty_n, - b_read_data_peek_read, - b_write_addr_din, - b_write_addr_full_n, - b_write_addr_write, - b_write_data_din, - b_write_data_full_n, - b_write_data_write, - b_write_resp_s_dout, - b_write_resp_s_empty_n, - b_write_resp_s_read, - b_write_resp_peek_dout, - b_write_resp_peek_empty_n, - b_write_resp_peek_read, - stream_out_din, - stream_out_full_n, - stream_out_write, - stream_in_s_dout, - stream_in_s_empty_n, - stream_in_s_read, - stream_in_peek_dout, - stream_in_peek_empty_n, - stream_in_peek_read, - iters -); - -parameter ap_ST_fsm_state1 = 3'd1; -parameter ap_ST_fsm_state2 = 3'd2; -parameter ap_ST_fsm_state3 = 3'd4; - -input ap_clk; -input ap_rst_n; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -output [64:0] a_read_addr_din; -input a_read_addr_full_n; -output a_read_addr_write; -input [512:0] a_read_data_s_dout; -input a_read_data_s_empty_n; -output a_read_data_s_read; -input [512:0] a_read_data_peek_dout; -input a_read_data_peek_empty_n; -output a_read_data_peek_read; -output [64:0] a_write_addr_din; -input a_write_addr_full_n; -output a_write_addr_write; -output [512:0] a_write_data_din; -input a_write_data_full_n; -output a_write_data_write; -input [8:0] a_write_resp_s_dout; -input a_write_resp_s_empty_n; -output a_write_resp_s_read; -input [8:0] a_write_resp_peek_dout; -input a_write_resp_peek_empty_n; -output a_write_resp_peek_read; -output [64:0] b_read_addr_din; -input b_read_addr_full_n; -output b_read_addr_write; -input [512:0] b_read_data_s_dout; -input b_read_data_s_empty_n; -output b_read_data_s_read; -input [512:0] b_read_data_peek_dout; -input b_read_data_peek_empty_n; -output b_read_data_peek_read; -output [64:0] b_write_addr_din; -input b_write_addr_full_n; -output b_write_addr_write; -output [512:0] b_write_data_din; -input b_write_data_full_n; -output b_write_data_write; -input [8:0] b_write_resp_s_dout; -input b_write_resp_s_empty_n; -output b_write_resp_s_read; -input [8:0] b_write_resp_peek_dout; -input b_write_resp_peek_empty_n; -output b_write_resp_peek_read; -output [512:0] stream_out_din; -input stream_out_full_n; -output stream_out_write; -input [512:0] stream_in_s_dout; -input stream_in_s_empty_n; -output stream_in_s_read; -input [512:0] stream_in_peek_dout; -input stream_in_peek_empty_n; -output stream_in_peek_read; -input [31:0] iters; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg a_read_addr_write; -reg a_read_data_s_read; -reg a_write_addr_write; -reg a_write_data_write; -reg a_write_resp_s_read; -reg b_read_addr_write; -reg b_read_data_s_read; -reg b_write_addr_write; -reg b_write_data_write; -reg b_write_resp_s_read; -reg stream_out_write; -reg stream_in_s_read; - - reg ap_rst_n_inv; -(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire [0:0] trunc_ln133_fu_250_p1; -reg [0:0] trunc_ln133_reg_282; -wire ap_CS_fsm_state2; -wire [31:0] i_2_fu_259_p2; -reg [31:0] i_2_reg_289; -wire grp_load_fu_218_ap_start; -wire grp_load_fu_218_ap_done; -wire grp_load_fu_218_ap_idle; -wire grp_load_fu_218_ap_ready; -wire [64:0] grp_load_fu_218_b_read_addr_din; -reg grp_load_fu_218_b_read_addr_full_n; -wire grp_load_fu_218_b_read_addr_write; -reg [512:0] grp_load_fu_218_b_read_data_s_dout; -reg grp_load_fu_218_b_read_data_s_empty_n; -wire grp_load_fu_218_b_read_data_s_read; -wire [64:0] grp_load_fu_218_a_write_addr_din; -reg grp_load_fu_218_a_write_addr_full_n; -wire grp_load_fu_218_a_write_addr_write; -wire [512:0] grp_load_fu_218_a_write_data_din; -reg grp_load_fu_218_a_write_data_full_n; -wire grp_load_fu_218_a_write_data_write; -reg [8:0] grp_load_fu_218_a_write_resp_s_dout; -reg grp_load_fu_218_a_write_resp_s_empty_n; -wire grp_load_fu_218_a_write_resp_s_read; -wire [512:0] grp_load_fu_218_stream_out_din; -wire grp_load_fu_218_stream_out_write; -wire grp_load_fu_218_stream_in_s_read; -reg grp_load_fu_218_ap_start_reg; -wire [0:0] icmp_ln133_fu_254_p2; -wire ap_CS_fsm_state3; -reg [31:0] i_fu_72; -reg ap_block_state3_on_subcall_done; -reg [2:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 3'd1; -#0 grp_load_fu_218_ap_start_reg = 1'b0; -end - -inter_kernel_load grp_load_fu_218( - .ap_clk(ap_clk), - .ap_rst(ap_rst_n_inv), - .ap_start(grp_load_fu_218_ap_start), - .ap_done(grp_load_fu_218_ap_done), - .ap_idle(grp_load_fu_218_ap_idle), - .ap_ready(grp_load_fu_218_ap_ready), - .b_read_addr_din(grp_load_fu_218_b_read_addr_din), - .b_read_addr_full_n(grp_load_fu_218_b_read_addr_full_n), - .b_read_addr_write(grp_load_fu_218_b_read_addr_write), - .b_read_data_s_dout(grp_load_fu_218_b_read_data_s_dout), - .b_read_data_s_empty_n(grp_load_fu_218_b_read_data_s_empty_n), - .b_read_data_s_read(grp_load_fu_218_b_read_data_s_read), - .a_write_addr_din(grp_load_fu_218_a_write_addr_din), - .a_write_addr_full_n(grp_load_fu_218_a_write_addr_full_n), - .a_write_addr_write(grp_load_fu_218_a_write_addr_write), - .a_write_data_din(grp_load_fu_218_a_write_data_din), - .a_write_data_full_n(grp_load_fu_218_a_write_data_full_n), - .a_write_data_write(grp_load_fu_218_a_write_data_write), - .a_write_resp_s_dout(grp_load_fu_218_a_write_resp_s_dout), - .a_write_resp_s_empty_n(grp_load_fu_218_a_write_resp_s_empty_n), - .a_write_resp_s_read(grp_load_fu_218_a_write_resp_s_read), - .stream_out_din(grp_load_fu_218_stream_out_din), - .stream_out_full_n(stream_out_full_n), - .stream_out_write(grp_load_fu_218_stream_out_write), - .stream_in_s_dout(stream_in_s_dout), - .stream_in_s_empty_n(stream_in_s_empty_n), - .stream_in_s_read(grp_load_fu_218_stream_in_s_read), - .iters(iters) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - grp_load_fu_218_ap_start_reg <= 1'b0; - end else begin - if ((((trunc_ln133_fu_250_p1 == 1'd1) & (1'b1 == ap_CS_fsm_state2) & (icmp_ln133_fu_254_p2 == 1'd0)) | ((trunc_ln133_fu_250_p1 == 1'd0) & (1'b1 == ap_CS_fsm_state2) & (icmp_ln133_fu_254_p2 == 1'd0)))) begin - grp_load_fu_218_ap_start_reg <= 1'b1; - end else if ((grp_load_fu_218_ap_ready == 1'b1)) begin - grp_load_fu_218_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - i_fu_72 <= 32'd0; - end else if (((1'b1 == ap_CS_fsm_state3) & (1'b0 == ap_block_state3_on_subcall_done))) begin - i_fu_72 <= i_2_reg_289; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state2)) begin - i_2_reg_289 <= i_2_fu_259_p2; - trunc_ln133_reg_282 <= trunc_ln133_fu_250_p1; - end -end - -always @ (*) begin - if (((trunc_ln133_reg_282 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin - a_read_addr_write = grp_load_fu_218_b_read_addr_write; - end else begin - a_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((trunc_ln133_reg_282 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin - a_read_data_s_read = grp_load_fu_218_b_read_data_s_read; - end else begin - a_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if (((trunc_ln133_reg_282 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin - a_write_addr_write = grp_load_fu_218_a_write_addr_write; - end else begin - a_write_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((trunc_ln133_reg_282 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin - a_write_data_write = grp_load_fu_218_a_write_data_write; - end else begin - a_write_data_write = 1'b0; - end -end - -always @ (*) begin - if (((trunc_ln133_reg_282 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin - a_write_resp_s_read = grp_load_fu_218_a_write_resp_s_read; - end else begin - a_write_resp_s_read = 1'b0; - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if ((1'b1 == ap_block_state3_on_subcall_done)) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln133_fu_254_p2 == 1'd1))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln133_fu_254_p2 == 1'd1))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if (((trunc_ln133_reg_282 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin - b_read_addr_write = grp_load_fu_218_b_read_addr_write; - end else begin - b_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((trunc_ln133_reg_282 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin - b_read_data_s_read = grp_load_fu_218_b_read_data_s_read; - end else begin - b_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if (((trunc_ln133_reg_282 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin - b_write_addr_write = grp_load_fu_218_a_write_addr_write; - end else begin - b_write_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((trunc_ln133_reg_282 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin - b_write_data_write = grp_load_fu_218_a_write_data_write; - end else begin - b_write_data_write = 1'b0; - end -end - -always @ (*) begin - if (((trunc_ln133_reg_282 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin - b_write_resp_s_read = grp_load_fu_218_a_write_resp_s_read; - end else begin - b_write_resp_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - if ((trunc_ln133_reg_282 == 1'd1)) begin - grp_load_fu_218_a_write_addr_full_n = a_write_addr_full_n; - end else if ((trunc_ln133_reg_282 == 1'd0)) begin - grp_load_fu_218_a_write_addr_full_n = b_write_addr_full_n; - end else begin - grp_load_fu_218_a_write_addr_full_n = a_write_addr_full_n; - end - end else begin - grp_load_fu_218_a_write_addr_full_n = a_write_addr_full_n; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - if ((trunc_ln133_reg_282 == 1'd1)) begin - grp_load_fu_218_a_write_data_full_n = a_write_data_full_n; - end else if ((trunc_ln133_reg_282 == 1'd0)) begin - grp_load_fu_218_a_write_data_full_n = b_write_data_full_n; - end else begin - grp_load_fu_218_a_write_data_full_n = a_write_data_full_n; - end - end else begin - grp_load_fu_218_a_write_data_full_n = a_write_data_full_n; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - if ((trunc_ln133_reg_282 == 1'd1)) begin - grp_load_fu_218_a_write_resp_s_dout = a_write_resp_s_dout; - end else if ((trunc_ln133_reg_282 == 1'd0)) begin - grp_load_fu_218_a_write_resp_s_dout = b_write_resp_s_dout; - end else begin - grp_load_fu_218_a_write_resp_s_dout = a_write_resp_s_dout; - end - end else begin - grp_load_fu_218_a_write_resp_s_dout = a_write_resp_s_dout; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - if ((trunc_ln133_reg_282 == 1'd1)) begin - grp_load_fu_218_a_write_resp_s_empty_n = a_write_resp_s_empty_n; - end else if ((trunc_ln133_reg_282 == 1'd0)) begin - grp_load_fu_218_a_write_resp_s_empty_n = b_write_resp_s_empty_n; - end else begin - grp_load_fu_218_a_write_resp_s_empty_n = a_write_resp_s_empty_n; - end - end else begin - grp_load_fu_218_a_write_resp_s_empty_n = a_write_resp_s_empty_n; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - if ((trunc_ln133_reg_282 == 1'd1)) begin - grp_load_fu_218_b_read_addr_full_n = b_read_addr_full_n; - end else if ((trunc_ln133_reg_282 == 1'd0)) begin - grp_load_fu_218_b_read_addr_full_n = a_read_addr_full_n; - end else begin - grp_load_fu_218_b_read_addr_full_n = b_read_addr_full_n; - end - end else begin - grp_load_fu_218_b_read_addr_full_n = b_read_addr_full_n; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - if ((trunc_ln133_reg_282 == 1'd1)) begin - grp_load_fu_218_b_read_data_s_dout = b_read_data_s_dout; - end else if ((trunc_ln133_reg_282 == 1'd0)) begin - grp_load_fu_218_b_read_data_s_dout = a_read_data_s_dout; - end else begin - grp_load_fu_218_b_read_data_s_dout = b_read_data_s_dout; - end - end else begin - grp_load_fu_218_b_read_data_s_dout = b_read_data_s_dout; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - if ((trunc_ln133_reg_282 == 1'd1)) begin - grp_load_fu_218_b_read_data_s_empty_n = b_read_data_s_empty_n; - end else if ((trunc_ln133_reg_282 == 1'd0)) begin - grp_load_fu_218_b_read_data_s_empty_n = a_read_data_s_empty_n; - end else begin - grp_load_fu_218_b_read_data_s_empty_n = b_read_data_s_empty_n; - end - end else begin - grp_load_fu_218_b_read_data_s_empty_n = b_read_data_s_empty_n; - end -end - -always @ (*) begin - if ((((trunc_ln133_reg_282 == 1'd1) & (1'b1 == ap_CS_fsm_state3)) | ((trunc_ln133_reg_282 == 1'd0) & (1'b1 == ap_CS_fsm_state3)))) begin - stream_in_s_read = grp_load_fu_218_stream_in_s_read; - end else begin - stream_in_s_read = 1'b0; - end -end - -always @ (*) begin - if ((((trunc_ln133_reg_282 == 1'd1) & (1'b1 == ap_CS_fsm_state3)) | ((trunc_ln133_reg_282 == 1'd0) & (1'b1 == ap_CS_fsm_state3)))) begin - stream_out_write = grp_load_fu_218_stream_out_write; - end else begin - stream_out_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln133_fu_254_p2 == 1'd1))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - ap_ST_fsm_state3 : begin - if (((1'b1 == ap_CS_fsm_state3) & (1'b0 == ap_block_state3_on_subcall_done))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign a_read_addr_din = grp_load_fu_218_b_read_addr_din; - -assign a_read_data_peek_read = 1'b0; - -assign a_write_addr_din = grp_load_fu_218_a_write_addr_din; - -assign a_write_data_din = grp_load_fu_218_a_write_data_din; - -assign a_write_resp_peek_read = 1'b0; - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -always @ (*) begin - ap_block_state3_on_subcall_done = (((trunc_ln133_reg_282 == 1'd1) & (grp_load_fu_218_ap_done == 1'b0)) | ((trunc_ln133_reg_282 == 1'd0) & (grp_load_fu_218_ap_done == 1'b0))); -end - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -assign b_read_addr_din = grp_load_fu_218_b_read_addr_din; - -assign b_read_data_peek_read = 1'b0; - -assign b_write_addr_din = grp_load_fu_218_a_write_addr_din; - -assign b_write_data_din = grp_load_fu_218_a_write_data_din; - -assign b_write_resp_peek_read = 1'b0; - -assign grp_load_fu_218_ap_start = grp_load_fu_218_ap_start_reg; - -assign i_2_fu_259_p2 = (i_fu_72 + 32'd1); - -assign icmp_ln133_fu_254_p2 = ((i_fu_72 == iters) ? 1'b1 : 1'b0); - -assign stream_in_peek_read = 1'b0; - -assign stream_out_din = grp_load_fu_218_stream_out_din; - -assign trunc_ln133_fu_250_p1 = i_fu_72[0:0]; - -endmodule //inter_kernel diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel_flow_control_loop_pipe_sequential_init.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel_flow_control_loop_pipe_sequential_init.v deleted file mode 100644 index fad8c899..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel_flow_control_loop_pipe_sequential_init.v +++ /dev/null @@ -1,104 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== - -`timescale 1 ns / 1 ps - -module inter_kernel_flow_control_loop_pipe_sequential_init( - ap_clk, - ap_rst, - ap_start, - ap_ready, - ap_done, - ap_start_int, - ap_ready_int, - ap_done_int, - ap_continue_int, - ap_loop_init, - ap_loop_exit_ready, - ap_loop_exit_done -); - -input ap_clk; -input ap_rst; - -//Block level handshake with outside loop -input ap_start; -output ap_ready; -output ap_done; - -//Block level handshake with loop body -output ap_start_int; -input ap_ready_int; -input ap_done_int; -output ap_continue_int; - -//Init live in variables -output ap_loop_init; -wire ap_loop_init; -reg ap_loop_init_int; -reg ap_done; -reg ap_done_cache; - -//Exit signal from loop body -input ap_loop_exit_ready; -input ap_loop_exit_done; - -// power-on initialization -initial begin -#0 ap_loop_init_int = 1'b1; -#0 ap_done_cache = 1'b0; -end - -assign ap_start_int = ap_start; - -assign ap_continue_int = 1'b1; - -assign ap_ready = ap_loop_exit_ready; - -//ap_loop_init is valid for the first II -//of the first loop run so as to enable -//the init block ops which are pushed into -//the first state of the pipeline region -always @ (posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_loop_exit_done == 1'b1) begin - ap_loop_init_int <= 1'b1; - end else if(ap_ready_int == 1'b1) begin - ap_loop_init_int <= 1'b0; - end -end - -assign ap_loop_init = ap_loop_init_int & ap_start; - -// if no ap_continue port and current module is not top module, -// ap_done handshakes with ap_start. Internally, flow control sends out -// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle. -// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int -// is asserted, so DUT can start the next run -always @(posedge ap_clk) -begin - if (ap_rst == 1'b1) begin - ap_done_cache <= 1'b0; - end else if (ap_done_int == 1'b1) begin - ap_done_cache <= 1'b1; - end else if (ap_start_int == 1'b1) begin - ap_done_cache <= 1'b0; - end -end - -// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start -always @(*) -begin - if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel_load.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel_load.v deleted file mode 100644 index 6b19cd56..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel_load.v +++ /dev/null @@ -1,323 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module inter_kernel_load ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - b_read_addr_din, - b_read_addr_full_n, - b_read_addr_write, - b_read_data_s_dout, - b_read_data_s_empty_n, - b_read_data_s_read, - a_write_addr_din, - a_write_addr_full_n, - a_write_addr_write, - a_write_data_din, - a_write_data_full_n, - a_write_data_write, - a_write_resp_s_dout, - a_write_resp_s_empty_n, - a_write_resp_s_read, - stream_out_din, - stream_out_full_n, - stream_out_write, - stream_in_s_dout, - stream_in_s_empty_n, - stream_in_s_read, - iters -); - -parameter ap_ST_fsm_state1 = 3'd1; -parameter ap_ST_fsm_state2 = 3'd2; -parameter ap_ST_fsm_state3 = 3'd4; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -output [64:0] b_read_addr_din; -input b_read_addr_full_n; -output b_read_addr_write; -input [512:0] b_read_data_s_dout; -input b_read_data_s_empty_n; -output b_read_data_s_read; -output [64:0] a_write_addr_din; -input a_write_addr_full_n; -output a_write_addr_write; -output [512:0] a_write_data_din; -input a_write_data_full_n; -output a_write_data_write; -input [8:0] a_write_resp_s_dout; -input a_write_resp_s_empty_n; -output a_write_resp_s_read; -output [512:0] stream_out_din; -input stream_out_full_n; -output stream_out_write; -input [512:0] stream_in_s_dout; -input stream_in_s_empty_n; -output stream_in_s_read; -input [31:0] iters; - -reg ap_done; -reg ap_idle; -reg ap_ready; -reg b_read_addr_write; -reg b_read_data_s_read; -reg a_write_addr_write; -reg a_write_data_write; -reg a_write_resp_s_read; -reg stream_out_write; -reg stream_in_s_read; - -(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm; -wire ap_CS_fsm_state1; -wire [31:0] loop_bound_fu_71_p2; -reg [31:0] loop_bound_reg_84; -wire ap_CS_fsm_state2; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_start; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_done; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_idle; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_ready; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_resp_s_read; -wire [64:0] grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_b_read_addr_din; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_b_read_addr_write; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_b_read_data_s_read; -wire [512:0] grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_stream_out_din; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_stream_out_write; -wire [64:0] grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_addr_din; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_addr_write; -wire [512:0] grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_data_din; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_data_write; -wire grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_stream_in_s_read; -reg grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_start_reg; -wire ap_CS_fsm_state3; -wire [31:0] add_ln44_fu_66_p2; -wire [31:0] shl_ln44_fu_61_p2; -reg [2:0] ap_NS_fsm; -reg ap_ST_fsm_state1_blk; -wire ap_ST_fsm_state2_blk; -reg ap_ST_fsm_state3_blk; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 3'd1; -#0 grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_start_reg = 1'b0; -end - -inter_kernel_load_Pipeline_VITIS_LOOP_45_1 grp_load_Pipeline_VITIS_LOOP_45_1_fu_42( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_start), - .ap_done(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_done), - .ap_idle(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_idle), - .ap_ready(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_ready), - .a_write_resp_s_dout(a_write_resp_s_dout), - .a_write_resp_s_empty_n(a_write_resp_s_empty_n), - .a_write_resp_s_read(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_resp_s_read), - .loop_bound(loop_bound_reg_84), - .b_read_addr_din(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_b_read_addr_din), - .b_read_addr_full_n(b_read_addr_full_n), - .b_read_addr_write(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_b_read_addr_write), - .b_read_data_s_dout(b_read_data_s_dout), - .b_read_data_s_empty_n(b_read_data_s_empty_n), - .b_read_data_s_read(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_b_read_data_s_read), - .stream_out_din(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_stream_out_din), - .stream_out_full_n(stream_out_full_n), - .stream_out_write(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_stream_out_write), - .a_write_addr_din(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_addr_din), - .a_write_addr_full_n(a_write_addr_full_n), - .a_write_addr_write(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_addr_write), - .a_write_data_din(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_data_din), - .a_write_data_full_n(a_write_data_full_n), - .a_write_data_write(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_data_write), - .stream_in_s_dout(stream_in_s_dout), - .stream_in_s_empty_n(stream_in_s_empty_n), - .stream_in_s_read(grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_stream_in_s_read) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_state1; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_start_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_state2)) begin - grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_start_reg <= 1'b1; - end else if ((grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_ready == 1'b1)) begin - grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_start_reg <= 1'b0; - end - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_CS_fsm_state2)) begin - loop_bound_reg_84 <= loop_bound_fu_71_p2; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - a_write_addr_write = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_addr_write; - end else begin - a_write_addr_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - a_write_data_write = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_data_write; - end else begin - a_write_data_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - a_write_resp_s_read = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_resp_s_read; - end else begin - a_write_resp_s_read = 1'b0; - end -end - -always @ (*) begin - if ((ap_start == 1'b0)) begin - ap_ST_fsm_state1_blk = 1'b1; - end else begin - ap_ST_fsm_state1_blk = 1'b0; - end -end - -assign ap_ST_fsm_state2_blk = 1'b0; - -always @ (*) begin - if ((grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_done == 1'b0)) begin - ap_ST_fsm_state3_blk = 1'b1; - end else begin - ap_ST_fsm_state3_blk = 1'b0; - end -end - -always @ (*) begin - if ((((grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3)) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - b_read_addr_write = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_b_read_addr_write; - end else begin - b_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - b_read_data_s_read = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_b_read_data_s_read; - end else begin - b_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - stream_in_s_read = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_stream_in_s_read; - end else begin - stream_in_s_read = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_state3)) begin - stream_out_write = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_stream_out_write; - end else begin - stream_out_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_state1 : begin - if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin - ap_NS_fsm = ap_ST_fsm_state2; - end else begin - ap_NS_fsm = ap_ST_fsm_state1; - end - end - ap_ST_fsm_state2 : begin - ap_NS_fsm = ap_ST_fsm_state3; - end - ap_ST_fsm_state3 : begin - if (((grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin - ap_NS_fsm = ap_ST_fsm_state1; - end else begin - ap_NS_fsm = ap_ST_fsm_state3; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign a_write_addr_din = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_addr_din; - -assign a_write_data_din = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_a_write_data_din; - -assign add_ln44_fu_66_p2 = (iters + 32'd341); - -assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; - -assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; - -assign b_read_addr_din = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_b_read_addr_din; - -assign grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_start = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_ap_start_reg; - -assign loop_bound_fu_71_p2 = (add_ln44_fu_66_p2 + shl_ln44_fu_61_p2); - -assign shl_ln44_fu_61_p2 = iters << 32'd5; - -assign stream_out_din = grp_load_Pipeline_VITIS_LOOP_45_1_fu_42_stream_out_din; - -endmodule //inter_kernel_load diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel_load_Pipeline_VITIS_LOOP_45_1.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel_load_Pipeline_VITIS_LOOP_45_1.v deleted file mode 100644 index 6b0bdc26..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/inter_kernel_load_Pipeline_VITIS_LOOP_45_1.v +++ /dev/null @@ -1,662 +0,0 @@ -// ============================================================== -// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Version: 2022.2 -// Copyright (C) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -module inter_kernel_load_Pipeline_VITIS_LOOP_45_1 ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_idle, - ap_ready, - a_write_resp_s_dout, - a_write_resp_s_empty_n, - a_write_resp_s_read, - loop_bound, - b_read_addr_din, - b_read_addr_full_n, - b_read_addr_write, - b_read_data_s_dout, - b_read_data_s_empty_n, - b_read_data_s_read, - stream_out_din, - stream_out_full_n, - stream_out_write, - a_write_addr_din, - a_write_addr_full_n, - a_write_addr_write, - a_write_data_din, - a_write_data_full_n, - a_write_data_write, - stream_in_s_dout, - stream_in_s_empty_n, - stream_in_s_read -); - -parameter ap_ST_fsm_pp0_stage0 = 2'd1; -parameter ap_ST_fsm_pp0_stage1 = 2'd2; - -input ap_clk; -input ap_rst; -input ap_start; -output ap_done; -output ap_idle; -output ap_ready; -input [8:0] a_write_resp_s_dout; -input a_write_resp_s_empty_n; -output a_write_resp_s_read; -input [31:0] loop_bound; -output [64:0] b_read_addr_din; -input b_read_addr_full_n; -output b_read_addr_write; -input [512:0] b_read_data_s_dout; -input b_read_data_s_empty_n; -output b_read_data_s_read; -output [512:0] stream_out_din; -input stream_out_full_n; -output stream_out_write; -output [64:0] a_write_addr_din; -input a_write_addr_full_n; -output a_write_addr_write; -output [512:0] a_write_data_din; -input a_write_data_full_n; -output a_write_data_write; -input [512:0] stream_in_s_dout; -input stream_in_s_empty_n; -output stream_in_s_read; - -reg ap_idle; -reg a_write_resp_s_read; -reg b_read_addr_write; -reg b_read_data_s_read; -reg stream_out_write; -reg a_write_addr_write; -reg a_write_data_write; -reg stream_in_s_read; - -(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm; -wire ap_CS_fsm_pp0_stage0; -reg ap_enable_reg_pp0_iter0; -reg ap_enable_reg_pp0_iter1; -reg ap_idle_pp0; -wire ap_CS_fsm_pp0_stage1; -wire [0:0] or_ln45_fu_226_p2; -wire [0:0] tmp_1_nbreadreq_fu_137_p3; -reg ap_predicate_op53_read_state2; -reg ap_block_state2_pp0_stage1_iter0; -reg ap_block_pp0_stage1_subdone; -reg ap_condition_exit_pp0_iter0_stage1; -wire ap_loop_exit_ready; -reg ap_ready_int; -reg a_write_resp_s_blk_n; -wire ap_block_pp0_stage1; -reg stream_out_blk_n; -wire ap_block_pp0_stage0; -reg [0:0] or_ln45_reg_418; -reg [0:0] icmp_ln45_reg_414; -reg [0:0] tmp_3_reg_431; -reg [0:0] tmp_4_reg_435; -reg a_write_addr_blk_n; -reg [0:0] icmp_ln56_reg_439; -reg [0:0] tmp_s_reg_443; -reg [0:0] tmp_5_reg_447; -reg [0:0] tmp_6_reg_451; -reg a_write_data_blk_n; -reg stream_in_s_blk_n; -wire ap_block_state1_pp0_stage0_iter0; -reg ap_predicate_op62_write_state3; -reg ap_predicate_op68_write_state3; -reg ap_predicate_op69_read_state3; -reg ap_predicate_op72_write_state3; -reg ap_block_state3_pp0_stage0_iter1; -reg ap_block_pp0_stage0_11001; -reg signed [31:0] k_wr_req_1_reg_398; -reg ap_block_pp0_stage1_11001; -reg [31:0] k_rd_resp_1_reg_404; -reg [31:0] k_wr_resp_1_reg_409; -wire [0:0] icmp_ln45_fu_216_p2; -wire [0:0] icmp_ln47_fu_232_p2; -reg [0:0] icmp_ln47_reg_422; -wire [31:0] select_ln47_fu_256_p3; -reg [31:0] select_ln47_reg_426; -wire [0:0] tmp_3_nbreadreq_fu_97_p3; -wire [0:0] icmp_ln56_fu_264_p2; -wire [0:0] tmp_s_nbwritereq_fu_113_p3; -wire [0:0] tmp_5_nbwritereq_fu_121_p3; -wire [0:0] tmp_6_nbreadreq_fu_129_p3; -reg [0:0] tmp_1_reg_455; -wire [7:0] trunc_ln85_1_fu_269_p1; -reg [7:0] trunc_ln85_1_reg_459; -reg ap_enable_reg_pp0_iter0_reg; -reg ap_block_pp0_stage0_subdone; -reg [31:0] k_wr_req_fu_68; -wire [31:0] k_wr_req_2_fu_329_p2; -wire ap_loop_init; -reg [31:0] k_rd_resp_fu_72; -wire [31:0] k_rd_resp_2_fu_294_p2; -reg [31:0] k_rd_req_fu_76; -reg [31:0] k_wr_resp_fu_80; -wire [31:0] k_wr_resp_2_fu_352_p2; -reg ap_block_pp0_stage1_01001; -reg ap_block_pp0_stage0_01001; -wire [0:0] icmp_ln45_1_fu_221_p2; -wire signed [31:0] icmp_ln47_fu_232_p0; -wire signed [31:0] sext_ln47_fu_237_p0; -wire signed [63:0] sext_ln47_fu_237_p1; -wire signed [31:0] add_ln48_fu_250_p0; -wire [0:0] select_ln47_fu_256_p0; -wire [31:0] add_ln48_fu_250_p2; -wire signed [31:0] select_ln47_fu_256_p2; -wire signed [31:0] icmp_ln56_fu_264_p0; -wire [511:0] trunc_ln104_fu_281_p1; -wire signed [63:0] sext_ln57_fu_304_p1; -wire [511:0] trunc_ln85_fu_316_p1; -wire [8:0] zext_ln62_fu_339_p1; -wire [8:0] add_ln62_fu_342_p2; -wire [31:0] zext_ln62_1_fu_348_p1; -reg ap_done_reg; -wire ap_continue_int; -reg ap_done_int; -reg [1:0] ap_NS_fsm; -reg ap_idle_pp0_1to1; -wire ap_enable_pp0; -wire ap_start_int; -reg ap_condition_400; -reg ap_condition_406; -reg ap_condition_413; -reg ap_condition_417; -wire ap_ce_reg; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 2'd1; -#0 ap_enable_reg_pp0_iter1 = 1'b0; -#0 ap_enable_reg_pp0_iter0_reg = 1'b0; -#0 ap_done_reg = 1'b0; -end - -inter_kernel_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U( - .ap_clk(ap_clk), - .ap_rst(ap_rst), - .ap_start(ap_start), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_start_int(ap_start_int), - .ap_loop_init(ap_loop_init), - .ap_ready_int(ap_ready_int), - .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage1), - .ap_loop_exit_done(ap_done_int), - .ap_continue_int(ap_continue_int), - .ap_done_int(ap_done_int) -); - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_CS_fsm <= ap_ST_fsm_pp0_stage0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_done_reg <= 1'b0; - end else begin - if ((ap_continue_int == 1'b1)) begin - ap_done_reg <= 1'b0; - end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin - ap_done_reg <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter0_reg <= 1'b0; - end else begin - if ((1'b1 == ap_CS_fsm_pp0_stage0)) begin - ap_enable_reg_pp0_iter0_reg <= ap_start_int; - end - end -end - -always @ (posedge ap_clk) begin - if (ap_rst == 1'b1) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else begin - if (((1'b1 == ap_condition_exit_pp0_iter0_stage1) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin - ap_enable_reg_pp0_iter1 <= 1'b0; - end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin - ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - k_rd_req_fu_76 <= 32'd0; - end else if ((1'b1 == ap_condition_400)) begin - k_rd_req_fu_76 <= select_ln47_reg_426; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - k_rd_resp_fu_72 <= 32'd0; - end else if ((1'b1 == ap_condition_406)) begin - k_rd_resp_fu_72 <= k_rd_resp_2_fu_294_p2; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - k_wr_req_fu_68 <= 32'd33; - end else if ((1'b1 == ap_condition_413)) begin - k_wr_req_fu_68 <= k_wr_req_2_fu_329_p2; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - if ((ap_loop_init == 1'b1)) begin - k_wr_resp_fu_80 <= 32'd33; - end else if ((1'b1 == ap_condition_417)) begin - k_wr_resp_fu_80 <= k_wr_resp_2_fu_352_p2; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin - icmp_ln45_reg_414 <= icmp_ln45_fu_216_p2; - k_rd_resp_1_reg_404 <= k_rd_resp_fu_72; - k_wr_req_1_reg_398 <= k_wr_req_fu_68; - k_wr_resp_1_reg_409 <= k_wr_resp_fu_80; - or_ln45_reg_418 <= or_ln45_fu_226_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage1_11001) & (or_ln45_fu_226_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin - icmp_ln47_reg_422 <= icmp_ln47_fu_232_p2; - icmp_ln56_reg_439 <= icmp_ln56_fu_264_p2; - tmp_1_reg_455 <= tmp_1_nbreadreq_fu_137_p3; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage1_11001) & (or_ln45_fu_226_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln47_fu_232_p2 == 1'd1))) begin - select_ln47_reg_426 <= select_ln47_fu_256_p3; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage1_11001) & (or_ln45_fu_226_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln45_fu_216_p2 == 1'd1))) begin - tmp_3_reg_431 <= tmp_3_nbreadreq_fu_97_p3; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage1_11001) & (or_ln45_fu_226_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (tmp_3_nbreadreq_fu_97_p3 == 1'd1) & (icmp_ln45_fu_216_p2 == 1'd1))) begin - tmp_4_reg_435 <= stream_out_full_n; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage1_11001) & (or_ln45_fu_226_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (tmp_s_nbwritereq_fu_113_p3 == 1'd1) & (icmp_ln56_fu_264_p2 == 1'd1))) begin - tmp_5_reg_447 <= a_write_data_full_n; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage1_11001) & (or_ln45_fu_226_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (tmp_5_nbwritereq_fu_121_p3 == 1'd1) & (tmp_s_nbwritereq_fu_113_p3 == 1'd1) & (icmp_ln56_fu_264_p2 == 1'd1))) begin - tmp_6_reg_451 <= tmp_6_nbreadreq_fu_129_p3; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage1_11001) & (or_ln45_fu_226_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln56_fu_264_p2 == 1'd1))) begin - tmp_s_reg_443 <= a_write_addr_full_n; - end -end - -always @ (posedge ap_clk) begin - if (((1'b0 == ap_block_pp0_stage1_11001) & (tmp_1_nbreadreq_fu_137_p3 == 1'd1) & (or_ln45_fu_226_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin - trunc_ln85_1_reg_459 <= trunc_ln85_1_fu_269_p1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (tmp_6_reg_451 == 1'd1) & (tmp_5_reg_447 == 1'd1) & (tmp_s_reg_443 == 1'd1) & (icmp_ln56_reg_439 == 1'd1) & (or_ln45_reg_418 == 1'd1))) begin - a_write_addr_blk_n = a_write_addr_full_n; - end else begin - a_write_addr_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_predicate_op68_write_state3 == 1'b1))) begin - a_write_addr_write = 1'b1; - end else begin - a_write_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (tmp_6_reg_451 == 1'd1) & (tmp_5_reg_447 == 1'd1) & (tmp_s_reg_443 == 1'd1) & (icmp_ln56_reg_439 == 1'd1) & (or_ln45_reg_418 == 1'd1))) begin - a_write_data_blk_n = a_write_data_full_n; - end else begin - a_write_data_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_predicate_op72_write_state3 == 1'b1))) begin - a_write_data_write = 1'b1; - end else begin - a_write_data_write = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage1) & (ap_predicate_op53_read_state2 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin - a_write_resp_s_blk_n = a_write_resp_s_empty_n; - end else begin - a_write_resp_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage1_11001) & (ap_predicate_op53_read_state2 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin - a_write_resp_s_read = 1'b1; - end else begin - a_write_resp_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage1_subdone) & (or_ln45_fu_226_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin - ap_condition_exit_pp0_iter0_stage1 = 1'b1; - end else begin - ap_condition_exit_pp0_iter0_stage1 = 1'b0; - end -end - -always @ (*) begin - if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin - ap_done_int = 1'b1; - end else begin - ap_done_int = ap_done_reg; - end -end - -always @ (*) begin - if ((1'b1 == ap_CS_fsm_pp0_stage0)) begin - ap_enable_reg_pp0_iter0 = ap_start_int; - end else begin - ap_enable_reg_pp0_iter0 = ap_enable_reg_pp0_iter0_reg; - end -end - -always @ (*) begin - if (((ap_start_int == 1'b0) & (ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin - ap_idle_pp0 = 1'b1; - end else begin - ap_idle_pp0 = 1'b0; - end -end - -always @ (*) begin - if ((ap_enable_reg_pp0_iter1 == 1'b0)) begin - ap_idle_pp0_1to1 = 1'b1; - end else begin - ap_idle_pp0_1to1 = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin - ap_ready_int = 1'b1; - end else begin - ap_ready_int = 1'b0; - end -end - -always @ (*) begin - if (((b_read_addr_full_n == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (or_ln45_fu_226_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln47_fu_232_p2 == 1'd1))) begin - b_read_addr_write = 1'b1; - end else begin - b_read_addr_write = 1'b0; - end -end - -always @ (*) begin - if (((b_read_data_s_empty_n == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (tmp_4_reg_435 == 1'd1) & (tmp_3_reg_431 == 1'd1) & (icmp_ln45_reg_414 == 1'd1) & (or_ln45_reg_418 == 1'd1))) begin - b_read_data_s_read = 1'b1; - end else begin - b_read_data_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (tmp_6_reg_451 == 1'd1) & (tmp_5_reg_447 == 1'd1) & (tmp_s_reg_443 == 1'd1) & (icmp_ln56_reg_439 == 1'd1) & (or_ln45_reg_418 == 1'd1))) begin - stream_in_s_blk_n = stream_in_s_empty_n; - end else begin - stream_in_s_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_predicate_op69_read_state3 == 1'b1))) begin - stream_in_s_read = 1'b1; - end else begin - stream_in_s_read = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (tmp_4_reg_435 == 1'd1) & (tmp_3_reg_431 == 1'd1) & (icmp_ln45_reg_414 == 1'd1) & (or_ln45_reg_418 == 1'd1))) begin - stream_out_blk_n = stream_out_full_n; - end else begin - stream_out_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_predicate_op62_write_state3 == 1'b1))) begin - stream_out_write = 1'b1; - end else begin - stream_out_write = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_fsm_pp0_stage0 : begin - if ((~((ap_start_int == 1'b0) & (ap_idle_pp0_1to1 == 1'b1)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin - ap_NS_fsm = ap_ST_fsm_pp0_stage1; - end else begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end - end - ap_ST_fsm_pp0_stage1 : begin - if ((1'b0 == ap_block_pp0_stage1_subdone)) begin - ap_NS_fsm = ap_ST_fsm_pp0_stage0; - end else begin - ap_NS_fsm = ap_ST_fsm_pp0_stage1; - end - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -assign a_write_addr_din = {{1'd0}, {sext_ln57_fu_304_p1}}; - -assign a_write_data_din = {{1'd0}, {trunc_ln85_fu_316_p1}}; - -assign add_ln48_fu_250_p0 = k_rd_req_fu_76; - -assign add_ln48_fu_250_p2 = ($signed(add_ln48_fu_250_p0) + $signed(32'd1)); - -assign add_ln62_fu_342_p2 = (zext_ln62_fu_339_p1 + 9'd1); - -assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; - -assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd1]; - -assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage0_01001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & (((1'b0 == a_write_data_full_n) & (ap_predicate_op72_write_state3 == 1'b1)) | ((stream_in_s_empty_n == 1'b0) & (ap_predicate_op69_read_state3 == 1'b1)) | ((1'b0 == a_write_addr_full_n) & (ap_predicate_op68_write_state3 == 1'b1)) | ((stream_out_full_n == 1'b0) & (ap_predicate_op62_write_state3 == 1'b1)))); -end - -always @ (*) begin - ap_block_pp0_stage0_11001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & (((1'b0 == a_write_data_full_n) & (ap_predicate_op72_write_state3 == 1'b1)) | ((stream_in_s_empty_n == 1'b0) & (ap_predicate_op69_read_state3 == 1'b1)) | ((1'b0 == a_write_addr_full_n) & (ap_predicate_op68_write_state3 == 1'b1)) | ((stream_out_full_n == 1'b0) & (ap_predicate_op62_write_state3 == 1'b1)))); -end - -always @ (*) begin - ap_block_pp0_stage0_subdone = ((ap_enable_reg_pp0_iter1 == 1'b1) & (((1'b0 == a_write_data_full_n) & (ap_predicate_op72_write_state3 == 1'b1)) | ((stream_in_s_empty_n == 1'b0) & (ap_predicate_op69_read_state3 == 1'b1)) | ((1'b0 == a_write_addr_full_n) & (ap_predicate_op68_write_state3 == 1'b1)) | ((stream_out_full_n == 1'b0) & (ap_predicate_op62_write_state3 == 1'b1)))); -end - -assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_pp0_stage1_01001 = ((ap_predicate_op53_read_state2 == 1'b1) & (1'b0 == a_write_resp_s_empty_n) & (ap_enable_reg_pp0_iter0 == 1'b1)); -end - -always @ (*) begin - ap_block_pp0_stage1_11001 = ((ap_predicate_op53_read_state2 == 1'b1) & (1'b0 == a_write_resp_s_empty_n) & (ap_enable_reg_pp0_iter0 == 1'b1)); -end - -always @ (*) begin - ap_block_pp0_stage1_subdone = ((ap_predicate_op53_read_state2 == 1'b1) & (1'b0 == a_write_resp_s_empty_n) & (ap_enable_reg_pp0_iter0 == 1'b1)); -end - -assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); - -always @ (*) begin - ap_block_state2_pp0_stage1_iter0 = ((ap_predicate_op53_read_state2 == 1'b1) & (1'b0 == a_write_resp_s_empty_n)); -end - -always @ (*) begin - ap_block_state3_pp0_stage0_iter1 = (((1'b0 == a_write_data_full_n) & (ap_predicate_op72_write_state3 == 1'b1)) | ((stream_in_s_empty_n == 1'b0) & (ap_predicate_op69_read_state3 == 1'b1)) | ((1'b0 == a_write_addr_full_n) & (ap_predicate_op68_write_state3 == 1'b1)) | ((stream_out_full_n == 1'b0) & (ap_predicate_op62_write_state3 == 1'b1))); -end - -always @ (*) begin - ap_condition_400 = ((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_422 == 1'd1) & (or_ln45_reg_418 == 1'd1)); -end - -always @ (*) begin - ap_condition_406 = ((ap_enable_reg_pp0_iter1 == 1'b1) & (tmp_4_reg_435 == 1'd1) & (tmp_3_reg_431 == 1'd1) & (icmp_ln45_reg_414 == 1'd1) & (or_ln45_reg_418 == 1'd1)); -end - -always @ (*) begin - ap_condition_413 = ((ap_enable_reg_pp0_iter1 == 1'b1) & (tmp_6_reg_451 == 1'd1) & (tmp_5_reg_447 == 1'd1) & (tmp_s_reg_443 == 1'd1) & (icmp_ln56_reg_439 == 1'd1) & (or_ln45_reg_418 == 1'd1)); -end - -always @ (*) begin - ap_condition_417 = ((ap_enable_reg_pp0_iter1 == 1'b1) & (tmp_1_reg_455 == 1'd1) & (or_ln45_reg_418 == 1'd1)); -end - -assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); - -assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage1; - -always @ (*) begin - ap_predicate_op53_read_state2 = ((tmp_1_nbreadreq_fu_137_p3 == 1'd1) & (or_ln45_fu_226_p2 == 1'd1)); -end - -always @ (*) begin - ap_predicate_op62_write_state3 = ((tmp_4_reg_435 == 1'd1) & (tmp_3_reg_431 == 1'd1) & (icmp_ln45_reg_414 == 1'd1) & (or_ln45_reg_418 == 1'd1)); -end - -always @ (*) begin - ap_predicate_op68_write_state3 = ((tmp_6_reg_451 == 1'd1) & (tmp_5_reg_447 == 1'd1) & (tmp_s_reg_443 == 1'd1) & (icmp_ln56_reg_439 == 1'd1) & (or_ln45_reg_418 == 1'd1)); -end - -always @ (*) begin - ap_predicate_op69_read_state3 = ((tmp_6_reg_451 == 1'd1) & (tmp_5_reg_447 == 1'd1) & (tmp_s_reg_443 == 1'd1) & (icmp_ln56_reg_439 == 1'd1) & (or_ln45_reg_418 == 1'd1)); -end - -always @ (*) begin - ap_predicate_op72_write_state3 = ((tmp_6_reg_451 == 1'd1) & (tmp_5_reg_447 == 1'd1) & (tmp_s_reg_443 == 1'd1) & (icmp_ln56_reg_439 == 1'd1) & (or_ln45_reg_418 == 1'd1)); -end - -assign b_read_addr_din = {{1'd0}, {sext_ln47_fu_237_p1}}; - -assign icmp_ln45_1_fu_221_p2 = ((k_wr_resp_fu_80 < loop_bound) ? 1'b1 : 1'b0); - -assign icmp_ln45_fu_216_p2 = ((k_rd_resp_fu_72 < loop_bound) ? 1'b1 : 1'b0); - -assign icmp_ln47_fu_232_p0 = k_rd_req_fu_76; - -assign icmp_ln47_fu_232_p2 = ((icmp_ln47_fu_232_p0 < loop_bound) ? 1'b1 : 1'b0); - -assign icmp_ln56_fu_264_p0 = k_wr_req_fu_68; - -assign icmp_ln56_fu_264_p2 = ((icmp_ln56_fu_264_p0 < loop_bound) ? 1'b1 : 1'b0); - -assign k_rd_resp_2_fu_294_p2 = (k_rd_resp_1_reg_404 + 32'd1); - -assign k_wr_req_2_fu_329_p2 = ($signed(k_wr_req_1_reg_398) + $signed(32'd1)); - -assign k_wr_resp_2_fu_352_p2 = (zext_ln62_1_fu_348_p1 + k_wr_resp_1_reg_409); - -assign or_ln45_fu_226_p2 = (icmp_ln45_fu_216_p2 | icmp_ln45_1_fu_221_p2); - -assign select_ln47_fu_256_p0 = b_read_addr_full_n; - -assign select_ln47_fu_256_p2 = k_rd_req_fu_76; - -assign select_ln47_fu_256_p3 = ((select_ln47_fu_256_p0[0:0] == 1'b1) ? add_ln48_fu_250_p2 : select_ln47_fu_256_p2); - -assign sext_ln47_fu_237_p0 = k_rd_req_fu_76; - -assign sext_ln47_fu_237_p1 = sext_ln47_fu_237_p0; - -assign sext_ln57_fu_304_p1 = k_wr_req_1_reg_398; - -assign stream_out_din = {{1'd0}, {trunc_ln104_fu_281_p1}}; - -assign tmp_1_nbreadreq_fu_137_p3 = a_write_resp_s_empty_n; - -assign tmp_3_nbreadreq_fu_97_p3 = b_read_data_s_empty_n; - -assign tmp_5_nbwritereq_fu_121_p3 = a_write_data_full_n; - -assign tmp_6_nbreadreq_fu_129_p3 = stream_in_s_empty_n; - -assign tmp_s_nbwritereq_fu_113_p3 = a_write_addr_full_n; - -assign trunc_ln104_fu_281_p1 = b_read_data_s_dout[511:0]; - -assign trunc_ln85_1_fu_269_p1 = a_write_resp_s_dout[7:0]; - -assign trunc_ln85_fu_316_p1 = stream_in_s_dout[511:0]; - -assign zext_ln62_1_fu_348_p1 = add_ln62_fu_342_p2; - -assign zext_ln62_fu_339_p1 = trunc_ln85_1_reg_459; - -endmodule //inter_kernel_load_Pipeline_VITIS_LOOP_45_1 diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/priority_encoder.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/priority_encoder.v deleted file mode 100644 index cf82512b..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/priority_encoder.v +++ /dev/null @@ -1,92 +0,0 @@ -/* - -Copyright (c) 2014-2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Priority encoder module - */ -module priority_encoder # -( - parameter WIDTH = 4, - // LSB priority selection - parameter LSB_HIGH_PRIORITY = 0 -) -( - input wire [WIDTH-1:0] input_unencoded, - output wire output_valid, - output wire [$clog2(WIDTH)-1:0] output_encoded, - output wire [WIDTH-1:0] output_unencoded -); - -parameter LEVELS = WIDTH > 2 ? $clog2(WIDTH) : 1; -parameter W = 2**LEVELS; - -// pad input to even power of two -wire [W-1:0] input_padded = {{W-WIDTH{1'b0}}, input_unencoded}; - -wire [W/2-1:0] stage_valid[LEVELS-1:0]; -wire [W/2-1:0] stage_enc[LEVELS-1:0]; - -generate - genvar l, n; - - // process input bits; generate valid bit and encoded bit for each pair - for (n = 0; n < W/2; n = n + 1) begin : loop_in - assign stage_valid[0][n] = |input_padded[n*2+1:n*2]; - if (LSB_HIGH_PRIORITY) begin - // bit 0 is highest priority - assign stage_enc[0][n] = !input_padded[n*2+0]; - end else begin - // bit 0 is lowest priority - assign stage_enc[0][n] = input_padded[n*2+1]; - end - end - - // compress down to single valid bit and encoded bus - for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels - for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress - assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2]; - if (LSB_HIGH_PRIORITY) begin - // bit 0 is highest priority - assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]}; - end else begin - // bit 0 is lowest priority - assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]}; - end - end - end -endgenerate - -assign output_valid = stage_valid[LEVELS-1]; -assign output_encoded = stage_enc[LEVELS-1]; -assign output_unencoded = 1 << output_encoded; - -endmodule - -`resetall diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/relay_station.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/relay_station.v deleted file mode 100644 index b2e39be4..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/relay_station.v +++ /dev/null @@ -1,522 +0,0 @@ -`default_nettype none - -// first-word fall-through (FWFT) FIFO that is friendly for floorplanning -module relay_station #( - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 5, - parameter DEPTH = 2, - parameter LEVEL = 2, - parameter CONNECT = 1 // add api to disconnect the relay station -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - - wire full_n [LEVEL:0]; - wire empty_n [LEVEL:0]; - wire [DATA_WIDTH-1:0] data [LEVEL:0]; - - // both full_n and write are registered, thus one level of relay_station cause - // two additional latency for the almost full fifo - parameter GRACE_PERIOD = LEVEL * 2; - parameter REAL_DEPTH = GRACE_PERIOD + DEPTH + 4; - parameter REAL_ADDR_WIDTH = $clog2(REAL_DEPTH); - - genvar i; - generate - if (CONNECT > 0) begin - if (LEVEL > 0) begin - - for (i = 0; i < LEVEL; i = i + 1) begin : inst - if (i < LEVEL - 1) begin - fifo_reg #( - .DATA_WIDTH(DATA_WIDTH) - ) unit ( - .clk(clk), - .reset(reset), - - // connect to fifo[i+1] - .if_empty_n(empty_n[i+1]), - .if_read_ce(if_read_ce), - .if_read (full_n[i+1]), - .if_dout (data[i+1]), - - // connect to fifo[i-1] - .if_full_n (full_n[i]), - .if_write_ce(if_write_ce), - .if_write (empty_n[i]), - .if_din (data[i]) - ); - - end else begin - (* keep = "true" *) fifo_almost_full #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(REAL_ADDR_WIDTH), - .DEPTH(REAL_DEPTH), - .GRACE_PERIOD(GRACE_PERIOD) - ) unit ( - .clk(clk), - .reset(reset), - - // connect to fifo[i+1] - .if_empty_n(empty_n[i+1]), - .if_read_ce(if_read_ce), - .if_read (full_n[i+1]), - .if_dout (data[i+1]), - - // connect to fifo[i-1] - .if_full_n (full_n[i]), - .if_write_ce(if_write_ce), - .if_write (empty_n[i]), - .if_din (data[i]) - ); - end - end - - // write - assign if_full_n = full_n[0]; // output - assign empty_n[0] = if_write & full_n[0]; // input - assign data[0] = if_din; // input - - // read - assign if_empty_n = empty_n[LEVEL]; // output - assign full_n[LEVEL] = if_read; // input - assign if_dout = data[LEVEL]; // output - - end - - // LEVEL == 0 - else begin - assign if_full_n = if_read; // output - assign if_empty_n = if_write; // output - assign if_dout = if_din; // output - end - end - - // disconnect the relay station - else begin - assign if_full_n = 0; // output - assign if_empty_n = 0; // output - // leave the dout port dangling to facilitate pruning - // assign if_dout = 0; // output - end - endgenerate - -endmodule // relay_station - -///////////////////////////////////////////////////////////// - -module fifo_reg #( - parameter DATA_WIDTH = 32 -) ( - input wire clk, - input wire reset, - - // write - (* keep = "true" *) - output reg if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - (* keep = "true" *) - output reg if_empty_n, - input wire if_read_ce, - input wire if_read, - (* keep = "true" *) - output reg [DATA_WIDTH-1:0] if_dout -); - - always @ (posedge clk) begin - if_dout <= if_din; - if_empty_n <= if_write; - if_full_n <= if_read; - end - -endmodule - -///////////////////////////////////////////////////////////////// - -// first-word fall-through (FWFT) FIFO -module fifo_almost_full #( - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 5, - parameter DEPTH = 32, - parameter GRACE_PERIOD = 2 -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - -generate - if (DATA_WIDTH >= 36 && DEPTH >= 4096) begin : uram - fifo_bram_almost_full #( - .MEM_STYLE ("ultra"), - .DATA_WIDTH (DATA_WIDTH), - .ADDR_WIDTH (ADDR_WIDTH), - .DEPTH (DEPTH), - .GRACE_PERIOD(GRACE_PERIOD) - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end else if (DEPTH >= 128) begin : bram - fifo_bram_almost_full #( - .MEM_STYLE ("block"), - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .DEPTH (DEPTH), - .GRACE_PERIOD(GRACE_PERIOD) /*********/ - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end else begin : srl - fifo_srl_almost_full #( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(ADDR_WIDTH), - .DEPTH (DEPTH), - .GRACE_PERIOD(GRACE_PERIOD) /*********/ - ) unit ( - .clk (clk), - .reset(reset), - - .if_full_n (if_full_n), - .if_write_ce(if_write_ce), - .if_write (if_write), - .if_din (if_din), - - .if_empty_n(if_empty_n), - .if_read_ce(if_read_ce), - .if_read (if_read), - .if_dout (if_dout) - ); - end -endgenerate - -endmodule // fifo - -///////////////////////////////////////////////////////////////// - -module fifo_srl_almost_full #( - parameter MEM_STYLE = "shiftreg", - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 4, - parameter DEPTH = 16, - parameter GRACE_PERIOD = 2 -) ( - input wire clk, - input wire reset, - - // write - output wire if_full_n, - input wire if_write_ce, - input wire if_write, - input wire [DATA_WIDTH-1:0] if_din, - - // read - output wire if_empty_n, - input wire if_read_ce, - input wire if_read, - output wire [DATA_WIDTH-1:0] if_dout -); - -parameter REAL_DEPTH = DEPTH < 4 ? 4 : DEPTH; -parameter REAL_ADDR_WIDTH = $clog2(REAL_DEPTH)+1; - -wire[REAL_ADDR_WIDTH - 1:0] shiftReg_addr ; -wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; -wire shiftReg_ce; -reg[REAL_ADDR_WIDTH:0] mOutPtr = ~{(REAL_ADDR_WIDTH+1){1'b0}}; -reg internal_empty_n = 0, internal_full_n = 1; - -assign if_empty_n = internal_empty_n; - -/*******************************************/ -// assign if_full_n = internal_full_n; -reg almost_full_q; -wire almost_full = mOutPtr >= REAL_DEPTH - 1 - GRACE_PERIOD - 1 && mOutPtr != ~{REAL_ADDR_WIDTH+1{1'b0}}; -always @ (posedge clk) almost_full_q <= almost_full; -assign if_full_n = ~almost_full_q; -/*******************************************/ - -assign shiftReg_data = if_din; -assign if_dout = shiftReg_q; - -always @ (posedge clk) begin - if (reset == 1'b1) - begin - mOutPtr <= ~{REAL_ADDR_WIDTH+1{1'b0}}; - internal_empty_n <= 1'b0; - internal_full_n <= 1'b1; - end - else begin - if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && - ((if_write & if_write_ce) == 0 | internal_full_n == 0)) - begin - mOutPtr <= mOutPtr - 5'd1; - if (mOutPtr == 0) - internal_empty_n <= 1'b0; - internal_full_n <= 1'b1; - end - else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && - ((if_write & if_write_ce) == 1 & internal_full_n == 1)) - begin - mOutPtr <= mOutPtr + 5'd1; - internal_empty_n <= 1'b1; - if (mOutPtr == REAL_DEPTH - 5'd2) - internal_full_n <= 1'b0; - end - end -end - -assign shiftReg_addr = mOutPtr[REAL_ADDR_WIDTH] == 1'b0 ? mOutPtr[REAL_ADDR_WIDTH-1:0]:{REAL_ADDR_WIDTH{1'b0}}; -assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; - -fifo_srl_almost_full_internal -#( - .DATA_WIDTH(DATA_WIDTH), - .ADDR_WIDTH(REAL_ADDR_WIDTH), - .DEPTH(REAL_DEPTH)) -U_fifo_w32_d16_A_ram ( - .clk(clk), - .data(shiftReg_data), - .ce(shiftReg_ce), - .a(shiftReg_addr), - .q(shiftReg_q)); - -endmodule - -module fifo_srl_almost_full_internal ( - input wire clk, - input wire [DATA_WIDTH-1:0] data, - input wire ce, - input wire [ADDR_WIDTH-1:0] a, - output wire [DATA_WIDTH-1:0] q -); - -parameter DATA_WIDTH = 32'd32; -parameter ADDR_WIDTH = 32'd4; -parameter DEPTH = 5'd16; - -(* shreg_extract = "yes" *) reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1]; -integer i; - -always @ (posedge clk) - begin - if (ce) - begin - for (i=0;i= DEPTH - 1 - GRACE_PERIOD); -//assign if_full_n = full_n; -assign if_full_n = ~almost_full; -/**************************************/ - -assign if_empty_n = dout_valid; -assign if_dout = dout_buf; -assign push = full_n & if_write_ce & if_write; -assign pop = empty_n & if_read_ce & (~dout_valid | if_read); -assign wnext = !push ? waddr : - (waddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : waddr + 1'd1; -assign rnext = !pop ? raddr : - (raddr == DepthM1) ? {ADDR_WIDTH{1'b0}} : raddr + 1'd1; - - - -// waddr -always @(posedge clk) begin - if (reset) - waddr <= {ADDR_WIDTH{1'b0}}; - else - waddr <= wnext; -end - -// raddr -always @(posedge clk) begin - if (reset) - raddr <= {ADDR_WIDTH{1'b0}}; - else - raddr <= rnext; -end - -// used -always @(posedge clk) begin - if (reset) - used <= {ADDR_WIDTH{1'b0}}; - else if (push && !pop) - used <= used + 1'b1; - else if (!push && pop) - used <= used - 1'b1; -end - -// full_n -always @(posedge clk) begin - if (reset) - full_n <= 1'b1; - else if (push && !pop) - full_n <= (used != DepthM1); - else if (!push && pop) - full_n <= 1'b1; -end - -// empty_n -always @(posedge clk) begin - if (reset) - empty_n <= 1'b0; - else if (push && !pop) - empty_n <= 1'b1; - else if (!push && pop) - empty_n <= (used != {{(ADDR_WIDTH-1){1'b0}},1'b1}); -end - -// mem -always @(posedge clk) begin - if (push) - mem[waddr] <= if_din; -end - -// q_buf -always @(posedge clk) begin - q_buf <= mem[rnext]; -end - -// q_tmp -always @(posedge clk) begin - if (reset) - q_tmp <= {DATA_WIDTH{1'b0}}; - else if (push) - q_tmp <= if_din; -end - -// show_ahead -always @(posedge clk) begin - if (reset) - show_ahead <= 1'b0; - else if (push && used == {{(ADDR_WIDTH-1){1'b0}},pop}) - show_ahead <= 1'b1; - else - show_ahead <= 1'b0; -end - -// dout_buf -always @(posedge clk) begin - if (reset) - dout_buf <= {DATA_WIDTH{1'b0}}; - else if (pop) - dout_buf <= show_ahead? q_tmp : q_buf; -end - -// dout_valid -always @(posedge clk) begin - if (reset) - dout_valid <= 1'b0; - else if (pop) - dout_valid <= 1'b1; - else if (if_read_ce & if_read) - dout_valid <= 1'b0; -end - -endmodule // fifo_bram - -`default_nettype wire diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/unikernel.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/unikernel.v deleted file mode 100644 index a382c8ad..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/unikernel.v +++ /dev/null @@ -1,5943 +0,0 @@ -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO = "unikernel_unikernel,hls_ip_2022_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcu280-fsvh2892-2L-e,HLS_INPUT_CLOCK=3.330000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.000000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=1754,HLS_SYN_LUT=3176,HLS_VERSION=2022_2}" *) - - -module unikernel -( - s_axi_control_AWVALID, - s_axi_control_AWREADY, - s_axi_control_AWADDR, - s_axi_control_WVALID, - s_axi_control_WREADY, - s_axi_control_WDATA, - s_axi_control_WSTRB, - s_axi_control_ARVALID, - s_axi_control_ARREADY, - s_axi_control_ARADDR, - s_axi_control_RVALID, - s_axi_control_RREADY, - s_axi_control_RDATA, - s_axi_control_RRESP, - s_axi_control_BVALID, - s_axi_control_BREADY, - s_axi_control_BRESP, - ap_clk, - ap_rst_n, - interrupt, - m_axi_in_0_ARADDR, - m_axi_in_0_ARBURST, - m_axi_in_0_ARCACHE, - m_axi_in_0_ARID, - m_axi_in_0_ARLEN, - m_axi_in_0_ARLOCK, - m_axi_in_0_ARPROT, - m_axi_in_0_ARQOS, - m_axi_in_0_ARREADY, - m_axi_in_0_ARSIZE, - m_axi_in_0_ARVALID, - m_axi_in_0_AWADDR, - m_axi_in_0_AWBURST, - m_axi_in_0_AWCACHE, - m_axi_in_0_AWID, - m_axi_in_0_AWLEN, - m_axi_in_0_AWLOCK, - m_axi_in_0_AWPROT, - m_axi_in_0_AWQOS, - m_axi_in_0_AWREADY, - m_axi_in_0_AWSIZE, - m_axi_in_0_AWVALID, - m_axi_in_0_BID, - m_axi_in_0_BREADY, - m_axi_in_0_BRESP, - m_axi_in_0_BVALID, - m_axi_in_0_RDATA, - m_axi_in_0_RID, - m_axi_in_0_RLAST, - m_axi_in_0_RREADY, - m_axi_in_0_RRESP, - m_axi_in_0_RVALID, - m_axi_in_0_WDATA, - m_axi_in_0_WLAST, - m_axi_in_0_WREADY, - m_axi_in_0_WSTRB, - m_axi_in_0_WVALID, - m_axi_out_0_ARADDR, - m_axi_out_0_ARBURST, - m_axi_out_0_ARCACHE, - m_axi_out_0_ARID, - m_axi_out_0_ARLEN, - m_axi_out_0_ARLOCK, - m_axi_out_0_ARPROT, - m_axi_out_0_ARQOS, - m_axi_out_0_ARREADY, - m_axi_out_0_ARSIZE, - m_axi_out_0_ARVALID, - m_axi_out_0_AWADDR, - m_axi_out_0_AWBURST, - m_axi_out_0_AWCACHE, - m_axi_out_0_AWID, - m_axi_out_0_AWLEN, - m_axi_out_0_AWLOCK, - m_axi_out_0_AWPROT, - m_axi_out_0_AWQOS, - m_axi_out_0_AWREADY, - m_axi_out_0_AWSIZE, - m_axi_out_0_AWVALID, - m_axi_out_0_BID, - m_axi_out_0_BREADY, - m_axi_out_0_BRESP, - m_axi_out_0_BVALID, - m_axi_out_0_RDATA, - m_axi_out_0_RID, - m_axi_out_0_RLAST, - m_axi_out_0_RREADY, - m_axi_out_0_RRESP, - m_axi_out_0_RVALID, - m_axi_out_0_WDATA, - m_axi_out_0_WLAST, - m_axi_out_0_WREADY, - m_axi_out_0_WSTRB, - m_axi_out_0_WVALID, - m_axi_in_1_ARADDR, - m_axi_in_1_ARBURST, - m_axi_in_1_ARCACHE, - m_axi_in_1_ARID, - m_axi_in_1_ARLEN, - m_axi_in_1_ARLOCK, - m_axi_in_1_ARPROT, - m_axi_in_1_ARQOS, - m_axi_in_1_ARREADY, - m_axi_in_1_ARSIZE, - m_axi_in_1_ARVALID, - m_axi_in_1_AWADDR, - m_axi_in_1_AWBURST, - m_axi_in_1_AWCACHE, - m_axi_in_1_AWID, - m_axi_in_1_AWLEN, - m_axi_in_1_AWLOCK, - m_axi_in_1_AWPROT, - m_axi_in_1_AWQOS, - m_axi_in_1_AWREADY, - m_axi_in_1_AWSIZE, - m_axi_in_1_AWVALID, - m_axi_in_1_BID, - m_axi_in_1_BREADY, - m_axi_in_1_BRESP, - m_axi_in_1_BVALID, - m_axi_in_1_RDATA, - m_axi_in_1_RID, - m_axi_in_1_RLAST, - m_axi_in_1_RREADY, - m_axi_in_1_RRESP, - m_axi_in_1_RVALID, - m_axi_in_1_WDATA, - m_axi_in_1_WLAST, - m_axi_in_1_WREADY, - m_axi_in_1_WSTRB, - m_axi_in_1_WVALID, - m_axi_out_1_ARADDR, - m_axi_out_1_ARBURST, - m_axi_out_1_ARCACHE, - m_axi_out_1_ARID, - m_axi_out_1_ARLEN, - m_axi_out_1_ARLOCK, - m_axi_out_1_ARPROT, - m_axi_out_1_ARQOS, - m_axi_out_1_ARREADY, - m_axi_out_1_ARSIZE, - m_axi_out_1_ARVALID, - m_axi_out_1_AWADDR, - m_axi_out_1_AWBURST, - m_axi_out_1_AWCACHE, - m_axi_out_1_AWID, - m_axi_out_1_AWLEN, - m_axi_out_1_AWLOCK, - m_axi_out_1_AWPROT, - m_axi_out_1_AWQOS, - m_axi_out_1_AWREADY, - m_axi_out_1_AWSIZE, - m_axi_out_1_AWVALID, - m_axi_out_1_BID, - m_axi_out_1_BREADY, - m_axi_out_1_BRESP, - m_axi_out_1_BVALID, - m_axi_out_1_RDATA, - m_axi_out_1_RID, - m_axi_out_1_RLAST, - m_axi_out_1_RREADY, - m_axi_out_1_RRESP, - m_axi_out_1_RVALID, - m_axi_out_1_WDATA, - m_axi_out_1_WLAST, - m_axi_out_1_WREADY, - m_axi_out_1_WSTRB, - m_axi_out_1_WVALID, - m_axi_in_2_ARADDR, - m_axi_in_2_ARBURST, - m_axi_in_2_ARCACHE, - m_axi_in_2_ARID, - m_axi_in_2_ARLEN, - m_axi_in_2_ARLOCK, - m_axi_in_2_ARPROT, - m_axi_in_2_ARQOS, - m_axi_in_2_ARREADY, - m_axi_in_2_ARSIZE, - m_axi_in_2_ARVALID, - m_axi_in_2_AWADDR, - m_axi_in_2_AWBURST, - m_axi_in_2_AWCACHE, - m_axi_in_2_AWID, - m_axi_in_2_AWLEN, - m_axi_in_2_AWLOCK, - m_axi_in_2_AWPROT, - m_axi_in_2_AWQOS, - m_axi_in_2_AWREADY, - m_axi_in_2_AWSIZE, - m_axi_in_2_AWVALID, - m_axi_in_2_BID, - m_axi_in_2_BREADY, - m_axi_in_2_BRESP, - m_axi_in_2_BVALID, - m_axi_in_2_RDATA, - m_axi_in_2_RID, - m_axi_in_2_RLAST, - m_axi_in_2_RREADY, - m_axi_in_2_RRESP, - m_axi_in_2_RVALID, - m_axi_in_2_WDATA, - m_axi_in_2_WLAST, - m_axi_in_2_WREADY, - m_axi_in_2_WSTRB, - m_axi_in_2_WVALID, - m_axi_out_2_ARADDR, - m_axi_out_2_ARBURST, - m_axi_out_2_ARCACHE, - m_axi_out_2_ARID, - m_axi_out_2_ARLEN, - m_axi_out_2_ARLOCK, - m_axi_out_2_ARPROT, - m_axi_out_2_ARQOS, - m_axi_out_2_ARREADY, - m_axi_out_2_ARSIZE, - m_axi_out_2_ARVALID, - m_axi_out_2_AWADDR, - m_axi_out_2_AWBURST, - m_axi_out_2_AWCACHE, - m_axi_out_2_AWID, - m_axi_out_2_AWLEN, - m_axi_out_2_AWLOCK, - m_axi_out_2_AWPROT, - m_axi_out_2_AWQOS, - m_axi_out_2_AWREADY, - m_axi_out_2_AWSIZE, - m_axi_out_2_AWVALID, - m_axi_out_2_BID, - m_axi_out_2_BREADY, - m_axi_out_2_BRESP, - m_axi_out_2_BVALID, - m_axi_out_2_RDATA, - m_axi_out_2_RID, - m_axi_out_2_RLAST, - m_axi_out_2_RREADY, - m_axi_out_2_RRESP, - m_axi_out_2_RVALID, - m_axi_out_2_WDATA, - m_axi_out_2_WLAST, - m_axi_out_2_WREADY, - m_axi_out_2_WSTRB, - m_axi_out_2_WVALID, - m_axi_in_3_ARADDR, - m_axi_in_3_ARBURST, - m_axi_in_3_ARCACHE, - m_axi_in_3_ARID, - m_axi_in_3_ARLEN, - m_axi_in_3_ARLOCK, - m_axi_in_3_ARPROT, - m_axi_in_3_ARQOS, - m_axi_in_3_ARREADY, - m_axi_in_3_ARSIZE, - m_axi_in_3_ARVALID, - m_axi_in_3_AWADDR, - m_axi_in_3_AWBURST, - m_axi_in_3_AWCACHE, - m_axi_in_3_AWID, - m_axi_in_3_AWLEN, - m_axi_in_3_AWLOCK, - m_axi_in_3_AWPROT, - m_axi_in_3_AWQOS, - m_axi_in_3_AWREADY, - m_axi_in_3_AWSIZE, - m_axi_in_3_AWVALID, - m_axi_in_3_BID, - m_axi_in_3_BREADY, - m_axi_in_3_BRESP, - m_axi_in_3_BVALID, - m_axi_in_3_RDATA, - m_axi_in_3_RID, - m_axi_in_3_RLAST, - m_axi_in_3_RREADY, - m_axi_in_3_RRESP, - m_axi_in_3_RVALID, - m_axi_in_3_WDATA, - m_axi_in_3_WLAST, - m_axi_in_3_WREADY, - m_axi_in_3_WSTRB, - m_axi_in_3_WVALID, - m_axi_out_3_ARADDR, - m_axi_out_3_ARBURST, - m_axi_out_3_ARCACHE, - m_axi_out_3_ARID, - m_axi_out_3_ARLEN, - m_axi_out_3_ARLOCK, - m_axi_out_3_ARPROT, - m_axi_out_3_ARQOS, - m_axi_out_3_ARREADY, - m_axi_out_3_ARSIZE, - m_axi_out_3_ARVALID, - m_axi_out_3_AWADDR, - m_axi_out_3_AWBURST, - m_axi_out_3_AWCACHE, - m_axi_out_3_AWID, - m_axi_out_3_AWLEN, - m_axi_out_3_AWLOCK, - m_axi_out_3_AWPROT, - m_axi_out_3_AWQOS, - m_axi_out_3_AWREADY, - m_axi_out_3_AWSIZE, - m_axi_out_3_AWVALID, - m_axi_out_3_BID, - m_axi_out_3_BREADY, - m_axi_out_3_BRESP, - m_axi_out_3_BVALID, - m_axi_out_3_RDATA, - m_axi_out_3_RID, - m_axi_out_3_RLAST, - m_axi_out_3_RREADY, - m_axi_out_3_RRESP, - m_axi_out_3_RVALID, - m_axi_out_3_WDATA, - m_axi_out_3_WLAST, - m_axi_out_3_WREADY, - m_axi_out_3_WSTRB, - m_axi_out_3_WVALID, - m_axi_in_4_ARADDR, - m_axi_in_4_ARBURST, - m_axi_in_4_ARCACHE, - m_axi_in_4_ARID, - m_axi_in_4_ARLEN, - m_axi_in_4_ARLOCK, - m_axi_in_4_ARPROT, - m_axi_in_4_ARQOS, - m_axi_in_4_ARREADY, - m_axi_in_4_ARSIZE, - m_axi_in_4_ARVALID, - m_axi_in_4_AWADDR, - m_axi_in_4_AWBURST, - m_axi_in_4_AWCACHE, - m_axi_in_4_AWID, - m_axi_in_4_AWLEN, - m_axi_in_4_AWLOCK, - m_axi_in_4_AWPROT, - m_axi_in_4_AWQOS, - m_axi_in_4_AWREADY, - m_axi_in_4_AWSIZE, - m_axi_in_4_AWVALID, - m_axi_in_4_BID, - m_axi_in_4_BREADY, - m_axi_in_4_BRESP, - m_axi_in_4_BVALID, - m_axi_in_4_RDATA, - m_axi_in_4_RID, - m_axi_in_4_RLAST, - m_axi_in_4_RREADY, - m_axi_in_4_RRESP, - m_axi_in_4_RVALID, - m_axi_in_4_WDATA, - m_axi_in_4_WLAST, - m_axi_in_4_WREADY, - m_axi_in_4_WSTRB, - m_axi_in_4_WVALID, - m_axi_out_4_ARADDR, - m_axi_out_4_ARBURST, - m_axi_out_4_ARCACHE, - m_axi_out_4_ARID, - m_axi_out_4_ARLEN, - m_axi_out_4_ARLOCK, - m_axi_out_4_ARPROT, - m_axi_out_4_ARQOS, - m_axi_out_4_ARREADY, - m_axi_out_4_ARSIZE, - m_axi_out_4_ARVALID, - m_axi_out_4_AWADDR, - m_axi_out_4_AWBURST, - m_axi_out_4_AWCACHE, - m_axi_out_4_AWID, - m_axi_out_4_AWLEN, - m_axi_out_4_AWLOCK, - m_axi_out_4_AWPROT, - m_axi_out_4_AWQOS, - m_axi_out_4_AWREADY, - m_axi_out_4_AWSIZE, - m_axi_out_4_AWVALID, - m_axi_out_4_BID, - m_axi_out_4_BREADY, - m_axi_out_4_BRESP, - m_axi_out_4_BVALID, - m_axi_out_4_RDATA, - m_axi_out_4_RID, - m_axi_out_4_RLAST, - m_axi_out_4_RREADY, - m_axi_out_4_RRESP, - m_axi_out_4_RVALID, - m_axi_out_4_WDATA, - m_axi_out_4_WLAST, - m_axi_out_4_WREADY, - m_axi_out_4_WSTRB, - m_axi_out_4_WVALID, - m_axi_in_5_ARADDR, - m_axi_in_5_ARBURST, - m_axi_in_5_ARCACHE, - m_axi_in_5_ARID, - m_axi_in_5_ARLEN, - m_axi_in_5_ARLOCK, - m_axi_in_5_ARPROT, - m_axi_in_5_ARQOS, - m_axi_in_5_ARREADY, - m_axi_in_5_ARSIZE, - m_axi_in_5_ARVALID, - m_axi_in_5_AWADDR, - m_axi_in_5_AWBURST, - m_axi_in_5_AWCACHE, - m_axi_in_5_AWID, - m_axi_in_5_AWLEN, - m_axi_in_5_AWLOCK, - m_axi_in_5_AWPROT, - m_axi_in_5_AWQOS, - m_axi_in_5_AWREADY, - m_axi_in_5_AWSIZE, - m_axi_in_5_AWVALID, - m_axi_in_5_BID, - m_axi_in_5_BREADY, - m_axi_in_5_BRESP, - m_axi_in_5_BVALID, - m_axi_in_5_RDATA, - m_axi_in_5_RID, - m_axi_in_5_RLAST, - m_axi_in_5_RREADY, - m_axi_in_5_RRESP, - m_axi_in_5_RVALID, - m_axi_in_5_WDATA, - m_axi_in_5_WLAST, - m_axi_in_5_WREADY, - m_axi_in_5_WSTRB, - m_axi_in_5_WVALID, - m_axi_out_5_ARADDR, - m_axi_out_5_ARBURST, - m_axi_out_5_ARCACHE, - m_axi_out_5_ARID, - m_axi_out_5_ARLEN, - m_axi_out_5_ARLOCK, - m_axi_out_5_ARPROT, - m_axi_out_5_ARQOS, - m_axi_out_5_ARREADY, - m_axi_out_5_ARSIZE, - m_axi_out_5_ARVALID, - m_axi_out_5_AWADDR, - m_axi_out_5_AWBURST, - m_axi_out_5_AWCACHE, - m_axi_out_5_AWID, - m_axi_out_5_AWLEN, - m_axi_out_5_AWLOCK, - m_axi_out_5_AWPROT, - m_axi_out_5_AWQOS, - m_axi_out_5_AWREADY, - m_axi_out_5_AWSIZE, - m_axi_out_5_AWVALID, - m_axi_out_5_BID, - m_axi_out_5_BREADY, - m_axi_out_5_BRESP, - m_axi_out_5_BVALID, - m_axi_out_5_RDATA, - m_axi_out_5_RID, - m_axi_out_5_RLAST, - m_axi_out_5_RREADY, - m_axi_out_5_RRESP, - m_axi_out_5_RVALID, - m_axi_out_5_WDATA, - m_axi_out_5_WLAST, - m_axi_out_5_WREADY, - m_axi_out_5_WSTRB, - m_axi_out_5_WVALID, - m_axi_in_6_ARADDR, - m_axi_in_6_ARBURST, - m_axi_in_6_ARCACHE, - m_axi_in_6_ARID, - m_axi_in_6_ARLEN, - m_axi_in_6_ARLOCK, - m_axi_in_6_ARPROT, - m_axi_in_6_ARQOS, - m_axi_in_6_ARREADY, - m_axi_in_6_ARSIZE, - m_axi_in_6_ARVALID, - m_axi_in_6_AWADDR, - m_axi_in_6_AWBURST, - m_axi_in_6_AWCACHE, - m_axi_in_6_AWID, - m_axi_in_6_AWLEN, - m_axi_in_6_AWLOCK, - m_axi_in_6_AWPROT, - m_axi_in_6_AWQOS, - m_axi_in_6_AWREADY, - m_axi_in_6_AWSIZE, - m_axi_in_6_AWVALID, - m_axi_in_6_BID, - m_axi_in_6_BREADY, - m_axi_in_6_BRESP, - m_axi_in_6_BVALID, - m_axi_in_6_RDATA, - m_axi_in_6_RID, - m_axi_in_6_RLAST, - m_axi_in_6_RREADY, - m_axi_in_6_RRESP, - m_axi_in_6_RVALID, - m_axi_in_6_WDATA, - m_axi_in_6_WLAST, - m_axi_in_6_WREADY, - m_axi_in_6_WSTRB, - m_axi_in_6_WVALID, - m_axi_out_6_ARADDR, - m_axi_out_6_ARBURST, - m_axi_out_6_ARCACHE, - m_axi_out_6_ARID, - m_axi_out_6_ARLEN, - m_axi_out_6_ARLOCK, - m_axi_out_6_ARPROT, - m_axi_out_6_ARQOS, - m_axi_out_6_ARREADY, - m_axi_out_6_ARSIZE, - m_axi_out_6_ARVALID, - m_axi_out_6_AWADDR, - m_axi_out_6_AWBURST, - m_axi_out_6_AWCACHE, - m_axi_out_6_AWID, - m_axi_out_6_AWLEN, - m_axi_out_6_AWLOCK, - m_axi_out_6_AWPROT, - m_axi_out_6_AWQOS, - m_axi_out_6_AWREADY, - m_axi_out_6_AWSIZE, - m_axi_out_6_AWVALID, - m_axi_out_6_BID, - m_axi_out_6_BREADY, - m_axi_out_6_BRESP, - m_axi_out_6_BVALID, - m_axi_out_6_RDATA, - m_axi_out_6_RID, - m_axi_out_6_RLAST, - m_axi_out_6_RREADY, - m_axi_out_6_RRESP, - m_axi_out_6_RVALID, - m_axi_out_6_WDATA, - m_axi_out_6_WLAST, - m_axi_out_6_WREADY, - m_axi_out_6_WSTRB, - m_axi_out_6_WVALID, - m_axi_in_7_ARADDR, - m_axi_in_7_ARBURST, - m_axi_in_7_ARCACHE, - m_axi_in_7_ARID, - m_axi_in_7_ARLEN, - m_axi_in_7_ARLOCK, - m_axi_in_7_ARPROT, - m_axi_in_7_ARQOS, - m_axi_in_7_ARREADY, - m_axi_in_7_ARSIZE, - m_axi_in_7_ARVALID, - m_axi_in_7_AWADDR, - m_axi_in_7_AWBURST, - m_axi_in_7_AWCACHE, - m_axi_in_7_AWID, - m_axi_in_7_AWLEN, - m_axi_in_7_AWLOCK, - m_axi_in_7_AWPROT, - m_axi_in_7_AWQOS, - m_axi_in_7_AWREADY, - m_axi_in_7_AWSIZE, - m_axi_in_7_AWVALID, - m_axi_in_7_BID, - m_axi_in_7_BREADY, - m_axi_in_7_BRESP, - m_axi_in_7_BVALID, - m_axi_in_7_RDATA, - m_axi_in_7_RID, - m_axi_in_7_RLAST, - m_axi_in_7_RREADY, - m_axi_in_7_RRESP, - m_axi_in_7_RVALID, - m_axi_in_7_WDATA, - m_axi_in_7_WLAST, - m_axi_in_7_WREADY, - m_axi_in_7_WSTRB, - m_axi_in_7_WVALID, - m_axi_out_7_ARADDR, - m_axi_out_7_ARBURST, - m_axi_out_7_ARCACHE, - m_axi_out_7_ARID, - m_axi_out_7_ARLEN, - m_axi_out_7_ARLOCK, - m_axi_out_7_ARPROT, - m_axi_out_7_ARQOS, - m_axi_out_7_ARREADY, - m_axi_out_7_ARSIZE, - m_axi_out_7_ARVALID, - m_axi_out_7_AWADDR, - m_axi_out_7_AWBURST, - m_axi_out_7_AWCACHE, - m_axi_out_7_AWID, - m_axi_out_7_AWLEN, - m_axi_out_7_AWLOCK, - m_axi_out_7_AWPROT, - m_axi_out_7_AWQOS, - m_axi_out_7_AWREADY, - m_axi_out_7_AWSIZE, - m_axi_out_7_AWVALID, - m_axi_out_7_BID, - m_axi_out_7_BREADY, - m_axi_out_7_BRESP, - m_axi_out_7_BVALID, - m_axi_out_7_RDATA, - m_axi_out_7_RID, - m_axi_out_7_RLAST, - m_axi_out_7_RREADY, - m_axi_out_7_RRESP, - m_axi_out_7_RVALID, - m_axi_out_7_WDATA, - m_axi_out_7_WLAST, - m_axi_out_7_WREADY, - m_axi_out_7_WSTRB, - m_axi_out_7_WVALID, - m_axi_in_8_ARADDR, - m_axi_in_8_ARBURST, - m_axi_in_8_ARCACHE, - m_axi_in_8_ARID, - m_axi_in_8_ARLEN, - m_axi_in_8_ARLOCK, - m_axi_in_8_ARPROT, - m_axi_in_8_ARQOS, - m_axi_in_8_ARREADY, - m_axi_in_8_ARSIZE, - m_axi_in_8_ARVALID, - m_axi_in_8_AWADDR, - m_axi_in_8_AWBURST, - m_axi_in_8_AWCACHE, - m_axi_in_8_AWID, - m_axi_in_8_AWLEN, - m_axi_in_8_AWLOCK, - m_axi_in_8_AWPROT, - m_axi_in_8_AWQOS, - m_axi_in_8_AWREADY, - m_axi_in_8_AWSIZE, - m_axi_in_8_AWVALID, - m_axi_in_8_BID, - m_axi_in_8_BREADY, - m_axi_in_8_BRESP, - m_axi_in_8_BVALID, - m_axi_in_8_RDATA, - m_axi_in_8_RID, - m_axi_in_8_RLAST, - m_axi_in_8_RREADY, - m_axi_in_8_RRESP, - m_axi_in_8_RVALID, - m_axi_in_8_WDATA, - m_axi_in_8_WLAST, - m_axi_in_8_WREADY, - m_axi_in_8_WSTRB, - m_axi_in_8_WVALID, - m_axi_out_8_ARADDR, - m_axi_out_8_ARBURST, - m_axi_out_8_ARCACHE, - m_axi_out_8_ARID, - m_axi_out_8_ARLEN, - m_axi_out_8_ARLOCK, - m_axi_out_8_ARPROT, - m_axi_out_8_ARQOS, - m_axi_out_8_ARREADY, - m_axi_out_8_ARSIZE, - m_axi_out_8_ARVALID, - m_axi_out_8_AWADDR, - m_axi_out_8_AWBURST, - m_axi_out_8_AWCACHE, - m_axi_out_8_AWID, - m_axi_out_8_AWLEN, - m_axi_out_8_AWLOCK, - m_axi_out_8_AWPROT, - m_axi_out_8_AWQOS, - m_axi_out_8_AWREADY, - m_axi_out_8_AWSIZE, - m_axi_out_8_AWVALID, - m_axi_out_8_BID, - m_axi_out_8_BREADY, - m_axi_out_8_BRESP, - m_axi_out_8_BVALID, - m_axi_out_8_RDATA, - m_axi_out_8_RID, - m_axi_out_8_RLAST, - m_axi_out_8_RREADY, - m_axi_out_8_RRESP, - m_axi_out_8_RVALID, - m_axi_out_8_WDATA, - m_axi_out_8_WLAST, - m_axi_out_8_WREADY, - m_axi_out_8_WSTRB, - m_axi_out_8_WVALID, - m_axi_in_9_ARADDR, - m_axi_in_9_ARBURST, - m_axi_in_9_ARCACHE, - m_axi_in_9_ARID, - m_axi_in_9_ARLEN, - m_axi_in_9_ARLOCK, - m_axi_in_9_ARPROT, - m_axi_in_9_ARQOS, - m_axi_in_9_ARREADY, - m_axi_in_9_ARSIZE, - m_axi_in_9_ARVALID, - m_axi_in_9_AWADDR, - m_axi_in_9_AWBURST, - m_axi_in_9_AWCACHE, - m_axi_in_9_AWID, - m_axi_in_9_AWLEN, - m_axi_in_9_AWLOCK, - m_axi_in_9_AWPROT, - m_axi_in_9_AWQOS, - m_axi_in_9_AWREADY, - m_axi_in_9_AWSIZE, - m_axi_in_9_AWVALID, - m_axi_in_9_BID, - m_axi_in_9_BREADY, - m_axi_in_9_BRESP, - m_axi_in_9_BVALID, - m_axi_in_9_RDATA, - m_axi_in_9_RID, - m_axi_in_9_RLAST, - m_axi_in_9_RREADY, - m_axi_in_9_RRESP, - m_axi_in_9_RVALID, - m_axi_in_9_WDATA, - m_axi_in_9_WLAST, - m_axi_in_9_WREADY, - m_axi_in_9_WSTRB, - m_axi_in_9_WVALID, - m_axi_out_9_ARADDR, - m_axi_out_9_ARBURST, - m_axi_out_9_ARCACHE, - m_axi_out_9_ARID, - m_axi_out_9_ARLEN, - m_axi_out_9_ARLOCK, - m_axi_out_9_ARPROT, - m_axi_out_9_ARQOS, - m_axi_out_9_ARREADY, - m_axi_out_9_ARSIZE, - m_axi_out_9_ARVALID, - m_axi_out_9_AWADDR, - m_axi_out_9_AWBURST, - m_axi_out_9_AWCACHE, - m_axi_out_9_AWID, - m_axi_out_9_AWLEN, - m_axi_out_9_AWLOCK, - m_axi_out_9_AWPROT, - m_axi_out_9_AWQOS, - m_axi_out_9_AWREADY, - m_axi_out_9_AWSIZE, - m_axi_out_9_AWVALID, - m_axi_out_9_BID, - m_axi_out_9_BREADY, - m_axi_out_9_BRESP, - m_axi_out_9_BVALID, - m_axi_out_9_RDATA, - m_axi_out_9_RID, - m_axi_out_9_RLAST, - m_axi_out_9_RREADY, - m_axi_out_9_RRESP, - m_axi_out_9_RVALID, - m_axi_out_9_WDATA, - m_axi_out_9_WLAST, - m_axi_out_9_WREADY, - m_axi_out_9_WSTRB, - m_axi_out_9_WVALID, - m_axi_in_10_ARADDR, - m_axi_in_10_ARBURST, - m_axi_in_10_ARCACHE, - m_axi_in_10_ARID, - m_axi_in_10_ARLEN, - m_axi_in_10_ARLOCK, - m_axi_in_10_ARPROT, - m_axi_in_10_ARQOS, - m_axi_in_10_ARREADY, - m_axi_in_10_ARSIZE, - m_axi_in_10_ARVALID, - m_axi_in_10_AWADDR, - m_axi_in_10_AWBURST, - m_axi_in_10_AWCACHE, - m_axi_in_10_AWID, - m_axi_in_10_AWLEN, - m_axi_in_10_AWLOCK, - m_axi_in_10_AWPROT, - m_axi_in_10_AWQOS, - m_axi_in_10_AWREADY, - m_axi_in_10_AWSIZE, - m_axi_in_10_AWVALID, - m_axi_in_10_BID, - m_axi_in_10_BREADY, - m_axi_in_10_BRESP, - m_axi_in_10_BVALID, - m_axi_in_10_RDATA, - m_axi_in_10_RID, - m_axi_in_10_RLAST, - m_axi_in_10_RREADY, - m_axi_in_10_RRESP, - m_axi_in_10_RVALID, - m_axi_in_10_WDATA, - m_axi_in_10_WLAST, - m_axi_in_10_WREADY, - m_axi_in_10_WSTRB, - m_axi_in_10_WVALID, - m_axi_out_10_ARADDR, - m_axi_out_10_ARBURST, - m_axi_out_10_ARCACHE, - m_axi_out_10_ARID, - m_axi_out_10_ARLEN, - m_axi_out_10_ARLOCK, - m_axi_out_10_ARPROT, - m_axi_out_10_ARQOS, - m_axi_out_10_ARREADY, - m_axi_out_10_ARSIZE, - m_axi_out_10_ARVALID, - m_axi_out_10_AWADDR, - m_axi_out_10_AWBURST, - m_axi_out_10_AWCACHE, - m_axi_out_10_AWID, - m_axi_out_10_AWLEN, - m_axi_out_10_AWLOCK, - m_axi_out_10_AWPROT, - m_axi_out_10_AWQOS, - m_axi_out_10_AWREADY, - m_axi_out_10_AWSIZE, - m_axi_out_10_AWVALID, - m_axi_out_10_BID, - m_axi_out_10_BREADY, - m_axi_out_10_BRESP, - m_axi_out_10_BVALID, - m_axi_out_10_RDATA, - m_axi_out_10_RID, - m_axi_out_10_RLAST, - m_axi_out_10_RREADY, - m_axi_out_10_RRESP, - m_axi_out_10_RVALID, - m_axi_out_10_WDATA, - m_axi_out_10_WLAST, - m_axi_out_10_WREADY, - m_axi_out_10_WSTRB, - m_axi_out_10_WVALID, - m_axi_in_11_ARADDR, - m_axi_in_11_ARBURST, - m_axi_in_11_ARCACHE, - m_axi_in_11_ARID, - m_axi_in_11_ARLEN, - m_axi_in_11_ARLOCK, - m_axi_in_11_ARPROT, - m_axi_in_11_ARQOS, - m_axi_in_11_ARREADY, - m_axi_in_11_ARSIZE, - m_axi_in_11_ARVALID, - m_axi_in_11_AWADDR, - m_axi_in_11_AWBURST, - m_axi_in_11_AWCACHE, - m_axi_in_11_AWID, - m_axi_in_11_AWLEN, - m_axi_in_11_AWLOCK, - m_axi_in_11_AWPROT, - m_axi_in_11_AWQOS, - m_axi_in_11_AWREADY, - m_axi_in_11_AWSIZE, - m_axi_in_11_AWVALID, - m_axi_in_11_BID, - m_axi_in_11_BREADY, - m_axi_in_11_BRESP, - m_axi_in_11_BVALID, - m_axi_in_11_RDATA, - m_axi_in_11_RID, - m_axi_in_11_RLAST, - m_axi_in_11_RREADY, - m_axi_in_11_RRESP, - m_axi_in_11_RVALID, - m_axi_in_11_WDATA, - m_axi_in_11_WLAST, - m_axi_in_11_WREADY, - m_axi_in_11_WSTRB, - m_axi_in_11_WVALID, - m_axi_out_11_ARADDR, - m_axi_out_11_ARBURST, - m_axi_out_11_ARCACHE, - m_axi_out_11_ARID, - m_axi_out_11_ARLEN, - m_axi_out_11_ARLOCK, - m_axi_out_11_ARPROT, - m_axi_out_11_ARQOS, - m_axi_out_11_ARREADY, - m_axi_out_11_ARSIZE, - m_axi_out_11_ARVALID, - m_axi_out_11_AWADDR, - m_axi_out_11_AWBURST, - m_axi_out_11_AWCACHE, - m_axi_out_11_AWID, - m_axi_out_11_AWLEN, - m_axi_out_11_AWLOCK, - m_axi_out_11_AWPROT, - m_axi_out_11_AWQOS, - m_axi_out_11_AWREADY, - m_axi_out_11_AWSIZE, - m_axi_out_11_AWVALID, - m_axi_out_11_BID, - m_axi_out_11_BREADY, - m_axi_out_11_BRESP, - m_axi_out_11_BVALID, - m_axi_out_11_RDATA, - m_axi_out_11_RID, - m_axi_out_11_RLAST, - m_axi_out_11_RREADY, - m_axi_out_11_RRESP, - m_axi_out_11_RVALID, - m_axi_out_11_WDATA, - m_axi_out_11_WLAST, - m_axi_out_11_WREADY, - m_axi_out_11_WSTRB, - m_axi_out_11_WVALID -); - - parameter C_S_AXI_CONTROL_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_ADDR_WIDTH = 9; - parameter C_S_AXI_DATA_WIDTH = 32; - parameter C_S_AXI_CONTROL_WSTRB_WIDTH = 32 / 8; - parameter C_S_AXI_WSTRB_WIDTH = 32 / 8; - (* RS_HS = "s_axi_control_AW.valid" *)input s_axi_control_AWVALID; - (* RS_HS = "s_axi_control_AW.ready" *)output s_axi_control_AWREADY; - (* RS_HS = "s_axi_control_AW.data" *)input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR; - (* RS_HS = "s_axi_control_W.valid" *)input s_axi_control_WVALID; - (* RS_HS = "s_axi_control_W.ready" *)output s_axi_control_WREADY; - (* RS_HS = "s_axi_control_W.data" *)input [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA; - (* RS_HS = "s_axi_control_W.data" *)input [C_S_AXI_CONTROL_WSTRB_WIDTH-1:0] s_axi_control_WSTRB; - (* RS_HS = "s_axi_control_AR.valid" *)input s_axi_control_ARVALID; - (* RS_HS = "s_axi_control_AR.ready" *)output s_axi_control_ARREADY; - (* RS_HS = "s_axi_control_AR.data" *)input [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_ARADDR; - (* RS_HS = "s_axi_control_R.valid" *)output s_axi_control_RVALID; - (* RS_HS = "s_axi_control_R.ready" *)input s_axi_control_RREADY; - (* RS_HS = "s_axi_control_R.data" *)output [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_RDATA; - (* RS_HS = "s_axi_control_R.data" *)output [1:0] s_axi_control_RRESP; - (* RS_HS = "s_axi_control_B.valid" *)output s_axi_control_BVALID; - (* RS_HS = "s_axi_control_B.ready" *)input s_axi_control_BREADY; - (* RS_HS = "s_axi_control_B.data" *)output [1:0] s_axi_control_BRESP; - (* RS_CLK *)input ap_clk; - (* RS_RST = "ff" *)input ap_rst_n; - (* RS_FF = "interrupt" *)output interrupt; - (* RS_HS = "m_axi_in_0_AR.data" *)output [63:0] m_axi_in_0_ARADDR; - (* RS_HS = "m_axi_in_0_AR.data" *)output [1:0] m_axi_in_0_ARBURST; - (* RS_HS = "m_axi_in_0_AR.data" *)output [3:0] m_axi_in_0_ARCACHE; - (* RS_HS = "m_axi_in_0_AR.data" *)output [0:0] m_axi_in_0_ARID; - (* RS_HS = "m_axi_in_0_AR.data" *)output [7:0] m_axi_in_0_ARLEN; - (* RS_HS = "m_axi_in_0_AR.data" *)output m_axi_in_0_ARLOCK; - (* RS_HS = "m_axi_in_0_AR.data" *)output [2:0] m_axi_in_0_ARPROT; - (* RS_HS = "m_axi_in_0_AR.data" *)output [3:0] m_axi_in_0_ARQOS; - (* RS_HS = "m_axi_in_0_AR.ready" *)input m_axi_in_0_ARREADY; - (* RS_HS = "m_axi_in_0_AR.data" *)output [2:0] m_axi_in_0_ARSIZE; - (* RS_HS = "m_axi_in_0_AR.valid" *)output m_axi_in_0_ARVALID; - (* RS_HS = "m_axi_in_0_AW.data" *)output [63:0] m_axi_in_0_AWADDR; - (* RS_HS = "m_axi_in_0_AW.data" *)output [1:0] m_axi_in_0_AWBURST; - (* RS_HS = "m_axi_in_0_AW.data" *)output [3:0] m_axi_in_0_AWCACHE; - (* RS_HS = "m_axi_in_0_AW.data" *)output [0:0] m_axi_in_0_AWID; - (* RS_HS = "m_axi_in_0_AW.data" *)output [7:0] m_axi_in_0_AWLEN; - (* RS_HS = "m_axi_in_0_AW.data" *)output m_axi_in_0_AWLOCK; - (* RS_HS = "m_axi_in_0_AW.data" *)output [2:0] m_axi_in_0_AWPROT; - (* RS_HS = "m_axi_in_0_AW.data" *)output [3:0] m_axi_in_0_AWQOS; - (* RS_HS = "m_axi_in_0_AW.ready" *)input m_axi_in_0_AWREADY; - (* RS_HS = "m_axi_in_0_AW.data" *)output [2:0] m_axi_in_0_AWSIZE; - (* RS_HS = "m_axi_in_0_AW.valid" *)output m_axi_in_0_AWVALID; - (* RS_HS = "m_axi_in_0_B.data" *)input [0:0] m_axi_in_0_BID; - (* RS_HS = "m_axi_in_0_B.ready" *)output m_axi_in_0_BREADY; - (* RS_HS = "m_axi_in_0_B.data" *)input [1:0] m_axi_in_0_BRESP; - (* RS_HS = "m_axi_in_0_B.valid" *)input m_axi_in_0_BVALID; - (* RS_HS = "m_axi_in_0_R.data" *)input [511:0] m_axi_in_0_RDATA; - (* RS_HS = "m_axi_in_0_R.data" *)input [0:0] m_axi_in_0_RID; - (* RS_HS = "m_axi_in_0_R.data" *)input m_axi_in_0_RLAST; - (* RS_HS = "m_axi_in_0_R.ready" *)output m_axi_in_0_RREADY; - (* RS_HS = "m_axi_in_0_R.data" *)input [1:0] m_axi_in_0_RRESP; - (* RS_HS = "m_axi_in_0_R.valid" *)input m_axi_in_0_RVALID; - (* RS_HS = "m_axi_in_0_W.data" *)output [511:0] m_axi_in_0_WDATA; - (* RS_HS = "m_axi_in_0_W.data" *)output m_axi_in_0_WLAST; - (* RS_HS = "m_axi_in_0_W.ready" *)input m_axi_in_0_WREADY; - (* RS_HS = "m_axi_in_0_W.data" *)output [63:0] m_axi_in_0_WSTRB; - (* RS_HS = "m_axi_in_0_W.valid" *)output m_axi_in_0_WVALID; - (* RS_HS = "m_axi_out_0_AR.data" *)output [63:0] m_axi_out_0_ARADDR; - (* RS_HS = "m_axi_out_0_AR.data" *)output [1:0] m_axi_out_0_ARBURST; - (* RS_HS = "m_axi_out_0_AR.data" *)output [3:0] m_axi_out_0_ARCACHE; - (* RS_HS = "m_axi_out_0_AR.data" *)output [0:0] m_axi_out_0_ARID; - (* RS_HS = "m_axi_out_0_AR.data" *)output [7:0] m_axi_out_0_ARLEN; - (* RS_HS = "m_axi_out_0_AR.data" *)output m_axi_out_0_ARLOCK; - (* RS_HS = "m_axi_out_0_AR.data" *)output [2:0] m_axi_out_0_ARPROT; - (* RS_HS = "m_axi_out_0_AR.data" *)output [3:0] m_axi_out_0_ARQOS; - (* RS_HS = "m_axi_out_0_AR.ready" *)input m_axi_out_0_ARREADY; - (* RS_HS = "m_axi_out_0_AR.data" *)output [2:0] m_axi_out_0_ARSIZE; - (* RS_HS = "m_axi_out_0_AR.valid" *)output m_axi_out_0_ARVALID; - (* RS_HS = "m_axi_out_0_AW.data" *)output [63:0] m_axi_out_0_AWADDR; - (* RS_HS = "m_axi_out_0_AW.data" *)output [1:0] m_axi_out_0_AWBURST; - (* RS_HS = "m_axi_out_0_AW.data" *)output [3:0] m_axi_out_0_AWCACHE; - (* RS_HS = "m_axi_out_0_AW.data" *)output [0:0] m_axi_out_0_AWID; - (* RS_HS = "m_axi_out_0_AW.data" *)output [7:0] m_axi_out_0_AWLEN; - (* RS_HS = "m_axi_out_0_AW.data" *)output m_axi_out_0_AWLOCK; - (* RS_HS = "m_axi_out_0_AW.data" *)output [2:0] m_axi_out_0_AWPROT; - (* RS_HS = "m_axi_out_0_AW.data" *)output [3:0] m_axi_out_0_AWQOS; - (* RS_HS = "m_axi_out_0_AW.ready" *)input m_axi_out_0_AWREADY; - (* RS_HS = "m_axi_out_0_AW.data" *)output [2:0] m_axi_out_0_AWSIZE; - (* RS_HS = "m_axi_out_0_AW.valid" *)output m_axi_out_0_AWVALID; - (* RS_HS = "m_axi_out_0_B.data" *)input [0:0] m_axi_out_0_BID; - (* RS_HS = "m_axi_out_0_B.ready" *)output m_axi_out_0_BREADY; - (* RS_HS = "m_axi_out_0_B.data" *)input [1:0] m_axi_out_0_BRESP; - (* RS_HS = "m_axi_out_0_B.valid" *)input m_axi_out_0_BVALID; - (* RS_HS = "m_axi_out_0_R.data" *)input [511:0] m_axi_out_0_RDATA; - (* RS_HS = "m_axi_out_0_R.data" *)input [0:0] m_axi_out_0_RID; - (* RS_HS = "m_axi_out_0_R.data" *)input m_axi_out_0_RLAST; - (* RS_HS = "m_axi_out_0_R.ready" *)output m_axi_out_0_RREADY; - (* RS_HS = "m_axi_out_0_R.data" *)input [1:0] m_axi_out_0_RRESP; - (* RS_HS = "m_axi_out_0_R.valid" *)input m_axi_out_0_RVALID; - (* RS_HS = "m_axi_out_0_W.data" *)output [511:0] m_axi_out_0_WDATA; - (* RS_HS = "m_axi_out_0_W.data" *)output m_axi_out_0_WLAST; - (* RS_HS = "m_axi_out_0_W.ready" *)input m_axi_out_0_WREADY; - (* RS_HS = "m_axi_out_0_W.data" *)output [63:0] m_axi_out_0_WSTRB; - (* RS_HS = "m_axi_out_0_W.valid" *)output m_axi_out_0_WVALID; - (* RS_HS = "m_axi_in_1_AR.data" *)output [63:0] m_axi_in_1_ARADDR; - (* RS_HS = "m_axi_in_1_AR.data" *)output [1:0] m_axi_in_1_ARBURST; - (* RS_HS = "m_axi_in_1_AR.data" *)output [3:0] m_axi_in_1_ARCACHE; - (* RS_HS = "m_axi_in_1_AR.data" *)output [0:0] m_axi_in_1_ARID; - (* RS_HS = "m_axi_in_1_AR.data" *)output [7:0] m_axi_in_1_ARLEN; - (* RS_HS = "m_axi_in_1_AR.data" *)output m_axi_in_1_ARLOCK; - (* RS_HS = "m_axi_in_1_AR.data" *)output [2:0] m_axi_in_1_ARPROT; - (* RS_HS = "m_axi_in_1_AR.data" *)output [3:0] m_axi_in_1_ARQOS; - (* RS_HS = "m_axi_in_1_AR.ready" *)input m_axi_in_1_ARREADY; - (* RS_HS = "m_axi_in_1_AR.data" *)output [2:0] m_axi_in_1_ARSIZE; - (* RS_HS = "m_axi_in_1_AR.valid" *)output m_axi_in_1_ARVALID; - (* RS_HS = "m_axi_in_1_AW.data" *)output [63:0] m_axi_in_1_AWADDR; - (* RS_HS = "m_axi_in_1_AW.data" *)output [1:0] m_axi_in_1_AWBURST; - (* RS_HS = "m_axi_in_1_AW.data" *)output [3:0] m_axi_in_1_AWCACHE; - (* RS_HS = "m_axi_in_1_AW.data" *)output [0:0] m_axi_in_1_AWID; - (* RS_HS = "m_axi_in_1_AW.data" *)output [7:0] m_axi_in_1_AWLEN; - (* RS_HS = "m_axi_in_1_AW.data" *)output m_axi_in_1_AWLOCK; - (* RS_HS = "m_axi_in_1_AW.data" *)output [2:0] m_axi_in_1_AWPROT; - (* RS_HS = "m_axi_in_1_AW.data" *)output [3:0] m_axi_in_1_AWQOS; - (* RS_HS = "m_axi_in_1_AW.ready" *)input m_axi_in_1_AWREADY; - (* RS_HS = "m_axi_in_1_AW.data" *)output [2:0] m_axi_in_1_AWSIZE; - (* RS_HS = "m_axi_in_1_AW.valid" *)output m_axi_in_1_AWVALID; - (* RS_HS = "m_axi_in_1_B.data" *)input [0:0] m_axi_in_1_BID; - (* RS_HS = "m_axi_in_1_B.ready" *)output m_axi_in_1_BREADY; - (* RS_HS = "m_axi_in_1_B.data" *)input [1:0] m_axi_in_1_BRESP; - (* RS_HS = "m_axi_in_1_B.valid" *)input m_axi_in_1_BVALID; - (* RS_HS = "m_axi_in_1_R.data" *)input [511:0] m_axi_in_1_RDATA; - (* RS_HS = "m_axi_in_1_R.data" *)input [0:0] m_axi_in_1_RID; - (* RS_HS = "m_axi_in_1_R.data" *)input m_axi_in_1_RLAST; - (* RS_HS = "m_axi_in_1_R.ready" *)output m_axi_in_1_RREADY; - (* RS_HS = "m_axi_in_1_R.data" *)input [1:0] m_axi_in_1_RRESP; - (* RS_HS = "m_axi_in_1_R.valid" *)input m_axi_in_1_RVALID; - (* RS_HS = "m_axi_in_1_W.data" *)output [511:0] m_axi_in_1_WDATA; - (* RS_HS = "m_axi_in_1_W.data" *)output m_axi_in_1_WLAST; - (* RS_HS = "m_axi_in_1_W.ready" *)input m_axi_in_1_WREADY; - (* RS_HS = "m_axi_in_1_W.data" *)output [63:0] m_axi_in_1_WSTRB; - (* RS_HS = "m_axi_in_1_W.valid" *)output m_axi_in_1_WVALID; - (* RS_HS = "m_axi_out_1_AR.data" *)output [63:0] m_axi_out_1_ARADDR; - (* RS_HS = "m_axi_out_1_AR.data" *)output [1:0] m_axi_out_1_ARBURST; - (* RS_HS = "m_axi_out_1_AR.data" *)output [3:0] m_axi_out_1_ARCACHE; - (* RS_HS = "m_axi_out_1_AR.data" *)output [0:0] m_axi_out_1_ARID; - (* RS_HS = "m_axi_out_1_AR.data" *)output [7:0] m_axi_out_1_ARLEN; - (* RS_HS = "m_axi_out_1_AR.data" *)output m_axi_out_1_ARLOCK; - (* RS_HS = "m_axi_out_1_AR.data" *)output [2:0] m_axi_out_1_ARPROT; - (* RS_HS = "m_axi_out_1_AR.data" *)output [3:0] m_axi_out_1_ARQOS; - (* RS_HS = "m_axi_out_1_AR.ready" *)input m_axi_out_1_ARREADY; - (* RS_HS = "m_axi_out_1_AR.data" *)output [2:0] m_axi_out_1_ARSIZE; - (* RS_HS = "m_axi_out_1_AR.valid" *)output m_axi_out_1_ARVALID; - (* RS_HS = "m_axi_out_1_AW.data" *)output [63:0] m_axi_out_1_AWADDR; - (* RS_HS = "m_axi_out_1_AW.data" *)output [1:0] m_axi_out_1_AWBURST; - (* RS_HS = "m_axi_out_1_AW.data" *)output [3:0] m_axi_out_1_AWCACHE; - (* RS_HS = "m_axi_out_1_AW.data" *)output [0:0] m_axi_out_1_AWID; - (* RS_HS = "m_axi_out_1_AW.data" *)output [7:0] m_axi_out_1_AWLEN; - (* RS_HS = "m_axi_out_1_AW.data" *)output m_axi_out_1_AWLOCK; - (* RS_HS = "m_axi_out_1_AW.data" *)output [2:0] m_axi_out_1_AWPROT; - (* RS_HS = "m_axi_out_1_AW.data" *)output [3:0] m_axi_out_1_AWQOS; - (* RS_HS = "m_axi_out_1_AW.ready" *)input m_axi_out_1_AWREADY; - (* RS_HS = "m_axi_out_1_AW.data" *)output [2:0] m_axi_out_1_AWSIZE; - (* RS_HS = "m_axi_out_1_AW.valid" *)output m_axi_out_1_AWVALID; - (* RS_HS = "m_axi_out_1_B.data" *)input [0:0] m_axi_out_1_BID; - (* RS_HS = "m_axi_out_1_B.ready" *)output m_axi_out_1_BREADY; - (* RS_HS = "m_axi_out_1_B.data" *)input [1:0] m_axi_out_1_BRESP; - (* RS_HS = "m_axi_out_1_B.valid" *)input m_axi_out_1_BVALID; - (* RS_HS = "m_axi_out_1_R.data" *)input [511:0] m_axi_out_1_RDATA; - (* RS_HS = "m_axi_out_1_R.data" *)input [0:0] m_axi_out_1_RID; - (* RS_HS = "m_axi_out_1_R.data" *)input m_axi_out_1_RLAST; - (* RS_HS = "m_axi_out_1_R.ready" *)output m_axi_out_1_RREADY; - (* RS_HS = "m_axi_out_1_R.data" *)input [1:0] m_axi_out_1_RRESP; - (* RS_HS = "m_axi_out_1_R.valid" *)input m_axi_out_1_RVALID; - (* RS_HS = "m_axi_out_1_W.data" *)output [511:0] m_axi_out_1_WDATA; - (* RS_HS = "m_axi_out_1_W.data" *)output m_axi_out_1_WLAST; - (* RS_HS = "m_axi_out_1_W.ready" *)input m_axi_out_1_WREADY; - (* RS_HS = "m_axi_out_1_W.data" *)output [63:0] m_axi_out_1_WSTRB; - (* RS_HS = "m_axi_out_1_W.valid" *)output m_axi_out_1_WVALID; - (* RS_HS = "m_axi_in_2_AR.data" *)output [63:0] m_axi_in_2_ARADDR; - (* RS_HS = "m_axi_in_2_AR.data" *)output [1:0] m_axi_in_2_ARBURST; - (* RS_HS = "m_axi_in_2_AR.data" *)output [3:0] m_axi_in_2_ARCACHE; - (* RS_HS = "m_axi_in_2_AR.data" *)output [0:0] m_axi_in_2_ARID; - (* RS_HS = "m_axi_in_2_AR.data" *)output [7:0] m_axi_in_2_ARLEN; - (* RS_HS = "m_axi_in_2_AR.data" *)output m_axi_in_2_ARLOCK; - (* RS_HS = "m_axi_in_2_AR.data" *)output [2:0] m_axi_in_2_ARPROT; - (* RS_HS = "m_axi_in_2_AR.data" *)output [3:0] m_axi_in_2_ARQOS; - (* RS_HS = "m_axi_in_2_AR.ready" *)input m_axi_in_2_ARREADY; - (* RS_HS = "m_axi_in_2_AR.data" *)output [2:0] m_axi_in_2_ARSIZE; - (* RS_HS = "m_axi_in_2_AR.valid" *)output m_axi_in_2_ARVALID; - (* RS_HS = "m_axi_in_2_AW.data" *)output [63:0] m_axi_in_2_AWADDR; - (* RS_HS = "m_axi_in_2_AW.data" *)output [1:0] m_axi_in_2_AWBURST; - (* RS_HS = "m_axi_in_2_AW.data" *)output [3:0] m_axi_in_2_AWCACHE; - (* RS_HS = "m_axi_in_2_AW.data" *)output [0:0] m_axi_in_2_AWID; - (* RS_HS = "m_axi_in_2_AW.data" *)output [7:0] m_axi_in_2_AWLEN; - (* RS_HS = "m_axi_in_2_AW.data" *)output m_axi_in_2_AWLOCK; - (* RS_HS = "m_axi_in_2_AW.data" *)output [2:0] m_axi_in_2_AWPROT; - (* RS_HS = "m_axi_in_2_AW.data" *)output [3:0] m_axi_in_2_AWQOS; - (* RS_HS = "m_axi_in_2_AW.ready" *)input m_axi_in_2_AWREADY; - (* RS_HS = "m_axi_in_2_AW.data" *)output [2:0] m_axi_in_2_AWSIZE; - (* RS_HS = "m_axi_in_2_AW.valid" *)output m_axi_in_2_AWVALID; - (* RS_HS = "m_axi_in_2_B.data" *)input [0:0] m_axi_in_2_BID; - (* RS_HS = "m_axi_in_2_B.ready" *)output m_axi_in_2_BREADY; - (* RS_HS = "m_axi_in_2_B.data" *)input [1:0] m_axi_in_2_BRESP; - (* RS_HS = "m_axi_in_2_B.valid" *)input m_axi_in_2_BVALID; - (* RS_HS = "m_axi_in_2_R.data" *)input [511:0] m_axi_in_2_RDATA; - (* RS_HS = "m_axi_in_2_R.data" *)input [0:0] m_axi_in_2_RID; - (* RS_HS = "m_axi_in_2_R.data" *)input m_axi_in_2_RLAST; - (* RS_HS = "m_axi_in_2_R.ready" *)output m_axi_in_2_RREADY; - (* RS_HS = "m_axi_in_2_R.data" *)input [1:0] m_axi_in_2_RRESP; - (* RS_HS = "m_axi_in_2_R.valid" *)input m_axi_in_2_RVALID; - (* RS_HS = "m_axi_in_2_W.data" *)output [511:0] m_axi_in_2_WDATA; - (* RS_HS = "m_axi_in_2_W.data" *)output m_axi_in_2_WLAST; - (* RS_HS = "m_axi_in_2_W.ready" *)input m_axi_in_2_WREADY; - (* RS_HS = "m_axi_in_2_W.data" *)output [63:0] m_axi_in_2_WSTRB; - (* RS_HS = "m_axi_in_2_W.valid" *)output m_axi_in_2_WVALID; - (* RS_HS = "m_axi_out_2_AR.data" *)output [63:0] m_axi_out_2_ARADDR; - (* RS_HS = "m_axi_out_2_AR.data" *)output [1:0] m_axi_out_2_ARBURST; - (* RS_HS = "m_axi_out_2_AR.data" *)output [3:0] m_axi_out_2_ARCACHE; - (* RS_HS = "m_axi_out_2_AR.data" *)output [0:0] m_axi_out_2_ARID; - (* RS_HS = "m_axi_out_2_AR.data" *)output [7:0] m_axi_out_2_ARLEN; - (* RS_HS = "m_axi_out_2_AR.data" *)output m_axi_out_2_ARLOCK; - (* RS_HS = "m_axi_out_2_AR.data" *)output [2:0] m_axi_out_2_ARPROT; - (* RS_HS = "m_axi_out_2_AR.data" *)output [3:0] m_axi_out_2_ARQOS; - (* RS_HS = "m_axi_out_2_AR.ready" *)input m_axi_out_2_ARREADY; - (* RS_HS = "m_axi_out_2_AR.data" *)output [2:0] m_axi_out_2_ARSIZE; - (* RS_HS = "m_axi_out_2_AR.valid" *)output m_axi_out_2_ARVALID; - (* RS_HS = "m_axi_out_2_AW.data" *)output [63:0] m_axi_out_2_AWADDR; - (* RS_HS = "m_axi_out_2_AW.data" *)output [1:0] m_axi_out_2_AWBURST; - (* RS_HS = "m_axi_out_2_AW.data" *)output [3:0] m_axi_out_2_AWCACHE; - (* RS_HS = "m_axi_out_2_AW.data" *)output [0:0] m_axi_out_2_AWID; - (* RS_HS = "m_axi_out_2_AW.data" *)output [7:0] m_axi_out_2_AWLEN; - (* RS_HS = "m_axi_out_2_AW.data" *)output m_axi_out_2_AWLOCK; - (* RS_HS = "m_axi_out_2_AW.data" *)output [2:0] m_axi_out_2_AWPROT; - (* RS_HS = "m_axi_out_2_AW.data" *)output [3:0] m_axi_out_2_AWQOS; - (* RS_HS = "m_axi_out_2_AW.ready" *)input m_axi_out_2_AWREADY; - (* RS_HS = "m_axi_out_2_AW.data" *)output [2:0] m_axi_out_2_AWSIZE; - (* RS_HS = "m_axi_out_2_AW.valid" *)output m_axi_out_2_AWVALID; - (* RS_HS = "m_axi_out_2_B.data" *)input [0:0] m_axi_out_2_BID; - (* RS_HS = "m_axi_out_2_B.ready" *)output m_axi_out_2_BREADY; - (* RS_HS = "m_axi_out_2_B.data" *)input [1:0] m_axi_out_2_BRESP; - (* RS_HS = "m_axi_out_2_B.valid" *)input m_axi_out_2_BVALID; - (* RS_HS = "m_axi_out_2_R.data" *)input [511:0] m_axi_out_2_RDATA; - (* RS_HS = "m_axi_out_2_R.data" *)input [0:0] m_axi_out_2_RID; - (* RS_HS = "m_axi_out_2_R.data" *)input m_axi_out_2_RLAST; - (* RS_HS = "m_axi_out_2_R.ready" *)output m_axi_out_2_RREADY; - (* RS_HS = "m_axi_out_2_R.data" *)input [1:0] m_axi_out_2_RRESP; - (* RS_HS = "m_axi_out_2_R.valid" *)input m_axi_out_2_RVALID; - (* RS_HS = "m_axi_out_2_W.data" *)output [511:0] m_axi_out_2_WDATA; - (* RS_HS = "m_axi_out_2_W.data" *)output m_axi_out_2_WLAST; - (* RS_HS = "m_axi_out_2_W.ready" *)input m_axi_out_2_WREADY; - (* RS_HS = "m_axi_out_2_W.data" *)output [63:0] m_axi_out_2_WSTRB; - (* RS_HS = "m_axi_out_2_W.valid" *)output m_axi_out_2_WVALID; - (* RS_HS = "m_axi_in_3_AR.data" *)output [63:0] m_axi_in_3_ARADDR; - (* RS_HS = "m_axi_in_3_AR.data" *)output [1:0] m_axi_in_3_ARBURST; - (* RS_HS = "m_axi_in_3_AR.data" *)output [3:0] m_axi_in_3_ARCACHE; - (* RS_HS = "m_axi_in_3_AR.data" *)output [0:0] m_axi_in_3_ARID; - (* RS_HS = "m_axi_in_3_AR.data" *)output [7:0] m_axi_in_3_ARLEN; - (* RS_HS = "m_axi_in_3_AR.data" *)output m_axi_in_3_ARLOCK; - (* RS_HS = "m_axi_in_3_AR.data" *)output [2:0] m_axi_in_3_ARPROT; - (* RS_HS = "m_axi_in_3_AR.data" *)output [3:0] m_axi_in_3_ARQOS; - (* RS_HS = "m_axi_in_3_AR.ready" *)input m_axi_in_3_ARREADY; - (* RS_HS = "m_axi_in_3_AR.data" *)output [2:0] m_axi_in_3_ARSIZE; - (* RS_HS = "m_axi_in_3_AR.valid" *)output m_axi_in_3_ARVALID; - (* RS_HS = "m_axi_in_3_AW.data" *)output [63:0] m_axi_in_3_AWADDR; - (* RS_HS = "m_axi_in_3_AW.data" *)output [1:0] m_axi_in_3_AWBURST; - (* RS_HS = "m_axi_in_3_AW.data" *)output [3:0] m_axi_in_3_AWCACHE; - (* RS_HS = "m_axi_in_3_AW.data" *)output [0:0] m_axi_in_3_AWID; - (* RS_HS = "m_axi_in_3_AW.data" *)output [7:0] m_axi_in_3_AWLEN; - (* RS_HS = "m_axi_in_3_AW.data" *)output m_axi_in_3_AWLOCK; - (* RS_HS = "m_axi_in_3_AW.data" *)output [2:0] m_axi_in_3_AWPROT; - (* RS_HS = "m_axi_in_3_AW.data" *)output [3:0] m_axi_in_3_AWQOS; - (* RS_HS = "m_axi_in_3_AW.ready" *)input m_axi_in_3_AWREADY; - (* RS_HS = "m_axi_in_3_AW.data" *)output [2:0] m_axi_in_3_AWSIZE; - (* RS_HS = "m_axi_in_3_AW.valid" *)output m_axi_in_3_AWVALID; - (* RS_HS = "m_axi_in_3_B.data" *)input [0:0] m_axi_in_3_BID; - (* RS_HS = "m_axi_in_3_B.ready" *)output m_axi_in_3_BREADY; - (* RS_HS = "m_axi_in_3_B.data" *)input [1:0] m_axi_in_3_BRESP; - (* RS_HS = "m_axi_in_3_B.valid" *)input m_axi_in_3_BVALID; - (* RS_HS = "m_axi_in_3_R.data" *)input [511:0] m_axi_in_3_RDATA; - (* RS_HS = "m_axi_in_3_R.data" *)input [0:0] m_axi_in_3_RID; - (* RS_HS = "m_axi_in_3_R.data" *)input m_axi_in_3_RLAST; - (* RS_HS = "m_axi_in_3_R.ready" *)output m_axi_in_3_RREADY; - (* RS_HS = "m_axi_in_3_R.data" *)input [1:0] m_axi_in_3_RRESP; - (* RS_HS = "m_axi_in_3_R.valid" *)input m_axi_in_3_RVALID; - (* RS_HS = "m_axi_in_3_W.data" *)output [511:0] m_axi_in_3_WDATA; - (* RS_HS = "m_axi_in_3_W.data" *)output m_axi_in_3_WLAST; - (* RS_HS = "m_axi_in_3_W.ready" *)input m_axi_in_3_WREADY; - (* RS_HS = "m_axi_in_3_W.data" *)output [63:0] m_axi_in_3_WSTRB; - (* RS_HS = "m_axi_in_3_W.valid" *)output m_axi_in_3_WVALID; - (* RS_HS = "m_axi_out_3_AR.data" *)output [63:0] m_axi_out_3_ARADDR; - (* RS_HS = "m_axi_out_3_AR.data" *)output [1:0] m_axi_out_3_ARBURST; - (* RS_HS = "m_axi_out_3_AR.data" *)output [3:0] m_axi_out_3_ARCACHE; - (* RS_HS = "m_axi_out_3_AR.data" *)output [0:0] m_axi_out_3_ARID; - (* RS_HS = "m_axi_out_3_AR.data" *)output [7:0] m_axi_out_3_ARLEN; - (* RS_HS = "m_axi_out_3_AR.data" *)output m_axi_out_3_ARLOCK; - (* RS_HS = "m_axi_out_3_AR.data" *)output [2:0] m_axi_out_3_ARPROT; - (* RS_HS = "m_axi_out_3_AR.data" *)output [3:0] m_axi_out_3_ARQOS; - (* RS_HS = "m_axi_out_3_AR.ready" *)input m_axi_out_3_ARREADY; - (* RS_HS = "m_axi_out_3_AR.data" *)output [2:0] m_axi_out_3_ARSIZE; - (* RS_HS = "m_axi_out_3_AR.valid" *)output m_axi_out_3_ARVALID; - (* RS_HS = "m_axi_out_3_AW.data" *)output [63:0] m_axi_out_3_AWADDR; - (* RS_HS = "m_axi_out_3_AW.data" *)output [1:0] m_axi_out_3_AWBURST; - (* RS_HS = "m_axi_out_3_AW.data" *)output [3:0] m_axi_out_3_AWCACHE; - (* RS_HS = "m_axi_out_3_AW.data" *)output [0:0] m_axi_out_3_AWID; - (* RS_HS = "m_axi_out_3_AW.data" *)output [7:0] m_axi_out_3_AWLEN; - (* RS_HS = "m_axi_out_3_AW.data" *)output m_axi_out_3_AWLOCK; - (* RS_HS = "m_axi_out_3_AW.data" *)output [2:0] m_axi_out_3_AWPROT; - (* RS_HS = "m_axi_out_3_AW.data" *)output [3:0] m_axi_out_3_AWQOS; - (* RS_HS = "m_axi_out_3_AW.ready" *)input m_axi_out_3_AWREADY; - (* RS_HS = "m_axi_out_3_AW.data" *)output [2:0] m_axi_out_3_AWSIZE; - (* RS_HS = "m_axi_out_3_AW.valid" *)output m_axi_out_3_AWVALID; - (* RS_HS = "m_axi_out_3_B.data" *)input [0:0] m_axi_out_3_BID; - (* RS_HS = "m_axi_out_3_B.ready" *)output m_axi_out_3_BREADY; - (* RS_HS = "m_axi_out_3_B.data" *)input [1:0] m_axi_out_3_BRESP; - (* RS_HS = "m_axi_out_3_B.valid" *)input m_axi_out_3_BVALID; - (* RS_HS = "m_axi_out_3_R.data" *)input [511:0] m_axi_out_3_RDATA; - (* RS_HS = "m_axi_out_3_R.data" *)input [0:0] m_axi_out_3_RID; - (* RS_HS = "m_axi_out_3_R.data" *)input m_axi_out_3_RLAST; - (* RS_HS = "m_axi_out_3_R.ready" *)output m_axi_out_3_RREADY; - (* RS_HS = "m_axi_out_3_R.data" *)input [1:0] m_axi_out_3_RRESP; - (* RS_HS = "m_axi_out_3_R.valid" *)input m_axi_out_3_RVALID; - (* RS_HS = "m_axi_out_3_W.data" *)output [511:0] m_axi_out_3_WDATA; - (* RS_HS = "m_axi_out_3_W.data" *)output m_axi_out_3_WLAST; - (* RS_HS = "m_axi_out_3_W.ready" *)input m_axi_out_3_WREADY; - (* RS_HS = "m_axi_out_3_W.data" *)output [63:0] m_axi_out_3_WSTRB; - (* RS_HS = "m_axi_out_3_W.valid" *)output m_axi_out_3_WVALID; - (* RS_HS = "m_axi_in_4_AR.data" *)output [63:0] m_axi_in_4_ARADDR; - (* RS_HS = "m_axi_in_4_AR.data" *)output [1:0] m_axi_in_4_ARBURST; - (* RS_HS = "m_axi_in_4_AR.data" *)output [3:0] m_axi_in_4_ARCACHE; - (* RS_HS = "m_axi_in_4_AR.data" *)output [0:0] m_axi_in_4_ARID; - (* RS_HS = "m_axi_in_4_AR.data" *)output [7:0] m_axi_in_4_ARLEN; - (* RS_HS = "m_axi_in_4_AR.data" *)output m_axi_in_4_ARLOCK; - (* RS_HS = "m_axi_in_4_AR.data" *)output [2:0] m_axi_in_4_ARPROT; - (* RS_HS = "m_axi_in_4_AR.data" *)output [3:0] m_axi_in_4_ARQOS; - (* RS_HS = "m_axi_in_4_AR.ready" *)input m_axi_in_4_ARREADY; - (* RS_HS = "m_axi_in_4_AR.data" *)output [2:0] m_axi_in_4_ARSIZE; - (* RS_HS = "m_axi_in_4_AR.valid" *)output m_axi_in_4_ARVALID; - (* RS_HS = "m_axi_in_4_AW.data" *)output [63:0] m_axi_in_4_AWADDR; - (* RS_HS = "m_axi_in_4_AW.data" *)output [1:0] m_axi_in_4_AWBURST; - (* RS_HS = "m_axi_in_4_AW.data" *)output [3:0] m_axi_in_4_AWCACHE; - (* RS_HS = "m_axi_in_4_AW.data" *)output [0:0] m_axi_in_4_AWID; - (* RS_HS = "m_axi_in_4_AW.data" *)output [7:0] m_axi_in_4_AWLEN; - (* RS_HS = "m_axi_in_4_AW.data" *)output m_axi_in_4_AWLOCK; - (* RS_HS = "m_axi_in_4_AW.data" *)output [2:0] m_axi_in_4_AWPROT; - (* RS_HS = "m_axi_in_4_AW.data" *)output [3:0] m_axi_in_4_AWQOS; - (* RS_HS = "m_axi_in_4_AW.ready" *)input m_axi_in_4_AWREADY; - (* RS_HS = "m_axi_in_4_AW.data" *)output [2:0] m_axi_in_4_AWSIZE; - (* RS_HS = "m_axi_in_4_AW.valid" *)output m_axi_in_4_AWVALID; - (* RS_HS = "m_axi_in_4_B.data" *)input [0:0] m_axi_in_4_BID; - (* RS_HS = "m_axi_in_4_B.ready" *)output m_axi_in_4_BREADY; - (* RS_HS = "m_axi_in_4_B.data" *)input [1:0] m_axi_in_4_BRESP; - (* RS_HS = "m_axi_in_4_B.valid" *)input m_axi_in_4_BVALID; - (* RS_HS = "m_axi_in_4_R.data" *)input [511:0] m_axi_in_4_RDATA; - (* RS_HS = "m_axi_in_4_R.data" *)input [0:0] m_axi_in_4_RID; - (* RS_HS = "m_axi_in_4_R.data" *)input m_axi_in_4_RLAST; - (* RS_HS = "m_axi_in_4_R.ready" *)output m_axi_in_4_RREADY; - (* RS_HS = "m_axi_in_4_R.data" *)input [1:0] m_axi_in_4_RRESP; - (* RS_HS = "m_axi_in_4_R.valid" *)input m_axi_in_4_RVALID; - (* RS_HS = "m_axi_in_4_W.data" *)output [511:0] m_axi_in_4_WDATA; - (* RS_HS = "m_axi_in_4_W.data" *)output m_axi_in_4_WLAST; - (* RS_HS = "m_axi_in_4_W.ready" *)input m_axi_in_4_WREADY; - (* RS_HS = "m_axi_in_4_W.data" *)output [63:0] m_axi_in_4_WSTRB; - (* RS_HS = "m_axi_in_4_W.valid" *)output m_axi_in_4_WVALID; - (* RS_HS = "m_axi_out_4_AR.data" *)output [63:0] m_axi_out_4_ARADDR; - (* RS_HS = "m_axi_out_4_AR.data" *)output [1:0] m_axi_out_4_ARBURST; - (* RS_HS = "m_axi_out_4_AR.data" *)output [3:0] m_axi_out_4_ARCACHE; - (* RS_HS = "m_axi_out_4_AR.data" *)output [0:0] m_axi_out_4_ARID; - (* RS_HS = "m_axi_out_4_AR.data" *)output [7:0] m_axi_out_4_ARLEN; - (* RS_HS = "m_axi_out_4_AR.data" *)output m_axi_out_4_ARLOCK; - (* RS_HS = "m_axi_out_4_AR.data" *)output [2:0] m_axi_out_4_ARPROT; - (* RS_HS = "m_axi_out_4_AR.data" *)output [3:0] m_axi_out_4_ARQOS; - (* RS_HS = "m_axi_out_4_AR.ready" *)input m_axi_out_4_ARREADY; - (* RS_HS = "m_axi_out_4_AR.data" *)output [2:0] m_axi_out_4_ARSIZE; - (* RS_HS = "m_axi_out_4_AR.valid" *)output m_axi_out_4_ARVALID; - (* RS_HS = "m_axi_out_4_AW.data" *)output [63:0] m_axi_out_4_AWADDR; - (* RS_HS = "m_axi_out_4_AW.data" *)output [1:0] m_axi_out_4_AWBURST; - (* RS_HS = "m_axi_out_4_AW.data" *)output [3:0] m_axi_out_4_AWCACHE; - (* RS_HS = "m_axi_out_4_AW.data" *)output [0:0] m_axi_out_4_AWID; - (* RS_HS = "m_axi_out_4_AW.data" *)output [7:0] m_axi_out_4_AWLEN; - (* RS_HS = "m_axi_out_4_AW.data" *)output m_axi_out_4_AWLOCK; - (* RS_HS = "m_axi_out_4_AW.data" *)output [2:0] m_axi_out_4_AWPROT; - (* RS_HS = "m_axi_out_4_AW.data" *)output [3:0] m_axi_out_4_AWQOS; - (* RS_HS = "m_axi_out_4_AW.ready" *)input m_axi_out_4_AWREADY; - (* RS_HS = "m_axi_out_4_AW.data" *)output [2:0] m_axi_out_4_AWSIZE; - (* RS_HS = "m_axi_out_4_AW.valid" *)output m_axi_out_4_AWVALID; - (* RS_HS = "m_axi_out_4_B.data" *)input [0:0] m_axi_out_4_BID; - (* RS_HS = "m_axi_out_4_B.ready" *)output m_axi_out_4_BREADY; - (* RS_HS = "m_axi_out_4_B.data" *)input [1:0] m_axi_out_4_BRESP; - (* RS_HS = "m_axi_out_4_B.valid" *)input m_axi_out_4_BVALID; - (* RS_HS = "m_axi_out_4_R.data" *)input [511:0] m_axi_out_4_RDATA; - (* RS_HS = "m_axi_out_4_R.data" *)input [0:0] m_axi_out_4_RID; - (* RS_HS = "m_axi_out_4_R.data" *)input m_axi_out_4_RLAST; - (* RS_HS = "m_axi_out_4_R.ready" *)output m_axi_out_4_RREADY; - (* RS_HS = "m_axi_out_4_R.data" *)input [1:0] m_axi_out_4_RRESP; - (* RS_HS = "m_axi_out_4_R.valid" *)input m_axi_out_4_RVALID; - (* RS_HS = "m_axi_out_4_W.data" *)output [511:0] m_axi_out_4_WDATA; - (* RS_HS = "m_axi_out_4_W.data" *)output m_axi_out_4_WLAST; - (* RS_HS = "m_axi_out_4_W.ready" *)input m_axi_out_4_WREADY; - (* RS_HS = "m_axi_out_4_W.data" *)output [63:0] m_axi_out_4_WSTRB; - (* RS_HS = "m_axi_out_4_W.valid" *)output m_axi_out_4_WVALID; - (* RS_HS = "m_axi_in_5_AR.data" *)output [63:0] m_axi_in_5_ARADDR; - (* RS_HS = "m_axi_in_5_AR.data" *)output [1:0] m_axi_in_5_ARBURST; - (* RS_HS = "m_axi_in_5_AR.data" *)output [3:0] m_axi_in_5_ARCACHE; - (* RS_HS = "m_axi_in_5_AR.data" *)output [0:0] m_axi_in_5_ARID; - (* RS_HS = "m_axi_in_5_AR.data" *)output [7:0] m_axi_in_5_ARLEN; - (* RS_HS = "m_axi_in_5_AR.data" *)output m_axi_in_5_ARLOCK; - (* RS_HS = "m_axi_in_5_AR.data" *)output [2:0] m_axi_in_5_ARPROT; - (* RS_HS = "m_axi_in_5_AR.data" *)output [3:0] m_axi_in_5_ARQOS; - (* RS_HS = "m_axi_in_5_AR.ready" *)input m_axi_in_5_ARREADY; - (* RS_HS = "m_axi_in_5_AR.data" *)output [2:0] m_axi_in_5_ARSIZE; - (* RS_HS = "m_axi_in_5_AR.valid" *)output m_axi_in_5_ARVALID; - (* RS_HS = "m_axi_in_5_AW.data" *)output [63:0] m_axi_in_5_AWADDR; - (* RS_HS = "m_axi_in_5_AW.data" *)output [1:0] m_axi_in_5_AWBURST; - (* RS_HS = "m_axi_in_5_AW.data" *)output [3:0] m_axi_in_5_AWCACHE; - (* RS_HS = "m_axi_in_5_AW.data" *)output [0:0] m_axi_in_5_AWID; - (* RS_HS = "m_axi_in_5_AW.data" *)output [7:0] m_axi_in_5_AWLEN; - (* RS_HS = "m_axi_in_5_AW.data" *)output m_axi_in_5_AWLOCK; - (* RS_HS = "m_axi_in_5_AW.data" *)output [2:0] m_axi_in_5_AWPROT; - (* RS_HS = "m_axi_in_5_AW.data" *)output [3:0] m_axi_in_5_AWQOS; - (* RS_HS = "m_axi_in_5_AW.ready" *)input m_axi_in_5_AWREADY; - (* RS_HS = "m_axi_in_5_AW.data" *)output [2:0] m_axi_in_5_AWSIZE; - (* RS_HS = "m_axi_in_5_AW.valid" *)output m_axi_in_5_AWVALID; - (* RS_HS = "m_axi_in_5_B.data" *)input [0:0] m_axi_in_5_BID; - (* RS_HS = "m_axi_in_5_B.ready" *)output m_axi_in_5_BREADY; - (* RS_HS = "m_axi_in_5_B.data" *)input [1:0] m_axi_in_5_BRESP; - (* RS_HS = "m_axi_in_5_B.valid" *)input m_axi_in_5_BVALID; - (* RS_HS = "m_axi_in_5_R.data" *)input [511:0] m_axi_in_5_RDATA; - (* RS_HS = "m_axi_in_5_R.data" *)input [0:0] m_axi_in_5_RID; - (* RS_HS = "m_axi_in_5_R.data" *)input m_axi_in_5_RLAST; - (* RS_HS = "m_axi_in_5_R.ready" *)output m_axi_in_5_RREADY; - (* RS_HS = "m_axi_in_5_R.data" *)input [1:0] m_axi_in_5_RRESP; - (* RS_HS = "m_axi_in_5_R.valid" *)input m_axi_in_5_RVALID; - (* RS_HS = "m_axi_in_5_W.data" *)output [511:0] m_axi_in_5_WDATA; - (* RS_HS = "m_axi_in_5_W.data" *)output m_axi_in_5_WLAST; - (* RS_HS = "m_axi_in_5_W.ready" *)input m_axi_in_5_WREADY; - (* RS_HS = "m_axi_in_5_W.data" *)output [63:0] m_axi_in_5_WSTRB; - (* RS_HS = "m_axi_in_5_W.valid" *)output m_axi_in_5_WVALID; - (* RS_HS = "m_axi_out_5_AR.data" *)output [63:0] m_axi_out_5_ARADDR; - (* RS_HS = "m_axi_out_5_AR.data" *)output [1:0] m_axi_out_5_ARBURST; - (* RS_HS = "m_axi_out_5_AR.data" *)output [3:0] m_axi_out_5_ARCACHE; - (* RS_HS = "m_axi_out_5_AR.data" *)output [0:0] m_axi_out_5_ARID; - (* RS_HS = "m_axi_out_5_AR.data" *)output [7:0] m_axi_out_5_ARLEN; - (* RS_HS = "m_axi_out_5_AR.data" *)output m_axi_out_5_ARLOCK; - (* RS_HS = "m_axi_out_5_AR.data" *)output [2:0] m_axi_out_5_ARPROT; - (* RS_HS = "m_axi_out_5_AR.data" *)output [3:0] m_axi_out_5_ARQOS; - (* RS_HS = "m_axi_out_5_AR.ready" *)input m_axi_out_5_ARREADY; - (* RS_HS = "m_axi_out_5_AR.data" *)output [2:0] m_axi_out_5_ARSIZE; - (* RS_HS = "m_axi_out_5_AR.valid" *)output m_axi_out_5_ARVALID; - (* RS_HS = "m_axi_out_5_AW.data" *)output [63:0] m_axi_out_5_AWADDR; - (* RS_HS = "m_axi_out_5_AW.data" *)output [1:0] m_axi_out_5_AWBURST; - (* RS_HS = "m_axi_out_5_AW.data" *)output [3:0] m_axi_out_5_AWCACHE; - (* RS_HS = "m_axi_out_5_AW.data" *)output [0:0] m_axi_out_5_AWID; - (* RS_HS = "m_axi_out_5_AW.data" *)output [7:0] m_axi_out_5_AWLEN; - (* RS_HS = "m_axi_out_5_AW.data" *)output m_axi_out_5_AWLOCK; - (* RS_HS = "m_axi_out_5_AW.data" *)output [2:0] m_axi_out_5_AWPROT; - (* RS_HS = "m_axi_out_5_AW.data" *)output [3:0] m_axi_out_5_AWQOS; - (* RS_HS = "m_axi_out_5_AW.ready" *)input m_axi_out_5_AWREADY; - (* RS_HS = "m_axi_out_5_AW.data" *)output [2:0] m_axi_out_5_AWSIZE; - (* RS_HS = "m_axi_out_5_AW.valid" *)output m_axi_out_5_AWVALID; - (* RS_HS = "m_axi_out_5_B.data" *)input [0:0] m_axi_out_5_BID; - (* RS_HS = "m_axi_out_5_B.ready" *)output m_axi_out_5_BREADY; - (* RS_HS = "m_axi_out_5_B.data" *)input [1:0] m_axi_out_5_BRESP; - (* RS_HS = "m_axi_out_5_B.valid" *)input m_axi_out_5_BVALID; - (* RS_HS = "m_axi_out_5_R.data" *)input [511:0] m_axi_out_5_RDATA; - (* RS_HS = "m_axi_out_5_R.data" *)input [0:0] m_axi_out_5_RID; - (* RS_HS = "m_axi_out_5_R.data" *)input m_axi_out_5_RLAST; - (* RS_HS = "m_axi_out_5_R.ready" *)output m_axi_out_5_RREADY; - (* RS_HS = "m_axi_out_5_R.data" *)input [1:0] m_axi_out_5_RRESP; - (* RS_HS = "m_axi_out_5_R.valid" *)input m_axi_out_5_RVALID; - (* RS_HS = "m_axi_out_5_W.data" *)output [511:0] m_axi_out_5_WDATA; - (* RS_HS = "m_axi_out_5_W.data" *)output m_axi_out_5_WLAST; - (* RS_HS = "m_axi_out_5_W.ready" *)input m_axi_out_5_WREADY; - (* RS_HS = "m_axi_out_5_W.data" *)output [63:0] m_axi_out_5_WSTRB; - (* RS_HS = "m_axi_out_5_W.valid" *)output m_axi_out_5_WVALID; - (* RS_HS = "m_axi_in_6_AR.data" *)output [63:0] m_axi_in_6_ARADDR; - (* RS_HS = "m_axi_in_6_AR.data" *)output [1:0] m_axi_in_6_ARBURST; - (* RS_HS = "m_axi_in_6_AR.data" *)output [3:0] m_axi_in_6_ARCACHE; - (* RS_HS = "m_axi_in_6_AR.data" *)output [0:0] m_axi_in_6_ARID; - (* RS_HS = "m_axi_in_6_AR.data" *)output [7:0] m_axi_in_6_ARLEN; - (* RS_HS = "m_axi_in_6_AR.data" *)output m_axi_in_6_ARLOCK; - (* RS_HS = "m_axi_in_6_AR.data" *)output [2:0] m_axi_in_6_ARPROT; - (* RS_HS = "m_axi_in_6_AR.data" *)output [3:0] m_axi_in_6_ARQOS; - (* RS_HS = "m_axi_in_6_AR.ready" *)input m_axi_in_6_ARREADY; - (* RS_HS = "m_axi_in_6_AR.data" *)output [2:0] m_axi_in_6_ARSIZE; - (* RS_HS = "m_axi_in_6_AR.valid" *)output m_axi_in_6_ARVALID; - (* RS_HS = "m_axi_in_6_AW.data" *)output [63:0] m_axi_in_6_AWADDR; - (* RS_HS = "m_axi_in_6_AW.data" *)output [1:0] m_axi_in_6_AWBURST; - (* RS_HS = "m_axi_in_6_AW.data" *)output [3:0] m_axi_in_6_AWCACHE; - (* RS_HS = "m_axi_in_6_AW.data" *)output [0:0] m_axi_in_6_AWID; - (* RS_HS = "m_axi_in_6_AW.data" *)output [7:0] m_axi_in_6_AWLEN; - (* RS_HS = "m_axi_in_6_AW.data" *)output m_axi_in_6_AWLOCK; - (* RS_HS = "m_axi_in_6_AW.data" *)output [2:0] m_axi_in_6_AWPROT; - (* RS_HS = "m_axi_in_6_AW.data" *)output [3:0] m_axi_in_6_AWQOS; - (* RS_HS = "m_axi_in_6_AW.ready" *)input m_axi_in_6_AWREADY; - (* RS_HS = "m_axi_in_6_AW.data" *)output [2:0] m_axi_in_6_AWSIZE; - (* RS_HS = "m_axi_in_6_AW.valid" *)output m_axi_in_6_AWVALID; - (* RS_HS = "m_axi_in_6_B.data" *)input [0:0] m_axi_in_6_BID; - (* RS_HS = "m_axi_in_6_B.ready" *)output m_axi_in_6_BREADY; - (* RS_HS = "m_axi_in_6_B.data" *)input [1:0] m_axi_in_6_BRESP; - (* RS_HS = "m_axi_in_6_B.valid" *)input m_axi_in_6_BVALID; - (* RS_HS = "m_axi_in_6_R.data" *)input [511:0] m_axi_in_6_RDATA; - (* RS_HS = "m_axi_in_6_R.data" *)input [0:0] m_axi_in_6_RID; - (* RS_HS = "m_axi_in_6_R.data" *)input m_axi_in_6_RLAST; - (* RS_HS = "m_axi_in_6_R.ready" *)output m_axi_in_6_RREADY; - (* RS_HS = "m_axi_in_6_R.data" *)input [1:0] m_axi_in_6_RRESP; - (* RS_HS = "m_axi_in_6_R.valid" *)input m_axi_in_6_RVALID; - (* RS_HS = "m_axi_in_6_W.data" *)output [511:0] m_axi_in_6_WDATA; - (* RS_HS = "m_axi_in_6_W.data" *)output m_axi_in_6_WLAST; - (* RS_HS = "m_axi_in_6_W.ready" *)input m_axi_in_6_WREADY; - (* RS_HS = "m_axi_in_6_W.data" *)output [63:0] m_axi_in_6_WSTRB; - (* RS_HS = "m_axi_in_6_W.valid" *)output m_axi_in_6_WVALID; - (* RS_HS = "m_axi_out_6_AR.data" *)output [63:0] m_axi_out_6_ARADDR; - (* RS_HS = "m_axi_out_6_AR.data" *)output [1:0] m_axi_out_6_ARBURST; - (* RS_HS = "m_axi_out_6_AR.data" *)output [3:0] m_axi_out_6_ARCACHE; - (* RS_HS = "m_axi_out_6_AR.data" *)output [0:0] m_axi_out_6_ARID; - (* RS_HS = "m_axi_out_6_AR.data" *)output [7:0] m_axi_out_6_ARLEN; - (* RS_HS = "m_axi_out_6_AR.data" *)output m_axi_out_6_ARLOCK; - (* RS_HS = "m_axi_out_6_AR.data" *)output [2:0] m_axi_out_6_ARPROT; - (* RS_HS = "m_axi_out_6_AR.data" *)output [3:0] m_axi_out_6_ARQOS; - (* RS_HS = "m_axi_out_6_AR.ready" *)input m_axi_out_6_ARREADY; - (* RS_HS = "m_axi_out_6_AR.data" *)output [2:0] m_axi_out_6_ARSIZE; - (* RS_HS = "m_axi_out_6_AR.valid" *)output m_axi_out_6_ARVALID; - (* RS_HS = "m_axi_out_6_AW.data" *)output [63:0] m_axi_out_6_AWADDR; - (* RS_HS = "m_axi_out_6_AW.data" *)output [1:0] m_axi_out_6_AWBURST; - (* RS_HS = "m_axi_out_6_AW.data" *)output [3:0] m_axi_out_6_AWCACHE; - (* RS_HS = "m_axi_out_6_AW.data" *)output [0:0] m_axi_out_6_AWID; - (* RS_HS = "m_axi_out_6_AW.data" *)output [7:0] m_axi_out_6_AWLEN; - (* RS_HS = "m_axi_out_6_AW.data" *)output m_axi_out_6_AWLOCK; - (* RS_HS = "m_axi_out_6_AW.data" *)output [2:0] m_axi_out_6_AWPROT; - (* RS_HS = "m_axi_out_6_AW.data" *)output [3:0] m_axi_out_6_AWQOS; - (* RS_HS = "m_axi_out_6_AW.ready" *)input m_axi_out_6_AWREADY; - (* RS_HS = "m_axi_out_6_AW.data" *)output [2:0] m_axi_out_6_AWSIZE; - (* RS_HS = "m_axi_out_6_AW.valid" *)output m_axi_out_6_AWVALID; - (* RS_HS = "m_axi_out_6_B.data" *)input [0:0] m_axi_out_6_BID; - (* RS_HS = "m_axi_out_6_B.ready" *)output m_axi_out_6_BREADY; - (* RS_HS = "m_axi_out_6_B.data" *)input [1:0] m_axi_out_6_BRESP; - (* RS_HS = "m_axi_out_6_B.valid" *)input m_axi_out_6_BVALID; - (* RS_HS = "m_axi_out_6_R.data" *)input [511:0] m_axi_out_6_RDATA; - (* RS_HS = "m_axi_out_6_R.data" *)input [0:0] m_axi_out_6_RID; - (* RS_HS = "m_axi_out_6_R.data" *)input m_axi_out_6_RLAST; - (* RS_HS = "m_axi_out_6_R.ready" *)output m_axi_out_6_RREADY; - (* RS_HS = "m_axi_out_6_R.data" *)input [1:0] m_axi_out_6_RRESP; - (* RS_HS = "m_axi_out_6_R.valid" *)input m_axi_out_6_RVALID; - (* RS_HS = "m_axi_out_6_W.data" *)output [511:0] m_axi_out_6_WDATA; - (* RS_HS = "m_axi_out_6_W.data" *)output m_axi_out_6_WLAST; - (* RS_HS = "m_axi_out_6_W.ready" *)input m_axi_out_6_WREADY; - (* RS_HS = "m_axi_out_6_W.data" *)output [63:0] m_axi_out_6_WSTRB; - (* RS_HS = "m_axi_out_6_W.valid" *)output m_axi_out_6_WVALID; - (* RS_HS = "m_axi_in_7_AR.data" *)output [63:0] m_axi_in_7_ARADDR; - (* RS_HS = "m_axi_in_7_AR.data" *)output [1:0] m_axi_in_7_ARBURST; - (* RS_HS = "m_axi_in_7_AR.data" *)output [3:0] m_axi_in_7_ARCACHE; - (* RS_HS = "m_axi_in_7_AR.data" *)output [0:0] m_axi_in_7_ARID; - (* RS_HS = "m_axi_in_7_AR.data" *)output [7:0] m_axi_in_7_ARLEN; - (* RS_HS = "m_axi_in_7_AR.data" *)output m_axi_in_7_ARLOCK; - (* RS_HS = "m_axi_in_7_AR.data" *)output [2:0] m_axi_in_7_ARPROT; - (* RS_HS = "m_axi_in_7_AR.data" *)output [3:0] m_axi_in_7_ARQOS; - (* RS_HS = "m_axi_in_7_AR.ready" *)input m_axi_in_7_ARREADY; - (* RS_HS = "m_axi_in_7_AR.data" *)output [2:0] m_axi_in_7_ARSIZE; - (* RS_HS = "m_axi_in_7_AR.valid" *)output m_axi_in_7_ARVALID; - (* RS_HS = "m_axi_in_7_AW.data" *)output [63:0] m_axi_in_7_AWADDR; - (* RS_HS = "m_axi_in_7_AW.data" *)output [1:0] m_axi_in_7_AWBURST; - (* RS_HS = "m_axi_in_7_AW.data" *)output [3:0] m_axi_in_7_AWCACHE; - (* RS_HS = "m_axi_in_7_AW.data" *)output [0:0] m_axi_in_7_AWID; - (* RS_HS = "m_axi_in_7_AW.data" *)output [7:0] m_axi_in_7_AWLEN; - (* RS_HS = "m_axi_in_7_AW.data" *)output m_axi_in_7_AWLOCK; - (* RS_HS = "m_axi_in_7_AW.data" *)output [2:0] m_axi_in_7_AWPROT; - (* RS_HS = "m_axi_in_7_AW.data" *)output [3:0] m_axi_in_7_AWQOS; - (* RS_HS = "m_axi_in_7_AW.ready" *)input m_axi_in_7_AWREADY; - (* RS_HS = "m_axi_in_7_AW.data" *)output [2:0] m_axi_in_7_AWSIZE; - (* RS_HS = "m_axi_in_7_AW.valid" *)output m_axi_in_7_AWVALID; - (* RS_HS = "m_axi_in_7_B.data" *)input [0:0] m_axi_in_7_BID; - (* RS_HS = "m_axi_in_7_B.ready" *)output m_axi_in_7_BREADY; - (* RS_HS = "m_axi_in_7_B.data" *)input [1:0] m_axi_in_7_BRESP; - (* RS_HS = "m_axi_in_7_B.valid" *)input m_axi_in_7_BVALID; - (* RS_HS = "m_axi_in_7_R.data" *)input [511:0] m_axi_in_7_RDATA; - (* RS_HS = "m_axi_in_7_R.data" *)input [0:0] m_axi_in_7_RID; - (* RS_HS = "m_axi_in_7_R.data" *)input m_axi_in_7_RLAST; - (* RS_HS = "m_axi_in_7_R.ready" *)output m_axi_in_7_RREADY; - (* RS_HS = "m_axi_in_7_R.data" *)input [1:0] m_axi_in_7_RRESP; - (* RS_HS = "m_axi_in_7_R.valid" *)input m_axi_in_7_RVALID; - (* RS_HS = "m_axi_in_7_W.data" *)output [511:0] m_axi_in_7_WDATA; - (* RS_HS = "m_axi_in_7_W.data" *)output m_axi_in_7_WLAST; - (* RS_HS = "m_axi_in_7_W.ready" *)input m_axi_in_7_WREADY; - (* RS_HS = "m_axi_in_7_W.data" *)output [63:0] m_axi_in_7_WSTRB; - (* RS_HS = "m_axi_in_7_W.valid" *)output m_axi_in_7_WVALID; - (* RS_HS = "m_axi_out_7_AR.data" *)output [63:0] m_axi_out_7_ARADDR; - (* RS_HS = "m_axi_out_7_AR.data" *)output [1:0] m_axi_out_7_ARBURST; - (* RS_HS = "m_axi_out_7_AR.data" *)output [3:0] m_axi_out_7_ARCACHE; - (* RS_HS = "m_axi_out_7_AR.data" *)output [0:0] m_axi_out_7_ARID; - (* RS_HS = "m_axi_out_7_AR.data" *)output [7:0] m_axi_out_7_ARLEN; - (* RS_HS = "m_axi_out_7_AR.data" *)output m_axi_out_7_ARLOCK; - (* RS_HS = "m_axi_out_7_AR.data" *)output [2:0] m_axi_out_7_ARPROT; - (* RS_HS = "m_axi_out_7_AR.data" *)output [3:0] m_axi_out_7_ARQOS; - (* RS_HS = "m_axi_out_7_AR.ready" *)input m_axi_out_7_ARREADY; - (* RS_HS = "m_axi_out_7_AR.data" *)output [2:0] m_axi_out_7_ARSIZE; - (* RS_HS = "m_axi_out_7_AR.valid" *)output m_axi_out_7_ARVALID; - (* RS_HS = "m_axi_out_7_AW.data" *)output [63:0] m_axi_out_7_AWADDR; - (* RS_HS = "m_axi_out_7_AW.data" *)output [1:0] m_axi_out_7_AWBURST; - (* RS_HS = "m_axi_out_7_AW.data" *)output [3:0] m_axi_out_7_AWCACHE; - (* RS_HS = "m_axi_out_7_AW.data" *)output [0:0] m_axi_out_7_AWID; - (* RS_HS = "m_axi_out_7_AW.data" *)output [7:0] m_axi_out_7_AWLEN; - (* RS_HS = "m_axi_out_7_AW.data" *)output m_axi_out_7_AWLOCK; - (* RS_HS = "m_axi_out_7_AW.data" *)output [2:0] m_axi_out_7_AWPROT; - (* RS_HS = "m_axi_out_7_AW.data" *)output [3:0] m_axi_out_7_AWQOS; - (* RS_HS = "m_axi_out_7_AW.ready" *)input m_axi_out_7_AWREADY; - (* RS_HS = "m_axi_out_7_AW.data" *)output [2:0] m_axi_out_7_AWSIZE; - (* RS_HS = "m_axi_out_7_AW.valid" *)output m_axi_out_7_AWVALID; - (* RS_HS = "m_axi_out_7_B.data" *)input [0:0] m_axi_out_7_BID; - (* RS_HS = "m_axi_out_7_B.ready" *)output m_axi_out_7_BREADY; - (* RS_HS = "m_axi_out_7_B.data" *)input [1:0] m_axi_out_7_BRESP; - (* RS_HS = "m_axi_out_7_B.valid" *)input m_axi_out_7_BVALID; - (* RS_HS = "m_axi_out_7_R.data" *)input [511:0] m_axi_out_7_RDATA; - (* RS_HS = "m_axi_out_7_R.data" *)input [0:0] m_axi_out_7_RID; - (* RS_HS = "m_axi_out_7_R.data" *)input m_axi_out_7_RLAST; - (* RS_HS = "m_axi_out_7_R.ready" *)output m_axi_out_7_RREADY; - (* RS_HS = "m_axi_out_7_R.data" *)input [1:0] m_axi_out_7_RRESP; - (* RS_HS = "m_axi_out_7_R.valid" *)input m_axi_out_7_RVALID; - (* RS_HS = "m_axi_out_7_W.data" *)output [511:0] m_axi_out_7_WDATA; - (* RS_HS = "m_axi_out_7_W.data" *)output m_axi_out_7_WLAST; - (* RS_HS = "m_axi_out_7_W.ready" *)input m_axi_out_7_WREADY; - (* RS_HS = "m_axi_out_7_W.data" *)output [63:0] m_axi_out_7_WSTRB; - (* RS_HS = "m_axi_out_7_W.valid" *)output m_axi_out_7_WVALID; - (* RS_HS = "m_axi_in_8_AR.data" *)output [63:0] m_axi_in_8_ARADDR; - (* RS_HS = "m_axi_in_8_AR.data" *)output [1:0] m_axi_in_8_ARBURST; - (* RS_HS = "m_axi_in_8_AR.data" *)output [3:0] m_axi_in_8_ARCACHE; - (* RS_HS = "m_axi_in_8_AR.data" *)output [0:0] m_axi_in_8_ARID; - (* RS_HS = "m_axi_in_8_AR.data" *)output [7:0] m_axi_in_8_ARLEN; - (* RS_HS = "m_axi_in_8_AR.data" *)output m_axi_in_8_ARLOCK; - (* RS_HS = "m_axi_in_8_AR.data" *)output [2:0] m_axi_in_8_ARPROT; - (* RS_HS = "m_axi_in_8_AR.data" *)output [3:0] m_axi_in_8_ARQOS; - (* RS_HS = "m_axi_in_8_AR.ready" *)input m_axi_in_8_ARREADY; - (* RS_HS = "m_axi_in_8_AR.data" *)output [2:0] m_axi_in_8_ARSIZE; - (* RS_HS = "m_axi_in_8_AR.valid" *)output m_axi_in_8_ARVALID; - (* RS_HS = "m_axi_in_8_AW.data" *)output [63:0] m_axi_in_8_AWADDR; - (* RS_HS = "m_axi_in_8_AW.data" *)output [1:0] m_axi_in_8_AWBURST; - (* RS_HS = "m_axi_in_8_AW.data" *)output [3:0] m_axi_in_8_AWCACHE; - (* RS_HS = "m_axi_in_8_AW.data" *)output [0:0] m_axi_in_8_AWID; - (* RS_HS = "m_axi_in_8_AW.data" *)output [7:0] m_axi_in_8_AWLEN; - (* RS_HS = "m_axi_in_8_AW.data" *)output m_axi_in_8_AWLOCK; - (* RS_HS = "m_axi_in_8_AW.data" *)output [2:0] m_axi_in_8_AWPROT; - (* RS_HS = "m_axi_in_8_AW.data" *)output [3:0] m_axi_in_8_AWQOS; - (* RS_HS = "m_axi_in_8_AW.ready" *)input m_axi_in_8_AWREADY; - (* RS_HS = "m_axi_in_8_AW.data" *)output [2:0] m_axi_in_8_AWSIZE; - (* RS_HS = "m_axi_in_8_AW.valid" *)output m_axi_in_8_AWVALID; - (* RS_HS = "m_axi_in_8_B.data" *)input [0:0] m_axi_in_8_BID; - (* RS_HS = "m_axi_in_8_B.ready" *)output m_axi_in_8_BREADY; - (* RS_HS = "m_axi_in_8_B.data" *)input [1:0] m_axi_in_8_BRESP; - (* RS_HS = "m_axi_in_8_B.valid" *)input m_axi_in_8_BVALID; - (* RS_HS = "m_axi_in_8_R.data" *)input [511:0] m_axi_in_8_RDATA; - (* RS_HS = "m_axi_in_8_R.data" *)input [0:0] m_axi_in_8_RID; - (* RS_HS = "m_axi_in_8_R.data" *)input m_axi_in_8_RLAST; - (* RS_HS = "m_axi_in_8_R.ready" *)output m_axi_in_8_RREADY; - (* RS_HS = "m_axi_in_8_R.data" *)input [1:0] m_axi_in_8_RRESP; - (* RS_HS = "m_axi_in_8_R.valid" *)input m_axi_in_8_RVALID; - (* RS_HS = "m_axi_in_8_W.data" *)output [511:0] m_axi_in_8_WDATA; - (* RS_HS = "m_axi_in_8_W.data" *)output m_axi_in_8_WLAST; - (* RS_HS = "m_axi_in_8_W.ready" *)input m_axi_in_8_WREADY; - (* RS_HS = "m_axi_in_8_W.data" *)output [63:0] m_axi_in_8_WSTRB; - (* RS_HS = "m_axi_in_8_W.valid" *)output m_axi_in_8_WVALID; - (* RS_HS = "m_axi_out_8_AR.data" *)output [63:0] m_axi_out_8_ARADDR; - (* RS_HS = "m_axi_out_8_AR.data" *)output [1:0] m_axi_out_8_ARBURST; - (* RS_HS = "m_axi_out_8_AR.data" *)output [3:0] m_axi_out_8_ARCACHE; - (* RS_HS = "m_axi_out_8_AR.data" *)output [0:0] m_axi_out_8_ARID; - (* RS_HS = "m_axi_out_8_AR.data" *)output [7:0] m_axi_out_8_ARLEN; - (* RS_HS = "m_axi_out_8_AR.data" *)output m_axi_out_8_ARLOCK; - (* RS_HS = "m_axi_out_8_AR.data" *)output [2:0] m_axi_out_8_ARPROT; - (* RS_HS = "m_axi_out_8_AR.data" *)output [3:0] m_axi_out_8_ARQOS; - (* RS_HS = "m_axi_out_8_AR.ready" *)input m_axi_out_8_ARREADY; - (* RS_HS = "m_axi_out_8_AR.data" *)output [2:0] m_axi_out_8_ARSIZE; - (* RS_HS = "m_axi_out_8_AR.valid" *)output m_axi_out_8_ARVALID; - (* RS_HS = "m_axi_out_8_AW.data" *)output [63:0] m_axi_out_8_AWADDR; - (* RS_HS = "m_axi_out_8_AW.data" *)output [1:0] m_axi_out_8_AWBURST; - (* RS_HS = "m_axi_out_8_AW.data" *)output [3:0] m_axi_out_8_AWCACHE; - (* RS_HS = "m_axi_out_8_AW.data" *)output [0:0] m_axi_out_8_AWID; - (* RS_HS = "m_axi_out_8_AW.data" *)output [7:0] m_axi_out_8_AWLEN; - (* RS_HS = "m_axi_out_8_AW.data" *)output m_axi_out_8_AWLOCK; - (* RS_HS = "m_axi_out_8_AW.data" *)output [2:0] m_axi_out_8_AWPROT; - (* RS_HS = "m_axi_out_8_AW.data" *)output [3:0] m_axi_out_8_AWQOS; - (* RS_HS = "m_axi_out_8_AW.ready" *)input m_axi_out_8_AWREADY; - (* RS_HS = "m_axi_out_8_AW.data" *)output [2:0] m_axi_out_8_AWSIZE; - (* RS_HS = "m_axi_out_8_AW.valid" *)output m_axi_out_8_AWVALID; - (* RS_HS = "m_axi_out_8_B.data" *)input [0:0] m_axi_out_8_BID; - (* RS_HS = "m_axi_out_8_B.ready" *)output m_axi_out_8_BREADY; - (* RS_HS = "m_axi_out_8_B.data" *)input [1:0] m_axi_out_8_BRESP; - (* RS_HS = "m_axi_out_8_B.valid" *)input m_axi_out_8_BVALID; - (* RS_HS = "m_axi_out_8_R.data" *)input [511:0] m_axi_out_8_RDATA; - (* RS_HS = "m_axi_out_8_R.data" *)input [0:0] m_axi_out_8_RID; - (* RS_HS = "m_axi_out_8_R.data" *)input m_axi_out_8_RLAST; - (* RS_HS = "m_axi_out_8_R.ready" *)output m_axi_out_8_RREADY; - (* RS_HS = "m_axi_out_8_R.data" *)input [1:0] m_axi_out_8_RRESP; - (* RS_HS = "m_axi_out_8_R.valid" *)input m_axi_out_8_RVALID; - (* RS_HS = "m_axi_out_8_W.data" *)output [511:0] m_axi_out_8_WDATA; - (* RS_HS = "m_axi_out_8_W.data" *)output m_axi_out_8_WLAST; - (* RS_HS = "m_axi_out_8_W.ready" *)input m_axi_out_8_WREADY; - (* RS_HS = "m_axi_out_8_W.data" *)output [63:0] m_axi_out_8_WSTRB; - (* RS_HS = "m_axi_out_8_W.valid" *)output m_axi_out_8_WVALID; - (* RS_HS = "m_axi_in_9_AR.data" *)output [63:0] m_axi_in_9_ARADDR; - (* RS_HS = "m_axi_in_9_AR.data" *)output [1:0] m_axi_in_9_ARBURST; - (* RS_HS = "m_axi_in_9_AR.data" *)output [3:0] m_axi_in_9_ARCACHE; - (* RS_HS = "m_axi_in_9_AR.data" *)output [0:0] m_axi_in_9_ARID; - (* RS_HS = "m_axi_in_9_AR.data" *)output [7:0] m_axi_in_9_ARLEN; - (* RS_HS = "m_axi_in_9_AR.data" *)output m_axi_in_9_ARLOCK; - (* RS_HS = "m_axi_in_9_AR.data" *)output [2:0] m_axi_in_9_ARPROT; - (* RS_HS = "m_axi_in_9_AR.data" *)output [3:0] m_axi_in_9_ARQOS; - (* RS_HS = "m_axi_in_9_AR.ready" *)input m_axi_in_9_ARREADY; - (* RS_HS = "m_axi_in_9_AR.data" *)output [2:0] m_axi_in_9_ARSIZE; - (* RS_HS = "m_axi_in_9_AR.valid" *)output m_axi_in_9_ARVALID; - (* RS_HS = "m_axi_in_9_AW.data" *)output [63:0] m_axi_in_9_AWADDR; - (* RS_HS = "m_axi_in_9_AW.data" *)output [1:0] m_axi_in_9_AWBURST; - (* RS_HS = "m_axi_in_9_AW.data" *)output [3:0] m_axi_in_9_AWCACHE; - (* RS_HS = "m_axi_in_9_AW.data" *)output [0:0] m_axi_in_9_AWID; - (* RS_HS = "m_axi_in_9_AW.data" *)output [7:0] m_axi_in_9_AWLEN; - (* RS_HS = "m_axi_in_9_AW.data" *)output m_axi_in_9_AWLOCK; - (* RS_HS = "m_axi_in_9_AW.data" *)output [2:0] m_axi_in_9_AWPROT; - (* RS_HS = "m_axi_in_9_AW.data" *)output [3:0] m_axi_in_9_AWQOS; - (* RS_HS = "m_axi_in_9_AW.ready" *)input m_axi_in_9_AWREADY; - (* RS_HS = "m_axi_in_9_AW.data" *)output [2:0] m_axi_in_9_AWSIZE; - (* RS_HS = "m_axi_in_9_AW.valid" *)output m_axi_in_9_AWVALID; - (* RS_HS = "m_axi_in_9_B.data" *)input [0:0] m_axi_in_9_BID; - (* RS_HS = "m_axi_in_9_B.ready" *)output m_axi_in_9_BREADY; - (* RS_HS = "m_axi_in_9_B.data" *)input [1:0] m_axi_in_9_BRESP; - (* RS_HS = "m_axi_in_9_B.valid" *)input m_axi_in_9_BVALID; - (* RS_HS = "m_axi_in_9_R.data" *)input [511:0] m_axi_in_9_RDATA; - (* RS_HS = "m_axi_in_9_R.data" *)input [0:0] m_axi_in_9_RID; - (* RS_HS = "m_axi_in_9_R.data" *)input m_axi_in_9_RLAST; - (* RS_HS = "m_axi_in_9_R.ready" *)output m_axi_in_9_RREADY; - (* RS_HS = "m_axi_in_9_R.data" *)input [1:0] m_axi_in_9_RRESP; - (* RS_HS = "m_axi_in_9_R.valid" *)input m_axi_in_9_RVALID; - (* RS_HS = "m_axi_in_9_W.data" *)output [511:0] m_axi_in_9_WDATA; - (* RS_HS = "m_axi_in_9_W.data" *)output m_axi_in_9_WLAST; - (* RS_HS = "m_axi_in_9_W.ready" *)input m_axi_in_9_WREADY; - (* RS_HS = "m_axi_in_9_W.data" *)output [63:0] m_axi_in_9_WSTRB; - (* RS_HS = "m_axi_in_9_W.valid" *)output m_axi_in_9_WVALID; - (* RS_HS = "m_axi_out_9_AR.data" *)output [63:0] m_axi_out_9_ARADDR; - (* RS_HS = "m_axi_out_9_AR.data" *)output [1:0] m_axi_out_9_ARBURST; - (* RS_HS = "m_axi_out_9_AR.data" *)output [3:0] m_axi_out_9_ARCACHE; - (* RS_HS = "m_axi_out_9_AR.data" *)output [0:0] m_axi_out_9_ARID; - (* RS_HS = "m_axi_out_9_AR.data" *)output [7:0] m_axi_out_9_ARLEN; - (* RS_HS = "m_axi_out_9_AR.data" *)output m_axi_out_9_ARLOCK; - (* RS_HS = "m_axi_out_9_AR.data" *)output [2:0] m_axi_out_9_ARPROT; - (* RS_HS = "m_axi_out_9_AR.data" *)output [3:0] m_axi_out_9_ARQOS; - (* RS_HS = "m_axi_out_9_AR.ready" *)input m_axi_out_9_ARREADY; - (* RS_HS = "m_axi_out_9_AR.data" *)output [2:0] m_axi_out_9_ARSIZE; - (* RS_HS = "m_axi_out_9_AR.valid" *)output m_axi_out_9_ARVALID; - (* RS_HS = "m_axi_out_9_AW.data" *)output [63:0] m_axi_out_9_AWADDR; - (* RS_HS = "m_axi_out_9_AW.data" *)output [1:0] m_axi_out_9_AWBURST; - (* RS_HS = "m_axi_out_9_AW.data" *)output [3:0] m_axi_out_9_AWCACHE; - (* RS_HS = "m_axi_out_9_AW.data" *)output [0:0] m_axi_out_9_AWID; - (* RS_HS = "m_axi_out_9_AW.data" *)output [7:0] m_axi_out_9_AWLEN; - (* RS_HS = "m_axi_out_9_AW.data" *)output m_axi_out_9_AWLOCK; - (* RS_HS = "m_axi_out_9_AW.data" *)output [2:0] m_axi_out_9_AWPROT; - (* RS_HS = "m_axi_out_9_AW.data" *)output [3:0] m_axi_out_9_AWQOS; - (* RS_HS = "m_axi_out_9_AW.ready" *)input m_axi_out_9_AWREADY; - (* RS_HS = "m_axi_out_9_AW.data" *)output [2:0] m_axi_out_9_AWSIZE; - (* RS_HS = "m_axi_out_9_AW.valid" *)output m_axi_out_9_AWVALID; - (* RS_HS = "m_axi_out_9_B.data" *)input [0:0] m_axi_out_9_BID; - (* RS_HS = "m_axi_out_9_B.ready" *)output m_axi_out_9_BREADY; - (* RS_HS = "m_axi_out_9_B.data" *)input [1:0] m_axi_out_9_BRESP; - (* RS_HS = "m_axi_out_9_B.valid" *)input m_axi_out_9_BVALID; - (* RS_HS = "m_axi_out_9_R.data" *)input [511:0] m_axi_out_9_RDATA; - (* RS_HS = "m_axi_out_9_R.data" *)input [0:0] m_axi_out_9_RID; - (* RS_HS = "m_axi_out_9_R.data" *)input m_axi_out_9_RLAST; - (* RS_HS = "m_axi_out_9_R.ready" *)output m_axi_out_9_RREADY; - (* RS_HS = "m_axi_out_9_R.data" *)input [1:0] m_axi_out_9_RRESP; - (* RS_HS = "m_axi_out_9_R.valid" *)input m_axi_out_9_RVALID; - (* RS_HS = "m_axi_out_9_W.data" *)output [511:0] m_axi_out_9_WDATA; - (* RS_HS = "m_axi_out_9_W.data" *)output m_axi_out_9_WLAST; - (* RS_HS = "m_axi_out_9_W.ready" *)input m_axi_out_9_WREADY; - (* RS_HS = "m_axi_out_9_W.data" *)output [63:0] m_axi_out_9_WSTRB; - (* RS_HS = "m_axi_out_9_W.valid" *)output m_axi_out_9_WVALID; - (* RS_HS = "m_axi_in_10_AR.data" *)output [63:0] m_axi_in_10_ARADDR; - (* RS_HS = "m_axi_in_10_AR.data" *)output [1:0] m_axi_in_10_ARBURST; - (* RS_HS = "m_axi_in_10_AR.data" *)output [3:0] m_axi_in_10_ARCACHE; - (* RS_HS = "m_axi_in_10_AR.data" *)output [0:0] m_axi_in_10_ARID; - (* RS_HS = "m_axi_in_10_AR.data" *)output [7:0] m_axi_in_10_ARLEN; - (* RS_HS = "m_axi_in_10_AR.data" *)output m_axi_in_10_ARLOCK; - (* RS_HS = "m_axi_in_10_AR.data" *)output [2:0] m_axi_in_10_ARPROT; - (* RS_HS = "m_axi_in_10_AR.data" *)output [3:0] m_axi_in_10_ARQOS; - (* RS_HS = "m_axi_in_10_AR.ready" *)input m_axi_in_10_ARREADY; - (* RS_HS = "m_axi_in_10_AR.data" *)output [2:0] m_axi_in_10_ARSIZE; - (* RS_HS = "m_axi_in_10_AR.valid" *)output m_axi_in_10_ARVALID; - (* RS_HS = "m_axi_in_10_AW.data" *)output [63:0] m_axi_in_10_AWADDR; - (* RS_HS = "m_axi_in_10_AW.data" *)output [1:0] m_axi_in_10_AWBURST; - (* RS_HS = "m_axi_in_10_AW.data" *)output [3:0] m_axi_in_10_AWCACHE; - (* RS_HS = "m_axi_in_10_AW.data" *)output [0:0] m_axi_in_10_AWID; - (* RS_HS = "m_axi_in_10_AW.data" *)output [7:0] m_axi_in_10_AWLEN; - (* RS_HS = "m_axi_in_10_AW.data" *)output m_axi_in_10_AWLOCK; - (* RS_HS = "m_axi_in_10_AW.data" *)output [2:0] m_axi_in_10_AWPROT; - (* RS_HS = "m_axi_in_10_AW.data" *)output [3:0] m_axi_in_10_AWQOS; - (* RS_HS = "m_axi_in_10_AW.ready" *)input m_axi_in_10_AWREADY; - (* RS_HS = "m_axi_in_10_AW.data" *)output [2:0] m_axi_in_10_AWSIZE; - (* RS_HS = "m_axi_in_10_AW.valid" *)output m_axi_in_10_AWVALID; - (* RS_HS = "m_axi_in_10_B.data" *)input [0:0] m_axi_in_10_BID; - (* RS_HS = "m_axi_in_10_B.ready" *)output m_axi_in_10_BREADY; - (* RS_HS = "m_axi_in_10_B.data" *)input [1:0] m_axi_in_10_BRESP; - (* RS_HS = "m_axi_in_10_B.valid" *)input m_axi_in_10_BVALID; - (* RS_HS = "m_axi_in_10_R.data" *)input [511:0] m_axi_in_10_RDATA; - (* RS_HS = "m_axi_in_10_R.data" *)input [0:0] m_axi_in_10_RID; - (* RS_HS = "m_axi_in_10_R.data" *)input m_axi_in_10_RLAST; - (* RS_HS = "m_axi_in_10_R.ready" *)output m_axi_in_10_RREADY; - (* RS_HS = "m_axi_in_10_R.data" *)input [1:0] m_axi_in_10_RRESP; - (* RS_HS = "m_axi_in_10_R.valid" *)input m_axi_in_10_RVALID; - (* RS_HS = "m_axi_in_10_W.data" *)output [511:0] m_axi_in_10_WDATA; - (* RS_HS = "m_axi_in_10_W.data" *)output m_axi_in_10_WLAST; - (* RS_HS = "m_axi_in_10_W.ready" *)input m_axi_in_10_WREADY; - (* RS_HS = "m_axi_in_10_W.data" *)output [63:0] m_axi_in_10_WSTRB; - (* RS_HS = "m_axi_in_10_W.valid" *)output m_axi_in_10_WVALID; - (* RS_HS = "m_axi_out_10_AR.data" *)output [63:0] m_axi_out_10_ARADDR; - (* RS_HS = "m_axi_out_10_AR.data" *)output [1:0] m_axi_out_10_ARBURST; - (* RS_HS = "m_axi_out_10_AR.data" *)output [3:0] m_axi_out_10_ARCACHE; - (* RS_HS = "m_axi_out_10_AR.data" *)output [0:0] m_axi_out_10_ARID; - (* RS_HS = "m_axi_out_10_AR.data" *)output [7:0] m_axi_out_10_ARLEN; - (* RS_HS = "m_axi_out_10_AR.data" *)output m_axi_out_10_ARLOCK; - (* RS_HS = "m_axi_out_10_AR.data" *)output [2:0] m_axi_out_10_ARPROT; - (* RS_HS = "m_axi_out_10_AR.data" *)output [3:0] m_axi_out_10_ARQOS; - (* RS_HS = "m_axi_out_10_AR.ready" *)input m_axi_out_10_ARREADY; - (* RS_HS = "m_axi_out_10_AR.data" *)output [2:0] m_axi_out_10_ARSIZE; - (* RS_HS = "m_axi_out_10_AR.valid" *)output m_axi_out_10_ARVALID; - (* RS_HS = "m_axi_out_10_AW.data" *)output [63:0] m_axi_out_10_AWADDR; - (* RS_HS = "m_axi_out_10_AW.data" *)output [1:0] m_axi_out_10_AWBURST; - (* RS_HS = "m_axi_out_10_AW.data" *)output [3:0] m_axi_out_10_AWCACHE; - (* RS_HS = "m_axi_out_10_AW.data" *)output [0:0] m_axi_out_10_AWID; - (* RS_HS = "m_axi_out_10_AW.data" *)output [7:0] m_axi_out_10_AWLEN; - (* RS_HS = "m_axi_out_10_AW.data" *)output m_axi_out_10_AWLOCK; - (* RS_HS = "m_axi_out_10_AW.data" *)output [2:0] m_axi_out_10_AWPROT; - (* RS_HS = "m_axi_out_10_AW.data" *)output [3:0] m_axi_out_10_AWQOS; - (* RS_HS = "m_axi_out_10_AW.ready" *)input m_axi_out_10_AWREADY; - (* RS_HS = "m_axi_out_10_AW.data" *)output [2:0] m_axi_out_10_AWSIZE; - (* RS_HS = "m_axi_out_10_AW.valid" *)output m_axi_out_10_AWVALID; - (* RS_HS = "m_axi_out_10_B.data" *)input [0:0] m_axi_out_10_BID; - (* RS_HS = "m_axi_out_10_B.ready" *)output m_axi_out_10_BREADY; - (* RS_HS = "m_axi_out_10_B.data" *)input [1:0] m_axi_out_10_BRESP; - (* RS_HS = "m_axi_out_10_B.valid" *)input m_axi_out_10_BVALID; - (* RS_HS = "m_axi_out_10_R.data" *)input [511:0] m_axi_out_10_RDATA; - (* RS_HS = "m_axi_out_10_R.data" *)input [0:0] m_axi_out_10_RID; - (* RS_HS = "m_axi_out_10_R.data" *)input m_axi_out_10_RLAST; - (* RS_HS = "m_axi_out_10_R.ready" *)output m_axi_out_10_RREADY; - (* RS_HS = "m_axi_out_10_R.data" *)input [1:0] m_axi_out_10_RRESP; - (* RS_HS = "m_axi_out_10_R.valid" *)input m_axi_out_10_RVALID; - (* RS_HS = "m_axi_out_10_W.data" *)output [511:0] m_axi_out_10_WDATA; - (* RS_HS = "m_axi_out_10_W.data" *)output m_axi_out_10_WLAST; - (* RS_HS = "m_axi_out_10_W.ready" *)input m_axi_out_10_WREADY; - (* RS_HS = "m_axi_out_10_W.data" *)output [63:0] m_axi_out_10_WSTRB; - (* RS_HS = "m_axi_out_10_W.valid" *)output m_axi_out_10_WVALID; - (* RS_HS = "m_axi_in_11_AR.data" *)output [63:0] m_axi_in_11_ARADDR; - (* RS_HS = "m_axi_in_11_AR.data" *)output [1:0] m_axi_in_11_ARBURST; - (* RS_HS = "m_axi_in_11_AR.data" *)output [3:0] m_axi_in_11_ARCACHE; - (* RS_HS = "m_axi_in_11_AR.data" *)output [0:0] m_axi_in_11_ARID; - (* RS_HS = "m_axi_in_11_AR.data" *)output [7:0] m_axi_in_11_ARLEN; - (* RS_HS = "m_axi_in_11_AR.data" *)output m_axi_in_11_ARLOCK; - (* RS_HS = "m_axi_in_11_AR.data" *)output [2:0] m_axi_in_11_ARPROT; - (* RS_HS = "m_axi_in_11_AR.data" *)output [3:0] m_axi_in_11_ARQOS; - (* RS_HS = "m_axi_in_11_AR.ready" *)input m_axi_in_11_ARREADY; - (* RS_HS = "m_axi_in_11_AR.data" *)output [2:0] m_axi_in_11_ARSIZE; - (* RS_HS = "m_axi_in_11_AR.valid" *)output m_axi_in_11_ARVALID; - (* RS_HS = "m_axi_in_11_AW.data" *)output [63:0] m_axi_in_11_AWADDR; - (* RS_HS = "m_axi_in_11_AW.data" *)output [1:0] m_axi_in_11_AWBURST; - (* RS_HS = "m_axi_in_11_AW.data" *)output [3:0] m_axi_in_11_AWCACHE; - (* RS_HS = "m_axi_in_11_AW.data" *)output [0:0] m_axi_in_11_AWID; - (* RS_HS = "m_axi_in_11_AW.data" *)output [7:0] m_axi_in_11_AWLEN; - (* RS_HS = "m_axi_in_11_AW.data" *)output m_axi_in_11_AWLOCK; - (* RS_HS = "m_axi_in_11_AW.data" *)output [2:0] m_axi_in_11_AWPROT; - (* RS_HS = "m_axi_in_11_AW.data" *)output [3:0] m_axi_in_11_AWQOS; - (* RS_HS = "m_axi_in_11_AW.ready" *)input m_axi_in_11_AWREADY; - (* RS_HS = "m_axi_in_11_AW.data" *)output [2:0] m_axi_in_11_AWSIZE; - (* RS_HS = "m_axi_in_11_AW.valid" *)output m_axi_in_11_AWVALID; - (* RS_HS = "m_axi_in_11_B.data" *)input [0:0] m_axi_in_11_BID; - (* RS_HS = "m_axi_in_11_B.ready" *)output m_axi_in_11_BREADY; - (* RS_HS = "m_axi_in_11_B.data" *)input [1:0] m_axi_in_11_BRESP; - (* RS_HS = "m_axi_in_11_B.valid" *)input m_axi_in_11_BVALID; - (* RS_HS = "m_axi_in_11_R.data" *)input [511:0] m_axi_in_11_RDATA; - (* RS_HS = "m_axi_in_11_R.data" *)input [0:0] m_axi_in_11_RID; - (* RS_HS = "m_axi_in_11_R.data" *)input m_axi_in_11_RLAST; - (* RS_HS = "m_axi_in_11_R.ready" *)output m_axi_in_11_RREADY; - (* RS_HS = "m_axi_in_11_R.data" *)input [1:0] m_axi_in_11_RRESP; - (* RS_HS = "m_axi_in_11_R.valid" *)input m_axi_in_11_RVALID; - (* RS_HS = "m_axi_in_11_W.data" *)output [511:0] m_axi_in_11_WDATA; - (* RS_HS = "m_axi_in_11_W.data" *)output m_axi_in_11_WLAST; - (* RS_HS = "m_axi_in_11_W.ready" *)input m_axi_in_11_WREADY; - (* RS_HS = "m_axi_in_11_W.data" *)output [63:0] m_axi_in_11_WSTRB; - (* RS_HS = "m_axi_in_11_W.valid" *)output m_axi_in_11_WVALID; - (* RS_HS = "m_axi_out_11_AR.data" *)output [63:0] m_axi_out_11_ARADDR; - (* RS_HS = "m_axi_out_11_AR.data" *)output [1:0] m_axi_out_11_ARBURST; - (* RS_HS = "m_axi_out_11_AR.data" *)output [3:0] m_axi_out_11_ARCACHE; - (* RS_HS = "m_axi_out_11_AR.data" *)output [0:0] m_axi_out_11_ARID; - (* RS_HS = "m_axi_out_11_AR.data" *)output [7:0] m_axi_out_11_ARLEN; - (* RS_HS = "m_axi_out_11_AR.data" *)output m_axi_out_11_ARLOCK; - (* RS_HS = "m_axi_out_11_AR.data" *)output [2:0] m_axi_out_11_ARPROT; - (* RS_HS = "m_axi_out_11_AR.data" *)output [3:0] m_axi_out_11_ARQOS; - (* RS_HS = "m_axi_out_11_AR.ready" *)input m_axi_out_11_ARREADY; - (* RS_HS = "m_axi_out_11_AR.data" *)output [2:0] m_axi_out_11_ARSIZE; - (* RS_HS = "m_axi_out_11_AR.valid" *)output m_axi_out_11_ARVALID; - (* RS_HS = "m_axi_out_11_AW.data" *)output [63:0] m_axi_out_11_AWADDR; - (* RS_HS = "m_axi_out_11_AW.data" *)output [1:0] m_axi_out_11_AWBURST; - (* RS_HS = "m_axi_out_11_AW.data" *)output [3:0] m_axi_out_11_AWCACHE; - (* RS_HS = "m_axi_out_11_AW.data" *)output [0:0] m_axi_out_11_AWID; - (* RS_HS = "m_axi_out_11_AW.data" *)output [7:0] m_axi_out_11_AWLEN; - (* RS_HS = "m_axi_out_11_AW.data" *)output m_axi_out_11_AWLOCK; - (* RS_HS = "m_axi_out_11_AW.data" *)output [2:0] m_axi_out_11_AWPROT; - (* RS_HS = "m_axi_out_11_AW.data" *)output [3:0] m_axi_out_11_AWQOS; - (* RS_HS = "m_axi_out_11_AW.ready" *)input m_axi_out_11_AWREADY; - (* RS_HS = "m_axi_out_11_AW.data" *)output [2:0] m_axi_out_11_AWSIZE; - (* RS_HS = "m_axi_out_11_AW.valid" *)output m_axi_out_11_AWVALID; - (* RS_HS = "m_axi_out_11_B.data" *)input [0:0] m_axi_out_11_BID; - (* RS_HS = "m_axi_out_11_B.ready" *)output m_axi_out_11_BREADY; - (* RS_HS = "m_axi_out_11_B.data" *)input [1:0] m_axi_out_11_BRESP; - (* RS_HS = "m_axi_out_11_B.valid" *)input m_axi_out_11_BVALID; - (* RS_HS = "m_axi_out_11_R.data" *)input [511:0] m_axi_out_11_RDATA; - (* RS_HS = "m_axi_out_11_R.data" *)input [0:0] m_axi_out_11_RID; - (* RS_HS = "m_axi_out_11_R.data" *)input m_axi_out_11_RLAST; - (* RS_HS = "m_axi_out_11_R.ready" *)output m_axi_out_11_RREADY; - (* RS_HS = "m_axi_out_11_R.data" *)input [1:0] m_axi_out_11_RRESP; - (* RS_HS = "m_axi_out_11_R.valid" *)input m_axi_out_11_RVALID; - (* RS_HS = "m_axi_out_11_W.data" *)output [511:0] m_axi_out_11_WDATA; - (* RS_HS = "m_axi_out_11_W.data" *)output m_axi_out_11_WLAST; - (* RS_HS = "m_axi_out_11_W.ready" *)input m_axi_out_11_WREADY; - (* RS_HS = "m_axi_out_11_W.data" *)output [63:0] m_axi_out_11_WSTRB; - (* RS_HS = "m_axi_out_11_W.valid" *)output m_axi_out_11_WVALID; - wire ap_start; - wire [63:0] in_0; - wire [63:0] out_0; - wire [63:0] in_1; - wire [63:0] out_1; - wire [63:0] in_2; - wire [63:0] out_2; - wire [63:0] in_3; - wire [63:0] out_3; - wire [63:0] in_4; - wire [63:0] out_4; - wire [63:0] in_5; - wire [63:0] out_5; - wire [63:0] in_6; - wire [63:0] out_6; - wire [63:0] in_7; - wire [63:0] out_7; - wire [63:0] in_8; - wire [63:0] out_8; - wire [63:0] in_9; - wire [63:0] out_9; - wire [63:0] in_10; - wire [63:0] out_10; - wire [63:0] in_11; - wire [63:0] out_11; - wire [31:0] iters; - wire [512:0] k_rd_unikernel_0__dout; - wire k_rd_unikernel_0__empty_n; - wire k_rd_unikernel_0__read; - wire [512:0] k_rd_unikernel_0__din; - wire k_rd_unikernel_0__full_n; - wire k_rd_unikernel_0__write; - wire [512:0] k_rd_unikernel_10__dout; - wire k_rd_unikernel_10__empty_n; - wire k_rd_unikernel_10__read; - wire [512:0] k_rd_unikernel_10__din; - wire k_rd_unikernel_10__full_n; - wire k_rd_unikernel_10__write; - wire [512:0] k_rd_unikernel_11__dout; - wire k_rd_unikernel_11__empty_n; - wire k_rd_unikernel_11__read; - wire [512:0] k_rd_unikernel_11__din; - wire k_rd_unikernel_11__full_n; - wire k_rd_unikernel_11__write; - wire [512:0] k_rd_unikernel_1__dout; - wire k_rd_unikernel_1__empty_n; - wire k_rd_unikernel_1__read; - wire [512:0] k_rd_unikernel_1__din; - wire k_rd_unikernel_1__full_n; - wire k_rd_unikernel_1__write; - wire [512:0] k_rd_unikernel_2__dout; - wire k_rd_unikernel_2__empty_n; - wire k_rd_unikernel_2__read; - wire [512:0] k_rd_unikernel_2__din; - wire k_rd_unikernel_2__full_n; - wire k_rd_unikernel_2__write; - wire [512:0] k_rd_unikernel_3__dout; - wire k_rd_unikernel_3__empty_n; - wire k_rd_unikernel_3__read; - wire [512:0] k_rd_unikernel_3__din; - wire k_rd_unikernel_3__full_n; - wire k_rd_unikernel_3__write; - wire [512:0] k_rd_unikernel_4__dout; - wire k_rd_unikernel_4__empty_n; - wire k_rd_unikernel_4__read; - wire [512:0] k_rd_unikernel_4__din; - wire k_rd_unikernel_4__full_n; - wire k_rd_unikernel_4__write; - wire [512:0] k_rd_unikernel_5__dout; - wire k_rd_unikernel_5__empty_n; - wire k_rd_unikernel_5__read; - wire [512:0] k_rd_unikernel_5__din; - wire k_rd_unikernel_5__full_n; - wire k_rd_unikernel_5__write; - wire [512:0] k_rd_unikernel_6__dout; - wire k_rd_unikernel_6__empty_n; - wire k_rd_unikernel_6__read; - wire [512:0] k_rd_unikernel_6__din; - wire k_rd_unikernel_6__full_n; - wire k_rd_unikernel_6__write; - wire [512:0] k_rd_unikernel_7__dout; - wire k_rd_unikernel_7__empty_n; - wire k_rd_unikernel_7__read; - wire [512:0] k_rd_unikernel_7__din; - wire k_rd_unikernel_7__full_n; - wire k_rd_unikernel_7__write; - wire [512:0] k_rd_unikernel_8__dout; - wire k_rd_unikernel_8__empty_n; - wire k_rd_unikernel_8__read; - wire [512:0] k_rd_unikernel_8__din; - wire k_rd_unikernel_8__full_n; - wire k_rd_unikernel_8__write; - wire [512:0] k_rd_unikernel_9__dout; - wire k_rd_unikernel_9__empty_n; - wire k_rd_unikernel_9__read; - wire [512:0] k_rd_unikernel_9__din; - wire k_rd_unikernel_9__full_n; - wire k_rd_unikernel_9__write; - wire [512:0] k_wr_unikernel_0__dout; - wire k_wr_unikernel_0__empty_n; - wire k_wr_unikernel_0__read; - wire [512:0] k_wr_unikernel_0__din; - wire k_wr_unikernel_0__full_n; - wire k_wr_unikernel_0__write; - wire [512:0] k_wr_unikernel_10__dout; - wire k_wr_unikernel_10__empty_n; - wire k_wr_unikernel_10__read; - wire [512:0] k_wr_unikernel_10__din; - wire k_wr_unikernel_10__full_n; - wire k_wr_unikernel_10__write; - wire [512:0] k_wr_unikernel_11__dout; - wire k_wr_unikernel_11__empty_n; - wire k_wr_unikernel_11__read; - wire [512:0] k_wr_unikernel_11__din; - wire k_wr_unikernel_11__full_n; - wire k_wr_unikernel_11__write; - wire [512:0] k_wr_unikernel_1__dout; - wire k_wr_unikernel_1__empty_n; - wire k_wr_unikernel_1__read; - wire [512:0] k_wr_unikernel_1__din; - wire k_wr_unikernel_1__full_n; - wire k_wr_unikernel_1__write; - wire [512:0] k_wr_unikernel_2__dout; - wire k_wr_unikernel_2__empty_n; - wire k_wr_unikernel_2__read; - wire [512:0] k_wr_unikernel_2__din; - wire k_wr_unikernel_2__full_n; - wire k_wr_unikernel_2__write; - wire [512:0] k_wr_unikernel_3__dout; - wire k_wr_unikernel_3__empty_n; - wire k_wr_unikernel_3__read; - wire [512:0] k_wr_unikernel_3__din; - wire k_wr_unikernel_3__full_n; - wire k_wr_unikernel_3__write; - wire [512:0] k_wr_unikernel_4__dout; - wire k_wr_unikernel_4__empty_n; - wire k_wr_unikernel_4__read; - wire [512:0] k_wr_unikernel_4__din; - wire k_wr_unikernel_4__full_n; - wire k_wr_unikernel_4__write; - wire [512:0] k_wr_unikernel_5__dout; - wire k_wr_unikernel_5__empty_n; - wire k_wr_unikernel_5__read; - wire [512:0] k_wr_unikernel_5__din; - wire k_wr_unikernel_5__full_n; - wire k_wr_unikernel_5__write; - wire [512:0] k_wr_unikernel_6__dout; - wire k_wr_unikernel_6__empty_n; - wire k_wr_unikernel_6__read; - wire [512:0] k_wr_unikernel_6__din; - wire k_wr_unikernel_6__full_n; - wire k_wr_unikernel_6__write; - wire [512:0] k_wr_unikernel_7__dout; - wire k_wr_unikernel_7__empty_n; - wire k_wr_unikernel_7__read; - wire [512:0] k_wr_unikernel_7__din; - wire k_wr_unikernel_7__full_n; - wire k_wr_unikernel_7__write; - wire [512:0] k_wr_unikernel_8__dout; - wire k_wr_unikernel_8__empty_n; - wire k_wr_unikernel_8__read; - wire [512:0] k_wr_unikernel_8__din; - wire k_wr_unikernel_8__full_n; - wire k_wr_unikernel_8__write; - wire [512:0] k_wr_unikernel_9__dout; - wire k_wr_unikernel_9__empty_n; - wire k_wr_unikernel_9__read; - wire [512:0] k_wr_unikernel_9__din; - wire k_wr_unikernel_9__full_n; - wire k_wr_unikernel_9__write; - wire [31:0] HEAT3D_0___iters__q0; - wire HEAT3D_0__ap_start; - wire HEAT3D_0__ap_ready; - wire HEAT3D_0__ap_done; - wire HEAT3D_0__ap_idle; - wire [31:0] HEAT3D_1___iters__q0; - wire HEAT3D_1__ap_start; - wire HEAT3D_1__ap_ready; - wire HEAT3D_1__ap_done; - wire HEAT3D_1__ap_idle; - wire [31:0] HEAT3D_2___iters__q0; - wire HEAT3D_2__ap_start; - wire HEAT3D_2__ap_ready; - wire HEAT3D_2__ap_done; - wire HEAT3D_2__ap_idle; - wire [31:0] HEAT3D_3___iters__q0; - wire HEAT3D_3__ap_start; - wire HEAT3D_3__ap_ready; - wire HEAT3D_3__ap_done; - wire HEAT3D_3__ap_idle; - wire [31:0] HEAT3D_4___iters__q0; - wire HEAT3D_4__ap_start; - wire HEAT3D_4__ap_ready; - wire HEAT3D_4__ap_done; - wire HEAT3D_4__ap_idle; - wire [31:0] HEAT3D_5___iters__q0; - wire HEAT3D_5__ap_start; - wire HEAT3D_5__ap_ready; - wire HEAT3D_5__ap_done; - wire HEAT3D_5__ap_idle; - wire [31:0] HEAT3D_6___iters__q0; - wire HEAT3D_6__ap_start; - wire HEAT3D_6__ap_ready; - wire HEAT3D_6__ap_done; - wire HEAT3D_6__ap_idle; - wire [31:0] HEAT3D_7___iters__q0; - wire HEAT3D_7__ap_start; - wire HEAT3D_7__ap_ready; - wire HEAT3D_7__ap_done; - wire HEAT3D_7__ap_idle; - wire [31:0] HEAT3D_8___iters__q0; - wire HEAT3D_8__ap_start; - wire HEAT3D_8__ap_ready; - wire HEAT3D_8__ap_done; - wire HEAT3D_8__ap_idle; - wire [31:0] HEAT3D_9___iters__q0; - wire HEAT3D_9__ap_start; - wire HEAT3D_9__ap_ready; - wire HEAT3D_9__ap_done; - wire HEAT3D_9__ap_idle; - wire [31:0] HEAT3D_10___iters__q0; - wire HEAT3D_10__ap_start; - wire HEAT3D_10__ap_ready; - wire HEAT3D_10__ap_done; - wire HEAT3D_10__ap_idle; - wire [31:0] HEAT3D_11___iters__q0; - wire HEAT3D_11__ap_start; - wire HEAT3D_11__ap_ready; - wire HEAT3D_11__ap_done; - wire HEAT3D_11__ap_idle; - wire [63:0] inter_kernel_0___in_0__q0; - wire [63:0] in_0_read_addr__din; - wire in_0_read_addr__full_n; - wire in_0_read_addr__write; - wire [511:0] in_0_read_data__dout; - wire in_0_read_data__empty_n; - wire in_0_read_data__read; - wire [63:0] in_0_write_addr__din; - wire in_0_write_addr__full_n; - wire in_0_write_addr__write; - wire [511:0] in_0_write_data__din; - wire in_0_write_data__full_n; - wire in_0_write_data__write; - wire [7:0] in_0_write_resp__dout; - wire in_0_write_resp__empty_n; - wire in_0_write_resp__read; - wire [31:0] inter_kernel_0___iters__q0; - wire [63:0] inter_kernel_0___out_0__q0; - wire [63:0] out_0_read_addr__din; - wire out_0_read_addr__full_n; - wire out_0_read_addr__write; - wire [511:0] out_0_read_data__dout; - wire out_0_read_data__empty_n; - wire out_0_read_data__read; - wire [63:0] out_0_write_addr__din; - wire out_0_write_addr__full_n; - wire out_0_write_addr__write; - wire [511:0] out_0_write_data__din; - wire out_0_write_data__full_n; - wire out_0_write_data__write; - wire [7:0] out_0_write_resp__dout; - wire out_0_write_resp__empty_n; - wire out_0_write_resp__read; - wire inter_kernel_0__ap_start; - wire inter_kernel_0__ap_ready; - wire inter_kernel_0__ap_done; - wire inter_kernel_0__ap_idle; - wire [63:0] inter_kernel_1___in_1__q0; - wire [63:0] in_1_read_addr__din; - wire in_1_read_addr__full_n; - wire in_1_read_addr__write; - wire [511:0] in_1_read_data__dout; - wire in_1_read_data__empty_n; - wire in_1_read_data__read; - wire [63:0] in_1_write_addr__din; - wire in_1_write_addr__full_n; - wire in_1_write_addr__write; - wire [511:0] in_1_write_data__din; - wire in_1_write_data__full_n; - wire in_1_write_data__write; - wire [7:0] in_1_write_resp__dout; - wire in_1_write_resp__empty_n; - wire in_1_write_resp__read; - wire [31:0] inter_kernel_1___iters__q0; - wire [63:0] inter_kernel_1___out_1__q0; - wire [63:0] out_1_read_addr__din; - wire out_1_read_addr__full_n; - wire out_1_read_addr__write; - wire [511:0] out_1_read_data__dout; - wire out_1_read_data__empty_n; - wire out_1_read_data__read; - wire [63:0] out_1_write_addr__din; - wire out_1_write_addr__full_n; - wire out_1_write_addr__write; - wire [511:0] out_1_write_data__din; - wire out_1_write_data__full_n; - wire out_1_write_data__write; - wire [7:0] out_1_write_resp__dout; - wire out_1_write_resp__empty_n; - wire out_1_write_resp__read; - wire inter_kernel_1__ap_start; - wire inter_kernel_1__ap_ready; - wire inter_kernel_1__ap_done; - wire inter_kernel_1__ap_idle; - wire [63:0] inter_kernel_2___in_2__q0; - wire [63:0] in_2_read_addr__din; - wire in_2_read_addr__full_n; - wire in_2_read_addr__write; - wire [511:0] in_2_read_data__dout; - wire in_2_read_data__empty_n; - wire in_2_read_data__read; - wire [63:0] in_2_write_addr__din; - wire in_2_write_addr__full_n; - wire in_2_write_addr__write; - wire [511:0] in_2_write_data__din; - wire in_2_write_data__full_n; - wire in_2_write_data__write; - wire [7:0] in_2_write_resp__dout; - wire in_2_write_resp__empty_n; - wire in_2_write_resp__read; - wire [31:0] inter_kernel_2___iters__q0; - wire [63:0] inter_kernel_2___out_2__q0; - wire [63:0] out_2_read_addr__din; - wire out_2_read_addr__full_n; - wire out_2_read_addr__write; - wire [511:0] out_2_read_data__dout; - wire out_2_read_data__empty_n; - wire out_2_read_data__read; - wire [63:0] out_2_write_addr__din; - wire out_2_write_addr__full_n; - wire out_2_write_addr__write; - wire [511:0] out_2_write_data__din; - wire out_2_write_data__full_n; - wire out_2_write_data__write; - wire [7:0] out_2_write_resp__dout; - wire out_2_write_resp__empty_n; - wire out_2_write_resp__read; - wire inter_kernel_2__ap_start; - wire inter_kernel_2__ap_ready; - wire inter_kernel_2__ap_done; - wire inter_kernel_2__ap_idle; - wire [63:0] inter_kernel_3___in_3__q0; - wire [63:0] in_3_read_addr__din; - wire in_3_read_addr__full_n; - wire in_3_read_addr__write; - wire [511:0] in_3_read_data__dout; - wire in_3_read_data__empty_n; - wire in_3_read_data__read; - wire [63:0] in_3_write_addr__din; - wire in_3_write_addr__full_n; - wire in_3_write_addr__write; - wire [511:0] in_3_write_data__din; - wire in_3_write_data__full_n; - wire in_3_write_data__write; - wire [7:0] in_3_write_resp__dout; - wire in_3_write_resp__empty_n; - wire in_3_write_resp__read; - wire [31:0] inter_kernel_3___iters__q0; - wire [63:0] inter_kernel_3___out_3__q0; - wire [63:0] out_3_read_addr__din; - wire out_3_read_addr__full_n; - wire out_3_read_addr__write; - wire [511:0] out_3_read_data__dout; - wire out_3_read_data__empty_n; - wire out_3_read_data__read; - wire [63:0] out_3_write_addr__din; - wire out_3_write_addr__full_n; - wire out_3_write_addr__write; - wire [511:0] out_3_write_data__din; - wire out_3_write_data__full_n; - wire out_3_write_data__write; - wire [7:0] out_3_write_resp__dout; - wire out_3_write_resp__empty_n; - wire out_3_write_resp__read; - wire inter_kernel_3__ap_start; - wire inter_kernel_3__ap_ready; - wire inter_kernel_3__ap_done; - wire inter_kernel_3__ap_idle; - wire [63:0] inter_kernel_4___in_4__q0; - wire [63:0] in_4_read_addr__din; - wire in_4_read_addr__full_n; - wire in_4_read_addr__write; - wire [511:0] in_4_read_data__dout; - wire in_4_read_data__empty_n; - wire in_4_read_data__read; - wire [63:0] in_4_write_addr__din; - wire in_4_write_addr__full_n; - wire in_4_write_addr__write; - wire [511:0] in_4_write_data__din; - wire in_4_write_data__full_n; - wire in_4_write_data__write; - wire [7:0] in_4_write_resp__dout; - wire in_4_write_resp__empty_n; - wire in_4_write_resp__read; - wire [31:0] inter_kernel_4___iters__q0; - wire [63:0] inter_kernel_4___out_4__q0; - wire [63:0] out_4_read_addr__din; - wire out_4_read_addr__full_n; - wire out_4_read_addr__write; - wire [511:0] out_4_read_data__dout; - wire out_4_read_data__empty_n; - wire out_4_read_data__read; - wire [63:0] out_4_write_addr__din; - wire out_4_write_addr__full_n; - wire out_4_write_addr__write; - wire [511:0] out_4_write_data__din; - wire out_4_write_data__full_n; - wire out_4_write_data__write; - wire [7:0] out_4_write_resp__dout; - wire out_4_write_resp__empty_n; - wire out_4_write_resp__read; - wire inter_kernel_4__ap_start; - wire inter_kernel_4__ap_ready; - wire inter_kernel_4__ap_done; - wire inter_kernel_4__ap_idle; - wire [63:0] inter_kernel_5___in_5__q0; - wire [63:0] in_5_read_addr__din; - wire in_5_read_addr__full_n; - wire in_5_read_addr__write; - wire [511:0] in_5_read_data__dout; - wire in_5_read_data__empty_n; - wire in_5_read_data__read; - wire [63:0] in_5_write_addr__din; - wire in_5_write_addr__full_n; - wire in_5_write_addr__write; - wire [511:0] in_5_write_data__din; - wire in_5_write_data__full_n; - wire in_5_write_data__write; - wire [7:0] in_5_write_resp__dout; - wire in_5_write_resp__empty_n; - wire in_5_write_resp__read; - wire [31:0] inter_kernel_5___iters__q0; - wire [63:0] inter_kernel_5___out_5__q0; - wire [63:0] out_5_read_addr__din; - wire out_5_read_addr__full_n; - wire out_5_read_addr__write; - wire [511:0] out_5_read_data__dout; - wire out_5_read_data__empty_n; - wire out_5_read_data__read; - wire [63:0] out_5_write_addr__din; - wire out_5_write_addr__full_n; - wire out_5_write_addr__write; - wire [511:0] out_5_write_data__din; - wire out_5_write_data__full_n; - wire out_5_write_data__write; - wire [7:0] out_5_write_resp__dout; - wire out_5_write_resp__empty_n; - wire out_5_write_resp__read; - wire inter_kernel_5__ap_start; - wire inter_kernel_5__ap_ready; - wire inter_kernel_5__ap_done; - wire inter_kernel_5__ap_idle; - wire [63:0] inter_kernel_6___in_6__q0; - wire [63:0] in_6_read_addr__din; - wire in_6_read_addr__full_n; - wire in_6_read_addr__write; - wire [511:0] in_6_read_data__dout; - wire in_6_read_data__empty_n; - wire in_6_read_data__read; - wire [63:0] in_6_write_addr__din; - wire in_6_write_addr__full_n; - wire in_6_write_addr__write; - wire [511:0] in_6_write_data__din; - wire in_6_write_data__full_n; - wire in_6_write_data__write; - wire [7:0] in_6_write_resp__dout; - wire in_6_write_resp__empty_n; - wire in_6_write_resp__read; - wire [31:0] inter_kernel_6___iters__q0; - wire [63:0] inter_kernel_6___out_6__q0; - wire [63:0] out_6_read_addr__din; - wire out_6_read_addr__full_n; - wire out_6_read_addr__write; - wire [511:0] out_6_read_data__dout; - wire out_6_read_data__empty_n; - wire out_6_read_data__read; - wire [63:0] out_6_write_addr__din; - wire out_6_write_addr__full_n; - wire out_6_write_addr__write; - wire [511:0] out_6_write_data__din; - wire out_6_write_data__full_n; - wire out_6_write_data__write; - wire [7:0] out_6_write_resp__dout; - wire out_6_write_resp__empty_n; - wire out_6_write_resp__read; - wire inter_kernel_6__ap_start; - wire inter_kernel_6__ap_ready; - wire inter_kernel_6__ap_done; - wire inter_kernel_6__ap_idle; - wire [63:0] inter_kernel_7___in_7__q0; - wire [63:0] in_7_read_addr__din; - wire in_7_read_addr__full_n; - wire in_7_read_addr__write; - wire [511:0] in_7_read_data__dout; - wire in_7_read_data__empty_n; - wire in_7_read_data__read; - wire [63:0] in_7_write_addr__din; - wire in_7_write_addr__full_n; - wire in_7_write_addr__write; - wire [511:0] in_7_write_data__din; - wire in_7_write_data__full_n; - wire in_7_write_data__write; - wire [7:0] in_7_write_resp__dout; - wire in_7_write_resp__empty_n; - wire in_7_write_resp__read; - wire [31:0] inter_kernel_7___iters__q0; - wire [63:0] inter_kernel_7___out_7__q0; - wire [63:0] out_7_read_addr__din; - wire out_7_read_addr__full_n; - wire out_7_read_addr__write; - wire [511:0] out_7_read_data__dout; - wire out_7_read_data__empty_n; - wire out_7_read_data__read; - wire [63:0] out_7_write_addr__din; - wire out_7_write_addr__full_n; - wire out_7_write_addr__write; - wire [511:0] out_7_write_data__din; - wire out_7_write_data__full_n; - wire out_7_write_data__write; - wire [7:0] out_7_write_resp__dout; - wire out_7_write_resp__empty_n; - wire out_7_write_resp__read; - wire inter_kernel_7__ap_start; - wire inter_kernel_7__ap_ready; - wire inter_kernel_7__ap_done; - wire inter_kernel_7__ap_idle; - wire [63:0] inter_kernel_8___in_8__q0; - wire [63:0] in_8_read_addr__din; - wire in_8_read_addr__full_n; - wire in_8_read_addr__write; - wire [511:0] in_8_read_data__dout; - wire in_8_read_data__empty_n; - wire in_8_read_data__read; - wire [63:0] in_8_write_addr__din; - wire in_8_write_addr__full_n; - wire in_8_write_addr__write; - wire [511:0] in_8_write_data__din; - wire in_8_write_data__full_n; - wire in_8_write_data__write; - wire [7:0] in_8_write_resp__dout; - wire in_8_write_resp__empty_n; - wire in_8_write_resp__read; - wire [31:0] inter_kernel_8___iters__q0; - wire [63:0] inter_kernel_8___out_8__q0; - wire [63:0] out_8_read_addr__din; - wire out_8_read_addr__full_n; - wire out_8_read_addr__write; - wire [511:0] out_8_read_data__dout; - wire out_8_read_data__empty_n; - wire out_8_read_data__read; - wire [63:0] out_8_write_addr__din; - wire out_8_write_addr__full_n; - wire out_8_write_addr__write; - wire [511:0] out_8_write_data__din; - wire out_8_write_data__full_n; - wire out_8_write_data__write; - wire [7:0] out_8_write_resp__dout; - wire out_8_write_resp__empty_n; - wire out_8_write_resp__read; - wire inter_kernel_8__ap_start; - wire inter_kernel_8__ap_ready; - wire inter_kernel_8__ap_done; - wire inter_kernel_8__ap_idle; - wire [63:0] inter_kernel_9___in_9__q0; - wire [63:0] in_9_read_addr__din; - wire in_9_read_addr__full_n; - wire in_9_read_addr__write; - wire [511:0] in_9_read_data__dout; - wire in_9_read_data__empty_n; - wire in_9_read_data__read; - wire [63:0] in_9_write_addr__din; - wire in_9_write_addr__full_n; - wire in_9_write_addr__write; - wire [511:0] in_9_write_data__din; - wire in_9_write_data__full_n; - wire in_9_write_data__write; - wire [7:0] in_9_write_resp__dout; - wire in_9_write_resp__empty_n; - wire in_9_write_resp__read; - wire [31:0] inter_kernel_9___iters__q0; - wire [63:0] inter_kernel_9___out_9__q0; - wire [63:0] out_9_read_addr__din; - wire out_9_read_addr__full_n; - wire out_9_read_addr__write; - wire [511:0] out_9_read_data__dout; - wire out_9_read_data__empty_n; - wire out_9_read_data__read; - wire [63:0] out_9_write_addr__din; - wire out_9_write_addr__full_n; - wire out_9_write_addr__write; - wire [511:0] out_9_write_data__din; - wire out_9_write_data__full_n; - wire out_9_write_data__write; - wire [7:0] out_9_write_resp__dout; - wire out_9_write_resp__empty_n; - wire out_9_write_resp__read; - wire inter_kernel_9__ap_start; - wire inter_kernel_9__ap_ready; - wire inter_kernel_9__ap_done; - wire inter_kernel_9__ap_idle; - wire [63:0] inter_kernel_10___in_10__q0; - wire [63:0] in_10_read_addr__din; - wire in_10_read_addr__full_n; - wire in_10_read_addr__write; - wire [511:0] in_10_read_data__dout; - wire in_10_read_data__empty_n; - wire in_10_read_data__read; - wire [63:0] in_10_write_addr__din; - wire in_10_write_addr__full_n; - wire in_10_write_addr__write; - wire [511:0] in_10_write_data__din; - wire in_10_write_data__full_n; - wire in_10_write_data__write; - wire [7:0] in_10_write_resp__dout; - wire in_10_write_resp__empty_n; - wire in_10_write_resp__read; - wire [31:0] inter_kernel_10___iters__q0; - wire [63:0] inter_kernel_10___out_10__q0; - wire [63:0] out_10_read_addr__din; - wire out_10_read_addr__full_n; - wire out_10_read_addr__write; - wire [511:0] out_10_read_data__dout; - wire out_10_read_data__empty_n; - wire out_10_read_data__read; - wire [63:0] out_10_write_addr__din; - wire out_10_write_addr__full_n; - wire out_10_write_addr__write; - wire [511:0] out_10_write_data__din; - wire out_10_write_data__full_n; - wire out_10_write_data__write; - wire [7:0] out_10_write_resp__dout; - wire out_10_write_resp__empty_n; - wire out_10_write_resp__read; - wire inter_kernel_10__ap_start; - wire inter_kernel_10__ap_ready; - wire inter_kernel_10__ap_done; - wire inter_kernel_10__ap_idle; - wire [63:0] inter_kernel_11___in_11__q0; - wire [63:0] in_11_read_addr__din; - wire in_11_read_addr__full_n; - wire in_11_read_addr__write; - wire [511:0] in_11_read_data__dout; - wire in_11_read_data__empty_n; - wire in_11_read_data__read; - wire [63:0] in_11_write_addr__din; - wire in_11_write_addr__full_n; - wire in_11_write_addr__write; - wire [511:0] in_11_write_data__din; - wire in_11_write_data__full_n; - wire in_11_write_data__write; - wire [7:0] in_11_write_resp__dout; - wire in_11_write_resp__empty_n; - wire in_11_write_resp__read; - wire [31:0] inter_kernel_11___iters__q0; - wire [63:0] inter_kernel_11___out_11__q0; - wire [63:0] out_11_read_addr__din; - wire out_11_read_addr__full_n; - wire out_11_read_addr__write; - wire [511:0] out_11_read_data__dout; - wire out_11_read_data__empty_n; - wire out_11_read_data__read; - wire [63:0] out_11_write_addr__din; - wire out_11_write_addr__full_n; - wire out_11_write_addr__write; - wire [511:0] out_11_write_data__din; - wire out_11_write_data__full_n; - wire out_11_write_data__write; - wire [7:0] out_11_write_resp__dout; - wire out_11_write_resp__empty_n; - wire out_11_write_resp__read; - wire inter_kernel_11__ap_start; - wire inter_kernel_11__ap_ready; - wire inter_kernel_11__ap_done; - wire inter_kernel_11__ap_idle; - wire ap_rst_n_inv; - wire ap_done; - wire ap_idle; - wire ap_ready; - - unikernel_control_s_axi - #( - .C_S_AXI_ADDR_WIDTH(C_S_AXI_CONTROL_ADDR_WIDTH), - .C_S_AXI_DATA_WIDTH(C_S_AXI_CONTROL_DATA_WIDTH) - ) - control_s_axi_U - ( - .AWVALID(s_axi_control_AWVALID), - .AWREADY(s_axi_control_AWREADY), - .AWADDR(s_axi_control_AWADDR), - .WVALID(s_axi_control_WVALID), - .WREADY(s_axi_control_WREADY), - .WDATA(s_axi_control_WDATA), - .WSTRB(s_axi_control_WSTRB), - .ARVALID(s_axi_control_ARVALID), - .ARREADY(s_axi_control_ARREADY), - .ARADDR(s_axi_control_ARADDR), - .RVALID(s_axi_control_RVALID), - .RREADY(s_axi_control_RREADY), - .RDATA(s_axi_control_RDATA), - .RRESP(s_axi_control_RRESP), - .BVALID(s_axi_control_BVALID), - .BREADY(s_axi_control_BREADY), - .BRESP(s_axi_control_BRESP), - .ACLK(ap_clk), - .ARESET(ap_rst_n_inv), - .ACLK_EN(1'b1), - .in_0(in_0), - .out_0(out_0), - .in_1(in_1), - .out_1(out_1), - .in_2(in_2), - .out_2(out_2), - .in_3(in_3), - .out_3(out_3), - .in_4(in_4), - .out_4(out_4), - .in_5(in_5), - .out_5(out_5), - .in_6(in_6), - .out_6(out_6), - .in_7(in_7), - .out_7(out_7), - .in_8(in_8), - .out_8(out_8), - .in_9(in_9), - .out_9(out_9), - .in_10(in_10), - .out_10(out_10), - .in_11(in_11), - .out_11(out_11), - .iters(iters), - .ap_start(ap_start), - .interrupt(interrupt), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_idle(ap_idle) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_0__dout), - .if_empty_n(k_rd_unikernel_0__empty_n), - .if_read(k_rd_unikernel_0__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_0__din), - .if_full_n(k_rd_unikernel_0__full_n), - .if_write(k_rd_unikernel_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_10 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_10__dout), - .if_empty_n(k_rd_unikernel_10__empty_n), - .if_read(k_rd_unikernel_10__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_10__din), - .if_full_n(k_rd_unikernel_10__full_n), - .if_write(k_rd_unikernel_10__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_11 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_11__dout), - .if_empty_n(k_rd_unikernel_11__empty_n), - .if_read(k_rd_unikernel_11__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_11__din), - .if_full_n(k_rd_unikernel_11__full_n), - .if_write(k_rd_unikernel_11__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_1__dout), - .if_empty_n(k_rd_unikernel_1__empty_n), - .if_read(k_rd_unikernel_1__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_1__din), - .if_full_n(k_rd_unikernel_1__full_n), - .if_write(k_rd_unikernel_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_2__dout), - .if_empty_n(k_rd_unikernel_2__empty_n), - .if_read(k_rd_unikernel_2__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_2__din), - .if_full_n(k_rd_unikernel_2__full_n), - .if_write(k_rd_unikernel_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_3__dout), - .if_empty_n(k_rd_unikernel_3__empty_n), - .if_read(k_rd_unikernel_3__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_3__din), - .if_full_n(k_rd_unikernel_3__full_n), - .if_write(k_rd_unikernel_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_4__dout), - .if_empty_n(k_rd_unikernel_4__empty_n), - .if_read(k_rd_unikernel_4__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_4__din), - .if_full_n(k_rd_unikernel_4__full_n), - .if_write(k_rd_unikernel_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_5__dout), - .if_empty_n(k_rd_unikernel_5__empty_n), - .if_read(k_rd_unikernel_5__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_5__din), - .if_full_n(k_rd_unikernel_5__full_n), - .if_write(k_rd_unikernel_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_6__dout), - .if_empty_n(k_rd_unikernel_6__empty_n), - .if_read(k_rd_unikernel_6__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_6__din), - .if_full_n(k_rd_unikernel_6__full_n), - .if_write(k_rd_unikernel_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_7__dout), - .if_empty_n(k_rd_unikernel_7__empty_n), - .if_read(k_rd_unikernel_7__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_7__din), - .if_full_n(k_rd_unikernel_7__full_n), - .if_write(k_rd_unikernel_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_8 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_8__dout), - .if_empty_n(k_rd_unikernel_8__empty_n), - .if_read(k_rd_unikernel_8__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_8__din), - .if_full_n(k_rd_unikernel_8__full_n), - .if_write(k_rd_unikernel_8__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_rd_unikernel_9 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_rd_unikernel_9__dout), - .if_empty_n(k_rd_unikernel_9__empty_n), - .if_read(k_rd_unikernel_9__read), - .if_read_ce(1'b1), - .if_din(k_rd_unikernel_9__din), - .if_full_n(k_rd_unikernel_9__full_n), - .if_write(k_rd_unikernel_9__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_0 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_0__dout), - .if_empty_n(k_wr_unikernel_0__empty_n), - .if_read(k_wr_unikernel_0__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_0__din), - .if_full_n(k_wr_unikernel_0__full_n), - .if_write(k_wr_unikernel_0__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_10 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_10__dout), - .if_empty_n(k_wr_unikernel_10__empty_n), - .if_read(k_wr_unikernel_10__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_10__din), - .if_full_n(k_wr_unikernel_10__full_n), - .if_write(k_wr_unikernel_10__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_11 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_11__dout), - .if_empty_n(k_wr_unikernel_11__empty_n), - .if_read(k_wr_unikernel_11__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_11__din), - .if_full_n(k_wr_unikernel_11__full_n), - .if_write(k_wr_unikernel_11__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_1 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_1__dout), - .if_empty_n(k_wr_unikernel_1__empty_n), - .if_read(k_wr_unikernel_1__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_1__din), - .if_full_n(k_wr_unikernel_1__full_n), - .if_write(k_wr_unikernel_1__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_2 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_2__dout), - .if_empty_n(k_wr_unikernel_2__empty_n), - .if_read(k_wr_unikernel_2__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_2__din), - .if_full_n(k_wr_unikernel_2__full_n), - .if_write(k_wr_unikernel_2__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_3 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_3__dout), - .if_empty_n(k_wr_unikernel_3__empty_n), - .if_read(k_wr_unikernel_3__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_3__din), - .if_full_n(k_wr_unikernel_3__full_n), - .if_write(k_wr_unikernel_3__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_4 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_4__dout), - .if_empty_n(k_wr_unikernel_4__empty_n), - .if_read(k_wr_unikernel_4__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_4__din), - .if_full_n(k_wr_unikernel_4__full_n), - .if_write(k_wr_unikernel_4__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_5 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_5__dout), - .if_empty_n(k_wr_unikernel_5__empty_n), - .if_read(k_wr_unikernel_5__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_5__din), - .if_full_n(k_wr_unikernel_5__full_n), - .if_write(k_wr_unikernel_5__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_6 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_6__dout), - .if_empty_n(k_wr_unikernel_6__empty_n), - .if_read(k_wr_unikernel_6__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_6__din), - .if_full_n(k_wr_unikernel_6__full_n), - .if_write(k_wr_unikernel_6__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_7 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_7__dout), - .if_empty_n(k_wr_unikernel_7__empty_n), - .if_read(k_wr_unikernel_7__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_7__din), - .if_full_n(k_wr_unikernel_7__full_n), - .if_write(k_wr_unikernel_7__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_8 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_8__dout), - .if_empty_n(k_wr_unikernel_8__empty_n), - .if_read(k_wr_unikernel_8__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_8__din), - .if_full_n(k_wr_unikernel_8__full_n), - .if_write(k_wr_unikernel_8__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) fifo - #( - .DATA_WIDTH(513), - .ADDR_WIDTH(2), - .DEPTH(3) - ) - k_wr_unikernel_9 - ( - .clk(ap_clk), - .reset(~ap_rst_n), - .if_dout(k_wr_unikernel_9__dout), - .if_empty_n(k_wr_unikernel_9__empty_n), - .if_read(k_wr_unikernel_9__read), - .if_read_ce(1'b1), - .if_din(k_wr_unikernel_9__din), - .if_full_n(k_wr_unikernel_9__full_n), - .if_write(k_wr_unikernel_9__write), - .if_write_ce(1'b1) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_0__ap_start), - .ap_done(HEAT3D_0__ap_done), - .ap_idle(HEAT3D_0__ap_idle), - .ap_ready(HEAT3D_0__ap_ready), - .iters(HEAT3D_0___iters__q0), - .in_s_dout(k_rd_unikernel_0__dout), - .in_peek_dout(k_rd_unikernel_0__dout), - .in_s_empty_n(k_rd_unikernel_0__empty_n), - .in_peek_empty_n(k_rd_unikernel_0__empty_n), - .in_s_read(k_rd_unikernel_0__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_0__din), - .out_r_full_n(k_wr_unikernel_0__full_n), - .out_r_write(k_wr_unikernel_0__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_1__ap_start), - .ap_done(HEAT3D_1__ap_done), - .ap_idle(HEAT3D_1__ap_idle), - .ap_ready(HEAT3D_1__ap_ready), - .iters(HEAT3D_1___iters__q0), - .in_s_dout(k_rd_unikernel_1__dout), - .in_peek_dout(k_rd_unikernel_1__dout), - .in_s_empty_n(k_rd_unikernel_1__empty_n), - .in_peek_empty_n(k_rd_unikernel_1__empty_n), - .in_s_read(k_rd_unikernel_1__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_1__din), - .out_r_full_n(k_wr_unikernel_1__full_n), - .out_r_write(k_wr_unikernel_1__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_2__ap_start), - .ap_done(HEAT3D_2__ap_done), - .ap_idle(HEAT3D_2__ap_idle), - .ap_ready(HEAT3D_2__ap_ready), - .iters(HEAT3D_2___iters__q0), - .in_s_dout(k_rd_unikernel_2__dout), - .in_peek_dout(k_rd_unikernel_2__dout), - .in_s_empty_n(k_rd_unikernel_2__empty_n), - .in_peek_empty_n(k_rd_unikernel_2__empty_n), - .in_s_read(k_rd_unikernel_2__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_2__din), - .out_r_full_n(k_wr_unikernel_2__full_n), - .out_r_write(k_wr_unikernel_2__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_3__ap_start), - .ap_done(HEAT3D_3__ap_done), - .ap_idle(HEAT3D_3__ap_idle), - .ap_ready(HEAT3D_3__ap_ready), - .iters(HEAT3D_3___iters__q0), - .in_s_dout(k_rd_unikernel_3__dout), - .in_peek_dout(k_rd_unikernel_3__dout), - .in_s_empty_n(k_rd_unikernel_3__empty_n), - .in_peek_empty_n(k_rd_unikernel_3__empty_n), - .in_s_read(k_rd_unikernel_3__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_3__din), - .out_r_full_n(k_wr_unikernel_3__full_n), - .out_r_write(k_wr_unikernel_3__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_4__ap_start), - .ap_done(HEAT3D_4__ap_done), - .ap_idle(HEAT3D_4__ap_idle), - .ap_ready(HEAT3D_4__ap_ready), - .iters(HEAT3D_4___iters__q0), - .in_s_dout(k_rd_unikernel_4__dout), - .in_peek_dout(k_rd_unikernel_4__dout), - .in_s_empty_n(k_rd_unikernel_4__empty_n), - .in_peek_empty_n(k_rd_unikernel_4__empty_n), - .in_s_read(k_rd_unikernel_4__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_4__din), - .out_r_full_n(k_wr_unikernel_4__full_n), - .out_r_write(k_wr_unikernel_4__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_5__ap_start), - .ap_done(HEAT3D_5__ap_done), - .ap_idle(HEAT3D_5__ap_idle), - .ap_ready(HEAT3D_5__ap_ready), - .iters(HEAT3D_5___iters__q0), - .in_s_dout(k_rd_unikernel_5__dout), - .in_peek_dout(k_rd_unikernel_5__dout), - .in_s_empty_n(k_rd_unikernel_5__empty_n), - .in_peek_empty_n(k_rd_unikernel_5__empty_n), - .in_s_read(k_rd_unikernel_5__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_5__din), - .out_r_full_n(k_wr_unikernel_5__full_n), - .out_r_write(k_wr_unikernel_5__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_6__ap_start), - .ap_done(HEAT3D_6__ap_done), - .ap_idle(HEAT3D_6__ap_idle), - .ap_ready(HEAT3D_6__ap_ready), - .iters(HEAT3D_6___iters__q0), - .in_s_dout(k_rd_unikernel_6__dout), - .in_peek_dout(k_rd_unikernel_6__dout), - .in_s_empty_n(k_rd_unikernel_6__empty_n), - .in_peek_empty_n(k_rd_unikernel_6__empty_n), - .in_s_read(k_rd_unikernel_6__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_6__din), - .out_r_full_n(k_wr_unikernel_6__full_n), - .out_r_write(k_wr_unikernel_6__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_7__ap_start), - .ap_done(HEAT3D_7__ap_done), - .ap_idle(HEAT3D_7__ap_idle), - .ap_ready(HEAT3D_7__ap_ready), - .iters(HEAT3D_7___iters__q0), - .in_s_dout(k_rd_unikernel_7__dout), - .in_peek_dout(k_rd_unikernel_7__dout), - .in_s_empty_n(k_rd_unikernel_7__empty_n), - .in_peek_empty_n(k_rd_unikernel_7__empty_n), - .in_s_read(k_rd_unikernel_7__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_7__din), - .out_r_full_n(k_wr_unikernel_7__full_n), - .out_r_write(k_wr_unikernel_7__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_8 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_8__ap_start), - .ap_done(HEAT3D_8__ap_done), - .ap_idle(HEAT3D_8__ap_idle), - .ap_ready(HEAT3D_8__ap_ready), - .iters(HEAT3D_8___iters__q0), - .in_s_dout(k_rd_unikernel_8__dout), - .in_peek_dout(k_rd_unikernel_8__dout), - .in_s_empty_n(k_rd_unikernel_8__empty_n), - .in_peek_empty_n(k_rd_unikernel_8__empty_n), - .in_s_read(k_rd_unikernel_8__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_8__din), - .out_r_full_n(k_wr_unikernel_8__full_n), - .out_r_write(k_wr_unikernel_8__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_9 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_9__ap_start), - .ap_done(HEAT3D_9__ap_done), - .ap_idle(HEAT3D_9__ap_idle), - .ap_ready(HEAT3D_9__ap_ready), - .iters(HEAT3D_9___iters__q0), - .in_s_dout(k_rd_unikernel_9__dout), - .in_peek_dout(k_rd_unikernel_9__dout), - .in_s_empty_n(k_rd_unikernel_9__empty_n), - .in_peek_empty_n(k_rd_unikernel_9__empty_n), - .in_s_read(k_rd_unikernel_9__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_9__din), - .out_r_full_n(k_wr_unikernel_9__full_n), - .out_r_write(k_wr_unikernel_9__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_10 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_10__ap_start), - .ap_done(HEAT3D_10__ap_done), - .ap_idle(HEAT3D_10__ap_idle), - .ap_ready(HEAT3D_10__ap_ready), - .iters(HEAT3D_10___iters__q0), - .in_s_dout(k_rd_unikernel_10__dout), - .in_peek_dout(k_rd_unikernel_10__dout), - .in_s_empty_n(k_rd_unikernel_10__empty_n), - .in_peek_empty_n(k_rd_unikernel_10__empty_n), - .in_s_read(k_rd_unikernel_10__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_10__din), - .out_r_full_n(k_wr_unikernel_10__full_n), - .out_r_write(k_wr_unikernel_10__write) - ); - - - (* keep_hierarchy = "yes" *) HEAT3D - HEAT3D_11 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(HEAT3D_11__ap_start), - .ap_done(HEAT3D_11__ap_done), - .ap_idle(HEAT3D_11__ap_idle), - .ap_ready(HEAT3D_11__ap_ready), - .iters(HEAT3D_11___iters__q0), - .in_s_dout(k_rd_unikernel_11__dout), - .in_peek_dout(k_rd_unikernel_11__dout), - .in_s_empty_n(k_rd_unikernel_11__empty_n), - .in_peek_empty_n(k_rd_unikernel_11__empty_n), - .in_s_read(k_rd_unikernel_11__read), - .in_peek_read(), - .out_r_din(k_wr_unikernel_11__din), - .out_r_full_n(k_wr_unikernel_11__full_n), - .out_r_write(k_wr_unikernel_11__write) - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_0 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_0__ap_start), - .ap_done(inter_kernel_0__ap_done), - .ap_idle(inter_kernel_0__ap_idle), - .ap_ready(inter_kernel_0__ap_ready), - .a_read_addr_din(in_0_read_addr__din), - .a_read_addr_full_n(in_0_read_addr__full_n), - .a_read_addr_write(in_0_read_addr__write), - .a_read_data_s_dout({1'b0, in_0_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_0_read_data__dout}), - .a_read_data_s_empty_n(in_0_read_data__empty_n), - .a_read_data_peek_empty_n(in_0_read_data__empty_n), - .a_read_data_s_read(in_0_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_0_write_addr__din), - .a_write_addr_full_n(in_0_write_addr__full_n), - .a_write_addr_write(in_0_write_addr__write), - .a_write_data_din(in_0_write_data__din), - .a_write_data_full_n(in_0_write_data__full_n), - .a_write_data_write(in_0_write_data__write), - .a_write_resp_s_dout({1'b0, in_0_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_0_write_resp__dout}), - .a_write_resp_s_empty_n(in_0_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_0_write_resp__empty_n), - .a_write_resp_s_read(in_0_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_0___iters__q0), - .stream_out_din(k_rd_unikernel_0__din), - .stream_out_full_n(k_rd_unikernel_0__full_n), - .stream_out_write(k_rd_unikernel_0__write), - .stream_in_s_dout(k_wr_unikernel_0__dout), - .stream_in_peek_dout(k_wr_unikernel_0__dout), - .stream_in_s_empty_n(k_wr_unikernel_0__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_0__empty_n), - .stream_in_s_read(k_wr_unikernel_0__read), - .stream_in_peek_read(), - .b_read_addr_din(out_0_read_addr__din), - .b_read_addr_full_n(out_0_read_addr__full_n), - .b_read_addr_write(out_0_read_addr__write), - .b_read_data_s_dout({1'b0, out_0_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_0_read_data__dout}), - .b_read_data_s_empty_n(out_0_read_data__empty_n), - .b_read_data_peek_empty_n(out_0_read_data__empty_n), - .b_read_data_s_read(out_0_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_0_write_addr__din), - .b_write_addr_full_n(out_0_write_addr__full_n), - .b_write_addr_write(out_0_write_addr__write), - .b_write_data_din(out_0_write_data__din), - .b_write_data_full_n(out_0_write_data__full_n), - .b_write_data_write(out_0_write_data__write), - .b_write_resp_s_dout({1'b0, out_0_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_0_write_resp__dout}), - .b_write_resp_s_empty_n(out_0_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_0_write_resp__empty_n), - .b_write_resp_s_read(out_0_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_1 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_1__ap_start), - .ap_done(inter_kernel_1__ap_done), - .ap_idle(inter_kernel_1__ap_idle), - .ap_ready(inter_kernel_1__ap_ready), - .a_read_addr_din(in_1_read_addr__din), - .a_read_addr_full_n(in_1_read_addr__full_n), - .a_read_addr_write(in_1_read_addr__write), - .a_read_data_s_dout({1'b0, in_1_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_1_read_data__dout}), - .a_read_data_s_empty_n(in_1_read_data__empty_n), - .a_read_data_peek_empty_n(in_1_read_data__empty_n), - .a_read_data_s_read(in_1_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_1_write_addr__din), - .a_write_addr_full_n(in_1_write_addr__full_n), - .a_write_addr_write(in_1_write_addr__write), - .a_write_data_din(in_1_write_data__din), - .a_write_data_full_n(in_1_write_data__full_n), - .a_write_data_write(in_1_write_data__write), - .a_write_resp_s_dout({1'b0, in_1_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_1_write_resp__dout}), - .a_write_resp_s_empty_n(in_1_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_1_write_resp__empty_n), - .a_write_resp_s_read(in_1_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_1___iters__q0), - .stream_out_din(k_rd_unikernel_1__din), - .stream_out_full_n(k_rd_unikernel_1__full_n), - .stream_out_write(k_rd_unikernel_1__write), - .stream_in_s_dout(k_wr_unikernel_1__dout), - .stream_in_peek_dout(k_wr_unikernel_1__dout), - .stream_in_s_empty_n(k_wr_unikernel_1__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_1__empty_n), - .stream_in_s_read(k_wr_unikernel_1__read), - .stream_in_peek_read(), - .b_read_addr_din(out_1_read_addr__din), - .b_read_addr_full_n(out_1_read_addr__full_n), - .b_read_addr_write(out_1_read_addr__write), - .b_read_data_s_dout({1'b0, out_1_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_1_read_data__dout}), - .b_read_data_s_empty_n(out_1_read_data__empty_n), - .b_read_data_peek_empty_n(out_1_read_data__empty_n), - .b_read_data_s_read(out_1_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_1_write_addr__din), - .b_write_addr_full_n(out_1_write_addr__full_n), - .b_write_addr_write(out_1_write_addr__write), - .b_write_data_din(out_1_write_data__din), - .b_write_data_full_n(out_1_write_data__full_n), - .b_write_data_write(out_1_write_data__write), - .b_write_resp_s_dout({1'b0, out_1_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_1_write_resp__dout}), - .b_write_resp_s_empty_n(out_1_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_1_write_resp__empty_n), - .b_write_resp_s_read(out_1_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_2 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_2__ap_start), - .ap_done(inter_kernel_2__ap_done), - .ap_idle(inter_kernel_2__ap_idle), - .ap_ready(inter_kernel_2__ap_ready), - .a_read_addr_din(in_2_read_addr__din), - .a_read_addr_full_n(in_2_read_addr__full_n), - .a_read_addr_write(in_2_read_addr__write), - .a_read_data_s_dout({1'b0, in_2_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_2_read_data__dout}), - .a_read_data_s_empty_n(in_2_read_data__empty_n), - .a_read_data_peek_empty_n(in_2_read_data__empty_n), - .a_read_data_s_read(in_2_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_2_write_addr__din), - .a_write_addr_full_n(in_2_write_addr__full_n), - .a_write_addr_write(in_2_write_addr__write), - .a_write_data_din(in_2_write_data__din), - .a_write_data_full_n(in_2_write_data__full_n), - .a_write_data_write(in_2_write_data__write), - .a_write_resp_s_dout({1'b0, in_2_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_2_write_resp__dout}), - .a_write_resp_s_empty_n(in_2_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_2_write_resp__empty_n), - .a_write_resp_s_read(in_2_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_2___iters__q0), - .stream_out_din(k_rd_unikernel_2__din), - .stream_out_full_n(k_rd_unikernel_2__full_n), - .stream_out_write(k_rd_unikernel_2__write), - .stream_in_s_dout(k_wr_unikernel_2__dout), - .stream_in_peek_dout(k_wr_unikernel_2__dout), - .stream_in_s_empty_n(k_wr_unikernel_2__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_2__empty_n), - .stream_in_s_read(k_wr_unikernel_2__read), - .stream_in_peek_read(), - .b_read_addr_din(out_2_read_addr__din), - .b_read_addr_full_n(out_2_read_addr__full_n), - .b_read_addr_write(out_2_read_addr__write), - .b_read_data_s_dout({1'b0, out_2_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_2_read_data__dout}), - .b_read_data_s_empty_n(out_2_read_data__empty_n), - .b_read_data_peek_empty_n(out_2_read_data__empty_n), - .b_read_data_s_read(out_2_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_2_write_addr__din), - .b_write_addr_full_n(out_2_write_addr__full_n), - .b_write_addr_write(out_2_write_addr__write), - .b_write_data_din(out_2_write_data__din), - .b_write_data_full_n(out_2_write_data__full_n), - .b_write_data_write(out_2_write_data__write), - .b_write_resp_s_dout({1'b0, out_2_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_2_write_resp__dout}), - .b_write_resp_s_empty_n(out_2_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_2_write_resp__empty_n), - .b_write_resp_s_read(out_2_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_3 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_3__ap_start), - .ap_done(inter_kernel_3__ap_done), - .ap_idle(inter_kernel_3__ap_idle), - .ap_ready(inter_kernel_3__ap_ready), - .a_read_addr_din(in_3_read_addr__din), - .a_read_addr_full_n(in_3_read_addr__full_n), - .a_read_addr_write(in_3_read_addr__write), - .a_read_data_s_dout({1'b0, in_3_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_3_read_data__dout}), - .a_read_data_s_empty_n(in_3_read_data__empty_n), - .a_read_data_peek_empty_n(in_3_read_data__empty_n), - .a_read_data_s_read(in_3_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_3_write_addr__din), - .a_write_addr_full_n(in_3_write_addr__full_n), - .a_write_addr_write(in_3_write_addr__write), - .a_write_data_din(in_3_write_data__din), - .a_write_data_full_n(in_3_write_data__full_n), - .a_write_data_write(in_3_write_data__write), - .a_write_resp_s_dout({1'b0, in_3_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_3_write_resp__dout}), - .a_write_resp_s_empty_n(in_3_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_3_write_resp__empty_n), - .a_write_resp_s_read(in_3_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_3___iters__q0), - .stream_out_din(k_rd_unikernel_3__din), - .stream_out_full_n(k_rd_unikernel_3__full_n), - .stream_out_write(k_rd_unikernel_3__write), - .stream_in_s_dout(k_wr_unikernel_3__dout), - .stream_in_peek_dout(k_wr_unikernel_3__dout), - .stream_in_s_empty_n(k_wr_unikernel_3__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_3__empty_n), - .stream_in_s_read(k_wr_unikernel_3__read), - .stream_in_peek_read(), - .b_read_addr_din(out_3_read_addr__din), - .b_read_addr_full_n(out_3_read_addr__full_n), - .b_read_addr_write(out_3_read_addr__write), - .b_read_data_s_dout({1'b0, out_3_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_3_read_data__dout}), - .b_read_data_s_empty_n(out_3_read_data__empty_n), - .b_read_data_peek_empty_n(out_3_read_data__empty_n), - .b_read_data_s_read(out_3_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_3_write_addr__din), - .b_write_addr_full_n(out_3_write_addr__full_n), - .b_write_addr_write(out_3_write_addr__write), - .b_write_data_din(out_3_write_data__din), - .b_write_data_full_n(out_3_write_data__full_n), - .b_write_data_write(out_3_write_data__write), - .b_write_resp_s_dout({1'b0, out_3_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_3_write_resp__dout}), - .b_write_resp_s_empty_n(out_3_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_3_write_resp__empty_n), - .b_write_resp_s_read(out_3_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_4 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_4__ap_start), - .ap_done(inter_kernel_4__ap_done), - .ap_idle(inter_kernel_4__ap_idle), - .ap_ready(inter_kernel_4__ap_ready), - .a_read_addr_din(in_4_read_addr__din), - .a_read_addr_full_n(in_4_read_addr__full_n), - .a_read_addr_write(in_4_read_addr__write), - .a_read_data_s_dout({1'b0, in_4_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_4_read_data__dout}), - .a_read_data_s_empty_n(in_4_read_data__empty_n), - .a_read_data_peek_empty_n(in_4_read_data__empty_n), - .a_read_data_s_read(in_4_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_4_write_addr__din), - .a_write_addr_full_n(in_4_write_addr__full_n), - .a_write_addr_write(in_4_write_addr__write), - .a_write_data_din(in_4_write_data__din), - .a_write_data_full_n(in_4_write_data__full_n), - .a_write_data_write(in_4_write_data__write), - .a_write_resp_s_dout({1'b0, in_4_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_4_write_resp__dout}), - .a_write_resp_s_empty_n(in_4_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_4_write_resp__empty_n), - .a_write_resp_s_read(in_4_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_4___iters__q0), - .stream_out_din(k_rd_unikernel_4__din), - .stream_out_full_n(k_rd_unikernel_4__full_n), - .stream_out_write(k_rd_unikernel_4__write), - .stream_in_s_dout(k_wr_unikernel_4__dout), - .stream_in_peek_dout(k_wr_unikernel_4__dout), - .stream_in_s_empty_n(k_wr_unikernel_4__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_4__empty_n), - .stream_in_s_read(k_wr_unikernel_4__read), - .stream_in_peek_read(), - .b_read_addr_din(out_4_read_addr__din), - .b_read_addr_full_n(out_4_read_addr__full_n), - .b_read_addr_write(out_4_read_addr__write), - .b_read_data_s_dout({1'b0, out_4_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_4_read_data__dout}), - .b_read_data_s_empty_n(out_4_read_data__empty_n), - .b_read_data_peek_empty_n(out_4_read_data__empty_n), - .b_read_data_s_read(out_4_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_4_write_addr__din), - .b_write_addr_full_n(out_4_write_addr__full_n), - .b_write_addr_write(out_4_write_addr__write), - .b_write_data_din(out_4_write_data__din), - .b_write_data_full_n(out_4_write_data__full_n), - .b_write_data_write(out_4_write_data__write), - .b_write_resp_s_dout({1'b0, out_4_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_4_write_resp__dout}), - .b_write_resp_s_empty_n(out_4_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_4_write_resp__empty_n), - .b_write_resp_s_read(out_4_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_5 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_5__ap_start), - .ap_done(inter_kernel_5__ap_done), - .ap_idle(inter_kernel_5__ap_idle), - .ap_ready(inter_kernel_5__ap_ready), - .a_read_addr_din(in_5_read_addr__din), - .a_read_addr_full_n(in_5_read_addr__full_n), - .a_read_addr_write(in_5_read_addr__write), - .a_read_data_s_dout({1'b0, in_5_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_5_read_data__dout}), - .a_read_data_s_empty_n(in_5_read_data__empty_n), - .a_read_data_peek_empty_n(in_5_read_data__empty_n), - .a_read_data_s_read(in_5_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_5_write_addr__din), - .a_write_addr_full_n(in_5_write_addr__full_n), - .a_write_addr_write(in_5_write_addr__write), - .a_write_data_din(in_5_write_data__din), - .a_write_data_full_n(in_5_write_data__full_n), - .a_write_data_write(in_5_write_data__write), - .a_write_resp_s_dout({1'b0, in_5_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_5_write_resp__dout}), - .a_write_resp_s_empty_n(in_5_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_5_write_resp__empty_n), - .a_write_resp_s_read(in_5_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_5___iters__q0), - .stream_out_din(k_rd_unikernel_5__din), - .stream_out_full_n(k_rd_unikernel_5__full_n), - .stream_out_write(k_rd_unikernel_5__write), - .stream_in_s_dout(k_wr_unikernel_5__dout), - .stream_in_peek_dout(k_wr_unikernel_5__dout), - .stream_in_s_empty_n(k_wr_unikernel_5__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_5__empty_n), - .stream_in_s_read(k_wr_unikernel_5__read), - .stream_in_peek_read(), - .b_read_addr_din(out_5_read_addr__din), - .b_read_addr_full_n(out_5_read_addr__full_n), - .b_read_addr_write(out_5_read_addr__write), - .b_read_data_s_dout({1'b0, out_5_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_5_read_data__dout}), - .b_read_data_s_empty_n(out_5_read_data__empty_n), - .b_read_data_peek_empty_n(out_5_read_data__empty_n), - .b_read_data_s_read(out_5_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_5_write_addr__din), - .b_write_addr_full_n(out_5_write_addr__full_n), - .b_write_addr_write(out_5_write_addr__write), - .b_write_data_din(out_5_write_data__din), - .b_write_data_full_n(out_5_write_data__full_n), - .b_write_data_write(out_5_write_data__write), - .b_write_resp_s_dout({1'b0, out_5_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_5_write_resp__dout}), - .b_write_resp_s_empty_n(out_5_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_5_write_resp__empty_n), - .b_write_resp_s_read(out_5_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_6 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_6__ap_start), - .ap_done(inter_kernel_6__ap_done), - .ap_idle(inter_kernel_6__ap_idle), - .ap_ready(inter_kernel_6__ap_ready), - .a_read_addr_din(in_6_read_addr__din), - .a_read_addr_full_n(in_6_read_addr__full_n), - .a_read_addr_write(in_6_read_addr__write), - .a_read_data_s_dout({1'b0, in_6_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_6_read_data__dout}), - .a_read_data_s_empty_n(in_6_read_data__empty_n), - .a_read_data_peek_empty_n(in_6_read_data__empty_n), - .a_read_data_s_read(in_6_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_6_write_addr__din), - .a_write_addr_full_n(in_6_write_addr__full_n), - .a_write_addr_write(in_6_write_addr__write), - .a_write_data_din(in_6_write_data__din), - .a_write_data_full_n(in_6_write_data__full_n), - .a_write_data_write(in_6_write_data__write), - .a_write_resp_s_dout({1'b0, in_6_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_6_write_resp__dout}), - .a_write_resp_s_empty_n(in_6_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_6_write_resp__empty_n), - .a_write_resp_s_read(in_6_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_6___iters__q0), - .stream_out_din(k_rd_unikernel_6__din), - .stream_out_full_n(k_rd_unikernel_6__full_n), - .stream_out_write(k_rd_unikernel_6__write), - .stream_in_s_dout(k_wr_unikernel_6__dout), - .stream_in_peek_dout(k_wr_unikernel_6__dout), - .stream_in_s_empty_n(k_wr_unikernel_6__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_6__empty_n), - .stream_in_s_read(k_wr_unikernel_6__read), - .stream_in_peek_read(), - .b_read_addr_din(out_6_read_addr__din), - .b_read_addr_full_n(out_6_read_addr__full_n), - .b_read_addr_write(out_6_read_addr__write), - .b_read_data_s_dout({1'b0, out_6_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_6_read_data__dout}), - .b_read_data_s_empty_n(out_6_read_data__empty_n), - .b_read_data_peek_empty_n(out_6_read_data__empty_n), - .b_read_data_s_read(out_6_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_6_write_addr__din), - .b_write_addr_full_n(out_6_write_addr__full_n), - .b_write_addr_write(out_6_write_addr__write), - .b_write_data_din(out_6_write_data__din), - .b_write_data_full_n(out_6_write_data__full_n), - .b_write_data_write(out_6_write_data__write), - .b_write_resp_s_dout({1'b0, out_6_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_6_write_resp__dout}), - .b_write_resp_s_empty_n(out_6_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_6_write_resp__empty_n), - .b_write_resp_s_read(out_6_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_7 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_7__ap_start), - .ap_done(inter_kernel_7__ap_done), - .ap_idle(inter_kernel_7__ap_idle), - .ap_ready(inter_kernel_7__ap_ready), - .a_read_addr_din(in_7_read_addr__din), - .a_read_addr_full_n(in_7_read_addr__full_n), - .a_read_addr_write(in_7_read_addr__write), - .a_read_data_s_dout({1'b0, in_7_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_7_read_data__dout}), - .a_read_data_s_empty_n(in_7_read_data__empty_n), - .a_read_data_peek_empty_n(in_7_read_data__empty_n), - .a_read_data_s_read(in_7_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_7_write_addr__din), - .a_write_addr_full_n(in_7_write_addr__full_n), - .a_write_addr_write(in_7_write_addr__write), - .a_write_data_din(in_7_write_data__din), - .a_write_data_full_n(in_7_write_data__full_n), - .a_write_data_write(in_7_write_data__write), - .a_write_resp_s_dout({1'b0, in_7_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_7_write_resp__dout}), - .a_write_resp_s_empty_n(in_7_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_7_write_resp__empty_n), - .a_write_resp_s_read(in_7_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_7___iters__q0), - .stream_out_din(k_rd_unikernel_7__din), - .stream_out_full_n(k_rd_unikernel_7__full_n), - .stream_out_write(k_rd_unikernel_7__write), - .stream_in_s_dout(k_wr_unikernel_7__dout), - .stream_in_peek_dout(k_wr_unikernel_7__dout), - .stream_in_s_empty_n(k_wr_unikernel_7__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_7__empty_n), - .stream_in_s_read(k_wr_unikernel_7__read), - .stream_in_peek_read(), - .b_read_addr_din(out_7_read_addr__din), - .b_read_addr_full_n(out_7_read_addr__full_n), - .b_read_addr_write(out_7_read_addr__write), - .b_read_data_s_dout({1'b0, out_7_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_7_read_data__dout}), - .b_read_data_s_empty_n(out_7_read_data__empty_n), - .b_read_data_peek_empty_n(out_7_read_data__empty_n), - .b_read_data_s_read(out_7_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_7_write_addr__din), - .b_write_addr_full_n(out_7_write_addr__full_n), - .b_write_addr_write(out_7_write_addr__write), - .b_write_data_din(out_7_write_data__din), - .b_write_data_full_n(out_7_write_data__full_n), - .b_write_data_write(out_7_write_data__write), - .b_write_resp_s_dout({1'b0, out_7_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_7_write_resp__dout}), - .b_write_resp_s_empty_n(out_7_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_7_write_resp__empty_n), - .b_write_resp_s_read(out_7_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_8 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_8__ap_start), - .ap_done(inter_kernel_8__ap_done), - .ap_idle(inter_kernel_8__ap_idle), - .ap_ready(inter_kernel_8__ap_ready), - .a_read_addr_din(in_8_read_addr__din), - .a_read_addr_full_n(in_8_read_addr__full_n), - .a_read_addr_write(in_8_read_addr__write), - .a_read_data_s_dout({1'b0, in_8_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_8_read_data__dout}), - .a_read_data_s_empty_n(in_8_read_data__empty_n), - .a_read_data_peek_empty_n(in_8_read_data__empty_n), - .a_read_data_s_read(in_8_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_8_write_addr__din), - .a_write_addr_full_n(in_8_write_addr__full_n), - .a_write_addr_write(in_8_write_addr__write), - .a_write_data_din(in_8_write_data__din), - .a_write_data_full_n(in_8_write_data__full_n), - .a_write_data_write(in_8_write_data__write), - .a_write_resp_s_dout({1'b0, in_8_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_8_write_resp__dout}), - .a_write_resp_s_empty_n(in_8_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_8_write_resp__empty_n), - .a_write_resp_s_read(in_8_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_8___iters__q0), - .stream_out_din(k_rd_unikernel_8__din), - .stream_out_full_n(k_rd_unikernel_8__full_n), - .stream_out_write(k_rd_unikernel_8__write), - .stream_in_s_dout(k_wr_unikernel_8__dout), - .stream_in_peek_dout(k_wr_unikernel_8__dout), - .stream_in_s_empty_n(k_wr_unikernel_8__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_8__empty_n), - .stream_in_s_read(k_wr_unikernel_8__read), - .stream_in_peek_read(), - .b_read_addr_din(out_8_read_addr__din), - .b_read_addr_full_n(out_8_read_addr__full_n), - .b_read_addr_write(out_8_read_addr__write), - .b_read_data_s_dout({1'b0, out_8_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_8_read_data__dout}), - .b_read_data_s_empty_n(out_8_read_data__empty_n), - .b_read_data_peek_empty_n(out_8_read_data__empty_n), - .b_read_data_s_read(out_8_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_8_write_addr__din), - .b_write_addr_full_n(out_8_write_addr__full_n), - .b_write_addr_write(out_8_write_addr__write), - .b_write_data_din(out_8_write_data__din), - .b_write_data_full_n(out_8_write_data__full_n), - .b_write_data_write(out_8_write_data__write), - .b_write_resp_s_dout({1'b0, out_8_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_8_write_resp__dout}), - .b_write_resp_s_empty_n(out_8_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_8_write_resp__empty_n), - .b_write_resp_s_read(out_8_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_9 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_9__ap_start), - .ap_done(inter_kernel_9__ap_done), - .ap_idle(inter_kernel_9__ap_idle), - .ap_ready(inter_kernel_9__ap_ready), - .a_read_addr_din(in_9_read_addr__din), - .a_read_addr_full_n(in_9_read_addr__full_n), - .a_read_addr_write(in_9_read_addr__write), - .a_read_data_s_dout({1'b0, in_9_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_9_read_data__dout}), - .a_read_data_s_empty_n(in_9_read_data__empty_n), - .a_read_data_peek_empty_n(in_9_read_data__empty_n), - .a_read_data_s_read(in_9_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_9_write_addr__din), - .a_write_addr_full_n(in_9_write_addr__full_n), - .a_write_addr_write(in_9_write_addr__write), - .a_write_data_din(in_9_write_data__din), - .a_write_data_full_n(in_9_write_data__full_n), - .a_write_data_write(in_9_write_data__write), - .a_write_resp_s_dout({1'b0, in_9_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_9_write_resp__dout}), - .a_write_resp_s_empty_n(in_9_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_9_write_resp__empty_n), - .a_write_resp_s_read(in_9_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_9___iters__q0), - .stream_out_din(k_rd_unikernel_9__din), - .stream_out_full_n(k_rd_unikernel_9__full_n), - .stream_out_write(k_rd_unikernel_9__write), - .stream_in_s_dout(k_wr_unikernel_9__dout), - .stream_in_peek_dout(k_wr_unikernel_9__dout), - .stream_in_s_empty_n(k_wr_unikernel_9__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_9__empty_n), - .stream_in_s_read(k_wr_unikernel_9__read), - .stream_in_peek_read(), - .b_read_addr_din(out_9_read_addr__din), - .b_read_addr_full_n(out_9_read_addr__full_n), - .b_read_addr_write(out_9_read_addr__write), - .b_read_data_s_dout({1'b0, out_9_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_9_read_data__dout}), - .b_read_data_s_empty_n(out_9_read_data__empty_n), - .b_read_data_peek_empty_n(out_9_read_data__empty_n), - .b_read_data_s_read(out_9_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_9_write_addr__din), - .b_write_addr_full_n(out_9_write_addr__full_n), - .b_write_addr_write(out_9_write_addr__write), - .b_write_data_din(out_9_write_data__din), - .b_write_data_full_n(out_9_write_data__full_n), - .b_write_data_write(out_9_write_data__write), - .b_write_resp_s_dout({1'b0, out_9_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_9_write_resp__dout}), - .b_write_resp_s_empty_n(out_9_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_9_write_resp__empty_n), - .b_write_resp_s_read(out_9_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_10 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_10__ap_start), - .ap_done(inter_kernel_10__ap_done), - .ap_idle(inter_kernel_10__ap_idle), - .ap_ready(inter_kernel_10__ap_ready), - .a_read_addr_din(in_10_read_addr__din), - .a_read_addr_full_n(in_10_read_addr__full_n), - .a_read_addr_write(in_10_read_addr__write), - .a_read_data_s_dout({1'b0, in_10_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_10_read_data__dout}), - .a_read_data_s_empty_n(in_10_read_data__empty_n), - .a_read_data_peek_empty_n(in_10_read_data__empty_n), - .a_read_data_s_read(in_10_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_10_write_addr__din), - .a_write_addr_full_n(in_10_write_addr__full_n), - .a_write_addr_write(in_10_write_addr__write), - .a_write_data_din(in_10_write_data__din), - .a_write_data_full_n(in_10_write_data__full_n), - .a_write_data_write(in_10_write_data__write), - .a_write_resp_s_dout({1'b0, in_10_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_10_write_resp__dout}), - .a_write_resp_s_empty_n(in_10_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_10_write_resp__empty_n), - .a_write_resp_s_read(in_10_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_10___iters__q0), - .stream_out_din(k_rd_unikernel_10__din), - .stream_out_full_n(k_rd_unikernel_10__full_n), - .stream_out_write(k_rd_unikernel_10__write), - .stream_in_s_dout(k_wr_unikernel_10__dout), - .stream_in_peek_dout(k_wr_unikernel_10__dout), - .stream_in_s_empty_n(k_wr_unikernel_10__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_10__empty_n), - .stream_in_s_read(k_wr_unikernel_10__read), - .stream_in_peek_read(), - .b_read_addr_din(out_10_read_addr__din), - .b_read_addr_full_n(out_10_read_addr__full_n), - .b_read_addr_write(out_10_read_addr__write), - .b_read_data_s_dout({1'b0, out_10_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_10_read_data__dout}), - .b_read_data_s_empty_n(out_10_read_data__empty_n), - .b_read_data_peek_empty_n(out_10_read_data__empty_n), - .b_read_data_s_read(out_10_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_10_write_addr__din), - .b_write_addr_full_n(out_10_write_addr__full_n), - .b_write_addr_write(out_10_write_addr__write), - .b_write_data_din(out_10_write_data__din), - .b_write_data_full_n(out_10_write_data__full_n), - .b_write_data_write(out_10_write_data__write), - .b_write_resp_s_dout({1'b0, out_10_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_10_write_resp__dout}), - .b_write_resp_s_empty_n(out_10_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_10_write_resp__empty_n), - .b_write_resp_s_read(out_10_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) inter_kernel - inter_kernel_11 - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(inter_kernel_11__ap_start), - .ap_done(inter_kernel_11__ap_done), - .ap_idle(inter_kernel_11__ap_idle), - .ap_ready(inter_kernel_11__ap_ready), - .a_read_addr_din(in_11_read_addr__din), - .a_read_addr_full_n(in_11_read_addr__full_n), - .a_read_addr_write(in_11_read_addr__write), - .a_read_data_s_dout({1'b0, in_11_read_data__dout}), - .a_read_data_peek_dout({1'b0, in_11_read_data__dout}), - .a_read_data_s_empty_n(in_11_read_data__empty_n), - .a_read_data_peek_empty_n(in_11_read_data__empty_n), - .a_read_data_s_read(in_11_read_data__read), - .a_read_data_peek_read(), - .a_write_addr_din(in_11_write_addr__din), - .a_write_addr_full_n(in_11_write_addr__full_n), - .a_write_addr_write(in_11_write_addr__write), - .a_write_data_din(in_11_write_data__din), - .a_write_data_full_n(in_11_write_data__full_n), - .a_write_data_write(in_11_write_data__write), - .a_write_resp_s_dout({1'b0, in_11_write_resp__dout}), - .a_write_resp_peek_dout({1'b0, in_11_write_resp__dout}), - .a_write_resp_s_empty_n(in_11_write_resp__empty_n), - .a_write_resp_peek_empty_n(in_11_write_resp__empty_n), - .a_write_resp_s_read(in_11_write_resp__read), - .a_write_resp_peek_read(), - .iters(inter_kernel_11___iters__q0), - .stream_out_din(k_rd_unikernel_11__din), - .stream_out_full_n(k_rd_unikernel_11__full_n), - .stream_out_write(k_rd_unikernel_11__write), - .stream_in_s_dout(k_wr_unikernel_11__dout), - .stream_in_peek_dout(k_wr_unikernel_11__dout), - .stream_in_s_empty_n(k_wr_unikernel_11__empty_n), - .stream_in_peek_empty_n(k_wr_unikernel_11__empty_n), - .stream_in_s_read(k_wr_unikernel_11__read), - .stream_in_peek_read(), - .b_read_addr_din(out_11_read_addr__din), - .b_read_addr_full_n(out_11_read_addr__full_n), - .b_read_addr_write(out_11_read_addr__write), - .b_read_data_s_dout({1'b0, out_11_read_data__dout}), - .b_read_data_peek_dout({1'b0, out_11_read_data__dout}), - .b_read_data_s_empty_n(out_11_read_data__empty_n), - .b_read_data_peek_empty_n(out_11_read_data__empty_n), - .b_read_data_s_read(out_11_read_data__read), - .b_read_data_peek_read(), - .b_write_addr_din(out_11_write_addr__din), - .b_write_addr_full_n(out_11_write_addr__full_n), - .b_write_addr_write(out_11_write_addr__write), - .b_write_data_din(out_11_write_data__din), - .b_write_data_full_n(out_11_write_data__full_n), - .b_write_data_write(out_11_write_data__write), - .b_write_resp_s_dout({1'b0, out_11_write_resp__dout}), - .b_write_resp_peek_dout({1'b0, out_11_write_resp__dout}), - .b_write_resp_s_empty_n(out_11_write_resp__empty_n), - .b_write_resp_peek_empty_n(out_11_write_resp__empty_n), - .b_write_resp_s_read(out_11_write_resp__read), - .b_write_resp_peek_read() - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_0__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_0___in_0__q0), - .m_axi_ARADDR(m_axi_in_0_ARADDR), - .m_axi_ARBURST(m_axi_in_0_ARBURST), - .m_axi_ARCACHE(m_axi_in_0_ARCACHE), - .m_axi_ARID(m_axi_in_0_ARID), - .m_axi_ARLEN(m_axi_in_0_ARLEN), - .m_axi_ARLOCK(m_axi_in_0_ARLOCK), - .m_axi_ARPROT(m_axi_in_0_ARPROT), - .m_axi_ARQOS(m_axi_in_0_ARQOS), - .m_axi_ARREADY(m_axi_in_0_ARREADY), - .m_axi_ARSIZE(m_axi_in_0_ARSIZE), - .m_axi_ARVALID(m_axi_in_0_ARVALID), - .m_axi_AWADDR(m_axi_in_0_AWADDR), - .m_axi_AWBURST(m_axi_in_0_AWBURST), - .m_axi_AWCACHE(m_axi_in_0_AWCACHE), - .m_axi_AWID(m_axi_in_0_AWID), - .m_axi_AWLEN(m_axi_in_0_AWLEN), - .m_axi_AWLOCK(m_axi_in_0_AWLOCK), - .m_axi_AWPROT(m_axi_in_0_AWPROT), - .m_axi_AWQOS(m_axi_in_0_AWQOS), - .m_axi_AWREADY(m_axi_in_0_AWREADY), - .m_axi_AWSIZE(m_axi_in_0_AWSIZE), - .m_axi_AWVALID(m_axi_in_0_AWVALID), - .m_axi_BID(m_axi_in_0_BID), - .m_axi_BREADY(m_axi_in_0_BREADY), - .m_axi_BRESP(m_axi_in_0_BRESP), - .m_axi_BVALID(m_axi_in_0_BVALID), - .m_axi_RDATA(m_axi_in_0_RDATA), - .m_axi_RID(m_axi_in_0_RID), - .m_axi_RLAST(m_axi_in_0_RLAST), - .m_axi_RREADY(m_axi_in_0_RREADY), - .m_axi_RRESP(m_axi_in_0_RRESP), - .m_axi_RVALID(m_axi_in_0_RVALID), - .m_axi_WDATA(m_axi_in_0_WDATA), - .m_axi_WLAST(m_axi_in_0_WLAST), - .m_axi_WREADY(m_axi_in_0_WREADY), - .m_axi_WSTRB(m_axi_in_0_WSTRB), - .m_axi_WVALID(m_axi_in_0_WVALID), - .read_addr_din(in_0_read_addr__din), - .read_addr_full_n(in_0_read_addr__full_n), - .read_addr_write(in_0_read_addr__write), - .read_data_dout(in_0_read_data__dout), - .read_data_empty_n(in_0_read_data__empty_n), - .read_data_read(in_0_read_data__read), - .write_addr_din(in_0_write_addr__din), - .write_addr_full_n(in_0_write_addr__full_n), - .write_addr_write(in_0_write_addr__write), - .write_data_din(in_0_write_data__din), - .write_data_full_n(in_0_write_data__full_n), - .write_data_write(in_0_write_data__write), - .write_resp_dout(in_0_write_resp__dout), - .write_resp_empty_n(in_0_write_resp__empty_n), - .write_resp_read(in_0_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_0__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_0___out_0__q0), - .m_axi_ARADDR(m_axi_out_0_ARADDR), - .m_axi_ARBURST(m_axi_out_0_ARBURST), - .m_axi_ARCACHE(m_axi_out_0_ARCACHE), - .m_axi_ARID(m_axi_out_0_ARID), - .m_axi_ARLEN(m_axi_out_0_ARLEN), - .m_axi_ARLOCK(m_axi_out_0_ARLOCK), - .m_axi_ARPROT(m_axi_out_0_ARPROT), - .m_axi_ARQOS(m_axi_out_0_ARQOS), - .m_axi_ARREADY(m_axi_out_0_ARREADY), - .m_axi_ARSIZE(m_axi_out_0_ARSIZE), - .m_axi_ARVALID(m_axi_out_0_ARVALID), - .m_axi_AWADDR(m_axi_out_0_AWADDR), - .m_axi_AWBURST(m_axi_out_0_AWBURST), - .m_axi_AWCACHE(m_axi_out_0_AWCACHE), - .m_axi_AWID(m_axi_out_0_AWID), - .m_axi_AWLEN(m_axi_out_0_AWLEN), - .m_axi_AWLOCK(m_axi_out_0_AWLOCK), - .m_axi_AWPROT(m_axi_out_0_AWPROT), - .m_axi_AWQOS(m_axi_out_0_AWQOS), - .m_axi_AWREADY(m_axi_out_0_AWREADY), - .m_axi_AWSIZE(m_axi_out_0_AWSIZE), - .m_axi_AWVALID(m_axi_out_0_AWVALID), - .m_axi_BID(m_axi_out_0_BID), - .m_axi_BREADY(m_axi_out_0_BREADY), - .m_axi_BRESP(m_axi_out_0_BRESP), - .m_axi_BVALID(m_axi_out_0_BVALID), - .m_axi_RDATA(m_axi_out_0_RDATA), - .m_axi_RID(m_axi_out_0_RID), - .m_axi_RLAST(m_axi_out_0_RLAST), - .m_axi_RREADY(m_axi_out_0_RREADY), - .m_axi_RRESP(m_axi_out_0_RRESP), - .m_axi_RVALID(m_axi_out_0_RVALID), - .m_axi_WDATA(m_axi_out_0_WDATA), - .m_axi_WLAST(m_axi_out_0_WLAST), - .m_axi_WREADY(m_axi_out_0_WREADY), - .m_axi_WSTRB(m_axi_out_0_WSTRB), - .m_axi_WVALID(m_axi_out_0_WVALID), - .read_addr_din(out_0_read_addr__din), - .read_addr_full_n(out_0_read_addr__full_n), - .read_addr_write(out_0_read_addr__write), - .read_data_dout(out_0_read_data__dout), - .read_data_empty_n(out_0_read_data__empty_n), - .read_data_read(out_0_read_data__read), - .write_addr_din(out_0_write_addr__din), - .write_addr_full_n(out_0_write_addr__full_n), - .write_addr_write(out_0_write_addr__write), - .write_data_din(out_0_write_data__din), - .write_data_full_n(out_0_write_data__full_n), - .write_data_write(out_0_write_data__write), - .write_resp_dout(out_0_write_resp__dout), - .write_resp_empty_n(out_0_write_resp__empty_n), - .write_resp_read(out_0_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_1__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_1___in_1__q0), - .m_axi_ARADDR(m_axi_in_1_ARADDR), - .m_axi_ARBURST(m_axi_in_1_ARBURST), - .m_axi_ARCACHE(m_axi_in_1_ARCACHE), - .m_axi_ARID(m_axi_in_1_ARID), - .m_axi_ARLEN(m_axi_in_1_ARLEN), - .m_axi_ARLOCK(m_axi_in_1_ARLOCK), - .m_axi_ARPROT(m_axi_in_1_ARPROT), - .m_axi_ARQOS(m_axi_in_1_ARQOS), - .m_axi_ARREADY(m_axi_in_1_ARREADY), - .m_axi_ARSIZE(m_axi_in_1_ARSIZE), - .m_axi_ARVALID(m_axi_in_1_ARVALID), - .m_axi_AWADDR(m_axi_in_1_AWADDR), - .m_axi_AWBURST(m_axi_in_1_AWBURST), - .m_axi_AWCACHE(m_axi_in_1_AWCACHE), - .m_axi_AWID(m_axi_in_1_AWID), - .m_axi_AWLEN(m_axi_in_1_AWLEN), - .m_axi_AWLOCK(m_axi_in_1_AWLOCK), - .m_axi_AWPROT(m_axi_in_1_AWPROT), - .m_axi_AWQOS(m_axi_in_1_AWQOS), - .m_axi_AWREADY(m_axi_in_1_AWREADY), - .m_axi_AWSIZE(m_axi_in_1_AWSIZE), - .m_axi_AWVALID(m_axi_in_1_AWVALID), - .m_axi_BID(m_axi_in_1_BID), - .m_axi_BREADY(m_axi_in_1_BREADY), - .m_axi_BRESP(m_axi_in_1_BRESP), - .m_axi_BVALID(m_axi_in_1_BVALID), - .m_axi_RDATA(m_axi_in_1_RDATA), - .m_axi_RID(m_axi_in_1_RID), - .m_axi_RLAST(m_axi_in_1_RLAST), - .m_axi_RREADY(m_axi_in_1_RREADY), - .m_axi_RRESP(m_axi_in_1_RRESP), - .m_axi_RVALID(m_axi_in_1_RVALID), - .m_axi_WDATA(m_axi_in_1_WDATA), - .m_axi_WLAST(m_axi_in_1_WLAST), - .m_axi_WREADY(m_axi_in_1_WREADY), - .m_axi_WSTRB(m_axi_in_1_WSTRB), - .m_axi_WVALID(m_axi_in_1_WVALID), - .read_addr_din(in_1_read_addr__din), - .read_addr_full_n(in_1_read_addr__full_n), - .read_addr_write(in_1_read_addr__write), - .read_data_dout(in_1_read_data__dout), - .read_data_empty_n(in_1_read_data__empty_n), - .read_data_read(in_1_read_data__read), - .write_addr_din(in_1_write_addr__din), - .write_addr_full_n(in_1_write_addr__full_n), - .write_addr_write(in_1_write_addr__write), - .write_data_din(in_1_write_data__din), - .write_data_full_n(in_1_write_data__full_n), - .write_data_write(in_1_write_data__write), - .write_resp_dout(in_1_write_resp__dout), - .write_resp_empty_n(in_1_write_resp__empty_n), - .write_resp_read(in_1_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_1__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_1___out_1__q0), - .m_axi_ARADDR(m_axi_out_1_ARADDR), - .m_axi_ARBURST(m_axi_out_1_ARBURST), - .m_axi_ARCACHE(m_axi_out_1_ARCACHE), - .m_axi_ARID(m_axi_out_1_ARID), - .m_axi_ARLEN(m_axi_out_1_ARLEN), - .m_axi_ARLOCK(m_axi_out_1_ARLOCK), - .m_axi_ARPROT(m_axi_out_1_ARPROT), - .m_axi_ARQOS(m_axi_out_1_ARQOS), - .m_axi_ARREADY(m_axi_out_1_ARREADY), - .m_axi_ARSIZE(m_axi_out_1_ARSIZE), - .m_axi_ARVALID(m_axi_out_1_ARVALID), - .m_axi_AWADDR(m_axi_out_1_AWADDR), - .m_axi_AWBURST(m_axi_out_1_AWBURST), - .m_axi_AWCACHE(m_axi_out_1_AWCACHE), - .m_axi_AWID(m_axi_out_1_AWID), - .m_axi_AWLEN(m_axi_out_1_AWLEN), - .m_axi_AWLOCK(m_axi_out_1_AWLOCK), - .m_axi_AWPROT(m_axi_out_1_AWPROT), - .m_axi_AWQOS(m_axi_out_1_AWQOS), - .m_axi_AWREADY(m_axi_out_1_AWREADY), - .m_axi_AWSIZE(m_axi_out_1_AWSIZE), - .m_axi_AWVALID(m_axi_out_1_AWVALID), - .m_axi_BID(m_axi_out_1_BID), - .m_axi_BREADY(m_axi_out_1_BREADY), - .m_axi_BRESP(m_axi_out_1_BRESP), - .m_axi_BVALID(m_axi_out_1_BVALID), - .m_axi_RDATA(m_axi_out_1_RDATA), - .m_axi_RID(m_axi_out_1_RID), - .m_axi_RLAST(m_axi_out_1_RLAST), - .m_axi_RREADY(m_axi_out_1_RREADY), - .m_axi_RRESP(m_axi_out_1_RRESP), - .m_axi_RVALID(m_axi_out_1_RVALID), - .m_axi_WDATA(m_axi_out_1_WDATA), - .m_axi_WLAST(m_axi_out_1_WLAST), - .m_axi_WREADY(m_axi_out_1_WREADY), - .m_axi_WSTRB(m_axi_out_1_WSTRB), - .m_axi_WVALID(m_axi_out_1_WVALID), - .read_addr_din(out_1_read_addr__din), - .read_addr_full_n(out_1_read_addr__full_n), - .read_addr_write(out_1_read_addr__write), - .read_data_dout(out_1_read_data__dout), - .read_data_empty_n(out_1_read_data__empty_n), - .read_data_read(out_1_read_data__read), - .write_addr_din(out_1_write_addr__din), - .write_addr_full_n(out_1_write_addr__full_n), - .write_addr_write(out_1_write_addr__write), - .write_data_din(out_1_write_data__din), - .write_data_full_n(out_1_write_data__full_n), - .write_data_write(out_1_write_data__write), - .write_resp_dout(out_1_write_resp__dout), - .write_resp_empty_n(out_1_write_resp__empty_n), - .write_resp_read(out_1_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_2__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_2___in_2__q0), - .m_axi_ARADDR(m_axi_in_2_ARADDR), - .m_axi_ARBURST(m_axi_in_2_ARBURST), - .m_axi_ARCACHE(m_axi_in_2_ARCACHE), - .m_axi_ARID(m_axi_in_2_ARID), - .m_axi_ARLEN(m_axi_in_2_ARLEN), - .m_axi_ARLOCK(m_axi_in_2_ARLOCK), - .m_axi_ARPROT(m_axi_in_2_ARPROT), - .m_axi_ARQOS(m_axi_in_2_ARQOS), - .m_axi_ARREADY(m_axi_in_2_ARREADY), - .m_axi_ARSIZE(m_axi_in_2_ARSIZE), - .m_axi_ARVALID(m_axi_in_2_ARVALID), - .m_axi_AWADDR(m_axi_in_2_AWADDR), - .m_axi_AWBURST(m_axi_in_2_AWBURST), - .m_axi_AWCACHE(m_axi_in_2_AWCACHE), - .m_axi_AWID(m_axi_in_2_AWID), - .m_axi_AWLEN(m_axi_in_2_AWLEN), - .m_axi_AWLOCK(m_axi_in_2_AWLOCK), - .m_axi_AWPROT(m_axi_in_2_AWPROT), - .m_axi_AWQOS(m_axi_in_2_AWQOS), - .m_axi_AWREADY(m_axi_in_2_AWREADY), - .m_axi_AWSIZE(m_axi_in_2_AWSIZE), - .m_axi_AWVALID(m_axi_in_2_AWVALID), - .m_axi_BID(m_axi_in_2_BID), - .m_axi_BREADY(m_axi_in_2_BREADY), - .m_axi_BRESP(m_axi_in_2_BRESP), - .m_axi_BVALID(m_axi_in_2_BVALID), - .m_axi_RDATA(m_axi_in_2_RDATA), - .m_axi_RID(m_axi_in_2_RID), - .m_axi_RLAST(m_axi_in_2_RLAST), - .m_axi_RREADY(m_axi_in_2_RREADY), - .m_axi_RRESP(m_axi_in_2_RRESP), - .m_axi_RVALID(m_axi_in_2_RVALID), - .m_axi_WDATA(m_axi_in_2_WDATA), - .m_axi_WLAST(m_axi_in_2_WLAST), - .m_axi_WREADY(m_axi_in_2_WREADY), - .m_axi_WSTRB(m_axi_in_2_WSTRB), - .m_axi_WVALID(m_axi_in_2_WVALID), - .read_addr_din(in_2_read_addr__din), - .read_addr_full_n(in_2_read_addr__full_n), - .read_addr_write(in_2_read_addr__write), - .read_data_dout(in_2_read_data__dout), - .read_data_empty_n(in_2_read_data__empty_n), - .read_data_read(in_2_read_data__read), - .write_addr_din(in_2_write_addr__din), - .write_addr_full_n(in_2_write_addr__full_n), - .write_addr_write(in_2_write_addr__write), - .write_data_din(in_2_write_data__din), - .write_data_full_n(in_2_write_data__full_n), - .write_data_write(in_2_write_data__write), - .write_resp_dout(in_2_write_resp__dout), - .write_resp_empty_n(in_2_write_resp__empty_n), - .write_resp_read(in_2_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_2__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_2___out_2__q0), - .m_axi_ARADDR(m_axi_out_2_ARADDR), - .m_axi_ARBURST(m_axi_out_2_ARBURST), - .m_axi_ARCACHE(m_axi_out_2_ARCACHE), - .m_axi_ARID(m_axi_out_2_ARID), - .m_axi_ARLEN(m_axi_out_2_ARLEN), - .m_axi_ARLOCK(m_axi_out_2_ARLOCK), - .m_axi_ARPROT(m_axi_out_2_ARPROT), - .m_axi_ARQOS(m_axi_out_2_ARQOS), - .m_axi_ARREADY(m_axi_out_2_ARREADY), - .m_axi_ARSIZE(m_axi_out_2_ARSIZE), - .m_axi_ARVALID(m_axi_out_2_ARVALID), - .m_axi_AWADDR(m_axi_out_2_AWADDR), - .m_axi_AWBURST(m_axi_out_2_AWBURST), - .m_axi_AWCACHE(m_axi_out_2_AWCACHE), - .m_axi_AWID(m_axi_out_2_AWID), - .m_axi_AWLEN(m_axi_out_2_AWLEN), - .m_axi_AWLOCK(m_axi_out_2_AWLOCK), - .m_axi_AWPROT(m_axi_out_2_AWPROT), - .m_axi_AWQOS(m_axi_out_2_AWQOS), - .m_axi_AWREADY(m_axi_out_2_AWREADY), - .m_axi_AWSIZE(m_axi_out_2_AWSIZE), - .m_axi_AWVALID(m_axi_out_2_AWVALID), - .m_axi_BID(m_axi_out_2_BID), - .m_axi_BREADY(m_axi_out_2_BREADY), - .m_axi_BRESP(m_axi_out_2_BRESP), - .m_axi_BVALID(m_axi_out_2_BVALID), - .m_axi_RDATA(m_axi_out_2_RDATA), - .m_axi_RID(m_axi_out_2_RID), - .m_axi_RLAST(m_axi_out_2_RLAST), - .m_axi_RREADY(m_axi_out_2_RREADY), - .m_axi_RRESP(m_axi_out_2_RRESP), - .m_axi_RVALID(m_axi_out_2_RVALID), - .m_axi_WDATA(m_axi_out_2_WDATA), - .m_axi_WLAST(m_axi_out_2_WLAST), - .m_axi_WREADY(m_axi_out_2_WREADY), - .m_axi_WSTRB(m_axi_out_2_WSTRB), - .m_axi_WVALID(m_axi_out_2_WVALID), - .read_addr_din(out_2_read_addr__din), - .read_addr_full_n(out_2_read_addr__full_n), - .read_addr_write(out_2_read_addr__write), - .read_data_dout(out_2_read_data__dout), - .read_data_empty_n(out_2_read_data__empty_n), - .read_data_read(out_2_read_data__read), - .write_addr_din(out_2_write_addr__din), - .write_addr_full_n(out_2_write_addr__full_n), - .write_addr_write(out_2_write_addr__write), - .write_data_din(out_2_write_data__din), - .write_data_full_n(out_2_write_data__full_n), - .write_data_write(out_2_write_data__write), - .write_resp_dout(out_2_write_resp__dout), - .write_resp_empty_n(out_2_write_resp__empty_n), - .write_resp_read(out_2_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_3__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_3___in_3__q0), - .m_axi_ARADDR(m_axi_in_3_ARADDR), - .m_axi_ARBURST(m_axi_in_3_ARBURST), - .m_axi_ARCACHE(m_axi_in_3_ARCACHE), - .m_axi_ARID(m_axi_in_3_ARID), - .m_axi_ARLEN(m_axi_in_3_ARLEN), - .m_axi_ARLOCK(m_axi_in_3_ARLOCK), - .m_axi_ARPROT(m_axi_in_3_ARPROT), - .m_axi_ARQOS(m_axi_in_3_ARQOS), - .m_axi_ARREADY(m_axi_in_3_ARREADY), - .m_axi_ARSIZE(m_axi_in_3_ARSIZE), - .m_axi_ARVALID(m_axi_in_3_ARVALID), - .m_axi_AWADDR(m_axi_in_3_AWADDR), - .m_axi_AWBURST(m_axi_in_3_AWBURST), - .m_axi_AWCACHE(m_axi_in_3_AWCACHE), - .m_axi_AWID(m_axi_in_3_AWID), - .m_axi_AWLEN(m_axi_in_3_AWLEN), - .m_axi_AWLOCK(m_axi_in_3_AWLOCK), - .m_axi_AWPROT(m_axi_in_3_AWPROT), - .m_axi_AWQOS(m_axi_in_3_AWQOS), - .m_axi_AWREADY(m_axi_in_3_AWREADY), - .m_axi_AWSIZE(m_axi_in_3_AWSIZE), - .m_axi_AWVALID(m_axi_in_3_AWVALID), - .m_axi_BID(m_axi_in_3_BID), - .m_axi_BREADY(m_axi_in_3_BREADY), - .m_axi_BRESP(m_axi_in_3_BRESP), - .m_axi_BVALID(m_axi_in_3_BVALID), - .m_axi_RDATA(m_axi_in_3_RDATA), - .m_axi_RID(m_axi_in_3_RID), - .m_axi_RLAST(m_axi_in_3_RLAST), - .m_axi_RREADY(m_axi_in_3_RREADY), - .m_axi_RRESP(m_axi_in_3_RRESP), - .m_axi_RVALID(m_axi_in_3_RVALID), - .m_axi_WDATA(m_axi_in_3_WDATA), - .m_axi_WLAST(m_axi_in_3_WLAST), - .m_axi_WREADY(m_axi_in_3_WREADY), - .m_axi_WSTRB(m_axi_in_3_WSTRB), - .m_axi_WVALID(m_axi_in_3_WVALID), - .read_addr_din(in_3_read_addr__din), - .read_addr_full_n(in_3_read_addr__full_n), - .read_addr_write(in_3_read_addr__write), - .read_data_dout(in_3_read_data__dout), - .read_data_empty_n(in_3_read_data__empty_n), - .read_data_read(in_3_read_data__read), - .write_addr_din(in_3_write_addr__din), - .write_addr_full_n(in_3_write_addr__full_n), - .write_addr_write(in_3_write_addr__write), - .write_data_din(in_3_write_data__din), - .write_data_full_n(in_3_write_data__full_n), - .write_data_write(in_3_write_data__write), - .write_resp_dout(in_3_write_resp__dout), - .write_resp_empty_n(in_3_write_resp__empty_n), - .write_resp_read(in_3_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_3__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_3___out_3__q0), - .m_axi_ARADDR(m_axi_out_3_ARADDR), - .m_axi_ARBURST(m_axi_out_3_ARBURST), - .m_axi_ARCACHE(m_axi_out_3_ARCACHE), - .m_axi_ARID(m_axi_out_3_ARID), - .m_axi_ARLEN(m_axi_out_3_ARLEN), - .m_axi_ARLOCK(m_axi_out_3_ARLOCK), - .m_axi_ARPROT(m_axi_out_3_ARPROT), - .m_axi_ARQOS(m_axi_out_3_ARQOS), - .m_axi_ARREADY(m_axi_out_3_ARREADY), - .m_axi_ARSIZE(m_axi_out_3_ARSIZE), - .m_axi_ARVALID(m_axi_out_3_ARVALID), - .m_axi_AWADDR(m_axi_out_3_AWADDR), - .m_axi_AWBURST(m_axi_out_3_AWBURST), - .m_axi_AWCACHE(m_axi_out_3_AWCACHE), - .m_axi_AWID(m_axi_out_3_AWID), - .m_axi_AWLEN(m_axi_out_3_AWLEN), - .m_axi_AWLOCK(m_axi_out_3_AWLOCK), - .m_axi_AWPROT(m_axi_out_3_AWPROT), - .m_axi_AWQOS(m_axi_out_3_AWQOS), - .m_axi_AWREADY(m_axi_out_3_AWREADY), - .m_axi_AWSIZE(m_axi_out_3_AWSIZE), - .m_axi_AWVALID(m_axi_out_3_AWVALID), - .m_axi_BID(m_axi_out_3_BID), - .m_axi_BREADY(m_axi_out_3_BREADY), - .m_axi_BRESP(m_axi_out_3_BRESP), - .m_axi_BVALID(m_axi_out_3_BVALID), - .m_axi_RDATA(m_axi_out_3_RDATA), - .m_axi_RID(m_axi_out_3_RID), - .m_axi_RLAST(m_axi_out_3_RLAST), - .m_axi_RREADY(m_axi_out_3_RREADY), - .m_axi_RRESP(m_axi_out_3_RRESP), - .m_axi_RVALID(m_axi_out_3_RVALID), - .m_axi_WDATA(m_axi_out_3_WDATA), - .m_axi_WLAST(m_axi_out_3_WLAST), - .m_axi_WREADY(m_axi_out_3_WREADY), - .m_axi_WSTRB(m_axi_out_3_WSTRB), - .m_axi_WVALID(m_axi_out_3_WVALID), - .read_addr_din(out_3_read_addr__din), - .read_addr_full_n(out_3_read_addr__full_n), - .read_addr_write(out_3_read_addr__write), - .read_data_dout(out_3_read_data__dout), - .read_data_empty_n(out_3_read_data__empty_n), - .read_data_read(out_3_read_data__read), - .write_addr_din(out_3_write_addr__din), - .write_addr_full_n(out_3_write_addr__full_n), - .write_addr_write(out_3_write_addr__write), - .write_data_din(out_3_write_data__din), - .write_data_full_n(out_3_write_data__full_n), - .write_data_write(out_3_write_data__write), - .write_resp_dout(out_3_write_resp__dout), - .write_resp_empty_n(out_3_write_resp__empty_n), - .write_resp_read(out_3_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_4__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_4___in_4__q0), - .m_axi_ARADDR(m_axi_in_4_ARADDR), - .m_axi_ARBURST(m_axi_in_4_ARBURST), - .m_axi_ARCACHE(m_axi_in_4_ARCACHE), - .m_axi_ARID(m_axi_in_4_ARID), - .m_axi_ARLEN(m_axi_in_4_ARLEN), - .m_axi_ARLOCK(m_axi_in_4_ARLOCK), - .m_axi_ARPROT(m_axi_in_4_ARPROT), - .m_axi_ARQOS(m_axi_in_4_ARQOS), - .m_axi_ARREADY(m_axi_in_4_ARREADY), - .m_axi_ARSIZE(m_axi_in_4_ARSIZE), - .m_axi_ARVALID(m_axi_in_4_ARVALID), - .m_axi_AWADDR(m_axi_in_4_AWADDR), - .m_axi_AWBURST(m_axi_in_4_AWBURST), - .m_axi_AWCACHE(m_axi_in_4_AWCACHE), - .m_axi_AWID(m_axi_in_4_AWID), - .m_axi_AWLEN(m_axi_in_4_AWLEN), - .m_axi_AWLOCK(m_axi_in_4_AWLOCK), - .m_axi_AWPROT(m_axi_in_4_AWPROT), - .m_axi_AWQOS(m_axi_in_4_AWQOS), - .m_axi_AWREADY(m_axi_in_4_AWREADY), - .m_axi_AWSIZE(m_axi_in_4_AWSIZE), - .m_axi_AWVALID(m_axi_in_4_AWVALID), - .m_axi_BID(m_axi_in_4_BID), - .m_axi_BREADY(m_axi_in_4_BREADY), - .m_axi_BRESP(m_axi_in_4_BRESP), - .m_axi_BVALID(m_axi_in_4_BVALID), - .m_axi_RDATA(m_axi_in_4_RDATA), - .m_axi_RID(m_axi_in_4_RID), - .m_axi_RLAST(m_axi_in_4_RLAST), - .m_axi_RREADY(m_axi_in_4_RREADY), - .m_axi_RRESP(m_axi_in_4_RRESP), - .m_axi_RVALID(m_axi_in_4_RVALID), - .m_axi_WDATA(m_axi_in_4_WDATA), - .m_axi_WLAST(m_axi_in_4_WLAST), - .m_axi_WREADY(m_axi_in_4_WREADY), - .m_axi_WSTRB(m_axi_in_4_WSTRB), - .m_axi_WVALID(m_axi_in_4_WVALID), - .read_addr_din(in_4_read_addr__din), - .read_addr_full_n(in_4_read_addr__full_n), - .read_addr_write(in_4_read_addr__write), - .read_data_dout(in_4_read_data__dout), - .read_data_empty_n(in_4_read_data__empty_n), - .read_data_read(in_4_read_data__read), - .write_addr_din(in_4_write_addr__din), - .write_addr_full_n(in_4_write_addr__full_n), - .write_addr_write(in_4_write_addr__write), - .write_data_din(in_4_write_data__din), - .write_data_full_n(in_4_write_data__full_n), - .write_data_write(in_4_write_data__write), - .write_resp_dout(in_4_write_resp__dout), - .write_resp_empty_n(in_4_write_resp__empty_n), - .write_resp_read(in_4_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_4__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_4___out_4__q0), - .m_axi_ARADDR(m_axi_out_4_ARADDR), - .m_axi_ARBURST(m_axi_out_4_ARBURST), - .m_axi_ARCACHE(m_axi_out_4_ARCACHE), - .m_axi_ARID(m_axi_out_4_ARID), - .m_axi_ARLEN(m_axi_out_4_ARLEN), - .m_axi_ARLOCK(m_axi_out_4_ARLOCK), - .m_axi_ARPROT(m_axi_out_4_ARPROT), - .m_axi_ARQOS(m_axi_out_4_ARQOS), - .m_axi_ARREADY(m_axi_out_4_ARREADY), - .m_axi_ARSIZE(m_axi_out_4_ARSIZE), - .m_axi_ARVALID(m_axi_out_4_ARVALID), - .m_axi_AWADDR(m_axi_out_4_AWADDR), - .m_axi_AWBURST(m_axi_out_4_AWBURST), - .m_axi_AWCACHE(m_axi_out_4_AWCACHE), - .m_axi_AWID(m_axi_out_4_AWID), - .m_axi_AWLEN(m_axi_out_4_AWLEN), - .m_axi_AWLOCK(m_axi_out_4_AWLOCK), - .m_axi_AWPROT(m_axi_out_4_AWPROT), - .m_axi_AWQOS(m_axi_out_4_AWQOS), - .m_axi_AWREADY(m_axi_out_4_AWREADY), - .m_axi_AWSIZE(m_axi_out_4_AWSIZE), - .m_axi_AWVALID(m_axi_out_4_AWVALID), - .m_axi_BID(m_axi_out_4_BID), - .m_axi_BREADY(m_axi_out_4_BREADY), - .m_axi_BRESP(m_axi_out_4_BRESP), - .m_axi_BVALID(m_axi_out_4_BVALID), - .m_axi_RDATA(m_axi_out_4_RDATA), - .m_axi_RID(m_axi_out_4_RID), - .m_axi_RLAST(m_axi_out_4_RLAST), - .m_axi_RREADY(m_axi_out_4_RREADY), - .m_axi_RRESP(m_axi_out_4_RRESP), - .m_axi_RVALID(m_axi_out_4_RVALID), - .m_axi_WDATA(m_axi_out_4_WDATA), - .m_axi_WLAST(m_axi_out_4_WLAST), - .m_axi_WREADY(m_axi_out_4_WREADY), - .m_axi_WSTRB(m_axi_out_4_WSTRB), - .m_axi_WVALID(m_axi_out_4_WVALID), - .read_addr_din(out_4_read_addr__din), - .read_addr_full_n(out_4_read_addr__full_n), - .read_addr_write(out_4_read_addr__write), - .read_data_dout(out_4_read_data__dout), - .read_data_empty_n(out_4_read_data__empty_n), - .read_data_read(out_4_read_data__read), - .write_addr_din(out_4_write_addr__din), - .write_addr_full_n(out_4_write_addr__full_n), - .write_addr_write(out_4_write_addr__write), - .write_data_din(out_4_write_data__din), - .write_data_full_n(out_4_write_data__full_n), - .write_data_write(out_4_write_data__write), - .write_resp_dout(out_4_write_resp__dout), - .write_resp_empty_n(out_4_write_resp__empty_n), - .write_resp_read(out_4_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_5__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_5___in_5__q0), - .m_axi_ARADDR(m_axi_in_5_ARADDR), - .m_axi_ARBURST(m_axi_in_5_ARBURST), - .m_axi_ARCACHE(m_axi_in_5_ARCACHE), - .m_axi_ARID(m_axi_in_5_ARID), - .m_axi_ARLEN(m_axi_in_5_ARLEN), - .m_axi_ARLOCK(m_axi_in_5_ARLOCK), - .m_axi_ARPROT(m_axi_in_5_ARPROT), - .m_axi_ARQOS(m_axi_in_5_ARQOS), - .m_axi_ARREADY(m_axi_in_5_ARREADY), - .m_axi_ARSIZE(m_axi_in_5_ARSIZE), - .m_axi_ARVALID(m_axi_in_5_ARVALID), - .m_axi_AWADDR(m_axi_in_5_AWADDR), - .m_axi_AWBURST(m_axi_in_5_AWBURST), - .m_axi_AWCACHE(m_axi_in_5_AWCACHE), - .m_axi_AWID(m_axi_in_5_AWID), - .m_axi_AWLEN(m_axi_in_5_AWLEN), - .m_axi_AWLOCK(m_axi_in_5_AWLOCK), - .m_axi_AWPROT(m_axi_in_5_AWPROT), - .m_axi_AWQOS(m_axi_in_5_AWQOS), - .m_axi_AWREADY(m_axi_in_5_AWREADY), - .m_axi_AWSIZE(m_axi_in_5_AWSIZE), - .m_axi_AWVALID(m_axi_in_5_AWVALID), - .m_axi_BID(m_axi_in_5_BID), - .m_axi_BREADY(m_axi_in_5_BREADY), - .m_axi_BRESP(m_axi_in_5_BRESP), - .m_axi_BVALID(m_axi_in_5_BVALID), - .m_axi_RDATA(m_axi_in_5_RDATA), - .m_axi_RID(m_axi_in_5_RID), - .m_axi_RLAST(m_axi_in_5_RLAST), - .m_axi_RREADY(m_axi_in_5_RREADY), - .m_axi_RRESP(m_axi_in_5_RRESP), - .m_axi_RVALID(m_axi_in_5_RVALID), - .m_axi_WDATA(m_axi_in_5_WDATA), - .m_axi_WLAST(m_axi_in_5_WLAST), - .m_axi_WREADY(m_axi_in_5_WREADY), - .m_axi_WSTRB(m_axi_in_5_WSTRB), - .m_axi_WVALID(m_axi_in_5_WVALID), - .read_addr_din(in_5_read_addr__din), - .read_addr_full_n(in_5_read_addr__full_n), - .read_addr_write(in_5_read_addr__write), - .read_data_dout(in_5_read_data__dout), - .read_data_empty_n(in_5_read_data__empty_n), - .read_data_read(in_5_read_data__read), - .write_addr_din(in_5_write_addr__din), - .write_addr_full_n(in_5_write_addr__full_n), - .write_addr_write(in_5_write_addr__write), - .write_data_din(in_5_write_data__din), - .write_data_full_n(in_5_write_data__full_n), - .write_data_write(in_5_write_data__write), - .write_resp_dout(in_5_write_resp__dout), - .write_resp_empty_n(in_5_write_resp__empty_n), - .write_resp_read(in_5_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_5__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_5___out_5__q0), - .m_axi_ARADDR(m_axi_out_5_ARADDR), - .m_axi_ARBURST(m_axi_out_5_ARBURST), - .m_axi_ARCACHE(m_axi_out_5_ARCACHE), - .m_axi_ARID(m_axi_out_5_ARID), - .m_axi_ARLEN(m_axi_out_5_ARLEN), - .m_axi_ARLOCK(m_axi_out_5_ARLOCK), - .m_axi_ARPROT(m_axi_out_5_ARPROT), - .m_axi_ARQOS(m_axi_out_5_ARQOS), - .m_axi_ARREADY(m_axi_out_5_ARREADY), - .m_axi_ARSIZE(m_axi_out_5_ARSIZE), - .m_axi_ARVALID(m_axi_out_5_ARVALID), - .m_axi_AWADDR(m_axi_out_5_AWADDR), - .m_axi_AWBURST(m_axi_out_5_AWBURST), - .m_axi_AWCACHE(m_axi_out_5_AWCACHE), - .m_axi_AWID(m_axi_out_5_AWID), - .m_axi_AWLEN(m_axi_out_5_AWLEN), - .m_axi_AWLOCK(m_axi_out_5_AWLOCK), - .m_axi_AWPROT(m_axi_out_5_AWPROT), - .m_axi_AWQOS(m_axi_out_5_AWQOS), - .m_axi_AWREADY(m_axi_out_5_AWREADY), - .m_axi_AWSIZE(m_axi_out_5_AWSIZE), - .m_axi_AWVALID(m_axi_out_5_AWVALID), - .m_axi_BID(m_axi_out_5_BID), - .m_axi_BREADY(m_axi_out_5_BREADY), - .m_axi_BRESP(m_axi_out_5_BRESP), - .m_axi_BVALID(m_axi_out_5_BVALID), - .m_axi_RDATA(m_axi_out_5_RDATA), - .m_axi_RID(m_axi_out_5_RID), - .m_axi_RLAST(m_axi_out_5_RLAST), - .m_axi_RREADY(m_axi_out_5_RREADY), - .m_axi_RRESP(m_axi_out_5_RRESP), - .m_axi_RVALID(m_axi_out_5_RVALID), - .m_axi_WDATA(m_axi_out_5_WDATA), - .m_axi_WLAST(m_axi_out_5_WLAST), - .m_axi_WREADY(m_axi_out_5_WREADY), - .m_axi_WSTRB(m_axi_out_5_WSTRB), - .m_axi_WVALID(m_axi_out_5_WVALID), - .read_addr_din(out_5_read_addr__din), - .read_addr_full_n(out_5_read_addr__full_n), - .read_addr_write(out_5_read_addr__write), - .read_data_dout(out_5_read_data__dout), - .read_data_empty_n(out_5_read_data__empty_n), - .read_data_read(out_5_read_data__read), - .write_addr_din(out_5_write_addr__din), - .write_addr_full_n(out_5_write_addr__full_n), - .write_addr_write(out_5_write_addr__write), - .write_data_din(out_5_write_data__din), - .write_data_full_n(out_5_write_data__full_n), - .write_data_write(out_5_write_data__write), - .write_resp_dout(out_5_write_resp__dout), - .write_resp_empty_n(out_5_write_resp__empty_n), - .write_resp_read(out_5_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_6__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_6___in_6__q0), - .m_axi_ARADDR(m_axi_in_6_ARADDR), - .m_axi_ARBURST(m_axi_in_6_ARBURST), - .m_axi_ARCACHE(m_axi_in_6_ARCACHE), - .m_axi_ARID(m_axi_in_6_ARID), - .m_axi_ARLEN(m_axi_in_6_ARLEN), - .m_axi_ARLOCK(m_axi_in_6_ARLOCK), - .m_axi_ARPROT(m_axi_in_6_ARPROT), - .m_axi_ARQOS(m_axi_in_6_ARQOS), - .m_axi_ARREADY(m_axi_in_6_ARREADY), - .m_axi_ARSIZE(m_axi_in_6_ARSIZE), - .m_axi_ARVALID(m_axi_in_6_ARVALID), - .m_axi_AWADDR(m_axi_in_6_AWADDR), - .m_axi_AWBURST(m_axi_in_6_AWBURST), - .m_axi_AWCACHE(m_axi_in_6_AWCACHE), - .m_axi_AWID(m_axi_in_6_AWID), - .m_axi_AWLEN(m_axi_in_6_AWLEN), - .m_axi_AWLOCK(m_axi_in_6_AWLOCK), - .m_axi_AWPROT(m_axi_in_6_AWPROT), - .m_axi_AWQOS(m_axi_in_6_AWQOS), - .m_axi_AWREADY(m_axi_in_6_AWREADY), - .m_axi_AWSIZE(m_axi_in_6_AWSIZE), - .m_axi_AWVALID(m_axi_in_6_AWVALID), - .m_axi_BID(m_axi_in_6_BID), - .m_axi_BREADY(m_axi_in_6_BREADY), - .m_axi_BRESP(m_axi_in_6_BRESP), - .m_axi_BVALID(m_axi_in_6_BVALID), - .m_axi_RDATA(m_axi_in_6_RDATA), - .m_axi_RID(m_axi_in_6_RID), - .m_axi_RLAST(m_axi_in_6_RLAST), - .m_axi_RREADY(m_axi_in_6_RREADY), - .m_axi_RRESP(m_axi_in_6_RRESP), - .m_axi_RVALID(m_axi_in_6_RVALID), - .m_axi_WDATA(m_axi_in_6_WDATA), - .m_axi_WLAST(m_axi_in_6_WLAST), - .m_axi_WREADY(m_axi_in_6_WREADY), - .m_axi_WSTRB(m_axi_in_6_WSTRB), - .m_axi_WVALID(m_axi_in_6_WVALID), - .read_addr_din(in_6_read_addr__din), - .read_addr_full_n(in_6_read_addr__full_n), - .read_addr_write(in_6_read_addr__write), - .read_data_dout(in_6_read_data__dout), - .read_data_empty_n(in_6_read_data__empty_n), - .read_data_read(in_6_read_data__read), - .write_addr_din(in_6_write_addr__din), - .write_addr_full_n(in_6_write_addr__full_n), - .write_addr_write(in_6_write_addr__write), - .write_data_din(in_6_write_data__din), - .write_data_full_n(in_6_write_data__full_n), - .write_data_write(in_6_write_data__write), - .write_resp_dout(in_6_write_resp__dout), - .write_resp_empty_n(in_6_write_resp__empty_n), - .write_resp_read(in_6_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_6__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_6___out_6__q0), - .m_axi_ARADDR(m_axi_out_6_ARADDR), - .m_axi_ARBURST(m_axi_out_6_ARBURST), - .m_axi_ARCACHE(m_axi_out_6_ARCACHE), - .m_axi_ARID(m_axi_out_6_ARID), - .m_axi_ARLEN(m_axi_out_6_ARLEN), - .m_axi_ARLOCK(m_axi_out_6_ARLOCK), - .m_axi_ARPROT(m_axi_out_6_ARPROT), - .m_axi_ARQOS(m_axi_out_6_ARQOS), - .m_axi_ARREADY(m_axi_out_6_ARREADY), - .m_axi_ARSIZE(m_axi_out_6_ARSIZE), - .m_axi_ARVALID(m_axi_out_6_ARVALID), - .m_axi_AWADDR(m_axi_out_6_AWADDR), - .m_axi_AWBURST(m_axi_out_6_AWBURST), - .m_axi_AWCACHE(m_axi_out_6_AWCACHE), - .m_axi_AWID(m_axi_out_6_AWID), - .m_axi_AWLEN(m_axi_out_6_AWLEN), - .m_axi_AWLOCK(m_axi_out_6_AWLOCK), - .m_axi_AWPROT(m_axi_out_6_AWPROT), - .m_axi_AWQOS(m_axi_out_6_AWQOS), - .m_axi_AWREADY(m_axi_out_6_AWREADY), - .m_axi_AWSIZE(m_axi_out_6_AWSIZE), - .m_axi_AWVALID(m_axi_out_6_AWVALID), - .m_axi_BID(m_axi_out_6_BID), - .m_axi_BREADY(m_axi_out_6_BREADY), - .m_axi_BRESP(m_axi_out_6_BRESP), - .m_axi_BVALID(m_axi_out_6_BVALID), - .m_axi_RDATA(m_axi_out_6_RDATA), - .m_axi_RID(m_axi_out_6_RID), - .m_axi_RLAST(m_axi_out_6_RLAST), - .m_axi_RREADY(m_axi_out_6_RREADY), - .m_axi_RRESP(m_axi_out_6_RRESP), - .m_axi_RVALID(m_axi_out_6_RVALID), - .m_axi_WDATA(m_axi_out_6_WDATA), - .m_axi_WLAST(m_axi_out_6_WLAST), - .m_axi_WREADY(m_axi_out_6_WREADY), - .m_axi_WSTRB(m_axi_out_6_WSTRB), - .m_axi_WVALID(m_axi_out_6_WVALID), - .read_addr_din(out_6_read_addr__din), - .read_addr_full_n(out_6_read_addr__full_n), - .read_addr_write(out_6_read_addr__write), - .read_data_dout(out_6_read_data__dout), - .read_data_empty_n(out_6_read_data__empty_n), - .read_data_read(out_6_read_data__read), - .write_addr_din(out_6_write_addr__din), - .write_addr_full_n(out_6_write_addr__full_n), - .write_addr_write(out_6_write_addr__write), - .write_data_din(out_6_write_data__din), - .write_data_full_n(out_6_write_data__full_n), - .write_data_write(out_6_write_data__write), - .write_resp_dout(out_6_write_resp__dout), - .write_resp_empty_n(out_6_write_resp__empty_n), - .write_resp_read(out_6_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_7__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_7___in_7__q0), - .m_axi_ARADDR(m_axi_in_7_ARADDR), - .m_axi_ARBURST(m_axi_in_7_ARBURST), - .m_axi_ARCACHE(m_axi_in_7_ARCACHE), - .m_axi_ARID(m_axi_in_7_ARID), - .m_axi_ARLEN(m_axi_in_7_ARLEN), - .m_axi_ARLOCK(m_axi_in_7_ARLOCK), - .m_axi_ARPROT(m_axi_in_7_ARPROT), - .m_axi_ARQOS(m_axi_in_7_ARQOS), - .m_axi_ARREADY(m_axi_in_7_ARREADY), - .m_axi_ARSIZE(m_axi_in_7_ARSIZE), - .m_axi_ARVALID(m_axi_in_7_ARVALID), - .m_axi_AWADDR(m_axi_in_7_AWADDR), - .m_axi_AWBURST(m_axi_in_7_AWBURST), - .m_axi_AWCACHE(m_axi_in_7_AWCACHE), - .m_axi_AWID(m_axi_in_7_AWID), - .m_axi_AWLEN(m_axi_in_7_AWLEN), - .m_axi_AWLOCK(m_axi_in_7_AWLOCK), - .m_axi_AWPROT(m_axi_in_7_AWPROT), - .m_axi_AWQOS(m_axi_in_7_AWQOS), - .m_axi_AWREADY(m_axi_in_7_AWREADY), - .m_axi_AWSIZE(m_axi_in_7_AWSIZE), - .m_axi_AWVALID(m_axi_in_7_AWVALID), - .m_axi_BID(m_axi_in_7_BID), - .m_axi_BREADY(m_axi_in_7_BREADY), - .m_axi_BRESP(m_axi_in_7_BRESP), - .m_axi_BVALID(m_axi_in_7_BVALID), - .m_axi_RDATA(m_axi_in_7_RDATA), - .m_axi_RID(m_axi_in_7_RID), - .m_axi_RLAST(m_axi_in_7_RLAST), - .m_axi_RREADY(m_axi_in_7_RREADY), - .m_axi_RRESP(m_axi_in_7_RRESP), - .m_axi_RVALID(m_axi_in_7_RVALID), - .m_axi_WDATA(m_axi_in_7_WDATA), - .m_axi_WLAST(m_axi_in_7_WLAST), - .m_axi_WREADY(m_axi_in_7_WREADY), - .m_axi_WSTRB(m_axi_in_7_WSTRB), - .m_axi_WVALID(m_axi_in_7_WVALID), - .read_addr_din(in_7_read_addr__din), - .read_addr_full_n(in_7_read_addr__full_n), - .read_addr_write(in_7_read_addr__write), - .read_data_dout(in_7_read_data__dout), - .read_data_empty_n(in_7_read_data__empty_n), - .read_data_read(in_7_read_data__read), - .write_addr_din(in_7_write_addr__din), - .write_addr_full_n(in_7_write_addr__full_n), - .write_addr_write(in_7_write_addr__write), - .write_data_din(in_7_write_data__din), - .write_data_full_n(in_7_write_data__full_n), - .write_data_write(in_7_write_data__write), - .write_resp_dout(in_7_write_resp__dout), - .write_resp_empty_n(in_7_write_resp__empty_n), - .write_resp_read(in_7_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_7__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_7___out_7__q0), - .m_axi_ARADDR(m_axi_out_7_ARADDR), - .m_axi_ARBURST(m_axi_out_7_ARBURST), - .m_axi_ARCACHE(m_axi_out_7_ARCACHE), - .m_axi_ARID(m_axi_out_7_ARID), - .m_axi_ARLEN(m_axi_out_7_ARLEN), - .m_axi_ARLOCK(m_axi_out_7_ARLOCK), - .m_axi_ARPROT(m_axi_out_7_ARPROT), - .m_axi_ARQOS(m_axi_out_7_ARQOS), - .m_axi_ARREADY(m_axi_out_7_ARREADY), - .m_axi_ARSIZE(m_axi_out_7_ARSIZE), - .m_axi_ARVALID(m_axi_out_7_ARVALID), - .m_axi_AWADDR(m_axi_out_7_AWADDR), - .m_axi_AWBURST(m_axi_out_7_AWBURST), - .m_axi_AWCACHE(m_axi_out_7_AWCACHE), - .m_axi_AWID(m_axi_out_7_AWID), - .m_axi_AWLEN(m_axi_out_7_AWLEN), - .m_axi_AWLOCK(m_axi_out_7_AWLOCK), - .m_axi_AWPROT(m_axi_out_7_AWPROT), - .m_axi_AWQOS(m_axi_out_7_AWQOS), - .m_axi_AWREADY(m_axi_out_7_AWREADY), - .m_axi_AWSIZE(m_axi_out_7_AWSIZE), - .m_axi_AWVALID(m_axi_out_7_AWVALID), - .m_axi_BID(m_axi_out_7_BID), - .m_axi_BREADY(m_axi_out_7_BREADY), - .m_axi_BRESP(m_axi_out_7_BRESP), - .m_axi_BVALID(m_axi_out_7_BVALID), - .m_axi_RDATA(m_axi_out_7_RDATA), - .m_axi_RID(m_axi_out_7_RID), - .m_axi_RLAST(m_axi_out_7_RLAST), - .m_axi_RREADY(m_axi_out_7_RREADY), - .m_axi_RRESP(m_axi_out_7_RRESP), - .m_axi_RVALID(m_axi_out_7_RVALID), - .m_axi_WDATA(m_axi_out_7_WDATA), - .m_axi_WLAST(m_axi_out_7_WLAST), - .m_axi_WREADY(m_axi_out_7_WREADY), - .m_axi_WSTRB(m_axi_out_7_WSTRB), - .m_axi_WVALID(m_axi_out_7_WVALID), - .read_addr_din(out_7_read_addr__din), - .read_addr_full_n(out_7_read_addr__full_n), - .read_addr_write(out_7_read_addr__write), - .read_data_dout(out_7_read_data__dout), - .read_data_empty_n(out_7_read_data__empty_n), - .read_data_read(out_7_read_data__read), - .write_addr_din(out_7_write_addr__din), - .write_addr_full_n(out_7_write_addr__full_n), - .write_addr_write(out_7_write_addr__write), - .write_data_din(out_7_write_data__din), - .write_data_full_n(out_7_write_data__full_n), - .write_data_write(out_7_write_data__write), - .write_resp_dout(out_7_write_resp__dout), - .write_resp_empty_n(out_7_write_resp__empty_n), - .write_resp_read(out_7_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_8__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_8___in_8__q0), - .m_axi_ARADDR(m_axi_in_8_ARADDR), - .m_axi_ARBURST(m_axi_in_8_ARBURST), - .m_axi_ARCACHE(m_axi_in_8_ARCACHE), - .m_axi_ARID(m_axi_in_8_ARID), - .m_axi_ARLEN(m_axi_in_8_ARLEN), - .m_axi_ARLOCK(m_axi_in_8_ARLOCK), - .m_axi_ARPROT(m_axi_in_8_ARPROT), - .m_axi_ARQOS(m_axi_in_8_ARQOS), - .m_axi_ARREADY(m_axi_in_8_ARREADY), - .m_axi_ARSIZE(m_axi_in_8_ARSIZE), - .m_axi_ARVALID(m_axi_in_8_ARVALID), - .m_axi_AWADDR(m_axi_in_8_AWADDR), - .m_axi_AWBURST(m_axi_in_8_AWBURST), - .m_axi_AWCACHE(m_axi_in_8_AWCACHE), - .m_axi_AWID(m_axi_in_8_AWID), - .m_axi_AWLEN(m_axi_in_8_AWLEN), - .m_axi_AWLOCK(m_axi_in_8_AWLOCK), - .m_axi_AWPROT(m_axi_in_8_AWPROT), - .m_axi_AWQOS(m_axi_in_8_AWQOS), - .m_axi_AWREADY(m_axi_in_8_AWREADY), - .m_axi_AWSIZE(m_axi_in_8_AWSIZE), - .m_axi_AWVALID(m_axi_in_8_AWVALID), - .m_axi_BID(m_axi_in_8_BID), - .m_axi_BREADY(m_axi_in_8_BREADY), - .m_axi_BRESP(m_axi_in_8_BRESP), - .m_axi_BVALID(m_axi_in_8_BVALID), - .m_axi_RDATA(m_axi_in_8_RDATA), - .m_axi_RID(m_axi_in_8_RID), - .m_axi_RLAST(m_axi_in_8_RLAST), - .m_axi_RREADY(m_axi_in_8_RREADY), - .m_axi_RRESP(m_axi_in_8_RRESP), - .m_axi_RVALID(m_axi_in_8_RVALID), - .m_axi_WDATA(m_axi_in_8_WDATA), - .m_axi_WLAST(m_axi_in_8_WLAST), - .m_axi_WREADY(m_axi_in_8_WREADY), - .m_axi_WSTRB(m_axi_in_8_WSTRB), - .m_axi_WVALID(m_axi_in_8_WVALID), - .read_addr_din(in_8_read_addr__din), - .read_addr_full_n(in_8_read_addr__full_n), - .read_addr_write(in_8_read_addr__write), - .read_data_dout(in_8_read_data__dout), - .read_data_empty_n(in_8_read_data__empty_n), - .read_data_read(in_8_read_data__read), - .write_addr_din(in_8_write_addr__din), - .write_addr_full_n(in_8_write_addr__full_n), - .write_addr_write(in_8_write_addr__write), - .write_data_din(in_8_write_data__din), - .write_data_full_n(in_8_write_data__full_n), - .write_data_write(in_8_write_data__write), - .write_resp_dout(in_8_write_resp__dout), - .write_resp_empty_n(in_8_write_resp__empty_n), - .write_resp_read(in_8_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_8__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_8___out_8__q0), - .m_axi_ARADDR(m_axi_out_8_ARADDR), - .m_axi_ARBURST(m_axi_out_8_ARBURST), - .m_axi_ARCACHE(m_axi_out_8_ARCACHE), - .m_axi_ARID(m_axi_out_8_ARID), - .m_axi_ARLEN(m_axi_out_8_ARLEN), - .m_axi_ARLOCK(m_axi_out_8_ARLOCK), - .m_axi_ARPROT(m_axi_out_8_ARPROT), - .m_axi_ARQOS(m_axi_out_8_ARQOS), - .m_axi_ARREADY(m_axi_out_8_ARREADY), - .m_axi_ARSIZE(m_axi_out_8_ARSIZE), - .m_axi_ARVALID(m_axi_out_8_ARVALID), - .m_axi_AWADDR(m_axi_out_8_AWADDR), - .m_axi_AWBURST(m_axi_out_8_AWBURST), - .m_axi_AWCACHE(m_axi_out_8_AWCACHE), - .m_axi_AWID(m_axi_out_8_AWID), - .m_axi_AWLEN(m_axi_out_8_AWLEN), - .m_axi_AWLOCK(m_axi_out_8_AWLOCK), - .m_axi_AWPROT(m_axi_out_8_AWPROT), - .m_axi_AWQOS(m_axi_out_8_AWQOS), - .m_axi_AWREADY(m_axi_out_8_AWREADY), - .m_axi_AWSIZE(m_axi_out_8_AWSIZE), - .m_axi_AWVALID(m_axi_out_8_AWVALID), - .m_axi_BID(m_axi_out_8_BID), - .m_axi_BREADY(m_axi_out_8_BREADY), - .m_axi_BRESP(m_axi_out_8_BRESP), - .m_axi_BVALID(m_axi_out_8_BVALID), - .m_axi_RDATA(m_axi_out_8_RDATA), - .m_axi_RID(m_axi_out_8_RID), - .m_axi_RLAST(m_axi_out_8_RLAST), - .m_axi_RREADY(m_axi_out_8_RREADY), - .m_axi_RRESP(m_axi_out_8_RRESP), - .m_axi_RVALID(m_axi_out_8_RVALID), - .m_axi_WDATA(m_axi_out_8_WDATA), - .m_axi_WLAST(m_axi_out_8_WLAST), - .m_axi_WREADY(m_axi_out_8_WREADY), - .m_axi_WSTRB(m_axi_out_8_WSTRB), - .m_axi_WVALID(m_axi_out_8_WVALID), - .read_addr_din(out_8_read_addr__din), - .read_addr_full_n(out_8_read_addr__full_n), - .read_addr_write(out_8_read_addr__write), - .read_data_dout(out_8_read_data__dout), - .read_data_empty_n(out_8_read_data__empty_n), - .read_data_read(out_8_read_data__read), - .write_addr_din(out_8_write_addr__din), - .write_addr_full_n(out_8_write_addr__full_n), - .write_addr_write(out_8_write_addr__write), - .write_data_din(out_8_write_data__din), - .write_data_full_n(out_8_write_data__full_n), - .write_data_write(out_8_write_data__write), - .write_resp_dout(out_8_write_resp__dout), - .write_resp_empty_n(out_8_write_resp__empty_n), - .write_resp_read(out_8_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_9__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_9___in_9__q0), - .m_axi_ARADDR(m_axi_in_9_ARADDR), - .m_axi_ARBURST(m_axi_in_9_ARBURST), - .m_axi_ARCACHE(m_axi_in_9_ARCACHE), - .m_axi_ARID(m_axi_in_9_ARID), - .m_axi_ARLEN(m_axi_in_9_ARLEN), - .m_axi_ARLOCK(m_axi_in_9_ARLOCK), - .m_axi_ARPROT(m_axi_in_9_ARPROT), - .m_axi_ARQOS(m_axi_in_9_ARQOS), - .m_axi_ARREADY(m_axi_in_9_ARREADY), - .m_axi_ARSIZE(m_axi_in_9_ARSIZE), - .m_axi_ARVALID(m_axi_in_9_ARVALID), - .m_axi_AWADDR(m_axi_in_9_AWADDR), - .m_axi_AWBURST(m_axi_in_9_AWBURST), - .m_axi_AWCACHE(m_axi_in_9_AWCACHE), - .m_axi_AWID(m_axi_in_9_AWID), - .m_axi_AWLEN(m_axi_in_9_AWLEN), - .m_axi_AWLOCK(m_axi_in_9_AWLOCK), - .m_axi_AWPROT(m_axi_in_9_AWPROT), - .m_axi_AWQOS(m_axi_in_9_AWQOS), - .m_axi_AWREADY(m_axi_in_9_AWREADY), - .m_axi_AWSIZE(m_axi_in_9_AWSIZE), - .m_axi_AWVALID(m_axi_in_9_AWVALID), - .m_axi_BID(m_axi_in_9_BID), - .m_axi_BREADY(m_axi_in_9_BREADY), - .m_axi_BRESP(m_axi_in_9_BRESP), - .m_axi_BVALID(m_axi_in_9_BVALID), - .m_axi_RDATA(m_axi_in_9_RDATA), - .m_axi_RID(m_axi_in_9_RID), - .m_axi_RLAST(m_axi_in_9_RLAST), - .m_axi_RREADY(m_axi_in_9_RREADY), - .m_axi_RRESP(m_axi_in_9_RRESP), - .m_axi_RVALID(m_axi_in_9_RVALID), - .m_axi_WDATA(m_axi_in_9_WDATA), - .m_axi_WLAST(m_axi_in_9_WLAST), - .m_axi_WREADY(m_axi_in_9_WREADY), - .m_axi_WSTRB(m_axi_in_9_WSTRB), - .m_axi_WVALID(m_axi_in_9_WVALID), - .read_addr_din(in_9_read_addr__din), - .read_addr_full_n(in_9_read_addr__full_n), - .read_addr_write(in_9_read_addr__write), - .read_data_dout(in_9_read_data__dout), - .read_data_empty_n(in_9_read_data__empty_n), - .read_data_read(in_9_read_data__read), - .write_addr_din(in_9_write_addr__din), - .write_addr_full_n(in_9_write_addr__full_n), - .write_addr_write(in_9_write_addr__write), - .write_data_din(in_9_write_data__din), - .write_data_full_n(in_9_write_data__full_n), - .write_data_write(in_9_write_data__write), - .write_resp_dout(in_9_write_resp__dout), - .write_resp_empty_n(in_9_write_resp__empty_n), - .write_resp_read(in_9_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_9__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_9___out_9__q0), - .m_axi_ARADDR(m_axi_out_9_ARADDR), - .m_axi_ARBURST(m_axi_out_9_ARBURST), - .m_axi_ARCACHE(m_axi_out_9_ARCACHE), - .m_axi_ARID(m_axi_out_9_ARID), - .m_axi_ARLEN(m_axi_out_9_ARLEN), - .m_axi_ARLOCK(m_axi_out_9_ARLOCK), - .m_axi_ARPROT(m_axi_out_9_ARPROT), - .m_axi_ARQOS(m_axi_out_9_ARQOS), - .m_axi_ARREADY(m_axi_out_9_ARREADY), - .m_axi_ARSIZE(m_axi_out_9_ARSIZE), - .m_axi_ARVALID(m_axi_out_9_ARVALID), - .m_axi_AWADDR(m_axi_out_9_AWADDR), - .m_axi_AWBURST(m_axi_out_9_AWBURST), - .m_axi_AWCACHE(m_axi_out_9_AWCACHE), - .m_axi_AWID(m_axi_out_9_AWID), - .m_axi_AWLEN(m_axi_out_9_AWLEN), - .m_axi_AWLOCK(m_axi_out_9_AWLOCK), - .m_axi_AWPROT(m_axi_out_9_AWPROT), - .m_axi_AWQOS(m_axi_out_9_AWQOS), - .m_axi_AWREADY(m_axi_out_9_AWREADY), - .m_axi_AWSIZE(m_axi_out_9_AWSIZE), - .m_axi_AWVALID(m_axi_out_9_AWVALID), - .m_axi_BID(m_axi_out_9_BID), - .m_axi_BREADY(m_axi_out_9_BREADY), - .m_axi_BRESP(m_axi_out_9_BRESP), - .m_axi_BVALID(m_axi_out_9_BVALID), - .m_axi_RDATA(m_axi_out_9_RDATA), - .m_axi_RID(m_axi_out_9_RID), - .m_axi_RLAST(m_axi_out_9_RLAST), - .m_axi_RREADY(m_axi_out_9_RREADY), - .m_axi_RRESP(m_axi_out_9_RRESP), - .m_axi_RVALID(m_axi_out_9_RVALID), - .m_axi_WDATA(m_axi_out_9_WDATA), - .m_axi_WLAST(m_axi_out_9_WLAST), - .m_axi_WREADY(m_axi_out_9_WREADY), - .m_axi_WSTRB(m_axi_out_9_WSTRB), - .m_axi_WVALID(m_axi_out_9_WVALID), - .read_addr_din(out_9_read_addr__din), - .read_addr_full_n(out_9_read_addr__full_n), - .read_addr_write(out_9_read_addr__write), - .read_data_dout(out_9_read_data__dout), - .read_data_empty_n(out_9_read_data__empty_n), - .read_data_read(out_9_read_data__read), - .write_addr_din(out_9_write_addr__din), - .write_addr_full_n(out_9_write_addr__full_n), - .write_addr_write(out_9_write_addr__write), - .write_data_din(out_9_write_data__din), - .write_data_full_n(out_9_write_data__full_n), - .write_data_write(out_9_write_data__write), - .write_resp_dout(out_9_write_resp__dout), - .write_resp_empty_n(out_9_write_resp__empty_n), - .write_resp_read(out_9_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_10__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_10___in_10__q0), - .m_axi_ARADDR(m_axi_in_10_ARADDR), - .m_axi_ARBURST(m_axi_in_10_ARBURST), - .m_axi_ARCACHE(m_axi_in_10_ARCACHE), - .m_axi_ARID(m_axi_in_10_ARID), - .m_axi_ARLEN(m_axi_in_10_ARLEN), - .m_axi_ARLOCK(m_axi_in_10_ARLOCK), - .m_axi_ARPROT(m_axi_in_10_ARPROT), - .m_axi_ARQOS(m_axi_in_10_ARQOS), - .m_axi_ARREADY(m_axi_in_10_ARREADY), - .m_axi_ARSIZE(m_axi_in_10_ARSIZE), - .m_axi_ARVALID(m_axi_in_10_ARVALID), - .m_axi_AWADDR(m_axi_in_10_AWADDR), - .m_axi_AWBURST(m_axi_in_10_AWBURST), - .m_axi_AWCACHE(m_axi_in_10_AWCACHE), - .m_axi_AWID(m_axi_in_10_AWID), - .m_axi_AWLEN(m_axi_in_10_AWLEN), - .m_axi_AWLOCK(m_axi_in_10_AWLOCK), - .m_axi_AWPROT(m_axi_in_10_AWPROT), - .m_axi_AWQOS(m_axi_in_10_AWQOS), - .m_axi_AWREADY(m_axi_in_10_AWREADY), - .m_axi_AWSIZE(m_axi_in_10_AWSIZE), - .m_axi_AWVALID(m_axi_in_10_AWVALID), - .m_axi_BID(m_axi_in_10_BID), - .m_axi_BREADY(m_axi_in_10_BREADY), - .m_axi_BRESP(m_axi_in_10_BRESP), - .m_axi_BVALID(m_axi_in_10_BVALID), - .m_axi_RDATA(m_axi_in_10_RDATA), - .m_axi_RID(m_axi_in_10_RID), - .m_axi_RLAST(m_axi_in_10_RLAST), - .m_axi_RREADY(m_axi_in_10_RREADY), - .m_axi_RRESP(m_axi_in_10_RRESP), - .m_axi_RVALID(m_axi_in_10_RVALID), - .m_axi_WDATA(m_axi_in_10_WDATA), - .m_axi_WLAST(m_axi_in_10_WLAST), - .m_axi_WREADY(m_axi_in_10_WREADY), - .m_axi_WSTRB(m_axi_in_10_WSTRB), - .m_axi_WVALID(m_axi_in_10_WVALID), - .read_addr_din(in_10_read_addr__din), - .read_addr_full_n(in_10_read_addr__full_n), - .read_addr_write(in_10_read_addr__write), - .read_data_dout(in_10_read_data__dout), - .read_data_empty_n(in_10_read_data__empty_n), - .read_data_read(in_10_read_data__read), - .write_addr_din(in_10_write_addr__din), - .write_addr_full_n(in_10_write_addr__full_n), - .write_addr_write(in_10_write_addr__write), - .write_data_din(in_10_write_data__din), - .write_data_full_n(in_10_write_data__full_n), - .write_data_write(in_10_write_data__write), - .write_resp_dout(in_10_write_resp__dout), - .write_resp_empty_n(in_10_write_resp__empty_n), - .write_resp_read(in_10_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_10__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_10___out_10__q0), - .m_axi_ARADDR(m_axi_out_10_ARADDR), - .m_axi_ARBURST(m_axi_out_10_ARBURST), - .m_axi_ARCACHE(m_axi_out_10_ARCACHE), - .m_axi_ARID(m_axi_out_10_ARID), - .m_axi_ARLEN(m_axi_out_10_ARLEN), - .m_axi_ARLOCK(m_axi_out_10_ARLOCK), - .m_axi_ARPROT(m_axi_out_10_ARPROT), - .m_axi_ARQOS(m_axi_out_10_ARQOS), - .m_axi_ARREADY(m_axi_out_10_ARREADY), - .m_axi_ARSIZE(m_axi_out_10_ARSIZE), - .m_axi_ARVALID(m_axi_out_10_ARVALID), - .m_axi_AWADDR(m_axi_out_10_AWADDR), - .m_axi_AWBURST(m_axi_out_10_AWBURST), - .m_axi_AWCACHE(m_axi_out_10_AWCACHE), - .m_axi_AWID(m_axi_out_10_AWID), - .m_axi_AWLEN(m_axi_out_10_AWLEN), - .m_axi_AWLOCK(m_axi_out_10_AWLOCK), - .m_axi_AWPROT(m_axi_out_10_AWPROT), - .m_axi_AWQOS(m_axi_out_10_AWQOS), - .m_axi_AWREADY(m_axi_out_10_AWREADY), - .m_axi_AWSIZE(m_axi_out_10_AWSIZE), - .m_axi_AWVALID(m_axi_out_10_AWVALID), - .m_axi_BID(m_axi_out_10_BID), - .m_axi_BREADY(m_axi_out_10_BREADY), - .m_axi_BRESP(m_axi_out_10_BRESP), - .m_axi_BVALID(m_axi_out_10_BVALID), - .m_axi_RDATA(m_axi_out_10_RDATA), - .m_axi_RID(m_axi_out_10_RID), - .m_axi_RLAST(m_axi_out_10_RLAST), - .m_axi_RREADY(m_axi_out_10_RREADY), - .m_axi_RRESP(m_axi_out_10_RRESP), - .m_axi_RVALID(m_axi_out_10_RVALID), - .m_axi_WDATA(m_axi_out_10_WDATA), - .m_axi_WLAST(m_axi_out_10_WLAST), - .m_axi_WREADY(m_axi_out_10_WREADY), - .m_axi_WSTRB(m_axi_out_10_WSTRB), - .m_axi_WVALID(m_axi_out_10_WVALID), - .read_addr_din(out_10_read_addr__din), - .read_addr_full_n(out_10_read_addr__full_n), - .read_addr_write(out_10_read_addr__write), - .read_data_dout(out_10_read_data__dout), - .read_data_empty_n(out_10_read_data__empty_n), - .read_data_read(out_10_read_data__read), - .write_addr_din(out_10_write_addr__din), - .write_addr_full_n(out_10_write_addr__full_n), - .write_addr_write(out_10_write_addr__write), - .write_data_din(out_10_write_data__din), - .write_data_full_n(out_10_write_data__full_n), - .write_data_write(out_10_write_data__write), - .write_resp_dout(out_10_write_resp__dout), - .write_resp_empty_n(out_10_write_resp__empty_n), - .write_resp_read(out_10_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - in_11__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_11___in_11__q0), - .m_axi_ARADDR(m_axi_in_11_ARADDR), - .m_axi_ARBURST(m_axi_in_11_ARBURST), - .m_axi_ARCACHE(m_axi_in_11_ARCACHE), - .m_axi_ARID(m_axi_in_11_ARID), - .m_axi_ARLEN(m_axi_in_11_ARLEN), - .m_axi_ARLOCK(m_axi_in_11_ARLOCK), - .m_axi_ARPROT(m_axi_in_11_ARPROT), - .m_axi_ARQOS(m_axi_in_11_ARQOS), - .m_axi_ARREADY(m_axi_in_11_ARREADY), - .m_axi_ARSIZE(m_axi_in_11_ARSIZE), - .m_axi_ARVALID(m_axi_in_11_ARVALID), - .m_axi_AWADDR(m_axi_in_11_AWADDR), - .m_axi_AWBURST(m_axi_in_11_AWBURST), - .m_axi_AWCACHE(m_axi_in_11_AWCACHE), - .m_axi_AWID(m_axi_in_11_AWID), - .m_axi_AWLEN(m_axi_in_11_AWLEN), - .m_axi_AWLOCK(m_axi_in_11_AWLOCK), - .m_axi_AWPROT(m_axi_in_11_AWPROT), - .m_axi_AWQOS(m_axi_in_11_AWQOS), - .m_axi_AWREADY(m_axi_in_11_AWREADY), - .m_axi_AWSIZE(m_axi_in_11_AWSIZE), - .m_axi_AWVALID(m_axi_in_11_AWVALID), - .m_axi_BID(m_axi_in_11_BID), - .m_axi_BREADY(m_axi_in_11_BREADY), - .m_axi_BRESP(m_axi_in_11_BRESP), - .m_axi_BVALID(m_axi_in_11_BVALID), - .m_axi_RDATA(m_axi_in_11_RDATA), - .m_axi_RID(m_axi_in_11_RID), - .m_axi_RLAST(m_axi_in_11_RLAST), - .m_axi_RREADY(m_axi_in_11_RREADY), - .m_axi_RRESP(m_axi_in_11_RRESP), - .m_axi_RVALID(m_axi_in_11_RVALID), - .m_axi_WDATA(m_axi_in_11_WDATA), - .m_axi_WLAST(m_axi_in_11_WLAST), - .m_axi_WREADY(m_axi_in_11_WREADY), - .m_axi_WSTRB(m_axi_in_11_WSTRB), - .m_axi_WVALID(m_axi_in_11_WVALID), - .read_addr_din(in_11_read_addr__din), - .read_addr_full_n(in_11_read_addr__full_n), - .read_addr_write(in_11_read_addr__write), - .read_data_dout(in_11_read_data__dout), - .read_data_empty_n(in_11_read_data__empty_n), - .read_data_read(in_11_read_data__read), - .write_addr_din(in_11_write_addr__din), - .write_addr_full_n(in_11_write_addr__full_n), - .write_addr_write(in_11_write_addr__write), - .write_data_din(in_11_write_data__din), - .write_data_full_n(in_11_write_data__full_n), - .write_data_write(in_11_write_data__write), - .write_resp_dout(in_11_write_resp__dout), - .write_resp_empty_n(in_11_write_resp__empty_n), - .write_resp_read(in_11_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) async_mmap - #( - .DataWidth(512), - .DataWidthBytesLog(6), - .AddrWidth(64), - .WaitTimeWidth(2), - .MaxWaitTime(3), - .BurstLenWidth(9), - .MaxBurstLen(15) - ) - out_11__m_axi - ( - .clk(ap_clk), - .rst(~ap_rst_n), - .offset(inter_kernel_11___out_11__q0), - .m_axi_ARADDR(m_axi_out_11_ARADDR), - .m_axi_ARBURST(m_axi_out_11_ARBURST), - .m_axi_ARCACHE(m_axi_out_11_ARCACHE), - .m_axi_ARID(m_axi_out_11_ARID), - .m_axi_ARLEN(m_axi_out_11_ARLEN), - .m_axi_ARLOCK(m_axi_out_11_ARLOCK), - .m_axi_ARPROT(m_axi_out_11_ARPROT), - .m_axi_ARQOS(m_axi_out_11_ARQOS), - .m_axi_ARREADY(m_axi_out_11_ARREADY), - .m_axi_ARSIZE(m_axi_out_11_ARSIZE), - .m_axi_ARVALID(m_axi_out_11_ARVALID), - .m_axi_AWADDR(m_axi_out_11_AWADDR), - .m_axi_AWBURST(m_axi_out_11_AWBURST), - .m_axi_AWCACHE(m_axi_out_11_AWCACHE), - .m_axi_AWID(m_axi_out_11_AWID), - .m_axi_AWLEN(m_axi_out_11_AWLEN), - .m_axi_AWLOCK(m_axi_out_11_AWLOCK), - .m_axi_AWPROT(m_axi_out_11_AWPROT), - .m_axi_AWQOS(m_axi_out_11_AWQOS), - .m_axi_AWREADY(m_axi_out_11_AWREADY), - .m_axi_AWSIZE(m_axi_out_11_AWSIZE), - .m_axi_AWVALID(m_axi_out_11_AWVALID), - .m_axi_BID(m_axi_out_11_BID), - .m_axi_BREADY(m_axi_out_11_BREADY), - .m_axi_BRESP(m_axi_out_11_BRESP), - .m_axi_BVALID(m_axi_out_11_BVALID), - .m_axi_RDATA(m_axi_out_11_RDATA), - .m_axi_RID(m_axi_out_11_RID), - .m_axi_RLAST(m_axi_out_11_RLAST), - .m_axi_RREADY(m_axi_out_11_RREADY), - .m_axi_RRESP(m_axi_out_11_RRESP), - .m_axi_RVALID(m_axi_out_11_RVALID), - .m_axi_WDATA(m_axi_out_11_WDATA), - .m_axi_WLAST(m_axi_out_11_WLAST), - .m_axi_WREADY(m_axi_out_11_WREADY), - .m_axi_WSTRB(m_axi_out_11_WSTRB), - .m_axi_WVALID(m_axi_out_11_WVALID), - .read_addr_din(out_11_read_addr__din), - .read_addr_full_n(out_11_read_addr__full_n), - .read_addr_write(out_11_read_addr__write), - .read_data_dout(out_11_read_data__dout), - .read_data_empty_n(out_11_read_data__empty_n), - .read_data_read(out_11_read_data__read), - .write_addr_din(out_11_write_addr__din), - .write_addr_full_n(out_11_write_addr__full_n), - .write_addr_write(out_11_write_addr__write), - .write_data_din(out_11_write_data__din), - .write_data_full_n(out_11_write_data__full_n), - .write_data_write(out_11_write_data__write), - .write_resp_dout(out_11_write_resp__dout), - .write_resp_empty_n(out_11_write_resp__empty_n), - .write_resp_read(out_11_write_resp__read) - ); - - - (* keep_hierarchy = "yes" *) unikernel_fsm - __tapa_fsm_unit - ( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .ap_start(ap_start), - .ap_done(ap_done), - .ap_idle(ap_idle), - .ap_ready(ap_ready), - .HEAT3D_0__ap_start(HEAT3D_0__ap_start), - .HEAT3D_0__ap_ready(HEAT3D_0__ap_ready), - .HEAT3D_0__ap_done(HEAT3D_0__ap_done), - .HEAT3D_0__ap_idle(HEAT3D_0__ap_idle), - .HEAT3D_1__ap_start(HEAT3D_1__ap_start), - .HEAT3D_1__ap_ready(HEAT3D_1__ap_ready), - .HEAT3D_1__ap_done(HEAT3D_1__ap_done), - .HEAT3D_1__ap_idle(HEAT3D_1__ap_idle), - .HEAT3D_2__ap_start(HEAT3D_2__ap_start), - .HEAT3D_2__ap_ready(HEAT3D_2__ap_ready), - .HEAT3D_2__ap_done(HEAT3D_2__ap_done), - .HEAT3D_2__ap_idle(HEAT3D_2__ap_idle), - .HEAT3D_3__ap_start(HEAT3D_3__ap_start), - .HEAT3D_3__ap_ready(HEAT3D_3__ap_ready), - .HEAT3D_3__ap_done(HEAT3D_3__ap_done), - .HEAT3D_3__ap_idle(HEAT3D_3__ap_idle), - .HEAT3D_4__ap_start(HEAT3D_4__ap_start), - .HEAT3D_4__ap_ready(HEAT3D_4__ap_ready), - .HEAT3D_4__ap_done(HEAT3D_4__ap_done), - .HEAT3D_4__ap_idle(HEAT3D_4__ap_idle), - .HEAT3D_5__ap_start(HEAT3D_5__ap_start), - .HEAT3D_5__ap_ready(HEAT3D_5__ap_ready), - .HEAT3D_5__ap_done(HEAT3D_5__ap_done), - .HEAT3D_5__ap_idle(HEAT3D_5__ap_idle), - .HEAT3D_6__ap_start(HEAT3D_6__ap_start), - .HEAT3D_6__ap_ready(HEAT3D_6__ap_ready), - .HEAT3D_6__ap_done(HEAT3D_6__ap_done), - .HEAT3D_6__ap_idle(HEAT3D_6__ap_idle), - .HEAT3D_7__ap_start(HEAT3D_7__ap_start), - .HEAT3D_7__ap_ready(HEAT3D_7__ap_ready), - .HEAT3D_7__ap_done(HEAT3D_7__ap_done), - .HEAT3D_7__ap_idle(HEAT3D_7__ap_idle), - .HEAT3D_8__ap_start(HEAT3D_8__ap_start), - .HEAT3D_8__ap_ready(HEAT3D_8__ap_ready), - .HEAT3D_8__ap_done(HEAT3D_8__ap_done), - .HEAT3D_8__ap_idle(HEAT3D_8__ap_idle), - .HEAT3D_9__ap_start(HEAT3D_9__ap_start), - .HEAT3D_9__ap_ready(HEAT3D_9__ap_ready), - .HEAT3D_9__ap_done(HEAT3D_9__ap_done), - .HEAT3D_9__ap_idle(HEAT3D_9__ap_idle), - .HEAT3D_10__ap_start(HEAT3D_10__ap_start), - .HEAT3D_10__ap_ready(HEAT3D_10__ap_ready), - .HEAT3D_10__ap_done(HEAT3D_10__ap_done), - .HEAT3D_10__ap_idle(HEAT3D_10__ap_idle), - .HEAT3D_11__ap_start(HEAT3D_11__ap_start), - .HEAT3D_11__ap_ready(HEAT3D_11__ap_ready), - .HEAT3D_11__ap_done(HEAT3D_11__ap_done), - .HEAT3D_11__ap_idle(HEAT3D_11__ap_idle), - .inter_kernel_0__ap_start(inter_kernel_0__ap_start), - .inter_kernel_0__ap_ready(inter_kernel_0__ap_ready), - .inter_kernel_0__ap_done(inter_kernel_0__ap_done), - .inter_kernel_0__ap_idle(inter_kernel_0__ap_idle), - .inter_kernel_1__ap_start(inter_kernel_1__ap_start), - .inter_kernel_1__ap_ready(inter_kernel_1__ap_ready), - .inter_kernel_1__ap_done(inter_kernel_1__ap_done), - .inter_kernel_1__ap_idle(inter_kernel_1__ap_idle), - .inter_kernel_2__ap_start(inter_kernel_2__ap_start), - .inter_kernel_2__ap_ready(inter_kernel_2__ap_ready), - .inter_kernel_2__ap_done(inter_kernel_2__ap_done), - .inter_kernel_2__ap_idle(inter_kernel_2__ap_idle), - .inter_kernel_3__ap_start(inter_kernel_3__ap_start), - .inter_kernel_3__ap_ready(inter_kernel_3__ap_ready), - .inter_kernel_3__ap_done(inter_kernel_3__ap_done), - .inter_kernel_3__ap_idle(inter_kernel_3__ap_idle), - .inter_kernel_4__ap_start(inter_kernel_4__ap_start), - .inter_kernel_4__ap_ready(inter_kernel_4__ap_ready), - .inter_kernel_4__ap_done(inter_kernel_4__ap_done), - .inter_kernel_4__ap_idle(inter_kernel_4__ap_idle), - .inter_kernel_5__ap_start(inter_kernel_5__ap_start), - .inter_kernel_5__ap_ready(inter_kernel_5__ap_ready), - .inter_kernel_5__ap_done(inter_kernel_5__ap_done), - .inter_kernel_5__ap_idle(inter_kernel_5__ap_idle), - .inter_kernel_6__ap_start(inter_kernel_6__ap_start), - .inter_kernel_6__ap_ready(inter_kernel_6__ap_ready), - .inter_kernel_6__ap_done(inter_kernel_6__ap_done), - .inter_kernel_6__ap_idle(inter_kernel_6__ap_idle), - .inter_kernel_7__ap_start(inter_kernel_7__ap_start), - .inter_kernel_7__ap_ready(inter_kernel_7__ap_ready), - .inter_kernel_7__ap_done(inter_kernel_7__ap_done), - .inter_kernel_7__ap_idle(inter_kernel_7__ap_idle), - .inter_kernel_8__ap_start(inter_kernel_8__ap_start), - .inter_kernel_8__ap_ready(inter_kernel_8__ap_ready), - .inter_kernel_8__ap_done(inter_kernel_8__ap_done), - .inter_kernel_8__ap_idle(inter_kernel_8__ap_idle), - .inter_kernel_9__ap_start(inter_kernel_9__ap_start), - .inter_kernel_9__ap_ready(inter_kernel_9__ap_ready), - .inter_kernel_9__ap_done(inter_kernel_9__ap_done), - .inter_kernel_9__ap_idle(inter_kernel_9__ap_idle), - .inter_kernel_10__ap_start(inter_kernel_10__ap_start), - .inter_kernel_10__ap_ready(inter_kernel_10__ap_ready), - .inter_kernel_10__ap_done(inter_kernel_10__ap_done), - .inter_kernel_10__ap_idle(inter_kernel_10__ap_idle), - .inter_kernel_11__ap_start(inter_kernel_11__ap_start), - .inter_kernel_11__ap_ready(inter_kernel_11__ap_ready), - .inter_kernel_11__ap_done(inter_kernel_11__ap_done), - .inter_kernel_11__ap_idle(inter_kernel_11__ap_idle) - ); - - assign ap_rst_n_inv = (~ap_rst_n); - assign HEAT3D_0___iters__q0 = iters; - assign HEAT3D_1___iters__q0 = iters; - assign HEAT3D_2___iters__q0 = iters; - assign HEAT3D_3___iters__q0 = iters; - assign HEAT3D_4___iters__q0 = iters; - assign HEAT3D_5___iters__q0 = iters; - assign HEAT3D_6___iters__q0 = iters; - assign HEAT3D_7___iters__q0 = iters; - assign HEAT3D_8___iters__q0 = iters; - assign HEAT3D_9___iters__q0 = iters; - assign HEAT3D_10___iters__q0 = iters; - assign HEAT3D_11___iters__q0 = iters; - assign inter_kernel_0___in_0__q0 = in_0; - assign inter_kernel_0___iters__q0 = iters; - assign inter_kernel_0___out_0__q0 = out_0; - assign inter_kernel_1___in_1__q0 = in_1; - assign inter_kernel_1___iters__q0 = iters; - assign inter_kernel_1___out_1__q0 = out_1; - assign inter_kernel_2___in_2__q0 = in_2; - assign inter_kernel_2___iters__q0 = iters; - assign inter_kernel_2___out_2__q0 = out_2; - assign inter_kernel_3___in_3__q0 = in_3; - assign inter_kernel_3___iters__q0 = iters; - assign inter_kernel_3___out_3__q0 = out_3; - assign inter_kernel_4___in_4__q0 = in_4; - assign inter_kernel_4___iters__q0 = iters; - assign inter_kernel_4___out_4__q0 = out_4; - assign inter_kernel_5___in_5__q0 = in_5; - assign inter_kernel_5___iters__q0 = iters; - assign inter_kernel_5___out_5__q0 = out_5; - assign inter_kernel_6___in_6__q0 = in_6; - assign inter_kernel_6___iters__q0 = iters; - assign inter_kernel_6___out_6__q0 = out_6; - assign inter_kernel_7___in_7__q0 = in_7; - assign inter_kernel_7___iters__q0 = iters; - assign inter_kernel_7___out_7__q0 = out_7; - assign inter_kernel_8___in_8__q0 = in_8; - assign inter_kernel_8___iters__q0 = iters; - assign inter_kernel_8___out_8__q0 = out_8; - assign inter_kernel_9___in_9__q0 = in_9; - assign inter_kernel_9___iters__q0 = iters; - assign inter_kernel_9___out_9__q0 = out_9; - assign inter_kernel_10___in_10__q0 = in_10; - assign inter_kernel_10___iters__q0 = iters; - assign inter_kernel_10___out_10__q0 = out_10; - assign inter_kernel_11___in_11__q0 = in_11; - assign inter_kernel_11___iters__q0 = iters; - assign inter_kernel_11___out_11__q0 = out_11; - -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/unikernel_control_s_axi.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/unikernel_control_s_axi.v deleted file mode 100644 index 6005a635..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/unikernel_control_s_axi.v +++ /dev/null @@ -1,1263 +0,0 @@ -// ============================================================== -// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit) -// Tool Version Limit: 2019.12 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// ============================================================== -`timescale 1ns/1ps -module unikernel_control_s_axi -#(parameter - C_S_AXI_ADDR_WIDTH = 9, - C_S_AXI_DATA_WIDTH = 32 -)( - input wire ACLK, - input wire ARESET, - input wire ACLK_EN, - input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR, - input wire AWVALID, - output wire AWREADY, - input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA, - input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB, - input wire WVALID, - output wire WREADY, - output wire [1:0] BRESP, - output wire BVALID, - input wire BREADY, - input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR, - input wire ARVALID, - output wire ARREADY, - output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA, - output wire [1:0] RRESP, - output wire RVALID, - input wire RREADY, - output wire interrupt, - output wire [63:0] in_0, - output wire [63:0] out_0, - output wire [63:0] in_1, - output wire [63:0] out_1, - output wire [63:0] in_2, - output wire [63:0] out_2, - output wire [63:0] in_3, - output wire [63:0] out_3, - output wire [63:0] in_4, - output wire [63:0] out_4, - output wire [63:0] in_5, - output wire [63:0] out_5, - output wire [63:0] in_6, - output wire [63:0] out_6, - output wire [63:0] in_7, - output wire [63:0] out_7, - output wire [63:0] in_8, - output wire [63:0] out_8, - output wire [63:0] in_9, - output wire [63:0] out_9, - output wire [63:0] in_10, - output wire [63:0] out_10, - output wire [63:0] in_11, - output wire [63:0] out_11, - output wire [31:0] iters, - output wire ap_start, - input wire ap_done, - input wire ap_ready, - input wire ap_idle -); -//------------------------Address Info------------------- -// 0x000 : Control signals -// bit 0 - ap_start (Read/Write/SC) -// bit 1 - ap_done (Read/COR) -// bit 2 - ap_idle (Read) -// bit 3 - ap_ready (Read/COR) -// bit 7 - auto_restart (Read/Write) -// bit 9 - interrupt (Read) -// others - reserved -// 0x004 : Global Interrupt Enable Register -// bit 0 - Global Interrupt Enable (Read/Write) -// others - reserved -// 0x008 : IP Interrupt Enable Register (Read/Write) -// bit 0 - enable ap_done interrupt (Read/Write) -// others - reserved -// 0x00c : IP Interrupt Status Register (Read/TOW) -// bit 0 - ap_done (Read/TOW) -// others - reserved -// 0x010 : Data signal of in_0 -// bit 31~0 - in_0[31:0] (Read/Write) -// 0x014 : Data signal of in_0 -// bit 31~0 - in_0[63:32] (Read/Write) -// 0x018 : reserved -// 0x01c : Data signal of out_0 -// bit 31~0 - out_0[31:0] (Read/Write) -// 0x020 : Data signal of out_0 -// bit 31~0 - out_0[63:32] (Read/Write) -// 0x024 : reserved -// 0x028 : Data signal of in_1 -// bit 31~0 - in_1[31:0] (Read/Write) -// 0x02c : Data signal of in_1 -// bit 31~0 - in_1[63:32] (Read/Write) -// 0x030 : reserved -// 0x034 : Data signal of out_1 -// bit 31~0 - out_1[31:0] (Read/Write) -// 0x038 : Data signal of out_1 -// bit 31~0 - out_1[63:32] (Read/Write) -// 0x03c : reserved -// 0x040 : Data signal of in_2 -// bit 31~0 - in_2[31:0] (Read/Write) -// 0x044 : Data signal of in_2 -// bit 31~0 - in_2[63:32] (Read/Write) -// 0x048 : reserved -// 0x04c : Data signal of out_2 -// bit 31~0 - out_2[31:0] (Read/Write) -// 0x050 : Data signal of out_2 -// bit 31~0 - out_2[63:32] (Read/Write) -// 0x054 : reserved -// 0x058 : Data signal of in_3 -// bit 31~0 - in_3[31:0] (Read/Write) -// 0x05c : Data signal of in_3 -// bit 31~0 - in_3[63:32] (Read/Write) -// 0x060 : reserved -// 0x064 : Data signal of out_3 -// bit 31~0 - out_3[31:0] (Read/Write) -// 0x068 : Data signal of out_3 -// bit 31~0 - out_3[63:32] (Read/Write) -// 0x06c : reserved -// 0x070 : Data signal of in_4 -// bit 31~0 - in_4[31:0] (Read/Write) -// 0x074 : Data signal of in_4 -// bit 31~0 - in_4[63:32] (Read/Write) -// 0x078 : reserved -// 0x07c : Data signal of out_4 -// bit 31~0 - out_4[31:0] (Read/Write) -// 0x080 : Data signal of out_4 -// bit 31~0 - out_4[63:32] (Read/Write) -// 0x084 : reserved -// 0x088 : Data signal of in_5 -// bit 31~0 - in_5[31:0] (Read/Write) -// 0x08c : Data signal of in_5 -// bit 31~0 - in_5[63:32] (Read/Write) -// 0x090 : reserved -// 0x094 : Data signal of out_5 -// bit 31~0 - out_5[31:0] (Read/Write) -// 0x098 : Data signal of out_5 -// bit 31~0 - out_5[63:32] (Read/Write) -// 0x09c : reserved -// 0x0a0 : Data signal of in_6 -// bit 31~0 - in_6[31:0] (Read/Write) -// 0x0a4 : Data signal of in_6 -// bit 31~0 - in_6[63:32] (Read/Write) -// 0x0a8 : reserved -// 0x0ac : Data signal of out_6 -// bit 31~0 - out_6[31:0] (Read/Write) -// 0x0b0 : Data signal of out_6 -// bit 31~0 - out_6[63:32] (Read/Write) -// 0x0b4 : reserved -// 0x0b8 : Data signal of in_7 -// bit 31~0 - in_7[31:0] (Read/Write) -// 0x0bc : Data signal of in_7 -// bit 31~0 - in_7[63:32] (Read/Write) -// 0x0c0 : reserved -// 0x0c4 : Data signal of out_7 -// bit 31~0 - out_7[31:0] (Read/Write) -// 0x0c8 : Data signal of out_7 -// bit 31~0 - out_7[63:32] (Read/Write) -// 0x0cc : reserved -// 0x0d0 : Data signal of in_8 -// bit 31~0 - in_8[31:0] (Read/Write) -// 0x0d4 : Data signal of in_8 -// bit 31~0 - in_8[63:32] (Read/Write) -// 0x0d8 : reserved -// 0x0dc : Data signal of out_8 -// bit 31~0 - out_8[31:0] (Read/Write) -// 0x0e0 : Data signal of out_8 -// bit 31~0 - out_8[63:32] (Read/Write) -// 0x0e4 : reserved -// 0x0e8 : Data signal of in_9 -// bit 31~0 - in_9[31:0] (Read/Write) -// 0x0ec : Data signal of in_9 -// bit 31~0 - in_9[63:32] (Read/Write) -// 0x0f0 : reserved -// 0x0f4 : Data signal of out_9 -// bit 31~0 - out_9[31:0] (Read/Write) -// 0x0f8 : Data signal of out_9 -// bit 31~0 - out_9[63:32] (Read/Write) -// 0x0fc : reserved -// 0x100 : Data signal of in_10 -// bit 31~0 - in_10[31:0] (Read/Write) -// 0x104 : Data signal of in_10 -// bit 31~0 - in_10[63:32] (Read/Write) -// 0x108 : reserved -// 0x10c : Data signal of out_10 -// bit 31~0 - out_10[31:0] (Read/Write) -// 0x110 : Data signal of out_10 -// bit 31~0 - out_10[63:32] (Read/Write) -// 0x114 : reserved -// 0x118 : Data signal of in_11 -// bit 31~0 - in_11[31:0] (Read/Write) -// 0x11c : Data signal of in_11 -// bit 31~0 - in_11[63:32] (Read/Write) -// 0x120 : reserved -// 0x124 : Data signal of out_11 -// bit 31~0 - out_11[31:0] (Read/Write) -// 0x128 : Data signal of out_11 -// bit 31~0 - out_11[63:32] (Read/Write) -// 0x12c : reserved -// 0x130 : Data signal of iters -// bit 31~0 - iters[31:0] (Read/Write) -// 0x134 : reserved -// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) - -//------------------------Parameter---------------------- -localparam - ADDR_AP_CTRL = 9'h000, - ADDR_GIE = 9'h004, - ADDR_IER = 9'h008, - ADDR_ISR = 9'h00c, - ADDR_IN_0_DATA_0 = 9'h010, - ADDR_IN_0_DATA_1 = 9'h014, - ADDR_IN_0_CTRL = 9'h018, - ADDR_OUT_0_DATA_0 = 9'h01c, - ADDR_OUT_0_DATA_1 = 9'h020, - ADDR_OUT_0_CTRL = 9'h024, - ADDR_IN_1_DATA_0 = 9'h028, - ADDR_IN_1_DATA_1 = 9'h02c, - ADDR_IN_1_CTRL = 9'h030, - ADDR_OUT_1_DATA_0 = 9'h034, - ADDR_OUT_1_DATA_1 = 9'h038, - ADDR_OUT_1_CTRL = 9'h03c, - ADDR_IN_2_DATA_0 = 9'h040, - ADDR_IN_2_DATA_1 = 9'h044, - ADDR_IN_2_CTRL = 9'h048, - ADDR_OUT_2_DATA_0 = 9'h04c, - ADDR_OUT_2_DATA_1 = 9'h050, - ADDR_OUT_2_CTRL = 9'h054, - ADDR_IN_3_DATA_0 = 9'h058, - ADDR_IN_3_DATA_1 = 9'h05c, - ADDR_IN_3_CTRL = 9'h060, - ADDR_OUT_3_DATA_0 = 9'h064, - ADDR_OUT_3_DATA_1 = 9'h068, - ADDR_OUT_3_CTRL = 9'h06c, - ADDR_IN_4_DATA_0 = 9'h070, - ADDR_IN_4_DATA_1 = 9'h074, - ADDR_IN_4_CTRL = 9'h078, - ADDR_OUT_4_DATA_0 = 9'h07c, - ADDR_OUT_4_DATA_1 = 9'h080, - ADDR_OUT_4_CTRL = 9'h084, - ADDR_IN_5_DATA_0 = 9'h088, - ADDR_IN_5_DATA_1 = 9'h08c, - ADDR_IN_5_CTRL = 9'h090, - ADDR_OUT_5_DATA_0 = 9'h094, - ADDR_OUT_5_DATA_1 = 9'h098, - ADDR_OUT_5_CTRL = 9'h09c, - ADDR_IN_6_DATA_0 = 9'h0a0, - ADDR_IN_6_DATA_1 = 9'h0a4, - ADDR_IN_6_CTRL = 9'h0a8, - ADDR_OUT_6_DATA_0 = 9'h0ac, - ADDR_OUT_6_DATA_1 = 9'h0b0, - ADDR_OUT_6_CTRL = 9'h0b4, - ADDR_IN_7_DATA_0 = 9'h0b8, - ADDR_IN_7_DATA_1 = 9'h0bc, - ADDR_IN_7_CTRL = 9'h0c0, - ADDR_OUT_7_DATA_0 = 9'h0c4, - ADDR_OUT_7_DATA_1 = 9'h0c8, - ADDR_OUT_7_CTRL = 9'h0cc, - ADDR_IN_8_DATA_0 = 9'h0d0, - ADDR_IN_8_DATA_1 = 9'h0d4, - ADDR_IN_8_CTRL = 9'h0d8, - ADDR_OUT_8_DATA_0 = 9'h0dc, - ADDR_OUT_8_DATA_1 = 9'h0e0, - ADDR_OUT_8_CTRL = 9'h0e4, - ADDR_IN_9_DATA_0 = 9'h0e8, - ADDR_IN_9_DATA_1 = 9'h0ec, - ADDR_IN_9_CTRL = 9'h0f0, - ADDR_OUT_9_DATA_0 = 9'h0f4, - ADDR_OUT_9_DATA_1 = 9'h0f8, - ADDR_OUT_9_CTRL = 9'h0fc, - ADDR_IN_10_DATA_0 = 9'h100, - ADDR_IN_10_DATA_1 = 9'h104, - ADDR_IN_10_CTRL = 9'h108, - ADDR_OUT_10_DATA_0 = 9'h10c, - ADDR_OUT_10_DATA_1 = 9'h110, - ADDR_OUT_10_CTRL = 9'h114, - ADDR_IN_11_DATA_0 = 9'h118, - ADDR_IN_11_DATA_1 = 9'h11c, - ADDR_IN_11_CTRL = 9'h120, - ADDR_OUT_11_DATA_0 = 9'h124, - ADDR_OUT_11_DATA_1 = 9'h128, - ADDR_OUT_11_CTRL = 9'h12c, - ADDR_ITERS_DATA_0 = 9'h130, - ADDR_ITERS_CTRL = 9'h134, - WRIDLE = 2'd0, - WRDATA = 2'd1, - WRRESP = 2'd2, - WRRESET = 2'd3, - RDIDLE = 2'd0, - RDDATA = 2'd1, - RDRESET = 2'd2, - ADDR_BITS = 9; - -//------------------------Local signal------------------- - reg [1:0] wstate = WRRESET; - reg [1:0] wnext; - reg [ADDR_BITS-1:0] waddr; - wire [C_S_AXI_DATA_WIDTH-1:0] wmask; - wire aw_hs; - wire w_hs; - reg [1:0] rstate = RDRESET; - reg [1:0] rnext; - reg [C_S_AXI_DATA_WIDTH-1:0] rdata; - wire ar_hs; - wire [ADDR_BITS-1:0] raddr; - // internal registers - reg int_ap_idle; - reg int_ap_ready = 1'b0; - wire task_ap_ready; - reg int_ap_done = 1'b0; - wire task_ap_done; - reg int_task_ap_done = 1'b0; - reg int_ap_start = 1'b0; - reg int_interrupt = 1'b0; - reg int_auto_restart = 1'b0; - reg auto_restart_status = 1'b0; - wire auto_restart_done; - reg int_gie = 1'b0; - reg int_ier = 1'b0; - reg int_isr = 1'b0; - reg [63:0] int_in_0 = 'b0; - reg [63:0] int_out_0 = 'b0; - reg [63:0] int_in_1 = 'b0; - reg [63:0] int_out_1 = 'b0; - reg [63:0] int_in_2 = 'b0; - reg [63:0] int_out_2 = 'b0; - reg [63:0] int_in_3 = 'b0; - reg [63:0] int_out_3 = 'b0; - reg [63:0] int_in_4 = 'b0; - reg [63:0] int_out_4 = 'b0; - reg [63:0] int_in_5 = 'b0; - reg [63:0] int_out_5 = 'b0; - reg [63:0] int_in_6 = 'b0; - reg [63:0] int_out_6 = 'b0; - reg [63:0] int_in_7 = 'b0; - reg [63:0] int_out_7 = 'b0; - reg [63:0] int_in_8 = 'b0; - reg [63:0] int_out_8 = 'b0; - reg [63:0] int_in_9 = 'b0; - reg [63:0] int_out_9 = 'b0; - reg [63:0] int_in_10 = 'b0; - reg [63:0] int_out_10 = 'b0; - reg [63:0] int_in_11 = 'b0; - reg [63:0] int_out_11 = 'b0; - reg [31:0] int_iters = 'b0; - -//------------------------Instantiation------------------ - - -//------------------------AXI write fsm------------------ -assign AWREADY = (wstate == WRIDLE); -assign WREADY = (wstate == WRDATA); -assign BRESP = 2'b00; // OKAY -assign BVALID = (wstate == WRRESP); -assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} }; -assign aw_hs = AWVALID & AWREADY; -assign w_hs = WVALID & WREADY; - -// wstate -always @(posedge ACLK) begin - if (ARESET) - wstate <= WRRESET; - else if (ACLK_EN) - wstate <= wnext; -end - -// wnext -always @(*) begin - case (wstate) - WRIDLE: - if (AWVALID) - wnext = WRDATA; - else - wnext = WRIDLE; - WRDATA: - if (WVALID) - wnext = WRRESP; - else - wnext = WRDATA; - WRRESP: - if (BREADY) - wnext = WRIDLE; - else - wnext = WRRESP; - default: - wnext = WRIDLE; - endcase -end - -// waddr -always @(posedge ACLK) begin - if (ACLK_EN) begin - if (aw_hs) - waddr <= AWADDR[ADDR_BITS-1:0]; - end -end - -//------------------------AXI read fsm------------------- -assign ARREADY = (rstate == RDIDLE); -assign RDATA = rdata; -assign RRESP = 2'b00; // OKAY -assign RVALID = (rstate == RDDATA); -assign ar_hs = ARVALID & ARREADY; -assign raddr = ARADDR[ADDR_BITS-1:0]; - -// rstate -always @(posedge ACLK) begin - if (ARESET) - rstate <= RDRESET; - else if (ACLK_EN) - rstate <= rnext; -end - -// rnext -always @(*) begin - case (rstate) - RDIDLE: - if (ARVALID) - rnext = RDDATA; - else - rnext = RDIDLE; - RDDATA: - if (RREADY & RVALID) - rnext = RDIDLE; - else - rnext = RDDATA; - default: - rnext = RDIDLE; - endcase -end - -// rdata -always @(posedge ACLK) begin - if (ACLK_EN) begin - if (ar_hs) begin - rdata <= 'b0; - case (raddr) - ADDR_AP_CTRL: begin - rdata[0] <= int_ap_start; - rdata[1] <= int_task_ap_done; - rdata[2] <= int_ap_idle; - rdata[3] <= int_ap_ready; - rdata[7] <= int_auto_restart; - rdata[9] <= int_interrupt; - end - ADDR_GIE: begin - rdata <= int_gie; - end - ADDR_IER: begin - rdata <= int_ier; - end - ADDR_ISR: begin - rdata <= int_isr; - end - ADDR_IN_0_DATA_0: begin - rdata <= int_in_0[31:0]; - end - ADDR_IN_0_DATA_1: begin - rdata <= int_in_0[63:32]; - end - ADDR_OUT_0_DATA_0: begin - rdata <= int_out_0[31:0]; - end - ADDR_OUT_0_DATA_1: begin - rdata <= int_out_0[63:32]; - end - ADDR_IN_1_DATA_0: begin - rdata <= int_in_1[31:0]; - end - ADDR_IN_1_DATA_1: begin - rdata <= int_in_1[63:32]; - end - ADDR_OUT_1_DATA_0: begin - rdata <= int_out_1[31:0]; - end - ADDR_OUT_1_DATA_1: begin - rdata <= int_out_1[63:32]; - end - ADDR_IN_2_DATA_0: begin - rdata <= int_in_2[31:0]; - end - ADDR_IN_2_DATA_1: begin - rdata <= int_in_2[63:32]; - end - ADDR_OUT_2_DATA_0: begin - rdata <= int_out_2[31:0]; - end - ADDR_OUT_2_DATA_1: begin - rdata <= int_out_2[63:32]; - end - ADDR_IN_3_DATA_0: begin - rdata <= int_in_3[31:0]; - end - ADDR_IN_3_DATA_1: begin - rdata <= int_in_3[63:32]; - end - ADDR_OUT_3_DATA_0: begin - rdata <= int_out_3[31:0]; - end - ADDR_OUT_3_DATA_1: begin - rdata <= int_out_3[63:32]; - end - ADDR_IN_4_DATA_0: begin - rdata <= int_in_4[31:0]; - end - ADDR_IN_4_DATA_1: begin - rdata <= int_in_4[63:32]; - end - ADDR_OUT_4_DATA_0: begin - rdata <= int_out_4[31:0]; - end - ADDR_OUT_4_DATA_1: begin - rdata <= int_out_4[63:32]; - end - ADDR_IN_5_DATA_0: begin - rdata <= int_in_5[31:0]; - end - ADDR_IN_5_DATA_1: begin - rdata <= int_in_5[63:32]; - end - ADDR_OUT_5_DATA_0: begin - rdata <= int_out_5[31:0]; - end - ADDR_OUT_5_DATA_1: begin - rdata <= int_out_5[63:32]; - end - ADDR_IN_6_DATA_0: begin - rdata <= int_in_6[31:0]; - end - ADDR_IN_6_DATA_1: begin - rdata <= int_in_6[63:32]; - end - ADDR_OUT_6_DATA_0: begin - rdata <= int_out_6[31:0]; - end - ADDR_OUT_6_DATA_1: begin - rdata <= int_out_6[63:32]; - end - ADDR_IN_7_DATA_0: begin - rdata <= int_in_7[31:0]; - end - ADDR_IN_7_DATA_1: begin - rdata <= int_in_7[63:32]; - end - ADDR_OUT_7_DATA_0: begin - rdata <= int_out_7[31:0]; - end - ADDR_OUT_7_DATA_1: begin - rdata <= int_out_7[63:32]; - end - ADDR_IN_8_DATA_0: begin - rdata <= int_in_8[31:0]; - end - ADDR_IN_8_DATA_1: begin - rdata <= int_in_8[63:32]; - end - ADDR_OUT_8_DATA_0: begin - rdata <= int_out_8[31:0]; - end - ADDR_OUT_8_DATA_1: begin - rdata <= int_out_8[63:32]; - end - ADDR_IN_9_DATA_0: begin - rdata <= int_in_9[31:0]; - end - ADDR_IN_9_DATA_1: begin - rdata <= int_in_9[63:32]; - end - ADDR_OUT_9_DATA_0: begin - rdata <= int_out_9[31:0]; - end - ADDR_OUT_9_DATA_1: begin - rdata <= int_out_9[63:32]; - end - ADDR_IN_10_DATA_0: begin - rdata <= int_in_10[31:0]; - end - ADDR_IN_10_DATA_1: begin - rdata <= int_in_10[63:32]; - end - ADDR_OUT_10_DATA_0: begin - rdata <= int_out_10[31:0]; - end - ADDR_OUT_10_DATA_1: begin - rdata <= int_out_10[63:32]; - end - ADDR_IN_11_DATA_0: begin - rdata <= int_in_11[31:0]; - end - ADDR_IN_11_DATA_1: begin - rdata <= int_in_11[63:32]; - end - ADDR_OUT_11_DATA_0: begin - rdata <= int_out_11[31:0]; - end - ADDR_OUT_11_DATA_1: begin - rdata <= int_out_11[63:32]; - end - ADDR_ITERS_DATA_0: begin - rdata <= int_iters[31:0]; - end - endcase - end - end -end - - -//------------------------Register logic----------------- -assign interrupt = int_interrupt; -assign ap_start = int_ap_start; -assign task_ap_done = (ap_done && !auto_restart_status) || auto_restart_done; -assign task_ap_ready = ap_ready && !int_auto_restart; -assign auto_restart_done = auto_restart_status && (ap_idle && !int_ap_idle); -assign in_0 = int_in_0; -assign out_0 = int_out_0; -assign in_1 = int_in_1; -assign out_1 = int_out_1; -assign in_2 = int_in_2; -assign out_2 = int_out_2; -assign in_3 = int_in_3; -assign out_3 = int_out_3; -assign in_4 = int_in_4; -assign out_4 = int_out_4; -assign in_5 = int_in_5; -assign out_5 = int_out_5; -assign in_6 = int_in_6; -assign out_6 = int_out_6; -assign in_7 = int_in_7; -assign out_7 = int_out_7; -assign in_8 = int_in_8; -assign out_8 = int_out_8; -assign in_9 = int_in_9; -assign out_9 = int_out_9; -assign in_10 = int_in_10; -assign out_10 = int_out_10; -assign in_11 = int_in_11; -assign out_11 = int_out_11; -assign iters = int_iters; -// int_interrupt -always @(posedge ACLK) begin - if (ARESET) - int_interrupt <= 1'b0; - else if (ACLK_EN) begin - if (int_gie && (|int_isr)) - int_interrupt <= 1'b1; - else - int_interrupt <= 1'b0; - end -end - -// int_ap_start -always @(posedge ACLK) begin - if (ARESET) - int_ap_start <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0]) - int_ap_start <= 1'b1; - else if (ap_done & int_auto_restart) - int_ap_start <= 1'b1; // auto restart - else - int_ap_start <= 1'b0; // self clear - end -end - -// int_ap_done -always @(posedge ACLK) begin - if (ARESET) - int_ap_done <= 1'b0; - else if (ACLK_EN) begin - int_ap_done <= ap_done; - end -end - -// int_task_ap_done -always @(posedge ACLK) begin - if (ARESET) - int_task_ap_done <= 1'b0; - else if (ACLK_EN) begin - if (task_ap_done) - int_task_ap_done <= 1'b1; - else if (ar_hs && raddr == ADDR_AP_CTRL) - int_task_ap_done <= 1'b0; // clear on read - end -end - -// int_ap_idle -always @(posedge ACLK) begin - if (ARESET) - int_ap_idle <= 1'b0; - else if (ACLK_EN) begin - int_ap_idle <= ap_idle; - end -end - -// int_ap_ready -always @(posedge ACLK) begin - if (ARESET) - int_ap_ready <= 1'b0; - else if (ACLK_EN) begin - if (task_ap_ready) - int_ap_ready <= 1'b1; - else if (ar_hs && raddr == ADDR_AP_CTRL) - int_ap_ready <= 1'b0; - end -end - -// int_auto_restart -always @(posedge ACLK) begin - if (ARESET) - int_auto_restart <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0]) - int_auto_restart <= WDATA[7]; - end -end - -// auto_restart_status -always @(posedge ACLK) begin - if (ARESET) - auto_restart_status <= 1'b0; - else if (ACLK_EN) begin - if (int_auto_restart) - auto_restart_status <= 1'b1; - else if (ap_idle) - auto_restart_status <= 1'b0; - end -end - -// int_gie -always @(posedge ACLK) begin - if (ARESET) - int_gie <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_GIE && WSTRB[0]) - int_gie <= WDATA[0]; - end -end - -// int_ier -always @(posedge ACLK) begin - if (ARESET) - int_ier <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IER && WSTRB[0]) - int_ier <= WDATA[0]; - end -end - -// int_isr -always @(posedge ACLK) begin - if (ARESET) - int_isr <= 1'b0; - else if (ACLK_EN) begin - if (int_ier & ap_done) - int_isr <= 1'b1; - else if (w_hs && waddr == ADDR_ISR && WSTRB[0]) - int_isr <= int_isr ^ WDATA[0]; // toggle on write - end -end - -// int_in_0[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_0[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_0_DATA_0) - int_in_0[31:0] <= (WDATA[31:0] & wmask) | (int_in_0[31:0] & ~wmask); - end -end - -// int_in_0[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_0[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_0_DATA_1) - int_in_0[63:32] <= (WDATA[31:0] & wmask) | (int_in_0[63:32] & ~wmask); - end -end - -// int_out_0[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_0[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_0_DATA_0) - int_out_0[31:0] <= (WDATA[31:0] & wmask) | (int_out_0[31:0] & ~wmask); - end -end - -// int_out_0[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_0[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_0_DATA_1) - int_out_0[63:32] <= (WDATA[31:0] & wmask) | (int_out_0[63:32] & ~wmask); - end -end - -// int_in_1[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_1[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_1_DATA_0) - int_in_1[31:0] <= (WDATA[31:0] & wmask) | (int_in_1[31:0] & ~wmask); - end -end - -// int_in_1[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_1[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_1_DATA_1) - int_in_1[63:32] <= (WDATA[31:0] & wmask) | (int_in_1[63:32] & ~wmask); - end -end - -// int_out_1[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_1[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_1_DATA_0) - int_out_1[31:0] <= (WDATA[31:0] & wmask) | (int_out_1[31:0] & ~wmask); - end -end - -// int_out_1[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_1[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_1_DATA_1) - int_out_1[63:32] <= (WDATA[31:0] & wmask) | (int_out_1[63:32] & ~wmask); - end -end - -// int_in_2[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_2[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_2_DATA_0) - int_in_2[31:0] <= (WDATA[31:0] & wmask) | (int_in_2[31:0] & ~wmask); - end -end - -// int_in_2[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_2[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_2_DATA_1) - int_in_2[63:32] <= (WDATA[31:0] & wmask) | (int_in_2[63:32] & ~wmask); - end -end - -// int_out_2[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_2[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_2_DATA_0) - int_out_2[31:0] <= (WDATA[31:0] & wmask) | (int_out_2[31:0] & ~wmask); - end -end - -// int_out_2[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_2[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_2_DATA_1) - int_out_2[63:32] <= (WDATA[31:0] & wmask) | (int_out_2[63:32] & ~wmask); - end -end - -// int_in_3[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_3[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_3_DATA_0) - int_in_3[31:0] <= (WDATA[31:0] & wmask) | (int_in_3[31:0] & ~wmask); - end -end - -// int_in_3[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_3[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_3_DATA_1) - int_in_3[63:32] <= (WDATA[31:0] & wmask) | (int_in_3[63:32] & ~wmask); - end -end - -// int_out_3[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_3[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_3_DATA_0) - int_out_3[31:0] <= (WDATA[31:0] & wmask) | (int_out_3[31:0] & ~wmask); - end -end - -// int_out_3[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_3[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_3_DATA_1) - int_out_3[63:32] <= (WDATA[31:0] & wmask) | (int_out_3[63:32] & ~wmask); - end -end - -// int_in_4[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_4[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_4_DATA_0) - int_in_4[31:0] <= (WDATA[31:0] & wmask) | (int_in_4[31:0] & ~wmask); - end -end - -// int_in_4[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_4[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_4_DATA_1) - int_in_4[63:32] <= (WDATA[31:0] & wmask) | (int_in_4[63:32] & ~wmask); - end -end - -// int_out_4[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_4[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_4_DATA_0) - int_out_4[31:0] <= (WDATA[31:0] & wmask) | (int_out_4[31:0] & ~wmask); - end -end - -// int_out_4[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_4[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_4_DATA_1) - int_out_4[63:32] <= (WDATA[31:0] & wmask) | (int_out_4[63:32] & ~wmask); - end -end - -// int_in_5[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_5[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_5_DATA_0) - int_in_5[31:0] <= (WDATA[31:0] & wmask) | (int_in_5[31:0] & ~wmask); - end -end - -// int_in_5[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_5[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_5_DATA_1) - int_in_5[63:32] <= (WDATA[31:0] & wmask) | (int_in_5[63:32] & ~wmask); - end -end - -// int_out_5[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_5[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_5_DATA_0) - int_out_5[31:0] <= (WDATA[31:0] & wmask) | (int_out_5[31:0] & ~wmask); - end -end - -// int_out_5[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_5[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_5_DATA_1) - int_out_5[63:32] <= (WDATA[31:0] & wmask) | (int_out_5[63:32] & ~wmask); - end -end - -// int_in_6[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_6[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_6_DATA_0) - int_in_6[31:0] <= (WDATA[31:0] & wmask) | (int_in_6[31:0] & ~wmask); - end -end - -// int_in_6[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_6[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_6_DATA_1) - int_in_6[63:32] <= (WDATA[31:0] & wmask) | (int_in_6[63:32] & ~wmask); - end -end - -// int_out_6[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_6[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_6_DATA_0) - int_out_6[31:0] <= (WDATA[31:0] & wmask) | (int_out_6[31:0] & ~wmask); - end -end - -// int_out_6[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_6[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_6_DATA_1) - int_out_6[63:32] <= (WDATA[31:0] & wmask) | (int_out_6[63:32] & ~wmask); - end -end - -// int_in_7[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_7[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_7_DATA_0) - int_in_7[31:0] <= (WDATA[31:0] & wmask) | (int_in_7[31:0] & ~wmask); - end -end - -// int_in_7[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_7[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_7_DATA_1) - int_in_7[63:32] <= (WDATA[31:0] & wmask) | (int_in_7[63:32] & ~wmask); - end -end - -// int_out_7[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_7[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_7_DATA_0) - int_out_7[31:0] <= (WDATA[31:0] & wmask) | (int_out_7[31:0] & ~wmask); - end -end - -// int_out_7[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_7[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_7_DATA_1) - int_out_7[63:32] <= (WDATA[31:0] & wmask) | (int_out_7[63:32] & ~wmask); - end -end - -// int_in_8[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_8[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_8_DATA_0) - int_in_8[31:0] <= (WDATA[31:0] & wmask) | (int_in_8[31:0] & ~wmask); - end -end - -// int_in_8[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_8[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_8_DATA_1) - int_in_8[63:32] <= (WDATA[31:0] & wmask) | (int_in_8[63:32] & ~wmask); - end -end - -// int_out_8[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_8[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_8_DATA_0) - int_out_8[31:0] <= (WDATA[31:0] & wmask) | (int_out_8[31:0] & ~wmask); - end -end - -// int_out_8[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_8[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_8_DATA_1) - int_out_8[63:32] <= (WDATA[31:0] & wmask) | (int_out_8[63:32] & ~wmask); - end -end - -// int_in_9[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_9[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_9_DATA_0) - int_in_9[31:0] <= (WDATA[31:0] & wmask) | (int_in_9[31:0] & ~wmask); - end -end - -// int_in_9[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_9[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_9_DATA_1) - int_in_9[63:32] <= (WDATA[31:0] & wmask) | (int_in_9[63:32] & ~wmask); - end -end - -// int_out_9[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_9[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_9_DATA_0) - int_out_9[31:0] <= (WDATA[31:0] & wmask) | (int_out_9[31:0] & ~wmask); - end -end - -// int_out_9[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_9[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_9_DATA_1) - int_out_9[63:32] <= (WDATA[31:0] & wmask) | (int_out_9[63:32] & ~wmask); - end -end - -// int_in_10[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_10[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_10_DATA_0) - int_in_10[31:0] <= (WDATA[31:0] & wmask) | (int_in_10[31:0] & ~wmask); - end -end - -// int_in_10[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_10[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_10_DATA_1) - int_in_10[63:32] <= (WDATA[31:0] & wmask) | (int_in_10[63:32] & ~wmask); - end -end - -// int_out_10[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_10[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_10_DATA_0) - int_out_10[31:0] <= (WDATA[31:0] & wmask) | (int_out_10[31:0] & ~wmask); - end -end - -// int_out_10[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_10[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_10_DATA_1) - int_out_10[63:32] <= (WDATA[31:0] & wmask) | (int_out_10[63:32] & ~wmask); - end -end - -// int_in_11[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_in_11[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_11_DATA_0) - int_in_11[31:0] <= (WDATA[31:0] & wmask) | (int_in_11[31:0] & ~wmask); - end -end - -// int_in_11[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_in_11[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IN_11_DATA_1) - int_in_11[63:32] <= (WDATA[31:0] & wmask) | (int_in_11[63:32] & ~wmask); - end -end - -// int_out_11[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_out_11[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_11_DATA_0) - int_out_11[31:0] <= (WDATA[31:0] & wmask) | (int_out_11[31:0] & ~wmask); - end -end - -// int_out_11[63:32] -always @(posedge ACLK) begin - if (ARESET) - int_out_11[63:32] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_OUT_11_DATA_1) - int_out_11[63:32] <= (WDATA[31:0] & wmask) | (int_out_11[63:32] & ~wmask); - end -end - -// int_iters[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_iters[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_ITERS_DATA_0) - int_iters[31:0] <= (WDATA[31:0] & wmask) | (int_iters[31:0] & ~wmask); - end -end - -//synthesis translate_off -always @(posedge ACLK) begin - if (ACLK_EN) begin - if (int_gie & ~int_isr & int_ier & ap_done) - $display ("// Interrupt Monitor : interrupt for ap_done detected @ \"%0t\"", $time); - end -end -//synthesis translate_on - -//------------------------Memory logic------------------- - -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/unikernel_fsm.v b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/unikernel_fsm.v deleted file mode 100644 index ed2e35ef..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/hdl/unikernel_fsm.v +++ /dev/null @@ -1,1308 +0,0 @@ - - -module unikernel_fsm -( - ap_clk, - ap_rst_n, - ap_start, - ap_ready, - ap_done, - ap_idle, - HEAT3D_0__ap_start, - HEAT3D_0__ap_ready, - HEAT3D_0__ap_done, - HEAT3D_0__ap_idle, - HEAT3D_1__ap_start, - HEAT3D_1__ap_ready, - HEAT3D_1__ap_done, - HEAT3D_1__ap_idle, - HEAT3D_2__ap_start, - HEAT3D_2__ap_ready, - HEAT3D_2__ap_done, - HEAT3D_2__ap_idle, - HEAT3D_3__ap_start, - HEAT3D_3__ap_ready, - HEAT3D_3__ap_done, - HEAT3D_3__ap_idle, - HEAT3D_4__ap_start, - HEAT3D_4__ap_ready, - HEAT3D_4__ap_done, - HEAT3D_4__ap_idle, - HEAT3D_5__ap_start, - HEAT3D_5__ap_ready, - HEAT3D_5__ap_done, - HEAT3D_5__ap_idle, - HEAT3D_6__ap_start, - HEAT3D_6__ap_ready, - HEAT3D_6__ap_done, - HEAT3D_6__ap_idle, - HEAT3D_7__ap_start, - HEAT3D_7__ap_ready, - HEAT3D_7__ap_done, - HEAT3D_7__ap_idle, - HEAT3D_8__ap_start, - HEAT3D_8__ap_ready, - HEAT3D_8__ap_done, - HEAT3D_8__ap_idle, - HEAT3D_9__ap_start, - HEAT3D_9__ap_ready, - HEAT3D_9__ap_done, - HEAT3D_9__ap_idle, - HEAT3D_10__ap_start, - HEAT3D_10__ap_ready, - HEAT3D_10__ap_done, - HEAT3D_10__ap_idle, - HEAT3D_11__ap_start, - HEAT3D_11__ap_ready, - HEAT3D_11__ap_done, - HEAT3D_11__ap_idle, - inter_kernel_0__ap_start, - inter_kernel_0__ap_ready, - inter_kernel_0__ap_done, - inter_kernel_0__ap_idle, - inter_kernel_1__ap_start, - inter_kernel_1__ap_ready, - inter_kernel_1__ap_done, - inter_kernel_1__ap_idle, - inter_kernel_2__ap_start, - inter_kernel_2__ap_ready, - inter_kernel_2__ap_done, - inter_kernel_2__ap_idle, - inter_kernel_3__ap_start, - inter_kernel_3__ap_ready, - inter_kernel_3__ap_done, - inter_kernel_3__ap_idle, - inter_kernel_4__ap_start, - inter_kernel_4__ap_ready, - inter_kernel_4__ap_done, - inter_kernel_4__ap_idle, - inter_kernel_5__ap_start, - inter_kernel_5__ap_ready, - inter_kernel_5__ap_done, - inter_kernel_5__ap_idle, - inter_kernel_6__ap_start, - inter_kernel_6__ap_ready, - inter_kernel_6__ap_done, - inter_kernel_6__ap_idle, - inter_kernel_7__ap_start, - inter_kernel_7__ap_ready, - inter_kernel_7__ap_done, - inter_kernel_7__ap_idle, - inter_kernel_8__ap_start, - inter_kernel_8__ap_ready, - inter_kernel_8__ap_done, - inter_kernel_8__ap_idle, - inter_kernel_9__ap_start, - inter_kernel_9__ap_ready, - inter_kernel_9__ap_done, - inter_kernel_9__ap_idle, - inter_kernel_10__ap_start, - inter_kernel_10__ap_ready, - inter_kernel_10__ap_done, - inter_kernel_10__ap_idle, - inter_kernel_11__ap_start, - inter_kernel_11__ap_ready, - inter_kernel_11__ap_done, - inter_kernel_11__ap_idle -); - - (* RS_CLK *)input ap_clk; - (* RS_RST = "ff" *)input ap_rst_n; - (* RS_AP_CTRL = "unikernel.ap_start" *)input ap_start; - (* RS_AP_CTRL = "unikernel.ap_ready" *)output ap_ready; - (* RS_FF = "unikernel__ap_done" *)output ap_done; - (* RS_FF = "unikernel__ap_idle" *)output ap_idle; - (* RS_AP_CTRL = "HEAT3D_0.ap_start" *)output HEAT3D_0__ap_start; - (* RS_AP_CTRL = "HEAT3D_0.ap_ready" *)input HEAT3D_0__ap_ready; - (* RS_FF = "HEAT3D_0__ap_done" *)input HEAT3D_0__ap_done; - (* RS_FF = "HEAT3D_0__ap_idle" *)input HEAT3D_0__ap_idle; - (* RS_AP_CTRL = "HEAT3D_1.ap_start" *)output HEAT3D_1__ap_start; - (* RS_AP_CTRL = "HEAT3D_1.ap_ready" *)input HEAT3D_1__ap_ready; - (* RS_FF = "HEAT3D_1__ap_done" *)input HEAT3D_1__ap_done; - (* RS_FF = "HEAT3D_1__ap_idle" *)input HEAT3D_1__ap_idle; - (* RS_AP_CTRL = "HEAT3D_2.ap_start" *)output HEAT3D_2__ap_start; - (* RS_AP_CTRL = "HEAT3D_2.ap_ready" *)input HEAT3D_2__ap_ready; - (* RS_FF = "HEAT3D_2__ap_done" *)input HEAT3D_2__ap_done; - (* RS_FF = "HEAT3D_2__ap_idle" *)input HEAT3D_2__ap_idle; - (* RS_AP_CTRL = "HEAT3D_3.ap_start" *)output HEAT3D_3__ap_start; - (* RS_AP_CTRL = "HEAT3D_3.ap_ready" *)input HEAT3D_3__ap_ready; - (* RS_FF = "HEAT3D_3__ap_done" *)input HEAT3D_3__ap_done; - (* RS_FF = "HEAT3D_3__ap_idle" *)input HEAT3D_3__ap_idle; - (* RS_AP_CTRL = "HEAT3D_4.ap_start" *)output HEAT3D_4__ap_start; - (* RS_AP_CTRL = "HEAT3D_4.ap_ready" *)input HEAT3D_4__ap_ready; - (* RS_FF = "HEAT3D_4__ap_done" *)input HEAT3D_4__ap_done; - (* RS_FF = "HEAT3D_4__ap_idle" *)input HEAT3D_4__ap_idle; - (* RS_AP_CTRL = "HEAT3D_5.ap_start" *)output HEAT3D_5__ap_start; - (* RS_AP_CTRL = "HEAT3D_5.ap_ready" *)input HEAT3D_5__ap_ready; - (* RS_FF = "HEAT3D_5__ap_done" *)input HEAT3D_5__ap_done; - (* RS_FF = "HEAT3D_5__ap_idle" *)input HEAT3D_5__ap_idle; - (* RS_AP_CTRL = "HEAT3D_6.ap_start" *)output HEAT3D_6__ap_start; - (* RS_AP_CTRL = "HEAT3D_6.ap_ready" *)input HEAT3D_6__ap_ready; - (* RS_FF = "HEAT3D_6__ap_done" *)input HEAT3D_6__ap_done; - (* RS_FF = "HEAT3D_6__ap_idle" *)input HEAT3D_6__ap_idle; - (* RS_AP_CTRL = "HEAT3D_7.ap_start" *)output HEAT3D_7__ap_start; - (* RS_AP_CTRL = "HEAT3D_7.ap_ready" *)input HEAT3D_7__ap_ready; - (* RS_FF = "HEAT3D_7__ap_done" *)input HEAT3D_7__ap_done; - (* RS_FF = "HEAT3D_7__ap_idle" *)input HEAT3D_7__ap_idle; - (* RS_AP_CTRL = "HEAT3D_8.ap_start" *)output HEAT3D_8__ap_start; - (* RS_AP_CTRL = "HEAT3D_8.ap_ready" *)input HEAT3D_8__ap_ready; - (* RS_FF = "HEAT3D_8__ap_done" *)input HEAT3D_8__ap_done; - (* RS_FF = "HEAT3D_8__ap_idle" *)input HEAT3D_8__ap_idle; - (* RS_AP_CTRL = "HEAT3D_9.ap_start" *)output HEAT3D_9__ap_start; - (* RS_AP_CTRL = "HEAT3D_9.ap_ready" *)input HEAT3D_9__ap_ready; - (* RS_FF = "HEAT3D_9__ap_done" *)input HEAT3D_9__ap_done; - (* RS_FF = "HEAT3D_9__ap_idle" *)input HEAT3D_9__ap_idle; - (* RS_AP_CTRL = "HEAT3D_10.ap_start" *)output HEAT3D_10__ap_start; - (* RS_AP_CTRL = "HEAT3D_10.ap_ready" *)input HEAT3D_10__ap_ready; - (* RS_FF = "HEAT3D_10__ap_done" *)input HEAT3D_10__ap_done; - (* RS_FF = "HEAT3D_10__ap_idle" *)input HEAT3D_10__ap_idle; - (* RS_AP_CTRL = "HEAT3D_11.ap_start" *)output HEAT3D_11__ap_start; - (* RS_AP_CTRL = "HEAT3D_11.ap_ready" *)input HEAT3D_11__ap_ready; - (* RS_FF = "HEAT3D_11__ap_done" *)input HEAT3D_11__ap_done; - (* RS_FF = "HEAT3D_11__ap_idle" *)input HEAT3D_11__ap_idle; - (* RS_AP_CTRL = "inter_kernel_0.ap_start" *)output inter_kernel_0__ap_start; - (* RS_AP_CTRL = "inter_kernel_0.ap_ready" *)input inter_kernel_0__ap_ready; - (* RS_FF = "inter_kernel_0__ap_done" *)input inter_kernel_0__ap_done; - (* RS_FF = "inter_kernel_0__ap_idle" *)input inter_kernel_0__ap_idle; - (* RS_AP_CTRL = "inter_kernel_1.ap_start" *)output inter_kernel_1__ap_start; - (* RS_AP_CTRL = "inter_kernel_1.ap_ready" *)input inter_kernel_1__ap_ready; - (* RS_FF = "inter_kernel_1__ap_done" *)input inter_kernel_1__ap_done; - (* RS_FF = "inter_kernel_1__ap_idle" *)input inter_kernel_1__ap_idle; - (* RS_AP_CTRL = "inter_kernel_2.ap_start" *)output inter_kernel_2__ap_start; - (* RS_AP_CTRL = "inter_kernel_2.ap_ready" *)input inter_kernel_2__ap_ready; - (* RS_FF = "inter_kernel_2__ap_done" *)input inter_kernel_2__ap_done; - (* RS_FF = "inter_kernel_2__ap_idle" *)input inter_kernel_2__ap_idle; - (* RS_AP_CTRL = "inter_kernel_3.ap_start" *)output inter_kernel_3__ap_start; - (* RS_AP_CTRL = "inter_kernel_3.ap_ready" *)input inter_kernel_3__ap_ready; - (* RS_FF = "inter_kernel_3__ap_done" *)input inter_kernel_3__ap_done; - (* RS_FF = "inter_kernel_3__ap_idle" *)input inter_kernel_3__ap_idle; - (* RS_AP_CTRL = "inter_kernel_4.ap_start" *)output inter_kernel_4__ap_start; - (* RS_AP_CTRL = "inter_kernel_4.ap_ready" *)input inter_kernel_4__ap_ready; - (* RS_FF = "inter_kernel_4__ap_done" *)input inter_kernel_4__ap_done; - (* RS_FF = "inter_kernel_4__ap_idle" *)input inter_kernel_4__ap_idle; - (* RS_AP_CTRL = "inter_kernel_5.ap_start" *)output inter_kernel_5__ap_start; - (* RS_AP_CTRL = "inter_kernel_5.ap_ready" *)input inter_kernel_5__ap_ready; - (* RS_FF = "inter_kernel_5__ap_done" *)input inter_kernel_5__ap_done; - (* RS_FF = "inter_kernel_5__ap_idle" *)input inter_kernel_5__ap_idle; - (* RS_AP_CTRL = "inter_kernel_6.ap_start" *)output inter_kernel_6__ap_start; - (* RS_AP_CTRL = "inter_kernel_6.ap_ready" *)input inter_kernel_6__ap_ready; - (* RS_FF = "inter_kernel_6__ap_done" *)input inter_kernel_6__ap_done; - (* RS_FF = "inter_kernel_6__ap_idle" *)input inter_kernel_6__ap_idle; - (* RS_AP_CTRL = "inter_kernel_7.ap_start" *)output inter_kernel_7__ap_start; - (* RS_AP_CTRL = "inter_kernel_7.ap_ready" *)input inter_kernel_7__ap_ready; - (* RS_FF = "inter_kernel_7__ap_done" *)input inter_kernel_7__ap_done; - (* RS_FF = "inter_kernel_7__ap_idle" *)input inter_kernel_7__ap_idle; - (* RS_AP_CTRL = "inter_kernel_8.ap_start" *)output inter_kernel_8__ap_start; - (* RS_AP_CTRL = "inter_kernel_8.ap_ready" *)input inter_kernel_8__ap_ready; - (* RS_FF = "inter_kernel_8__ap_done" *)input inter_kernel_8__ap_done; - (* RS_FF = "inter_kernel_8__ap_idle" *)input inter_kernel_8__ap_idle; - (* RS_AP_CTRL = "inter_kernel_9.ap_start" *)output inter_kernel_9__ap_start; - (* RS_AP_CTRL = "inter_kernel_9.ap_ready" *)input inter_kernel_9__ap_ready; - (* RS_FF = "inter_kernel_9__ap_done" *)input inter_kernel_9__ap_done; - (* RS_FF = "inter_kernel_9__ap_idle" *)input inter_kernel_9__ap_idle; - (* RS_AP_CTRL = "inter_kernel_10.ap_start" *)output inter_kernel_10__ap_start; - (* RS_AP_CTRL = "inter_kernel_10.ap_ready" *)input inter_kernel_10__ap_ready; - (* RS_FF = "inter_kernel_10__ap_done" *)input inter_kernel_10__ap_done; - (* RS_FF = "inter_kernel_10__ap_idle" *)input inter_kernel_10__ap_idle; - (* RS_AP_CTRL = "inter_kernel_11.ap_start" *)output inter_kernel_11__ap_start; - (* RS_AP_CTRL = "inter_kernel_11.ap_ready" *)input inter_kernel_11__ap_ready; - (* RS_FF = "inter_kernel_11__ap_done" *)input inter_kernel_11__ap_done; - (* RS_FF = "inter_kernel_11__ap_idle" *)input inter_kernel_11__ap_idle; - wire HEAT3D_0__ap_start_global__q0; - wire HEAT3D_0__is_done__q0; - wire HEAT3D_0__ap_done_global__q0; - wire HEAT3D_0__ap_start; - wire HEAT3D_0__ap_ready; - wire HEAT3D_0__ap_done; - wire HEAT3D_0__ap_idle; - reg [1:0] HEAT3D_0__state; - wire HEAT3D_1__ap_start_global__q0; - wire HEAT3D_1__is_done__q0; - wire HEAT3D_1__ap_done_global__q0; - wire HEAT3D_1__ap_start; - wire HEAT3D_1__ap_ready; - wire HEAT3D_1__ap_done; - wire HEAT3D_1__ap_idle; - reg [1:0] HEAT3D_1__state; - wire HEAT3D_2__ap_start_global__q0; - wire HEAT3D_2__is_done__q0; - wire HEAT3D_2__ap_done_global__q0; - wire HEAT3D_2__ap_start; - wire HEAT3D_2__ap_ready; - wire HEAT3D_2__ap_done; - wire HEAT3D_2__ap_idle; - reg [1:0] HEAT3D_2__state; - wire HEAT3D_3__ap_start_global__q0; - wire HEAT3D_3__is_done__q0; - wire HEAT3D_3__ap_done_global__q0; - wire HEAT3D_3__ap_start; - wire HEAT3D_3__ap_ready; - wire HEAT3D_3__ap_done; - wire HEAT3D_3__ap_idle; - reg [1:0] HEAT3D_3__state; - wire HEAT3D_4__ap_start_global__q0; - wire HEAT3D_4__is_done__q0; - wire HEAT3D_4__ap_done_global__q0; - wire HEAT3D_4__ap_start; - wire HEAT3D_4__ap_ready; - wire HEAT3D_4__ap_done; - wire HEAT3D_4__ap_idle; - reg [1:0] HEAT3D_4__state; - wire HEAT3D_5__ap_start_global__q0; - wire HEAT3D_5__is_done__q0; - wire HEAT3D_5__ap_done_global__q0; - wire HEAT3D_5__ap_start; - wire HEAT3D_5__ap_ready; - wire HEAT3D_5__ap_done; - wire HEAT3D_5__ap_idle; - reg [1:0] HEAT3D_5__state; - wire HEAT3D_6__ap_start_global__q0; - wire HEAT3D_6__is_done__q0; - wire HEAT3D_6__ap_done_global__q0; - wire HEAT3D_6__ap_start; - wire HEAT3D_6__ap_ready; - wire HEAT3D_6__ap_done; - wire HEAT3D_6__ap_idle; - reg [1:0] HEAT3D_6__state; - wire HEAT3D_7__ap_start_global__q0; - wire HEAT3D_7__is_done__q0; - wire HEAT3D_7__ap_done_global__q0; - wire HEAT3D_7__ap_start; - wire HEAT3D_7__ap_ready; - wire HEAT3D_7__ap_done; - wire HEAT3D_7__ap_idle; - reg [1:0] HEAT3D_7__state; - wire HEAT3D_8__ap_start_global__q0; - wire HEAT3D_8__is_done__q0; - wire HEAT3D_8__ap_done_global__q0; - wire HEAT3D_8__ap_start; - wire HEAT3D_8__ap_ready; - wire HEAT3D_8__ap_done; - wire HEAT3D_8__ap_idle; - reg [1:0] HEAT3D_8__state; - wire HEAT3D_9__ap_start_global__q0; - wire HEAT3D_9__is_done__q0; - wire HEAT3D_9__ap_done_global__q0; - wire HEAT3D_9__ap_start; - wire HEAT3D_9__ap_ready; - wire HEAT3D_9__ap_done; - wire HEAT3D_9__ap_idle; - reg [1:0] HEAT3D_9__state; - wire HEAT3D_10__ap_start_global__q0; - wire HEAT3D_10__is_done__q0; - wire HEAT3D_10__ap_done_global__q0; - wire HEAT3D_10__ap_start; - wire HEAT3D_10__ap_ready; - wire HEAT3D_10__ap_done; - wire HEAT3D_10__ap_idle; - reg [1:0] HEAT3D_10__state; - wire HEAT3D_11__ap_start_global__q0; - wire HEAT3D_11__is_done__q0; - wire HEAT3D_11__ap_done_global__q0; - wire HEAT3D_11__ap_start; - wire HEAT3D_11__ap_ready; - wire HEAT3D_11__ap_done; - wire HEAT3D_11__ap_idle; - reg [1:0] HEAT3D_11__state; - wire inter_kernel_0__ap_start_global__q0; - wire inter_kernel_0__is_done__q0; - wire inter_kernel_0__ap_done_global__q0; - wire inter_kernel_0__ap_start; - wire inter_kernel_0__ap_ready; - wire inter_kernel_0__ap_done; - wire inter_kernel_0__ap_idle; - reg [1:0] inter_kernel_0__state; - wire inter_kernel_1__ap_start_global__q0; - wire inter_kernel_1__is_done__q0; - wire inter_kernel_1__ap_done_global__q0; - wire inter_kernel_1__ap_start; - wire inter_kernel_1__ap_ready; - wire inter_kernel_1__ap_done; - wire inter_kernel_1__ap_idle; - reg [1:0] inter_kernel_1__state; - wire inter_kernel_2__ap_start_global__q0; - wire inter_kernel_2__is_done__q0; - wire inter_kernel_2__ap_done_global__q0; - wire inter_kernel_2__ap_start; - wire inter_kernel_2__ap_ready; - wire inter_kernel_2__ap_done; - wire inter_kernel_2__ap_idle; - reg [1:0] inter_kernel_2__state; - wire inter_kernel_3__ap_start_global__q0; - wire inter_kernel_3__is_done__q0; - wire inter_kernel_3__ap_done_global__q0; - wire inter_kernel_3__ap_start; - wire inter_kernel_3__ap_ready; - wire inter_kernel_3__ap_done; - wire inter_kernel_3__ap_idle; - reg [1:0] inter_kernel_3__state; - wire inter_kernel_4__ap_start_global__q0; - wire inter_kernel_4__is_done__q0; - wire inter_kernel_4__ap_done_global__q0; - wire inter_kernel_4__ap_start; - wire inter_kernel_4__ap_ready; - wire inter_kernel_4__ap_done; - wire inter_kernel_4__ap_idle; - reg [1:0] inter_kernel_4__state; - wire inter_kernel_5__ap_start_global__q0; - wire inter_kernel_5__is_done__q0; - wire inter_kernel_5__ap_done_global__q0; - wire inter_kernel_5__ap_start; - wire inter_kernel_5__ap_ready; - wire inter_kernel_5__ap_done; - wire inter_kernel_5__ap_idle; - reg [1:0] inter_kernel_5__state; - wire inter_kernel_6__ap_start_global__q0; - wire inter_kernel_6__is_done__q0; - wire inter_kernel_6__ap_done_global__q0; - wire inter_kernel_6__ap_start; - wire inter_kernel_6__ap_ready; - wire inter_kernel_6__ap_done; - wire inter_kernel_6__ap_idle; - reg [1:0] inter_kernel_6__state; - wire inter_kernel_7__ap_start_global__q0; - wire inter_kernel_7__is_done__q0; - wire inter_kernel_7__ap_done_global__q0; - wire inter_kernel_7__ap_start; - wire inter_kernel_7__ap_ready; - wire inter_kernel_7__ap_done; - wire inter_kernel_7__ap_idle; - reg [1:0] inter_kernel_7__state; - wire inter_kernel_8__ap_start_global__q0; - wire inter_kernel_8__is_done__q0; - wire inter_kernel_8__ap_done_global__q0; - wire inter_kernel_8__ap_start; - wire inter_kernel_8__ap_ready; - wire inter_kernel_8__ap_done; - wire inter_kernel_8__ap_idle; - reg [1:0] inter_kernel_8__state; - wire inter_kernel_9__ap_start_global__q0; - wire inter_kernel_9__is_done__q0; - wire inter_kernel_9__ap_done_global__q0; - wire inter_kernel_9__ap_start; - wire inter_kernel_9__ap_ready; - wire inter_kernel_9__ap_done; - wire inter_kernel_9__ap_idle; - reg [1:0] inter_kernel_9__state; - wire inter_kernel_10__ap_start_global__q0; - wire inter_kernel_10__is_done__q0; - wire inter_kernel_10__ap_done_global__q0; - wire inter_kernel_10__ap_start; - wire inter_kernel_10__ap_ready; - wire inter_kernel_10__ap_done; - wire inter_kernel_10__ap_idle; - reg [1:0] inter_kernel_10__state; - wire inter_kernel_11__ap_start_global__q0; - wire inter_kernel_11__is_done__q0; - wire inter_kernel_11__ap_done_global__q0; - wire inter_kernel_11__ap_start; - wire inter_kernel_11__ap_ready; - wire inter_kernel_11__ap_done; - wire inter_kernel_11__ap_idle; - reg [1:0] inter_kernel_11__state; - reg [1:0] tapa_state; - reg [0:0] countdown; - wire ap_start__q0; - wire ap_done__q0; - assign HEAT3D_0__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_0__is_done__q0 = (HEAT3D_0__state == 2'b10); - assign HEAT3D_0__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_0__state <= 2'b00; - end else begin - if(HEAT3D_0__state == 2'b00) begin - if(HEAT3D_0__ap_start_global__q0) begin - HEAT3D_0__state <= 2'b01; - end - end - if(HEAT3D_0__state == 2'b01) begin - if(HEAT3D_0__ap_ready) begin - if(HEAT3D_0__ap_done) begin - HEAT3D_0__state <= 2'b10; - end else begin - HEAT3D_0__state <= 2'b11; - end - end - end - if(HEAT3D_0__state == 2'b11) begin - if(HEAT3D_0__ap_done) begin - HEAT3D_0__state <= 2'b10; - end - end - if(HEAT3D_0__state == 2'b10) begin - if(HEAT3D_0__ap_done_global__q0) begin - HEAT3D_0__state <= 2'b00; - end - end - end - end - - assign HEAT3D_0__ap_start = (HEAT3D_0__state == 2'b01); - assign HEAT3D_1__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_1__is_done__q0 = (HEAT3D_1__state == 2'b10); - assign HEAT3D_1__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_1__state <= 2'b00; - end else begin - if(HEAT3D_1__state == 2'b00) begin - if(HEAT3D_1__ap_start_global__q0) begin - HEAT3D_1__state <= 2'b01; - end - end - if(HEAT3D_1__state == 2'b01) begin - if(HEAT3D_1__ap_ready) begin - if(HEAT3D_1__ap_done) begin - HEAT3D_1__state <= 2'b10; - end else begin - HEAT3D_1__state <= 2'b11; - end - end - end - if(HEAT3D_1__state == 2'b11) begin - if(HEAT3D_1__ap_done) begin - HEAT3D_1__state <= 2'b10; - end - end - if(HEAT3D_1__state == 2'b10) begin - if(HEAT3D_1__ap_done_global__q0) begin - HEAT3D_1__state <= 2'b00; - end - end - end - end - - assign HEAT3D_1__ap_start = (HEAT3D_1__state == 2'b01); - assign HEAT3D_2__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_2__is_done__q0 = (HEAT3D_2__state == 2'b10); - assign HEAT3D_2__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_2__state <= 2'b00; - end else begin - if(HEAT3D_2__state == 2'b00) begin - if(HEAT3D_2__ap_start_global__q0) begin - HEAT3D_2__state <= 2'b01; - end - end - if(HEAT3D_2__state == 2'b01) begin - if(HEAT3D_2__ap_ready) begin - if(HEAT3D_2__ap_done) begin - HEAT3D_2__state <= 2'b10; - end else begin - HEAT3D_2__state <= 2'b11; - end - end - end - if(HEAT3D_2__state == 2'b11) begin - if(HEAT3D_2__ap_done) begin - HEAT3D_2__state <= 2'b10; - end - end - if(HEAT3D_2__state == 2'b10) begin - if(HEAT3D_2__ap_done_global__q0) begin - HEAT3D_2__state <= 2'b00; - end - end - end - end - - assign HEAT3D_2__ap_start = (HEAT3D_2__state == 2'b01); - assign HEAT3D_3__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_3__is_done__q0 = (HEAT3D_3__state == 2'b10); - assign HEAT3D_3__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_3__state <= 2'b00; - end else begin - if(HEAT3D_3__state == 2'b00) begin - if(HEAT3D_3__ap_start_global__q0) begin - HEAT3D_3__state <= 2'b01; - end - end - if(HEAT3D_3__state == 2'b01) begin - if(HEAT3D_3__ap_ready) begin - if(HEAT3D_3__ap_done) begin - HEAT3D_3__state <= 2'b10; - end else begin - HEAT3D_3__state <= 2'b11; - end - end - end - if(HEAT3D_3__state == 2'b11) begin - if(HEAT3D_3__ap_done) begin - HEAT3D_3__state <= 2'b10; - end - end - if(HEAT3D_3__state == 2'b10) begin - if(HEAT3D_3__ap_done_global__q0) begin - HEAT3D_3__state <= 2'b00; - end - end - end - end - - assign HEAT3D_3__ap_start = (HEAT3D_3__state == 2'b01); - assign HEAT3D_4__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_4__is_done__q0 = (HEAT3D_4__state == 2'b10); - assign HEAT3D_4__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_4__state <= 2'b00; - end else begin - if(HEAT3D_4__state == 2'b00) begin - if(HEAT3D_4__ap_start_global__q0) begin - HEAT3D_4__state <= 2'b01; - end - end - if(HEAT3D_4__state == 2'b01) begin - if(HEAT3D_4__ap_ready) begin - if(HEAT3D_4__ap_done) begin - HEAT3D_4__state <= 2'b10; - end else begin - HEAT3D_4__state <= 2'b11; - end - end - end - if(HEAT3D_4__state == 2'b11) begin - if(HEAT3D_4__ap_done) begin - HEAT3D_4__state <= 2'b10; - end - end - if(HEAT3D_4__state == 2'b10) begin - if(HEAT3D_4__ap_done_global__q0) begin - HEAT3D_4__state <= 2'b00; - end - end - end - end - - assign HEAT3D_4__ap_start = (HEAT3D_4__state == 2'b01); - assign HEAT3D_5__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_5__is_done__q0 = (HEAT3D_5__state == 2'b10); - assign HEAT3D_5__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_5__state <= 2'b00; - end else begin - if(HEAT3D_5__state == 2'b00) begin - if(HEAT3D_5__ap_start_global__q0) begin - HEAT3D_5__state <= 2'b01; - end - end - if(HEAT3D_5__state == 2'b01) begin - if(HEAT3D_5__ap_ready) begin - if(HEAT3D_5__ap_done) begin - HEAT3D_5__state <= 2'b10; - end else begin - HEAT3D_5__state <= 2'b11; - end - end - end - if(HEAT3D_5__state == 2'b11) begin - if(HEAT3D_5__ap_done) begin - HEAT3D_5__state <= 2'b10; - end - end - if(HEAT3D_5__state == 2'b10) begin - if(HEAT3D_5__ap_done_global__q0) begin - HEAT3D_5__state <= 2'b00; - end - end - end - end - - assign HEAT3D_5__ap_start = (HEAT3D_5__state == 2'b01); - assign HEAT3D_6__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_6__is_done__q0 = (HEAT3D_6__state == 2'b10); - assign HEAT3D_6__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_6__state <= 2'b00; - end else begin - if(HEAT3D_6__state == 2'b00) begin - if(HEAT3D_6__ap_start_global__q0) begin - HEAT3D_6__state <= 2'b01; - end - end - if(HEAT3D_6__state == 2'b01) begin - if(HEAT3D_6__ap_ready) begin - if(HEAT3D_6__ap_done) begin - HEAT3D_6__state <= 2'b10; - end else begin - HEAT3D_6__state <= 2'b11; - end - end - end - if(HEAT3D_6__state == 2'b11) begin - if(HEAT3D_6__ap_done) begin - HEAT3D_6__state <= 2'b10; - end - end - if(HEAT3D_6__state == 2'b10) begin - if(HEAT3D_6__ap_done_global__q0) begin - HEAT3D_6__state <= 2'b00; - end - end - end - end - - assign HEAT3D_6__ap_start = (HEAT3D_6__state == 2'b01); - assign HEAT3D_7__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_7__is_done__q0 = (HEAT3D_7__state == 2'b10); - assign HEAT3D_7__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_7__state <= 2'b00; - end else begin - if(HEAT3D_7__state == 2'b00) begin - if(HEAT3D_7__ap_start_global__q0) begin - HEAT3D_7__state <= 2'b01; - end - end - if(HEAT3D_7__state == 2'b01) begin - if(HEAT3D_7__ap_ready) begin - if(HEAT3D_7__ap_done) begin - HEAT3D_7__state <= 2'b10; - end else begin - HEAT3D_7__state <= 2'b11; - end - end - end - if(HEAT3D_7__state == 2'b11) begin - if(HEAT3D_7__ap_done) begin - HEAT3D_7__state <= 2'b10; - end - end - if(HEAT3D_7__state == 2'b10) begin - if(HEAT3D_7__ap_done_global__q0) begin - HEAT3D_7__state <= 2'b00; - end - end - end - end - - assign HEAT3D_7__ap_start = (HEAT3D_7__state == 2'b01); - assign HEAT3D_8__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_8__is_done__q0 = (HEAT3D_8__state == 2'b10); - assign HEAT3D_8__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_8__state <= 2'b00; - end else begin - if(HEAT3D_8__state == 2'b00) begin - if(HEAT3D_8__ap_start_global__q0) begin - HEAT3D_8__state <= 2'b01; - end - end - if(HEAT3D_8__state == 2'b01) begin - if(HEAT3D_8__ap_ready) begin - if(HEAT3D_8__ap_done) begin - HEAT3D_8__state <= 2'b10; - end else begin - HEAT3D_8__state <= 2'b11; - end - end - end - if(HEAT3D_8__state == 2'b11) begin - if(HEAT3D_8__ap_done) begin - HEAT3D_8__state <= 2'b10; - end - end - if(HEAT3D_8__state == 2'b10) begin - if(HEAT3D_8__ap_done_global__q0) begin - HEAT3D_8__state <= 2'b00; - end - end - end - end - - assign HEAT3D_8__ap_start = (HEAT3D_8__state == 2'b01); - assign HEAT3D_9__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_9__is_done__q0 = (HEAT3D_9__state == 2'b10); - assign HEAT3D_9__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_9__state <= 2'b00; - end else begin - if(HEAT3D_9__state == 2'b00) begin - if(HEAT3D_9__ap_start_global__q0) begin - HEAT3D_9__state <= 2'b01; - end - end - if(HEAT3D_9__state == 2'b01) begin - if(HEAT3D_9__ap_ready) begin - if(HEAT3D_9__ap_done) begin - HEAT3D_9__state <= 2'b10; - end else begin - HEAT3D_9__state <= 2'b11; - end - end - end - if(HEAT3D_9__state == 2'b11) begin - if(HEAT3D_9__ap_done) begin - HEAT3D_9__state <= 2'b10; - end - end - if(HEAT3D_9__state == 2'b10) begin - if(HEAT3D_9__ap_done_global__q0) begin - HEAT3D_9__state <= 2'b00; - end - end - end - end - - assign HEAT3D_9__ap_start = (HEAT3D_9__state == 2'b01); - assign HEAT3D_10__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_10__is_done__q0 = (HEAT3D_10__state == 2'b10); - assign HEAT3D_10__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_10__state <= 2'b00; - end else begin - if(HEAT3D_10__state == 2'b00) begin - if(HEAT3D_10__ap_start_global__q0) begin - HEAT3D_10__state <= 2'b01; - end - end - if(HEAT3D_10__state == 2'b01) begin - if(HEAT3D_10__ap_ready) begin - if(HEAT3D_10__ap_done) begin - HEAT3D_10__state <= 2'b10; - end else begin - HEAT3D_10__state <= 2'b11; - end - end - end - if(HEAT3D_10__state == 2'b11) begin - if(HEAT3D_10__ap_done) begin - HEAT3D_10__state <= 2'b10; - end - end - if(HEAT3D_10__state == 2'b10) begin - if(HEAT3D_10__ap_done_global__q0) begin - HEAT3D_10__state <= 2'b00; - end - end - end - end - - assign HEAT3D_10__ap_start = (HEAT3D_10__state == 2'b01); - assign HEAT3D_11__ap_start_global__q0 = ap_start__q0; - assign HEAT3D_11__is_done__q0 = (HEAT3D_11__state == 2'b10); - assign HEAT3D_11__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - HEAT3D_11__state <= 2'b00; - end else begin - if(HEAT3D_11__state == 2'b00) begin - if(HEAT3D_11__ap_start_global__q0) begin - HEAT3D_11__state <= 2'b01; - end - end - if(HEAT3D_11__state == 2'b01) begin - if(HEAT3D_11__ap_ready) begin - if(HEAT3D_11__ap_done) begin - HEAT3D_11__state <= 2'b10; - end else begin - HEAT3D_11__state <= 2'b11; - end - end - end - if(HEAT3D_11__state == 2'b11) begin - if(HEAT3D_11__ap_done) begin - HEAT3D_11__state <= 2'b10; - end - end - if(HEAT3D_11__state == 2'b10) begin - if(HEAT3D_11__ap_done_global__q0) begin - HEAT3D_11__state <= 2'b00; - end - end - end - end - - assign HEAT3D_11__ap_start = (HEAT3D_11__state == 2'b01); - assign inter_kernel_0__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_0__is_done__q0 = (inter_kernel_0__state == 2'b10); - assign inter_kernel_0__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_0__state <= 2'b00; - end else begin - if(inter_kernel_0__state == 2'b00) begin - if(inter_kernel_0__ap_start_global__q0) begin - inter_kernel_0__state <= 2'b01; - end - end - if(inter_kernel_0__state == 2'b01) begin - if(inter_kernel_0__ap_ready) begin - if(inter_kernel_0__ap_done) begin - inter_kernel_0__state <= 2'b10; - end else begin - inter_kernel_0__state <= 2'b11; - end - end - end - if(inter_kernel_0__state == 2'b11) begin - if(inter_kernel_0__ap_done) begin - inter_kernel_0__state <= 2'b10; - end - end - if(inter_kernel_0__state == 2'b10) begin - if(inter_kernel_0__ap_done_global__q0) begin - inter_kernel_0__state <= 2'b00; - end - end - end - end - - assign inter_kernel_0__ap_start = (inter_kernel_0__state == 2'b01); - assign inter_kernel_1__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_1__is_done__q0 = (inter_kernel_1__state == 2'b10); - assign inter_kernel_1__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_1__state <= 2'b00; - end else begin - if(inter_kernel_1__state == 2'b00) begin - if(inter_kernel_1__ap_start_global__q0) begin - inter_kernel_1__state <= 2'b01; - end - end - if(inter_kernel_1__state == 2'b01) begin - if(inter_kernel_1__ap_ready) begin - if(inter_kernel_1__ap_done) begin - inter_kernel_1__state <= 2'b10; - end else begin - inter_kernel_1__state <= 2'b11; - end - end - end - if(inter_kernel_1__state == 2'b11) begin - if(inter_kernel_1__ap_done) begin - inter_kernel_1__state <= 2'b10; - end - end - if(inter_kernel_1__state == 2'b10) begin - if(inter_kernel_1__ap_done_global__q0) begin - inter_kernel_1__state <= 2'b00; - end - end - end - end - - assign inter_kernel_1__ap_start = (inter_kernel_1__state == 2'b01); - assign inter_kernel_2__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_2__is_done__q0 = (inter_kernel_2__state == 2'b10); - assign inter_kernel_2__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_2__state <= 2'b00; - end else begin - if(inter_kernel_2__state == 2'b00) begin - if(inter_kernel_2__ap_start_global__q0) begin - inter_kernel_2__state <= 2'b01; - end - end - if(inter_kernel_2__state == 2'b01) begin - if(inter_kernel_2__ap_ready) begin - if(inter_kernel_2__ap_done) begin - inter_kernel_2__state <= 2'b10; - end else begin - inter_kernel_2__state <= 2'b11; - end - end - end - if(inter_kernel_2__state == 2'b11) begin - if(inter_kernel_2__ap_done) begin - inter_kernel_2__state <= 2'b10; - end - end - if(inter_kernel_2__state == 2'b10) begin - if(inter_kernel_2__ap_done_global__q0) begin - inter_kernel_2__state <= 2'b00; - end - end - end - end - - assign inter_kernel_2__ap_start = (inter_kernel_2__state == 2'b01); - assign inter_kernel_3__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_3__is_done__q0 = (inter_kernel_3__state == 2'b10); - assign inter_kernel_3__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_3__state <= 2'b00; - end else begin - if(inter_kernel_3__state == 2'b00) begin - if(inter_kernel_3__ap_start_global__q0) begin - inter_kernel_3__state <= 2'b01; - end - end - if(inter_kernel_3__state == 2'b01) begin - if(inter_kernel_3__ap_ready) begin - if(inter_kernel_3__ap_done) begin - inter_kernel_3__state <= 2'b10; - end else begin - inter_kernel_3__state <= 2'b11; - end - end - end - if(inter_kernel_3__state == 2'b11) begin - if(inter_kernel_3__ap_done) begin - inter_kernel_3__state <= 2'b10; - end - end - if(inter_kernel_3__state == 2'b10) begin - if(inter_kernel_3__ap_done_global__q0) begin - inter_kernel_3__state <= 2'b00; - end - end - end - end - - assign inter_kernel_3__ap_start = (inter_kernel_3__state == 2'b01); - assign inter_kernel_4__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_4__is_done__q0 = (inter_kernel_4__state == 2'b10); - assign inter_kernel_4__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_4__state <= 2'b00; - end else begin - if(inter_kernel_4__state == 2'b00) begin - if(inter_kernel_4__ap_start_global__q0) begin - inter_kernel_4__state <= 2'b01; - end - end - if(inter_kernel_4__state == 2'b01) begin - if(inter_kernel_4__ap_ready) begin - if(inter_kernel_4__ap_done) begin - inter_kernel_4__state <= 2'b10; - end else begin - inter_kernel_4__state <= 2'b11; - end - end - end - if(inter_kernel_4__state == 2'b11) begin - if(inter_kernel_4__ap_done) begin - inter_kernel_4__state <= 2'b10; - end - end - if(inter_kernel_4__state == 2'b10) begin - if(inter_kernel_4__ap_done_global__q0) begin - inter_kernel_4__state <= 2'b00; - end - end - end - end - - assign inter_kernel_4__ap_start = (inter_kernel_4__state == 2'b01); - assign inter_kernel_5__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_5__is_done__q0 = (inter_kernel_5__state == 2'b10); - assign inter_kernel_5__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_5__state <= 2'b00; - end else begin - if(inter_kernel_5__state == 2'b00) begin - if(inter_kernel_5__ap_start_global__q0) begin - inter_kernel_5__state <= 2'b01; - end - end - if(inter_kernel_5__state == 2'b01) begin - if(inter_kernel_5__ap_ready) begin - if(inter_kernel_5__ap_done) begin - inter_kernel_5__state <= 2'b10; - end else begin - inter_kernel_5__state <= 2'b11; - end - end - end - if(inter_kernel_5__state == 2'b11) begin - if(inter_kernel_5__ap_done) begin - inter_kernel_5__state <= 2'b10; - end - end - if(inter_kernel_5__state == 2'b10) begin - if(inter_kernel_5__ap_done_global__q0) begin - inter_kernel_5__state <= 2'b00; - end - end - end - end - - assign inter_kernel_5__ap_start = (inter_kernel_5__state == 2'b01); - assign inter_kernel_6__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_6__is_done__q0 = (inter_kernel_6__state == 2'b10); - assign inter_kernel_6__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_6__state <= 2'b00; - end else begin - if(inter_kernel_6__state == 2'b00) begin - if(inter_kernel_6__ap_start_global__q0) begin - inter_kernel_6__state <= 2'b01; - end - end - if(inter_kernel_6__state == 2'b01) begin - if(inter_kernel_6__ap_ready) begin - if(inter_kernel_6__ap_done) begin - inter_kernel_6__state <= 2'b10; - end else begin - inter_kernel_6__state <= 2'b11; - end - end - end - if(inter_kernel_6__state == 2'b11) begin - if(inter_kernel_6__ap_done) begin - inter_kernel_6__state <= 2'b10; - end - end - if(inter_kernel_6__state == 2'b10) begin - if(inter_kernel_6__ap_done_global__q0) begin - inter_kernel_6__state <= 2'b00; - end - end - end - end - - assign inter_kernel_6__ap_start = (inter_kernel_6__state == 2'b01); - assign inter_kernel_7__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_7__is_done__q0 = (inter_kernel_7__state == 2'b10); - assign inter_kernel_7__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_7__state <= 2'b00; - end else begin - if(inter_kernel_7__state == 2'b00) begin - if(inter_kernel_7__ap_start_global__q0) begin - inter_kernel_7__state <= 2'b01; - end - end - if(inter_kernel_7__state == 2'b01) begin - if(inter_kernel_7__ap_ready) begin - if(inter_kernel_7__ap_done) begin - inter_kernel_7__state <= 2'b10; - end else begin - inter_kernel_7__state <= 2'b11; - end - end - end - if(inter_kernel_7__state == 2'b11) begin - if(inter_kernel_7__ap_done) begin - inter_kernel_7__state <= 2'b10; - end - end - if(inter_kernel_7__state == 2'b10) begin - if(inter_kernel_7__ap_done_global__q0) begin - inter_kernel_7__state <= 2'b00; - end - end - end - end - - assign inter_kernel_7__ap_start = (inter_kernel_7__state == 2'b01); - assign inter_kernel_8__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_8__is_done__q0 = (inter_kernel_8__state == 2'b10); - assign inter_kernel_8__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_8__state <= 2'b00; - end else begin - if(inter_kernel_8__state == 2'b00) begin - if(inter_kernel_8__ap_start_global__q0) begin - inter_kernel_8__state <= 2'b01; - end - end - if(inter_kernel_8__state == 2'b01) begin - if(inter_kernel_8__ap_ready) begin - if(inter_kernel_8__ap_done) begin - inter_kernel_8__state <= 2'b10; - end else begin - inter_kernel_8__state <= 2'b11; - end - end - end - if(inter_kernel_8__state == 2'b11) begin - if(inter_kernel_8__ap_done) begin - inter_kernel_8__state <= 2'b10; - end - end - if(inter_kernel_8__state == 2'b10) begin - if(inter_kernel_8__ap_done_global__q0) begin - inter_kernel_8__state <= 2'b00; - end - end - end - end - - assign inter_kernel_8__ap_start = (inter_kernel_8__state == 2'b01); - assign inter_kernel_9__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_9__is_done__q0 = (inter_kernel_9__state == 2'b10); - assign inter_kernel_9__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_9__state <= 2'b00; - end else begin - if(inter_kernel_9__state == 2'b00) begin - if(inter_kernel_9__ap_start_global__q0) begin - inter_kernel_9__state <= 2'b01; - end - end - if(inter_kernel_9__state == 2'b01) begin - if(inter_kernel_9__ap_ready) begin - if(inter_kernel_9__ap_done) begin - inter_kernel_9__state <= 2'b10; - end else begin - inter_kernel_9__state <= 2'b11; - end - end - end - if(inter_kernel_9__state == 2'b11) begin - if(inter_kernel_9__ap_done) begin - inter_kernel_9__state <= 2'b10; - end - end - if(inter_kernel_9__state == 2'b10) begin - if(inter_kernel_9__ap_done_global__q0) begin - inter_kernel_9__state <= 2'b00; - end - end - end - end - - assign inter_kernel_9__ap_start = (inter_kernel_9__state == 2'b01); - assign inter_kernel_10__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_10__is_done__q0 = (inter_kernel_10__state == 2'b10); - assign inter_kernel_10__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_10__state <= 2'b00; - end else begin - if(inter_kernel_10__state == 2'b00) begin - if(inter_kernel_10__ap_start_global__q0) begin - inter_kernel_10__state <= 2'b01; - end - end - if(inter_kernel_10__state == 2'b01) begin - if(inter_kernel_10__ap_ready) begin - if(inter_kernel_10__ap_done) begin - inter_kernel_10__state <= 2'b10; - end else begin - inter_kernel_10__state <= 2'b11; - end - end - end - if(inter_kernel_10__state == 2'b11) begin - if(inter_kernel_10__ap_done) begin - inter_kernel_10__state <= 2'b10; - end - end - if(inter_kernel_10__state == 2'b10) begin - if(inter_kernel_10__ap_done_global__q0) begin - inter_kernel_10__state <= 2'b00; - end - end - end - end - - assign inter_kernel_10__ap_start = (inter_kernel_10__state == 2'b01); - assign inter_kernel_11__ap_start_global__q0 = ap_start__q0; - assign inter_kernel_11__is_done__q0 = (inter_kernel_11__state == 2'b10); - assign inter_kernel_11__ap_done_global__q0 = ap_done__q0; - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - inter_kernel_11__state <= 2'b00; - end else begin - if(inter_kernel_11__state == 2'b00) begin - if(inter_kernel_11__ap_start_global__q0) begin - inter_kernel_11__state <= 2'b01; - end - end - if(inter_kernel_11__state == 2'b01) begin - if(inter_kernel_11__ap_ready) begin - if(inter_kernel_11__ap_done) begin - inter_kernel_11__state <= 2'b10; - end else begin - inter_kernel_11__state <= 2'b11; - end - end - end - if(inter_kernel_11__state == 2'b11) begin - if(inter_kernel_11__ap_done) begin - inter_kernel_11__state <= 2'b10; - end - end - if(inter_kernel_11__state == 2'b10) begin - if(inter_kernel_11__ap_done_global__q0) begin - inter_kernel_11__state <= 2'b00; - end - end - end - end - - assign inter_kernel_11__ap_start = (inter_kernel_11__state == 2'b01); - - always @(posedge ap_clk) begin - if(~ap_rst_n) begin - tapa_state <= 2'b00; - end else begin - case(tapa_state) - 2'b00: begin - if(ap_start__q0) begin - tapa_state <= 2'b01; - end - end - 2'b01: begin - if(HEAT3D_0__is_done__q0 && HEAT3D_1__is_done__q0 && HEAT3D_2__is_done__q0 && HEAT3D_3__is_done__q0 && HEAT3D_4__is_done__q0 && HEAT3D_5__is_done__q0 && HEAT3D_6__is_done__q0 && HEAT3D_7__is_done__q0 && HEAT3D_8__is_done__q0 && HEAT3D_9__is_done__q0 && HEAT3D_10__is_done__q0 && HEAT3D_11__is_done__q0 && inter_kernel_0__is_done__q0 && inter_kernel_1__is_done__q0 && inter_kernel_2__is_done__q0 && inter_kernel_3__is_done__q0 && inter_kernel_4__is_done__q0 && inter_kernel_5__is_done__q0 && inter_kernel_6__is_done__q0 && inter_kernel_7__is_done__q0 && inter_kernel_8__is_done__q0 && inter_kernel_9__is_done__q0 && inter_kernel_10__is_done__q0 && inter_kernel_11__is_done__q0) begin - tapa_state <= 2'b10; - end - end - 2'b10: begin - tapa_state <= 2'b00; - countdown <= 1'd0; - end - 2'b11: begin - if(countdown == 1'd0) begin - tapa_state <= 2'b00; - end else begin - countdown <= (countdown - 1'd1); - end - end - endcase - end - end - - assign ap_idle = (tapa_state == 2'b00); - assign ap_done = ap_done__q0; - assign ap_ready = ap_done__q0; - assign ap_start__q0 = ap_start; - assign ap_done__q0 = (tapa_state == 2'b10); - -endmodule diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/log/tapac.INFO b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/log/tapac.INFO deleted file mode 120000 index 5878a575..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/log/tapac.INFO +++ /dev/null @@ -1 +0,0 @@ -tapac.iquark.ylxiao.log.INFO.20240712-200239.33259 \ No newline at end of file diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/log/tapac.iquark.ylxiao.log.INFO.20240712-200239.33259 b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/log/tapac.iquark.ylxiao.log.INFO.20240712-200239.33259 deleted file mode 100644 index c2ab4a45..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/log/tapac.iquark.ylxiao.log.INFO.20240712-200239.33259 +++ /dev/null @@ -1,2249 +0,0 @@ -I0712 20:02:39.695 tapa.util:184] logging level set to INFO -I0712 20:02:39.695 tapa.tapac:407] Executing all steps of tapac -I0712 20:02:39.695 tapa.tapac:521] running translated command: `tapa --work-dir=generated analyze --input=src/unikernel.cpp --top=unikernel synth --part-num=xcu280-fsvh2892-2L-e --clock-period=3.33 link pack --output=generated/unikernel.xo` -I0712 20:02:39.695 tapa.util:184] logging level set to INFO -I0712 20:02:39.695 tapa.util:184] logging level set to INFO -I0712 20:02:39.695 tapa.tapa:54] tapa version: 0.0.20240301.1 -I0712 20:02:39.695 tapa.tapa:54] tapa version: 0.0.20240301.1 -I0712 20:02:39.695 tapa.tapa:58] Python recursion limit set to 3000 -I0712 20:02:39.695 tapa.tapa:58] Python recursion limit set to 3000 -I0712 20:02:39.791 tapa.steps.analyze:151] added vendor include path `/tools/Xilinx/Vitis_HLS/2022.2/include` -I0712 20:02:39.791 tapa.steps.analyze:151] added vendor include path `/tools/Xilinx/Vitis_HLS/2022.2/include` -I0712 20:02:39.792 tapa.steps.analyze:248] Running tapacc command: /usr/bin/tapacc generated/flatten/flatten-e756cccc-unikernel.cpp -top unikernel -- -std=c++17 -I /home/ylxiao/.local/lib/python3.8/site-packages/tapa/../../../src -isystem /tools/Xilinx/Vitis_HLS/2022.2/include -stdlib=libc++ -isystem /usr/lib/llvm-17/include/c++/v1/ -isystem /usr/include/clang/17/include/ -isystem /usr/lib/clang/17/include/ -I0712 20:02:39.792 tapa.steps.analyze:248] Running tapacc command: /usr/bin/tapacc generated/flatten/flatten-e756cccc-unikernel.cpp -top unikernel -- -std=c++17 -I /home/ylxiao/.local/lib/python3.8/site-packages/tapa/../../../src -isystem /tools/Xilinx/Vitis_HLS/2022.2/include -stdlib=libc++ -isystem /usr/lib/llvm-17/include/c++/v1/ -isystem /usr/include/clang/17/include/ -isystem /usr/lib/clang/17/include/ -I0712 20:02:40.935 tapa.steps.common:92] writing TAPA graph to json `generated/graph.json`. -I0712 20:02:40.935 tapa.steps.common:92] writing TAPA graph to json `generated/graph.json`. -I0712 20:02:40.936 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 20:02:40.936 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 20:02:40.937 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 20:02:40.937 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 20:02:40.937 tapa.core:184] extracting HLS C++ files -I0712 20:02:40.937 tapa.core:184] extracting HLS C++ files -I0712 20:02:40.938 tapa.core:216] running HLS -I0712 20:02:40.938 tapa.core:216] running HLS -I0712 20:02:40.940 tapa.core:262] spawn 8 workers for parallel HLS synthesis of the tasks -I0712 20:02:40.940 tapa.core:262] spawn 8 workers for parallel HLS synthesis of the tasks -I0712 20:03:04.052 tapa.core:277] extracting RTL files -I0712 20:03:04.052 tapa.core:277] extracting RTL files -I0712 20:03:04.085 tapa.core:308] parsing RTL files and populating tasks -I0712 20:03:04.085 tapa.core:308] parsing RTL files and populating tasks -D0712 20:03:04.644 tapa.core:317] parsing HEAT3D -D0712 20:03:04.644 tapa.core:317] parsing HEAT3D -D0712 20:03:04.644 tapa.core:321] populating HEAT3D -D0712 20:03:04.644 tapa.core:321] populating HEAT3D -D0712 20:03:04.646 tapa.core:317] parsing inter_kernel -D0712 20:03:04.646 tapa.core:317] parsing inter_kernel -D0712 20:03:04.647 tapa.core:321] populating inter_kernel -D0712 20:03:04.647 tapa.core:321] populating inter_kernel -D0712 20:03:04.647 tapa.core:317] parsing unikernel -D0712 20:03:04.647 tapa.core:317] parsing unikernel -D0712 20:03:04.647 tapa.core:321] populating unikernel -D0712 20:03:04.647 tapa.core:321] populating unikernel -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_0.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_0.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_0.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_0' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_0.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_1.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_1.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_1.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_1' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_1.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_2.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_2.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_2.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_2' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_2.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_3.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_3.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_3.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_3' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_3.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_4' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_4.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_4' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_4.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_4' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_4.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_4' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_4.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_5' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_5.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_5' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_5.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_5' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_5.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_5' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_5.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_6' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_6.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_6' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_6.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_6' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_6.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_6' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_6.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_7' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_7.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_7' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_7.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_7' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_7.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_7' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_7.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_8' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_8.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_8' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_8.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_8' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_8.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_8' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_8.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_9' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_9.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_9' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_9.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_9' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_9.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_9' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_9.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_10' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_10.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_10' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_10.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_10' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_10.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_10' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_10.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_11' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_11.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.in_11' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_11.a' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_11' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_11.b' -D0712 20:03:04.648 tapa.task:149] mmap argument 'unikernel.out_11' (id_width=1, thread_count=1, chan_size=None, chan_count=None) is connected to port 'inter_kernel_11.b' -I0712 20:03:04.648 tapa.core:325] instrumenting upper-level RTL -I0712 20:03:04.648 tapa.core:325] instrumenting upper-level RTL -I0712 20:03:04.648 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 20:03:04.648 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 20:03:04.648 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 20:03:04.648 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 20:03:04.649 tapa.core:452] top task register level set to 0 -I0712 20:03:04.649 tapa.core:452] top task register level set to 0 -I0712 20:03:04.649 tapa.core:456] instrumenting top-level RTL -I0712 20:03:04.649 tapa.core:456] instrumenting top-level RTL -D0712 20:03:04.649 tapa.core:529] instantiating FIFOs in unikernel -D0712 20:03:04.649 tapa.core:529] instantiating FIFOs in unikernel -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[0] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[0] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[10] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[10] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[11] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[11] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[1] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[1] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[2] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[2] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[3] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[3] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[4] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[4] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[5] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[5] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[6] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[6] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[7] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[7] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[8] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[8] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[9] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_rd_unikernel[9] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_wr_unikernel[0] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_wr_unikernel[0] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_wr_unikernel[10] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_wr_unikernel[10] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_wr_unikernel[11] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_wr_unikernel[11] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_wr_unikernel[1] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_wr_unikernel[1] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_wr_unikernel[2] -D0712 20:03:04.650 tapa.core:542] instantiating unikernel.k_wr_unikernel[2] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[3] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[3] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[4] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[4] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[5] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[5] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[6] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[6] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[7] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[7] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[8] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[8] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[9] -D0712 20:03:04.651 tapa.core:542] instantiating unikernel.k_wr_unikernel[9] -D0712 20:03:04.651 tapa.core:507] connecting unikernel's children tasks -D0712 20:03:04.651 tapa.core:507] connecting unikernel's children tasks -D0712 20:03:04.654 tapa.core:598] instantiating children tasks in unikernel -D0712 20:03:04.654 tapa.core:598] instantiating children tasks in unikernel -D0712 20:03:04.669 tapa.core:671] pipelined signal: iters => HEAT3D_0___iters -D0712 20:03:04.669 tapa.core:671] pipelined signal: iters => HEAT3D_0___iters -D0712 20:03:04.669 tapa.core:671] pipelined signal: iters => HEAT3D_1___iters -D0712 20:03:04.669 tapa.core:671] pipelined signal: iters => HEAT3D_1___iters -D0712 20:03:04.669 tapa.core:671] pipelined signal: iters => HEAT3D_2___iters -D0712 20:03:04.669 tapa.core:671] pipelined signal: iters => HEAT3D_2___iters -D0712 20:03:04.670 tapa.core:671] pipelined signal: iters => HEAT3D_3___iters -D0712 20:03:04.670 tapa.core:671] pipelined signal: iters => HEAT3D_3___iters -D0712 20:03:04.670 tapa.core:671] pipelined signal: iters => HEAT3D_4___iters -D0712 20:03:04.670 tapa.core:671] pipelined signal: iters => HEAT3D_4___iters -D0712 20:03:04.671 tapa.core:671] pipelined signal: iters => HEAT3D_5___iters -D0712 20:03:04.671 tapa.core:671] pipelined signal: iters => HEAT3D_5___iters -D0712 20:03:04.671 tapa.core:671] pipelined signal: iters => HEAT3D_6___iters -D0712 20:03:04.671 tapa.core:671] pipelined signal: iters => HEAT3D_6___iters -D0712 20:03:04.671 tapa.core:671] pipelined signal: iters => HEAT3D_7___iters -D0712 20:03:04.671 tapa.core:671] pipelined signal: iters => HEAT3D_7___iters -D0712 20:03:04.672 tapa.core:671] pipelined signal: iters => HEAT3D_8___iters -D0712 20:03:04.672 tapa.core:671] pipelined signal: iters => HEAT3D_8___iters -D0712 20:03:04.672 tapa.core:671] pipelined signal: iters => HEAT3D_9___iters -D0712 20:03:04.672 tapa.core:671] pipelined signal: iters => HEAT3D_9___iters -D0712 20:03:04.672 tapa.core:671] pipelined signal: iters => HEAT3D_10___iters -D0712 20:03:04.672 tapa.core:671] pipelined signal: iters => HEAT3D_10___iters -D0712 20:03:04.673 tapa.core:671] pipelined signal: iters => HEAT3D_11___iters -D0712 20:03:04.673 tapa.core:671] pipelined signal: iters => HEAT3D_11___iters -D0712 20:03:04.673 tapa.core:671] pipelined signal: in_0 => inter_kernel_0___in_0 -D0712 20:03:04.673 tapa.core:671] pipelined signal: in_0 => inter_kernel_0___in_0 -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_din` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_din` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_full_n` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_full_n` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_write` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_write` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_dout` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_dout` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_read_data_peek_dout` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_read_data_peek_dout` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_empty_n` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_empty_n` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_read_data_peek_empty_n` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_read_data_peek_empty_n` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_read` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.673 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_read` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_din` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_din` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_full_n` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_full_n` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_write` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_write` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_din` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_din` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_full_n` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_full_n` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_write` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_write` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_dout` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_dout` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_write_resp_peek_dout` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_write_resp_peek_dout` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_empty_n` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_empty_n` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_write_resp_peek_empty_n` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_write_resp_peek_empty_n` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_read` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_read` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.674 tapa.core:671] pipelined signal: iters => inter_kernel_0___iters -D0712 20:03:04.674 tapa.core:671] pipelined signal: iters => inter_kernel_0___iters -D0712 20:03:04.674 tapa.core:671] pipelined signal: out_0 => inter_kernel_0___out_0 -D0712 20:03:04.674 tapa.core:671] pipelined signal: out_0 => inter_kernel_0___out_0 -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_din` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_din` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_full_n` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_full_n` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_write` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_write` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_dout` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_dout` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_read_data_peek_dout` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_read_data_peek_dout` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_empty_n` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_empty_n` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_read_data_peek_empty_n` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.674 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_read_data_peek_empty_n` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_read` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_read` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_din` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_din` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_full_n` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_full_n` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_write` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_write` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_din` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_din` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_full_n` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_full_n` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_write` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_write` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_dout` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_dout` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_write_resp_peek_dout` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_write_resp_peek_dout` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_empty_n` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_empty_n` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_write_resp_peek_empty_n` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_write_resp_peek_empty_n` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_read` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_read` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_din` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_din` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_full_n` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_full_n` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_write` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.675 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_addr_write` is connected to async_mmap port `in_0.read_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_dout` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_dout` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_read_data_peek_dout` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_read_data_peek_dout` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_empty_n` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_empty_n` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_read_data_peek_empty_n` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_read_data_peek_empty_n` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_read` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_read_data_s_read` is connected to async_mmap port `in_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_din` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_din` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_full_n` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_full_n` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_write` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_addr_write` is connected to async_mmap port `in_0.write_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_din` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_din` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_full_n` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_full_n` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_write` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_data_write` is connected to async_mmap port `in_0.write_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_dout` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_dout` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_write_resp_peek_dout` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_write_resp_peek_dout` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_empty_n` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_empty_n` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_write_resp_peek_empty_n` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.a_write_resp_peek_empty_n` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_read` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.a_write_resp_s_read` is connected to async_mmap port `in_0.write_resp` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_din` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_din` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_full_n` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_full_n` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_write` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_addr_write` is connected to async_mmap port `out_0.read_addr` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_dout` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.676 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_dout` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_read_data_peek_dout` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_read_data_peek_dout` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_empty_n` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_empty_n` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_read_data_peek_empty_n` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_read_data_peek_empty_n` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_read` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_read_data_s_read` is connected to async_mmap port `out_0.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_din` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_din` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_full_n` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_full_n` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_write` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_addr_write` is connected to async_mmap port `out_0.write_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_din` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_din` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_full_n` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_full_n` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_write` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_data_write` is connected to async_mmap port `out_0.write_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_dout` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_dout` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_write_resp_peek_dout` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_write_resp_peek_dout` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_empty_n` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_empty_n` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_write_resp_peek_empty_n` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_0.b_write_resp_peek_empty_n` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_read` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_0.b_write_resp_s_read` is connected to async_mmap port `out_0.write_resp` -D0712 20:03:04.677 tapa.core:671] pipelined signal: in_1 => inter_kernel_1___in_1 -D0712 20:03:04.677 tapa.core:671] pipelined signal: in_1 => inter_kernel_1___in_1 -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_din` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_din` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_full_n` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_full_n` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_write` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_write` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_dout` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_dout` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_read_data_peek_dout` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_read_data_peek_dout` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_empty_n` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_empty_n` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_read_data_peek_empty_n` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.677 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_read_data_peek_empty_n` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_read` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_read` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_din` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_din` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_full_n` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_full_n` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_write` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_write` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_din` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_din` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_full_n` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_full_n` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_write` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_write` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_dout` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_dout` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_write_resp_peek_dout` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_write_resp_peek_dout` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_empty_n` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_empty_n` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_write_resp_peek_empty_n` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_write_resp_peek_empty_n` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_read` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_read` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.678 tapa.core:671] pipelined signal: iters => inter_kernel_1___iters -D0712 20:03:04.678 tapa.core:671] pipelined signal: iters => inter_kernel_1___iters -D0712 20:03:04.678 tapa.core:671] pipelined signal: out_1 => inter_kernel_1___out_1 -D0712 20:03:04.678 tapa.core:671] pipelined signal: out_1 => inter_kernel_1___out_1 -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_din` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_din` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_full_n` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_full_n` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_write` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_write` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_dout` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_dout` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_read_data_peek_dout` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_read_data_peek_dout` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_empty_n` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_empty_n` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_read_data_peek_empty_n` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.678 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_read_data_peek_empty_n` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_read` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_read` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_din` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_din` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_full_n` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_full_n` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_write` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_write` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_din` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_din` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_full_n` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_full_n` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_write` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_write` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_dout` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_dout` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_write_resp_peek_dout` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_write_resp_peek_dout` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_empty_n` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_empty_n` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_write_resp_peek_empty_n` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_write_resp_peek_empty_n` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_read` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.679 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_read` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_din` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_din` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_full_n` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_full_n` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_write` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_addr_write` is connected to async_mmap port `in_1.read_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_dout` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_dout` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_read_data_peek_dout` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_read_data_peek_dout` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_empty_n` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_empty_n` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_read_data_peek_empty_n` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_read_data_peek_empty_n` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_read` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_read_data_s_read` is connected to async_mmap port `in_1.read_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_din` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_din` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_full_n` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_full_n` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_write` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_addr_write` is connected to async_mmap port `in_1.write_addr` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_din` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_din` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_full_n` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_full_n` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_write` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_data_write` is connected to async_mmap port `in_1.write_data` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_dout` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_dout` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_write_resp_peek_dout` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_write_resp_peek_dout` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_empty_n` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_empty_n` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_write_resp_peek_empty_n` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.a_write_resp_peek_empty_n` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_read` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.680 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.a_write_resp_s_read` is connected to async_mmap port `in_1.write_resp` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_din` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_din` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_full_n` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_full_n` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_write` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_addr_write` is connected to async_mmap port `out_1.read_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_dout` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_dout` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_read_data_peek_dout` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_read_data_peek_dout` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_empty_n` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_empty_n` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_read_data_peek_empty_n` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_read_data_peek_empty_n` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_read` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_read_data_s_read` is connected to async_mmap port `out_1.read_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_din` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_din` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_full_n` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_full_n` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_write` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_addr_write` is connected to async_mmap port `out_1.write_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_din` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_din` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_full_n` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_full_n` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_write` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_data_write` is connected to async_mmap port `out_1.write_data` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_dout` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_dout` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_write_resp_peek_dout` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_write_resp_peek_dout` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_empty_n` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_empty_n` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_write_resp_peek_empty_n` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_1.b_write_resp_peek_empty_n` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_read` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_1.b_write_resp_s_read` is connected to async_mmap port `out_1.write_resp` -D0712 20:03:04.681 tapa.core:671] pipelined signal: in_2 => inter_kernel_2___in_2 -D0712 20:03:04.681 tapa.core:671] pipelined signal: in_2 => inter_kernel_2___in_2 -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_din` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.681 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_din` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_full_n` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_full_n` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_write` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_write` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_dout` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_dout` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_read_data_peek_dout` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_read_data_peek_dout` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_empty_n` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_empty_n` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_read_data_peek_empty_n` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_read_data_peek_empty_n` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_read` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_read` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_din` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_din` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_full_n` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_full_n` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_write` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_write` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_din` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_din` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_full_n` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_full_n` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_write` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_write` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_dout` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_dout` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_write_resp_peek_dout` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_write_resp_peek_dout` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_empty_n` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_empty_n` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_write_resp_peek_empty_n` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_write_resp_peek_empty_n` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_read` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_read` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.682 tapa.core:671] pipelined signal: iters => inter_kernel_2___iters -D0712 20:03:04.682 tapa.core:671] pipelined signal: iters => inter_kernel_2___iters -D0712 20:03:04.682 tapa.core:671] pipelined signal: out_2 => inter_kernel_2___out_2 -D0712 20:03:04.682 tapa.core:671] pipelined signal: out_2 => inter_kernel_2___out_2 -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_din` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_din` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_full_n` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.682 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_full_n` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_write` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_write` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_dout` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_dout` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_read_data_peek_dout` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_read_data_peek_dout` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_empty_n` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_empty_n` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_read_data_peek_empty_n` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_read_data_peek_empty_n` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_read` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_read` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_din` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_din` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_full_n` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_full_n` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_write` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_write` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_din` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_din` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_full_n` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_full_n` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_write` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_write` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_dout` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_dout` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_write_resp_peek_dout` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_write_resp_peek_dout` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_empty_n` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_empty_n` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_write_resp_peek_empty_n` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_write_resp_peek_empty_n` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_read` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.683 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_read` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_din` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_din` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_full_n` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_full_n` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_write` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_addr_write` is connected to async_mmap port `in_2.read_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_dout` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_dout` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_read_data_peek_dout` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_read_data_peek_dout` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_empty_n` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_empty_n` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_read_data_peek_empty_n` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_read_data_peek_empty_n` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_read` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_read_data_s_read` is connected to async_mmap port `in_2.read_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_din` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_din` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_full_n` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_full_n` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_write` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_addr_write` is connected to async_mmap port `in_2.write_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_din` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_din` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_full_n` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_full_n` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_write` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_data_write` is connected to async_mmap port `in_2.write_data` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_dout` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_dout` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_write_resp_peek_dout` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_write_resp_peek_dout` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_empty_n` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_empty_n` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_write_resp_peek_empty_n` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.a_write_resp_peek_empty_n` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_read` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.a_write_resp_s_read` is connected to async_mmap port `in_2.write_resp` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_din` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.684 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_din` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_full_n` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_full_n` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_write` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_addr_write` is connected to async_mmap port `out_2.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_dout` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_dout` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_read_data_peek_dout` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_read_data_peek_dout` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_empty_n` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_empty_n` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_read_data_peek_empty_n` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_read_data_peek_empty_n` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_read` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_read_data_s_read` is connected to async_mmap port `out_2.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_din` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_din` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_full_n` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_full_n` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_write` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_addr_write` is connected to async_mmap port `out_2.write_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_din` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_din` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_full_n` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_full_n` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_write` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_data_write` is connected to async_mmap port `out_2.write_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_dout` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_dout` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_write_resp_peek_dout` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_write_resp_peek_dout` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_empty_n` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_empty_n` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_write_resp_peek_empty_n` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_2.b_write_resp_peek_empty_n` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_read` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_2.b_write_resp_s_read` is connected to async_mmap port `out_2.write_resp` -D0712 20:03:04.685 tapa.core:671] pipelined signal: in_3 => inter_kernel_3___in_3 -D0712 20:03:04.685 tapa.core:671] pipelined signal: in_3 => inter_kernel_3___in_3 -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_din` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_din` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_full_n` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_full_n` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_write` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_write` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_dout` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_dout` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_read_data_peek_dout` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.685 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_read_data_peek_dout` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_empty_n` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_empty_n` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_read_data_peek_empty_n` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_read_data_peek_empty_n` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_read` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_read` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_din` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_din` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_full_n` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_full_n` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_write` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_write` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_din` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_din` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_full_n` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_full_n` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_write` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_write` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_dout` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_dout` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_write_resp_peek_dout` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_write_resp_peek_dout` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_empty_n` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_empty_n` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_write_resp_peek_empty_n` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_write_resp_peek_empty_n` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_read` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_read` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.686 tapa.core:671] pipelined signal: iters => inter_kernel_3___iters -D0712 20:03:04.686 tapa.core:671] pipelined signal: iters => inter_kernel_3___iters -D0712 20:03:04.686 tapa.core:671] pipelined signal: out_3 => inter_kernel_3___out_3 -D0712 20:03:04.686 tapa.core:671] pipelined signal: out_3 => inter_kernel_3___out_3 -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_din` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_din` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_full_n` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_full_n` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_write` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_write` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_dout` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_dout` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_read_data_peek_dout` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_read_data_peek_dout` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_empty_n` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.686 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_empty_n` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_read_data_peek_empty_n` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_read_data_peek_empty_n` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_read` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_read` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_din` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_din` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_full_n` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_full_n` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_write` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_write` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_din` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_din` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_full_n` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_full_n` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_write` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_write` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_dout` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_dout` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_write_resp_peek_dout` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_write_resp_peek_dout` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_empty_n` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_empty_n` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_write_resp_peek_empty_n` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_write_resp_peek_empty_n` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_read` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_read` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_din` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_din` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_full_n` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_full_n` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_write` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_addr_write` is connected to async_mmap port `in_3.read_addr` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_dout` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_dout` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_read_data_peek_dout` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.687 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_read_data_peek_dout` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_empty_n` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_empty_n` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_read_data_peek_empty_n` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_read_data_peek_empty_n` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_read` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_read_data_s_read` is connected to async_mmap port `in_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_din` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_din` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_full_n` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_full_n` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_write` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_addr_write` is connected to async_mmap port `in_3.write_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_din` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_din` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_full_n` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_full_n` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_write` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_data_write` is connected to async_mmap port `in_3.write_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_dout` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_dout` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_write_resp_peek_dout` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_write_resp_peek_dout` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_empty_n` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_empty_n` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_write_resp_peek_empty_n` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.a_write_resp_peek_empty_n` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_read` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.a_write_resp_s_read` is connected to async_mmap port `in_3.write_resp` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_din` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_din` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_full_n` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_full_n` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_write` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_addr_write` is connected to async_mmap port `out_3.read_addr` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_dout` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_dout` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_read_data_peek_dout` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_read_data_peek_dout` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_empty_n` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.688 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_empty_n` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_read_data_peek_empty_n` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_read_data_peek_empty_n` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_read` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_read_data_s_read` is connected to async_mmap port `out_3.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_din` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_din` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_full_n` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_full_n` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_write` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_addr_write` is connected to async_mmap port `out_3.write_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_din` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_din` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_full_n` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_full_n` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_write` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_data_write` is connected to async_mmap port `out_3.write_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_dout` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_dout` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_write_resp_peek_dout` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_write_resp_peek_dout` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_empty_n` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_empty_n` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_write_resp_peek_empty_n` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_3.b_write_resp_peek_empty_n` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_read` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_3.b_write_resp_s_read` is connected to async_mmap port `out_3.write_resp` -D0712 20:03:04.689 tapa.core:671] pipelined signal: in_4 => inter_kernel_4___in_4 -D0712 20:03:04.689 tapa.core:671] pipelined signal: in_4 => inter_kernel_4___in_4 -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_din` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_din` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_full_n` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_full_n` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_write` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_write` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_dout` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_dout` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_read_data_peek_dout` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_read_data_peek_dout` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_empty_n` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_empty_n` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_read_data_peek_empty_n` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_read_data_peek_empty_n` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_read` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_read` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_din` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.689 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_din` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_full_n` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_full_n` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_write` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_write` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_din` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_din` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_full_n` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_full_n` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_write` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_write` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_dout` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_dout` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_write_resp_peek_dout` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_write_resp_peek_dout` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_empty_n` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_empty_n` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_write_resp_peek_empty_n` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_write_resp_peek_empty_n` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_read` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_read` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.690 tapa.core:671] pipelined signal: iters => inter_kernel_4___iters -D0712 20:03:04.690 tapa.core:671] pipelined signal: iters => inter_kernel_4___iters -D0712 20:03:04.690 tapa.core:671] pipelined signal: out_4 => inter_kernel_4___out_4 -D0712 20:03:04.690 tapa.core:671] pipelined signal: out_4 => inter_kernel_4___out_4 -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_din` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_din` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_full_n` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_full_n` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_write` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_write` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_dout` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_dout` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_read_data_peek_dout` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_read_data_peek_dout` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_empty_n` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_empty_n` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_read_data_peek_empty_n` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_read_data_peek_empty_n` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_read` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_read` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_din` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_din` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_full_n` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.690 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_full_n` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_write` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_write` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_din` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_din` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_full_n` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_full_n` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_write` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_write` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_dout` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_dout` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_write_resp_peek_dout` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_write_resp_peek_dout` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_empty_n` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_empty_n` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_write_resp_peek_empty_n` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_write_resp_peek_empty_n` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_read` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_read` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_din` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_din` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_full_n` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_full_n` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_write` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_addr_write` is connected to async_mmap port `in_4.read_addr` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_dout` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_dout` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_read_data_peek_dout` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_read_data_peek_dout` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_empty_n` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_empty_n` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_read_data_peek_empty_n` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_read_data_peek_empty_n` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_read` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_read_data_s_read` is connected to async_mmap port `in_4.read_data` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_din` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.691 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_din` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_full_n` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_full_n` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_write` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_addr_write` is connected to async_mmap port `in_4.write_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_din` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_din` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_full_n` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_full_n` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_write` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_data_write` is connected to async_mmap port `in_4.write_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_dout` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_dout` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_write_resp_peek_dout` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_write_resp_peek_dout` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_empty_n` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_empty_n` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_write_resp_peek_empty_n` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.a_write_resp_peek_empty_n` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_read` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.a_write_resp_s_read` is connected to async_mmap port `in_4.write_resp` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_din` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_din` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_full_n` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_full_n` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_write` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_addr_write` is connected to async_mmap port `out_4.read_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_dout` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_dout` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_read_data_peek_dout` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_read_data_peek_dout` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_empty_n` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_empty_n` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_read_data_peek_empty_n` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_read_data_peek_empty_n` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_read` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_read_data_s_read` is connected to async_mmap port `out_4.read_data` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_din` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_din` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_full_n` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.692 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_full_n` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_write` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_addr_write` is connected to async_mmap port `out_4.write_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_din` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_din` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_full_n` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_full_n` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_write` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_data_write` is connected to async_mmap port `out_4.write_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_dout` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_dout` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_write_resp_peek_dout` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_write_resp_peek_dout` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_empty_n` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_empty_n` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_write_resp_peek_empty_n` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_4.b_write_resp_peek_empty_n` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_read` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_4.b_write_resp_s_read` is connected to async_mmap port `out_4.write_resp` -D0712 20:03:04.693 tapa.core:671] pipelined signal: in_5 => inter_kernel_5___in_5 -D0712 20:03:04.693 tapa.core:671] pipelined signal: in_5 => inter_kernel_5___in_5 -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_din` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_din` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_full_n` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_full_n` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_write` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_write` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_dout` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_dout` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_read_data_peek_dout` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_read_data_peek_dout` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_empty_n` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_empty_n` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_read_data_peek_empty_n` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_read_data_peek_empty_n` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_read` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_read` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_din` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_din` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_full_n` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_full_n` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_write` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_write` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_din` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_din` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_full_n` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.693 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_full_n` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_write` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_write` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_dout` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_dout` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_write_resp_peek_dout` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_write_resp_peek_dout` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_empty_n` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_empty_n` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_write_resp_peek_empty_n` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_write_resp_peek_empty_n` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_read` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_read` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.694 tapa.core:671] pipelined signal: iters => inter_kernel_5___iters -D0712 20:03:04.694 tapa.core:671] pipelined signal: iters => inter_kernel_5___iters -D0712 20:03:04.694 tapa.core:671] pipelined signal: out_5 => inter_kernel_5___out_5 -D0712 20:03:04.694 tapa.core:671] pipelined signal: out_5 => inter_kernel_5___out_5 -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_din` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_din` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_full_n` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_full_n` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_write` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_write` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_dout` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_dout` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_read_data_peek_dout` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_read_data_peek_dout` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_empty_n` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_empty_n` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_read_data_peek_empty_n` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_read_data_peek_empty_n` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_read` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_read` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_din` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_din` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_full_n` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_full_n` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_write` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_write` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_din` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_din` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_full_n` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_full_n` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_write` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.694 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_write` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_dout` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_dout` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_write_resp_peek_dout` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_write_resp_peek_dout` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_empty_n` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_empty_n` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_write_resp_peek_empty_n` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_write_resp_peek_empty_n` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_read` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_read` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_din` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_din` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_full_n` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_full_n` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_write` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_addr_write` is connected to async_mmap port `in_5.read_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_dout` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_dout` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_read_data_peek_dout` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_read_data_peek_dout` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_empty_n` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_empty_n` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_read_data_peek_empty_n` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_read_data_peek_empty_n` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_read` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_read_data_s_read` is connected to async_mmap port `in_5.read_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_din` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_din` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_full_n` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_full_n` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_write` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_addr_write` is connected to async_mmap port `in_5.write_addr` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_din` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.695 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_din` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_full_n` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_full_n` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_write` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_data_write` is connected to async_mmap port `in_5.write_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_dout` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_dout` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_write_resp_peek_dout` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_write_resp_peek_dout` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_empty_n` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_empty_n` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_write_resp_peek_empty_n` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.a_write_resp_peek_empty_n` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_read` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.a_write_resp_s_read` is connected to async_mmap port `in_5.write_resp` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_din` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_din` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_full_n` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_full_n` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_write` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_addr_write` is connected to async_mmap port `out_5.read_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_dout` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_dout` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_read_data_peek_dout` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_read_data_peek_dout` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_empty_n` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_empty_n` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_read_data_peek_empty_n` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_read_data_peek_empty_n` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_read` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_read_data_s_read` is connected to async_mmap port `out_5.read_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_din` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_din` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_full_n` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_full_n` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_write` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_addr_write` is connected to async_mmap port `out_5.write_addr` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_din` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_din` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_full_n` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.696 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_full_n` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_write` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_data_write` is connected to async_mmap port `out_5.write_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_dout` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_dout` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_write_resp_peek_dout` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_write_resp_peek_dout` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_empty_n` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_empty_n` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_write_resp_peek_empty_n` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_5.b_write_resp_peek_empty_n` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_read` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_5.b_write_resp_s_read` is connected to async_mmap port `out_5.write_resp` -D0712 20:03:04.697 tapa.core:671] pipelined signal: in_6 => inter_kernel_6___in_6 -D0712 20:03:04.697 tapa.core:671] pipelined signal: in_6 => inter_kernel_6___in_6 -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_din` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_din` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_full_n` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_full_n` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_write` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_write` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_dout` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_dout` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_read_data_peek_dout` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_read_data_peek_dout` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_empty_n` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_empty_n` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_read_data_peek_empty_n` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_read_data_peek_empty_n` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_read` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_read` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_din` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_din` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_full_n` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_full_n` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_write` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_write` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_din` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_din` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_full_n` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_full_n` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_write` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_write` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_dout` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_dout` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_write_resp_peek_dout` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_write_resp_peek_dout` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_empty_n` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.697 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_empty_n` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_write_resp_peek_empty_n` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_write_resp_peek_empty_n` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_read` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_read` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.698 tapa.core:671] pipelined signal: iters => inter_kernel_6___iters -D0712 20:03:04.698 tapa.core:671] pipelined signal: iters => inter_kernel_6___iters -D0712 20:03:04.698 tapa.core:671] pipelined signal: out_6 => inter_kernel_6___out_6 -D0712 20:03:04.698 tapa.core:671] pipelined signal: out_6 => inter_kernel_6___out_6 -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_din` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_din` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_full_n` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_full_n` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_write` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_write` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_dout` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_dout` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_read_data_peek_dout` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_read_data_peek_dout` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_empty_n` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_empty_n` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_read_data_peek_empty_n` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_read_data_peek_empty_n` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_read` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_read` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_din` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_din` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_full_n` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_full_n` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_write` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_write` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_din` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_din` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_full_n` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_full_n` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_write` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_write` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_dout` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_dout` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_write_resp_peek_dout` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_write_resp_peek_dout` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_empty_n` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_empty_n` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_write_resp_peek_empty_n` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.698 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_write_resp_peek_empty_n` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_read` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_read` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_din` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_din` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_full_n` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_full_n` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_write` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_addr_write` is connected to async_mmap port `in_6.read_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_dout` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_dout` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_read_data_peek_dout` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_read_data_peek_dout` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_empty_n` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_empty_n` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_read_data_peek_empty_n` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_read_data_peek_empty_n` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_read` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_read_data_s_read` is connected to async_mmap port `in_6.read_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_din` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_din` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_full_n` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_full_n` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_write` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_addr_write` is connected to async_mmap port `in_6.write_addr` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_din` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_din` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_full_n` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_full_n` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_write` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_data_write` is connected to async_mmap port `in_6.write_data` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_dout` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_dout` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_write_resp_peek_dout` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.699 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_write_resp_peek_dout` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_empty_n` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_empty_n` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_write_resp_peek_empty_n` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.a_write_resp_peek_empty_n` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_read` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.a_write_resp_s_read` is connected to async_mmap port `in_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_din` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_din` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_full_n` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_full_n` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_write` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_addr_write` is connected to async_mmap port `out_6.read_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_dout` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_dout` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_read_data_peek_dout` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_read_data_peek_dout` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_empty_n` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_empty_n` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_read_data_peek_empty_n` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_read_data_peek_empty_n` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_read` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_read_data_s_read` is connected to async_mmap port `out_6.read_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_din` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_din` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_full_n` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_full_n` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_write` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_addr_write` is connected to async_mmap port `out_6.write_addr` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_din` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_din` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_full_n` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_full_n` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_write` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_data_write` is connected to async_mmap port `out_6.write_data` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_dout` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_dout` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_write_resp_peek_dout` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_write_resp_peek_dout` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_empty_n` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.700 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_empty_n` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_write_resp_peek_empty_n` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_6.b_write_resp_peek_empty_n` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_read` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_6.b_write_resp_s_read` is connected to async_mmap port `out_6.write_resp` -D0712 20:03:04.701 tapa.core:671] pipelined signal: in_7 => inter_kernel_7___in_7 -D0712 20:03:04.701 tapa.core:671] pipelined signal: in_7 => inter_kernel_7___in_7 -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_din` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_din` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_full_n` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_full_n` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_write` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_write` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_dout` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_dout` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_read_data_peek_dout` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_read_data_peek_dout` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_empty_n` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_empty_n` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_read_data_peek_empty_n` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_read_data_peek_empty_n` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_read` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_read` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_din` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_din` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_full_n` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_full_n` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_write` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_write` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_din` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_din` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_full_n` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_full_n` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_write` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_write` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_dout` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_dout` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_write_resp_peek_dout` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_write_resp_peek_dout` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_empty_n` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_empty_n` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_write_resp_peek_empty_n` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_write_resp_peek_empty_n` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_read` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.701 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_read` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.702 tapa.core:671] pipelined signal: iters => inter_kernel_7___iters -D0712 20:03:04.702 tapa.core:671] pipelined signal: iters => inter_kernel_7___iters -D0712 20:03:04.702 tapa.core:671] pipelined signal: out_7 => inter_kernel_7___out_7 -D0712 20:03:04.702 tapa.core:671] pipelined signal: out_7 => inter_kernel_7___out_7 -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_din` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_din` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_full_n` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_full_n` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_write` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_write` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_dout` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_dout` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_read_data_peek_dout` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_read_data_peek_dout` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_empty_n` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_empty_n` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_read_data_peek_empty_n` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_read_data_peek_empty_n` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_read` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_read` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_din` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_din` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_full_n` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_full_n` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_write` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_write` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_din` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_din` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_full_n` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_full_n` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_write` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_write` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_dout` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_dout` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_write_resp_peek_dout` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_write_resp_peek_dout` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_empty_n` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_empty_n` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_write_resp_peek_empty_n` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_write_resp_peek_empty_n` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_read` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.702 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_read` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_din` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_din` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_full_n` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_full_n` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_write` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_addr_write` is connected to async_mmap port `in_7.read_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_dout` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_dout` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_read_data_peek_dout` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_read_data_peek_dout` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_empty_n` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_empty_n` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_read_data_peek_empty_n` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_read_data_peek_empty_n` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_read` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_read_data_s_read` is connected to async_mmap port `in_7.read_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_din` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_din` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_full_n` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_full_n` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_write` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_addr_write` is connected to async_mmap port `in_7.write_addr` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_din` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_din` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_full_n` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_full_n` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_write` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_data_write` is connected to async_mmap port `in_7.write_data` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_dout` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_dout` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_write_resp_peek_dout` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_write_resp_peek_dout` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_empty_n` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_empty_n` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_write_resp_peek_empty_n` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.a_write_resp_peek_empty_n` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_read` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.703 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.a_write_resp_s_read` is connected to async_mmap port `in_7.write_resp` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_din` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_din` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_full_n` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_full_n` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_write` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_addr_write` is connected to async_mmap port `out_7.read_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_dout` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_dout` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_read_data_peek_dout` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_read_data_peek_dout` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_empty_n` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_empty_n` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_read_data_peek_empty_n` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_read_data_peek_empty_n` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_read` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_read_data_s_read` is connected to async_mmap port `out_7.read_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_din` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_din` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_full_n` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_full_n` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_write` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_addr_write` is connected to async_mmap port `out_7.write_addr` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_din` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_din` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_full_n` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_full_n` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_write` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_data_write` is connected to async_mmap port `out_7.write_data` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_dout` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_dout` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_write_resp_peek_dout` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_write_resp_peek_dout` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_empty_n` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_empty_n` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_write_resp_peek_empty_n` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_7.b_write_resp_peek_empty_n` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_read` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.704 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_7.b_write_resp_s_read` is connected to async_mmap port `out_7.write_resp` -D0712 20:03:04.705 tapa.core:671] pipelined signal: in_8 => inter_kernel_8___in_8 -D0712 20:03:04.705 tapa.core:671] pipelined signal: in_8 => inter_kernel_8___in_8 -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_din` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_din` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_full_n` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_full_n` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_write` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_write` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_dout` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_dout` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_read_data_peek_dout` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_read_data_peek_dout` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_empty_n` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_empty_n` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_read_data_peek_empty_n` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_read_data_peek_empty_n` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_read` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_read` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_din` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_din` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_full_n` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_full_n` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_write` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_write` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_din` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_din` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_full_n` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_full_n` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_write` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_write` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_dout` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_dout` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_write_resp_peek_dout` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_write_resp_peek_dout` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_empty_n` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_empty_n` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_write_resp_peek_empty_n` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_write_resp_peek_empty_n` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_read` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.705 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_read` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.706 tapa.core:671] pipelined signal: iters => inter_kernel_8___iters -D0712 20:03:04.706 tapa.core:671] pipelined signal: iters => inter_kernel_8___iters -D0712 20:03:04.706 tapa.core:671] pipelined signal: out_8 => inter_kernel_8___out_8 -D0712 20:03:04.706 tapa.core:671] pipelined signal: out_8 => inter_kernel_8___out_8 -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_din` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_din` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_full_n` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_full_n` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_write` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_write` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_dout` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_dout` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_read_data_peek_dout` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_read_data_peek_dout` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_empty_n` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_empty_n` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_read_data_peek_empty_n` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_read_data_peek_empty_n` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_read` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_read` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_din` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_din` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_full_n` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_full_n` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_write` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_write` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_din` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_din` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_full_n` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_full_n` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_write` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_write` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_dout` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_dout` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_write_resp_peek_dout` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_write_resp_peek_dout` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_empty_n` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_empty_n` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_write_resp_peek_empty_n` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_write_resp_peek_empty_n` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_read` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.706 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_read` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_din` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_din` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_full_n` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_full_n` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_write` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_addr_write` is connected to async_mmap port `in_8.read_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_dout` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_dout` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_read_data_peek_dout` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_read_data_peek_dout` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_empty_n` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_empty_n` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_read_data_peek_empty_n` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_read_data_peek_empty_n` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_read` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_read_data_s_read` is connected to async_mmap port `in_8.read_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_din` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_din` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_full_n` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_full_n` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_write` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_addr_write` is connected to async_mmap port `in_8.write_addr` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_din` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_din` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_full_n` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_full_n` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_write` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_data_write` is connected to async_mmap port `in_8.write_data` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_dout` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_dout` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_write_resp_peek_dout` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_write_resp_peek_dout` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_empty_n` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_empty_n` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_write_resp_peek_empty_n` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.a_write_resp_peek_empty_n` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_read` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.707 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.a_write_resp_s_read` is connected to async_mmap port `in_8.write_resp` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_din` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_din` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_full_n` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_full_n` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_write` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_addr_write` is connected to async_mmap port `out_8.read_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_dout` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_dout` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_read_data_peek_dout` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_read_data_peek_dout` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_empty_n` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_empty_n` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_read_data_peek_empty_n` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_read_data_peek_empty_n` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_read` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_read_data_s_read` is connected to async_mmap port `out_8.read_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_din` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_din` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_full_n` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_full_n` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_write` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_addr_write` is connected to async_mmap port `out_8.write_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_din` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_din` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_full_n` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_full_n` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_write` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_data_write` is connected to async_mmap port `out_8.write_data` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_dout` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_dout` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_write_resp_peek_dout` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_write_resp_peek_dout` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_empty_n` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_empty_n` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_write_resp_peek_empty_n` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_8.b_write_resp_peek_empty_n` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_read` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_8.b_write_resp_s_read` is connected to async_mmap port `out_8.write_resp` -D0712 20:03:04.708 tapa.core:671] pipelined signal: in_9 => inter_kernel_9___in_9 -D0712 20:03:04.708 tapa.core:671] pipelined signal: in_9 => inter_kernel_9___in_9 -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_din` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.708 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_din` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_full_n` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_full_n` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_write` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_write` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_dout` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_dout` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_read_data_peek_dout` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_read_data_peek_dout` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_empty_n` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_empty_n` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_read_data_peek_empty_n` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_read_data_peek_empty_n` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_read` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_read` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_din` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_din` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_full_n` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_full_n` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_write` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_write` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_din` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_din` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_full_n` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_full_n` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_write` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_write` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_dout` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_dout` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_write_resp_peek_dout` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_write_resp_peek_dout` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_empty_n` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_empty_n` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_write_resp_peek_empty_n` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_write_resp_peek_empty_n` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_read` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_read` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.709 tapa.core:671] pipelined signal: iters => inter_kernel_9___iters -D0712 20:03:04.709 tapa.core:671] pipelined signal: iters => inter_kernel_9___iters -D0712 20:03:04.709 tapa.core:671] pipelined signal: out_9 => inter_kernel_9___out_9 -D0712 20:03:04.709 tapa.core:671] pipelined signal: out_9 => inter_kernel_9___out_9 -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_din` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.709 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_din` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_full_n` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_full_n` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_write` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_write` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_dout` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_dout` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_read_data_peek_dout` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_read_data_peek_dout` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_empty_n` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_empty_n` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_read_data_peek_empty_n` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_read_data_peek_empty_n` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_read` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_read` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_din` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_din` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_full_n` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_full_n` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_write` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_write` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_din` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_din` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_full_n` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_full_n` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_write` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_write` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_dout` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_dout` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_write_resp_peek_dout` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_write_resp_peek_dout` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_empty_n` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_empty_n` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_write_resp_peek_empty_n` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_write_resp_peek_empty_n` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_read` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.710 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_read` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_din` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_din` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_full_n` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_full_n` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_write` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_addr_write` is connected to async_mmap port `in_9.read_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_dout` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_dout` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_read_data_peek_dout` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_read_data_peek_dout` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_empty_n` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_empty_n` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_read_data_peek_empty_n` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_read_data_peek_empty_n` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_read` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_read_data_s_read` is connected to async_mmap port `in_9.read_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_din` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_din` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_full_n` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_full_n` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_write` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_addr_write` is connected to async_mmap port `in_9.write_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_din` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_din` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_full_n` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_full_n` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_write` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_data_write` is connected to async_mmap port `in_9.write_data` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_dout` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_dout` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_write_resp_peek_dout` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_write_resp_peek_dout` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_empty_n` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_empty_n` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_write_resp_peek_empty_n` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.a_write_resp_peek_empty_n` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_read` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.a_write_resp_s_read` is connected to async_mmap port `in_9.write_resp` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_din` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.711 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_din` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_full_n` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_full_n` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_write` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_addr_write` is connected to async_mmap port `out_9.read_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_dout` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_dout` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_read_data_peek_dout` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_read_data_peek_dout` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_empty_n` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_empty_n` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_read_data_peek_empty_n` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_read_data_peek_empty_n` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_read` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_read_data_s_read` is connected to async_mmap port `out_9.read_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_din` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_din` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_full_n` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_full_n` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_write` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_addr_write` is connected to async_mmap port `out_9.write_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_din` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_din` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_full_n` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_full_n` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_write` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_data_write` is connected to async_mmap port `out_9.write_data` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_dout` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_dout` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_write_resp_peek_dout` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_write_resp_peek_dout` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_empty_n` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_empty_n` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_write_resp_peek_empty_n` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_9.b_write_resp_peek_empty_n` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_read` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_9.b_write_resp_s_read` is connected to async_mmap port `out_9.write_resp` -D0712 20:03:04.712 tapa.core:671] pipelined signal: in_10 => inter_kernel_10___in_10 -D0712 20:03:04.712 tapa.core:671] pipelined signal: in_10 => inter_kernel_10___in_10 -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_din` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_din` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_full_n` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_full_n` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_write` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.712 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_write` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_dout` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_dout` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_read_data_peek_dout` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_read_data_peek_dout` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_empty_n` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_empty_n` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_read_data_peek_empty_n` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_read_data_peek_empty_n` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_read` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_read` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_din` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_din` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_full_n` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_full_n` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_write` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_write` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_din` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_din` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_full_n` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_full_n` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_write` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_write` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_dout` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_dout` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_write_resp_peek_dout` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_write_resp_peek_dout` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_empty_n` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_empty_n` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_write_resp_peek_empty_n` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_write_resp_peek_empty_n` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_read` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_read` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.713 tapa.core:671] pipelined signal: iters => inter_kernel_10___iters -D0712 20:03:04.713 tapa.core:671] pipelined signal: iters => inter_kernel_10___iters -D0712 20:03:04.713 tapa.core:671] pipelined signal: out_10 => inter_kernel_10___out_10 -D0712 20:03:04.713 tapa.core:671] pipelined signal: out_10 => inter_kernel_10___out_10 -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_din` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_din` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_full_n` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.713 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_full_n` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_write` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_write` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_dout` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_dout` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_read_data_peek_dout` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_read_data_peek_dout` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_empty_n` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_empty_n` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_read_data_peek_empty_n` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_read_data_peek_empty_n` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_read` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_read` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_din` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_din` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_full_n` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_full_n` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_write` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_write` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_din` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_din` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_full_n` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_full_n` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_write` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_write` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_dout` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_dout` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_write_resp_peek_dout` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_write_resp_peek_dout` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_empty_n` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_empty_n` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_write_resp_peek_empty_n` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_write_resp_peek_empty_n` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_read` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.714 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_read` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_din` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_din` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_full_n` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_full_n` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_write` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_addr_write` is connected to async_mmap port `in_10.read_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_dout` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_dout` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_read_data_peek_dout` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_read_data_peek_dout` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_empty_n` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_empty_n` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_read_data_peek_empty_n` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_read_data_peek_empty_n` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_read` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_read_data_s_read` is connected to async_mmap port `in_10.read_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_din` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_din` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_full_n` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_full_n` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_write` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_addr_write` is connected to async_mmap port `in_10.write_addr` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_din` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_din` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_full_n` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_full_n` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_write` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_data_write` is connected to async_mmap port `in_10.write_data` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_dout` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_dout` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_write_resp_peek_dout` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_write_resp_peek_dout` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_empty_n` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_empty_n` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_write_resp_peek_empty_n` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.a_write_resp_peek_empty_n` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_read` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.715 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.a_write_resp_s_read` is connected to async_mmap port `in_10.write_resp` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_din` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_din` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_full_n` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_full_n` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_write` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_addr_write` is connected to async_mmap port `out_10.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_dout` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_dout` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_read_data_peek_dout` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_read_data_peek_dout` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_empty_n` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_empty_n` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_read_data_peek_empty_n` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_read_data_peek_empty_n` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_read` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_read_data_s_read` is connected to async_mmap port `out_10.read_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_din` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_din` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_full_n` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_full_n` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_write` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_addr_write` is connected to async_mmap port `out_10.write_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_din` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_din` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_full_n` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_full_n` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_write` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_data_write` is connected to async_mmap port `out_10.write_data` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_dout` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_dout` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_write_resp_peek_dout` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_write_resp_peek_dout` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_empty_n` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_empty_n` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_write_resp_peek_empty_n` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_10.b_write_resp_peek_empty_n` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_read` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_10.b_write_resp_s_read` is connected to async_mmap port `out_10.write_resp` -D0712 20:03:04.716 tapa.core:671] pipelined signal: in_11 => inter_kernel_11___in_11 -D0712 20:03:04.716 tapa.core:671] pipelined signal: in_11 => inter_kernel_11___in_11 -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_din` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_din` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_full_n` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_full_n` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_write` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.716 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_write` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_dout` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_dout` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_read_data_peek_dout` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_read_data_peek_dout` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_empty_n` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_empty_n` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_read_data_peek_empty_n` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_read_data_peek_empty_n` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_read` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_read` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_din` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_din` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_full_n` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_full_n` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_write` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_write` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_din` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_din` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_full_n` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_full_n` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_write` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_write` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_dout` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_dout` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_write_resp_peek_dout` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_write_resp_peek_dout` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_empty_n` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_empty_n` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_write_resp_peek_empty_n` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_write_resp_peek_empty_n` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_read` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_read` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.717 tapa.core:671] pipelined signal: iters => inter_kernel_11___iters -D0712 20:03:04.717 tapa.core:671] pipelined signal: iters => inter_kernel_11___iters -D0712 20:03:04.717 tapa.core:671] pipelined signal: out_11 => inter_kernel_11___out_11 -D0712 20:03:04.717 tapa.core:671] pipelined signal: out_11 => inter_kernel_11___out_11 -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_din` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_din` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_full_n` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_full_n` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_write` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.717 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_write` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_dout` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_dout` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_read_data_peek_dout` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_read_data_peek_dout` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_empty_n` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_empty_n` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_read_data_peek_empty_n` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_read_data_peek_empty_n` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_read` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_read` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_din` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_din` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_full_n` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_full_n` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_write` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_write` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_din` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_din` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_full_n` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_full_n` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_write` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_write` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_dout` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_dout` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_write_resp_peek_dout` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_write_resp_peek_dout` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_empty_n` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_empty_n` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_write_resp_peek_empty_n` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_write_resp_peek_empty_n` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_read` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_read` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_din` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.718 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_din` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_full_n` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_full_n` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_write` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_addr_write` is connected to async_mmap port `in_11.read_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_dout` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_dout` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_read_data_peek_dout` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_read_data_peek_dout` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_empty_n` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_empty_n` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_read_data_peek_empty_n` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_read_data_peek_empty_n` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_read` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_read_data_s_read` is connected to async_mmap port `in_11.read_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_din` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_din` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_full_n` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_full_n` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_write` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_addr_write` is connected to async_mmap port `in_11.write_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_din` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_din` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_full_n` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_full_n` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_write` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_data_write` is connected to async_mmap port `in_11.write_data` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_dout` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_dout` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_write_resp_peek_dout` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_write_resp_peek_dout` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_empty_n` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_empty_n` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_write_resp_peek_empty_n` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.a_write_resp_peek_empty_n` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_read` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.a_write_resp_s_read` is connected to async_mmap port `in_11.write_resp` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_din` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_din` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_full_n` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_full_n` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_write` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.719 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_addr_write` is connected to async_mmap port `out_11.read_addr` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_dout` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_dout` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_read_data_peek_dout` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_read_data_peek_dout` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_empty_n` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_empty_n` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_read_data_peek_empty_n` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_read_data_peek_empty_n` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_read` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_read_data_s_read` is connected to async_mmap port `out_11.read_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_din` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_din` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_full_n` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_full_n` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_write` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_addr_write` is connected to async_mmap port `out_11.write_addr` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_din` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_din` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_full_n` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_full_n` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_write` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_data_write` is connected to async_mmap port `out_11.write_data` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_dout` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_dout` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_write_resp_peek_dout` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_write_resp_peek_dout` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_empty_n` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_empty_n` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_write_resp_peek_empty_n` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:81] `inter_kernel_11.b_write_resp_peek_empty_n` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_read` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.720 tapa.verilog.xilinx.async_mmap:71] `inter_kernel_11.b_write_resp_s_read` is connected to async_mmap port `out_11.write_resp` -D0712 20:03:04.720 tapa.core:852] Set the address width of async_mmap to 64 -D0712 20:03:04.720 tapa.core:852] Set the address width of async_mmap to 64 -I0712 20:03:04.854 tapa.core:465] generating report -I0712 20:03:04.854 tapa.core:465] generating report -I0712 20:03:04.855 tapa.core:473] writing generated auxiliary RTL files -I0712 20:03:04.855 tapa.core:473] writing generated auxiliary RTL files -I0712 20:03:04.855 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 20:03:04.855 tapa.steps.common:92] writing TAPA settings to json `generated/settings.json`. -I0712 20:03:04.856 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 20:03:04.856 tapa.steps.common:46] reusing TAPA settings from upstream flows. -I0712 20:03:04.856 tapa.core:481] packaging RTL code -I0712 20:03:04.856 tapa.core:481] packaging RTL code -D0712 20:03:04.856 tapa.verilog.xilinx:70] RTL ports of unikernel: -D0712 20:03:04.856 tapa.verilog.xilinx:70] RTL ports of unikernel: -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_0, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_0, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_0, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_0, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_1, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_1, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_1, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_1, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_2, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_2, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_2, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_2, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_3, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_3, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_3, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_3, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_4, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_4, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_4, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_4, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_5, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_5, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_5, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_5, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_6, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_6, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_6, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_6, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_7, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_7, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_7, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_7, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_8, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_8, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_8, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_8, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_9, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_9, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_9, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_9, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_10, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_10, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_10, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_10, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_11, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: in_11, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_11, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.MMAP, name: out_11, ctype: ap_uint<512>*, width: 512, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: iters, ctype: uint32_t, width: 32, chan_count: None, chan_size: None -D0712 20:03:04.856 tapa.verilog.xilinx:75] cat: Cat.SCALAR, name: iters, ctype: uint32_t, width: 32, chan_count: None, chan_size: None -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_crossbar_addr.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_crossbar_addr.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: fifo.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: fifo.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip.tcl -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0_ip.tcl -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: arbiter.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: arbiter.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: detect_burst.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: detect_burst.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip.tcl -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0_ip.tcl -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_121_4.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_121_4.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fifo_w512_d15_A.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fifo_w512_d15_A.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: inter_kernel_flow_control_loop_pipe_sequential_init.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: inter_kernel_flow_control_loop_pipe_sequential_init.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: unikernel_fsm.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: unikernel_fsm.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: async_mmap.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: async_mmap.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fsub_32ns_32ns_32_7_full_dsp_0.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_Pipeline_MAJOR_LOOP.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_Pipeline_MAJOR_LOOP.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip.tcl -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0_ip.tcl -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: fifo_srl.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: fifo_srl.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_3.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_3.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_register_rd.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_register_rd.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_crossbar_rd.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_crossbar_rd.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fadd_32ns_32ns_32_7_full_dsp_0.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: fifo_bram.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: fifo_bram.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_stencil_kernel.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_stencil_kernel.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: inter_kernel.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: inter_kernel.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_crossbar_wr.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_crossbar_wr.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_68_2.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_68_2.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_crossbar.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_crossbar.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: unikernel_control_s_axi.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: unikernel_control_s_axi.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_pipeline.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_pipeline.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: relay_station.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: relay_station.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: fifo_fwd.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: fifo_fwd.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_116_3.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_116_3.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_flow_control_loop_pipe_sequential_init.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_flow_control_loop_pipe_sequential_init.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_4.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: a_axi_write_broadcastor_1_to_4.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_fmul_32ns_32ns_32_4_max_dsp_0.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: priority_encoder.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: priority_encoder.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: inter_kernel_load.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: inter_kernel_load.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: inter_kernel_load_Pipeline_VITIS_LOOP_45_1.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: inter_kernel_load_Pipeline_VITIS_LOOP_45_1.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HLS_REG_ap_uint_512_s.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HLS_REG_ap_uint_512_s.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_register_wr.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: axi_register_wr.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: unikernel.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: unikernel.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_62_1.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: HEAT3D_HEAT3D_Pipeline_VITIS_LOOP_62_1.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: generate_last.v -D0712 20:03:04.857 haoda.backend.xilinx:163] packing: generate_last.v -I0712 20:03:20.048 tapa.core:489] packaging HLS report -I0712 20:03:20.048 tapa.core:489] packaging HLS report -D0712 20:03:20.052 tapa.core:494] packing report/HEAT3D_Pipeline_MAJOR_LOOP_csynth.xml -D0712 20:03:20.052 tapa.core:494] packing report/HEAT3D_Pipeline_MAJOR_LOOP_csynth.xml -D0712 20:03:20.053 tapa.core:494] packing report/inter_kernel_csynth.xml -D0712 20:03:20.053 tapa.core:494] packing report/inter_kernel_csynth.xml -D0712 20:03:20.054 tapa.core:494] packing report/load_Pipeline_VITIS_LOOP_45_1_csynth.xml -D0712 20:03:20.054 tapa.core:494] packing report/load_Pipeline_VITIS_LOOP_45_1_csynth.xml -D0712 20:03:20.055 tapa.core:494] packing report/HLS_REG_ap_uint_512_s_csynth.xml -D0712 20:03:20.055 tapa.core:494] packing report/HLS_REG_ap_uint_512_s_csynth.xml -D0712 20:03:20.055 tapa.core:494] packing report/load_csynth.xml -D0712 20:03:20.055 tapa.core:494] packing report/load_csynth.xml -D0712 20:03:20.056 tapa.core:494] packing report/HEAT3D_stencil_kernel_csynth.xml -D0712 20:03:20.056 tapa.core:494] packing report/HEAT3D_stencil_kernel_csynth.xml -D0712 20:03:20.056 tapa.core:494] packing report/HEAT3D_csynth.xml -D0712 20:03:20.056 tapa.core:494] packing report/HEAT3D_csynth.xml -D0712 20:03:20.057 tapa.core:494] packing report/HEAT3D_Pipeline_VITIS_LOOP_116_3_csynth.xml -D0712 20:03:20.057 tapa.core:494] packing report/HEAT3D_Pipeline_VITIS_LOOP_116_3_csynth.xml -D0712 20:03:20.057 tapa.core:494] packing report/HEAT3D_Pipeline_VITIS_LOOP_121_4_csynth.xml -D0712 20:03:20.057 tapa.core:494] packing report/HEAT3D_Pipeline_VITIS_LOOP_121_4_csynth.xml -D0712 20:03:20.057 tapa.core:494] packing report/HEAT3D_Pipeline_VITIS_LOOP_68_2_csynth.xml -D0712 20:03:20.057 tapa.core:494] packing report/HEAT3D_Pipeline_VITIS_LOOP_68_2_csynth.xml -D0712 20:03:20.058 tapa.core:494] packing report/HEAT3D_Pipeline_VITIS_LOOP_62_1_csynth.xml -D0712 20:03:20.058 tapa.core:494] packing report/HEAT3D_Pipeline_VITIS_LOOP_62_1_csynth.xml -D0712 20:03:20.058 tapa.core:494] packing report/unikernel_csynth.xml -D0712 20:03:20.058 tapa.core:494] packing report/unikernel_csynth.xml -I0712 20:03:20.059 tapa.core:497] generated the v++ xo file at generated/unikernel.xo -I0712 20:03:20.059 tapa.core:497] generated the v++ xo file at generated/unikernel.xo diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report.json b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report.json deleted file mode 100644 index 5f15bf47..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report.json +++ /dev/null @@ -1,56 +0,0 @@ -{ - "area": { - "breakdown": { - "HEAT3D": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 480, - "FF": 85918, - "LUT": 40261, - "URAM": 0 - } - }, - "count": 12 - }, - "inter_kernel": { - "area": { - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 0, - "FF": 384, - "LUT": 846, - "URAM": 0 - } - }, - "count": 12 - } - }, - "source": "hls", - "total": { - "BRAM_18K": 0, - "DSP": 5760, - "FF": 1037378, - "LUT": 496460, - "URAM": 0 - } - }, - "name": "unikernel", - "performance": { - "clock_period": "2.431", - "critical_path": { - "HEAT3D": { - "clock_period": "2.431", - "source": "hls" - }, - "inter_kernel": { - "clock_period": "2.431", - "source": "hls" - } - }, - "source": "hls" - }, - "schema": "v0.0.20210922" -} diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report.yaml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report.yaml deleted file mode 100644 index 6d9b1f84..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report.yaml +++ /dev/null @@ -1,41 +0,0 @@ -schema: v0.0.20210922 -name: unikernel -performance: - source: hls - clock_period: '2.431' - critical_path: - HEAT3D: - source: hls - clock_period: '2.431' - inter_kernel: - source: hls - clock_period: '2.431' -area: - source: hls - total: - BRAM_18K: 0 - DSP: 5760 - FF: 1037378 - LUT: 496460 - URAM: 0 - breakdown: - HEAT3D: - count: 12 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 480 - FF: 85918 - LUT: 40261 - URAM: 0 - inter_kernel: - count: 12 - area: - source: hls - total: - BRAM_18K: 0 - DSP: 0 - FF: 384 - LUT: 846 - URAM: 0 diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D.sched.adb.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D.sched.adb.xml deleted file mode 100644 index 72a0ac82..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D.sched.adb.xml +++ /dev/null @@ -1,948 +0,0 @@ -HEAT3D - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -TAddSub - - - - - - - - - - - -TAddSub - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D.verbose.sched.rpt.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D.verbose.sched.rpt.xml deleted file mode 100644 index 02cc199d..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D.verbose.sched.rpt.xml +++ /dev/null @@ -1,45 +0,0 @@ - - -
-Fri Jul 12 20:03:01 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -HEAT3D (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
- -
- -
- -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
- -
- - -
- -, min, max, min, max, min, max, Type -?, ?, ?, ?, ?, ?, no -
- - -
- -Instance, Module, min, max, min, max, min, max, Type -
- - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -
- -
- -
- -
- diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_MAJOR_LOOP.sched.adb.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_MAJOR_LOOP.sched.adb.xml deleted file mode 100644 index 570bfac2..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_MAJOR_LOOP.sched.adb.xml +++ /dev/null @@ -1,14471 +0,0 @@ -HEAT3D_Pipeline_MAJOR_LOOP - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - -FIFO - - - - - - - - - - - - - - - - - - - >, i512 %p_Val2_3_load - -]]> - - - - -FIFO - - - - - - - - - - - - - - - - - - - >, i512 %p_Val2_2_load - -]]> - - - - - - - - - - - - >, i512 %p_Val2_4_load - -]]> - - - - -FIFO - - - - - - - - - - - - - - - - - - - >, i512 %p_Val2_1_load - -]]> - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - >, i512 %trunc_ln85 - -]]> - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_MAJOR_LOOP.verbose.sched.rpt.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_MAJOR_LOOP.verbose.sched.rpt.xml deleted file mode 100644 index 705d9b98..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_MAJOR_LOOP.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
-Fri Jul 12 20:03:00 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -HEAT3D (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
- -
- -
- -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.342 ns, 0.90 ns -
- -
- - -
- -, min, max, min, max, min, max, Type -?, ?, ?, ?, ?, ?, no -
- - -
- -Instance, Module, min, max, min, max, min, max, Type -
- - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -?, ?, 46, 1, 1, ?, yes -
- -
- -
- -
- diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_MAJOR_LOOP_csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_MAJOR_LOOP_csynth.xml deleted file mode 100644 index 8c9a6123..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_MAJOR_LOOP_csynth.xml +++ /dev/null @@ -1,398 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -HEAT3D_Pipeline_MAJOR_LOOP -3.33 -0.90 -vivado - - - -no - -ns -2.342 - - -clock cycles -undef -undef -undef -undef -undef -undef -undef -undef - - - -2.43 -undef -undef -undef -1 -46 - - - - - - - - -480 -80170 -38023 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -HEAT3D_Pipeline_MAJOR_LOOP -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -HEAT3D_Pipeline_MAJOR_LOOP -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -HEAT3D_Pipeline_MAJOR_LOOP -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -HEAT3D_Pipeline_MAJOR_LOOP -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -HEAT3D_Pipeline_MAJOR_LOOP -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -HEAT3D_Pipeline_MAJOR_LOOP -return value - -ap_ctrl_hs - -out -1 -control - - -in_stream_m15_to_m2_dout -in_stream_m15_to_m2 -pointer - -ap_fifo - -in -512 -control - - -in_stream_m15_to_m2_empty_n -in_stream_m15_to_m2 -pointer - -ap_fifo - -in -1 -control - - -in_stream_m15_to_m2_read -in_stream_m15_to_m2 -pointer - -ap_fifo - -out -1 -control - - -in_stream_m15_to_m2_din -in_stream_m15_to_m2 -pointer - -ap_fifo - -out -512 -control - - -in_stream_m15_to_m2_full_n -in_stream_m15_to_m2 -pointer - -ap_fifo - -in -1 -control - - -in_stream_m15_to_m2_write -in_stream_m15_to_m2 -pointer - -ap_fifo - -out -1 -control - - -in_stream_2_to_15_dout -in_stream_2_to_15 -pointer - -ap_fifo - -in -512 -control - - -in_stream_2_to_15_empty_n -in_stream_2_to_15 -pointer - -ap_fifo - -in -1 -control - - -in_stream_2_to_15_read -in_stream_2_to_15 -pointer - -ap_fifo - -out -1 -control - - -in_stream_2_to_15_din -in_stream_2_to_15 -pointer - -ap_fifo - -out -512 -control - - -in_stream_2_to_15_full_n -in_stream_2_to_15 -pointer - -ap_fifo - -in -1 -control - - -in_stream_2_to_15_write -in_stream_2_to_15 -pointer - -ap_fifo - -out -1 -control - - -in_s_dout -in_s -pointer - -ap_fifo - -in -513 -control - - -in_s_empty_n -in_s -pointer - -ap_fifo - -in -1 -control - - -in_s_read -in_s -pointer - -ap_fifo - -out -1 -control - - -out_r_din -out_r -pointer - -ap_fifo - -out -513 -control - - -out_r_full_n -out_r -pointer - -ap_fifo - -in -1 -control - - -out_r_write -out_r -pointer - -ap_fifo - -out -1 -control - - -in_block_1 -in_block_1 -scalar - -ap_none - -in -512 -data - - -in_block_m1 -in_block_m1 -scalar - -ap_none - -in -512 -data - - -in_block_0 -in_block_0 -scalar - -ap_none - -in -512 -data - - -in_block_16_V -in_block_16_V -scalar - -ap_none - -in -512 -data - - -in_block_m16_V -in_block_m16_V -scalar - -ap_none - -in -512 -data - - -add_ln73 -add_ln73 -scalar - -ap_none - -in -32 -data - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_116_3.sched.adb.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_116_3.sched.adb.xml deleted file mode 100644 index f686082b..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_116_3.sched.adb.xml +++ /dev/null @@ -1,260 +0,0 @@ -HEAT3D_Pipeline_VITIS_LOOP_116_3 - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_116_3.verbose.sched.rpt.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_116_3.verbose.sched.rpt.xml deleted file mode 100644 index c775a6db..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_116_3.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
-Fri Jul 12 20:03:01 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -HEAT3D (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
- -
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- -Clock, Target, Estimated, Uncertainty -3.33 ns, 1.215 ns, 0.90 ns -
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- -
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- diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_116_3_csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_116_3_csynth.xml deleted file mode 100644 index c39904b2..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_116_3_csynth.xml +++ /dev/null @@ -1,167 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -HEAT3D_Pipeline_VITIS_LOOP_116_3 -3.33 -0.90 -vivado - - - -no - -ns -1.215 - - -clock cycles -16 -16 -16 -53.280 ns -53.280 ns -53.280 ns -16 -16 - - - -2.43 -14 -14 -46 -1 -2 - - - - - - - - -7 -70 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -HEAT3D_Pipeline_VITIS_LOOP_116_3 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -HEAT3D_Pipeline_VITIS_LOOP_116_3 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -HEAT3D_Pipeline_VITIS_LOOP_116_3 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -HEAT3D_Pipeline_VITIS_LOOP_116_3 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -HEAT3D_Pipeline_VITIS_LOOP_116_3 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -HEAT3D_Pipeline_VITIS_LOOP_116_3 -return value - -ap_ctrl_hs - -out -1 -control - - -in_stream_m15_to_m2_dout -in_stream_m15_to_m2 -pointer - -ap_fifo - -in -512 -control - - -in_stream_m15_to_m2_empty_n -in_stream_m15_to_m2 -pointer - -ap_fifo - -in -1 -control - - -in_stream_m15_to_m2_read -in_stream_m15_to_m2 -pointer - -ap_fifo - -out -1 -control - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_121_4.sched.adb.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_121_4.sched.adb.xml deleted file mode 100644 index c4177f42..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_121_4.sched.adb.xml +++ /dev/null @@ -1,260 +0,0 @@ -HEAT3D_Pipeline_VITIS_LOOP_121_4 - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_121_4.verbose.sched.rpt.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_121_4.verbose.sched.rpt.xml deleted file mode 100644 index 67aaaa50..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_121_4.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
-Fri Jul 12 20:03:01 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -HEAT3D (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
- -
- -
- -Clock, Target, Estimated, Uncertainty -3.33 ns, 1.215 ns, 0.90 ns -
- -
- - -
- -, min, max, min, max, min, max, Type -16, 16, 53.280 ns, 53.280 ns, 16, 16, no -
- - -
- -Instance, Module, min, max, min, max, min, max, Type -
- - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -14, 14, 2, 1, 1, 14, yes -
- -
- -
- -
- diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_121_4_csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_121_4_csynth.xml deleted file mode 100644 index 1bbe1dce..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_121_4_csynth.xml +++ /dev/null @@ -1,167 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -HEAT3D_Pipeline_VITIS_LOOP_121_4 -3.33 -0.90 -vivado - - - -no - -ns -1.215 - - -clock cycles -16 -16 -16 -53.280 ns -53.280 ns -53.280 ns -16 -16 - - - -2.43 -14 -14 -46 -1 -2 - - - - - - - - -7 -70 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -HEAT3D_Pipeline_VITIS_LOOP_121_4 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -HEAT3D_Pipeline_VITIS_LOOP_121_4 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -HEAT3D_Pipeline_VITIS_LOOP_121_4 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -HEAT3D_Pipeline_VITIS_LOOP_121_4 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -HEAT3D_Pipeline_VITIS_LOOP_121_4 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -HEAT3D_Pipeline_VITIS_LOOP_121_4 -return value - -ap_ctrl_hs - -out -1 -control - - -in_stream_2_to_15_dout -in_stream_2_to_15 -pointer - -ap_fifo - -in -512 -control - - -in_stream_2_to_15_empty_n -in_stream_2_to_15 -pointer - -ap_fifo - -in -1 -control - - -in_stream_2_to_15_read -in_stream_2_to_15 -pointer - -ap_fifo - -out -1 -control - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_62_1.sched.adb.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_62_1.sched.adb.xml deleted file mode 100644 index f58679c2..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_62_1.sched.adb.xml +++ /dev/null @@ -1,306 +0,0 @@ -HEAT3D_Pipeline_VITIS_LOOP_62_1 - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_62_1.verbose.sched.rpt.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_62_1.verbose.sched.rpt.xml deleted file mode 100644 index b0599bf8..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_62_1.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
-Fri Jul 12 20:03:00 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -HEAT3D (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
- -
- -
- -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
- -
- - -
- -, min, max, min, max, min, max, Type -16, 16, 53.280 ns, 53.280 ns, 16, 16, no -
- - -
- -Instance, Module, min, max, min, max, min, max, Type -
- - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -14, 14, 2, 1, 1, 14, yes -
- -
- -
- -
- diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_62_1_csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_62_1_csynth.xml deleted file mode 100644 index 4ddadbb1..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_62_1_csynth.xml +++ /dev/null @@ -1,200 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -HEAT3D_Pipeline_VITIS_LOOP_62_1 -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -16 -16 -16 -53.280 ns -53.280 ns -53.280 ns -16 -16 - - - -2.43 -14 -14 -46 -1 -2 - - - - - - - - -7 -81 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -HEAT3D_Pipeline_VITIS_LOOP_62_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -HEAT3D_Pipeline_VITIS_LOOP_62_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -HEAT3D_Pipeline_VITIS_LOOP_62_1 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -HEAT3D_Pipeline_VITIS_LOOP_62_1 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -HEAT3D_Pipeline_VITIS_LOOP_62_1 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -HEAT3D_Pipeline_VITIS_LOOP_62_1 -return value - -ap_ctrl_hs - -out -1 -control - - -in_s_dout -in_s -pointer - -ap_fifo - -in -513 -control - - -in_s_empty_n -in_s -pointer - -ap_fifo - -in -1 -control - - -in_s_read -in_s -pointer - -ap_fifo - -out -1 -control - - -in_stream_m15_to_m2_din -in_stream_m15_to_m2 -pointer - -ap_fifo - -out -512 -control - - -in_stream_m15_to_m2_full_n -in_stream_m15_to_m2 -pointer - -ap_fifo - -in -1 -control - - -in_stream_m15_to_m2_write -in_stream_m15_to_m2 -pointer - -ap_fifo - -out -1 -control - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_68_2.sched.adb.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_68_2.sched.adb.xml deleted file mode 100644 index b9a0d66c..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_68_2.sched.adb.xml +++ /dev/null @@ -1,306 +0,0 @@ -HEAT3D_Pipeline_VITIS_LOOP_68_2 - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Adder - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_68_2.verbose.sched.rpt.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_68_2.verbose.sched.rpt.xml deleted file mode 100644 index e089c9f0..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_68_2.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
-Fri Jul 12 20:03:00 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -HEAT3D (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
- -
- -
- -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
- -
- - -
- -, min, max, min, max, min, max, Type -16, 16, 53.280 ns, 53.280 ns, 16, 16, no -
- - -
- -Instance, Module, min, max, min, max, min, max, Type -
- - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -14, 14, 2, 1, 1, 14, yes -
- -
- -
- -
- diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_68_2_csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_68_2_csynth.xml deleted file mode 100644 index 03f98a6a..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_Pipeline_VITIS_LOOP_68_2_csynth.xml +++ /dev/null @@ -1,200 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -HEAT3D_Pipeline_VITIS_LOOP_68_2 -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -16 -16 -16 -53.280 ns -53.280 ns -53.280 ns -16 -16 - - - -2.43 -14 -14 -46 -1 -2 - - - - - - - - -9 -83 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -HEAT3D_Pipeline_VITIS_LOOP_68_2 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -HEAT3D_Pipeline_VITIS_LOOP_68_2 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -HEAT3D_Pipeline_VITIS_LOOP_68_2 -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -HEAT3D_Pipeline_VITIS_LOOP_68_2 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -HEAT3D_Pipeline_VITIS_LOOP_68_2 -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -HEAT3D_Pipeline_VITIS_LOOP_68_2 -return value - -ap_ctrl_hs - -out -1 -control - - -in_s_dout -in_s -pointer - -ap_fifo - -in -513 -control - - -in_s_empty_n -in_s -pointer - -ap_fifo - -in -1 -control - - -in_s_read -in_s -pointer - -ap_fifo - -out -1 -control - - -in_stream_2_to_15_din -in_stream_2_to_15 -pointer - -ap_fifo - -out -512 -control - - -in_stream_2_to_15_full_n -in_stream_2_to_15 -pointer - -ap_fifo - -in -1 -control - - -in_stream_2_to_15_write -in_stream_2_to_15 -pointer - -ap_fifo - -out -1 -control - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_csynth.xml deleted file mode 100644 index cd514502..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_csynth.xml +++ /dev/null @@ -1,242 +0,0 @@ - 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- -in_peek_read -in_peek -pointer - -ap_fifo - -out -1 -control -int - - -out_r_din -out_r -pointer - -ap_fifo - -out -513 -control -int - - -out_r_full_n -out_r -pointer - -ap_fifo - -in -1 -control -int - - -out_r_write -out_r -pointer - -ap_fifo - -out -1 -control -int - - -iters -iters -scalar - -ap_none - -in -32 -data -int - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_stencil_kernel.sched.adb.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_stencil_kernel.sched.adb.xml deleted file mode 100644 index 3a3ee580..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_stencil_kernel.sched.adb.xml +++ /dev/null @@ -1,1707 +0,0 @@ -HEAT3D_stencil_kernel - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- -
-Fri Jul 12 20:03:00 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -HEAT3D (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
- -
- -
- -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.342 ns, 0.90 ns -
- -
- - -
- -, min, max, min, max, min, max, Type -42, 42, 0.140 us, 0.140 us, 1, 1, yes -
- - -
- -Instance, Module, min, max, min, max, min, max, Type -
- - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -
- -
- -
- -
- diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_stencil_kernel_csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_stencil_kernel_csynth.xml deleted file mode 100644 index 5c4cf24a..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HEAT3D_stencil_kernel_csynth.xml +++ /dev/null @@ -1,179 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -HEAT3D_stencil_kernel -3.33 -0.90 -vivado - - - -yes - -ns -2.342 - - -clock cycles -42 -42 -42 -0.140 us -0.140 us -0.140 us -1 -43 -1 -1 - - - - - -30 -4811 -2364 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -HEAT3D_stencil_kernel -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst -HEAT3D_stencil_kernel -return value - -ap_ctrl_hs - -in -1 -control - - -ap_return -HEAT3D_stencil_kernel -return value - -ap_ctrl_hs - -out -32 -data - - -ap_ce -HEAT3D_stencil_kernel -return value - -ap_ctrl_hs - -in -1 -control - - -in_1_0_0 -in_1_0_0 -scalar - -ap_none - -in -32 -data - - -in_0_0_1 -in_0_0_1 -scalar - -ap_none - -in -32 -data - - -in_0_0_m1 -in_0_0_m1 -scalar - -ap_none - -in -32 -data - - -in_0_0_0 -in_0_0_0 -scalar - -ap_none - -in -32 -data - - -in_0_m1_0 -in_0_m1_0 -scalar - -ap_none - -in -32 -data - - -in_m1_0_0 -in_m1_0_0 -scalar - -ap_none - -in -32 -data - - -in_0_1_0 -in_0_1_0 -scalar - -ap_none - -in -32 -data - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HLS_REG_ap_uint_512_s.verbose.sched.rpt.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HLS_REG_ap_uint_512_s.verbose.sched.rpt.xml deleted file mode 100644 index cc132da8..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HLS_REG_ap_uint_512_s.verbose.sched.rpt.xml +++ /dev/null @@ -1,45 +0,0 @@ - - -
-Fri Jul 12 20:03:00 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -HEAT3D (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
- -
- -
- -Clock, Target, Estimated, Uncertainty -3.33 ns, 0 ns, 0.90 ns -
- -
- - -
- -, min, max, min, max, min, max, Type -0, 0, 0 ns, 0 ns, 1, 1, yes -
- - -
- -Instance, Module, min, max, min, max, min, max, Type -
- - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -
- -
- -
- -
- diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HLS_REG_ap_uint_512_s_csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HLS_REG_ap_uint_512_s_csynth.xml deleted file mode 100644 index 6056385c..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/HLS_REG_ap_uint_512_s_csynth.xml +++ /dev/null @@ -1,92 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -HLS_REG_ap_uint_512_s -3.33 -0.90 -4294967295 -vivado - - - -yes - -ns -0.000 - - -clock cycles -0 -0 -0 -0 ns -0 ns -0 ns -1 -1 -1 -1 - - - - - -0 -0 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_ready -HLS_REG<ap_uint<512> > -return value - -ap_ctrl_hs - -out -1 -control - - -ap_return -HLS_REG<ap_uint<512> > -return value - -ap_ctrl_hs - -out -512 -data - - -in_r -in_r -scalar - -ap_none - -in -512 -data - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/csynth.xml deleted file mode 100644 index e8641769..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/csynth.xml +++ /dev/null @@ -1,1038 +0,0 @@ - - - 2022.2 - - - ns - virtexuplus - xcu280-fsvh2892-2L-e - unikernel - 3.33 - 0.90 - vivado - - - no - - ns - 1.000 - - - clock cycles - 0 - 0 - 0 - 0 ns - 0 ns - 0 ns - 1 - 1 - - - - - 0 - 1754 - 3176 - 0 - 0 - - - 4032 - 9024 - 2607360 - 1303680 - 960 - - - - - s_axi_control_AWVALID - control - scalar - s_axi - in - 1 - unknown - int - 1 - - - s_axi_control_AWREADY - control - scalar - s_axi - out - 1 - unknown - int - 1 - - - s_axi_control_AWADDR - control - scalar - s_axi - in - 9 - unknown - int - 1 - - - s_axi_control_WVALID - control - scalar - s_axi - in - 1 - unknown - int - 1 - - - s_axi_control_WREADY - control - scalar - s_axi - out - 1 - unknown - int - 1 - - - s_axi_control_WDATA - control - scalar - s_axi - in - 32 - unknown - int - 1 - - - s_axi_control_WSTRB - control - scalar - s_axi - in - 4 - unknown - int - 1 - - - s_axi_control_ARVALID - control - scalar - s_axi - in - 1 - unknown - int - 1 - - - s_axi_control_ARREADY - control - scalar - s_axi - out - 1 - unknown - int - 1 - - - s_axi_control_ARADDR - control - scalar - s_axi - in - 9 - unknown - int - 1 - - - s_axi_control_RVALID - control - scalar - s_axi - out - 1 - unknown - int - 1 - - - s_axi_control_RREADY - control - scalar - s_axi - in - 1 - unknown - int - 1 - - - s_axi_control_RDATA - control - scalar - s_axi - out - 32 - unknown - int - 1 - - - s_axi_control_RRESP - control - scalar - s_axi - out - 2 - unknown - int - 1 - - - s_axi_control_BVALID - control - scalar - s_axi - out - 1 - unknown - int - 1 - - - s_axi_control_BREADY - control - scalar - s_axi - in - 1 - unknown - int - 1 - - - s_axi_control_BRESP - control - scalar - s_axi - out - 2 - unknown - int - 1 - - - ap_clk - unikernel - return value - - ap_ctrl_hs - - in - 1 - control - - - ap_rst_n - unikernel - return value - - ap_ctrl_hs - - in - 1 - control - - - interrupt - unikernel - return value - - ap_ctrl_hs - - out - 1 - unknown - - - - - unikernel - - - - - unikernel - - - 3.33 - 0.90 - 1.000 - - - 0 - 0 - 0 - 0 ns - 0 ns - 0 ns - 1 - no - - - - - 0 - 4032 - 0 - 1754 - 2607360 - ~0 - 3176 - 1303680 - ~0 - 0 - 960 - 0 - 0 - 9024 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - s_axi_control_ARADDR - s_axi_control_ARREADY - s_axi_control_ARVALID - s_axi_control_AWADDR - s_axi_control_AWREADY - s_axi_control_AWVALID - s_axi_control_BREADY - s_axi_control_BRESP - s_axi_control_BVALID - s_axi_control_RDATA - s_axi_control_RREADY - s_axi_control_RRESP - s_axi_control_RVALID - s_axi_control_WDATA - s_axi_control_WREADY - s_axi_control_WSTRB - s_axi_control_WVALID - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - s_axi_control - ap_rst_n - - - CLK - - - ap_clk - - - - - ACTIVE_LOW - - - RST - - - ap_rst_n - - - - - LEVEL_HIGH - - - INTERRUPT - - - interrupt - - - - -
- - - Interface, Data Width, Address Width, Offset, Register - 32, 9, 16, 0, , , , , -
- - - - Interface, Register, Offset, Width, Access, Description, Bit Fields - CTRL, 0x00, 32, RW, Control signals, 0=AP_START 1=AP_DONE 2=AP_IDLE 3=AP_READY 7=AUTO_RESTART 9=INTERRUPT - GIER, 0x04, 32, RW, Global Interrupt Enable Register, 0=Enable - IP_IER, 0x08, 32, RW, IP Interrupt Enable Register, 0=CHAN0_INT_EN 1=CHAN1_INT_EN - IP_ISR, 0x0c, 32, RW, IP Interrupt Status Register, 0=CHAN0_INT_ST 1=CHAN1_INT_ST - in_0_1, 0x10, 32, W, Data signal of in_0, - in_0_2, 0x14, 32, W, Data signal of in_0, - out_0_1, 0x1c, 32, W, Data signal of out_0, - out_0_2, 0x20, 32, W, Data signal of out_0, - in_1_1, 0x28, 32, W, Data signal of in_1, - in_1_2, 0x2c, 32, W, Data signal of in_1, - out_1_1, 0x34, 32, W, Data signal of out_1, - out_1_2, 0x38, 32, W, Data signal of out_1, - in_2_1, 0x40, 32, W, Data signal of in_2, - in_2_2, 0x44, 32, W, Data signal of in_2, - out_2_1, 0x4c, 32, W, Data signal of out_2, - out_2_2, 0x50, 32, W, Data signal of out_2, - in_3_1, 0x58, 32, W, Data signal of in_3, - in_3_2, 0x5c, 32, W, Data signal of in_3, - out_3_1, 0x64, 32, W, Data signal of out_3, - out_3_2, 0x68, 32, W, Data signal of out_3, - in_4_1, 0x70, 32, W, Data signal of in_4, - in_4_2, 0x74, 32, W, Data signal of in_4, - out_4_1, 0x7c, 32, W, Data signal of out_4, - out_4_2, 0x80, 32, W, Data signal of out_4, - in_5_1, 0x88, 32, W, Data signal of in_5, - in_5_2, 0x8c, 32, W, Data signal of in_5, - out_5_1, 0x94, 32, W, Data signal of out_5, - out_5_2, 0x98, 32, W, Data signal of out_5, - in_6_1, 0xa0, 32, W, Data signal of in_6, - in_6_2, 0xa4, 32, W, Data signal of in_6, - out_6_1, 0xac, 32, W, Data signal of out_6, - out_6_2, 0xb0, 32, W, Data signal of out_6, - in_7_1, 0xb8, 32, W, Data signal of in_7, - in_7_2, 0xbc, 32, W, Data signal of in_7, - out_7_1, 0xc4, 32, W, Data signal of out_7, - out_7_2, 0xc8, 32, W, Data signal of out_7, - in_8_1, 0xd0, 32, W, Data signal of in_8, - in_8_2, 0xd4, 32, W, Data signal of in_8, - out_8_1, 0xdc, 32, W, Data signal of out_8, - out_8_2, 0xe0, 32, W, Data signal of out_8, - in_9_1, 0xe8, 32, W, Data signal of in_9, - in_9_2, 0xec, 32, W, Data signal of in_9, - out_9_1, 0xf4, 32, W, Data signal of out_9, - out_9_2, 0xf8, 32, W, Data signal of out_9, - in_10_1, 0x100, 32, W, Data signal of in_10, - in_10_2, 0x104, 32, W, Data signal of in_10, - out_10_1, 0x10c, 32, W, Data signal of out_10, - out_10_2, 0x110, 32, W, Data signal of out_10, - in_11_1, 0x118, 32, W, Data signal of in_11, - in_11_2, 0x11c, 32, W, Data signal of in_11, - out_11_1, 0x124, 32, W, Data signal of out_11, - out_11_2, 0x128, 32, W, Data signal of out_11, - iters, 0x130, 32, W, Data signal of iters, -
- - - - Interface, Type, Ports - clock, ap_clk, - reset, ap_rst_n, - interrupt, interrupt, - ap_ctrl_hs, , -
- -
- - -
- - - Argument, Direction, Datatype - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, long unsigned int - in, unsigned int -
- - - - Argument, HW Interface, HW Type, HW Info - s_axi_control, register, name=in_0_1 offset=0x10 range=32, - s_axi_control, register, name=in_0_2 offset=0x14 range=32, - s_axi_control, register, name=out_0_1 offset=0x1c range=32, - s_axi_control, register, name=out_0_2 offset=0x20 range=32, - s_axi_control, register, name=in_1_1 offset=0x28 range=32, - s_axi_control, register, name=in_1_2 offset=0x2c range=32, - s_axi_control, register, name=out_1_1 offset=0x34 range=32, - s_axi_control, register, name=out_1_2 offset=0x38 range=32, - s_axi_control, register, name=in_2_1 offset=0x40 range=32, - s_axi_control, register, name=in_2_2 offset=0x44 range=32, - s_axi_control, register, name=out_2_1 offset=0x4c range=32, - s_axi_control, register, name=out_2_2 offset=0x50 range=32, - s_axi_control, register, name=in_3_1 offset=0x58 range=32, - s_axi_control, register, name=in_3_2 offset=0x5c range=32, - s_axi_control, register, name=out_3_1 offset=0x64 range=32, - s_axi_control, register, name=out_3_2 offset=0x68 range=32, - s_axi_control, register, name=in_4_1 offset=0x70 range=32, - s_axi_control, register, name=in_4_2 offset=0x74 range=32, - s_axi_control, register, name=out_4_1 offset=0x7c range=32, - s_axi_control, register, name=out_4_2 offset=0x80 range=32, - s_axi_control, register, name=in_5_1 offset=0x88 range=32, - s_axi_control, register, name=in_5_2 offset=0x8c range=32, - s_axi_control, register, name=out_5_1 offset=0x94 range=32, - s_axi_control, register, name=out_5_2 offset=0x98 range=32, - s_axi_control, register, name=in_6_1 offset=0xa0 range=32, - s_axi_control, register, name=in_6_2 offset=0xa4 range=32, - s_axi_control, register, name=out_6_1 offset=0xac range=32, - s_axi_control, register, name=out_6_2 offset=0xb0 range=32, - s_axi_control, register, name=in_7_1 offset=0xb8 range=32, - s_axi_control, register, name=in_7_2 offset=0xbc range=32, - s_axi_control, register, name=out_7_1 offset=0xc4 range=32, - s_axi_control, register, name=out_7_2 offset=0xc8 range=32, - s_axi_control, register, name=in_8_1 offset=0xd0 range=32, - s_axi_control, register, name=in_8_2 offset=0xd4 range=32, - s_axi_control, register, name=out_8_1 offset=0xdc range=32, - s_axi_control, register, name=out_8_2 offset=0xe0 range=32, - s_axi_control, register, name=in_9_1 offset=0xe8 range=32, - s_axi_control, register, name=in_9_2 offset=0xec range=32, - s_axi_control, register, name=out_9_1 offset=0xf4 range=32, - s_axi_control, register, name=out_9_2 offset=0xf8 range=32, - s_axi_control, register, name=in_10_1 offset=0x100 range=32, - s_axi_control, register, name=in_10_2 offset=0x104 range=32, - s_axi_control, register, name=out_10_1 offset=0x10c range=32, - s_axi_control, register, name=out_10_2 offset=0x110 range=32, - s_axi_control, register, name=in_11_1 offset=0x118 range=32, - s_axi_control, register, name=in_11_2 offset=0x11c range=32, - s_axi_control, register, name=out_11_1 offset=0x124 range=32, - s_axi_control, register, name=out_11_2 offset=0x128 range=32, - s_axi_control, register, name=iters offset=0x130 range=32, -
- -
- - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/inter_kernel.sched.adb.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/inter_kernel.sched.adb.xml deleted file mode 100644 index 5461337f..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/inter_kernel.sched.adb.xml +++ /dev/null @@ -1,1170 +0,0 @@ -inter_kernel - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -FIFO - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -Cmp - - - - - - - - - - - -Adder - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - - - - -NULL - - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/inter_kernel.verbose.sched.rpt.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/inter_kernel.verbose.sched.rpt.xml deleted file mode 100644 index 68525a5c..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/inter_kernel.verbose.sched.rpt.xml +++ /dev/null @@ -1,46 +0,0 @@ - - -
-Fri Jul 12 20:03:00 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -inter_kernel (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
- -
- -
- -Clock, Target, Estimated, Uncertainty -3.33 ns, 2.431 ns, 0.90 ns -
- -
- - -
- -, min, max, min, max, min, max, Type -?, ?, ?, ?, ?, ?, no -
- - -
- -Instance, Module, min, max, min, max, min, max, Type -
- - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -?, ?, ?, -, -, ?, no -
- -
- -
- -
- diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/inter_kernel_csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/inter_kernel_csynth.xml deleted file mode 100644 index 3cf9c435..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/inter_kernel_csynth.xml +++ /dev/null @@ -1,757 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -inter_kernel -3.33 -0.90 -vivado - - - -no - -ns -2.431 - - -clock cycles -undef -undef -undef -undef -undef -undef -undef -undef - - - -2.43 -undef -undef -undef -undef - - - - - - - - -384 -846 -0 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -ap_clk -inter_kernel -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst_n -inter_kernel -return value - -ap_ctrl_hs - -in -1 -control - - -ap_start -inter_kernel -return value - -ap_ctrl_hs - -in -1 -control - - -ap_done -inter_kernel -return value - -ap_ctrl_hs - -out -1 -control - - -ap_idle -inter_kernel -return value - -ap_ctrl_hs - -out -1 -control - - -ap_ready -inter_kernel -return value - -ap_ctrl_hs - -out -1 -control - - -a_read_addr_din -a_read_addr -pointer - -ap_fifo - -out -65 -control -int - - -a_read_addr_full_n -a_read_addr -pointer - -ap_fifo - -in -1 -control -int - - -a_read_addr_write -a_read_addr -pointer - -ap_fifo - -out -1 -control -int - - -a_read_data_s_dout -a_read_data_s -pointer - -ap_fifo - -in -513 -control -int - - -a_read_data_s_empty_n -a_read_data_s -pointer - -ap_fifo - -in -1 -control -int - - -a_read_data_s_read -a_read_data_s -pointer - -ap_fifo - -out -1 -control -int - - -a_read_data_peek_dout -a_read_data_peek -pointer - -ap_fifo - -in -513 -control -int - - -a_read_data_peek_empty_n -a_read_data_peek -pointer - -ap_fifo - -in -1 -control -int - - -a_read_data_peek_read -a_read_data_peek -pointer - -ap_fifo - -out -1 -control -int - - -a_write_addr_din -a_write_addr -pointer - -ap_fifo - -out -65 -control -int - - -a_write_addr_full_n -a_write_addr -pointer - -ap_fifo - -in -1 -control -int - - -a_write_addr_write -a_write_addr -pointer - -ap_fifo - -out -1 -control -int - - -a_write_data_din -a_write_data -pointer - -ap_fifo - -out -513 -control -int - - -a_write_data_full_n -a_write_data -pointer - -ap_fifo - -in -1 -control -int - - -a_write_data_write -a_write_data -pointer - -ap_fifo - -out -1 -control -int - - -a_write_resp_s_dout -a_write_resp_s -pointer - -ap_fifo - -in -9 -control -int - - -a_write_resp_s_empty_n -a_write_resp_s -pointer - -ap_fifo - -in -1 -control -int - - -a_write_resp_s_read -a_write_resp_s -pointer - -ap_fifo - -out -1 -control -int - - -a_write_resp_peek_dout -a_write_resp_peek -pointer - -ap_fifo - -in -9 -control -int - - -a_write_resp_peek_empty_n -a_write_resp_peek -pointer - -ap_fifo - -in -1 -control -int - - -a_write_resp_peek_read -a_write_resp_peek -pointer - -ap_fifo - -out -1 -control -int - - -b_read_addr_din -b_read_addr -pointer - -ap_fifo - -out -65 -control -int - - -b_read_addr_full_n -b_read_addr -pointer - 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- - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -s_axilite - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - -NULL - - - - - - - - - - - - - - - - - - - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/unikernel.verbose.sched.rpt.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/unikernel.verbose.sched.rpt.xml deleted file mode 100644 index f0fe535d..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/unikernel.verbose.sched.rpt.xml +++ /dev/null @@ -1,45 +0,0 @@ - - -
-Fri Jul 12 20:02:59 2024 - -2022.2 (Build 3670227 on Oct 13 2022) -project -unikernel (Vivado IP Flow Target) -virtexuplus -xcu280-fsvh2892-2L-e -
- -
- -
- -Clock, Target, Estimated, Uncertainty -3.33 ns, 1.000 ns, 0.90 ns -
- -
- - -
- -, min, max, min, max, min, max, Type -0, 0, 0 ns, 0 ns, 1, 1, no -
- - -
- -Instance, Module, min, max, min, max, min, max, Type -
- - -Loop Name, min, max, Latency, achieved, target, Count, Pipelined -
- -
- -
- -
- diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/unikernel_csynth.xml b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/unikernel_csynth.xml deleted file mode 100644 index acb8a0aa..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/report/unikernel_csynth.xml +++ /dev/null @@ -1,276 +0,0 @@ - - - -2022.2 - - - -ns -virtexuplus -xcu280-fsvh2892-2L-e -unikernel -3.33 -0.90 -vivado - - - -no - -ns -1.000 - - -clock cycles -0 -0 -0 -0 ns -0 ns -0 ns -1 -1 - - - - - -0 -1754 -3176 -0 -0 - - -4032 -9024 -2607360 -1303680 -960 - - - - - -s_axi_control_AWVALID -control -scalar -s_axi -in -1 -unknown -int -1 - - -s_axi_control_AWREADY -control -scalar -s_axi -out -1 -unknown -int -1 - - -s_axi_control_AWADDR -control -scalar -s_axi -in -9 -unknown -int -1 - - -s_axi_control_WVALID -control -scalar -s_axi -in -1 -unknown -int -1 - - -s_axi_control_WREADY -control -scalar -s_axi -out -1 -unknown -int -1 - - -s_axi_control_WDATA -control -scalar -s_axi -in -32 -unknown -int -1 - - -s_axi_control_WSTRB -control -scalar -s_axi -in -4 -unknown -int -1 - - -s_axi_control_ARVALID -control -scalar -s_axi -in -1 -unknown -int -1 - - -s_axi_control_ARREADY -control -scalar -s_axi -out -1 -unknown -int -1 - - -s_axi_control_ARADDR -control -scalar -s_axi -in -9 -unknown -int -1 - - -s_axi_control_RVALID -control -scalar -s_axi -out -1 -unknown -int -1 - - -s_axi_control_RREADY -control -scalar -s_axi -in -1 -unknown -int -1 - - -s_axi_control_RDATA -control -scalar -s_axi -out -32 -unknown -int -1 - - -s_axi_control_RRESP -control -scalar -s_axi -out -2 -unknown -int -1 - - -s_axi_control_BVALID -control -scalar -s_axi -out -1 -unknown -int -1 - - -s_axi_control_BREADY -control -scalar -s_axi -in -1 -unknown -int -1 - - -s_axi_control_BRESP -control -scalar -s_axi -out -2 -unknown -int -1 - - -ap_clk -unikernel -return value - -ap_ctrl_hs - -in -1 -control - - -ap_rst_n -unikernel -return value - -ap_ctrl_hs - -in -1 -control - - -interrupt -unikernel -return value - -ap_ctrl_hs - -out -1 -unknown - - - - diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/settings.json b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/settings.json deleted file mode 100644 index fdeb22a8..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/settings.json +++ /dev/null @@ -1,8 +0,0 @@ -{ - "additional_fifo_pipelining": false, - "clock_period": 3.33, - "linked": true, - "part_num": "xcu280-fsvh2892-2L-e", - "platform": null, - "synthed": true -} diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/tar/HEAT3D.tar b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/tar/HEAT3D.tar deleted file mode 100644 index bffd5cd2..00000000 Binary files a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/tar/HEAT3D.tar and /dev/null differ diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/tar/inter_kernel.tar b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/tar/inter_kernel.tar deleted file mode 100644 index 1f0e0738..00000000 Binary files a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/tar/inter_kernel.tar and /dev/null differ diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/tar/unikernel.tar b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/tar/unikernel.tar deleted file mode 100644 index 8004bfb8..00000000 Binary files a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/tar/unikernel.tar and /dev/null differ diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/unikernel.xo b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/unikernel.xo deleted file mode 100644 index 50ebdc11..00000000 Binary files a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/generated/unikernel.xo and /dev/null differ diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/run_tapa.sh b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/run_tapa.sh deleted file mode 100644 index 5c92e301..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/run_tapa.sh +++ /dev/null @@ -1,11 +0,0 @@ -WORK_DIR=generated - -tapac \ - --work-dir ${WORK_DIR} \ - --top unikernel \ - --part-num xcu280-fsvh2892-2L-e \ - --clock-period 3.33 \ - -o ${WORK_DIR}/unikernel.xo \ - --connectivity config/link_config.ini \ - src/unikernel.cpp \ - 2>&1 | tee tapa.log diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/src/HEAT3D.h b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/src/HEAT3D.h deleted file mode 100644 index 3b0e26de..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/src/HEAT3D.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef HEAT3D_H -#define HEAT3D_H - -#define GRID_ROWS 256 -#define GRID_COLS 256 - -#define KERNEL_COUNT 12 -#define PART_ROWS GRID_ROWS / KERNEL_COUNT - -#define ITERATION 512 - -#include "ap_int.h" -#include -#define DWIDTH 512 -#define INTERFACE_WIDTH ap_uint - const int WIDTH_FACTOR = DWIDTH/32; -#define PARA_FACTOR 16 - -#define STAGE_COUNT 1 -#define TOP_APPEND 16 -#define BOTTOM_APPEND 17 -#define OVERLAP_TOP_OVERHEAD 8176 -#define OVERLAP_BOTTOM_OVERHEAD 8687 -#define DECRE_TOP_APPEND 16 -#define DECRE_BOTTOM_APPEND 17 - -#define MIDLE_REGION (GRID_COLS*PART_ROWS + 258*WIDTH_FACTOR + (TOP_APPEND+BOTTOM_APPEND)*WIDTH_FACTOR*(STAGE_COUNT-1) + (OVERLAP_TOP_OVERHEAD + OVERLAP_BOTTOM_OVERHEAD))/WIDTH_FACTOR -#endif diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/src/host.cpp b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/src/host.cpp deleted file mode 100644 index 3d12ade3..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/src/host.cpp +++ /dev/null @@ -1,173 +0,0 @@ -#include -#include -#include -#include - -#include -#include -#include "HEAT3D.h" - -using std::clog; -using std::endl; -using std::vector; -using std::chrono::duration; -using std::chrono::high_resolution_clock; - - -void unikernel(tapa::mmap in_0, tapa::mmap out_0, - tapa::mmap in_1, tapa::mmap out_1, - tapa::mmap in_2, tapa::mmap out_2, - tapa::mmap in_3, tapa::mmap out_3, - tapa::mmap in_4, tapa::mmap out_4, - tapa::mmap in_5, tapa::mmap out_5, - tapa::mmap in_6, tapa::mmap out_6, - tapa::mmap in_7, tapa::mmap out_7, - tapa::mmap in_8, tapa::mmap out_8, - tapa::mmap in_9, tapa::mmap out_9, - tapa::mmap in_10, tapa::mmap out_10, - tapa::mmap in_11, tapa::mmap out_11, - // tapa::mmap in_12, tapa::mmap out_12, - // tapa::mmap in_13, tapa::mmap out_13, - // tapa::mmap in_14, tapa::mmap out_14, - uint32_t iters); - -DEFINE_string(bitstream, "", "path to bitstream file, run csim if empty"); - -int main(int argc, char* argv[]) { - gflags::ParseCommandLineFlags(&argc, &argv, /*remove_flags=*/true); - - srand (time(NULL)); - - //Data initialization - // const uint64_t n = argc > 1 ? atoll(argv[1]) : 1024 * 1024; - printf("midle_region = %d\n", MIDLE_REGION); - vector in_0(MIDLE_REGION); vector out_0(MIDLE_REGION); - vector in_1(MIDLE_REGION); vector out_1(MIDLE_REGION); - vector in_2(MIDLE_REGION); vector out_2(MIDLE_REGION); - vector in_3(MIDLE_REGION); vector out_3(MIDLE_REGION); - vector in_4(MIDLE_REGION); vector out_4(MIDLE_REGION); - vector in_5(MIDLE_REGION); vector out_5(MIDLE_REGION); - vector in_6(MIDLE_REGION); vector out_6(MIDLE_REGION); - vector in_7(MIDLE_REGION); vector out_7(MIDLE_REGION); - vector in_8(MIDLE_REGION); vector out_8(MIDLE_REGION); - vector in_9(MIDLE_REGION); vector out_9(MIDLE_REGION); - vector in_10(MIDLE_REGION); vector out_10(MIDLE_REGION); - vector in_11(MIDLE_REGION); vector out_11(MIDLE_REGION); - // vector in_12(MIDLE_REGION); vector out_12(MIDLE_REGION); - // vector in_13(MIDLE_REGION); vector out_13(MIDLE_REGION); - // vector in_14(MIDLE_REGION); vector out_14(MIDLE_REGION); - - //Software emulation vector - float sw_in[MIDLE_REGION * WIDTH_FACTOR]; - float sw_out[MIDLE_REGION * WIDTH_FACTOR]; - - // input test - for(int i = 0; i < MIDLE_REGION; i++){ - INTERFACE_WIDTH a; - float temp = rand() % 100 + 1; - // float temp = (i * i) % 100; - for(int k = 0; k < WIDTH_FACTOR; k++){ - unsigned int idx_k = k << 5; - // float temp = (i * WIDTH_FACTOR + k); - - a.range(idx_k + 31, idx_k) = *((uint32_t *)(&temp)); - sw_in[i * WIDTH_FACTOR + k] = temp; - } - in_0[i] = a; out_0[i] = a; - in_1[i] = a; out_1[i] = a; - in_2[i] = a; out_2[i] = a; - in_3[i] = a; out_3[i] = a; - in_4[i] = a; out_4[i] = a; - in_5[i] = a; out_5[i] = a; - in_6[i] = a; out_6[i] = a; - in_7[i] = a; out_7[i] = a; - in_8[i] = a; out_8[i] = a; - in_9[i] = a; out_9[i] = a; - in_10[i] = a; out_10[i] = a; - in_11[i] = a; out_11[i] = a; - // in_12[i] = a; out_12[i] = a; - // in_13[i] = a; out_13[i] = a; - // in_14[i] = a; out_14[i] = a; - } - const uint32_t iter = 1; - - // Software result - - // for(int i = 0; i < MIDLE_REGION * WIDTH_FACTOR; i++){ - // sw_in[i] = i; - // } - - for(int n = 0; n < iter; n++){ - for(int i = 1025; i < MIDLE_REGION * WIDTH_FACTOR - 1025; i++){ - sw_out[i] = (sw_in[i - 1024] + sw_in[i - 1025] + sw_in[i - 1023] + sw_in[i - 1] + sw_in[i] + sw_in[i + 1] + sw_in[i + 1023] + sw_in[i + 1] + sw_in[i + 1025]) /(float) 9; - } - } - // std::cout << (GRID_COLS/WIDTH_FACTOR*PART_ROWS + (TOP_APPEND+BOTTOM_APPEND)*(1-1)) << endl; - // std::cout << MIDLE_REGION << endl; - - std::cout << "kernel start" << endl; - //Kernel execution - auto start = high_resolution_clock::now(); - // tapa::invoke(VecAdd, FLAGS_bitstream, tapa::read_only_mmap(a), - // tapa::read_only_mmap(b), - // tapa::write_only_mmap(c), n); - tapa::invoke(unikernel, FLAGS_bitstream, - tapa::read_write_mmap(in_0), tapa::read_write_mmap(out_0), - tapa::read_write_mmap(in_1), tapa::read_write_mmap (out_1), - tapa::read_write_mmap(in_2), tapa::read_write_mmap (out_2), - tapa::read_write_mmap(in_3), tapa::read_write_mmap (out_3), - tapa::read_write_mmap(in_4), tapa::read_write_mmap (out_4), - tapa::read_write_mmap(in_5), tapa::read_write_mmap (out_5), - tapa::read_write_mmap(in_6), tapa::read_write_mmap (out_6), - tapa::read_write_mmap(in_7), tapa::read_write_mmap (out_7), - tapa::read_write_mmap(in_8), tapa::read_write_mmap (out_8), - tapa::read_write_mmap(in_9), tapa::read_write_mmap (out_9), - tapa::read_write_mmap(in_10), tapa::read_write_mmap (out_10), - tapa::read_write_mmap(in_11), tapa::read_write_mmap (out_11), - // tapa::read_write_mmap(in_12), tapa::read_write_mmap (out_12), - // tapa::read_write_mmap(in_13), tapa::read_write_mmap (out_13), - // tapa::read_write_mmap(in_14), tapa::read_write_mmap (out_14), - iter); - auto stop = high_resolution_clock::now(); - duration elapsed = stop - start; - clog << "elapsed time: " << elapsed.count() << "s" << endl; - - // Verification - uint64_t num_errors = 0; - const uint64_t threshold = 10; // only report up to these errors - for(int i = 66; i < 128; i++){ - for(int k = 0; k < WIDTH_FACTOR; k++){ - unsigned int idx_k = k << 5; - uint32_t temp = out_0[i + 66].range(idx_k + 31, idx_k); - float hw_result = (*((float*)(&temp))); - if(sw_out[i * WIDTH_FACTOR + k] != hw_result){ - ++num_errors; - std::cout << (i * WIDTH_FACTOR + k) << " " << hw_result << " " << sw_out[i * WIDTH_FACTOR + k] << endl; - } - // sstd::cout << (i * WIDTH_FACTOR + k) << " " << hw_result << " " << sw_out[i * WIDTH_FACTOR + k] << endl; - } - } - // for (uint64_t i = 0; i < n; ++i) { - // auto expected = i * 3; - // auto actual = static_cast(c[i]); - // if (actual != expected) { - // if (num_errors < threshold) { - // clog << "expected: " << expected << ", actual: " << actual << endl; - // } else if (num_errors == threshold) { - // clog << "..."; - // } - // ++num_errors; - // } - // } - - - if (num_errors == 0) { - clog << "PASS!" << endl; - } else { - if (num_errors > threshold) { - clog << " (+" << (num_errors - threshold) << " more errors)" << endl; - } - clog << "FAIL!" << endl; - } - return num_errors > 0 ? 1 : 0; -} diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/src/unikernel.cpp b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/src/unikernel.cpp deleted file mode 100644 index 3c57354e..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/design/src/unikernel.cpp +++ /dev/null @@ -1,207 +0,0 @@ -#include -#include "math.h" -#include "HEAT3D.h" -#include - -template -T HLS_REG(T in){ -#pragma HLS pipeline -#pragma HLS inline off -#pragma HLS interface port=return register - return in; -} - -float HEAT3D_stencil_kernel(float in_1_0_0, float in_0_0_1, - float in_0_0_m1, float in_0_0_0, float in_0_m1_0, float in_m1_0_0, - float in_0_1_0) -{ - /* - (cal1 + cal2 + cal3 + in(0, 0, 0)) - */ - const float cal1 = ((in_1_0_0 - ((float)2 * in_0_0_0) + in_m1_0_0) / (float)8); - const float cal2 = ((in_0_1_0 - ((float)2 * in_0_0_0) + in_0_m1_0) / (float)8); - const float cal3 = ((in_0_0_1 - ((float)2 * in_0_0_0) + in_0_0_m1) / (float)8); - return (cal1 + cal2 + cal3 + in_0_0_0); -} // stencil kernel definition - -void HEAT3D(tapa::istream&in, tapa::ostream&out, //int useless, - int iters) -{ - INTERFACE_WIDTH in_block_m16; - hls::stream in_stream_m15_to_m2; - INTERFACE_WIDTH in_block_m1; - INTERFACE_WIDTH in_block_0; - INTERFACE_WIDTH in_block_1; - hls::stream in_stream_2_to_15; - INTERFACE_WIDTH in_block_16; - - in_block_m16 = in.read(); - for (int i = 16 + -15; i < 16 + -1; i++) { - in_stream_m15_to_m2 << in.read(); - } - in_block_m1 = in.read(); - in_block_0 = in.read(); - in_block_1 = in.read(); - for (int i = 16 + 2; i < 16 + 16; i++) { - in_stream_2_to_15 << in.read(); - } - in_block_16 = in.read(); - - MAJOR_LOOP: - for (int i = 0; i < GRID_COLS/WIDTH_FACTOR*PART_ROWS + (TOP_APPEND+BOTTOM_APPEND)*(iters-1); i++) { - #pragma HLS pipeline II=1 - INTERFACE_WIDTH out_temp; - COMPUTE_LOOP: - for (int k = 0; k < PARA_FACTOR; k++) { - #pragma HLS unroll - float in_1_0_0[PARA_FACTOR], in_0_0_1[PARA_FACTOR], in_0_0_m1[PARA_FACTOR], in_0_0_0[PARA_FACTOR], in_0_m1_0[PARA_FACTOR], in_m1_0_0[PARA_FACTOR], in_0_1_0[PARA_FACTOR]; - #pragma HLS array_partition variable=in_1_0_0 complete dim=0 - #pragma HLS array_partition variable=in_0_0_1 complete dim=0 - #pragma HLS array_partition variable=in_0_0_m1 complete dim=0 - #pragma HLS array_partition variable=in_0_0_0 complete dim=0 - #pragma HLS array_partition variable=in_0_m1_0 complete dim=0 - #pragma HLS array_partition variable=in_m1_0_0 complete dim=0 - #pragma HLS array_partition variable=in_0_1_0 complete dim=0 - - - unsigned int idx_k = k << 5; - - uint32_t temp_in_1_0_0 = in_block_16.range(idx_k+31, idx_k); - in_1_0_0[k] = *((float*)(&temp_in_1_0_0)); - uint32_t temp_in_0_0_1 = (k<15)?in_block_0.range(idx_k + 63, idx_k + 32) : in_block_1.range(idx_k + -449, idx_k + -480); - in_0_0_1[k] = *((float*)(&temp_in_0_0_1)); - uint32_t temp_in_0_0_m1 = (k<1)?in_block_m1.range(idx_k + 511, idx_k + 480) : in_block_0.range(idx_k + -1, idx_k + -32); - in_0_0_m1[k] = *((float*)(&temp_in_0_0_m1)); - uint32_t temp_in_0_0_0 = in_block_0.range(idx_k+31, idx_k); - in_0_0_0[k] = *((float*)(&temp_in_0_0_0)); - uint32_t temp_in_0_m1_0 = in_block_m1.range(idx_k+31, idx_k); - in_0_m1_0[k] = *((float*)(&temp_in_0_m1_0)); - uint32_t temp_in_m1_0_0 = in_block_m16.range(idx_k+31, idx_k); - in_m1_0_0[k] = *((float*)(&temp_in_m1_0_0)); - uint32_t temp_in_0_1_0 = in_block_1.range(idx_k+31, idx_k); - in_0_1_0[k] = *((float*)(&temp_in_0_1_0)); - - float result = HEAT3D_stencil_kernel(in_1_0_0[k], in_0_0_1[k], in_0_0_m1[k], in_0_0_0[k], in_0_m1_0[k], in_m1_0_0[k], in_0_1_0[k]); - out_temp.range(idx_k+31, idx_k) = *((uint32_t *)(&result)); - } - out.write(out_temp); - - in_block_m16 = in_stream_m15_to_m2.read(); - in_stream_m15_to_m2 << HLS_REG(in_block_m1); - in_block_m1 = HLS_REG(in_block_0); - in_block_0 = HLS_REG(in_block_1); - in_block_1 = in_stream_2_to_15.read(); - in_stream_2_to_15 << HLS_REG(in_block_16); - - unsigned int idx_in = 16 + (i + 17); - in_block_16 = HLS_REG(in.read()); - } - - INTERFACE_WIDTH popout_in_stream_m15_to_m2; - for (int i = 0; i < 14; i++) { - #pragma HLS pipeline II=1 - in_stream_m15_to_m2 >> popout_in_stream_m15_to_m2; - } - INTERFACE_WIDTH popout_in_stream_2_to_15; - for (int i = 0; i < 14; i++) { - #pragma HLS pipeline II=1 - in_stream_2_to_15 >> popout_in_stream_2_to_15; - } - return; -} // stencil kernel definition - -void load(tapa::async_mmap& a, tapa::async_mmap& b, - tapa::ostream &stream_out, tapa::istream &stream_in, - uint32_t iters) { - #pragma HLS inline off - unsigned int loop_bound = GRID_COLS/WIDTH_FACTOR*PART_ROWS + (TOP_APPEND+BOTTOM_APPEND)*(iters-1) + 17 + 16; - - for(int k_wr_req = (17 + 16), k_wr_resp = (17 + 16), k_rd_req = 0, k_rd_resp = 0; k_rd_resp < loop_bound || k_wr_resp < loop_bound; ) { - // read from a - if (k_rd_req < loop_bound && a.read_addr.try_write(k_rd_req)) { - k_rd_req++; - } - if (k_rd_resp < loop_bound && !a.read_data.empty() && !stream_out.full()) { - INTERFACE_WIDTH temp = a.read_data.read(nullptr); - stream_out.write(temp); - k_rd_resp++; - } - - // write to b - if (k_wr_req < loop_bound && !b.write_addr.full() && !b.write_data.full() && !stream_in.empty()) { - b.write_addr.write(k_wr_req); - b.write_data.write(stream_in.read()); - k_wr_req++; - } - if (!b.write_resp.empty()) { - k_wr_resp += (unsigned int)(b.write_resp.read()) + 1; - } - } -} - -void inter_kernel(tapa::async_mmap& a, tapa::async_mmap& b, - tapa::ostream &stream_out, tapa::istream &stream_in, - uint32_t iters){ - - for(int i = 0; i < iters; i+=STAGE_COUNT){ - if(i%(2*STAGE_COUNT)==0){ - load(a, b, stream_out, stream_in, iters); - } - else{ - load(b, a, stream_out, stream_in, iters); - } - } -} - -void unikernel(tapa::mmap in_0, tapa::mmap out_0, //HBM 0 1 - tapa::mmap in_1, tapa::mmap out_1, - tapa::mmap in_2, tapa::mmap out_2, - tapa::mmap in_3, tapa::mmap out_3, - tapa::mmap in_4, tapa::mmap out_4, - tapa::mmap in_5, tapa::mmap out_5, - tapa::mmap in_6, tapa::mmap out_6, - tapa::mmap in_7, tapa::mmap out_7, - tapa::mmap in_8, tapa::mmap out_8, - tapa::mmap in_9, tapa::mmap out_9, - tapa::mmap in_10, tapa::mmap out_10, - tapa::mmap in_11, tapa::mmap out_11, - // tapa::mmap in_12, tapa::mmap out_12, - // tapa::mmap in_13, tapa::mmap out_13, - // tapa::mmap in_14, tapa::mmap out_14, - uint32_t iters){ - tapa::streams k_wr; - tapa::streams k_rd; - - tapa::task() - .invoke(inter_kernel, in_0, out_0, k_rd[0], k_wr[0], iters) - .invoke(HEAT3D, k_rd[0], k_wr[0], iters) - .invoke(inter_kernel, in_1, out_1, k_rd[1], k_wr[1], iters) - .invoke(HEAT3D, k_rd[1], k_wr[1], iters) - .invoke(inter_kernel, in_2, out_2, k_rd[2], k_wr[2], iters) - .invoke(HEAT3D, k_rd[2], k_wr[2], iters) - .invoke(inter_kernel, in_3, out_3, k_rd[3], k_wr[3], iters) - .invoke(HEAT3D, k_rd[3], k_wr[3], iters) - .invoke(inter_kernel, in_4, out_4, k_rd[4], k_wr[4], iters) - .invoke(HEAT3D, k_rd[4], k_wr[4], iters) - .invoke(inter_kernel, in_5, out_5, k_rd[5], k_wr[5], iters) - .invoke(HEAT3D, k_rd[5], k_wr[5], iters) - .invoke(inter_kernel, in_6, out_6, k_rd[6], k_wr[6], iters) - .invoke(HEAT3D, k_rd[6], k_wr[6], iters) - .invoke(inter_kernel, in_7, out_7, k_rd[7], k_wr[7], iters) - .invoke(HEAT3D, k_rd[7], k_wr[7], iters) - .invoke(inter_kernel, in_8, out_8, k_rd[8], k_wr[8], iters) - .invoke(HEAT3D, k_rd[8], k_wr[8], iters) - .invoke(inter_kernel, in_9, out_9, k_rd[9], k_wr[9], iters) - .invoke(HEAT3D, k_rd[9], k_wr[9], iters) - .invoke(inter_kernel, in_10, out_10, k_rd[10], k_wr[10], iters) - .invoke(HEAT3D, k_rd[10], k_wr[10], iters) - .invoke(inter_kernel, in_11, out_11, k_rd[11], k_wr[11], iters) - .invoke(HEAT3D, k_rd[11], k_wr[11], iters) - // .invoke(inter_kernel, in_12, out_12, k_rd[12], k_wr[12], iters) - // .invoke(HEAT3D, k_rd[12], k_wr[12], iters) - // .invoke(inter_kernel, in_13, out_13, k_rd[13], k_wr[13], iters) - // .invoke(HEAT3D, k_rd[13], k_wr[13], iters) - // .invoke(inter_kernel, in_14, out_14, k_rd[14], k_wr[14], iters) - // .invoke(HEAT3D, k_rd[14], k_wr[14], iters) - ; -} diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/run.py b/benchmarks/tapa_flow/stencil_sasa/medium_congestion/run.py deleted file mode 100644 index 9bc48294..00000000 --- a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/run.py +++ /dev/null @@ -1,134 +0,0 @@ -__copyright__ = """ -Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. -The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -""" - -from rapidstream import get_u280_vitis_device_factory, RapidStreamTAPA -import os - -CURR_DIR = os.path.dirname(os.path.abspath(__file__)) -INI_PATH = f"{CURR_DIR}/design/config/link_config.ini" -VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1" -XO_PATH = f"{CURR_DIR}/design/generated/unikernel.xo" -kernel_name = "unikernel" - -factory = get_u280_vitis_device_factory(VITIS_PLATFORM) - -# Reserve resource for the HBM Memory Sub-System. -# The HMSS is not part of the user kernel so the partition optimization process -# is unaware of its existence. We need to manually reserve resources for it. -# For 512-bit HBM channels, each HBM channel uses approximately the following resources: -# AREA_PER_HBM_CHANNEL = { -# "LUT": 5000, -# "FF": 6500, -# "BRAM": 0, -# "URAM": 0, -# "DSP": 0, -# } -factory.reduce_slot_area(1, 0, lut=5000 * 16, ff=6500 * 16) -factory.reduce_slot_area(0, 0, lut=5000 * 13, ff=6500 * 13) - -# For this U280 platform, the right most DSP column on the boundary between -# dynamic/static region is not usable. So we need to adjust the DSP count -# to reflect the actual available DSPs. -print("Reducing DSP of (1, 1) to make it less congested") -factory.reduce_slot_area(1, 1, dsp=100) - -rs = RapidStreamTAPA(f"{CURR_DIR}/build") - -rs.set_virtual_device(factory.generate_virtual_device()) -rs.add_xo_file(XO_PATH) -rs.set_vitis_platform(VITIS_PLATFORM) -rs.set_vitis_connectivity_config(INI_PATH) - -rs.set_top_module_name(kernel_name) -rs.add_clock("ap_clk", 3.33) - -rs.add_flatten_targets([kernel_name]) - -# Bind ports to HBM 16-31 -right_slot = "SLOT_X1Y0:SLOT_X1Y0" -left_slot = "SLOT_X0Y0:SLOT_X0Y0" -# The config file binds the following argument to HBM 0 - 15 -# sp=unikernel.in_0:HBM[0] -# sp=unikernel.out_0:HBM[1] -# sp=unikernel.in_1:HBM[2] -# sp=unikernel.out_1:HBM[3] -# sp=unikernel.in_2:HBM[4] -# sp=unikernel.out_2:HBM[5] -# sp=unikernel.in_3:HBM[6] -# sp=unikernel.out_3:HBM[7] -# sp=unikernel.in_4:HBM[8] -# sp=unikernel.out_4:HBM[9] -# sp=unikernel.in_5:HBM[10] -# sp=unikernel.out_5:HBM[11] -# sp=unikernel.in_6:HBM[12] -# sp=unikernel.out_6:HBM[13] -# sp=unikernel.in_7:HBM[14] -# sp=unikernel.out_7:HBM[15] - -left_args = [ - "in_0", - "out_0", - "in_1", - "out_1", - "in_2", - "out_2", - "in_3", - "out_3", - "in_4", - "out_4", - "in_5", - "out_5", - "in_6", - "out_6", - "in_7", - "out_7", -] - - -for arg in left_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", left_slot) - -# The config file binds the following argument to HBM 16 - 31 -# sp=unikernel.in_8:HBM[17] -# sp=unikernel.out_8:HBM[18] -# sp=unikernel.in_9:HBM[19] -# sp=unikernel.out_9:HBM[20] -# sp=unikernel.in_10:HBM[21] -# sp=unikernel.out_10:HBM[22] -# sp=unikernel.in_11:HBM[23] -# sp=unikernel.out_11:HBM[24] - -right_args = [ - "in_8", - "out_8", - "in_9", - "out_9", - "in_10", - "out_10", - "in_11", - "out_11", -] - -for arg in right_args: - rs.assign_port_to_region(f"m_axi_{arg}_.*", right_slot) - - -# Constrain the remaining control ports. -# All ports must be constrained to a specific slot: -rs.assign_port_to_region("s_axi_control_.*", left_slot) -rs.assign_port_to_region("ap_clk", left_slot) -rs.assign_port_to_region("ap_rst_n", left_slot) -rs.assign_port_to_region("interrupt", left_slot) - -# Xustomize the placement strategy: -rs.set_placement_strategy("EarlyBlockPlacement") - -# Allow two parallel Vitis implementation -rs.run_dse( - max_workers=2, - max_dse_limit=0.85, - min_dse_limit=0.75, - partition_strategy="flat", -) diff --git a/benchmarks/vitis_flow/LLM/Makefile b/benchmarks/vitis_flow/LLM/Makefile index d8c339ba..d7ee1faf 100644 --- a/benchmarks/vitis_flow/LLM/Makefile +++ b/benchmarks/vitis_flow/LLM/Makefile @@ -1,24 +1,30 @@ # Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -ROOT_DIR := $(shell git rev-parse --show-toplevel) -GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py -PLATFORM := xilinx_u50_gen3x16_xdma_5_202210_1 -KERNEL_NAME := bert_all -HLSXX := vitis_hls -HLS_SRC_DIR := $(CURDIR)/design -HLS_SRC_FILES := $(foreach n, $(shell seq 1 3 ), $(HLS_SRC_DIR)/bert_region_$(n).cpp) -HLS_SRC_FILES += $(foreach n, $(shell seq 1 3 ), $(HLS_SRC_DIR)/bert_region_$(n).h) -HLS_SRC_FILES += $(HLS_SRC_DIR)/bert_all.cpp $(HLS_SRC_DIR)/kernel.h - -TEMP_DIR := $(CURDIR)/build -KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo -KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin -RS_XCLBIN := $(TEMP_DIR)/dse/candidate_0/design.xclbin -CLK_PERIOD_NS := 3 -TARGET := hw -HLS2RTL_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl -GEN_XO := 1 +ROOT_DIR := $(shell git rev-parse --show-toplevel) +GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py +PLATFORM := xilinx_u280_gen3x16_xdma_1_202211_1 +KERNEL_NAME := bert_all +HLSXX := vitis_hls +HLS_SRC_DIR := $(CURDIR)/design +HLS_SRC_FILES := $(foreach n, $(shell seq 1 3 ), $(HLS_SRC_DIR)/bert_region_$(n).cpp) +HLS_SRC_FILES += $(foreach n, $(shell seq 1 3 ), $(HLS_SRC_DIR)/bert_region_$(n).h) +HLS_SRC_FILES += $(HLS_SRC_DIR)/bert_all.cpp $(HLS_SRC_DIR)/kernel.h + +TEMP_DIR := $(CURDIR)/build +KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo +KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin +RS_XCLBIN := $(TEMP_DIR)/dse/candidate_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin +CLK_PERIOD_NS := 3 +TARGET := hw +HLS2RTL_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl +GEN_XO := 1 + +BUILD_LOG := $(TEMP_DIR)/build.json +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/dse/candidate_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).temp/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py + ifeq ($(PLATFORM), xilinx_u50_gen3x16_xdma_5_202210_1) PART := xcu50-fsvh2104-2-e @@ -41,6 +47,8 @@ else endif all: $(RS_XCLBIN) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) $(RS_XCLBIN):$(KERNEL_XO) rapidstream $(RUN_FILE) diff --git a/benchmarks/vitis_flow/LLM/design/bert_all.cpp b/benchmarks/vitis_flow/LLM/design/bert_all.cpp index c3d8cb9a..58070a0d 100644 --- a/benchmarks/vitis_flow/LLM/design/bert_all.cpp +++ b/benchmarks/vitis_flow/LLM/design/bert_all.cpp @@ -115,3 +115,109 @@ void bert_all( ); } } + + +void k1( + io_pack_float *inp_addr_0, + io_pack_float *inp_addr_1, + io_pack_float *inp_addr_2, + io_pack_int16 *wk_addr, + io_pack_int16 *wv_addr, + io_pack_int16 *wq_addr, + hls::stream& stream_out +){ + uint32_t out = 0; + out = inp_addr_0[0] + inp_addr_1[0] + inp_addr_2[0] + wk_addr[0] + wv_addr[0] + wq_addr[0]; + stream_out.write(out); +} + + +void k2( + io_pack_int16 *w_ds0_addr, + double_io_pack_int16 *w_ds1_addr, + double_io_pack_int16 *w_ds2_addr, + hls::stream& stream_out + +){ + uint32_t out = 0; + out = w_ds0_addr[0] + w_ds1_addr[0] + w_ds2_addr[0]; + stream_out.write(out); +} + +void k3( + hls::stream& stream_in1, + hls::stream& stream_in2, + hls::stream& stream_out +){ + float out = 0; + float a = 0; + float b = 0; + a = stream_in1.read(); + b = stream_in2.read(); + out = a * b; + stream_out.write(out); + +} + +void k4( + hls::stream& stream_in, + io_pack_float *outp_addr +){ + float out = 0; + out = stream_in.read(); + outp_addr[0] = out; +} + + +extern "C" { +void bert_all1( + io_pack_float *inp_addr_0, + io_pack_float *inp_addr_1, + io_pack_float *inp_addr_2, + io_pack_int16 *wk_addr, + io_pack_int16 *wv_addr, + io_pack_int16 *wq_addr, + io_pack_int16 *w_ds0_addr, + double_io_pack_int16 *w_ds1_addr, + double_io_pack_int16 *w_ds2_addr, + io_pack_float *outp_addr +){ + #pragma HLS interface m_axi port=inp_addr_0 offset=slave bundle=gmem0 + #pragma HLS interface m_axi port=inp_addr_1 offset=slave bundle=gmem1 + #pragma HLS interface m_axi port=inp_addr_2 offset=slave bundle=gmem2 + #pragma HLS interface m_axi port=wk_addr offset=slave bundle=gmem3 + #pragma HLS interface m_axi port=wv_addr offset=slave bundle=gmem4 + #pragma HLS interface m_axi port=wq_addr offset=slave bundle=gmem5 + #pragma HLS interface m_axi port=w_ds0_addr offset=slave bundle=gmem6 + #pragma HLS interface m_axi port=w_ds1_addr offset=slave bundle=gmem7 + #pragma HLS interface m_axi port=w_ds2_addr offset=slave bundle=gmem8 + #pragma HLS interface m_axi port=outp_addr offset=slave bundle=gmem9 + + #pragma HLS INTERFACE s_axilite port=inp_addr_0 bundle=control + #pragma HLS INTERFACE s_axilite port=inp_addr_1 bundle=control + #pragma HLS INTERFACE s_axilite port=inp_addr_2 bundle=control + #pragma HLS INTERFACE s_axilite port=wk_addr bundle=control + #pragma HLS INTERFACE s_axilite port=wv_addr bundle=control + #pragma HLS INTERFACE s_axilite port=wq_addr bundle=control + #pragma HLS INTERFACE s_axilite port=w_ds0_addr bundle=control + #pragma HLS INTERFACE s_axilite port=w_ds1_addr bundle=control + #pragma HLS INTERFACE s_axilite port=w_ds2_addr bundle=control + #pragma HLS INTERFACE s_axilite port=outp_addr bundle=control + + #pragma HLS INTERFACE s_axilite port=return bundle=control + + static hls::stream stream_in1("input_stream_1"); + static hls::stream stream_in2("input_stream_2"); + static hls::stream stream_in3("input_stream_3"); + static hls::stream stream_in4("input_stream_4"); + static hls::stream stream_in5("input_stream_5"); + static hls::stream stream_in6("input_stream_6"); + static hls::stream stream_in7("input_stream_7"); + +#pragma HLS dataflow + k1(inp_addr_0, inp_addr_1, inp_addr_2, wk_addr, wv_addr, wq_addr, stream_in1); + k2(w_ds0_addr, w_ds1_addr, w_ds2_addr, stream_in2); + k3(stream_in1, stream_in2, stream_in3); + k4(stream_in3, outp_addr); +} +} diff --git a/benchmarks/vitis_flow/README.md b/benchmarks/vitis_flow/README.md index afebed07..06c460b8 100644 --- a/benchmarks/vitis_flow/README.md +++ b/benchmarks/vitis_flow/README.md @@ -22,7 +22,7 @@ The figures below demonstrate how RapidStream seamlessly integrates with the Vit Figure (b) illustrates the integration of RapidStream with the Vitis flow. Users continue to leverage Vitis HLS for compiling dataflow HLS C++ code into an Xilinx Objective file (`.xo`). Subsequently, RapidStream processes the `.xo` file, seamlessly implementing transformations like partitioning, floorplanning, and pipeline insertion. The optimized design is then re-packaged into another `.xo` file format, which can be integrated with standard Vitis tools to target FPGA devices for generating executable bitstreams (`xclbin`). -RapidStream Logo +vitis_rapidstream_flow Compared to the standard Vitis flow, the RapidStream-aided Vitis flow shows distinct advantages in layout generation. The standard implementation tends to consolidate all logic within a single SLR (Super Logic Region), which can lead to local routing congestion. In contrast, RapidStream distributes the logic across four separate slots, effectively mitigating this congestion. Additionally, by incorporating pipeline registers after floorplanning, the extended route wires are less likely to impact the clock frequency negatively. diff --git a/benchmarks/vitis_flow/cnn13x2/Makefile b/benchmarks/vitis_flow/cnn13x2/Makefile index d45313c1..aa6da56c 100644 --- a/benchmarks/vitis_flow/cnn13x2/Makefile +++ b/benchmarks/vitis_flow/cnn13x2/Makefile @@ -19,6 +19,10 @@ HOST := app.exe HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl CLK_PERIOD_NS := 4 RS_TARGET := $(TEMP_DIR)/dse/candidate_0/exported/$(KERNEL_NAME).xo +BUILD_LOG := $(TEMP_DIR)/build.json +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py ifeq ($(PLATFORM), xilinx_u50_gen3x16_xdma_5_202210_1) PART := xcu50-fsvh2104-2-e @@ -41,6 +45,8 @@ else endif all: $(RS_KERNEL_XCLBIN) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) sw_emu: $(KERNEL_XCLBIN) $(HOST) XCL_EMULATION_MODE=sw_emu ./app.exe $< diff --git a/benchmarks/vitis_flow/cnn13x4_16/cnn13x10/Makefile b/benchmarks/vitis_flow/cnn13x4_16/cnn13x10/Makefile index 4fb149f4..4c090507 100644 --- a/benchmarks/vitis_flow/cnn13x4_16/cnn13x10/Makefile +++ b/benchmarks/vitis_flow/cnn13x4_16/cnn13x10/Makefile @@ -2,35 +2,53 @@ # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -ROOT_DIR := $(shell git rev-parse --show-toplevel) -GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py -PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 -PART := xcu250-figd2104-2L-e -RUN_FILE := run.py -LINK_FILE := link_config.ini -KERNEL_NAME := kernel3 -SRC_DIR := $(CURDIR)/design -TARGET := hw -TEMP_DIR := $(CURDIR)/build -KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo -KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin -INCLUDE := -I $(XILINX_HLS)/include -CFLAGS := $(INCLUDE) $(OPT_LEVEL) -CXX := g++ -HOST := app.exe -HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl -CLK_PERIOD_NS := 4 - - - -all:rs_opt +ROOT_DIR := $(shell git rev-parse --show-toplevel) +GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py +PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 +PART := xcu250-figd2104-2L-e +RUN_FILE := run.py +LINK_FILE := link_config.ini +KERNEL_NAME := kernel3 +SRC_DIR := $(CURDIR)/design +TARGET := hw +TEMP_DIR := $(CURDIR)/build +KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo +KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin +RS_KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME)_rs.xclbin +INCLUDE := -I $(XILINX_HLS)/include +CFLAGS := $(INCLUDE) $(OPT_LEVEL) +CXX := g++ +HOST := app.exe +HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl +CLK_PERIOD_NS := 4 +RS_TARGET := $(TEMP_DIR)/dse/candidate_0/exported/$(KERNEL_NAME).xo +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt +BUILD_LOG := $(TEMP_DIR)/build.json + +all: $(RS_KERNEL_XCLBIN) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) sw_emu: $(KERNEL_XCLBIN) $(HOST) XCL_EMULATION_MODE=sw_emu ./app.exe $< hw: $(KERNEL_XCLBIN) $(HOST) -rs_opt:$(KERNEL_XO) +$(RS_KERNEL_XCLBIN): $(RS_TARGET) + v++ -l -t ${TARGET} \ + --platform $(PLATFORM) \ + --kernel $(KERNEL_NAME) \ + --connectivity.nk $(KERNEL_NAME):1:$(KERNEL_NAME) \ + --config $(SRC_DIR)/$(LINK_FILE) \ + --temp_dir $(TEMP_DIR) \ + -o $@ \ + $^ + +rs_opt:$(RS_TARGET) + +$(RS_TARGET): $(KERNEL_XO) rapidstream $(RUN_FILE) $(KERNEL_XCLBIN): $(KERNEL_XO) @@ -80,7 +98,6 @@ show_groups: - clean: rm -rf $(TEMP_DIR) *.log rm -rf .Xil .run diff --git a/benchmarks/vitis_flow/cnn13x4_16/cnn13x12/Makefile b/benchmarks/vitis_flow/cnn13x4_16/cnn13x12/Makefile index 4fb149f4..4c090507 100644 --- a/benchmarks/vitis_flow/cnn13x4_16/cnn13x12/Makefile +++ b/benchmarks/vitis_flow/cnn13x4_16/cnn13x12/Makefile @@ -2,35 +2,53 @@ # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -ROOT_DIR := $(shell git rev-parse --show-toplevel) -GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py -PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 -PART := xcu250-figd2104-2L-e -RUN_FILE := run.py -LINK_FILE := link_config.ini -KERNEL_NAME := kernel3 -SRC_DIR := $(CURDIR)/design -TARGET := hw -TEMP_DIR := $(CURDIR)/build -KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo -KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin -INCLUDE := -I $(XILINX_HLS)/include -CFLAGS := $(INCLUDE) $(OPT_LEVEL) -CXX := g++ -HOST := app.exe -HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl -CLK_PERIOD_NS := 4 - - - -all:rs_opt +ROOT_DIR := $(shell git rev-parse --show-toplevel) +GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py +PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 +PART := xcu250-figd2104-2L-e +RUN_FILE := run.py +LINK_FILE := link_config.ini +KERNEL_NAME := kernel3 +SRC_DIR := $(CURDIR)/design +TARGET := hw +TEMP_DIR := $(CURDIR)/build +KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo +KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin +RS_KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME)_rs.xclbin +INCLUDE := -I $(XILINX_HLS)/include +CFLAGS := $(INCLUDE) $(OPT_LEVEL) +CXX := g++ +HOST := app.exe +HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl +CLK_PERIOD_NS := 4 +RS_TARGET := $(TEMP_DIR)/dse/candidate_0/exported/$(KERNEL_NAME).xo +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt +BUILD_LOG := $(TEMP_DIR)/build.json + +all: $(RS_KERNEL_XCLBIN) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) sw_emu: $(KERNEL_XCLBIN) $(HOST) XCL_EMULATION_MODE=sw_emu ./app.exe $< hw: $(KERNEL_XCLBIN) $(HOST) -rs_opt:$(KERNEL_XO) +$(RS_KERNEL_XCLBIN): $(RS_TARGET) + v++ -l -t ${TARGET} \ + --platform $(PLATFORM) \ + --kernel $(KERNEL_NAME) \ + --connectivity.nk $(KERNEL_NAME):1:$(KERNEL_NAME) \ + --config $(SRC_DIR)/$(LINK_FILE) \ + --temp_dir $(TEMP_DIR) \ + -o $@ \ + $^ + +rs_opt:$(RS_TARGET) + +$(RS_TARGET): $(KERNEL_XO) rapidstream $(RUN_FILE) $(KERNEL_XCLBIN): $(KERNEL_XO) @@ -80,7 +98,6 @@ show_groups: - clean: rm -rf $(TEMP_DIR) *.log rm -rf .Xil .run diff --git a/benchmarks/vitis_flow/cnn13x4_16/cnn13x14/Makefile b/benchmarks/vitis_flow/cnn13x4_16/cnn13x14/Makefile index 4fb149f4..4c090507 100644 --- a/benchmarks/vitis_flow/cnn13x4_16/cnn13x14/Makefile +++ b/benchmarks/vitis_flow/cnn13x4_16/cnn13x14/Makefile @@ -2,35 +2,53 @@ # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -ROOT_DIR := $(shell git rev-parse --show-toplevel) -GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py -PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 -PART := xcu250-figd2104-2L-e -RUN_FILE := run.py -LINK_FILE := link_config.ini -KERNEL_NAME := kernel3 -SRC_DIR := $(CURDIR)/design -TARGET := hw -TEMP_DIR := $(CURDIR)/build -KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo -KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin -INCLUDE := -I $(XILINX_HLS)/include -CFLAGS := $(INCLUDE) $(OPT_LEVEL) -CXX := g++ -HOST := app.exe -HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl -CLK_PERIOD_NS := 4 - - - -all:rs_opt +ROOT_DIR := $(shell git rev-parse --show-toplevel) +GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py +PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 +PART := xcu250-figd2104-2L-e +RUN_FILE := run.py +LINK_FILE := link_config.ini +KERNEL_NAME := kernel3 +SRC_DIR := $(CURDIR)/design +TARGET := hw +TEMP_DIR := $(CURDIR)/build +KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo +KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin +RS_KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME)_rs.xclbin +INCLUDE := -I $(XILINX_HLS)/include +CFLAGS := $(INCLUDE) $(OPT_LEVEL) +CXX := g++ +HOST := app.exe +HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl +CLK_PERIOD_NS := 4 +RS_TARGET := $(TEMP_DIR)/dse/candidate_0/exported/$(KERNEL_NAME).xo +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt +BUILD_LOG := $(TEMP_DIR)/build.json + +all: $(RS_KERNEL_XCLBIN) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) sw_emu: $(KERNEL_XCLBIN) $(HOST) XCL_EMULATION_MODE=sw_emu ./app.exe $< hw: $(KERNEL_XCLBIN) $(HOST) -rs_opt:$(KERNEL_XO) +$(RS_KERNEL_XCLBIN): $(RS_TARGET) + v++ -l -t ${TARGET} \ + --platform $(PLATFORM) \ + --kernel $(KERNEL_NAME) \ + --connectivity.nk $(KERNEL_NAME):1:$(KERNEL_NAME) \ + --config $(SRC_DIR)/$(LINK_FILE) \ + --temp_dir $(TEMP_DIR) \ + -o $@ \ + $^ + +rs_opt:$(RS_TARGET) + +$(RS_TARGET): $(KERNEL_XO) rapidstream $(RUN_FILE) $(KERNEL_XCLBIN): $(KERNEL_XO) @@ -80,7 +98,6 @@ show_groups: - clean: rm -rf $(TEMP_DIR) *.log rm -rf .Xil .run diff --git a/benchmarks/vitis_flow/cnn13x4_16/cnn13x16/Makefile b/benchmarks/vitis_flow/cnn13x4_16/cnn13x16/Makefile index 4fb149f4..4c090507 100644 --- a/benchmarks/vitis_flow/cnn13x4_16/cnn13x16/Makefile +++ b/benchmarks/vitis_flow/cnn13x4_16/cnn13x16/Makefile @@ -2,35 +2,53 @@ # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -ROOT_DIR := $(shell git rev-parse --show-toplevel) -GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py -PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 -PART := xcu250-figd2104-2L-e -RUN_FILE := run.py -LINK_FILE := link_config.ini -KERNEL_NAME := kernel3 -SRC_DIR := $(CURDIR)/design -TARGET := hw -TEMP_DIR := $(CURDIR)/build -KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo -KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin -INCLUDE := -I $(XILINX_HLS)/include -CFLAGS := $(INCLUDE) $(OPT_LEVEL) -CXX := g++ -HOST := app.exe -HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl -CLK_PERIOD_NS := 4 - - - -all:rs_opt +ROOT_DIR := $(shell git rev-parse --show-toplevel) +GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py +PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 +PART := xcu250-figd2104-2L-e +RUN_FILE := run.py +LINK_FILE := link_config.ini +KERNEL_NAME := kernel3 +SRC_DIR := $(CURDIR)/design +TARGET := hw +TEMP_DIR := $(CURDIR)/build +KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo +KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin +RS_KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME)_rs.xclbin +INCLUDE := -I $(XILINX_HLS)/include +CFLAGS := $(INCLUDE) $(OPT_LEVEL) +CXX := g++ +HOST := app.exe +HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl +CLK_PERIOD_NS := 4 +RS_TARGET := $(TEMP_DIR)/dse/candidate_0/exported/$(KERNEL_NAME).xo +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt +BUILD_LOG := $(TEMP_DIR)/build.json + +all: $(RS_KERNEL_XCLBIN) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) sw_emu: $(KERNEL_XCLBIN) $(HOST) XCL_EMULATION_MODE=sw_emu ./app.exe $< hw: $(KERNEL_XCLBIN) $(HOST) -rs_opt:$(KERNEL_XO) +$(RS_KERNEL_XCLBIN): $(RS_TARGET) + v++ -l -t ${TARGET} \ + --platform $(PLATFORM) \ + --kernel $(KERNEL_NAME) \ + --connectivity.nk $(KERNEL_NAME):1:$(KERNEL_NAME) \ + --config $(SRC_DIR)/$(LINK_FILE) \ + --temp_dir $(TEMP_DIR) \ + -o $@ \ + $^ + +rs_opt:$(RS_TARGET) + +$(RS_TARGET): $(KERNEL_XO) rapidstream $(RUN_FILE) $(KERNEL_XCLBIN): $(KERNEL_XO) @@ -80,7 +98,6 @@ show_groups: - clean: rm -rf $(TEMP_DIR) *.log rm -rf .Xil .run diff --git a/benchmarks/vitis_flow/cnn13x4_16/cnn13x4/Makefile b/benchmarks/vitis_flow/cnn13x4_16/cnn13x4/Makefile index 04eaf99b..4c090507 100644 --- a/benchmarks/vitis_flow/cnn13x4_16/cnn13x4/Makefile +++ b/benchmarks/vitis_flow/cnn13x4_16/cnn13x4/Makefile @@ -22,9 +22,14 @@ HOST := app.exe HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl CLK_PERIOD_NS := 4 RS_TARGET := $(TEMP_DIR)/dse/candidate_0/exported/$(KERNEL_NAME).xo - +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt +BUILD_LOG := $(TEMP_DIR)/build.json all: $(RS_KERNEL_XCLBIN) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) sw_emu: $(KERNEL_XCLBIN) $(HOST) XCL_EMULATION_MODE=sw_emu ./app.exe $< diff --git a/benchmarks/vitis_flow/cnn13x4_16/cnn13x6/Makefile b/benchmarks/vitis_flow/cnn13x4_16/cnn13x6/Makefile index 4fb149f4..4c090507 100644 --- a/benchmarks/vitis_flow/cnn13x4_16/cnn13x6/Makefile +++ b/benchmarks/vitis_flow/cnn13x4_16/cnn13x6/Makefile @@ -2,35 +2,53 @@ # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -ROOT_DIR := $(shell git rev-parse --show-toplevel) -GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py -PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 -PART := xcu250-figd2104-2L-e -RUN_FILE := run.py -LINK_FILE := link_config.ini -KERNEL_NAME := kernel3 -SRC_DIR := $(CURDIR)/design -TARGET := hw -TEMP_DIR := $(CURDIR)/build -KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo -KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin -INCLUDE := -I $(XILINX_HLS)/include -CFLAGS := $(INCLUDE) $(OPT_LEVEL) -CXX := g++ -HOST := app.exe -HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl -CLK_PERIOD_NS := 4 - - - -all:rs_opt +ROOT_DIR := $(shell git rev-parse --show-toplevel) +GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py +PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 +PART := xcu250-figd2104-2L-e +RUN_FILE := run.py +LINK_FILE := link_config.ini +KERNEL_NAME := kernel3 +SRC_DIR := $(CURDIR)/design +TARGET := hw +TEMP_DIR := $(CURDIR)/build +KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo +KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin +RS_KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME)_rs.xclbin +INCLUDE := -I $(XILINX_HLS)/include +CFLAGS := $(INCLUDE) $(OPT_LEVEL) +CXX := g++ +HOST := app.exe +HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl +CLK_PERIOD_NS := 4 +RS_TARGET := $(TEMP_DIR)/dse/candidate_0/exported/$(KERNEL_NAME).xo +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt +BUILD_LOG := $(TEMP_DIR)/build.json + +all: $(RS_KERNEL_XCLBIN) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) sw_emu: $(KERNEL_XCLBIN) $(HOST) XCL_EMULATION_MODE=sw_emu ./app.exe $< hw: $(KERNEL_XCLBIN) $(HOST) -rs_opt:$(KERNEL_XO) +$(RS_KERNEL_XCLBIN): $(RS_TARGET) + v++ -l -t ${TARGET} \ + --platform $(PLATFORM) \ + --kernel $(KERNEL_NAME) \ + --connectivity.nk $(KERNEL_NAME):1:$(KERNEL_NAME) \ + --config $(SRC_DIR)/$(LINK_FILE) \ + --temp_dir $(TEMP_DIR) \ + -o $@ \ + $^ + +rs_opt:$(RS_TARGET) + +$(RS_TARGET): $(KERNEL_XO) rapidstream $(RUN_FILE) $(KERNEL_XCLBIN): $(KERNEL_XO) @@ -80,7 +98,6 @@ show_groups: - clean: rm -rf $(TEMP_DIR) *.log rm -rf .Xil .run diff --git a/benchmarks/vitis_flow/cnn13x4_16/cnn13x8/Makefile b/benchmarks/vitis_flow/cnn13x4_16/cnn13x8/Makefile index 4fb149f4..4c090507 100644 --- a/benchmarks/vitis_flow/cnn13x4_16/cnn13x8/Makefile +++ b/benchmarks/vitis_flow/cnn13x4_16/cnn13x8/Makefile @@ -2,35 +2,53 @@ # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. -ROOT_DIR := $(shell git rev-parse --show-toplevel) -GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py -PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 -PART := xcu250-figd2104-2L-e -RUN_FILE := run.py -LINK_FILE := link_config.ini -KERNEL_NAME := kernel3 -SRC_DIR := $(CURDIR)/design -TARGET := hw -TEMP_DIR := $(CURDIR)/build -KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo -KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin -INCLUDE := -I $(XILINX_HLS)/include -CFLAGS := $(INCLUDE) $(OPT_LEVEL) -CXX := g++ -HOST := app.exe -HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl -CLK_PERIOD_NS := 4 - - - -all:rs_opt +ROOT_DIR := $(shell git rev-parse --show-toplevel) +GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py +PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1 +PART := xcu250-figd2104-2L-e +RUN_FILE := run.py +LINK_FILE := link_config.ini +KERNEL_NAME := kernel3 +SRC_DIR := $(CURDIR)/design +TARGET := hw +TEMP_DIR := $(CURDIR)/build +KERNEL_XO := $(TEMP_DIR)/$(KERNEL_NAME).xo +KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME).xclbin +RS_KERNEL_XCLBIN := $(TEMP_DIR)/$(KERNEL_NAME)_rs.xclbin +INCLUDE := -I $(XILINX_HLS)/include +CFLAGS := $(INCLUDE) $(OPT_LEVEL) +CXX := g++ +HOST := app.exe +HLS2XO_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl +CLK_PERIOD_NS := 4 +RS_TARGET := $(TEMP_DIR)/dse/candidate_0/exported/$(KERNEL_NAME).xo +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt +BUILD_LOG := $(TEMP_DIR)/build.json + +all: $(RS_KERNEL_XCLBIN) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) sw_emu: $(KERNEL_XCLBIN) $(HOST) XCL_EMULATION_MODE=sw_emu ./app.exe $< hw: $(KERNEL_XCLBIN) $(HOST) -rs_opt:$(KERNEL_XO) +$(RS_KERNEL_XCLBIN): $(RS_TARGET) + v++ -l -t ${TARGET} \ + --platform $(PLATFORM) \ + --kernel $(KERNEL_NAME) \ + --connectivity.nk $(KERNEL_NAME):1:$(KERNEL_NAME) \ + --config $(SRC_DIR)/$(LINK_FILE) \ + --temp_dir $(TEMP_DIR) \ + -o $@ \ + $^ + +rs_opt:$(RS_TARGET) + +$(RS_TARGET): $(KERNEL_XO) rapidstream $(RUN_FILE) $(KERNEL_XCLBIN): $(KERNEL_XO) @@ -80,7 +98,6 @@ show_groups: - clean: rm -rf $(TEMP_DIR) *.log rm -rf .Xil .run diff --git a/benchmarks/vivado_flow/CNN/cnn13x2/Makefile b/benchmarks/vivado_flow/CNN/cnn13x2/Makefile index f3faf321..5a7af8fb 100644 --- a/benchmarks/vivado_flow/CNN/cnn13x2/Makefile +++ b/benchmarks/vivado_flow/CNN/cnn13x2/Makefile @@ -20,8 +20,11 @@ KERNEL_CLK_MHZ := 300 SHELL_CLK_MHZ := 300 GEN_XO := 0 VXX := vivado -mode batch -source -RS_DCP := $(TEMP_DIR)/run/dse/candidate_0/route.dcp - +RS_DCP := $(TEMP_DIR)/run/dse/candidate_0/exported/impl/route.dcp +TIMING_RPT := $(TEMP_DIR)/run/dse/candidate_0/exported/impl/timing_summary.rpt +SUCCESS := "Build Successful" +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +BUILD_LOG := $(TEMP_DIR)/build.json ifeq ($(PLATFORM), xilinx_u50_gen3x16_xdma_5_202210_1) PART := xcu50-fsvh2104-2-e @@ -35,7 +38,9 @@ endif SHELL_DCP := $(TEMP_DIR)/shell_$(CARD)_$(KERNEL_CLK_MHZ)_$(SHELL_CLK_MHZ)M_prj/shell.dcp CL_IPI_PRJ := $(TEMP_DIR)/$(KERNEL_NAME)_$(CARD)_$(KERNEL_CLK_MHZ)_$(SHELL_CLK_MHZ)M_cl_prj/$(KERNEL_NAME)_$(CARD)_cl_prj.xpr -all:$(RS_DCP) +all: $(RS_DCP) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) $(RS_DCP):$(CL_IPI_PRJ) $(SHELL_DCP) rapidstream $(RUN_FILE) diff --git a/benchmarks/vivado_flow/CNN/cnn13x2/run_au50.py b/benchmarks/vivado_flow/CNN/cnn13x2/run_au50.py index 653fff08..e9321b33 100644 --- a/benchmarks/vivado_flow/CNN/cnn13x2/run_au50.py +++ b/benchmarks/vivado_flow/CNN/cnn13x2/run_au50.py @@ -20,16 +20,16 @@ kernel_clk_mhz = 300 hbm_clk_mhz = 300 -temp_dir = "build" +temp_dir = f"{CURR_DIR}/build" kernel_name = "kernel3" card = "au50" -hdl_src_dir = f"{CURR_DIR}/{temp_dir}/hdl" -ipi_prj_name = ( - f"{CURR_DIR}/{temp_dir}/{kernel_name}_{card}_{kernel_clk_mhz}_{hbm_clk_mhz}M_cl_prj" +hdl_src_dir = f"{temp_dir}/hdl" +ipi_prj_name = f"{temp_dir}/{kernel_name}_{card}_{kernel_clk_mhz}_{hbm_clk_mhz}M_cl_prj" +txt_prj_name = ( + f"{temp_dir}/{kernel_name}_{card}_{kernel_clk_mhz}_{hbm_clk_mhz}M_cl_txt_prj" ) -txt_prj_name = f"{CURR_DIR}/{temp_dir}/{kernel_name}_{card}_{kernel_clk_mhz}_{hbm_clk_mhz}M_cl_txt_prj" -hls_dir = f"{CURR_DIR}/{temp_dir}/{kernel_name}/solution" +hls_dir = f"{temp_dir}/{kernel_name}/solution" verilog_input_dirs: list[str] = [ hdl_src_dir, diff --git a/benchmarks/vivado_flow/LLM/Makefile b/benchmarks/vivado_flow/LLM/Makefile index 9cca59a5..69993ac4 100644 --- a/benchmarks/vivado_flow/LLM/Makefile +++ b/benchmarks/vivado_flow/LLM/Makefile @@ -23,6 +23,11 @@ BIT_TARGET := $(TEMP_DIR)/prj/prj.runs/impl_1/design_1_wrapper.bit GEN_XO := 0 VXX := vivado -mode batch -source +BUILD_LOG := $(TEMP_DIR)/build.json +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/prj/prj.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt +SLACK_GETTER := $(REPO_ROOT)/common/util/get_slack.py + ifeq ($(PLATFORM), vhk158) PART := xcvh1582-vsva3697-2MP-e-S BOARD := xilinx.com:vhk158:part0:1.1 @@ -57,12 +62,15 @@ else $(error PLATFORM not supported) endif -all:$(BIT_TARGET) - echo "TESTS PASS!" +all: $(BIT_TARGET) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) $(BIT_TARGET):$(RS_TARGET) cd $(TEMP_DIR) && $(VXX) $(IMPL_RS_TCL) -tclargs $(PART) $(BOARD) $(BD_TCL) +rs_opt: $(RS_TARGET) + $(RS_TARGET):$(KERNEL_HLS_SOL) rapidstream $(RUN_FILE) diff --git a/benchmarks/vivado_flow/LLM/run_vu9p.py b/benchmarks/vivado_flow/LLM/run_vu9p.py index a16cabdb..c873c6d8 100644 --- a/benchmarks/vivado_flow/LLM/run_vu9p.py +++ b/benchmarks/vivado_flow/LLM/run_vu9p.py @@ -35,6 +35,5 @@ rs.add_clock("ap_clk", kernel_clk_ns) rs.assign_port_to_region(".*", "SLOT_X0Y0:SLOT_X0Y0") -rs.assign_cell_to_region(".*k3.*", "SLOT_X0Y1:SLOT_X0Y1") rs.run_dse(skip_impl=True) diff --git a/benchmarks/vivado_flow/cnn13x2/Makefile b/benchmarks/vivado_flow/cnn13x2/Makefile index eab7aa13..dc0812b3 100644 --- a/benchmarks/vivado_flow/cnn13x2/Makefile +++ b/benchmarks/vivado_flow/cnn13x2/Makefile @@ -23,6 +23,11 @@ VIVADO_BIT_TARGET := $(TEMP_DIR)/prj_vivado/prj_vivado.runs/impl_1/design_1_w SLOTS_BIT_TARGET := $(TEMP_DIR)/slot/prj_slot/prj_slot.runs/impl_1/design_1_wrapper.bit BD_BIT_TARGET := $(TEMP_DIR)/bd/prj_bd/prj_bd.runs/impl_1/design_1_wrapper.bit +BUILD_LOG := $(TEMP_DIR)/build.json +SUCCESS := "Build Successful" +TIMING_RPT := $(TEMP_DIR)/prj/prj.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt +SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py + # Do not generate XO file GEN_XO := 0 VXX := vivado -mode batch -source @@ -35,9 +40,11 @@ BD_TCL := $(CURDIR)/tcl/gen_design_u50.tcl BIT := $(BIT_TARGET) -all:$(BIT_TARGET) +all: $(BIT_TARGET) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) + echo $(SUCCESS) -$(BIT_TARGET):$(RS_TARGET) +$(BIT_TARGET): $(RS_TARGET) mkdir -p $(TEMP_DIR) cd $(TEMP_DIR) && $(VXX) $(IMPL_TCL) -tclargs $(PART) $(BOARD) $(shell dirname $<) diff --git a/benchmarks/vivado_flow/cnn13x2/README.md b/benchmarks/vivado_flow/cnn13x2/README.md index 0ac392a9..6d9a374c 100644 --- a/benchmarks/vivado_flow/cnn13x2/README.md +++ b/benchmarks/vivado_flow/cnn13x2/README.md @@ -14,7 +14,7 @@ Although AMD Vitis is widely used for its support of high-level languages, Vivad At this moment, Rapidstream mainly accepts text-based input sources as shown below. -RapidStream Logo +rapidstream_input Design modules can be represented by `.v`, `.tcl`, or `.xci` (Xilinx Compiled IP) files. Interface information can be described within the Verilog code as outlined in [getting_started/mixed_sources](../../../getting_started/mixed_sources). Alternatively, if your modules are compiled using `vitis_hls`, you can provide `.rpt` or `.xml` files. diff --git a/benchmarks/tapa_flow/stencil_sasa/medium_congestion/autbridge_fail b/benchmarks/vivado_flow/cnn13x2/xfail_no_board_get_area similarity index 100% rename from benchmarks/tapa_flow/stencil_sasa/medium_congestion/autbridge_fail rename to benchmarks/vivado_flow/cnn13x2/xfail_no_board_get_area diff --git a/getting_started/img/VecAddMix.png b/common/img/VecAddMix.png similarity index 100% rename from getting_started/img/VecAddMix.png rename to common/img/VecAddMix.png diff --git a/getting_started/img/au250_virtual_device.png b/common/img/au250_virtual_device.png similarity index 100% rename from getting_started/img/au250_virtual_device.png rename to common/img/au250_virtual_device.png diff --git a/getting_started/img/au280_callipepla.png b/common/img/au280_callipepla.png similarity index 100% rename from getting_started/img/au280_callipepla.png rename to common/img/au280_callipepla.png diff --git a/getting_started/img/au280_sextans.png b/common/img/au280_sextans.png similarity index 100% rename from getting_started/img/au280_sextans.png rename to common/img/au280_sextans.png diff --git a/getting_started/img/au50_virtual_device.png b/common/img/au50_virtual_device.png similarity index 100% rename from getting_started/img/au50_virtual_device.png rename to common/img/au50_virtual_device.png diff --git a/getting_started/img/mixed_ooc_layout.png b/common/img/mixed_ooc_layout.png similarity index 100% rename from getting_started/img/mixed_ooc_layout.png rename to common/img/mixed_ooc_layout.png diff --git a/getting_started/img/rapid_shell.png b/common/img/rapid_shell.png similarity index 100% rename from getting_started/img/rapid_shell.png rename to common/img/rapid_shell.png diff --git a/getting_started/img/rapidsteram_xo.png b/common/img/rapidsteram_xo.png similarity index 100% rename from getting_started/img/rapidsteram_xo.png rename to common/img/rapidsteram_xo.png diff --git a/getting_started/img/rapidstream_input.png b/common/img/rapidstream_input.png similarity index 100% rename from getting_started/img/rapidstream_input.png rename to common/img/rapidstream_input.png diff --git a/getting_started/img/rapidstream_ipi_support.png b/common/img/rapidstream_ipi_support.png similarity index 100% rename from getting_started/img/rapidstream_ipi_support.png rename to common/img/rapidstream_ipi_support.png diff --git a/getting_started/img/vitis_rapidstream_flow.png b/common/img/vitis_rapidstream_flow.png similarity index 100% rename from getting_started/img/vitis_rapidstream_flow.png rename to common/img/vitis_rapidstream_flow.png diff --git a/getting_started/img/vivado_ipi_prj.png b/common/img/vivado_ipi_prj.png similarity index 100% rename from getting_started/img/vivado_ipi_prj.png rename to common/img/vivado_ipi_prj.png diff --git a/getting_started/img/vivado_kernel_flow.png b/common/img/vivado_kernel_flow.png similarity index 100% rename from getting_started/img/vivado_kernel_flow.png rename to common/img/vivado_kernel_flow.png diff --git a/getting_started/img/vivado_verilog_prj.png b/common/img/vivado_verilog_prj.png similarity index 100% rename from getting_started/img/vivado_verilog_prj.png rename to common/img/vivado_verilog_prj.png diff --git a/getting_started/img/vp1552_virtual_device.png b/common/img/vp1552_virtual_device.png similarity index 100% rename from getting_started/img/vp1552_virtual_device.png rename to common/img/vp1552_virtual_device.png diff --git a/common/util/get_slack.py b/common/util/get_slack.py index a3a7785f..4fc528ac 100644 --- a/common/util/get_slack.py +++ b/common/util/get_slack.py @@ -4,6 +4,7 @@ """ import argparse +import json # The value of WNS is 2 lines below the line that starts with "WNS(ns)" LINE_OFFSET = 2 @@ -22,11 +23,17 @@ output_file = args.output_file if input_file != ".": - with open(input_file, "r") as file: - lines = file.readlines() + with open(input_file, "r") as ifile: + lines = ifile.readlines() lines = [line.strip() for line in lines] + # Grab the slack value + results: dict[str, str] = {} for idx, line in enumerate(lines): if line.startswith("WNS(ns)"): slack = float(lines[idx + LINE_OFFSET].split()[0]) - print(f"WNS(ns) is {slack}") + results["slack"] = str(slack) + + if input_file != ".": + with open(output_file, "w") as ofile: + json.dump(results, ofile, indent=4) diff --git a/getting_started/mixed_sources/Makefile b/getting_started/mixed_sources/Makefile index 4c81051c..23b554b5 100644 --- a/getting_started/mixed_sources/Makefile +++ b/getting_started/mixed_sources/Makefile @@ -15,9 +15,10 @@ HLS_TCL := $(ROOT_DIR)/common/tcl/hls2rtl.tcl GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py SUCCESS := "Build Successful" SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +BUILD_LOG := $(TEMP_DIR)/build.json all: $(DCP_TARGET) - rapidstream $(SLACK_GETTER) -i $(dir $<)/timing_summary.rpt + rapidstream $(SLACK_GETTER) -i $(dir $<)/timing_summary.rpt -o $(BUILD_LOG) echo $(SUCCESS) $(DCP_TARGET):$(HLS_DIR_TARGETS) diff --git a/getting_started/mixed_sources/README.md b/getting_started/mixed_sources/README.md index 0a3da47f..f76d186d 100644 --- a/getting_started/mixed_sources/README.md +++ b/getting_started/mixed_sources/README.md @@ -25,7 +25,7 @@ and This example utilizes the predefined U50 virtual device, which divides the FPGA part into four equal slots, each occupying half of a Super Logic Region (SLR): -U50 Partitioning Scheme +U50 Partitioning Scheme The Python snippet below demonstrates how to define the device configuration for the Alveo U50 device. The source file u50.py can be found in your RapidStream installation directory, such as `/.rapidstream/opt/python3.10/lib/python3.10/site-packages/rapidstream/assets/device_library/u50/u50.py`. @@ -65,7 +65,7 @@ def get_u50_default_device(output_path: Path | None = None) -> VirtualDevice: RapidStream supports Verilog files, whether they are handcrafted or generated by tools. In this tutorial, we will recreate the VecAdd example from [vitis_source](../vitis_source/README.md), using source files from a different origin. -RapidStream Flow +RapidStream Flow The VecAddMix design has 3 types of input source: diff --git a/getting_started/vitis_source/Makefile b/getting_started/vitis_source/Makefile index aad9e90f..b28e29b1 100644 --- a/getting_started/vitis_source/Makefile +++ b/getting_started/vitis_source/Makefile @@ -19,12 +19,12 @@ RS_TARGET := $(TEMP_DIR)/dse/candidate_0/exported/VecAdd.xo TIMING_RPT := $(TEMP_DIR)/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt SUCCESS := "Build Successful" SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py +BUILD_LOG := $(TEMP_DIR)/build.json all: $(RS_KERNEL_XCLBIN) - rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) + rapidstream $(SLACK_GETTER) -i $(TIMING_RPT) -o $(BUILD_LOG) echo $(SUCCESS) - $(RS_KERNEL_XCLBIN): $(RS_TARGET) v++ -l -t ${TARGET} \ --platform $(PLATFORM) \ diff --git a/getting_started/vitis_source/README.md b/getting_started/vitis_source/README.md index e6ea50ef..34b7825d 100644 --- a/getting_started/vitis_source/README.md +++ b/getting_started/vitis_source/README.md @@ -11,7 +11,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L Rapidsteam is fully compatible with AMD Vitis by taking Vitis object files (`.xo`) as input, performing optimization and generating optimized `.xo` files as output. Therefore, users can use `v++ -link` to continue their Vitis development flow. -RapidStream Flow +rapidstream_xo.png In this recipe, we illustrate how to create a Vitis objective file (`.xo`) using Vitis, then optimize the `.xo` file with Rapidstream, and finally utilize the optimized output in the ongoing Vitis development process.