diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index e146a0c5..85de39ee 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -25,6 +25,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use CSR helper macros to define `misa` register
 - Use CSR helper macros to define `mip` register
 - Use CSR helper macros to define `mstatus` register
+- Use CSR helper macros to define `mstatush` register
 
 ## [v0.12.1] - 2024-10-20
 
diff --git a/riscv/src/register/mstatush.rs b/riscv/src/register/mstatush.rs
index b90878a6..cc64598e 100644
--- a/riscv/src/register/mstatush.rs
+++ b/riscv/src/register/mstatush.rs
@@ -42,3 +42,20 @@ pub unsafe fn set_mbe(endianness: Endianness) {
         Endianness::LittleEndian => _clear(1 << 5),
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mstatush() {
+        let mut m = Mstatush::from_bits(0);
+
+        [Endianness::LittleEndian, Endianness::BigEndian]
+            .into_iter()
+            .for_each(|endianness| {
+                test_csr_field!(m, sbe: endianness);
+                test_csr_field!(m, mbe: endianness);
+            });
+    }
+}