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devices.cmake
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devices.cmake
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# This CMake include defines the following functions:
#
# * DEFINE_ARCH - Define an FPGA architecture and tools to use that
# architecture.
# * DEFINE_DEVICE_TYPE - Define a device type within an FPGA architecture.
# * DEFINE_DEVICE - Define a device and packaging for a specific device type and
# FPGA architecture.
# * DEFINE_BOARD - Define a board that uses specific device and package.
# * ADD_FPGA_TARGET - Creates a FPGA image build against a specific board.
function(DEFINE_ARCH)
# ~~~
# DEFINE_ARCH(
# ARCH <arch>
# FAMILY <family>
# DOC_PRJ <documentation_project>
# DOC_PRJ_DB <documentation_database>
# PROTOTYPE_PART <prototype_part>
# YOSYS_SYNTH_SCRIPT <yosys_script>
# YOSYS_CONV_SCRIPT <yosys_script>
# BITSTREAM_EXTENSION <ext>
# [VPR_ARCH_ARGS <arg list>]
# RR_PATCH_TOOL <path to rr_patch tool>
# RR_PATCH_CMD <command to run RR_PATCH_TOOL>
# DEVICE_FULL_TEMPLATE <template for constructing DEVICE_FULL strings.
# [NO_PINS]
# [NO_PLACE]
# [NO_PLACE_CONSTR]
# [USE_FASM]
# PLACE_TOOL <path to place tool>
# PLACE_TOOL_CMD <command to run PLACE_TOOL>
# PLACE_CONSTR_TOOL <path to place constraints tool>
# PLACE_CONSTR_TOOL_CMD <command to run PLACE_CONSTR_TOOL>
# [NO_BITSTREAM]
# [NO_BIT_TO_BIN]
# [NO_BIT_TO_V]
# [CELLS_SIM <path to verilog file used for simulation>]
# HLC_TO_BIT <path to HLC to bitstream converter>
# HLC_TO_BIT_CMD <command to run HLC_TO_BIT>
# FASM_TO_BIT <path to FASM to bitstream converter>
# FASM_TO_BIT_CMD <command to run FASM_TO_BIT>
# FASM_TO_BIT_DEPS <list of dependencies for FASM_TO_BIT_CMD>
# BIT_TO_V <path to bitstream to verilog converter>
# BIT_TO_V_CMD <command to run BIT_TO_V>
# BIT_TO_BIN <path to bitstream to binary>
# BIT_TO_BIN_CMD <command to run BIT_TO_BIN>
# BIT_TIME <path to BIT_TIME executable>
# BIT_TIME_CMD <command to run BIT_TIME>
# [RR_GRAPH_EXT <ext>]
# )
# ~~~
#
# DEFINE_ARCH defines an FPGA architecture.
#
# FAMILY refers to the family under which the architecture is located.
# e.g. 7series, UltraScale, Spartan are all different kinds of families.
#
# DOC_PRJ and DOC_PRJ_DB are optional arguments that are relative to the
# third party projects containing tools and information to correctly run
# the flow:
#
# * DOC_PRJ - path to the third party documentation project
# * DOC_PRJ_DB - path to the third party documentation database
#
# If NO_PINS is set, PLACE_TOOL and PLACE_TOOL_CMD cannot be specified.
# If NO_BITSTREAM is set, HLC_TO_BIT, HLC_TO_BIT_CMD BIT_TO_V,
# BIT_TO_V_CMD, BIT_TO_BIN and BIT_TO_BIN_CMD cannot be specified.
#
# if NO_BIT_TO_BIN is given then there will be no BIT to BIN stage.
#
# YOSYS_SYNTH_SCRIPT - The main design synthesis script. It needs to write
# the synthesized design in JSON format to a file name pointed by the
# OUT_JSON env. variable.
#
# YOSYS_CONV_SCRIPT - This is the name of the script that makes Yosys convert
# the processed JSON design to the EBLIF format accepted by the VPR. The
# EBLIF file name is given in the OUT_EBLIF env. variable.
#
# DEVICE_FULL_TEMPLATE, RR_PATCH_CMD, PLACE_TOOL_CMD and HLC_TO_BIT_CMD will
# all be called with string(CONFIGURE) to substitute variables.
#
# DEVICE_FULL_TEMPLATE variables:
#
# * DEVICE
# * PACKAGE
#
# RR_PATCH_CMD variables:
#
# * RR_PATCH_TOOL - Value of RR_PATCH_TOOL property of <arch>.
# * DEVICE - What device is being patch (see DEFINE_DEVICE).
# * OUT_RRXML_VIRT - Input virtual rr_graph file for device.
# * OUT_RRXML_REAL - Output real XML rr_graph file for device.
# * OUT_RRBIN_REAL - Output real BIN rr_graph file for device.
#
# PLACE_TOOL_CMD variables:
#
# * PLACE_TOOL - Value of PLACE_TOOL property of <arch>.
# * PINMAP - Path to pinmap file. This file will be retrieved from the
# PINMAP property of the ${BOARD}. ${DEVICE} and ${PACKAGE}
# will be defined by the BOARD being used. See DEFINE_BOARD.
# * OUT_EBLIF - Input path to EBLIF file.
# * INPUT_IO_FILE - Path to input io file, as specified by ADD_FPGA_TARGET.
#
# PLACE_TOOL_CONSTR_CMD variables:
#
# * PLACE_CONSTR_TOOL - Value of PLACE_CONSTR_TOOL property of <arch>.
# * NO_PLACE_CONSTR - If this option is set, the PLACE_CONSTR_TOOL is disabled
#
# This command enables the possibility to add an additional step consisting
# on the addition of extra placement constraints through the usage of the chosen
# script.
# The IO placement file is passed to the script through standard input and, when
# the new placement constraints for non-IO tiles have been added, a new placement
# constraint file is generated and fed to standard output.
#
#
#
# HLC_TO_BIT_CMD variables:
#
# * HLC_TO_BIT - Value of HLC_TO_BIT property of <arch>.
# * OUT_HLC - Input path to HLC file.
# * OUT_BITSTREAM - Output path to bitstream file.
#
# BIT_TO_V variables:
#
# * BIT_TO_V - Value of BIT_TO_V property of <arch>.
# * TOP - Name of top module.
# * INPUT_IO_FILE - Logic to IO pad constraint file.
# * PACKAGE - Package of bitstream.
# * OUT_BITSTREAM - Input path to bitstream.
# * OUT_BIT_VERILOG - Output path to verilog version of bitstream.
set(options
NO_PLACE_CONSTR
NO_PINS
NO_BITSTREAM
NO_BIT_TO_BIN
NO_BIT_TO_V
NO_BIT_TIME
USE_FASM
)
set(
oneValueArgs
ARCH
FAMILY
DOC_PRJ
DOC_PRJ_DB
PROTOTYPE_PART
YOSYS_SYNTH_SCRIPT
YOSYS_CONV_SCRIPT
YOSYS_TECHMAP
DEVICE_FULL_TEMPLATE
BITSTREAM_EXTENSION
BIN_EXTENSION
RR_PATCH_TOOL
RR_PATCH_CMD
PLACE_TOOL
PLACE_TOOL_CMD
PLACE_CONSTR_TOOL
PLACE_CONSTR_TOOL_CMD
HLC_TO_BIT
HLC_TO_BIT_CMD
FASM_TO_BIT
FASM_TO_BIT_CMD
BIT_TO_V
BIT_TO_V_CMD
BIT_TO_BIN
BIT_TO_BIN_CMD
BIT_TIME
BIT_TIME_CMD
RR_GRAPH_EXT
ROUTE_CHAN_WIDTH
)
set(
multiValueArgs
CELLS_SIM
VPR_ARCH_ARGS
FASM_TO_BIT_DEPS
)
cmake_parse_arguments(
DEFINE_ARCH
"${options}"
"${oneValueArgs}"
"${multiValueArgs}"
${ARGN}
)
add_custom_target(${DEFINE_ARCH_ARCH})
set(REQUIRED_ARGS
YOSYS_SYNTH_SCRIPT
YOSYS_CONV_SCRIPT
DEVICE_FULL_TEMPLATE
RR_PATCH_TOOL
RR_PATCH_CMD
NO_PLACE_CONSTR
NO_PINS
NO_BITSTREAM
NO_BIT_TO_BIN
NO_BIT_TO_V
NO_BIT_TIME
USE_FASM
ROUTE_CHAN_WIDTH
)
set(DISALLOWED_ARGS "")
set(OPTIONAL_ARGS
FAMILY
DOC_PRJ
DOC_PRJ_DB
PROTOTYPE_PART
VPR_ARCH_ARGS
YOSYS_TECHMAP
CELLS_SIM
)
set(PLACE_ARGS
PLACE_TOOL
PLACE_TOOL_CMD
)
set(PLACE_CONSTR_ARGS
PLACE_CONSTR_TOOL
PLACE_CONSTR_TOOL_CMD
)
set(FASM_BIT_ARGS
FASM_TO_BIT
FASM_TO_BIT_CMD
)
set(HLC_BIT_ARGS
HLC_TO_BIT
HLC_TO_BIT_CMD
)
set(BIT_ARGS
BITSTREAM_EXTENSION
)
set(BIN_ARGS
BIN_EXTENSION
BIT_TO_BIN
BIT_TO_BIN_CMD
)
set(BIT_TO_V_ARGS
BIT_TO_V
BIT_TO_V_CMD
)
set(BIT_TIME_ARGS
BIT_TIME
BIT_TIME_CMD
)
if(NOT ${DEFINE_ARCH_NO_BIT_TO_BIN})
list(APPEND BIT_ARGS ${BIN_ARGS})
else()
list(APPEND DISALLOWED_ARGS ${BIN_ARGS})
endif()
if(${DEFINE_ARCH_USE_FASM})
list(APPEND DISALLOWED_ARGS ${HLC_BIT_ARGS})
list(APPEND OPTIONAL_ARGS FASM_TO_BIT_DEPS)
list(APPEND BIT_ARGS ${FASM_BIT_ARGS})
else()
list(APPEND DISALLOWED_ARGS ${FASM_BIT_ARGS})
list(APPEND DISALLOWED_ARGS FASM_TO_BIT_DEPS)
list(APPEND BIT_ARGS ${HLC_BIT_ARGS})
endif()
set(VPR_${DEFINE_ARCH_ARCH}_ARCH_ARGS "${DEFINE_ARCH_VPR_ARCH_ARGS}"
CACHE STRING "Extra VPR arguments for ARCH=${ARCH}")
if(${DEFINE_ARCH_NO_PINS})
list(APPEND DISALLOWED_ARGS ${PLACE_ARGS})
else()
list(APPEND REQUIRED_ARGS ${PLACE_ARGS})
endif()
if(${DEFINE_ARCH_NO_PLACE_CONSTR})
list(APPEND DISALLOWED_ARGS ${PLACE_CONSTR_ARGS})
else()
list(APPEND REQUIRED_ARGS ${PLACE_CONSTR_ARGS})
endif()
set(RR_GRAPH_EXT ".xml")
if(NOT "${DEFINE_ARCH_RR_GRAPH_EXT}" STREQUAL "")
set(RR_GRAPH_EXT "${DEFINE_ARCH_RR_GRAPH_EXT}")
endif()
if(${DEFINE_ARCH_NO_BITSTREAM})
list(APPEND DISALLOWED_ARGS ${BIT_ARGS})
else()
list(APPEND REQUIRED_ARGS ${BIT_ARGS})
endif()
if(${DEFINE_ARCH_NO_BIT_TO_V})
list(APPEND DISALLOWED_ARGS ${BIT_TO_V_ARGS})
else()
list(APPEND REQUIRED_ARGS ${BIT_TO_V_ARGS})
endif()
if(${DEFINE_ARCH_NO_BIT_TIME})
list(APPEND DISALLOWED_ARGS ${BIT_TIME_ARGS})
else()
list(APPEND REQUIRED_ARGS ${BIT_TIME_ARGS})
endif()
foreach(ARG ${REQUIRED_ARGS})
if("${DEFINE_ARCH_${ARG}}" STREQUAL "")
message(FATAL_ERROR "Required argument ${ARG} is the empty string.")
endif()
set_target_properties(
${DEFINE_ARCH_ARCH}
PROPERTIES ${ARG} "${DEFINE_ARCH_${ARG}}"
)
endforeach()
set_target_properties(
${DEFINE_ARCH_ARCH}
PROPERTIES RR_GRAPH_EXT "${RR_GRAPH_EXT}"
)
foreach(ARG ${OPTIONAL_ARGS})
set_target_properties(
${DEFINE_ARCH_ARCH}
PROPERTIES ${ARG} "${DEFINE_ARCH_${ARG}}"
)
endforeach()
foreach(ARG ${DISALLOWED_ARGS})
if(NOT "${DEFINE_ARCH_${ARG}}" STREQUAL "")
message(FATAL_ERROR "Argument ${ARG} is disallowed when NO_PINS = ${NO_PINS} and NO_BITSTREAM = ${NO_BITSTREAM}.")
endif()
endforeach()
endfunction()
function(DEFINE_DEVICE_TYPE)
# ~~~
# DEFINE_DEVICE_TYPE(
# DEVICE_TYPE <device_type>
# ARCH <arch>
# ARCH_XML <arch.xml>
# [SCRIPT_OUTPUT_NAME]
# [SCRIPT_DEPS]
# [SCRIPTS]
# )
# ~~~
#
# Defines a device type with the specified architecture. ARCH_XML argument
# must be a file target (see ADD_FILE_TARGET).
#
# optional SCRIPTs can be run after the standard flow to augment the
# final arch xml. The name and script must be provided and each
# script will be run as `cmd < input > output`.
# If the SCRIPT has dependencies, SCRIPT_DEPS can be used to be passed to the
# SCRIPT command.
#
# DEFINE_DEVICE_TYPE defines a dummy target <arch>_<device_type>_arch that
# will build the merged architecture file for the device type.
set(options "")
set(oneValueArgs DEVICE_TYPE ARCH ARCH_XML)
set(multiValueArgs SCRIPT_OUTPUT_NAME SCRIPTS SCRIPT_DEPS)
cmake_parse_arguments(
DEFINE_DEVICE_TYPE
"${options}"
"${oneValueArgs}"
"${multiValueArgs}"
${ARGN}
)
#
# Generate a arch.xml for a device.
#
set(DEVICE_MERGED_FILE arch.merged.xml)
set(DEVICE_UNIQUE_PACK_FILE arch.unique_pack.xml)
set(DEVICE_LINT_FILE arch.lint.html)
set(MERGE_XML_OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${DEVICE_MERGED_FILE})
set(UNIQUE_PACK_OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${DEVICE_UNIQUE_PACK_FILE})
set(XMLLINT_OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${DEVICE_LINT_FILE})
xml_canonicalize_merge(
NAME ${DEFINE_DEVICE_TYPE_ARCH}_${DEFINE_DEVICE_TYPE_DEVICE_TYPE}_arch_merged
FILE ${DEFINE_DEVICE_TYPE_ARCH_XML}
OUTPUT ${DEVICE_MERGED_FILE}
)
get_target_property_required(PYTHON3 env PYTHON3)
append_file_dependency(SPECIALIZE_CARRYCHAINS_DEPS ${DEVICE_MERGED_FILE})
set(SPECIALIZE_CARRYCHAINS ${symbiflow-arch-defs_SOURCE_DIR}/utils/specialize_carrychains.py)
add_custom_command(
OUTPUT ${UNIQUE_PACK_OUTPUT}
COMMAND ${PYTHON3} ${SPECIALIZE_CARRYCHAINS}
--input_arch_xml ${MERGE_XML_OUTPUT} > ${DEVICE_UNIQUE_PACK_FILE}
DEPENDS
${PYTHON3}
${SPECIALIZE_CARRYCHAINS}
${SPECIALIZE_CARRYCHAINS_DEPS}
)
add_file_target(FILE ${DEVICE_UNIQUE_PACK_FILE} GENERATED)
get_file_target(FINAL_TARGET ${DEVICE_UNIQUE_PACK_FILE})
get_file_location(FINAL_FILE ${DEVICE_UNIQUE_PACK_FILE})
set(FINAL_OUTPUT ${DEVICE_UNIQUE_PACK_FILE})
# for each script generate next chain of deps
if (DEFINE_DEVICE_TYPE_SCRIPTS)
list(LENGTH DEFINE_DEVICE_TYPE_SCRIPT_OUTPUT_NAME SCRIPT_LEN)
math(EXPR SCRIPT_LEN ${SCRIPT_LEN}-1)
foreach(SCRIPT_IND RANGE ${SCRIPT_LEN})
list(GET DEFINE_DEVICE_TYPE_SCRIPT_OUTPUT_NAME ${SCRIPT_IND} OUTPUT_NAME)
list(GET DEFINE_DEVICE_TYPE_SCRIPT_DEPS ${SCRIPT_IND} DEFINE_DEVICE_TYPE_SCRIPT_DEP_VAR)
list(GET DEFINE_DEVICE_TYPE_SCRIPTS ${SCRIPT_IND} SCRIPT)
set(SCRIPT ${${SCRIPT}})
set(DEFINE_DEVICE_TYPE_SCRIPT_DEP_VAR ${${DEFINE_DEVICE_TYPE_SCRIPT_DEP_VAR}})
separate_arguments(CMD_W_ARGS UNIX_COMMAND ${SCRIPT})
list(GET CMD_W_ARGS 0 CMD)
set(TEMP_TARGET arch.${OUTPUT_NAME}.xml)
set(DEFINE_DEVICE_DEPS ${PYTHON3} ${CMD} ${DEFINE_DEVICE_TYPE_SCRIPT_DEP_VAR})
append_file_dependency(DEFINE_DEVICE_DEPS ${FINAL_OUTPUT})
add_custom_command(
OUTPUT ${TEMP_TARGET}
COMMAND ${CMD_W_ARGS} < ${FINAL_FILE} > ${TEMP_TARGET}
DEPENDS ${DEFINE_DEVICE_DEPS}
)
add_file_target(FILE ${TEMP_TARGET} GENERATED)
get_file_target(FINAL_TARGET ${TEMP_TARGET})
get_file_location(FINAL_FILE ${TEMP_TARGET})
set(FINAL_OUTPUT ${TEMP_TARGET})
endforeach(SCRIPT_IND RANGE ${SCRIPT_LEN})
endif (DEFINE_DEVICE_TYPE_SCRIPTS)
add_custom_target(
${DEFINE_DEVICE_TYPE_ARCH}_${DEFINE_DEVICE_TYPE_DEVICE_TYPE}_arch
DEPENDS ${FINAL_TARGET}
)
add_dependencies(
all_merged_arch_xmls
${DEFINE_DEVICE_TYPE_ARCH}_${DEFINE_DEVICE_TYPE_DEVICE_TYPE}_arch
)
set(ARCH_SCHEMA ${symbiflow-arch-defs_SOURCE_DIR}/common/xml/fpga_architecture.xsd)
xml_lint(
NAME ${DEFINE_DEVICE_TYPE_ARCH}_${DEFINE_DEVICE_TYPE_DEVICE_TYPE}_arch_lint
FILE ${FINAL_FILE}
LINT_OUTPUT ${XMLLINT_OUTPUT}
SCHEMA ${ARCH_SCHEMA}
)
append_file_dependency(FINAL_DEPS ${FINAL_OUTPUT})
add_custom_target(
${DEFINE_DEVICE_TYPE_DEVICE_TYPE}
DEPENDS ${FINAL_DEPS}
)
foreach(ARG ARCH)
if("${DEFINE_DEVICE_TYPE_${ARG}}" STREQUAL "")
message(FATAL_ERROR "Required argument ${ARG} is the empty string.")
endif()
set_target_properties(
${DEFINE_DEVICE_TYPE_DEVICE_TYPE}
PROPERTIES ${ARG} ${DEFINE_DEVICE_TYPE_${ARG}}
)
endforeach()
set_target_properties(
${DEFINE_DEVICE_TYPE_DEVICE_TYPE}
PROPERTIES
DEVICE_MERGED_FILE ${CMAKE_CURRENT_SOURCE_DIR}/${FINAL_OUTPUT}
)
endfunction()
function(DEFINE_DEVICE)
# ~~~
# DEFINE_DEVICE(
# DEVICE <device>
# ARCH <arch>
# PART <part>
# DEVICE_TYPE <device_type>
# PACKAGES <list of packages>
# [WIRE_EBLIF <a dummy design eblif file>
# [CACHE_PLACE_DELAY]
# [CACHE_LOOKAHEAD]
# [CACHE_ARGS <args>]
# )
# ~~~
#
# Defines a device within a specified FPGA architecture.
#
# Creates dummy targets <arch>_<device>_<package>_rrxml_virt and
# <arch>_<device>_<package>_rrxml_virt that generates the the virtual and
# real rr_graph for a specific device and package.
#
# The WIRE_EBLIF specifies a dummy design file to use. If not given then
# the default "common/wire.eblif" is used.
#
# To prevent VPR from recomputing the place delay matrix and/or lookahead,
# CACHE_PLACE_DELAY and CACHE_LOOKAHEAD options may be specified.
#
# If either are specified, CACHE_ARGS must be supplied with the relevant
# VPR arguments needed to emit the correct place delay and lookahead outputs.
# It is not required that the all arguments match the DEFINE_ARCH.VPR_ARCH_ARGS
# as it may be advantagous to increase routing effort for the placement delay
# matrix computation (e.g. lower astar_fac, etc).
#
# At a minimum, the --route_chan_width argument must be supplied.
#
# WARNING: Using a different place delay or lookahead algorithm will result
# in an invalid cache.
set(options CACHE_LOOKAHEAD CACHE_PLACE_DELAY)
set(oneValueArgs DEVICE ARCH PART DEVICE_TYPE PACKAGES WIRE_EBLIF)
set(multiValueArgs RR_PATCH_DEPS RR_PATCH_EXTRA_ARGS CACHE_ARGS)
cmake_parse_arguments(
DEFINE_DEVICE
"${options}"
"${oneValueArgs}"
"${multiValueArgs}"
${ARGN}
)
add_custom_target(${DEFINE_DEVICE_DEVICE})
foreach(ARG ARCH DEVICE_TYPE PACKAGES)
if("${DEFINE_DEVICE_${ARG}}" STREQUAL "")
message(FATAL_ERROR "Required argument ${ARG} is the empty string.")
endif()
set_target_properties(
${DEFINE_DEVICE_DEVICE}
PROPERTIES ${ARG} ${DEFINE_DEVICE_${ARG}}
)
endforeach()
if("${DEFINE_DEVICE_WIRE_EBLIF}" STREQUAL "")
set(WIRE_EBLIF ${symbiflow-arch-defs_SOURCE_DIR}/common/wire.eblif)
else()
set(WIRE_EBLIF ${DEFINE_DEVICE_WIRE_EBLIF})
endif()
get_target_property_required(
RR_PATCH_TOOL ${DEFINE_DEVICE_ARCH} RR_PATCH_TOOL
)
get_target_property_required(RR_PATCH_CMD ${DEFINE_DEVICE_ARCH} RR_PATCH_CMD)
get_target_property_required(ROUTE_CHAN_WIDTH ${DEFINE_DEVICE_ARCH}
ROUTE_CHAN_WIDTH)
get_target_property_required(
VIRT_DEVICE_MERGED_FILE ${DEFINE_DEVICE_DEVICE_TYPE} DEVICE_MERGED_FILE
)
get_file_target(DEVICE_MERGED_FILE_TARGET ${VIRT_DEVICE_MERGED_FILE})
get_file_location(DEVICE_MERGED_FILE ${VIRT_DEVICE_MERGED_FILE})
get_target_property_required(VPR env VPR)
get_target_property_required(QUIET_CMD env QUIET_CMD)
get_target_property_required(RR_GRAPH_EXT ${DEFINE_DEVICE_ARCH} RR_GRAPH_EXT)
set(ROUTING_SCHEMA ${symbiflow-arch-defs_SOURCE_DIR}/common/xml/routing_resource.xsd)
set(PART ${DEFINE_DEVICE_PART})
set(DEVICE ${DEFINE_DEVICE_DEVICE})
foreach(PACKAGE ${DEFINE_DEVICE_PACKAGES})
get_target_property_required(DEVICE_FULL_TEMPLATE ${DEFINE_DEVICE_ARCH} DEVICE_FULL_TEMPLATE)
string(CONFIGURE ${DEVICE_FULL_TEMPLATE} DEVICE_FULL)
set(OUT_RRXML_VIRT_FILENAME
rr_graph_${DEVICE}_${PACKAGE}.rr_graph.virt${RR_GRAPH_EXT})
set(OUT_RRXML_REAL_FILENAME
rr_graph_${DEVICE}_${PACKAGE}.rr_graph.real.patched${RR_GRAPH_EXT})
set(OUT_RRBIN_REAL_FILENAME
rr_graph_${DEVICE}_${PACKAGE}.rr_graph.real.bin)
set(LOOKAHEAD_FILENAME
rr_graph_${DEVICE}_${PACKAGE}.lookahead.bin)
set(PLACE_DELAY_FILENAME
rr_graph_${DEVICE}_${PACKAGE}.place_delay.bin)
set(OUT_RRXML_REAL_LINT_FILENAME rr_graph_${DEVICE}_${PACKAGE}.rr_graph.real.lint.html)
set(OUT_RRXML_VIRT ${CMAKE_CURRENT_BINARY_DIR}/${OUT_RRXML_VIRT_FILENAME})
set(OUT_RRXML_REAL ${CMAKE_CURRENT_BINARY_DIR}/${OUT_RRXML_REAL_FILENAME})
set(OUT_RRBIN_REAL ${CMAKE_CURRENT_BINARY_DIR}/${OUT_RRBIN_REAL_FILENAME})
set(OUT_RRXML_REAL_LINT ${CMAKE_CURRENT_BINARY_DIR}/${OUT_RRXML_REAL_LINT_FILENAME})
#
# Generate a rr_graph for a device.
#
# Generate the "default" rr_graph.xml we are going to patch using wire.
add_custom_command(
OUTPUT ${OUT_RRXML_VIRT} rr_graph_${DEVICE}_${PACKAGE}.virt.out
DEPENDS
${WIRE_EBLIF}
${DEVICE_MERGED_FILE} ${DEVICE_MERGED_FILE_TARGET}
${QUIET_CMD}
${VPR} ${DEFINE_DEVICE_DEVICE_TYPE}
COMMAND
${QUIET_CMD} ${VPR} ${DEVICE_MERGED_FILE}
--device ${DEVICE_FULL}
${WIRE_EBLIF}
--place_algorithm bounding_box
--enable_timing_computations off
--route_chan_width 6
--echo_file on
--min_route_chan_width_hint 1
--write_rr_graph ${OUT_RRXML_VIRT}
--outfile_prefix ${DEVICE}_${PACKAGE}
--pack
--pack_verbosity 100
--place
--allow_dangling_combinational_nodes on
COMMAND
${CMAKE_COMMAND} -E copy vpr_stdout.log
rr_graph_${DEVICE}_${PACKAGE}.virt.out
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
)
add_custom_target(
${DEFINE_DEVICE_ARCH}_${DEFINE_DEVICE_DEVICE}_${PACKAGE}_rrxml_virt
DEPENDS ${OUT_RRXML_VIRT}
)
add_file_target(FILE ${OUT_RRXML_VIRT_FILENAME} GENERATED)
set_target_properties(
${DEFINE_DEVICE_DEVICE}
PROPERTIES
OUT_RRXML_VIRT ${CMAKE_CURRENT_SOURCE_DIR}/${OUT_RRXML_VIRT_FILENAME}
)
set(RR_PATCH_DEPS ${DEFINE_DEVICE_RR_PATCH_DEPS})
append_file_dependency(RR_PATCH_DEPS ${VIRT_DEVICE_MERGED_FILE})
append_file_dependency(RR_PATCH_DEPS ${OUT_RRXML_VIRT_FILENAME})
# Generate the "real" rr_graph.xml from the default rr_graph.xml file
get_target_property_required(PYTHON3 env PYTHON3)
string(CONFIGURE ${RR_PATCH_CMD} RR_PATCH_CMD_FOR_TARGET)
separate_arguments(
RR_PATCH_CMD_FOR_TARGET_LIST UNIX_COMMAND ${RR_PATCH_CMD_FOR_TARGET}
)
add_custom_command(
OUTPUT ${OUT_RRXML_REAL}
DEPENDS ${RR_PATCH_DEPS} ${RR_PATCH_TOOL}
COMMAND ${RR_PATCH_CMD_FOR_TARGET_LIST} ${DEFINE_DEVICE_RR_PATCH_EXTRA_ARGS}
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
VERBATIM
)
add_file_target(FILE ${OUT_RRXML_REAL_FILENAME} GENERATED)
set_target_properties(
${DEFINE_DEVICE_DEVICE}
PROPERTIES
${PACKAGE}_OUT_RRXML_REAL
${CMAKE_CURRENT_SOURCE_DIR}/${OUT_RRXML_REAL_FILENAME}
)
add_custom_target(
${DEFINE_DEVICE_ARCH}_${DEFINE_DEVICE_DEVICE}_${PACKAGE}_rrxml_real
DEPENDS ${OUT_RRXML_REAL}
)
add_dependencies(all_rrgraph_xmls ${DEFINE_DEVICE_ARCH}_${DEFINE_DEVICE_DEVICE}_${PACKAGE}_rrxml_real)
# Lint the "real" rr_graph.xml
if("${RR_GRAPH_EXT}" STREQUAL ".xml")
xml_lint(
NAME ${DEFINE_DEVICE_ARCH}_${DEFINE_DEVICE_DEVICE}_${PACKAGE}_rrxml_real_lint
LINT_OUTPUT ${OUT_RRXML_REAL_LINT}
FILE ${OUT_RRXML_REAL}
SCHEMA ${ROUTING_SCHEMA}
)
endif()
# Generate lookahead and place delay lookup caches
set(DEPS)
append_file_dependency(DEPS ${OUT_RRXML_REAL_FILENAME})
append_file_dependency(DEPS ${VIRT_DEVICE_MERGED_FILE})
set(OUTPUTS ${OUT_RRBIN_REAL_FILENAME})
set(ARGS)
if(${DEFINE_DEVICE_CACHE_LOOKAHEAD})
list(APPEND OUTPUTS ${LOOKAHEAD_FILENAME})
list(APPEND ARGS --write_router_lookahead ${LOOKAHEAD_FILENAME})
endif()
if(${DEFINE_DEVICE_CACHE_PLACE_DELAY})
list(APPEND OUTPUTS ${PLACE_DELAY_FILENAME})
list(APPEND ARGS --write_placement_delay_lookup ${PLACE_DELAY_FILENAME})
endif()
add_custom_command(
OUTPUT ${OUT_RRXML_REAL}.cache ${OUTPUTS}
DEPENDS
${WIRE_EBLIF}
${VPR}
${QUIET_CMD}
${DEFINE_DEVICE_DEVICE_TYPE}
${DEPS} ${PYTHON3}
COMMAND
${PYTHON3} ${symbiflow-arch-defs_SOURCE_DIR}/utils/check_cache.py ${OUT_RRXML_REAL} ${OUT_RRXML_REAL}.cache ${OUTPUTS} || (
${QUIET_CMD} ${VPR} ${DEVICE_MERGED_FILE}
--device ${DEVICE_FULL}
${WIRE_EBLIF}
--read_rr_graph ${OUT_RRXML_REAL}
--write_rr_graph ${OUT_RRBIN_REAL}
--read_rr_edge_metadata on
--outfile_prefix ${DEVICE}_${PACKAGE}_cache
--pack
--place
${ARGS}
${DEFINE_DEVICE_CACHE_ARGS} &&
${PYTHON3} ${symbiflow-arch-defs_SOURCE_DIR}/utils/update_cache.py ${OUT_RRXML_REAL} ${OUT_RRXML_REAL}.cache)
COMMAND
${CMAKE_COMMAND} -E copy vpr_stdout.log
rr_graph_${DEVICE}_${PACKAGE}.cache.out
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
)
add_file_target(FILE ${OUT_RRBIN_REAL_FILENAME} GENERATED)
get_file_target(RRBIN_REAL_TARGET ${OUT_RRBIN_REAL_FILENAME})
set_target_properties(
${DEFINE_DEVICE_DEVICE}
PROPERTIES
${PACKAGE}_OUT_RRBIN_REAL ${CMAKE_CURRENT_SOURCE_DIR}/${OUT_RRBIN_REAL_FILENAME}
)
if(${DEFINE_DEVICE_CACHE_LOOKAHEAD})
add_file_target(FILE ${LOOKAHEAD_FILENAME} GENERATED)
# Linearize target dependency.
get_file_target(LOOKAHEAD_TARGET ${LOOKAHEAD_FILENAME})
add_dependencies(${LOOKAHEAD_TARGET} ${RRBIN_REAL_TARGET})
endif()
if(${DEFINE_DEVICE_CACHE_PLACE_DELAY})
add_file_target(FILE ${PLACE_DELAY_FILENAME} GENERATED)
# Linearize target dependency.
get_file_target(PLACE_DELAY_TARGET ${PLACE_DELAY_FILENAME})
add_dependencies(${PLACE_DELAY_TARGET} ${RRBIN_REAL_TARGET})
endif()
if(${DEFINE_DEVICE_CACHE_LOOKAHEAD} OR ${DEFINE_DEVICE_CACHE_PLACE_DELAY})
set_target_properties(
${DEFINE_DEVICE_DEVICE}
PROPERTIES
${PACKAGE}_HAS_PLACE_DELAY_CACHE ${DEFINE_DEVICE_CACHE_PLACE_DELAY}
${PACKAGE}_HAS_LOOKAHEAD_CACHE ${DEFINE_DEVICE_CACHE_LOOKAHEAD}
${PACKAGE}_LOOKAHEAD_FILE ${CMAKE_CURRENT_SOURCE_DIR}/${LOOKAHEAD_FILENAME}
${PACKAGE}_PLACE_DELAY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/${PLACE_DELAY_FILENAME}
)
else()
set_target_properties(
${DEFINE_DEVICE_DEVICE}
PROPERTIES
${PACKAGE}_HAS_PLACE_DELAY_CACHE FALSE
${PACKAGE}_HAS_LOOKAHEAD_CACHE FALSE
)
endif()
# Define dummy boards. PROG_TOOL is set to false to disallow programming.
define_board(
BOARD dummy_${DEFINE_DEVICE_ARCH}_${DEFINE_DEVICE_DEVICE}_${PACKAGE}
DEVICE ${DEFINE_DEVICE_DEVICE}
PACKAGE ${PACKAGE}
PROG_TOOL false
)
install_device_files(
PART ${PART}
DEVICE ${DEFINE_DEVICE_DEVICE}
DEVICE_TYPE ${DEFINE_DEVICE_DEVICE_TYPE}
PACKAGE ${PACKAGE})
endforeach()
endfunction()
function(DEFINE_BOARD)
# ~~~
# DEFINE_BOARD(
# BOARD <board>
# DEVICE <device>
# PACKAGE <package>
# PROG_TOOL <prog_tool>
# [PROG_CMD <command to use PROG_TOOL>
# )
# ~~~
#
# Defines a target board for a project. The listed device and package must
# have been defined using DEFINE_DEVICE.
#
# PROG_TOOL should be an executable that will program a bitstream to the
# specified board. PROG_CMD is an optional command string. If PROG_CMD is not
# provided, PROG_CMD will simply be ${PROG_TOOL}.
#
set(options)
set(oneValueArgs BOARD DEVICE PACKAGE PROG_TOOL PROG_CMD)
set(multiValueArgs)
cmake_parse_arguments(
DEFINE_BOARD
"${options}"
"${oneValueArgs}"
"${multiValueArgs}"
${ARGN}
)
add_custom_target(${DEFINE_BOARD_BOARD})
foreach(ARG DEVICE PACKAGE PROG_TOOL PROG_CMD)
set_target_properties(
${DEFINE_BOARD_BOARD}
PROPERTIES ${ARG} "${DEFINE_BOARD_${ARG}}"
)
endforeach()
# Target for gathering all targets for a particular board.
add_custom_target(all_${DEFINE_BOARD_BOARD}_route)
add_custom_target(all_${DEFINE_BOARD_BOARD}_bin)
endfunction()
function(ADD_OUTPUT_TO_FPGA_TARGET name property file)
add_file_target(FILE ${file} GENERATED)
set_target_properties(${name} PROPERTIES ${property} ${file})
endfunction()
set(VPR_BASE_ARGS
--max_router_iterations 500
--routing_failure_predictor off
--router_high_fanout_threshold -1
--constant_net_method route
CACHE STRING "Base VPR arguments")
set(VPR_EXTRA_ARGS "" CACHE STRING "Extra VPR arguments")
function(ADD_FPGA_TARGET_BOARDS)
# ~~~
# ADD_FPGA_TARGET_BOARDS(
# NAME <name>
# [TOP <top>]
# BOARDS <board list>
# SOURCES <source list>
# TESTBENCH_SOURCES <testbench source list>
# [IMPLICIT_INPUT_IO_FILES]
# [INPUT_IO_FILES <input_io_file list>]
# [EXPLICIT_ADD_FILE_TARGET]
# [EMIT_CHECK_TESTS EQUIV_CHECK_SCRIPT <yosys to script verify two bitstreams gold and gate>]
# )
# ~~~
# Version of ADD_FPGA_TARGET that emits targets for multiple boards.
#
# If INPUT_IO_FILES is supplied, BOARDS[i] will use INPUT_IO_FILES[i].
#
# If IMPLICIT_INPUT_IO_FILES is supplied, INPUT_IO_FILES[i] will be set to
# "BOARDS[i].pcf".
#
# Targets will be named <name>_<board>.
#
set(options EXPLICIT_ADD_FILE_TARGET EMIT_CHECK_TESTS IMPLICIT_INPUT_IO_FILES)
set(oneValueArgs NAME TOP EQUIV_CHECK_SCRIPT)
set(multiValueArgs SOURCES BOARDS INPUT_IO_FILE TESTBENCH_SOURCES)
cmake_parse_arguments(
ADD_FPGA_TARGET_BOARDS
"${options}"
"${oneValueArgs}"
"${multiValueArgs}"
${ARGN}
)
set(INPUT_IO_FILES ${ADD_FPGA_TARGET_BOARDS_INPUT_IO_FILES})
if(NOT "${INPUT_IO_FILES}" STREQUAL "" AND ${ADD_FPGA_TARGET_BOARDS_IMPLICIT_INPUT_IO_FILES})
message(FATAL_ERROR "Cannot request implicit IO files and supply explicit IO file list")
endif()
set(BOARDS ${ADD_FPGA_TARGET_BOARDS_BOARDS})
list(LENGTH BOARDS NUM_BOARDS)
if(${ADD_FPGA_TARGET_BOARDS_IMPLICIT_INPUT_IO_FILES})
foreach(BOARD ${BOARDS})
list(APPEND INPUT_IO_FILES ${BOARD}.pcf)
endforeach()
set(HAVE_IO_FILES TRUE)
else()
list(LENGTH INPUT_IO_FILES NUM_INPUT_IO_FILES)
if(${NUM_INPUT_IO_FILES} GREATER 0)
set(HAVE_IO_FILES TRUE)
else()
set(HAVE_IO_FILES FALSE)
endif()
if(${HAVE_IO_FILES} AND NOT ${NUM_INPUT_IO_FILES} EQUAL ${NUM_BOARDS})
message(FATAL_ERROR "Provide ${NUM_BOARDS} boards and ${NUM_INPUT_IO_FILES} io files, must be equal.")
endif()
endif()
if(NOT ${ADD_FPGA_TARGET_BOARDS_EXPLICIT_ADD_FILE_TARGET})
set(FILE_LIST "")
foreach(SRC ${ADD_FPGA_TARGET_BOARDS_SOURCES} ${ADD_FPGA_TARGET_BOARDS_TESTBENCH_SOURCES})
add_file_target(FILE ${SRC} SCANNER_TYPE verilog)
endforeach()
foreach(SRC ${INPUT_IO_FILES})
add_file_target(FILE ${SRC})
endforeach()
endif()
set(OPT_ARGS "")
foreach(OPT_STR_ARG TOP EQUIV_CHECK_SCRIPT)
if("${ADD_FPGA_TARGET_BOARDS_${OPT_STR_ARG}}" STREQUAL "")
list(APPEND OPT_ARGS ${OPT_STR_ARG} ${ADD_FPGA_TARGET_BOARDS_${OPT_STR_ARG}})
endif()
endforeach()
foreach(OPT_OPTION_ARG EMIT_CHECK_TESTS)
if(${ADD_FPGA_TARGET_BOARDS_${OPT_OPTION_ARG}})
list(APPEND OPT_ARGS ${OPT_OPTION_ARG})
endif()
endforeach()
list(LENGTH ADD_FPGA_TARGET_BOARDS_TESTBENCH_SOURCES NUM_TESTBENCH_SOURCES)
if($NUM_TESTBENCH_SOURCES} GREATER 0)
list(APPEND OPT_ARGS TESTBENCH_SOURCES ${ADD_FPGA_TARGET_BOARDS_TESTBENCH_SOURCES})
endif()
math(EXPR NUM_BOARDS_MINUS_1 ${NUM_BOARDS}-1)
foreach(IDX RANGE ${NUM_BOARDS_MINUS_1})
list(GET BOARDS ${IDX} BOARD)
set(BOARD_OPT_ARGS ${OPT_ARGS})
if(${HAVE_IO_FILES})
list(GET INPUT_IO_FILES ${IDX} INPUT_IO_FILE)
list(APPEND BOARD_OPT_ARGS INPUT_IO_FILE ${INPUT_IO_FILE})
endif()
add_fpga_target(
NAME ${ADD_FPGA_TARGET_BOARDS_NAME}_${BOARD}
BOARD ${BOARD}
SOURCES ${ADD_FPGA_TARGET_BOARDS_SOURCES}
EXPLICIT_ADD_FILE_TARGET
${BOARD_OPT_ARGS}
)
endforeach()
endfunction()
function(ADD_FPGA_TARGET)
# ~~~
# ADD_FPGA_TARGET(
# NAME <name>
# [TOP <top>]
# BOARD <board>
# SOURCES <source list>
# TESTBENCH_SOURCES <testbench source list>
# [INPUT_IO_FILE <input_io_file>]
# [EXPLICIT_ADD_FILE_TARGET]
# [EMIT_CHECK_TESTS EQUIV_CHECK_SCRIPT <yosys to script verify two bitstreams gold and gate>]
# [NO_SYNTHESIS]
# [ASSERT_USAGE <usage_spec>]
# [DEFINES <definitions>]
# [SDC_FILE <sdc file>]
# [BIT_TO_V_EXTRA_ARGS]
# )
# ~~~
#
# ADD_FPGA_TARGET defines a FPGA build targetting a specific board. By
# default input files (SOURCES, TESTBENCH_SOURCES, INPUT_IO_FILE) will be
# implicitly passed to ADD_FILE_TARGET. If EXPLICIT_ADD_FILE_TARGET is
# supplied, this behavior is supressed.
#
# TOP is the name of the top-level module in the design. If no supplied,
# TOP is set to "top".
#
# The SOURCES file list will be used to synthesize the FPGA images.
# INPUT_IO_FILE is required to define an io map. TESTBENCH_SOURCES will be
# used to run test benches.
#
# If NO_SYNTHESIS is supplied, <source list> must be 1 eblif file.
#
# DEFINES is a list of environment variables to be defined during Yosys
# invocation.
#
# SDC_FILE can be supplied to provide a SDC constraints file to the flow.
#
# Targets generated:
#
# * <name>_eblif - Generated eblif file.
# * <name>_route - Generate place and routing synthesized design.
# * <name>_bit - Generate output bitstream.
#
# Outputs for this target will all be located in
# ~~~
# ${CMAKE_CURRENT_BINARY_DIR}/${NAME}/${ARCH}-${DEVICE_TYPE}-${DEVICE}-${PACKAGE}
# ~~~
#
# Output files:
#
# * ${TOP}.eblif - Synthesized design (http://docs.verilogtorouting.org/en/latest/vpr/file_formats/#extended-blif-eblif)
# * ${TOP}_io.place - IO placement.
# * ${TOP}.route - Place and routed design (http://docs.verilogtorouting.org/en/latest/vpr/file_formats/#routing-file-format-route)
# * ${TOP}.${BITSTREAM_EXTENSION} - Bitstream for target.
#
set(options EXPLICIT_ADD_FILE_TARGET EMIT_CHECK_TESTS NO_SYNTHESIS ROUTE_ONLY)
set(oneValueArgs NAME TOP BOARD INPUT_IO_FILE EQUIV_CHECK_SCRIPT AUTOSIM_CYCLES ASSERT_USAGE SDC_FILE INPUT_XDC_FILE)
set(multiValueArgs SOURCES TESTBENCH_SOURCES DEFINES BIT_TO_V_EXTRA_ARGS)
cmake_parse_arguments(
ADD_FPGA_TARGET
"${options}"
"${oneValueArgs}"
"${multiValueArgs}"
${ARGN}
)
get_target_property_required(PYTHON3 env PYTHON3)