RV64I.core_desc

import "RV32I.core_desc"

InstructionSet RV64I extends RV32I {
    architectural_state {
        XLEN = 64;
    }

    instructions {
        LWU { // 80000104: 0000ef03 lwu t5,0(ra)
            encoding: imm[11:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b0000011;
            assembly:"{name(rd)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> offs = X[rs1 % RFS] + (signed<12>)imm;
                unsigned<32> res = (unsigned<32>)MEM[offs];
                if ((rd % RFS) != 0) X[rd % RFS] = (unsigned<XLEN>)res;
            }
        }

        LD {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0000011;
            assembly:"{name(rd)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> offs = X[rs1 % RFS] + (signed)imm;
                signed<64> res = (signed<64>)MEM[offs];
                if ((rd % RFS) != 0) X[rd % RFS] = (unsigned<XLEN>)res;
            }
        }

        SD {
            encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: imm[4:0] :: 7'b0100011;
            assembly:"{name(rs2)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> offs = X[rs1 % RFS] + (signed)imm;
                MEM[offs] = (unsigned<XLEN>)X[rs2 % RFS];
            }
        }

        SLLI {
            encoding: 0b000000 :: shamt[5:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {shamt}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] << shamt;
        }

        SRLI {
            encoding: 0b000000 :: shamt[5:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {shamt}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] >> shamt;
        }

        SRAI {
            encoding: 0b010000 :: shamt[5:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {shamt}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = ((signed)X[rs1 % RFS]) >> shamt;
        }

        ADDIW {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0011011;
            assembly:"{name(rd)}, {name(rs1)}, {imm}";
            behavior: {
                if ((rd % RFS) != 0) {
                    signed<32> res = X[rs1 % RFS] + (signed)imm;
                    X[rd % RFS] = (signed<64>)res;
                }
            }
        }

        SLLIW {
            encoding: 7'b0000000 :: shamt[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0011011;
            assembly:"{name(rd)}, {name(rs1)}, {shamt}";
            behavior: {
                if ((rd % RFS) != 0) {
                    unsigned<32> sh_val = ((unsigned<32>)X[rs1 % RFS]) <<  shamt;
                    X[rd % RFS] = (unsigned<64>)(signed)sh_val;
                }
            }
        }

        SRLIW {
            encoding: 7'b0000000 :: shamt[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0011011;
            assembly:"{name(rd)}, {name(rs1)}, {shamt}";
            behavior: {
                if ((rd % RFS) != 0) {
                    unsigned<32> sh_val = ((unsigned<32>)X[rs1 % RFS]) >> shamt;
                    X[rd % RFS] = (unsigned<64>)(signed)sh_val;
                }
            }
        }

        SRAIW {
            encoding: 7'b0100000 :: shamt[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0011011;
            assembly:"{name(rd)}, {name(rs1)}, {shamt}";
            behavior: {
                if ((rd % RFS) != 0) {
                    signed<32> sh_val = ((signed<32>)X[rs1 % RFS]) >> shamt;
                    X[rd % RFS] = (unsigned<64>)sh_val;
                }
            }
        }

        ADDW {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0111011;
            behavior: {
                if ((rd % RFS) != 0) {
                    signed<32> res = (signed<32>)X[rs1 % RFS] + (signed<32>)X[rs2 % RFS];
                    X[rd % RFS] = (signed<64>)res;
                }
            }
        }

        SUBW {
            encoding: 7'b0100000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0111011;
            behavior: {
                if ((rd % RFS) != 0) {
                    signed<32> res = (signed<32>)X[rs1 % RFS] - (signed<32>)X[rs2 % RFS];
                    X[rd % RFS] = (signed<64>)res;
                }
            }
        }

        SLLW {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0111011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: {
                if ((rd % RFS) != 0) {
                    unsigned<32> count = (unsigned)X[rs2 % RFS] & 0x1f;
                    unsigned<32> sh_val = ((unsigned<32>)X[rs1 % RFS]) << count;
                    X[rd % RFS] = (unsigned<64>)(signed)sh_val;
                }
            }
        }

        SRLW {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0111011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: {
                if ((rd % RFS) != 0) {
                    unsigned<32> count = (unsigned)X[rs2 % RFS] & 0x1f;
                    unsigned<32> sh_val = ((unsigned<32>)X[rs1 % RFS]) >> count;
                    X[rd % RFS] = (unsigned<64>)(signed)sh_val;
                }
            }
        }

        SRAW {
            encoding: 7'b0100000 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0111011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: {
                if ((rd % RFS) != 0) {
                    unsigned<32> count = (unsigned)X[rs2 % RFS] & 0x1f;
                    signed<32> sh_val = ((signed<32>)X[rs1 % RFS]) >> count;
                    X[rd % RFS] = (signed<64>)sh_val;
                }
            }
        }
    }
}