Machine mode CSRs not accessible with Ibex host core when using Vicuna's verilated model

[AnjaliVerma1314]

Unable to get the cycle count by reading a machine mode CSR (mcycle) on verilated model of Vicuna with Ibex host core. The machine mode CSRs seem to be not accessible with Ibex host core on Vicuna's verilator.

[aaqdas]

I am facing a similar problem. It declares it illegal instruction.

Update: I just remembered this issue, from the time I ran some simulations earlier. In the folder /sim, when you run the command make verilator, you need to run make verilator CORE=cv32e40x which uses the core cv32e40x instead of ibex. This resolves the problem

[AlfredoRodrigues4]

I'm facing the same problem, when I use Ibex I can't access the CSRs. Can any of you remember how you solved this? With cv32e40x it works, but I need Ibex specifically