Rare infinite stall triggered by a specific delay constellation during memory transactions

[moimfeld]

Hi @michael-platzer,

Issue

I found a situation where Vicuna would stall forever (i.e. instr_complete_valid is never asserted for the corresponding instruction). This situation can happen when there is memory transaction delay enabled on both the memory request handshake and the memory result transaction. Vicuna stalls when a memory result transaction of an "older" instruction happens after Vicuna has already started issuing memory requests for "newer" instructions. After such an event, the "newer" instruction will not have a corresponding instr_complete_valid signal an therefore also no result transaction.

In the screenshot below you can see that a memory result with id = 3 happens at 1305 ns while Vicuna has already offloaded a memory request with id = 5 at 1285 ns.

How to reproduce

Run the following command to reproduce the issue with the UVM environment.

make UVM_TESTNAME=cvxif_test_direct_issue_85 SEED=5

The issue is quite rare, this is why I had to look for a random seed that would trigger this infinite stall (the default seed 0 did not trigger the issue). I hope the issue is reproducible on different versions of QuestaSim with this seed. Let me know if there are any issues.

Sidenote

In the screenshot one can also see that the memory_req.last signal is not asserted during the last memory transaction, but a few cycles later. I assume this comes from "suppressing" certain memory requests. I think this is not compliant with the cvxif specs.

[michael-platzer]

Hi @moimfeld,

Thanks for this bug report. You are right, the issue is related to the suppressed memory requests. Thanks also for pointing out the issue with the last signal!

I will think about a better way to deal with memory requests for invalid parts of a vector register.