Verilator problem in simulating added custom config

[Mousavikia]

Hi @michael-platzer... In verilator simulation I have tried this:
Added config to config.mk:

ifeq ($(VPROC_CONFIG), littlekian)
  VMEM_W          := 64
  VREG_W          ?= 128
  VPROC_PIPELINES ?= $(VMEM_W):VLSU $(shell echo $$(($(VREG_W) / 2))):VALU,VELEM                  \
                                    $(shell echo $$(($(VREG_W) / 2))):VMUL,VSLD
else

Verilator command in sim directory:
make PROG_PATHS=progs.txt VPROC_CONFIG=littlekian MEM_W=64
Result:
Verilator freeze and I see no answer. Also in FPGA implementation, I have done everything you said about SRAM and hwreg_iface implementation and change in signal lengths in demo_top.sv but no answer is transmitted via uart there still. Moreover in verilator, when runing the code with compact config (MEM_W=32) everything is fine and results are correct. I even enabled cache for my added config since you said when cache is enabled there is no need to have MEM_W=VMEM_W. The verilator command is like this:
make PROG_PATHS=progs.txt VPROC_CONFIG=littlekian ICACHE_SZ=1024 DCACHE_SZ=1024
This time the verilator ends the simulation but returns no answers regardless of the configuration I pass to it. I hope this time I am asking a better question that worths the time.
The test code is attached (I tried non aligned version of variables as well).
vecaddtimer.txt