Illegal configuration created by config.mk

[moimfeld]

Hi @michael-platzer,

when using the VPORT_POLICY=many policy, the Makefile can generate configurations where the maximum PIPE_W is equal to VREG_W.
When one PIPE_W is equal to VREG_W then the MAX_OP_W of one vproc_pipeline is also equal to VREG_W. This will trigger the fatal error below:

vicuna/rtl/vproc_pipeline.sv

Lines 98 to 102 in d3c1cf8

	if ((MAX_OP_W & (MAX_OP_W - 1)) != 0 || MAX_OP_W < 32 || MAX_OP_W >= VREG_W) begin
	$fatal(1, "The vector pipeline operand width MAX_OP_W must be at least 32, less than ",
	"the vector register width VREG_W and a power of two. ",
	"The current value of %d is invalid.", MAX_OP_W);
	end

The following lines in the config.mk cause this "issue":

vicuna/config.mk

Line 37 in d3c1cf8

VPROC_PIPELINES ?= $(VMEM_W):VLSU,VALU,VELEM $(VPIPE_W_VMUL):VMUL,VSLD

vicuna/config.mk

Lines 67 to 70 in d3c1cf8

	ifeq ($(VPORT_POLICY), many)
	VPIPE_W_DFLT := $(VREG_W)
	VPIPE_W_VMUL := $(VREG_W)
	else

[michael-platzer]

@moimfeld Thanks for reporting! Two units are still causing problems when the operand width equals the register width, but I am working on resolving this and will then change this fatal error to only trigger if the operand width is larger than VREG_W.

[Aravind-kris]

@moimfeld Thanks for reporting! Two units are still causing problems when the operand width equals the register width, but I am working on resolving this and will then change this fatal error to only trigger if the operand width is larger than VREG_W.

Did you solved it ? Please let me know.