gcc+cross: update to 14.2.0+glibc2.40+1

app-devel/gcc+cross/01-amd64/patches/0083-Fix-a-potential-deadlock-in-some-older-Loongson3-MIP.patch → app-devel/gcc+cross/01-amd64/patches/0001-Fix-a-potential-deadlock-in-some-older-Loongson3-MIP.patch

@@ -1,7 +1,7 @@
-From d801e59700c3cebd9a7fcb0f3950e9b9b17548b5 Mon Sep 17 00:00:00 2001
+From 86b0a8b18aa2d68b5ed6b8400b353923b6d697e9 Mon Sep 17 00:00:00 2001
 From: Paul Hua <[email protected]>
 Date: Fri, 30 Nov 2018 20:45:57 +0800
-Subject: [PATCH 83/87] Fix a potential deadlock in some older Loongson3 MIPS
+Subject: [PATCH 1/2] Fix a potential deadlock in some older Loongson3 MIPS
  processors.
 
 In some older Loongson3 processors there is a LL/SC errata that can
@@ -42,17 +42,17 @@ gcc/testsuite/
  gcc/config/mips/mips.h                        |  4 +++-
  gcc/config/mips/mips.opt                      |  4 ++++
  gcc/doc/install.texi                          |  4 ++++
- gcc/doc/invoke.texi                           |  9 +++++++++
+ gcc/doc/invoke.texi                           |  8 ++++++++
  .../gcc.target/mips/fix-loongson3-llsc.c      | 10 ++++++++++
  gcc/testsuite/gcc.target/mips/mips.exp        |  1 +
- 8 files changed, 59 insertions(+), 5 deletions(-)
+ 8 files changed, 58 insertions(+), 5 deletions(-)
  create mode 100644 gcc/testsuite/gcc.target/mips/fix-loongson3-llsc.c
 
 diff --git a/gcc/config.gcc b/gcc/config.gcc
-index 8681568b858..1d641526f69 100644
+index 95c91ee02be..1f92789898d 100644
 --- a/gcc/config.gcc
 +++ b/gcc/config.gcc
-@@ -4723,7 +4723,7 @@ case "${target}" in
+@@ -4842,7 +4842,7 @@ case "${target}" in
  		;;
 
  	mips*-*-*)
@@ -61,7 +61,7 @@ index 8681568b858..1d641526f69 100644
 
  		case ${with_float} in
  		"" | soft | hard)
-@@ -4900,6 +4900,21 @@ case "${target}" in
+@@ -5019,6 +5019,21 @@ case "${target}" in
  			exit 1
  			;;
  		esac
@@ -83,7 +83,7 @@ index 8681568b858..1d641526f69 100644
  		;;
 
  	loongarch*-*)
-@@ -5892,7 +5907,7 @@ case ${target} in
+@@ -6031,7 +6046,7 @@ case ${target} in
  esac
 
  t=
@@ -93,10 +93,10 @@ index 8681568b858..1d641526f69 100644
  do
  	eval "val=\$with_"`echo $option | sed s/-/_/g`
 diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
-index ca822758b41..e365bb60f4f 100644
+index 1156d212c1f..8eda1b53e06 100644
 --- a/gcc/config/mips/mips.cc
 +++ b/gcc/config/mips/mips.cc
-@@ -14300,7 +14300,7 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands)
+@@ -14501,7 +14501,7 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands)
    mips_multi_start ();
 
    /* Output the release side of the memory barrier.  */
@@ -105,7 +105,7 @@ index ca822758b41..e365bb60f4f 100644
      {
        if (required_oldval == 0 && TARGET_OCTEON)
  	{
-@@ -14321,6 +14321,10 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands)
+@@ -14522,6 +14522,10 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands)
    /* Output the branch-back label.  */
    mips_multi_add_label ("1:");
 
@@ -116,7 +116,7 @@ index ca822758b41..e365bb60f4f 100644
    /* OLDVAL = *MEM.  */
    mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
  		       oldval, mem, NULL);
-@@ -14430,13 +14434,18 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands)
+@@ -14631,13 +14635,18 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands)
      mips_multi_add_insn ("li\t%0,1", cmp, NULL);
 
    /* Output the acquire side of the memory barrier.  */
@@ -137,10 +137,10 @@ index ca822758b41..e365bb60f4f 100644
  }
 
 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
-index 6daf6d37165..159195f1c1d 100644
+index 616a275b918..99fa8d9c315 100644
 --- a/gcc/config/mips/mips.h
 +++ b/gcc/config/mips/mips.h
-@@ -917,7 +917,9 @@ struct mips_cpu_info {
+@@ -931,7 +931,9 @@ struct mips_cpu_info {
    {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
    {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" }, \
    {"compact-branches", "%{!mcompact-branches=*:-mcompact-branches=%(VALUE)}" }, \
@@ -152,10 +152,10 @@ index 6daf6d37165..159195f1c1d 100644
  /* A spec that infers the:
     -mnan=2008 setting from a -mips argument,
 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
-index 195f5be01cc..cd1f8e85da3 100644
+index c1abb36212f..5c2abed716b 100644
 --- a/gcc/config/mips/mips.opt
 +++ b/gcc/config/mips/mips.opt
-@@ -193,6 +193,10 @@ mfix4300
+@@ -214,6 +214,10 @@ mfix4300
  Target Var(TARGET_4300_MUL_FIX)
  Work around an early 4300 hardware bug.
 
@@ -167,10 +167,10 @@ index 195f5be01cc..cd1f8e85da3 100644
  Target Var(TARGET_FP_EXCEPTIONS) Init(1)
  FP exceptions are enabled.
 diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
-index a787af85671..2b30700caeb 100644
+index 9f2e427be68..155aa79ac0d 100644
 --- a/gcc/doc/install.texi
 +++ b/gcc/doc/install.texi
-@@ -1716,6 +1716,10 @@ These features are extensions to the traditional
+@@ -1762,6 +1762,10 @@ These features are extensions to the traditional
  SVR4-based MIPS ABIs and require support from GNU binutils
  and the runtime C library.
 
@@ -182,26 +182,18 @@ index a787af85671..2b30700caeb 100644
  On certain targets this option sets the default stack clash protection guard
  size as a power of two in bytes.  On AArch64 @var{size} is required to be either
 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
-index 5a00f62ba8e..bf9df284301 100644
+index f82f7d2817b..87460d3f48f 100644
 --- a/gcc/doc/invoke.texi
 +++ b/gcc/doc/invoke.texi
-@@ -1075,6 +1075,7 @@ Objective-C and Objective-C++ Dialects}.
- -mpic-data-is-text-relative}
-
- @emph{MIPS Options}
-+<<<<<<< HEAD
- @gccoptlist{-EL  -EB  -march=@var{arch}  -mtune=@var{arch}
- -mips1  -mips2  -mips3  -mips4  -mips32  -mips32r2  -mips32r3  -mips32r5
- -mips32r6  -mips64  -mips64r2  -mips64r3  -mips64r5  -mips64r6
-@@ -1123,6 +1124,7 @@ Objective-C and Objective-C++ Dialects}.
+@@ -1156,6 +1156,7 @@ Objective-C and Objective-C++ Dialects}.
  -mfix-r10000  -mno-fix-r10000  -mfix-rm7000  -mno-fix-rm7000
  -mfix-vr4120  -mno-fix-vr4120
  -mfix-vr4130  -mno-fix-vr4130  -mfix-sb1  -mno-fix-sb1
 +-mfix-loongson3-llsc  -mno-fix-loongson3-llsc
  -mflush-func=@var{func}  -mno-flush-func
  -mbranch-cost=@var{num}  -mbranch-likely  -mno-branch-likely
  -mcompact-branches=@var{policy}
-@@ -27543,6 +27545,13 @@ controls GCC's implementation of this workaround.  It assumes that
+@@ -28899,6 +28900,13 @@ controls GCC's implementation of this workaround.  It assumes that
  aborted accesses to any byte in the following regions does not have
  side effects:
 
@@ -232,10 +224,10 @@ index 00000000000..f82e39a47ef
 +/* { dg-final { scan-assembler "1:\n\tsync\n\tll" } } */
 +/* { dg-final { scan-assembler "2:\n\tsync\n" } } */
 diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp
-index 15d574202d3..744ebe80c71 100644
+index e028bc93b40..500da3f46f7 100644
 --- a/gcc/testsuite/gcc.target/mips/mips.exp
 +++ b/gcc/testsuite/gcc.target/mips/mips.exp
-@@ -283,6 +283,7 @@ foreach option {
+@@ -284,6 +284,7 @@ foreach option {
      fix-r4000
      fix-r10000
      fix-vr4130
@@ -244,5 +236,5 @@ index 15d574202d3..744ebe80c71 100644
      local-sdata
      long-calls
 -- 
-2.43.0
+2.47.1