Merge pull request #145 from kshitij-sisodia-arm/feature/od-vsi-support

MLECO-4536: Adding VSI video support

cmsis-pack-examples/README.md

@@ -14,11 +14,13 @@
 - [Prerequisites](#prerequisites)
   - [Visual Studio Code](#visual-studio-code)
   - [Packs](#packs)
+  - [Virtual Streaming Interface](#virtual-streaming-interface)
 - [Building the examples](#building-the-examples)
   - [Launch project in Visual Studio Code](#launch-project-in-visual-studio-code)
   - [Download Software Packs](#download-software-packs)
   - [Generate and build the project](#generate-and-build-the-project)
-  - [Execute project](#execute-project)
+  - [Execute Project](#execute-project)
+    - [Working with Virtual Streaming Interface](#working-with-virtual-streaming-interface)
   - [Application output](#application-output)
 - [Trademarks](#trademarks)
 - [Licenses](#licenses)
@@ -107,6 +109,33 @@ CMSIS-Pack defines a standardized way to deliver software components, device par
 support information and code. A list of available CMSIS-Packs can be found
 [here](https://developer.arm.com/tools-and-software/embedded/cmsis/cmsis-packs).
 
+## Virtual Streaming Interface
+
+[Virtual Streaming Interface)](https://arm-software.github.io/AVH/main/simulation/html/group__arm__vsi.html)
+(VSI) is available for certain
+[Fixed Virtual Platform](https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms) (FVP) or
+[Arm Virtual Hardware](https://developer.arm.com/Tools%20and%20Software/Arm%20Virtual%20Hardware) (AVH)
+targets. For VSI supported examples, you may need to install some dependencies.
+
+For more details and up-to-date requirements, see
+[Python environment setup](https://arm-software.github.io/AVH/main/simulation/html/group__arm__vsi__pyenv.html)
+which mentions:
+
+> The following packages are required on Linux systems (Ubuntu 20.04 and later):
+>   - libatomic1
+>   - python3.9
+>   - python3-pip
+
+In addition to the above, the VSI Python scripts depend on `opencv-python` package. We recommend using
+a virtual environment and installing this with pip.
+
+```shell
+$ pip install opencv-python
+```
+
+**NOTE**: The requirement for Python version is driven by the FVP executable. Versions <= 11.26 require
+Python3.9 but this may change for future releases.
+
 # Building the examples
 
 ## Launch project in Visual Studio Code
@@ -181,12 +210,12 @@ Build complete
 
 The built artifacts will be located under the `out/` directory in the project root.
 
-## Execute project
+## Execute Project
 
 The project is configured for execution on Arm Virtual Hardware which removes the requirement for
 a physical hardware board.
 
-- When using a Fixed Virtual Platform installed locally:
+- When using a Fixed Virtual Platform (FVP) installed locally:
   ```shell
   $ <path_to_installed_FVP> -a ./out/kws/AVH-SSE-300-U55/Debug/kws.Debug+AVH-SSE-300-U55.axf -f ./FVP/FVP_Corstone_SSE-300/fvp_config.txt
   ```
@@ -218,6 +247,21 @@ For example:
 $ cp ./out/kws/STM32F746-DISCO/Release/kws.Release+STM32F746-DISCO.bin /media/user/DIS_F746NG/ && sync
 ```
 
+### Working with Virtual Streaming Interface
+
+The object detection example for Arm Corstone-300 and Corstone-310 supports Virtual Streaming Interface (VSI).
+This allows the locally installed FVP application (or an AVH instance) to read images in from a camera connected to
+your local machine and stream these over to the application running within the FVP.
+
+To run the VSI application, append the command line with the v_path argument. For example:
+
+```shell
+  $ <path_to_installed_FVP> \
+    -a ./out/object-detection-vsi/AVH-SSE-300-U55/Release/object-detection-vsi.axf \
+    -C ethosu.num_macs=256 \
+    -C mps3_board.v_path=./device/corstone/vsi/video/python/
+  ```
+
 ## Application output
 
 Once the project can be built successfully, the execution on target hardware will show output of
@@ -378,4 +422,21 @@ spot immediately. Please help us improve this section by reporting them via GitH
    Currently Keil Studio Cloud only supports running with the Arm® Ethos™-U55 on AVH
    virtual targets.
    You can build the project but will have to run it on your local machine on an
-   installation of the equivalent Fixed Virtual Platform containing Arm® Ethos™-U65 NPU.
+   installation of the equivalent Fixed Virtual Platform containing Arm® Ethos™-U65 NPU.
+
+7. The newer versions of BSP packs for Arm® Corstone™-300 and Arm® Corstone™-310 require CMSIS 6.
+   There are warnings about some unsatisfied requirements because of this. For example:
+   ```shell
+   MISSING ARM::Device:[email protected]
+    require CMSIS:[email protected]
+   MISSING ARM::Device:Native Driver:[email protected]
+    require CMSIS:[email protected]
+   MISSING ARM::Device:Native Driver:[email protected]
+    require CMSIS:[email protected]
+   MISSING ARM::Device:Native Driver:[email protected]
+    require CMSIS:[email protected]
+   MISSING ARM::Device:Startup&C [email protected]
+    require CMSIS:[email protected]
+   ```
+   These are expected to be resolved once we bump up the version of CMSIS core pack. Currently,
+   this is blocked by other dependencies.

cmsis-pack-examples/device/alif-ensemble/alif-ensemble-E7-device.clayer.yml

@@ -67,7 +67,6 @@ layer:
     - component: AlifSemiconductor::Device:SOC Peripherals:PINCONF
     - component: AlifSemiconductor::Device:SOC Peripherals:MHU
     - component: AlifSemiconductor::Device:Startup
-    - component: ARM::CMSIS Driver:USART
     - component: ARM::CMSIS Driver:USART:Custom
 
     - component: AlifSemiconductor::Device:SOC Peripherals:DMA

cmsis-pack-examples/device/corstone/src/BoardInit.cpp

@@ -66,7 +66,11 @@ static void arm_ethosu_npu_irq_handler(void)
 /** @brief  Initialises the NPU IRQ */
 static void arm_ethosu_npu_irq_init(void)
 {
-    const IRQn_Type ethosu_irqnum = (IRQn_Type)ETHOS_U55_IRQn;
+    #if defined(CORSTONE310_FVP)
+        const IRQn_Type ethosu_irqnum = (IRQn_Type)NPU0_IRQn;
+    #else
+        const IRQn_Type ethosu_irqnum = (IRQn_Type)ETHOS_U55_IRQn;
+    #endif
 
     /* Register the EthosU IRQ handler in our vector table.
      * Note, this handler comes from the EthosU driver */
@@ -87,7 +91,11 @@ static int arm_ethosu_npu_init(void)
     arm_ethosu_npu_irq_init();
 
     /* Initialise Ethos-U device */
-    void* const ethosu_base_address = (void*)(ETHOS_U55_APB_BASE_S);
+    #if defined(CORSTONE310_FVP)
+        void* const ethosu_base_address = (void*)(NPU0_APB_BASE_NS);
+    #else
+        void* const ethosu_base_address = (void*)(ETHOS_U55_APB_BASE_S);
+    #endif
 
     debug("Cache arena: 0x%p\n", get_cache_arena());
 

cmsis-pack-examples/device/corstone/vsi/include/arm_vsi.h

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Virtual Streaming Interface (VSI)
+ */
+
+#ifndef __ARM_VSI_H
+#define __ARM_VSI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __IM
+#define __IM  volatile const    /*! Defines 'read only' structure member permissions */
+#endif
+#ifndef __OM
+#define __OM  volatile          /*! Defines 'write only' structure member permissions */
+#endif
+#ifndef __IOM
+#define __IOM volatile          /*! Defines 'read/write' structure member permissions */
+#endif
+
+#include <stdint.h>
+
+/// Structure type to access the virtual streaming interface
+typedef struct
+{
+  /// Interrupt Request (IRQ)
+  struct {
+    __IOM uint32_t Enable;      /*!< (R/W) IRQ Enable */
+    __OM  uint32_t Set;         /*!< (-/W) IRQ Set */
+    __OM  uint32_t Clear;       /*!< (-/W) IRQ Clear */
+    __IM  uint32_t Status;      /*!< (R/-) IRQ Status */
+  } IRQ;
+  uint32_t reserved1[60];
+  /// Time counter with 1MHz input frequency
+  struct {
+    __IOM uint32_t Control;     /*!< (R/W) Timer Control */
+    __IOM uint32_t Interval;    /*!< (R/W) Timer Interval Value (in microseconds) */
+    __IM  uint32_t Count;       /*!< (R/-) Timer Overflow Count */
+  } Timer;
+  uint32_t reserved2[61];
+  /// Direct Memory Access (DMA) Controller
+  struct {
+    __IOM uint32_t Control;     /*!< (R/W) DMA Control */
+    __IOM uint32_t Address;     /*!< (R/W) DMA Memory Start Address */
+    __IOM uint32_t BlockSize;   /*!< (R/W) DMA Block Size (in bytes, multiple of 4) */
+    __IOM uint32_t BlockNum;    /*!< (R/W) DMA Number of Blocks (must be 2^n) */
+    __IM  uint32_t BlockIndex;  /*!< (R/-) DMA Block Index */
+  } DMA;
+  uint32_t reserved3[59];
+  __IOM uint32_t Regs[64];      /*!< (R/W) User Registers */
+} ARM_VSI_Type;
+
+/* VSI Timer Control Definitions for Timer.Control register */
+#define ARM_VSI_Timer_Run_Pos           0U                                      /*!< Timer Control: Run Position */
+#define ARM_VSI_Timer_Run_Msk           (1UL << ARM_VSI_Timer_Run_Pos)          /*!< Timer Control: Run Mask */
+#define ARM_VSI_Timer_Periodic_Pos      1U                                      /*!< Timer Control: Periodic Position */
+#define ARM_VSI_Timer_Periodic_Msk      (1UL << ARM_VSI_Timer_Periodic_Pos)     /*!< Timer Control: Periodic Mask */
+#define ARM_VSI_Timer_Trig_IRQ_Pos      2U                                      /*!< Timer Control: Trig_IRQ Position */
+#define ARM_VSI_Timer_Trig_IRQ_Msk      (1UL << ARM_VSI_Timer_Trig_IRQ_Pos)     /*!< Timer Control: Trig_IRQ Mask */
+#define ARM_VSI_Timer_Trig_DMA_Pos      3U                                      /*!< Timer Control: Trig_DAM Position */
+#define ARM_VSI_Timer_Trig_DMA_Msk      (1UL << ARM_VSI_Timer_Trig_DMA_Pos)     /*!< Timer Control: Trig_DMA Mask */
+
+/* VSI DMA Control Definitions for DMA.Control register */
+#define ARM_VSI_DMA_Enable_Pos          0U                                      /*!< DMA Control: Enable Position */
+#define ARM_VSI_DMA_Enable_Msk          (1UL << ARM_VSI_DMA_Enable_Pos)         /*!< DMA Control: Enable Mask */
+#define ARM_VSI_DMA_Direction_Pos       1U                                      /*!< DMA Control: Direction Position */
+#define ARM_VSI_DMA_Direction_Msk       (1UL << ARM_VSI_DMA_Direction_Pos)      /*!< DMA Control: Direction Mask */
+#define ARM_VSI_DMA_Direction_P2M       (0UL*ARM_VSI_DMA_Direction_Msk)         /*!< DMA Control: Direction P2M */
+#define ARM_VSI_DMA_Direction_M2P       (1UL*ARM_VSI_DMA_Direction_Msk)         /*!< DMA Control: Direction M2P */
+
+/* Memory mapping of 8 VSI peripherals */
+#define ARM_VSI0_BASE           (0x4FF00000UL)                          /*!< VSI 0 Base Address */
+#define ARM_VSI1_BASE           (0x4FF10000UL)                          /*!< VSI 1 Base Address */
+#define ARM_VSI2_BASE           (0x4FF20000UL)                          /*!< VSI 2 Base Address */
+#define ARM_VSI3_BASE           (0x4FF30000UL)                          /*!< VSI 3 Base Address */
+#define ARM_VSI4_BASE           (0x4FF40000UL)                          /*!< VSI 4 Base Address */
+#define ARM_VSI5_BASE           (0x4FF50000UL)                          /*!< VSI 5 Base Address */
+#define ARM_VSI6_BASE           (0x4FF60000UL)                          /*!< VSI 6 Base Address */
+#define ARM_VSI7_BASE           (0x4FF70000UL)                          /*!< VSI 7 Base Address */
+#define ARM_VSI0                ((ARM_VSI_Type *)ARM_VSI0_BASE)         /*!< VSI 0 struct */
+#define ARM_VSI1                ((ARM_VSI_Type *)ARM_VSI1_BASE)         /*!< VSI 1 struct */
+#define ARM_VSI2                ((ARM_VSI_Type *)ARM_VSI2_BASE)         /*!< VSI 2 struct */
+#define ARM_VSI3                ((ARM_VSI_Type *)ARM_VSI3_BASE)         /*!< VSI 3 struct */
+#define ARM_VSI4                ((ARM_VSI_Type *)ARM_VSI4_BASE)         /*!< VSI 4 struct */
+#define ARM_VSI5                ((ARM_VSI_Type *)ARM_VSI5_BASE)         /*!< VSI 5 struct */
+#define ARM_VSI6                ((ARM_VSI_Type *)ARM_VSI6_BASE)         /*!< VSI 6 struct */
+#define ARM_VSI7                ((ARM_VSI_Type *)ARM_VSI7_BASE)         /*!< VSI 7 struct */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARM_VSI_H */

cmsis-pack-examples/device/corstone/vsi/provenance.md

@@ -0,0 +1,10 @@
+# Origin of files in this directory
+
+- `include`: https://github.com/ARM-software/AVH/tree/1d9e2b02001a6e5d8f2fd622e5cf301144604007/interface/include
+- `video`: https://github.com/ARM-software/AVH/tree/1d9e2b02001a6e5d8f2fd622e5cf301144604007/interface/video
+
+**Note**: Files in this repository and files from [AVH repository](https://github.com/ARM-software/AVH/)
+should be under the same license terms.
+
+* See [AVH repository LICENSE](https://github.com/ARM-software/AVH/blob/1d9e2b02001a6e5d8f2fd622e5cf301144604007/LICENSE)
+* This repository's [LICENSE](../../../LICENSE)