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Merge pull request #545 from armanbilge/topic/535
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Micro-optimization + bump base version
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mpilquist authored Nov 4, 2023
2 parents e25d489 + ea468f5 commit 65a8b34
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Showing 2 changed files with 3 additions and 3 deletions.
2 changes: 1 addition & 1 deletion build.sbt
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
import com.typesafe.tools.mima.core._

ThisBuild / tlBaseVersion := "3.3"
ThisBuild / tlBaseVersion := "3.4"

ThisBuild / organization := "com.comcast"
ThisBuild / organizationName := "Comcast Cable Communications Management, LLC"
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4 changes: 2 additions & 2 deletions shared/src/main/scala/com/comcast/ip4s/Cidr.scala
Original file line number Diff line number Diff line change
Expand Up @@ -138,9 +138,9 @@ object Cidr {
* This means the address will never have any bits set outside the prefix. For example, a range
* such as 192.168.0.1/31 is not allowed.
*/
final class Strict[+A <: IpAddress] private (override val prefix: A, prefixBits: Int)
extends Cidr[A](prefix, prefixBits) {
final class Strict[+A <: IpAddress] private (address: A, prefixBits: Int) extends Cidr[A](address, prefixBits) {
override def normalized: this.type = this
override def prefix = address
}

object Strict {
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