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added modules to test ddrc phy over axi read/write
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@AndreyFilippov
AndreyFilippov committed May 20, 2014
1 parent 03bce21 commit 5034058
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5 changes: 3 additions & 2 deletions axi/axibram_write.v
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Expand Up @@ -89,7 +89,7 @@ module axibram_write #(
reg [ 1:0] wburst; // registered burst type
reg [ 3:0] wlen; // registered awlen type (for wrapped over transfers)
wire [ADDRESS_BITS-1:0] next_wr_address_w; // next transfer address;
wire bram_we_w; // write BRAM memory
wire bram_we_w; //,bram_we_nonmasked; // write BRAM memory non-masked - should be combined with
wire start_write_burst_w;
wire write_in_progress_w;
reg dev_ready_r; // device, selected at start burst
Expand All @@ -98,7 +98,8 @@ module axibram_write #(
(wburst[0]? {ADDRESS_BITS{1'b0}}:((write_address[ADDRESS_BITS-1:0]+1) & {{(ADDRESS_BITS-4){1'b1}}, ~wlen[3:0]})):
(wburst[0]? (write_address[ADDRESS_BITS-1:0]+1):(write_address[ADDRESS_BITS-1:0]));

assign bram_we_w= w_nempty && write_in_progress && dev_ready_r;
assign bram_we_w= w_nempty && write_in_progress && dev_ready_r;
// assign bram_we_nonmasked= w_nempty && write_in_progress;
assign start_write_burst_w=aw_nempty && (!write_in_progress || (w_nempty && (write_left[3:0]==4'b0)));
assign write_in_progress_w=aw_nempty || (write_in_progress && !(w_nempty && (write_left[3:0]==4'b0)));

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69 changes: 69 additions & 0 deletions ddrc_control.v
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@@ -0,0 +1,69 @@
/*******************************************************************************
* Module: ddrc_control
* Date:2014-05-19
* Author: Andrey Filippov
* Description: Temporary module with DDRC control / command registers
*
* Copyright (c) 2014 Elphel, Inc.
* ddrc_control.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ddrc_control.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps

module ddrc_control #(
parameter AXI_WR_ADDR_BITS= 12,
parameter SELECT_ADDR = 'h800, // address to select this module
parameter SELECT_ADDR_MASK = 'h800, // address mask to select this module
parameter BUSY_ADDR = 'hc00, // address to generate busy
parameter BUSY_ADDR_MASK = 'hc00 // address mask to generate busy
)(
input clk,
input mclk,
input rst,
input [AXI_WR_ADDR_BITS-1:0] pre_waddr, // AXI write address, before actual writes (to generate busy), valid@start_burst
input start_wburst, // burst start - should generate ~ready (should be AND-ed with !busy internally)
input [AXI_WR_ADDR_BITS-1:0] waddr, // write address, valid with wr_en
input wr_en, // write enable
input [31:0] wdata, // write data, valid with waddr and wr_en
output busy, // interface busy (combinatorial delay from start_wburst and pre_addr
// control signals
// control: sequencer run
output [10:0] run_addr, // Start address of the physical sequencer (MSB = 0 - "manual", 1 -"auto")
output [ 3:0] run_chn, // channel number to use for I/O buffers
output run_seq, // single mclk pulse to start sequencer
// input run_done; // output - will go through other channel - sequencer done (add busy?)
// control: delays and mmcm setup
output [ 7:0] dly_data, // 8-bit IDELAY/ODELAY (fine) and MMCM phase shift
output [ 6:0] dly_addr, // address to select delay register
output ld_delay, // write dly_data to dly_address, one mclk active pulse
output set, // transfer (activate) all delays simultaneosly, 1 mclk pulse
// control: additional signals
output cmda_tri, // tri-state all command and address lines to DDR chip
output inv_clk_div, // invert clk_div to ISERDES
output [ 7:0] dqs_pattern, // DQS pattern during write (normally 8'h55)
output [ 7:0] dqm_pattern, // DQM pattern (just for testing, should be 8'h0)
// control: buffers pages
output [ 1:0] port0_page, // port 0 buffer read page (to be controlled by arbiter later, set to 2'b0)
output [ 1:0] port0_int_page, // port 0 PHY-side write to buffer page (to be controlled by arbiter later, set to 2'b0)
output [ 1:0] port1_page, // port 1 buffer write page (to be controlled by arbiter later, set to 2'b0)
output [ 1:0] port1_int_page // port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0)

);
reg busy_r=0;
reg selected_r=0;

// assign busy=busy_r && start_wburst?(((pre_addr ^ SELECT_ADDR) & SELECT_ADDR_MASK)==0): selected_r;
assign busy=busy_r && start_wburst?(((pre_waddr ^ BUSY_ADDR) & BUSY_ADDR_MASK)==0): selected_r;

endmodule

50 changes: 50 additions & 0 deletions ddrc_status.v
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/*******************************************************************************
* Module: ddrc_status
* Date:2014-05-19
* Author: Andrey Filippov
* Description: Read status/radback information from the DDR controller
*
* Copyright (c) 2014 Elphel, Inc.
* ddrc_status.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ddrc_status.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps

module ddrc_status#(
parameter AXI_RD_ADDR_BITS= 12,
parameter SELECT_ADDR = 'h800, // address to select this module
parameter SELECT_ADDR_MASK = 'h800, // address mask to select this module
parameter BUSY_ADDR = 'hc00, // address to generate busy
parameter BUSY_ADDR_MASK = 'hc00 // address mask to generate busy
)(
input clk,
input mclk,
input rst,
input [AXI_RD_ADDR_BITS-1:0] pre_raddr, // AXI reade address, before actual reads (to generate busy), valid@start_burst
input start_rburst, // burst start - should generate ~ready (should be AND-ed with !busy internally)
input [AXI_RD_ADDR_BITS-1:0] raddr, // read address, valid with rd_en
input rd_en, // read enable
output [31:0] rdata, // read data, should valid with raddr and rd_en
output busy, // interface busy (combinatorial delay from start_wburst and pre_addr
// status/readback signals
input run_done, // sequencer done (add busy?)
input run_busy, // sequencer busy

input locked, // MMCM and PLL locked
input ps_rdy, // MMCM phase shift control ready
input [ 7:0] ps_out // MMCM phase shift value (in 1/56 of the Fvco period)
);


endmodule

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