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CVM Development #3980

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CVM Development #3980

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yxtx1994
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@yxtx1994 yxtx1994 commented Dec 4, 2024

  • Add bitmap module in MMU for memory isolation
  • Add memory encryption module based on AXI protoco
  • We can don't using these modules by setting the option HasCVMExtension&HasMEMencryption to false

@Tang-Haojin Tang-Haojin marked this pull request as draft December 4, 2024 08:28
@good-circle good-circle marked this pull request as ready for review December 9, 2024 03:38
eastonman
eastonman requested changes Dec 10, 2024
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src/main/scala/device/MemEncrypt.scala Outdated Show resolved Hide resolved
src/main/scala/device/MemEncryptUtil.scala Outdated Show resolved Hide resolved
src/main/scala/xiangshan/backend/fu/PMP.scala Show resolved Hide resolved
eastonman
eastonman approved these changes Dec 25, 2024
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Ok, frontend part LGTM

@eastonman
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Maybe @Gao-Zeyu should also check this out.

yxtx1994 and others added 20 commits December 30, 2024 11:33
@yxtx1994
[feat] Updata Bitmap check in SV48
0f92ab8
@xzs5454 @yxtx1994
[fix] ptw fsm inner logic
c2ab6a1
@yxtx1994
[feat] Add MemEncrypt module to xiangshan device (moudule code only)
deefcf9
@yxtx1994
[fix] the bitmap check logic in PageTableCache(s2x_info =/= allStage …
2dbd6da 
…|| ishptw)

[fix] the signal “toLLPTW” gen logic(s2xlate === noS2xlate || s2xlate === onlyStage1)
[fix] the handle flow of jmp_bitmap_check and s2xlate === onlyStage2 request in PTW
@yxtx1994
[feat] Add a connection to the Memenc module in Soc.scala
ccd3506 
[feat] Add the option to implement the Memenc module in CVMconfig
@xzs5454 @yxtx1994
[fix] ptw hptw's pte need delay one cycle
42acf2e
@xzs5454 @yxtx1994
[fix] fix bitmap wakeup logic
13ef45c
@yxtx1994
[fix] keyid_check in PMP module, add leaveHitMux & valid same with pm…
959ef42 
…p_match_res
@yxtx1994
[fix] when jmp_bitmap_check valid lunch more used signal in PTW/HPTW
b7461f4
@yxtx1994
[feat] add HasDelayNoEncryption option and implementation to MemEncry…
fb83fea 
…ption module

[feat] delete unnecessary parameters in Soc
@yxtx1994
[feat] when HasDelayNoEncryption is ture, REG memenc_enable in MemEnc…
fa33901 
…ryptCSR is default ture.
@yxtx1994
[feat] Add option HasBitmapCheckDefault for test specific.
9645000 
[feat] Add lock logic for CSR MCVM.BME&BMA when BME is valid.
@yxtx1994
[feat] Add BMAField{ResetBMA,TestBMA} for HasBitmapCheckDefault option.
616189e
@yxtx1994
[feat] Rebase Xiangshan commit id 1856091
76092df
@yxtx1994
[fix] The Mux that generates wait_id in Bitmap is replaced PriorityMu…
c20bf8e 
…x from ParallelMux.
@yxtx1994
[fix] Reg ast_req_accepted update in MemEncryptCSR
d15ab8f 
[feat] Add BCLARE bit in CSR MCVM used for clear bitmap cache
[fix] bitmap req merge logic of enq entry and after lookup cache entry
[feat] remove bitmapReg clear logic in PTWCache for *fence, add clear logic when refill l0&sp
[fix] latch and update more state when PTW get jmp_bitmap_check req
@yxtx1994
[feat] Update WithNKBL1D config and MEMENCRange AddressSet
9bc7072
@yxtx1994
[feat] CSR MCVM uses Machine level Custom Read/Write Addr
8aa8a66 
[fix] l0BitmapReg wakeup uses pte_index without OHToUInt
[fix] bmppn compare and need_addr_check logic in LLPTW
@yxtx1994
[fix] bug in bitmap_cache module of output cfs gen in error cycle
eb4b270
@yxtx1994
chore: add licenses and author affiliations to some files
8fe0d42
@yxtx1994
chore: add licenses to files of memory encryption modules
8c588de
@yxtx1994
style: updata code style of Frontend.scala about CVM modify
db33a6c
@yxtx1994
fix(BitmapCache): Add resp_valid_reg flush logic when sfence.valid or…
6acc31c 
… *atp.changed.

feat: Move KeyIDBits config from SoC.scala to Configs.scala, add KeyIDBits usage in PMP.scala.
chore: remove needless licenses in MemEncrypt.scala and MemEncryptUtil.scala.
@yxtx1994
refactor：Modified the config register and parameters associated with …
fcf4b0c 
…Bitmap check

    *MCVM changed to MBMC(Machine Lavel Bitmap Check Register)
    *Modified ‘BME’、‘BCLEAR’、‘CMODE’ to CSR MBMC's lower bits
    *All related parameters remove ”Option“
    *HasCVMExtension changed to HasBitmapCheck
@yxtx1994 yxtx1994 requested a review from linjuanZ as a code owner January 3, 2025 02:57
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[Generated by IPC robot]
commit: fcf4b0c

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
fcf4b0c 1.814 0.442 2.639 1.231 2.152 2.141 2.360 0.933 1.407 1.985 3.107 2.558 2.267 3.308

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
2f0227e 1.231 0.933 3.107 3.308
ca892e7 0.442 2.639 1.231 2.360 0.933 1.406 3.107 2.558 3.308
51aa1b6 1.814 0.442 2.639 1.231 2.152 2.141 2.360 0.933 1.403 1.985 3.107 2.558 2.267 3.308
ae39693 1.814 0.442 2.639 1.231 2.152 2.141 2.361 0.933 1.403 1.985 3.107 2.558 2.267 3.308

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@eastonman eastonman eastonman approved these changes

@good-circle good-circle Awaiting requested review from good-circle good-circle is a code owner

@cebarobot cebarobot Awaiting requested review from cebarobot cebarobot is a code owner

@Lemover Lemover Awaiting requested review from Lemover

@linjuanZ linjuanZ Awaiting requested review from linjuanZ linjuanZ is a code owner

@Tang-Haojin Tang-Haojin Awaiting requested review from Tang-Haojin

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@yxtx1994 @eastonman @XiangShanRobot @xzs5454