LKP-Core: Change minimum mask width and clearance to 0. Slight GND vi…

…a rearrangements.
Project-Alpaca · Mar 14, 2021 · d2ee060 · d2ee060
1 parent cd58127
commit d2ee060
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Showing 2 changed files with 15 additions and 16 deletions.
diff --git a/pcb/LKP-Core/LKP-Core.kicad_pcb b/pcb/LKP-Core/LKP-Core.kicad_pcb
@@ -65,8 +65,7 @@
     (mod_text_width 0.15)
     (pad_size 1.524 1.524)
     (pad_drill 0.762)
-    (pad_to_mask_clearance 0.05)
-    (solder_mask_min_width 0.0762)
+    (pad_to_mask_clearance 0)
     (aux_axis_origin 0 0)
     (grid_origin 146.875 98)
     (visible_elements FFFFFF7F)
@@ -2065,7 +2064,7 @@
   (via (at 153.675 105.6) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1))
   (via (at 141.875 87.6) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1))
   (via (at 136.675 108.9) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1))
-  (via (at 155.775 98) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1))
+  (via (at 155.511 98) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1))
   (segment (start 137.212087 93.837087) (end 137.424219 93.837087) (width 0.5) (layer F.Cu) (net 1) (status 30))
   (via (at 146.475 105.3) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1))
   (segment (start 137.512087 93.637087) (end 137.624219 93.637087) (width 0.5) (layer F.Cu) (net 1) (status 30))

diff --git a/pcb/LKP-Core/LKP-Core.pro b/pcb/LKP-Core/LKP-Core.pro
@@ -1,4 +1,4 @@
-update=Sat 27 Feb 2021 01:41:16 AM AST
+update=Sun 14 Mar 2021 03:27:41 AM ADT
 version=1
 last_client=kicad
 [general]
@@ -12,6 +12,16 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=out/
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
 [pcbnew]
 version=1
 PageLayoutDescrFile=
@@ -55,8 +65,8 @@ OthersTextSizeH=1
 OthersTextSizeThickness=0.15
 OthersTextItalic=0
 OthersTextUpright=1
-SolderMaskClearance=0.05
-SolderMaskMinWidth=0.07619999999999999
+SolderMaskClearance=0
+SolderMaskMinWidth=0
 SolderPasteClearance=0
 SolderPasteRatio=-0
 [pcbnew/Layer.F.Cu]
@@ -259,13 +269,3 @@ uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=out/
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1