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Do not unroll gates in basis in add_control
#13475
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Pull Request Test Coverage Report for Build 12179929323Warning: This coverage report may be inaccurate.This pull request's base commit is no longer the HEAD commit of its target branch. This means it includes changes from outside the original pull request, including, potentially, unrelated coverage changes.
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if operation.definition is not None and operation.definition.global_phase: | ||
global_phase += operation.definition.global_phase | ||
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basis = ["p", "u", "x", "z", "rx", "ry", "rz", "cx"] |
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Any reason for this fixed list of gates? what about other gates like:
y / s / t / sx / cz / cp ?
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for example, it seems that mcy is not as efficiently decomposed as mcx or mcz, see #13514
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This was the original list in the code, this PR ensures we don't unroll unnecessarily but doesn't change what we unroll. For a bugfix PR I'd keep it this way, but we should add the cases above for main
!
target, | ||
use_basis_gates=True, | ||
) | ||
circuit.mcp(phi, controls, target) |
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why do you use here mcp-mcry-mcp and not mcrz-mcry-mcrz (which should have less CX gates) ?
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I didn't touch any of the synthesis logic in this PR, just how we unroll 🙂
We can change this in a PR to main
, but MCP-MCRY-MCP is not the same as MCRZ-MCRY-MCRZ due to the phase difference, so wouldn't that implement a different unitary?
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LGTM, thanks for the fix
* Do not unroll gates in basis * add tests * review comments * Add reno (cherry picked from commit 582070d)
@Mergifyio backport stable/1.4 |
✅ Backports have been created
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* Do not unroll gates in basis * add tests * review comments * Add reno (cherry picked from commit 582070d)
* Do not unroll gates in basis * add tests * review comments * Add reno (cherry picked from commit 582070d) Co-authored-by: Julien Gacon <[email protected]>
Summary
The
add_control
mechanism currently does some redundant unrolling and re-wrapping of gates that are already in the basis of gates we know how to control. This has knock-on effects and causes #13473, by translating an RZ operation (already supported) to a Phase gate.This PR avoids this unrolling. As discussed with @alexanderivrii, in the longer term we should consider rewriting this logic entirely and have a controlled gate plugin, which also allows users to supply their own control mechanism.
Details and comments
U(0,0,0)
gates.