Implemented AdvSimdScalar TwoRegisterMiscFp16

SamboyCoding · Sep 12, 2024 · 43f4ec3 · 43f4ec3
1 parent 4e07a59
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diff --git a/Disarm.Tests/SimdTest.cs b/Disarm.Tests/SimdTest.cs
@@ -351,4 +351,29 @@ public void TestScalarAdvancedSimdScalarXIndexedElement()
         inst = DisassembleAndCheckMnemonic(0x7FA09021, Arm64Mnemonic.FMULX);
         Assert.Equal("0x00000000 FMULX S1, S1, V0.S[1]", inst.ToString());
     }
+
+    [Fact]
+    public void TestScalarAdvancedSimdScalarTwoRegisterMiscFp16()
+    {
+        DisassembleAndCheckMnemonic(0x5E79A812, Arm64Mnemonic.FCVTNS);
+        DisassembleAndCheckMnemonic(0x5E79B812, Arm64Mnemonic.FCVTMS);
+        DisassembleAndCheckMnemonic(0x5E79C812, Arm64Mnemonic.FCVTAS);
+        DisassembleAndCheckMnemonic(0x5E79D812, Arm64Mnemonic.SCVTF);
+        DisassembleAndCheckMnemonic(0x5EF8C812, Arm64Mnemonic.FCMGT);
+        DisassembleAndCheckMnemonic(0x5EF8D812, Arm64Mnemonic.FCMEQ);
+        DisassembleAndCheckMnemonic(0x5EF8E812, Arm64Mnemonic.FCMLT);
+        DisassembleAndCheckMnemonic(0x5EF9A812, Arm64Mnemonic.FCVTPS);
+        DisassembleAndCheckMnemonic(0x5EF9B812, Arm64Mnemonic.FCVTZS);
+        DisassembleAndCheckMnemonic(0x5EF9D812, Arm64Mnemonic.FRECPE);
+        DisassembleAndCheckMnemonic(0x5EF9F812, Arm64Mnemonic.FRECPX);
+        DisassembleAndCheckMnemonic(0x7E79A812, Arm64Mnemonic.FCVTNU);
+        DisassembleAndCheckMnemonic(0x7E79B812, Arm64Mnemonic.FCVTMU);
+        DisassembleAndCheckMnemonic(0x7E79C812, Arm64Mnemonic.FCVTAU);
+        DisassembleAndCheckMnemonic(0x7E79D812, Arm64Mnemonic.UCVTF);
+        DisassembleAndCheckMnemonic(0x7EF8C812, Arm64Mnemonic.FCMGE);
+        DisassembleAndCheckMnemonic(0x7EF8D812, Arm64Mnemonic.FCMLE);
+        DisassembleAndCheckMnemonic(0x7EF9A812, Arm64Mnemonic.FCVTPU);
+        DisassembleAndCheckMnemonic(0x7EF9B812, Arm64Mnemonic.FCVTZU);
+        DisassembleAndCheckMnemonic(0x7EF9D812, Arm64Mnemonic.FRSQRTE);
+    }
 }
diff --git a/Disarm/InternalDisassembly/Arm64ScalarAdvancedSimd.cs b/Disarm/InternalDisassembly/Arm64ScalarAdvancedSimd.cs
@@ -401,10 +401,46 @@ public static Arm64Instruction ScalarXIndexedElement(uint instruction)
 
     public static Arm64Instruction TwoRegisterMiscFp16(uint instruction)
     {
-        return new()
+        var u = (instruction >> 29) & 1; // Bit 29
+        var a = (instruction >> 23) & 1; // Bit 23
+        var opcode = (instruction >> 12) & 0b1_1111; // Bits 12-16
+        var rd = (int)(instruction >> 5) & 0b1_1111; // Bits 5-9
+        var rn = (int)instruction & 0b1_1111; // Bits 0-4
+
+        return new ()
         {
-            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
-            MnemonicCategory = Arm64MnemonicCategory.Unspecified, //Could be comparison, math, conversion, or general data processing
+            Mnemonic = (u, a, opcode) switch
+            {
+                (0, 0, 0b11010) => Arm64Mnemonic.FCVTNS,
+                (0, 0, 0b11011) => Arm64Mnemonic.FCVTMS,
+                (0, 0, 0b11100) => Arm64Mnemonic.FCVTAS,
+                (0, 0, 0b11101) => Arm64Mnemonic.SCVTF,
+
+                (0, 1, 0b01100) => Arm64Mnemonic.FCMGT,
+                (0, 1, 0b01101) => Arm64Mnemonic.FCMEQ,
+                (0, 1, 0b01110) => Arm64Mnemonic.FCMLT,
+                (0, 1, 0b11010) => Arm64Mnemonic.FCVTPS,
+                (0, 1, 0b11011) => Arm64Mnemonic.FCVTZS,
+                (0, 1, 0b11101) => Arm64Mnemonic.FRECPE,
+                (0, 1, 0b11111) => Arm64Mnemonic.FRECPX,
+
+                (1, 0, 0b11010) => Arm64Mnemonic.FCVTNU,
+                (1, 0, 0b11011) => Arm64Mnemonic.FCVTMU,
+                (1, 0, 0b11100) => Arm64Mnemonic.FCVTAU,
+                (1, 0, 0b11101) => Arm64Mnemonic.UCVTF,
+
+                (1, 1, 0b01100) => Arm64Mnemonic.FCMGE,
+                (1, 1, 0b01101) => Arm64Mnemonic.FCMLE,
+                (1, 1, 0b11010) => Arm64Mnemonic.FCVTPU,
+                (1, 1, 0b11011) => Arm64Mnemonic.FCVTZU,
+                (1, 1, 0b11101) => Arm64Mnemonic.FRSQRTE,
+                _ => throw new Arm64UndefinedInstructionException("Unallocated")
+            },
+            MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath,
+            Op0Kind = Arm64OperandKind.Register,
+            Op1Kind = Arm64OperandKind.Register,
+            Op0Reg = Arm64Register.H0 + rd,
+            Op1Reg = Arm64Register.H0 + rn,
         };
     }