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Feed-Forward-Neural-Network-Hardware-Accelerator
Feed-Forward-Neural-Network-Hardware-Accelerator PublicHardware implementation written in SystemVerilog for a parameterizable FF-NN. Depth and Neurons per layer are parameters. Learning using SGD back propagation algorithm.
Verilog 2
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vos
vos Publicx86-64 OS with fat32 support, simple process and memory management, and user level application support
C
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Risc-V-Implementation
Risc-V-Implementation PublicRisc V Architecture implemented in SystemVerilog with a Data and Instruction Cache as well as Hardware Thread support
C
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