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[driver] smhc update for new driver
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SamulKyull authored and SamulKyull committed Nov 13, 2024
1 parent 4eb6f50 commit 2dfa06c
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Showing 5 changed files with 92 additions and 21 deletions.
30 changes: 26 additions & 4 deletions board/avaota-a1/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -106,8 +106,6 @@ sunxi_sdhci_t sdhci0 = {
.name = "sdhci0",
.id = MMC_CONTROLLER_0,
.reg_base = SUNXI_SMHC0_BASE,
.clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG,
.clk_base = CCU_BASE + CCU_SMHC0_CLK_REG,
.sdhci_mmc_type = MMC_TYPE_SD,
.max_clk = 50000000,
.width = SMHC_WIDTH_4BIT,
Expand All @@ -122,14 +120,25 @@ sunxi_sdhci_t sdhci0 = {
.gpio_cd = {GPIO_PIN(GPIO_PORTF, 6), GPIO_INPUT},
.cd_level = GPIO_LEVEL_LOW,
},
.clk_ctrl = {
.gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(0),
.rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(0),
},
.sdhci_clk = {
.reg_base = CCU_BASE + CCU_SMHC0_CLK_REG,
.reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET,
.reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET,
.clk_sel = 0x1,
.parent_clk = 300000000,
},
};

sunxi_sdhci_t sdhci2 = {
.name = "sdhci2",
.id = MMC_CONTROLLER_2,
.reg_base = SUNXI_SMHC2_BASE,
.clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG,
.clk_base = CCU_BASE + CCU_SMHC2_CLK_REG,
.sdhci_mmc_type = MMC_TYPE_EMMC,
.max_clk = 25000000,
.width = SMHC_WIDTH_8BIT,
Expand All @@ -148,6 +157,19 @@ sunxi_sdhci_t sdhci2 = {
.gpio_ds = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX3},
.gpio_rst = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX3},
},
.clk_ctrl = {
.gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(2),
.rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(2),
},
.sdhci_clk = {
.reg_base = CCU_BASE + CCU_SMHC2_CLK_REG,
.reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET,
.reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET,
.clk_sel = 0x1,
.parent_clk = 600000000,
},
};

sunxi_i2c_t i2c_pmu = {
Expand Down
21 changes: 12 additions & 9 deletions board/avaota-cam/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
#include <sys-dram.h>
#include <sys-gpio.h>
#include <sys-i2c.h>
#include <sys-sdhci.h>
#include <mmc/sys-sdhci.h>
#include <sys-spi.h>
#include <sys-uart.h>

Expand Down Expand Up @@ -136,14 +136,14 @@ sunxi_sdhci_t sdhci1 = {
.sdhci_mmc_type = MMC_TYPE_SD,
.max_clk = 50000000,
.width = SMHC_WIDTH_4BIT,
.dma_des_addr = SDRAM_BASE + 0x20080000,
.dma_des_addr = SDRAM_BASE + 0x10080000,
.pinctrl = {
.gpio_clk = {GPIO_PIN(GPIO_PORTD, 3), GPIO_PERIPH_MUX6},
.gpio_cmd = {GPIO_PIN(GPIO_PORTD, 4), GPIO_PERIPH_MUX6},
.gpio_d0 = {GPIO_PIN(GPIO_PORTD, 2), GPIO_PERIPH_MUX6},
.gpio_d1 = {GPIO_PIN(GPIO_PORTD, 1), GPIO_PERIPH_MUX6},
.gpio_d2 = {GPIO_PIN(GPIO_PORTD, 5), GPIO_PERIPH_MUX6},
.gpio_d3 = {GPIO_PIN(GPIO_PORTD, 6), GPIO_PERIPH_MUX6},
.gpio_clk = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX2},
.gpio_cmd = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX2},
.gpio_d0 = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX2},
.gpio_d1 = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX2},
.gpio_d2 = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX2},
.gpio_d3 = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX2},
},
.clk_ctrl = {
.gate_reg_base = SUNXI_CCU_APP_BASE + BUS_CLK_GATING1_REG,
Expand All @@ -153,7 +153,10 @@ sunxi_sdhci_t sdhci1 = {
},
.sdhci_clk = {
.reg_base = SUNXI_CCU_APP_BASE + SMHC_CTRL1_CLK_REG,
.clk_sel = SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_PERI_219M,
.reg_factor_n_offset = SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_DIV2_OFFSET,
.reg_factor_m_offset = SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_DIV1_OFFSET,
.clk_sel = SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_PERI_192M,
.parent_clk = 192000000,
},
};

Expand Down
30 changes: 26 additions & 4 deletions board/longanpi-4b/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -106,8 +106,6 @@ sunxi_sdhci_t sdhci0 = {
.name = "sdhci0",
.id = MMC_CONTROLLER_0,
.reg_base = SUNXI_SMHC0_BASE,
.clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG,
.clk_base = CCU_BASE + CCU_SMHC0_CLK_REG,
.sdhci_mmc_type = MMC_TYPE_SD,
.max_clk = 50000000,
.width = SMHC_WIDTH_4BIT,
Expand All @@ -122,14 +120,25 @@ sunxi_sdhci_t sdhci0 = {
.gpio_cd = {GPIO_PIN(GPIO_PORTF, 6), GPIO_INPUT},
.cd_level = GPIO_LEVEL_LOW,
},
.clk_ctrl = {
.gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(0),
.rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(0),
},
.sdhci_clk = {
.reg_base = CCU_BASE + CCU_SMHC0_CLK_REG,
.reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET,
.reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET,
.clk_sel = 0x1,
.parent_clk = 300000000,
},
};

sunxi_sdhci_t sdhci2 = {
.name = "sdhci2",
.id = MMC_CONTROLLER_2,
.reg_base = SUNXI_SMHC2_BASE,
.clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG,
.clk_base = CCU_BASE + CCU_SMHC2_CLK_REG,
.sdhci_mmc_type = MMC_TYPE_EMMC,
.max_clk = 25000000,
.width = SMHC_WIDTH_8BIT,
Expand All @@ -148,6 +157,19 @@ sunxi_sdhci_t sdhci2 = {
.gpio_ds = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX3},
.gpio_rst = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX3},
},
.clk_ctrl = {
.gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(2),
.rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(2),
},
.sdhci_clk = {
.reg_base = CCU_BASE + CCU_SMHC2_CLK_REG,
.reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET,
.reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET,
.clk_sel = 0x1,
.parent_clk = 600000000,
},
};

sunxi_i2c_t i2c_pmu = {
Expand Down
30 changes: 26 additions & 4 deletions board/lt527x/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -105,8 +105,6 @@ sunxi_sdhci_t sdhci0 = {
.name = "sdhci0",
.id = MMC_CONTROLLER_0,
.reg_base = SUNXI_SMHC0_BASE,
.clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG,
.clk_base = CCU_BASE + CCU_SMHC0_CLK_REG,
.sdhci_mmc_type = MMC_TYPE_SD,
.max_clk = 50000000,
.width = SMHC_WIDTH_4BIT,
Expand All @@ -121,14 +119,25 @@ sunxi_sdhci_t sdhci0 = {
.gpio_cd = {GPIO_PIN(GPIO_PORTF, 6), GPIO_INPUT},
.cd_level = GPIO_LEVEL_LOW,
},
.clk_ctrl = {
.gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(0),
.rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(0),
},
.sdhci_clk = {
.reg_base = CCU_BASE + CCU_SMHC0_CLK_REG,
.reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET,
.reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET,
.clk_sel = 0x1,
.parent_clk = 300000000,
},
};

sunxi_sdhci_t sdhci2 = {
.name = "sdhci2",
.id = MMC_CONTROLLER_2,
.reg_base = SUNXI_SMHC2_BASE,
.clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG,
.clk_base = CCU_BASE + CCU_SMHC2_CLK_REG,
.sdhci_mmc_type = MMC_TYPE_EMMC,
.max_clk = 25000000,
.width = SMHC_WIDTH_8BIT,
Expand All @@ -147,6 +156,19 @@ sunxi_sdhci_t sdhci2 = {
.gpio_ds = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX3},
.gpio_rst = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX3},
},
.clk_ctrl = {
.gate_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(2),
.rst_reg_base = CCU_BASE + CCU_SMHC_BGR_REG,
.rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(2),
},
.sdhci_clk = {
.reg_base = CCU_BASE + CCU_SMHC2_CLK_REG,
.reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET,
.reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET,
.clk_sel = 0x1,
.parent_clk = 600000000,
},
};

sunxi_i2c_t i2c_pmu = {
Expand Down
2 changes: 2 additions & 0 deletions include/drivers/mmc/sys-sdhci.h
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Original file line number Diff line number Diff line change
Expand Up @@ -125,6 +125,8 @@ typedef struct sunxi_sdhci {

#define SDHCI_DEFAULT_CLK_RST_OFFSET(x) (16 + x)
#define SDHCI_DEFAULT_CLK_GATE_OFFSET(x) (x)
#define SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET (0)
#define SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET (8)

/**
* @brief Initialize the SDHC controller.
Expand Down

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