[driver] add new spi driver

YuzukiHD · Nov 10, 2024 · 44130c0 · 44130c0
1 parent 7297daf
commit 44130c0
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Showing 16 changed files with 1,266 additions and 553 deletions.
diff --git a/board/avaota-cam/board.c b/board/avaota-cam/board.c
@@ -28,8 +28,8 @@ sunxi_serial_t uart_dbg = {
         .stop = UART_STOP_BIT_0,
         .parity = UART_PARITY_NO,
         .gpio_pin = {
-                .gpio_tx = {GPIO_PIN(GPIO_PORTL, 4), GPIO_PERIPH_MUX3},
-                .gpio_rx = {GPIO_PIN(GPIO_PORTL, 5), GPIO_PERIPH_MUX3},
+                .gpio_tx = {GPIO_PIN(GPIO_PORTD, 22), GPIO_PERIPH_MUX3},
+                .gpio_rx = {GPIO_PIN(GPIO_PORTD, 23), GPIO_PERIPH_MUX3},
         },
         .uart_clk = {
                 .gate_reg_base = SUNXI_CCU_APP_BASE + BUS_CLK_GATING0_REG,
@@ -57,7 +57,7 @@ sunxi_dma_t sunxi_dma = {
 sunxi_spi_t sunxi_spi0 = {
         .base = SUNXI_SPI0_BASE,
         .id = 0,
-        .clk_rate = 75 * 1000 * 1000,
+        .clk_rate = 25 * 1000 * 1000,
         .gpio = {
                 .gpio_cs = {GPIO_PIN(GPIO_PORTC, 10), GPIO_PERIPH_MUX3},
                 .gpio_sck = {GPIO_PIN(GPIO_PORTC, 9), GPIO_PERIPH_MUX3},
@@ -66,12 +66,17 @@ sunxi_spi_t sunxi_spi0 = {
                 .gpio_wp = {GPIO_PIN(GPIO_PORTC, 6), GPIO_PERIPH_MUX3},
                 .gpio_hold = {GPIO_PIN(GPIO_PORTC, 7), GPIO_PERIPH_MUX3},
         },
-        .clk_reg = {
-                .rst_reg_base = SUNXI_CCU_APP_BASE + BUS_Reset0_REG,
-                .rst_reg_offset = BUS_Reset0_REG_HRESETN_SGDMA_SW_OFFSET,
-                .gate_reg_base = SUNXI_CCU_APP_BASE + BUS_CLK_GATING0_REG,
-                .gate_reg_offset = BUS_CLK_GATING0_REG_SGDMA_HCLK_EN_OFFSET,
-                .parent_clk = 307000000,
+        .spi_clk = {
+                .spi_clock_cfg_base = SUNXI_CCU_APP_BASE + SPI_CLK_REG,
+                .spi_clock_factor_n_offset = SPI_CLK_REG_SPI_SCLK_DIV2_OFFSET,
+                .spi_clock_source = SPI_CLK_REG_SPI_SCLK_SEL_PERI_307M,
+        },
+        .parent_clk_reg = {
+                .rst_reg_base = SUNXI_CCU_APP_BASE + BUS_Reset1_REG,
+                .rst_reg_offset = BUS_Reset1_REG_HRESETN_SPI_SW_OFFSET,
+                .gate_reg_base = SUNXI_CCU_APP_BASE + BUS_CLK_GATING1_REG,
+                .gate_reg_offset = BUS_CLK_GATING1_REG_SPI_HCLK_EN_OFFSET,
+                .parent_clk = 307200000,
         },
         .dma_handle = &sunxi_dma,
 };

diff --git a/board/avaota-cam/cdk/avaota_cam.cdkproj b/board/avaota-cam/cdk/avaota_cam.cdkproj
@@ -433,10 +433,10 @@
       <File Name="../../../src/drivers/sys-spi.c" ExcludeProjConfig="">
         <FileOption/>
       </File>
-      <File Name="../../../src/drivers/sys-spi-nand.c" ExcludeProjConfig="BuildSet">
+      <File Name="../../../src/drivers/sys-spi-nand.c" ExcludeProjConfig="">
         <FileOption/>
       </File>
-      <File Name="../../../src/drivers/sys-spi-nor.c" ExcludeProjConfig="BuildSet">
+      <File Name="../../../src/drivers/sys-spi-nor.c" ExcludeProjConfig="">
         <FileOption/>
       </File>
       <VirtualDirectory Name="mmc">
@@ -486,6 +486,9 @@
           </File>
         </VirtualDirectory>
       </VirtualDirectory>
+      <File Name="../../../src/drivers/sys-spis.c" ExcludeProjConfig="BuildSet">
+        <FileOption/>
+      </File>
     </VirtualDirectory>
     <VirtualDirectory Name="log">
       <File Name="../../../src/log/log.c">
@@ -731,7 +734,7 @@
   </BuildConfigs>
   <DebugSessions>
     <watchExpressions/>
-    <memoryExpressions>0x0;;;</memoryExpressions>
+    <memoryExpressions>;;;</memoryExpressions>
     <statistics>;;32;;MHZ;;up</statistics>
     <peripheralTabs/>
     <WatchDisplayFormat>1</WatchDisplayFormat>

diff --git a/board/avaota-cam/hello_world/main.c b/board/avaota-cam/hello_world/main.c
@@ -11,7 +11,9 @@
 #include <sys-clk.h>
 #include <sys-dma.h>
 #include <sys-dram.h>
+#include <sys-gpio.h>
 #include <sys-i2c.h>
+#include <sys-spi-nor.h>
 
 #include <common.h>
 
@@ -23,6 +25,7 @@ extern sunxi_serial_t uart_dbg;
 extern dram_para_t dram_para;
 extern sunxi_dma_t sunxi_dma;
 extern sunxi_i2c_t sunxi_i2c0;
+extern sunxi_spi_t sunxi_spi0;
 
 msh_declare_command(helloworld);
 
@@ -54,15 +57,9 @@ int main(void) {
 
     uint64_t dram_size = sunxi_dram_init(&dram_para);
 
-    sunxi_dma_init(&sunxi_dma);
+    sunxi_spi_init(&sunxi_spi0);
 
-    sunxi_dma_test((uint32_t *) 0x81008000, (uint32_t *) 0x80008000);
-
-    sunxi_i2c_init(&sunxi_i2c0);
-
-    uint8_t axp_val = 0;
-
-    sunxi_i2c_read(&sunxi_i2c0, 0x37, 0x00, &axp_val);
+    spi_nor_detect(&sunxi_spi0);
 
     syterkit_shell_attach(commands);
 

diff --git a/cmake/board/100ask-ros.cmake b/cmake/board/100ask-ros.cmake
@@ -11,7 +11,6 @@ set(CONFIG_BOARD_100ASK_ROS True)
 
 add_definitions(-DCONFIG_CHIP_GPIO_V1)
 add_definitions(-DCONFIG_CHIP_SUN50IW10)
-add_definitions(-DSUNXI_DRAM_PARAM_V2)
 
 set(CONFIG_USE_DRAM_PAYLOAD True)
 set(CONFIG_USE_PREBUILT_DRAM_PAYLOAD True)

diff --git a/include/drivers/reg/reg-spi.h b/include/drivers/reg/reg-spi.h
@@ -60,6 +60,7 @@
 #define SPI_INT_STA_SSI (0x1 << 13)                                                    /* SS invalid interrupt, when set SS has changed from valid to invalid */
 #define SPI_INT_STA_ERR (SPI_INT_STA_TX_OVF | SPI_INT_STA_RX_UDR | SPI_INT_STA_RX_OVF) /* NO txFIFO underrun */
 #define SPI_INT_STA_MASK (0x77 | (0x3f << 8))
+#define SPI_INT_STA_PENDING_BIT (0xffffffff)
 
 /* SPI FIFO Control Register Bit Fields & Masks,default value:0x0040_0001 */
 #define SPI_FIFO_CTL_RX_LEVEL (0xFF << 0)  /* rxFIFO reday request trigger level,default 0x1 */
@@ -82,14 +83,22 @@
 #define SPI_RXCNT_BIT_POS (0)
 #define SPI_TXCNT_BIT_POS (16)
 
+#define SPI_FIFO_CTL_SHIFT (0x4)
+
 /* SPI Wait Clock Register Bit Fields & Masks,default value:0x0000_0000 */
 #define SPI_WAIT_WCC_MASK (0xFFFF << 0) /* used only in master mode: Wait Between Transactions */
 #define SPI_WAIT_SWC_MASK (0xF << 16)   /* used only in master mode: Wait before start dual data transfer in dual SPI mode */
 
 /* SPI Clock Control Register Bit Fields & Masks,default:0x0000_0002 */
-#define SPI_CLK_CTL_CDR2 (0xFF << 0) /* Clock Divide Rate 2,master mode only : SPI_CLK = AHB_CLK/(2*(n+1)) */
-#define SPI_CLK_CTL_CDR1 (0xF << 8)  /* Clock Divide Rate 1,master mode only : SPI_CLK = AHB_CLK/2^n */
-#define SPI_CLK_CTL_DRS (0x1 << 12)  /* Divide rate select,default,0:rate 1;1:rate 2 */
+/* SPI Clock Control Register Bit Fields & Masks,default:0x0000_0002 */
+#define SPI_CLK_CTL_CDR2_MASK \
+    0xff /* Clock Divide Rate 2,master mode only : SPI_CLK = AHB_CLK/(2*(n+1)) */
+#define SPI_CLK_CTL_CDR2(div) (((div) &SPI_CLK_CTL_CDR2_MASK) << 0)
+#define SPI_CLK_CTL_CDR1_MASK \
+    0xf /* Clock Divide Rate 1,master mode only : SPI_CLK = AHB_CLK/2^n */
+#define SPI_CLK_CTL_CDR1(div) (((div) &SPI_CLK_CTL_CDR1_MASK) << 8)
+#define SPI_CLK_CTL_DRS \
+    (0x1 << 12) /* Divide rate select,default,0:rate 1;1:rate 2 */
 #define SPI_CLK_SCOPE (SPI_CLK_CTL_CDR2 + 1)
 
 /* SPI Master Burst Counter Register Bit Fields & Masks,default:0x0000_0000 */
@@ -102,6 +111,7 @@
 /* SPI Master Burst Control Counter reigster Bit Fields & Masks,default:0x0000_0000 */
 #define SPI_BCC_STC_MASK (0xFFFFFF << 0) /* master single mode transmit counter */
 #define SPI_BCC_DBC_MASK (0xF << 24)     /* master dummy burst counter */
+#define SPI_BCC_DBC_POS  (24)            /* master dummy burst pos */
 #define SPI_BCC_DUAL_MODE (0x1 << 28)    /* master dual mode RX enable */
 #define SPI_BCC_QUAD_MODE (0x1 << 29)    /* master quad mode RX enable */
 

diff --git a/include/drivers/sys-dma.h b/include/drivers/sys-dma.h
@@ -233,7 +233,7 @@ int sunxi_dma_free_int(uint32_t dma_fd);
  * @param dst_addr Pointer to the destination address.
  * @return 0 if successful, or an error code if failed.
  */
-int sunxi_dma_test(uint32_t *src_addr, uint32_t *dst_addr);
+int sunxi_dma_test(uint32_t *src_addr, uint32_t *dst_addr, uint32_t len);
 
 #ifdef __cplusplus
 }

diff --git a/include/drivers/sys-spi-nand.h b/include/drivers/sys-spi-nand.h
@@ -55,7 +55,7 @@ int spi_nand_detect(sunxi_spi_t *spi);
  * @param rxlen Number of bytes to read.
  * @return Number of bytes read on success, -1 on failure.
  */
-uint32_t spi_nand_read(sunxi_spi_t *spi, uint8_t *buf, uint32_t addr,uint32_t rxlen);
+uint32_t spi_nand_read(sunxi_spi_t *spi, uint8_t *buf, uint32_t addr, uint32_t rxlen);
 
 #ifdef __cplusplus
 }

diff --git a/include/drivers/sys-spi-nor.h b/include/drivers/sys-spi-nor.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif// __cplusplus
 
-const int SFDP_MAX_NPH(6);
+#define SFDP_MAX_NPH (6)
 
 typedef struct sfdp_header {
     uint8_t sign[4];
@@ -46,9 +46,9 @@ typedef struct sfdp_basic_table {
 } sfdp_basic_table_t;
 
 typedef struct sfdp {
-    sfdp_header_t header{};
-    sfdp_parameter_header_t parameter_header[SFDP_MAX_NPH]{};
-    sfdp_basic_table_t basic_table{};
+    sfdp_header_t header;
+    sfdp_parameter_header_t parameter_header[SFDP_MAX_NPH];
+    sfdp_basic_table_t basic_table;
 } sfdp_t;
 
 typedef struct spi_nor_info {
@@ -68,13 +68,6 @@ typedef struct spi_nor_info {
     uint8_t opcode_erase_256k;
 } spi_nor_info_t;
 
-typedef struct spi_nor_pdata {
-    spi_nor_info_t info;
-    uint32_t swap_buf{};
-    uint32_t swap_len{};
-    uint32_t cmd_len{};
-} spi_nor_pdata_t;
-
 enum SPI_NOR_OPS {
     NOR_OPCODE_SFDP = 0x5a,
     NOR_OPCODE_RDID = 0x9f,
@@ -90,6 +83,20 @@ enum SPI_NOR_OPS {
     NOR_OPCODE_EXIT_4B = 0xe9,
 };
 
+enum SPI_CMD_OPS {
+    SPI_CMD_END = 0x00,
+    SPI_CMD_INIT = 0x01,
+    SPI_CMD_SELECT = 0x02,
+    SPI_CMD_DESELECT = 0x03,
+    SPI_CMD_FAST = 0x04,
+    SPI_CMD_TXBUF = 0x05,
+    SPI_CMD_RXBUF = 0x06,
+    SPI_CMD_SPINOR_WAIT = 0x07,
+    SPI_CMD_SPINAND_WAIT = 0x08,
+};
+
+int spi_nor_detect(sunxi_spi_t *spi);
+
 #ifdef __cplusplus
 }
 #endif// __cplusplus

diff --git a/include/drivers/sys-spi.h b/include/drivers/sys-spi.h
@@ -38,15 +38,25 @@ typedef struct {
     gpio_mux_t gpio_hold;
 } sunxi_spi_gpio_t;
 
+typedef struct {
+    uint32_t spi_clock_cfg_base;
+    uint32_t spi_clock_source;
+    uint32_t spi_clock_factor_n_offset;
+    uint32_t spi_clock_freq;
+} sunxi_spi_clk_t;
+
 typedef struct {
     uint32_t base;
     uint8_t id;
     uint32_t clk_rate;
-    sunxi_clk_t clk_reg;
     sunxi_spi_gpio_t gpio;
     sunxi_dma_t *dma_handle;
+    sunxi_clk_t parent_clk_reg;
+    sunxi_spi_clk_t spi_clk;
 } sunxi_spi_t;
 
+#define MAX_FIFU (64)
+
 /**
  * Initialize the Sunxi SPI controller with the specified configuration.
  *

diff --git a/src/drivers/sys-dma.c b/src/drivers/sys-dma.c
@@ -313,8 +313,7 @@ int sunxi_dma_free_int(uint32_t dma_fd) {
 }
 
 
-int sunxi_dma_test(uint32_t *src_addr, uint32_t *dst_addr) {
-    uint32_t len = 1024 * 1024 * 8;
+int sunxi_dma_test(uint32_t *src_addr, uint32_t *dst_addr, uint32_t len) {
     sunxi_dma_set_t dma_set;
     uint32_t st = 0;
     uint32_t timeout;

diff --git a/src/drivers/sys-gpio.c b/src/drivers/sys-gpio.c
@@ -191,7 +191,7 @@ void sunxi_gpio_set_pull(gpio_t pin, enum gpio_pull_t pull) {
     write32(addr, val);
 
     printk_trace("GPIO: PULL pin = %d, addr = 0x%08x, val = 0x%08x, set pull = %d\n",
-                 pin_num, addr, read32(addr), v);
+                 pin, addr, read32(addr), v);
 }
 
 /**
@@ -215,5 +215,5 @@ void sunxi_gpio_set_drv(gpio_t pin, gpio_drv_t drv) {
     write32(addr, val);
 
     printk_trace("GPIO: DRV pin = %d, addr = 0x%08x, val = 0x%08x, set drv = %d\n",
-                 pin_num, addr, read32(addr), drv);
+                 pin, addr, read32(addr), drv);
 }
diff --git a/src/drivers/sys-i2c.c b/src/drivers/sys-i2c.c
@@ -497,11 +497,7 @@ static void sunxi_i2c_set_clock(sunxi_i2c_t *i2c_dev) {
     uint32_t clk_m = 0, clk_n = 0, _2_pow_clk_n = 1, duty = 0, src_clk = 0;
     uint32_t divider, sclk_real; /* the real clock frequency */
 
-    if (i2c_dev->i2c_clk.parent_clk > 40000000) {
-        src_clk = i2c_dev->i2c_clk.parent_clk;
-    } else {
-        src_clk = i2c_dev->i2c_clk.parent_clk / 10;
-    }
+    src_clk = i2c_dev->i2c_clk.parent_clk / 10;
 
     divider = src_clk / i2c_dev->speed; /* 400kHz or 100kHz */
     sclk_real = 0;                      /* the real clock frequency */
@@ -541,6 +537,8 @@ static void sunxi_i2c_set_clock(sunxi_i2c_t *i2c_dev) {
         duty = TWI_CLK_DUTY;
         i2c->clk &= ~(duty);
     }
+
+    printk_info("twi->clk %x\r\n", i2c->clk);
 }
 
 /**