Quartus

Quartus can be somewhat tempermental, and I would recommend using it only for building projects and the tooling it provides; use some external editor like Visual Studio Code.

Common Problems

Megafunction versioning

If you are using a newer version of Quartus (latest is v21.1), you may run into problems with various Megafunctions (particularly the PLL) when you try to open it to edit:

Megafunction PLL Intel FPGA IP v21.1 is not listed in any 
wizard.lst file in the specified library path(s).Wizard launch aborted

To fix this, you can edit the wizard.lst to include the version of Quartus you are using. For me, this file is at C:\intelFPGA_lite\21.1\ip\altera\altera_pll\pll_wizard.lst.

Verilog Failures

By default Quartus will allow several questionable practices with only a warning when building Verilog or SystemVerilog files. It will let through variable names (nets) that have not been defined, even though this almost definitely is a bug you want to be told about.

The Pro version of Quartus has the ability to convert these warnings into errors (see here) but it seems this functionality is not available for the free version.

TODO: See if there is any solution to this besides external linting

SignalTap

SignalTap is the on device debugging tool provided as a part of Quartus. Using an Intel-approved USB blaster (you can buy one from DigiKey), you can inspect the value of nets at certain times in operation, triggered from a configurable state change.

Driver Installation

The Terasic/Altera USB Blaster recommended requires driver installation

• Manual
• Windows
• Linux

Basic Learning

Learn more about SignalTap

Useful Tips

• You can create multiple "instances" of the SignalTap debugger component. This lets you save multiple sets of nets to switch between as your debugging requirements change
• Changing which nets you trigger on (but not whether you AND or OR the triggers) can be done without recompiling, saving you minutes (or hours). There is a lock mode setting at the top of the trigger selection. This doesn't prevent all changes that requires compilation, but it does prevent some
• The Pocket has two settings under Tools/Developer that are helpful when debugging using SignalTap
  • Pause Core Boot - Halts the core boot process until you press a button. This allows you to set up SignalTap to trigger on something early in the boot cycle
  • Pause Data Load - Halts the loading of data slots until you press a button. Same as above

TimeQuest Timing Analysis

Allows you to inspect timing reports and generate additional ones.

Design doesn't pass timing

If your design doesn't pass timing, you can use Timing Analysis to show possible solutions to your timing issue. This can be found at the bottom of the list, under Macros/Report Timing Closure Recommendations. If you look at the main page of Quartus where it shows the "Compilation Report", you should be able to expand the timing analysis section and click on individual nets that are red (didn't meet timing). That should fill in the dialog in TimeQuest, allowing you to see the recommendations.

Clock doesn't pass timing

Make sure any clocks you have are present in the core_constraints.sdc, which Quartus uses to properly manage timing across your project. Clocks that represent the same clock domain must be within the same group, and asynchronous clocks must be in separate groups. See Clocks for more information.

set_clock_groups -asynchronous \
 -group { bridge_spiclk } \
 -group { clk_74a } \
 -group { clk_74b } \
 -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \
 -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \
 -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \
 -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk }