chore: Release 0.3.0

* feat: Support SGX via extensions * Updated version number * Fixed error when no save is found * Updated README and info.txt
agg23 · Nov 8, 2022 · 196b62d · 196b62d
1 parent 16a8e7e
commit 196b62d
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diff --git a/.gitignore b/.gitignore
@@ -1,6 +1,8 @@
 *.rbf_r
 *.rev
 *.zip
+dist/**/chip32.bin
+src/support/*.bin
 src/sim/work/
 src/sim/*.hex
 src/sim/*.mem

diff --git a/README.md b/README.md
@@ -19,7 +19,9 @@ To install the core, copy the `Assets`, `Cores`, and `Platform` folders over to
 
 ROMs should be placed in `/Assets/pce/common`
 
-Please note that SuperGrafx and CD games are not currently supported, due to needing fixes/feature support in the firmware. They will be added in a future update.
+SuperGrafix games **_MUST_** have the `.sgx` extension, as otherwise there's no way for the core to tell that it uses the SuperGrafx hardware.
+
+Please note that CD games are not currently supported. Support will be added in a future update.
 
 ## Features
 

diff --git a/dist/Cores/agg23.PC Engine/core.json b/dist/Cores/agg23.PC Engine/core.json
@@ -7,8 +7,8 @@
       "description": "PC Engine (known as TurboGrafx-16 in the US) by NEC",
       "author": "agg23",
       "url": "https://github.com/agg23/openfpga-pcengine/",
-      "version": "0.2.1",
-      "date_release": "2022-10-27"
+      "version": "0.3.0",
+      "date_release": "2022-11-08"
     },
     "framework": {
       "target_product": "Analogue Pocket",
@@ -21,7 +21,8 @@
       "hardware": {
         "link_port": false,
         "cartridge_adapter": -1
-      }
+      },
+      "chip32_vm": "chip32.bin"
     },
     "cores": [
       {

diff --git a/dist/Cores/agg23.PC Engine/data.json b/dist/Cores/agg23.PC Engine/data.json
@@ -7,12 +7,12 @@
         "id": 0,
         "required": true,
         "parameters": "0x109",
-        "extensions": ["pce"],
+        "extensions": ["pce", "sgx"],
         "address": "0x10000000"
       },
       {
         "name": "Save",
-        "id": 10,
+        "id": 1,
         "required": false,
         "parameters": "0x84",
         "nonvolatile": true,

diff --git a/dist/Cores/agg23.PC Engine/info.txt b/dist/Cores/agg23.PC Engine/info.txt
@@ -2,4 +2,4 @@ Port by agg23. Core by Gregory Estrade, srg320, and greyrogue
 
 PC Engine (PCE), known as TurboGrafx-16 in the United States, was created by NEC and was the first 4th generation console to reach the market. Therefore, even though it came out in the late 80s, it has significantly better graphics than 8-bit systems that were being sold at the time, such as the NES.
 
-Currently supports standard PC Engine/TurboGrafx ROMs only. SuperGrafx support coming soon, and CD support coming sometime in the future. Please report all issues to agg23, as most likely any issues experienced are issues with the port, not the core.
+Currently supports standard PC Engine/TurboGrafx and SuperGrafx ROMs. CD support is coming sometime in the future. Please report all issues to agg23, as most likely any issues experienced are issues with the port, not the core.
diff --git a/src/fpga/ap_core.qsf b/src/fpga/ap_core.qsf
@@ -774,5 +774,5 @@ set_global_assignment -name SDC_FILE core/core_constraints.sdc
 set_global_assignment -name SIGNALTAP_FILE core/stp1.stp
 set_global_assignment -name QIP_FILE core/mf_pllbase.qip
 set_global_assignment -name SIP_FILE core/mf_pllbase.sip
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
+set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/src/fpga/apf/build_id.mif b/src/fpga/apf/build_id.mif
@@ -9,8 +9,8 @@ DATA_RADIX = HEX;
 CONTENT
 BEGIN
 
-   0E0 : 20221026;
-   0E1 : 00133551;
-   0E2 : aadd71c0;
+   0E0 : 20221108;
+   0E1 : 00123037;
+   0E2 : e03d8a7e;
 
 END;
diff --git a/src/fpga/core/core_top.v b/src/fpga/core/core_top.v
@@ -330,10 +330,13 @@ module core_top (
 
     if (bridge_wr) begin
       casex (bridge_addr)
-        // 32'h0: begin
-        //   ioctl_download <= bridge_wr_data[0];
-        // end
+        32'h0: begin
+          ioctl_download <= bridge_wr_data[0];
+        end
         32'h4: begin
+          save_download <= bridge_wr_data[0];
+        end
+        32'h8: begin
           is_sgx <= bridge_wr_data[0];
         end
         32'h50: begin
@@ -484,15 +487,16 @@ module core_top (
   );
 
   reg ioctl_download = 0;
+  reg save_download = 0;
   reg is_sgx = 0;
   wire ioctl_wr;
   wire [23:0] ioctl_addr;
   wire [15:0] ioctl_dout;
 
-  always @(posedge clk_74a) begin
-    if (dataslot_requestwrite) ioctl_download <= 1;
-    else if (dataslot_allcomplete) ioctl_download <= 0;
-  end
+  // always @(posedge clk_74a) begin
+  //   if (dataslot_requestwrite) ioctl_download <= 1;
+  //   else if (dataslot_allcomplete) ioctl_download <= 0;
+  // end
 
   wire [31:0] sd_read_data;
 
@@ -505,17 +509,17 @@ module core_top (
   wire [24:0] sd_buff_addr_in;
   wire [24:0] sd_buff_addr_out;
 
-  wire save_loading = dataslot_requestwrite_id == 1 || dataslot_requestread_id == 1;
+  // wire save_loading = dataslot_requestwrite_id == 1 || dataslot_requestread_id == 1;
 
   wire ioctl_download_s;
-  wire save_loading_s;
+  wire save_download_s;
   wire is_sgx_s;
 
   synch_3 #(
       .WIDTH(3)
   ) download_s (
-      {ioctl_download, save_loading, is_sgx},
-      {ioctl_download_s, save_loading_s, is_sgx_s},
+      {ioctl_download, save_download, is_sgx},
+      {ioctl_download_s, save_download_s, is_sgx_s},
       clk_mem_85_91
   );
 
@@ -795,7 +799,7 @@ module core_top (
       .sd_lba(sd_buff_addr[24:9]),
       .sd_buff_dout(sd_buff_dout),
       .sd_buff_din(sd_buff_din),
-      .save_loading(save_loading_s),
+      .save_download(save_download_s),
 
       // SDRAM
       .dram_a(dram_a),

diff --git a/src/fpga/core/main.sv b/src/fpga/core/main.sv
@@ -88,7 +88,7 @@ module pce (
     input wire [16:0] sd_lba,
     input wire [15:0] sd_buff_dout,
     output wire [15:0] sd_buff_din,
-    input wire save_loading,
+    input wire save_download,
 
     // SDRAM
     output wire [12:0] dram_a,
@@ -119,7 +119,7 @@ module pce (
     output wire [15:0] audio_r
 );
 
-  wire                                      [63:0] status = 0;
+  wire                                       [63:0] status = 0;
 
   wire code_download = 0;
 
@@ -132,10 +132,10 @@ module pce (
 
   wire VDC_BG_EN = 1;
   wire VDC_SPR_EN = 1;
-  wire                                      [ 1:0] VDC_GRID_EN = 2'd0;
+  wire                                       [ 1:0] VDC_GRID_EN = 2'd0;
   wire CPU_PAUSE_EN = 0;
 
-  wire reset = (core_reset | save_loading);
+  wire reset = (core_reset | save_download);
 
   // wire code_index      = &ioctl_index;
   // wire code_download   = ioctl_download & code_index;
@@ -144,17 +144,17 @@ module pce (
 
   wire overscan = ~status[17];
 
-  wire                                      [95:0]                     cd_comm;
-  wire                                                                 cd_comm_send;
-  reg                                       [15:0]                     cd_stat;
-  reg                                                                  cd_stat_rec;
-  reg                                                                  cd_dataout_req;
-  wire                                      [79:0]                     cd_dataout;
-  wire                                                                 cd_dataout_send;
-  wire                                                                 cd_reset_req;
-  reg                                                                  cd_region;
-
-  wire                                      [21:0]                     cd_ram_a;
+  wire                                       [95:0]                     cd_comm;
+  wire                                                                  cd_comm_send;
+  reg                                        [15:0]                     cd_stat;
+  reg                                                                   cd_stat_rec;
+  reg                                                                   cd_dataout_req;
+  wire                                       [79:0]                     cd_dataout;
+  wire                                                                  cd_dataout_send;
+  wire                                                                  cd_reset_req;
+  reg                                                                   cd_region;
+
+  wire                                       [21:0]                     cd_ram_a;
   wire cd_ram_rd, cd_ram_wr;
   wire [7:0] cd_ram_do;
 
@@ -433,7 +433,7 @@ module pce (
 
   ////////////////////////////  MEMORY  //////////////////////////////////
 
-  localparam LITE = 1;
+  localparam LITE = 0;
 
   wire [21:0] rom_rdaddr;
   wire [ 7:0] rom_sdata;
Original file line number	Diff line number	Diff line change
Expand Up		@@ -2,4 +2,4 @@ Port by agg23. Core by Gregory Estrade, srg320, and greyrogue

		PC Engine (PCE), known as TurboGrafx-16 in the United States, was created by NEC and was the first 4th generation console to reach the market. Therefore, even though it came out in the late 80s, it has significantly better graphics than 8-bit systems that were being sold at the time, such as the NES.

		Currently supports standard PC Engine/TurboGrafx ROMs only. SuperGrafx support coming soon, and CD support coming sometime in the future. Please report all issues to agg23, as most likely any issues experienced are issues with the port, not the core.
		Currently supports standard PC Engine/TurboGrafx and SuperGrafx ROMs. CD support is coming sometime in the future. Please report all issues to agg23, as most likely any issues experienced are issues with the port, not the core.