port/wch: Add support for board yd-ch32v307vct6 from VCCGND

ports/wch/Makefile

@@ -21,6 +21,7 @@ CROSS_COMPILE ?= $(TOOLCHAIN_ROOT)riscv-none-embed-
 
 # Project specific
 BOARD ?= CH32V307EVT
+#BOARD ?= YD-CH32V307VCT6
 TARGET = $(BOARD).elf
 
 SRC_DIR = bsp/src/
@@ -80,6 +81,8 @@ OBJ += $(addprefix $(BUILD)/, $(SRC_S:.S=.o))
 
 MAKE_PINS = boards/make-pins.py
 BOARD_PINS = boards/ch32v307_evt_pins.csv
+#BOARD_PINS  = boards/yd-ch32v307vct6.csv
+
 AF_FILE = boards/ch32v30x_af.csv
 PREFIX_FILE = boards/prefix.c
 

ports/wch/boards/make-pins.py

@@ -2,7 +2,7 @@
 
 """
 Generates pin source files based on an MCU alternate-function definition (eg
-stm32f405_af.csv) and a board-specific pin definition file, pins.csv.
+ch32v30x_af.csv) and a board-specific pin definition file, pins.csv.
 
 The pins.csv file can contain empty lines, comments (a line beginning with "#")
 or pin definition lines.  Pin definition lines must be of the form:

ports/wch/boards/yd-ch32v307vct6.csv

@@ -0,0 +1,92 @@
+PE2,PE2
+PE3,PE3
+PE4,PE4
+PE5,PE5
+PE6,PE6
+PC13,PC13
+PC14,PC14
+PC15,PC15
+PD0,PD0
+PD1,PD1
+PC0,PC0
+PC1,PC1
+PC2,PC2
+PC3,PC3
+PA0,PA0
+PA1,PA1
+PA2,PA2
+PA3,PA3
+PA4,PA4
+PA5,PA5
+PA6,PA6
+PA7,PA7
+PC4,PC4
+PC5,PC5
+PB0,PB0
+PB1,PB1
+PB2,PB2
+PE7,PE7
+PE8,PE8
+PE9,PE9
+PE10,PE10
+PE11,PE11
+PE12,PE12
+PE13,PE13
+PE14,PE14
+PE15,PE15
+PB10,PB10
+PB11,PB11
+PB12,PB12
+PB13,PB13
+PB14,PB14
+PB15,PB15
+PD8,PD8
+PD9,PD9
+PD10,PD10
+PD11,PD11
+PD12,PD12
+PD13,PD13
+PD14,PD14
+PD15,PD15
+PC6,PC6
+PC7,PC7
+PC8,PC8
+PC9,PC9
+PA8,PA8
+PA9,PA9
+PA10,PA10
+PA11,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+LED1,PA15
+PC10,PC10
+PC11,PC11
+PC12,PC12
+PD0,PD0
+PD1,PD1
+PD2,PD2
+PD3,PD3
+PD4,PD4
+PD5,PD5
+PD6,PD6
+PD7,PD7
+PB3,PB3
+LED2,PB4
+PB5,PB5
+PB6,PB6
+PB7,PB7
+PB8,PB8
+PB9,PB9
+PE0,PE0
+PE1,PE1
+USBHS_DP,PB7
+USBHS_DM,PB6
+USBFS_DP,PA12
+USBFS_DM,PA11
+ETH_TXP,PC8
+ETH_TXN,PC9
+ETH_RXP,PC6
+ETH_RXN,PC7
+SWDIO,PA13
+SWCLK,PA14