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cpu: fix pc counter
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@choffmann
choffmann committed May 13, 2024
1 parent 105a7cc commit faa3e14
Showing 1 changed file with 54 additions and 39 deletions.
93 changes: 54 additions & 39 deletions gameboy-lib/src/cpu/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,11 @@ impl Cpu {
opcode
};

println!("[CPU] Next instruction 0x{:x}", instruction);
if !prefixed {
println!("[CPU] PC: 0x{:x} Opcode: 0x{:x}", self.pc, opcode);
} else {
println!("[CPU] PC: 0x{:x} Prefixed: 0x{:x}", self.pc, instruction);
}

let next_pc = match Instruction::from_byte(instruction, prefixed) {
Some(instruction) => self.execute(instruction, prefixed),
Expand Down Expand Up @@ -70,11 +74,11 @@ impl Cpu {
}

fn and(&mut self, instruction: Instruction) -> u16 {
let value = match instruction {
let (value, pc) = match instruction {
Instruction::And(from) => match &from {
Register::D8 => self.memory.read(self.pc + 1),
Register::HL => self.memory.read(self.registers.get_16(&Register::HL)),
_ => self.registers.get(&from),
Register::D8 => (self.memory.read(self.pc + 1), self.pc.wrapping_add(2)),
Register::HL => (self.memory.read(self.registers.get_16(&Register::HL)), self.pc.wrapping_add(1)),
_ => (self.registers.get(&from), self.pc.wrapping_add(1)),
},
_ => panic!("[CPU] Invalid instruction {:?}", instruction),
};
Expand All @@ -88,15 +92,15 @@ impl Cpu {
self.registers.f.carry = false;
self.registers.set(&Register::A, result);

self.pc.wrapping_add(2)
pc
}

fn or(&mut self, instruction: Instruction) -> u16 {
let value = match instruction {
let (value, pc) = match instruction {
Instruction::Or(from) => match &from {
Register::D8 => self.memory.read(self.pc + 1),
Register::HL => self.memory.read(self.registers.get_16(&Register::HL)),
_ => self.registers.get(&from),
Register::D8 => (self.memory.read(self.pc + 1), self.pc.wrapping_add(2)),
Register::HL => (self.memory.read(self.registers.get_16(&Register::HL)), self.pc.wrapping_add(1)),
_ => (self.registers.get(&from), self.pc.wrapping_add(1)),
},
_ => panic!("[CPU] Invalid instruction {:?}", instruction),
};
Expand All @@ -110,15 +114,15 @@ impl Cpu {
self.registers.f.carry = false;
self.registers.set(&Register::A, result);

self.pc.wrapping_add(2)
pc
}

fn xor(&mut self, instruction: Instruction) -> u16 {
let value = match instruction {
let (value, pc) = match instruction {
Instruction::Xor(from) => match &from {
Register::D8 => self.memory.read(self.pc + 1),
Register::HL => self.memory.read(self.registers.get_16(&Register::HL)),
_ => self.registers.get(&from),
Register::D8 => (self.memory.read(self.pc + 1), self.pc.wrapping_add(2)),
Register::HL => (self.memory.read(self.registers.get_16(&Register::HL)), self.pc.wrapping_add(1)),
_ => (self.registers.get(&from), self.pc.wrapping_add(1)),
},
_ => panic!("[CPU] Invalid instruction {:?}", instruction),
};
Expand All @@ -132,15 +136,15 @@ impl Cpu {
self.registers.f.carry = false;
self.registers.set(&Register::A, result);

self.pc.wrapping_add(2)
pc
}

fn compare(&mut self, instruction: Instruction) -> u16 {
let value = match instruction {
let (value, pc) = match instruction {
Instruction::Cp(from) => match &from {
Register::D8 => self.memory.read(self.pc + 1),
Register::HL => self.memory.read(self.registers.get_16(&Register::HL)),
_ => self.registers.get(&from),
Register::D8 => (self.memory.read(self.pc + 1), self.pc.wrapping_add(2)),
Register::HL => (self.memory.read(self.registers.get_16(&Register::HL)), self.pc.wrapping_add(1)),
_ => (self.registers.get(&from), self.pc.wrapping_add(1)),
},
_ => panic!("[CPU] Invalid instruction {:?}", instruction),
};
Expand All @@ -153,7 +157,7 @@ impl Cpu {
self.registers.f.half_carry = (a & 0xF) < (value & 0xF);
self.registers.f.carry = a < value;

self.pc.wrapping_add(2)
pc
}

fn inc(&mut self, register: Register) -> u16 {
Expand Down Expand Up @@ -189,21 +193,26 @@ impl Cpu {
}

fn add(&mut self, instruction: Instruction) -> u16 {
let value = match instruction {
let (value, pc) = match instruction {
Instruction::Add(from) => match &from {
Register::D8 => self.memory.read(self.pc + 1),
Register::HL => self.memory.read(self.registers.get_16(&Register::HL)),
_ => self.registers.get(&from),
Register::D8 => (self.memory.read(self.pc + 1), self.pc.wrapping_add(2)),
Register::HL => (self.memory.read(self.registers.get_16(&Register::HL)), self.pc.wrapping_add(1)),
_ => (self.registers.get(&from), self.pc.wrapping_add(1)),
},
Instruction::Adc(from) => match &from {
Register::D8 => {
self.memory.read(self.pc + 1) + if self.registers.f.carry { 1 } else { 0 }
let value = self.memory.read(self.pc + 1) + if self.registers.f.carry { 1 } else { 0 };
(value, self.pc.wrapping_add(2))
}
Register::HL => {
self.memory.read(self.registers.get_16(&Register::HL))
+ if self.registers.f.carry { 1 } else { 0 }
let value = self.memory.read(self.registers.get_16(&Register::HL))
+ if self.registers.f.carry { 1 } else { 0 };
(value, self.pc.wrapping_add(1))
}
_ => {
let value = self.registers.get(&from) + if self.registers.f.carry { 1 } else { 0 };
(value, self.pc.wrapping_add(1))
}
_ => self.registers.get(&from) + if self.registers.f.carry { 1 } else { 0 },
},
_ => panic!("[CPU] Invalid instruction {:?}", instruction),
};
Expand All @@ -216,25 +225,31 @@ impl Cpu {
self.registers.f.half_carry = (((a & 0xF) + (value & 0xF)) & 0x10) == 0x10;
self.registers.f.carry = did_overflow;
self.registers.set(&Register::A, result);
self.pc.wrapping_add(1)

pc
}

fn sub(&mut self, instruction: Instruction) -> u16 {
let value = match instruction {
let (value, pc) = match instruction {
Instruction::Sub(from) => match &from {
Register::D8 => self.memory.read(self.pc + 1),
Register::HL => self.memory.read(self.registers.get_16(&Register::HL)),
_ => self.registers.get(&from),
Register::D8 => (self.memory.read(self.pc + 1), self.pc.wrapping_add(2)),
Register::HL => (self.memory.read(self.registers.get_16(&Register::HL)), self.pc.wrapping_add(1)),
_ => (self.registers.get(&from), self.pc.wrapping_add(1)),
},
Instruction::Sbc(from) => match &from {
Register::D8 => {
self.memory.read(self.pc + 1) + if self.registers.f.carry { 1 } else { 0 }
let value = self.memory.read(self.pc + 1) + if self.registers.f.carry { 1 } else { 0 };
(value, self.pc.wrapping_add(2))
}
Register::HL => {
self.memory.read(self.registers.get_16(&Register::HL))
+ if self.registers.f.carry { 1 } else { 0 }
let value = self.memory.read(self.registers.get_16(&Register::HL))
+ if self.registers.f.carry { 1 } else { 0 };
(value, self.pc.wrapping_add(1))
}
_ => {
let value = self.registers.get(&from) + if self.registers.f.carry { 1 } else { 0 };
(value, self.pc.wrapping_add(1))
}
_ => self.registers.get(&from) + if self.registers.f.carry { 1 } else { 0 },
},
_ => panic!("[CPU] Invalid instruction {:?}", instruction),
};
Expand All @@ -248,7 +263,7 @@ impl Cpu {
self.registers.f.carry = did_overflow;
self.registers.set(&Register::A, result);

self.pc.wrapping_add(1)
pc
}

fn push(&mut self, register: Register) -> u16 {
Expand Down

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