[Intel/EP] Query the QPI frequency from all available QPI_Link.

cyring · Jun 1, 2022 · c9cb78f · c9cb78f
1 parent cd4cdfb
commit c9cb78f
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Showing 5 changed files with 41 additions and 16 deletions.
diff --git a/corefreq-api.h b/corefreq-api.h
@@ -1118,8 +1118,9 @@ typedef struct
 /* Source: Intel Xeon Processor E5 & E7 v1 Datasheet Vol 2		*/
 /*	DMI2: Device=0 - Function=0					*/
 #define DID_INTEL_SNB_EP_HOST_BRIDGE	0x3c00
-/*	QPIMISCSTAT: Device=8 - Function=0				*/
+/*	QPIMISCSTAT: Device=8,9 - Function=0				*/
 #define DID_INTEL_SNB_EP_QPI_LINK0	0x3c80
+#define DID_INTEL_SNB_EP_QPI_LINK1	0x3c90
 /*	Integrated Memory Controller # : General and MemHot Registers	*/
 /*	Xeon E5 - CPGC: Device=15 - Function=0				*/
 #define DID_INTEL_SNB_EP_IMC_CTRL0_CPGC 0x3ca8
@@ -1156,8 +1157,10 @@ typedef struct
 /* Source: Intel Xeon Processor E5 & E7 v2 Datasheet Vol 2		*/
 /*	DMI2: Device=0 - Function=0					*/
 #define DID_INTEL_IVB_EP_HOST_BRIDGE	0x0e00
-/*	QPIMISCSTAT: Device=8 - Function=0				*/
+/*	QPIMISCSTAT: Device={8,9},10 - Function=0			*/
 #define DID_INTEL_IVB_EP_QPI_LINK0	0x0e80
+#define DID_INTEL_IVB_EP_QPI_LINK1	0x0e90
+#define DID_INTEL_IVB_EP_QPI_LINK2	0x0e40
 /*	Integrated Memory Controller # : General and MemHot Registers	*/
 /*	Xeon E5 - CPGC: Device=15 - Function=0				*/
 #define DID_INTEL_IVB_EP_IMC_CTRL0_CPGC 0x0ea8
@@ -1194,8 +1197,10 @@ typedef struct
 /* Source: Intel Xeon Processor E5 & E7 v3 Datasheet Vol 2		*/
 /*	DMI2: Device=0 - Function=0					*/
 #define DID_INTEL_HSW_EP_HOST_BRIDGE	0x2f00
-/*	QPIMISCSTAT: Device=8 - Function=0				*/
+/*	QPIMISCSTAT: Device={8,9},10 - Function=0			*/
 #define DID_INTEL_HSW_EP_QPI_LINK0	0x2f80
+#define DID_INTEL_HSW_EP_QPI_LINK1	0x2f90
+#define DID_INTEL_HSW_EP_QPI_LINK2	0x2f40
 /*	Integrated Memory Controller # : General and MemHot Registers	*/
 /*	Xeon E7 - CPGC: Device=19 - Function=0,1			*/
 #define DID_INTEL_HSW_E7_IMC_CTRL0_F0_CPGC 0x2fa8

diff --git a/corefreqd.c b/corefreqd.c
@@ -3694,10 +3694,10 @@ void SNB_EP_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 	RO(Shm)->Uncore.CtrlSpeed /= RO(Shm)->Proc.Features.Factory.Clock.Hz;
 
 	RO(Shm)->Uncore.Bus.Rate = \
-		RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b010 ?
-	5600 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b011 ?
-	6400 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b100 ?
-	7200 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b101 ?
+		RO(Proc)->Uncore.Bus.QuickPath.EP.QPIFREQSEL == 0b010 ?
+	5600 :	RO(Proc)->Uncore.Bus.QuickPath.EP.QPIFREQSEL == 0b011 ?
+	6400 :	RO(Proc)->Uncore.Bus.QuickPath.EP.QPIFREQSEL == 0b100 ?
+	7200 :	RO(Proc)->Uncore.Bus.QuickPath.EP.QPIFREQSEL == 0b101 ?
 	8000 : 5000;
 
 	RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
@@ -3987,11 +3987,11 @@ void HSW_EP_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 	RO(Shm)->Uncore.CtrlSpeed /= RO(Shm)->Proc.Features.Factory.Clock.Hz;
 
 	RO(Shm)->Uncore.Bus.Rate = \
-		RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b010 ?
-	5600 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b011 ?
-	6400 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b100 ?
-	7200 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b101 ?
-	8000 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b111 ?
+		RO(Proc)->Uncore.Bus.QuickPath.EP.QPIFREQSEL == 0b010 ?
+	5600 :	RO(Proc)->Uncore.Bus.QuickPath.EP.QPIFREQSEL == 0b011 ?
+	6400 :	RO(Proc)->Uncore.Bus.QuickPath.EP.QPIFREQSEL == 0b100 ?
+	7200 :	RO(Proc)->Uncore.Bus.QuickPath.EP.QPIFREQSEL == 0b101 ?
+	8000 :	RO(Proc)->Uncore.Bus.QuickPath.EP.QPIFREQSEL == 0b111 ?
 	9600 : 6400;
 
 	RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz

diff --git a/corefreqk.c b/corefreqk.c
@@ -5286,9 +5286,13 @@ static PCI_CALLBACK SNB_EP_TAD_CTRL1_CHA3(struct pci_dev *dev)
 
 static PCI_CALLBACK SNB_EP_QPI(struct pci_dev *dev)
 {
-	pci_read_config_dword(dev, 0xd4,
-				&PUBLIC(RO(Proc))->Uncore.Bus.QuickPath.value);
+	QPI_FREQUENCY QuickPath = {.value = 0};
+	pci_read_config_dword(dev, 0xd4, &QuickPath.value);
 
+	if ((PUBLIC(RO(Proc))->Uncore.Bus.QuickPath.EP.QPIFREQSEL == 0b000)
+	 && (QuickPath.EP.QPIFREQSEL != 0b000)) {
+		PUBLIC(RO(Proc))->Uncore.Bus.QuickPath = QuickPath;
+	}
 	return (PCI_CALLBACK) 0;
 }
 

diff --git a/corefreqk.h b/corefreqk.h
@@ -2274,10 +2274,22 @@ static struct pci_device_id PCI_SandyBridge_EP_ids[] = {
 		PCI_VDEVICE(INTEL, DID_INTEL_SNB_EP_QPI_LINK0),
 		.driver_data = (kernel_ulong_t) SNB_EP_QPI
 	},
+	{
+		PCI_VDEVICE(INTEL, DID_INTEL_SNB_EP_QPI_LINK1),
+		.driver_data = (kernel_ulong_t) SNB_EP_QPI
+	},
 	{
 		PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_QPI_LINK0),
 		.driver_data = (kernel_ulong_t) SNB_EP_QPI
 	},
+	{	/*	Bus: 1 Device: 9 Function: 0 (From B stepping)	*/
+		PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_QPI_LINK1),
+		.driver_data = (kernel_ulong_t) SNB_EP_QPI
+	},
+	{
+		PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_QPI_LINK2),
+		.driver_data = (kernel_ulong_t) SNB_EP_QPI
+	},
 /*	Power Control Unit						*/
 	{
 		PCI_VDEVICE(INTEL, DID_INTEL_SNB_EP_CAPABILITY),
@@ -2449,6 +2461,10 @@ static struct pci_device_id PCI_Haswell_ids[] = {
 		PCI_VDEVICE(INTEL, DID_INTEL_HSW_EP_QPI_LINK0),
 		.driver_data = (kernel_ulong_t) HSW_EP_QPI
 	},
+	{
+		PCI_VDEVICE(INTEL, DID_INTEL_HSW_EP_QPI_LINK2),
+		.driver_data = (kernel_ulong_t) HSW_EP_QPI
+	},
 /*	Power Control Unit						*/
 	{
 		PCI_VDEVICE(INTEL, DID_INTEL_HSW_EP_CAPABILITY),

diff --git a/intelmsr.h b/intelmsr.h
@@ -2704,13 +2704,13 @@ typedef union
 		ReservedBits	: 31-2,
 		VT_d		: 32-31; /* Placeholder for VT-d: 0=Enable */
 	} X58;
-	struct {	/* Xeon E7 v2 & Xeon E5 v2			*/
+	struct {	/* Xeon E7 v2 & Xeon E5 v1,v2,v3		*/
 		unsigned int
 		QPIFREQSEL	:  3-0,  /*010=5600,011=6400,100=7200,101=8000*/
 		ReservedBits1	:  4-3,
 		Slow_Mode	:  5-4,
 		ReservedBits2	: 32-5;
-	} IVB_EP; /* Defined in SNB_EP as QPIMISCSTAT. HSW_EP: 111=9600 */
+	} EP; /* Defined in SNB_EP as QPIMISCSTAT. HSW_EP: 111=9600 */
 } QPI_FREQUENCY;