.gitignore

#########
#Exclude all
#########
*
!*/
!.gitignore
!*.md

# Created by https://www.gitignore.io/api/xilinxvivado,alteraquartusii

### AlteraQuartusII ###
##list taken from http://www.alterawiki.com/wiki/Version_Control (01.10.2015)

######### Quartus II source files

# project files:
### project_name.qpf Quartus II project file
### project_name.qsf Quartus constraint file (lists the hardware constraints defined for a project, from the used chip and pinout to timing constraints)
### project_name.qws Quartus Window Settings ? (the configuration of the Quartus gui for the project, may be omitted)

# top level source files:
### project_name.bdf Block diagram / Schematic file (top level schematic file, there may be many nested files)
### project_name.vhd VHDL file (top level VHDL file)
### project_name.v Verilog file (top level Verilog file)

# component source files:
### component_name.bsf Block Symbol file (component symbol file)
### component_name.vhd VHDL file (top level VHDL file)
### component_name.v Verilog file (top level Verilog file)

# SOPC builder project source files (SOPC builder creates many VHDL or Verilog files, that you do not need to store)
### sopc_project_name.ptf the list and configuration of components selected in the SOPC gui
### sopc_project_name.bsf Block Symbol file (SOPC component symbol file, especially if you modified it)

# Board Description (if you created your own board, the list is incomplete!)
### board_name/class.ptf

# software source files:
### tbd

######## Quartus II binary files

# hardware binary files
### project_name.sof SRAM Object File

# software binary files
### tbd
!.elf
##
!*.qpf
!*.qsf
!*.qws
##
!*.bdf
!*.vhd
!*.v
##
!*.ptf
!*.bsf
##
!**/class.ptf
##
!*.tbd
##
!*.sof
##
## tbd

!*.tcl

### XilinxVivado ###
#########################################################################################################
##	This is an example .gitignore file for Vivado, please treat it as an example as 
##	it might not be complete. In addition, XAPP 1165 should be followed.
#########################################################################################################
###########################################################################
##	VIVADO
###########################################################################
#########
#Source files:
#########
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.bd
!*.edif
#########
#IP files
#########
#.xci: IP-core property file with core container disabled
!*.xci
#*.dcp (checkpoint files: better be ignored!)
#!*.dcp
!*.vds
!*.pb
#All bd comments and layout coordinates are stored within .ui
!*.ui
!*.ooc
#########
#System Generator
#########
!*.mdl
!*.slx
!*.bxml
#########
#Simulation logic analyzer
#########
!*.wcfg
!*.coe
#########
#MIG
#########
!*.prj
!*.mem
#########
#Project files
#########
#XPR  +  *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
#Do NOT ignore *.xpr files
!*.xpr
#Include *.xml files for 2013.4 or earlier version
*.xml
#########
#Constraint files
#########
#Do NOT ignore *.xdc files
!*.xdc
#########
#TCL - files
#########
!*.tcl
#########
#Journal - files
#########
!*.jou
#########
#Reports
#########
!*.rpt
!*.txt
!*.vdi
#########
#C-files
#########
!*.c
!*.h
!*.elf
!*.bmm
!*.xmp

# intermediate build files

*.bgn
*.bit
*.bld
*.cmd_log
*.drc
*.ll
*.lso
*.msd
*.msk
*.ncd
*.ngc
*.ngd
*.ngr
*.pad
*.par
*.pcf
*.prj
*.ptwx
*.rbb
*.rbd
*.stx
*.syr
*.twr
*.twx
*.unroutes
*.ut
*.xpi
*.xst
*_bitgen.xwbt
*_envsettings.html
*_map.map
*_map.mrp
*_map.ngm
*_map.xrpt
*_ngdbuild.xrpt
*_pad.csv
*_pad.txt
*_par.xrpt
*_summary.html
*_summary.xml
*_usage.xml
*_xst.xrpt
par_usage_statistics.html
usage_statistics_ext_xsim.xml
usage_statistics_webtalk.html
webtalk.log
webtalk_pn.xml
webtalk_pa.xml
**/webtalk/
**/wt/
**/webtalk_pa.xml