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Personal expectations

1138-4EB edited this page May 10, 2015 · 1 revision

@1138-4EB

My objective is to be able to make the documentation of VHDL projects as part of the creation process. This would not only make documenting more natural, but it would be very useful during the development, as a visual feedback of the sources. That is, I'd like to:

  • Write comments as I describe modules in VHDL.
  • Have (browsable) documentation and (interactive) structural/RTL diagrams generated in 'real-time'.
  • Be able to open the sources from either the documentation or the diagrams.
  • When any of the sources is edited, have the documentation and diagrams regenerated automagically.
  • Ideally
    • Waveforms:
      • Feature to select some signals and a time frame, and have an image generated (SVG and or bitmap) and embedded in the documentation.
    • State Machines
    • Edit either structural/RTL diagrams or state machines graphically and have the sources updated.

Some of these features are not new (see first text block of the first comment in tgingold/ghdl#111 or check commercial solutions such as Xilinx's, Mentor Graphics', Aldec's, Altera/Intel's or Sigasi's). However, I think there is no tool which satisfies all of them. The closest might be 'Sigasi Studio XL Doc' (I tried the evaluation version, which does not include all the features), but it is still missing the ideal part, and being libre.


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