riscv64: Use canonical move instruction (bytecodealliance#6959)

This seems to be a leftover of the AArch64 port
gurry · Sep 5, 2023 · 5f9107a · 5f9107a
1 parent 7b16ecc
commit 5f9107a
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Showing 141 changed files with 1,373 additions and 1,385 deletions.
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -994,7 +994,7 @@ impl MachInstEmit for Inst {
 
                 match rm.class() {
                     RegClass::Int => Inst::AluRRImm12 {
-                        alu_op: AluOPRRI::Ori,
+                        alu_op: AluOPRRI::Addi,
                         rd: rd,
                         rs: rm,
                         imm12: Imm12::zero(),
@@ -1027,13 +1027,8 @@ impl MachInstEmit for Inst {
             &Inst::MovFromPReg { rd, rm } => {
                 debug_assert!([px_reg(2), px_reg(8)].contains(&rm));
                 let rd = allocs.next_writable(rd);
-                let x = Inst::AluRRImm12 {
-                    alu_op: AluOPRRI::Ori,
-                    rd,
-                    rs: Reg::from(rm),
-                    imm12: Imm12::zero(),
-                };
-                x.emit(&[], sink, emit_info, state);
+
+                Inst::gen_move(rd, Reg::from(rm), I64).emit(&[], sink, emit_info, state);
             }
 
             &Inst::BrTable {

diff --git a/cranelift/filetests/filetests/isa/riscv64/amodes.clif b/cranelift/filetests/filetests/isa/riscv64/amodes.clif
@@ -410,12 +410,12 @@ block0(v0: i64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   ld t2, 0(a0)
-;   ori a2, t2, 0
+;   mv a2, t2
 ;   ld a1, 8(a0)
-;   ori a3, a2, 0
+;   mv a3, a2
 ;   sd a3, 0(a0)
 ;   sd a1, 8(a0)
-;   ori a0, a2, 0
+;   mv a0, a2
 ;   ret
 
 function %i128_imm_offset(i64) -> i128 {
@@ -439,12 +439,12 @@ block0(v0: i64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   ld t2, 0x10(a0)
-;   ori a2, t2, 0
+;   mv a2, t2
 ;   ld a1, 0x18(a0)
-;   ori a3, a2, 0
+;   mv a3, a2
 ;   sd a3, 0x10(a0)
 ;   sd a1, 0x18(a0)
-;   ori a0, a2, 0
+;   mv a0, a2
 ;   ret
 
 function %i128_imm_offset_large(i64) -> i128 {
@@ -468,12 +468,12 @@ block0(v0: i64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   ld t2, 0x1f8(a0)
-;   ori a2, t2, 0
+;   mv a2, t2
 ;   ld a1, 0x200(a0)
-;   ori a3, a2, 0
+;   mv a3, a2
 ;   sd a3, 0x1f8(a0)
 ;   sd a1, 0x200(a0)
-;   ori a0, a2, 0
+;   mv a0, a2
 ;   ret
 
 function %i128_imm_offset_negative_large(i64) -> i128 {
@@ -497,12 +497,12 @@ block0(v0: i64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   ld t2, -0x200(a0)
-;   ori a2, t2, 0
+;   mv a2, t2
 ;   ld a1, -0x1f8(a0)
-;   ori a3, a2, 0
+;   mv a3, a2
 ;   sd a3, -0x200(a0)
 ;   sd a1, -0x1f8(a0)
-;   ori a0, a2, 0
+;   mv a0, a2
 ;   ret
 
 function %i128_add_offset(i64) -> i128 {

diff --git a/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif b/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif
@@ -693,9 +693,9 @@ block0(v0: i128, v1: i128):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   sub a2, a0, a2
-;   ori a7, a2, 0
+;   mv a7, a2
 ;   sltu a4, a0, a7
-;   ori a0, a7, 0
+;   mv a0, a7
 ;   sub a6, a1, a3
 ;   sub a1, a6, a4
 ;   ret

diff --git a/cranelift/filetests/filetests/isa/riscv64/atomic-rmw.clif b/cranelift/filetests/filetests/isa/riscv64/atomic-rmw.clif
@@ -117,8 +117,8 @@ block0(v0: i64, v1: i64):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   ori a3, a0, 0
-;   ori a2, a1, 0
+;   mv a3, a0
+;   mv a2, a1
 ;   lr.d.aqrl a0, (a3)
 ;   and a1, a2, a0
 ;   not a1, a1
@@ -141,8 +141,8 @@ block0(v0: i64, v1: i32):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   ori a3, a0, 0
-;   ori a2, a1, 0
+;   mv a3, a0
+;   mv a2, a1
 ;   lr.w.aqrl a0, (a3)
 ;   and a1, a2, a0
 ;   not a1, a1